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Sample records for level fpga trigger

  1. An FPGA based Topological Processor prototype for the ATLAS Level-1 Trigger upgrade

    NASA Astrophysics Data System (ADS)

    Bauss, B.; Büscher, V.; Degele, R.; Ji, W.; Moritz, S.; Reiss, A.; Schäfer, U.; Simioni, E.; Tapprogge, S.; Wenzel, V.

    2012-12-01

    Starting in 2014, the LHC will collide bunches of protons at up to 14 TeV with an instantaneous luminosity increasing above the design value of 1 × 1034 cm-2s-1. Even though the resulting higher event rate will challenge the existing ATLAS data acquisition system, the trigger rate can be reduced by selecting channels based on their expected decay topology and thus reducing background. This will be achieved by introducing a new FPGA based module in the Level-1 Trigger: the Topological Processor (L1Topo). With L1Topo it will be possible to concentrate detailed information from the entire calorimeters and the muon detector into a single module. L1Topo will receive a total aggregate bandwidth of ≈ 1 Tb/s. High density optical I/O and state of the art FPGAs with embedded multi-Gb/s transceivers will be required. For a typical algorithm, the topology data will be processed in less than 100 ns. This paper focuses on the design of the first L1Topo prototype and results from a full-size, full-function demonstrator module. Implementation details of a topological algorithm and latency figures are presented.

  2. FPGA Trigger System to Run Klystrons

    SciTech Connect

    Gray, Darius; /Texas A-M /SLAC

    2010-08-25

    The Klystron Department is in need of a new trigger system to update the laboratory capabilities. The objective of the research is to develop the trigger system using Field Programmable Gate Array (FPGA) technology with a user interface that will allow one to communicate with the FPGA via a Universal Serial Bus (USB). This trigger system will be used for the testing of klystrons. The key materials used consists of the Xilinx Integrated Software Environment (ISE) Foundation, a Programmable Read Only Memory (Prom) XCF04S, a Xilinx Spartan 3E 35S500E FPGA, Xilinx Platform Cable USB II, a Printed Circuit Board (PCB), a 100 MHz oscillator, and an oscilloscope. Key considerations include eight triggers, two of which have variable phase shifting capabilities. Once the project was completed the output signals were able to be manipulated via a Graphical User Interface by varying the delay and width of the signal. This was as planned; however, the ability to vary the phase was not completed. Future work could consist of being able to vary the phase. This project will give the operators in the Klystron Department more flexibility to run various tests.

  3. FPGA-based Trigger System for the Fermilab SeaQuest Experimentz

    SciTech Connect

    Shiu, Shiuan-Hal; Wu, Jinyuan; McClellan, Randall Evan; Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu; Gilman, Ron; Nakano, Kenichi; Peng, Jen-Chieh; Wang, Su-Yin

    2015-09-10

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ+ and μ-produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system we used consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Finally, information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

  4. FPGA-based Trigger System for the Fermilab SeaQuest Experimentz

    DOE PAGES

    Shiu, Shiuan-Hal; Wu, Jinyuan; McClellan, Randall Evan; ...

    2015-09-10

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ+ and μ-produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system we used consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined againstmore » pre-determined trigger matrices to identify candidate muon tracks. Finally, information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.« less

  5. A possible level 0 trigger scheme for the STAR EMC

    SciTech Connect

    Underwood, D.

    1994-05-01

    We propose a level 0 trigger for the STAR Electromagnetic Calorimeter, EMC, which provides a global energy sum and sums over cells appropriate for triggering on direct gammas and jets. It is implemented in analog at low level and digitally with FPGA`s at higher level. It will provide trigger information in less than 800 nanoseconds.

  6. FPGA Based Wavelet Trigger in Radio Detection of Cosmic Rays

    NASA Astrophysics Data System (ADS)

    Szadkowski, Zbigniew; Szadkowska, Anna

    2014-12-01

    Experiments which show coherent radio emission from extensive air showers induced by ultra-high-energy cosmic rays are designed for a detailed study of the development of the electromagnetic part of air showers. Radio detectors can operate with 100 % up time as, e.g., surface detectors based on water-Cherenkov tanks. They are being developed for ground-based experiments (e.g., the Pierre Auger Observatory) as another type of air-shower detector in addition to fluorescence detectors, which operate with only ˜10 % of duty on dark nights. The radio signals from air showers are caused by coherent emission from geomagnetic radiation and charge-excess processes. The self-triggers in radio detectors currently in use often generate a dense stream of data, which is analyzed afterwards. Huge amounts of registered data require significant manpower for off-line analysis. Improvement of trigger efficiency is a relevant factor. The wavelet trigger, which investigates on-line the power of radio signals (˜ V2/ R), is promising; however, it requires some improvements with respect to current designs. In this work, Morlet wavelets with various scaling factors were used for an analysis of real data from the Auger Engineering Radio Array and for optimization of the utilization of the resources in an FPGA. The wavelet analysis showed that the power of events is concentrated mostly in a limited range of the frequency spectrum (consistent with a range imposed by the input analog band-pass filter). However, we found several events with suspicious spectral characteristics, where the signal power is spread over the full band-width sampled by a 200 MHz digitizer with significant contribution of very high and very low frequencies. These events may not originate from cosmic ray showers but could be the result of human contamination. The engine of the wavelet analysis can be implemented in the modern powerful FPGAs and can remove suspicious events on-line to reduce the trigger rate.

  7. The CMS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Trocino, Daniele

    2014-06-01

    The CMS experiment has been designed with a two-level trigger system: the Level-1 Trigger, implemented in custom-designed electronics, and the High-Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. A software trigger system requires a tradeoff between the complexity of the algorithms running with the available computing power, the sustainable output rate, and the selection efficiency. We present the performance of the main triggers used during the 2012 data taking, ranging from simple single-object selections to more complex algorithms combining different objects, and applying analysis-level reconstruction and selection. We discuss the optimisation of the trigger and the specific techniques to cope with the increasing LHC pile-up, reducing its impact on the physics performance.

  8. FPGA-based trigger system for the LUX dark matter experiment

    SciTech Connect

    Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D. -M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O׳Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

    2016-05-01

    LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be >99% efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

  9. FPGA-based trigger system for the LUX dark matter experiment

    NASA Astrophysics Data System (ADS)

    Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D.-M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O`Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

    2016-05-01

    LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be > 99 % efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

  10. The CMS Level-1 Trigger Barrel Track Finder

    NASA Astrophysics Data System (ADS)

    Ero, J.; Evangelou, I.; Flouris, G.; Foudas, C.; Guiducci, L.; Loukas, N.; Manthos, N.; Papadopoulos, I.; Paradas, E.; Sotiropoulos, S.; Sphicas, P.; Triossi, A.; Wulz, C.

    2016-03-01

    The design and performance of the upgraded CMS Level-1 Trigger Barrel Muon Track Finder (BMTF) is presented. Monte Carlo simulation data as well as cosmic ray data from a CMS muon detector slice test have been used to study in detail the performance of the new track finder. The design architecture is based on twelve MP7 cards each of which uses a Xilinx Virtex-7 FPGA and can receive and transmit data at 10 Gbps from 72 input and 72 output fibers. According to the CMS Trigger Upgrade TDR the BMTF receives trigger primitive data which are computed using both RPC and DT data and transmits data from a number of muon candidates to the upgraded Global Muon Trigger. Results from detailed studies of comparisons between the BMTF algorithm results and the results of a C++ emulator are also presented. The new BMTF will be commissioned for data taking in 2016.

  11. FPGA-Based Approach to Level-1 Track Finding at CMS for the HL-LHC

    NASA Astrophysics Data System (ADS)

    Skinnari, Louise

    2016-11-01

    The high luminosity upgrade of the LHC is expected to deliver luminosities of 7.5 × 1034 cm-2s-1, with an average of 140-200 overlapping proton-proton collisions in each bunch crossing at a frequency of 40 MHz. To maintain manageable trigger rates under these conditions track reconstruction will be incorporated in the all-hardware first level of the CMS trigger. A track-finding algorithm based on seed tracklets has been developed and implemented on commercially available FPGAs for this purpose. An overview of the algorithm is presented, results are shown of its expected performance from simulations, and an implementation of the algorithm in a Xilinx Virtex-7 FPGA for a hardware demonstrator system is discussed.

  12. 4th generation of the 1st level surface detector trigger in the Pierre Auger Observator

    NASA Astrophysics Data System (ADS)

    Szadkowski, Z.

    The proposal of a new 4th generation of the Front-End with the advanced 1st level triggers for the Infill Array of the Pierre Auger Observatory and for the Auger North is described. Newest FPGA chips offer much higher capacity of logic registers and memories, as well as DSP blocks. The calibration channel, previously supported by an external dual-port RAM, has been fully implemented into FPGA chip, through a large internal memory. In turn DSP blocks allowed on implementation of much more sophisticated spectral trigger algorithms. A single chip simplified board design, newer architecture of FPGA reduced resouces utilization and power consumption. Higher sampling in the new Front- End in comparison with previous 40 MHz designs as well as free resources for new detection algotithms can be a good platform for CR radio detection technique at Auger enhancing a duty cycle for the detection of UHECR’s.

  13. Using MaxCompiler for the high level synthesis of trigger algorithms

    NASA Astrophysics Data System (ADS)

    Summers, S.; Rose, A.; Sanders, P.

    2017-02-01

    Firmware for FPGA trigger applications at the CMS experiment is conventionally written using hardware description languages such as Verilog and VHDL. MaxCompiler is an alternative, Java based, tool for developing FPGA applications which uses a higher level of abstraction from the hardware than a hardware description language. An implementation of the jet and energy sum algorithms for the CMS Level-1 calorimeter trigger has been written using MaxCompiler to benchmark against the VHDL implementation in terms of accuracy, latency, resource usage, and code size. A Kalman Filter track fitting algorithm has been developed using MaxCompiler for a proposed CMS Level-1 track trigger for the High-Luminosity LHC upgrade. The design achieves a low resource usage, and has a latency of 187.5 ns per iteration.

  14. An FPGA-based trigger for the phase II of the MEG experiment

    NASA Astrophysics Data System (ADS)

    Baldini, A.; Bemporad, C.; Cei, F.; Galli, L.; Grassi, M.; Morsani, F.; Nicolò, D.; Ritt, S.; Venturini, M.

    2016-07-01

    For the phase II of MEG, we are going to develop a combined trigger and DAQ system. Here we focus on the former side, which operates an on-line reconstruction of detector signals and event selection within 450 μs from event occurrence. Trigger concentrator boards (TCB) are under development to gather data from different crates, each connected to a set of detector channels, to accomplish higher-level algorithms to issue a trigger in the case of a candidate signal event. We describe the major features of the new system, in comparison with phase I, as well as its performances in terms of selection efficiency and background rejection.

  15. Graphics Processors in HEP Low-Level Trigger Systems

    NASA Astrophysics Data System (ADS)

    Ammendola, Roberto; Biagioni, Andrea; Chiozzi, Stefano; Cotta Ramusino, Angelo; Cretaro, Paolo; Di Lorenzo, Stefano; Fantechi, Riccardo; Fiorini, Massimiliano; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Lonardo, Alessandro; Martinelli, Michele; Neri, Ilaria; Paolucci, Pier Stanislao; Pastorelli, Elena; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Vicini, Piero

    2016-11-01

    Usage of Graphics Processing Units (GPUs) in the so called general-purpose computing is emerging as an effective approach in several fields of science, although so far applications have been employing GPUs typically for offline computations. Taking into account the steady performance increase of GPU architectures in terms of computing power and I/O capacity, the real-time applications of these devices can thrive in high-energy physics data acquisition and trigger systems. We will examine the use of online parallel computing on GPUs for the synchronous low-level trigger, focusing on tests performed on the trigger system of the CERN NA62 experiment. To successfully integrate GPUs in such an online environment, latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Furthermore, it is assessed how specific trigger algorithms can be parallelized and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen Large Hadron Collider (LHC) luminosity upgrade where highly selective algorithms will be essential to maintain sustainable trigger rates with very high pileup.

  16. A high-speed DAQ framework for future high-level trigger and event building clusters

    NASA Astrophysics Data System (ADS)

    Caselle, M.; Ardila Perez, L. E.; Balzer, M.; Dritschler, T.; Kopmann, A.; Mohr, H.; Rota, L.; Vogelgesang, M.; Weber, M.

    2017-03-01

    Modern data acquisition and trigger systems require a throughput of several GB/s and latencies of the order of microseconds. To satisfy such requirements, a heterogeneous readout system based on FPGA readout cards and GPU-based computing nodes coupled by InfiniBand has been developed. The incoming data from the back-end electronics is delivered directly into the internal memory of GPUs through a dedicated peer-to-peer PCIe communication. High performance DMA engines have been developed for direct communication between FPGAs and GPUs using "DirectGMA (AMD)" and "GPUDirect (NVIDIA)" technologies. The proposed infrastructure is a candidate for future generations of event building clusters, high-level trigger filter farms and low-level trigger system. In this paper the heterogeneous FPGA-GPU architecture will be presented and its performance be discussed.

  17. Synchronization of Thomson scattering measurements on MAST using an FPGA based ``Smart'' trigger unit

    NASA Astrophysics Data System (ADS)

    Naylor, G.

    2010-10-01

    The MAST Thomson scattering diagnostic has recently been upgraded to make electron density and temperature measurements at 130 points across the 1.5 m diameter of the plasma. The new system is able to take 240 measurements per second using eight Nd:YAG lasers, each running at 30 Hz. The exact firing time of these lasers is adjusted with 100 ns precision using a field programmable gate array based trigger unit. Trigger pulses are produced to fire the lamps of all lasers and the Q switches with the appropriate delay depending on the warm-up status. The lasers may be fired in rapid bursts so as to achieve a high temporal resolution over eight points separated down to the microsecond level. This trigger unit receives optical trigger events and signals from external sources, allowing the trigger sequences to be resynchronized to the start of the plasma pulse and further events during the shot such as the entry of a fuelling pellet or randomly occurring plasma events. This resynchronization of the laser firing sequence allows accurate and reproducible measurements of fast plasma phenomena.

  18. FPGA-based algorithms for the new trigger system for the phase 2 upgrade of the CMS drift tubes detector

    NASA Astrophysics Data System (ADS)

    Cela-Ruiz, J.-M.

    2017-01-01

    The new luminosity conditions imposed after the LHC upgrade will require a dedicated upgrade of several subdetectors. To cope with the new requirements, CMS drift tubes subdetector electronics will be redesigned in order to achieve the new foreseen response speed. In particular, it is necessary to enhance the first stage of the trigger system (L1A). In this document we present the development of a software algorithm, based on the mean timer paradigm, capable of reconstructing muon trajectories and rejecting spurious signals. It has been initially written in C++ programming language, but designed with its portability to a FPGA VHDL code in mind.

  19. The CDF LEVEL3 trigger

    SciTech Connect

    Carroll, T.; Joshi, U.; Auchincloss, P.

    1989-04-01

    CDF is currently taking data at a luminosity of 10{sup 30} cm{sup -2} sec{sup -1} using a four level event filtering scheme. The fourth level, LEVEL3, uses ACP (Fermilab`s Advanced Computer Program) designed 32 bit VME based parallel processors (1) capable of executing algorithms written in FORTRAN. LEVEL3 currently rejects about 50% of the events.

  20. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

    SciTech Connect

    Jinyuan Wu et al.

    2003-11-05

    A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.

  1. Commissioning of the CMS High Level Trigger

    SciTech Connect

    Agostino, Lorenzo; et al.

    2009-08-01

    The CMS experiment will collect data from the proton-proton collisions delivered by the Large Hadron Collider (LHC) at a centre-of-mass energy up to 14 TeV. The CMS trigger system is designed to cope with unprecedented luminosities and LHC bunch-crossing rates up to 40 MHz. The unique CMS trigger architecture only employs two trigger levels. The Level-1 trigger is implemented using custom electronics, while the High Level Trigger (HLT) is based on software algorithms running on a large cluster of commercial processors, the Event Filter Farm. We present the major functionalities of the CMS High Level Trigger system as of the starting of LHC beams operations in September 2008. The validation of the HLT system in the online environment with Monte Carlo simulated data and its commissioning during cosmic rays data taking campaigns are discussed in detail. We conclude with the description of the HLT operations with the first circulating LHC beams before the incident occurred the 19th September 2008.

  2. The Zeus calorimeter first level trigger

    SciTech Connect

    Smith, W.J.

    1989-04-01

    The design of the Zeus Detector Calorimeter Level Trigger is presented. The Zeus detector is being built for operation at HERA, a new storage ring that will provide collisions between 820 GeV protons and 30 GeV electrons in 1990. The calorimeter is made of depleted uranium plates and plastic scintillator read out by wavelength shifter bars into 12,864 photomultiplier tubes. These signals are combined into 974 trigger towers with separate electromagnetic and hadronic sums. The calorimeter first level trigger is pipelined with a decision provided 5 {mu}sec after each beam crossing, occurring every 96 nsec. The trigger determines the total energy, the total transverse energy, the missing energy, and the energy and number of isolated electrons and muons. It also provides information on the number and energy of clusters. The trigger rate needs to be held to 1 kHz against a rate of proton-beam gas interactions of approximately 500 kHz. The summed trigger tower pulseheights are digitized by flash ADC`s. The digital values are linearized, stored and used for sums and pattern tests.

  3. Software-based high-level synthesis design of FPGA beamformers for synthetic aperture imaging.

    PubMed

    Amaro, Joao; Yiu, Billy Y S; Falcao, Gabriel; Gomes, Marco A C; Yu, Alfred C H

    2015-05-01

    Field-programmable gate arrays (FPGAs) can potentially be configured as beamforming platforms for ultrasound imaging, but a long design time and skilled expertise in hardware programming are typically required. In this article, we present a novel approach to the efficient design of FPGA beamformers for synthetic aperture (SA) imaging via the use of software-based high-level synthesis techniques. Software kernels (coded in OpenCL) were first developed to stage-wise handle SA beamforming operations, and their corresponding FPGA logic circuitry was emulated through a high-level synthesis framework. After design space analysis, the fine-tuned OpenCL kernels were compiled into register transfer level descriptions to configure an FPGA as a beamformer module. The processing performance of this beamformer was assessed through a series of offline emulation experiments that sought to derive beamformed images from SA channel-domain raw data (40-MHz sampling rate, 12 bit resolution). With 128 channels, our FPGA-based SA beamformer can achieve 41 frames per second (fps) processing throughput (3.44 × 10(8) pixels per second for frame size of 256 × 256 pixels) at 31.5 W power consumption (1.30 fps/W power efficiency). It utilized 86.9% of the FPGA fabric and operated at a 196.5 MHz clock frequency (after optimization). Based on these findings, we anticipate that FPGA and high-level synthesis can together foster rapid prototyping of real-time ultrasound processor modules at low power consumption budgets.

  4. Performance of the CMS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Perrotta, Andrea

    2015-12-01

    The CMS experiment has been designed with a 2-level trigger system. The first level is implemented using custom-designed electronics. The second level is the so-called High Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. For Run II of the Large Hadron Collider, the increases in center-of-mass energy and luminosity will raise the event rate to a level challenging for the HLT algorithms. The increase in the number of interactions per bunch crossing, on average 25 in 2012, and expected to be around 40 in Run II, will be an additional complication. We present here the expected performance of the main triggers that will be used during the 2015 data taking campaign, paying particular attention to the new approaches that have been developed to cope with the challenges of the new run. This includes improvements in HLT electron and photon reconstruction as well as better performing muon triggers. We will also present the performance of the improved tracking and vertexing algorithms, discussing their impact on the b-tagging performance as well as on the jet and missing energy reconstruction.

  5. THE STAR LEVEL-3 TRIGGER SYSTEM.

    SciTech Connect

    LANGE, J.S.; ADLER, C.; BERGER, J.; DEMELLO, M.; FLIERL, D.; ET AL

    1999-11-15

    The STAR level-3 trigger is a MYRINET interconnected ALPHA processor farm, performing online tracking of N{sub track} {ge} 8000 particles (N{sub point} {le} 45 per track) with a design input rate of R=100 Hz. A large scale prototype system was tested in 12/99 with laser and cosmic particle events.

  6. An optimization of the FPGA trigger based on the artificial neural network for a detection of neutrino-origin showers

    SciTech Connect

    Szadkowski, Zbigniew; Glas, Dariusz; Pytel, Krzysztof

    2015-07-01

    Observations of ultra-high energy neutrinos became a priority in experimental astro-particle physics. Up to now, the Pierre Auger Observatory did not find any candidate on a neutrino event. This imposes competitive limits to the diffuse flux of ultra-high energy neutrinos in the EeV range and above. A very low rate of events potentially generated by neutrinos is a significant challenge for a detection technique and requires both sophisticated algorithms and high-resolution hardware. A trigger based on a artificial neural network was implemented into the Cyclone{sup R} V E FPGA 5CEFA9F31I7. The prototype Front-End boards for Auger-Beyond-2015 with Cyclone{sup R} V E can test the neural network algorithm in real pampas conditions in 2015. Showers for muon and tau neutrino initiating particles on various altitudes, angles and energies were simulated in CORSICA and Offline platforms giving pattern of ADC traces in Auger water Cherenkov detectors. The 3-layer 12-10-1 neural network was taught in MATLAB by simulated ADC traces according the Levenberg-Marquardt algorithm. Results show that a probability of a ADC traces generation is very low due to a small neutrino cross-section. Nevertheless, ADC traces, if occur, for 1-10 EeV showers are relatively short and can be analyzed by 16-point input algorithm. For 100 EeV range traces are much longer, but with significantly higher amplitudes, which can be detected by standard threshold algorithms. We optimized the coefficients from MATLAB to get a maximal range of potentially registered events and for fixed-point FPGA processing to minimize calculation errors. Currently used Front-End boards based on no-more produced ACEXR PLDs and obsolete Cyclone{sup R} FPGAs allow an implementation of relatively simple threshold algorithms for triggers. New sophisticated trigger implemented in Cyclone{sup R} V E FPGAs with large amount of DSP blocks, embedded memory running with 120 - 160 MHz sampling may support to discover neutrino events

  7. FPGA based implementation of hardware diagnostic layer for local trigger of BAC calorimeter for ZEUS detector

    NASA Astrophysics Data System (ADS)

    Pozniak, Krzysztof T.

    2004-07-01

    The paper describes design and construction of hardware diagnostics layer dedicated to the local trigger of the Backing Calorimeter (BAC). The BAC is a part of the ZEUS experiment in DESY, Hamburg. A general characteristic of the hardware of BAC trigger was presented. The design of hardware diagnostic and calibration sub-systems for BAC trigger bases on the continuous monitoring of consecutive electronic and photonic blocks. The monitoring process is performed via the specialized tests. The standardized diagnostic components were realized in the algorithmic and parameterized description in AHDL. There were presented the implementation results in ALTERA ACEX chips.

  8. Level-2 Calorimeter Trigger Upgrade at CDF

    SciTech Connect

    Flanagan, G.U.; /Purdue U.

    2007-04-01

    The CDF Run II Level-2 calorimeter trigger is implemented in hardware and is based on an algorithm used in Run I. This system insured good performance at low luminosity obtained during the Tevatron Run II. However, as the Tevatron instantaneous luminosity increases, the limitations of the current system due to the algorithm start to become clear. In this paper, we will present an upgrade of the Level-2 calorimeter trigger system at CDF. The upgrade is based on the Pulsar board, a general purpose VME board developed at CDF and used for upgrading both the Level-2 tracking and the Level-2 global decision crate. This paper will describe the design, hardware and software implementation, as well as the advantages of this approach over the existing system.

  9. A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

    NASA Astrophysics Data System (ADS)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

    2005-12-01

    We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC

  10. The DISTO first level trigger at SATURNE

    SciTech Connect

    Balestra, F. |; Bedfer, Y.; Bertini, R. ||

    1998-06-01

    The DISTO collaboration has built a large-acceptance magnetic spectrometer designed to provide broad kinematic coverage of multi-particle final states produced in pp scattering. The spectrometer has been installed in the polarized proton beam of the Saturne accelerator in Saclay to study polarization observables in the {rvec p}p {yields} pK{sup +}{rvec Y} (Y = {Lambda}, {Sigma}{sup 0} or Y{sup *}) reaction and vector meson production ({psi}, {omega} and {rho}) in pp collisions. The common signature of such events is the multiplicity of four charged particles in the final state. A flexible 1st level trigger which uses topological information from fast detectors has been built. It is completely software programmable through a menu-driven user interface and allows switching between production and monitor triggers on successive beam spills.

  11. The ALICE high-level trigger read-out upgrade for LHC Run 2

    NASA Astrophysics Data System (ADS)

    Engel, H.; Alt, T.; Breitner, T.; Gomez Ramirez, A.; Kollegger, T.; Krzewicki, M.; Lehrbach, J.; Rohr, D.; Kebschull, U.

    2016-01-01

    The ALICE experiment uses an optical read-out protocol called Detector Data Link (DDL) to connect the detectors with the computing clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The interfaces of the clusters to these optical links are realized with FPGA-based PCI-Express boards. The High-Level Trigger is a computing cluster dedicated to the online reconstruction and compression of experimental data. It uses a combination of CPU, GPU and FPGA processing. For Run 2, the HLT has replaced all of its previous interface boards with the Common Read-Out Receiver Card (C-RORC) to enable read-out of detectors at high link rates and to extend the pre-processing capabilities of the cluster. The new hardware also comes with an increased link density that reduces the number of boards required. A modular firmware approach allows different processing and transport tasks to be built from the same source tree. A hardware pre-processing core includes cluster finding already in the C-RORC firmware. State of the art interfaces and memory allocation schemes enable a transparent integration of the C-RORC into the existing HLT software infrastructure. Common cluster management and monitoring frameworks are used to also handle C-RORC metrics. The C-RORC is in use in the clusters of ALICE DAQ and HLT since the start of LHC Run 2.

  12. NaNet-10: a 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector.

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Fiorini, M.; Frezza, O.; Lonardo, A.; Lamanna, G.; Lo Cicero, F.; Martinelli, M.; Neri, I.; Paolucci, P. S.; Pastorelli, E.; Piandani, R.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.; Tosoratto, L.; Vicini, P.

    2016-03-01

    A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power. To ensure the real-time operation of the system, a dedicated data transport mechanism has been implemented: an FPGA-based Network Interface Card (NaNet-10) receives data from detectors and forwards them with low, predictable latency to the memory of the GPU performing the trigger algorithms. Results of the ring-shaped hit patterns reconstruction will be reported and discussed.

  13. Upgrade of the PreProcessor system for the ATLAS level-1 calorimeter trigger

    NASA Astrophysics Data System (ADS)

    Khomich, A.

    2010-12-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-PT objects in the ATLAS calorimeters within a fixed latency of 2.5 us. It consists of three subsystems: the PreProcessor which conditions and digitises analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serialisers designed and implemented in ten year old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to enhance the flexibility of the digital processing and to profit from state-of-the-art electronics. The development and first test results are presented.

  14. High Level Trigger Configuration and Handling of Trigger Tables in the CMS Filter Farm

    SciTech Connect

    Bauer, G; Behrens, U; Boyer, V; Branson, J; Brett, A; Cano, E; Carboni, A; Ciganek, M; Cittolin, S; O'dell, V; Erhan, S; Gigi, D; Glege, F; Gomez-Reino, R; Gulmini, M; Gutleber, J; Hollar, J; Lange, D; Kim, J C; Klute, M; Lipeles, E; Perez, J L; Maron, G; Meijers, F; Meschi, E; Moser, R; Mlot, E G; Murray, S; Oh, A; Orsini, L; Paus, C; Petrucci, A; Pieri, M; Pollet, L; Racz, A; Sakulin, H; Sani, M; Schieferdecker, P; Schwick, C; Sumorok, K; Suzuki, I; Tsirigkas, D; Varela, J

    2009-11-22

    The CMS experiment at the CERN Large Hadron Collider is currently being commissioned and is scheduled to collect the first pp collision data in 2008. CMS features a two-level trigger system. The Level-1 trigger, based on custom hardware, is designed to reduce the collision rate of 40 MHz to approximately 100 kHz. Data for events accepted by the Level-1 trigger are read out and assembled by an Event Builder. The High Level Trigger (HLT) employs a set of sophisticated software algorithms, to analyze the complete event information, and further reduce the accepted event rate for permanent storage and analysis. This paper describes the design and implementation of the HLT Configuration Management system. First experiences with commissioning of the HLT system are also reported.

  15. The upgrade of the ATLAS first-level calorimeter trigger

    NASA Astrophysics Data System (ADS)

    Yamamoto, Shimpei

    2016-07-01

    The first-level calorimeter trigger (L1Calo) had operated successfully through the first data taking phase of the ATLAS experiment at the CERN Large Hadron Collider. Towards forthcoming LHC runs, a series of upgrades is planned for L1Calo to face new challenges posed by the upcoming increases of the beam energy and the luminosity. This paper reviews the ATLAS L1Calo trigger upgrade project that introduces new architectures for the liquid-argon calorimeter trigger readout and the L1Calo trigger processing system.

  16. Artificial Neural Network as the FPGA Trigger in the Cyclone V based Front-End for a Detection of Neutrino-Origin Showers

    SciTech Connect

    Szadkowski, Zbigniew; Glas, Dariusz; Pytel, Krzysztof

    2015-07-01

    Neutrinos play a fundamental role in the understanding of the origin of ultra-high-energy cosmic rays. They interact through charged and neutral currents in the atmosphere generating extensive air showers. However, their a very low rate of events potentially generated by neutrinos is a significant challenge for a detection technique and requires both sophisticated algorithms and high-resolution hardware. A trigger based on a artificial neural network was implemented into the Cyclone{sup R} V E FPGA 5CEFA9F31I7 - the heart of the prototype Front-End boards developed for tests of new algorithms in the Pierre Auger surface detectors. Showers for muon and tau neutrino initiating particles on various altitudes, angles and energies were simulated in CORSICA and Offline platforms giving pattern of ADC traces in Auger water Cherenkov detectors. The 3-layer 12-8-1 neural network was taught in MATLAB by simulated ADC traces according the Levenberg-Marquardt algorithm. Results show that a probability of a ADC traces generation is very low due to a small neutrino cross-section. Nevertheless, ADC traces, if occur, for 1-10 EeV showers are relatively short and can be analyzed by 16-point input algorithm. We optimized the coefficients from MATLAB to get a maximal range of potentially registered events and for fixed-point FPGA processing to minimize calculation errors. New sophisticated triggers implemented in Cyclone{sup R} V E FPGAs with large amount of DSP blocks, embedded memory running with 120 - 160 MHz sampling may support a discovery of neutrino events in the Pierre Auger Observatory. (authors)

  17. Level Zero Trigger Processor for the ultra rare kaon decay experiment: NA62

    NASA Astrophysics Data System (ADS)

    Soldi, Dario; Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.

    2017-02-01

    The NA62 experiment is designed to measure the (ultra-)rare decay K+ →π+ ν ν bar branching ratio with a precision of ∼ 10 % at the CERN Super Proton Synchrotron (SPS). The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the L0TP is completely new for a high energy physics experiment. It is fully digital, based on a standard gigabit ethernet communication between detectors and L0TP Board. The L0TP Board is a commercial development board, Terasic DE4, mounting an Altera Stratix IV FPGA. The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period (about 5 seconds). The L0TP realigns in time the primitives coming from 7 different sources and manages the information of the time plus all the characteristics of the event as energy, multiplicity and position of hits in order to select good events with a comparison with preset masks. It should guarantee a maximum latency of 1 ms. The maximum input rate is 10 MHz for each sub-detector, while the design maximum output trigger rate is 1 MHz. A complete trigger-less parasitic acquisition of the primitives is possible using mirroring switches to monitor the L0 behavior. A first version of the L0TP was commissioned during the 2014 NA62 pilot run and it is used in the current data taking. A description of the trigger algorithm is here presented.

  18. NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

    NASA Astrophysics Data System (ADS)

    Ammendola, Roberto; Biagioni, Andrea; Fantechi, Riccardo; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Lonardo, Alessandro; Stanislao Paolucci, Pier; Pantaleo, Felice; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

    2014-06-01

    We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  19. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    NASA Astrophysics Data System (ADS)

    Glatzer, Julian

    2015-12-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of two with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the factor of two increase in the number of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to three different subdetector combinations. An overview of the operational software framework of the L1CT system with particular emphasis on the configuration, controls and monitoring aspects is given. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition system. Trigger and dead-time rates are monitored coherently at all stages of processing and are logged by the online computing system for physics analysis, data quality assurance and operational debugging. In addition, the synchronisation of trigger inputs is watched based on bunch-by-bunch trigger information. Several software tools allow for efficient display of the relevant information in the control room in a way useful for shifters and experts. The design of the framework aims at reliability, flexibility, and robustness of the system and takes into account the operational experience gained during Run 1. The Level-1 Central Trigger was successfully operated with high efficiency during the cosmic-ray, beam-splash and first Run 2 data taking with the full ATLAS detector.

  20. The CMS Level-1 Calorimeter Trigger for LHC Run II

    NASA Astrophysics Data System (ADS)

    Sinthuprasith, Tutanon

    2017-01-01

    The phase-1 upgrades of the CMS Level-1 calorimeter trigger have been completed. The Level-1 trigger has been fully commissioned and it will be used by CMS to collect data starting from the 2016 data run. The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Design, which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the uTCA standard. The architecture is flexible and the number of trigger processors can be expanded according to the physics needs of CMS. Intelligent, more complex, and innovative algorithms are now the core of the first decision layer of CMS: the upgraded trigger system implements pattern recognition and MVA (Boosted Decision Tree) regression techniques in the trigger processors for pT assignment, pile up subtraction, and isolation requirements for electrons, and taus. The performance of the TMT design and the latency measurements and the algorithm performance which has been measured using data is also presented here.

  1. The CMS Level-1 trigger system for LHC Run II

    NASA Astrophysics Data System (ADS)

    Cadamuro, L.

    2017-03-01

    The Compact Muon Solenoid (CMS) experiment implements a sophisticated two-level online selection system that achieves a rejection factor of nearly 105. During Run II, the LHC has increased the centre-of-mass energy of proton-proton collisions up to 13 TeV and may progressively reach an instantaneous luminosity of 2×1034 cm‑2 s‑1 or higher. In order to guarantee a successful and ambitious physics programme under this intense environment, the CMS Trigger and Data acquisition system has been upgraded. The upgraded CMS Level-1 (L1) trigger benefits from the recent μTCA technology and is designed to maintain the performance under high instantaneous luminosity conditions. More sophisticated, innovative algorithms are now the core of the first decision layer of CMS: this drastically reduces the trigger rate and improves the trigger efficiency for a wide variety of physics processes. In this document, we present the overall architecture of the upgraded Level-1 trigger system. The performance of single object triggers, measured on collision data recorded during the 2016 running period, are also summarised.

  2. CROC FPGA Firmware

    SciTech Connect

    2009-12-01

    The CROC FPGA firmware code controls the operation of CROC hardware primarily deterinining the location of neutron events and discriminating against false trigger by examining the output of multiple analog comparators. A number of stoical algorithms are encode within the firmware to achieve reliable operation. Other communication and control functions are also part of the firmware.

  3. A massively parallel track-finding system for the LEVEL 2 trigger in the CLAS detector at CEBAF

    SciTech Connect

    Doughty, D.C. Jr.; Collins, P.; Lemon, S. ); Bonneau, P. )

    1994-02-01

    The track segment finding subsystem of the LEVEL 2 trigger in the CLAS detector has been designed and prototyped. Track segments will be found in the 35,076 wires of the drift chambers using a massively parallel array of 768 Xilinx XC-4005 FPGA's. These FPGA's are located on daughter cards attached to the front-end boards distributed around the detector. Each chip is responsible for finding tracks passing through a 4 x 6 slice of an axial superlayer, and reports two segment found bits, one for each pair of cells. The algorithm used finds segments even when one or two layers or cells along the track is missing (this number is programmable), while being highly resistant to false segments arising from noise hits. Adjacent chips share data to find tracks crossing cell and board boundaries. For maximum speed, fully combinatorial logic is used inside each chip, with the result that all segments in the detector are found within 150 ns. Segment collection boards gather track segments from each axial superlayer and pass them via a high speed link to the segment linking subsystem in an additional 400 ns for typical events. The Xilinx chips are ram-based and therefore reprogrammable, allowing for future upgrades and algorithm enhancements.

  4. Event Builder and Level 3 trigger at the CDF experiment

    NASA Astrophysics Data System (ADS)

    Anikeev, K.; Bauer, G.; Furić, I.; Holmgren, D.; Korn, A.; Kravchenko, I.; Mulhearn, M.; Ngan, P.; Paus, Ch.; Rakitin, A.; Rechenmacher, R.; Shah, T.; Sphicas, P.; Sumorok, K.; Tether, S.; Tseng, J.; Wüerthwein, F.

    2001-10-01

    The Event Builder and Level 3 trigger systems of the CDF experiment at Fermilab are required to process about 300 events per second, with an average event size of ˜200 KB. In the event building process the event is assembled from 15 sources supplying event fragments with roughly equal sizes of 12-16 KB. In the subsequent commercial processor-based Level 3 trigger, the events are reconstructed and trigger algorithms are applied. The CPU power required for filtering such a high data throughput rate exceeds 45 000 MIPS. To meet these requirements a distributed and scalable architecture has been chosen. It is based on commodity components: VME-based CPU's for the data read out, an ATM switch for the event building and Pentium-based personal computers running the Linux operating system for the event processing. Event flow through ATM is controlled by a reflective memory ring. The roughly homogeneous distribution of the expected load allows the use of 100 Mbps Ethernet for event distribution and collection within the Level 3 system. Preliminary results from a test system obtained during the last year are presented.

  5. Implementation And Performance of the ATLAS Second Level Jet Trigger

    SciTech Connect

    Conde Muino, Patricia; Aracena, I.; Brelier, B.; Cranmer, K.; Delsart, P.A.; Dufour, M.A.; Eckweiler, S.; Ferland, J.; Idarraga, J.; Johns, K.; LeCompte, T.; Potter, C.; Robertson, S.; Santamarina Rios, C.; Segura, E.; Silverstein, D.; Vachon, B.; /McGill U.

    2011-11-09

    ATLAS is one of the four major LHC experiments, designed to cover a wide range of physics topics. In order to cope with a rate of 40MHz and 25 interactions per bunch crossing, the ATLAS trigger system is divided in three different levels. The jet selection starts at first level with dedicated processors that search for high E{sub T} hadronic energy depositions. At the LVL2, the jet signatures are verified with the execution of a dedicated, fast jet reconstruction algorithm, followed by a calibration algorithm. Three possible granularities have been proposed and are being evaluated: cell based (standard), energy sums calculated at each Front-End Board and the use of the LVL1 Trigger Towers. In this presentation, the design and implementation of the jet trigger of ATLAS will be discussed in detail, emphasazing the major difficulties of each selection step. The performance of the jet algorithm, including timing, efficiencies and rates will also be shown, with detailed comparisons of the different unpacking modes.

  6. The LHCb Data Acquisition and High Level Trigger Processing Architecture

    NASA Astrophysics Data System (ADS)

    Frank, M.; Gaspar, C.; Jost, B.; Neufeld, N.

    2015-12-01

    The LHCb experiment at the LHC accelerator at CERN collects collisions of particle bunches at 40 MHz. After a first level of hardware trigger with an output rate of 1 MHz, the physically interesting collisions are selected by running dedicated trigger algorithms in the High Level Trigger (HLT) computing farm. This farm consists of up to roughly 25000 CPU cores in roughly 1750 physical nodes each equipped with up to 4 TB local storage space. This work describes the LHCb online system with an emphasis on the developments implemented during the current long shutdown (LS1). We will elaborate the architecture to treble the available CPU power of the HLT farm and the technicalities to determine and verify precise calibration and alignment constants which are fed to the HLT event selection procedure. We will describe how the constants are fed into a two stage HLT event selection facility using extensively the local disk buffering capabilities on the worker nodes. With the installed disk buffers, the CPU resources can be used during periods of up to ten days without beams. These periods in the past accounted to more than 70% of the total time.

  7. ATLAS level-1 calorimeter trigger: Monitoring and data reprocessing

    NASA Astrophysics Data System (ADS)

    Dimond, David; Hong, Tae; Carlson, Benjamin; Atlas Collaboration

    2017-01-01

    We present the monitoring and data reprocessing for the calorimeter-based hardware level-1 trigger system (L1Calo) for the ATLAS experiment. This trigger system was upgraded after the Run-1 data taking period (2009-2012) to prepare for Run-2 (2015-current), which allowed better control the event rates for algorithms based on jets and/or missing energy. Monitoring tools for the upgraded system is described. We also present a new offline tool to reprocess previous data samples with altered L1Calo settings, such as calibration constants and noise cuts. The samples are used to study the dependence of the event rates and signal efficiencies on the settings. The studies can help plan the appropriate L1Calo settings for upcoming data taking periods as well as for future runs.

  8. FPGA Design Practices for I&C in Nuclear Power Plants

    SciTech Connect

    Bobrek, Miljko; Wood, Richard Thomas; Bouldin, Donald; Waterman, Michael E

    2009-01-01

    Safe FPGA design practices can be classified into three major groups covering board-level and FPGA logic-level design practices, FPGA design entry methods, and FPGA design methodology. This paper is presenting the most common hardware and software design practices that are acceptable in safety-critical FPGA systems. It also proposes an FPGA-specific design life cycle including design entry, FPGA synthesis, place and route, and validation and verification.

  9. GPU-based low-level trigger system for the standalone reconstruction of the ring-shaped hit patterns in the RICH Cherenkov detector of NA62 experiment

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Chiozzi, S.; Cretaro, P.; Cotta Ramusino, A.; Di Lorenzo, S.; Fantechi, R.; Fiorini, M.; Frezza, O.; Gianoli, A.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P. S.; Pastorelli, E.; Piandani, R.; Piccini, M.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.; Vicini, P.

    2017-03-01

    This project aims to exploit the parallel computing power of a commercial Graphics Processing Unit (GPU) to implement fast pattern matching in the Ring Imaging Cherenkov (RICH) detector for the level 0 (L0) trigger of the NA62 experiment. In this approach, the ring-fitting algorithm is seedless, being fed with raw RICH data, with no previous information on the ring position from other detectors. Moreover, since the L0 trigger is provided with a more elaborated information than a simple multiplicity number, it results in a higher selection power. Two methods have been studied in order to reduce the data transfer latency from the readout boards of the detector to the GPU, i.e., the use of a dedicated NIC device driver with very low latency and a direct data transfer protocol from a custom FPGA-based NIC to the GPU. The performance of the system, developed through the FPGA approach, for multi-ring Cherenkov online reconstruction obtained during the NA62 physics runs is presented.

  10. Real-time FPGA design for the L0-trigger of the RICH detector of the NA62 experiment at CERN SPS

    NASA Astrophysics Data System (ADS)

    Barbanera, M.; Gonnella, F.

    2017-01-01

    The NA62 experiment aims at measuring rare kaon decays, in order to precisely test the standard model. The RICH (Ring Imaging CHerenkov) detector of the experiment is instrumental in charged-particle identification and in measurement of their crossing time, with a resolution better than 100 ps. Here we describe the design of the Level-0 trigger system for the RICH, which provides a precise time reference by counting the input hit multiplicity within programmable fine-time windows. Since the design does not use spatial information and stands the maximum input rate of TDC-based NA62 systems, it can be deployed also in other subdetectors.

  11. The Level-1 Tile-Muon Trigger in the Tile Calorimeter upgrade program

    NASA Astrophysics Data System (ADS)

    Ryzhov, A.

    2016-12-01

    The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). TileCal provides highly-segmented energy measurements for incident particles. Information from TileCal's outermost radial layer can assist in muon tagging in the Level-1 Muon Trigger by rejecting fake muon triggers due to slow charged particles (typically protons) without degrading the efficiency of the trigger. The main activity of the Tile-Muon Trigger in the ATLAS Phase-0 upgrade program was to install and to activate the TileCal signal processor module for providing trigger inputs to the Level-1 Muon Trigger. This report describes the Tile-Muon Trigger, focusing on the new detector electronics such as the Tile Muon Digitizer Board (TMDB) that receives, digitizes and then provides the signal from eight TileCal modules to three Level-1 muon endcap Sector-Logic Boards.

  12. Active FPGA Security Through Decoy Circuits

    DTIC Science & Technology

    2006-03-01

    FPGA and is reported in the units provided by the FPGA software that converts a circuit schematic and/or VHDL code to an FPGA programming file. Power...described by truth or state tables and by Boolean Equations, in a gate-level representation, and in existing VHDL code are provided. The method for...The following is the VHDL code for a Combination Lock with eight states and three inputs. -- original state machine code from Doug Hodson’s -- L

  13. Natrium: Use of FPGA embedded processors for real-time data compression

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Rossetti, D.; Salamon, A.; Salina, G.; Simula, F.; Tosoratto, L.; Vicini, P.

    2011-12-01

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  14. The upgrade of the CMS Global Trigger

    NASA Astrophysics Data System (ADS)

    Wittmann, J.; Arnold, B.; Bergauer, H.; Jeitler, M.; Matsushita, T.; Rabady, D.; Rahbaran, B.; Wulz, C.-E.

    2016-02-01

    The Global Trigger is the final step of the CMS Level-1 Trigger. Previously implemented in VME, it has been redesigned and completely rebuilt in MicroTCA technology, using the Virtex-7 FPGA chip family. It will allow to implement trigger algorithms close to the final physics selection. The new system is presented, together with performance tests undertaken in parallel operation with the legacy system during the initial months of Run II of the LHC at a beam energy of 13 TeV.

  15. FPGA-based multimodal embedded sensor system integrating low- and mid-level vision.

    PubMed

    Botella, Guillermo; Martín H, José Antonio; Santos, Matilde; Meyer-Baese, Uwe

    2011-01-01

    Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

  16. Reconfigurable ASIC for a low level trigger system in Cherenkov Telescope Cameras

    NASA Astrophysics Data System (ADS)

    Gascon, D.; Barrio, J. A.; Blanch, O.; Boix, J.; Delagnes, E.; Delgado, C.; Freixas, L.; Guilloux, F.; Coto, R. L.; Griffiths, S.; Martínez, G.; Martínez, O.; Sanuy, A.; Tejedor, L. Á.

    2016-11-01

    A versatile and reconfigurable ASIC is presented, which implements two different concepts of low level trigger (L0) for Cherenkov telescopes: the Majority trigger (sum of discriminated inputs) and the Sum trigger concept (analogue clipped sum of inputs). Up to 7 input signals can be processed following one or both of the previous trigger concepts. Each differential pair output of the discriminator is also available as a LVDS output. Differential circuitry using local feedback allows the ASIC to achieve high speed (500 MHz) while maintaining good linearity in a 1 Vpp range. Experimental results are presented. A number of prototype camera designs of the Cherenkov Telescope Array (CTA) project will use this ASIC.

  17. The CMS Level-1 electron and photon trigger: for Run II of LHC

    NASA Astrophysics Data System (ADS)

    Dev, N.; Jessop, C.; Meng, F.; Marinelli, N.; Taroni, S.; Beaudette, F.; Cadamuro, L.; Davignon, O.; Romanteau, T.; Strebler, T.; Zabi, A.; Sauvan, J. B.; Marrouche, J.; Wardle, N.; Aggleton, R.; Ball, F.; Brooke, J.; Newbold, D.; Paramesvaran, S.; Smith, D.; Taylor, J.; Baber, M.; Bundock, A.; Citron, M.; Elwood, A.; Hall, G.; Iles, G.; Laner, C.; Penning, B.; Rose, A.; Shtipliyski, A.; Tapper, A.; Durkin, T.; Harder, K.; Harper, S.; Shepherd-Themistocleous, C.; Thea, A.; Williams, T.; Neu, C.; Sinthuprasith, T.; Xia, F.

    2017-02-01

    The Compact Muon Solenoid (CMS) employs a sophisticated two-level online triggering system that has a rejection factor of up to 105. Since the beginning of Run II of LHC, the conditions that CMS operates in have become increasingly challenging. The centre-of-mass energy is now 13 TeV and the instantaneous luminosity currently peaks at 1.5 ×1034 cm‑2s‑1. In order to keep low physics thresholds and to trigger efficiently in such conditions, the CMS trigger system has been upgraded. A new trigger architecture, the Time Multiplexed Trigger (TMT) has been introduced which allows the full granularity of the calorimeters to be exploited at the first level of the online trigger. The new trigger has also benefited immensely from technological improvements in hardware. Sophisticated algorithms, developed to fully exploit the advantages provided by the new hardware architecture, have been implemented. The new trigger system started taking physics data in 2016 following a commissioning period in 2015, and since then has performed extremely well. The hardware and firmware developments, electron and photon algorithms together with their performance in challenging 2016 conditions is presented.

  18. Measuring Science Teachers' Stress Level Triggered by Multiple Stressful Conditions

    ERIC Educational Resources Information Center

    Halim, Lilia; Samsudin, Mohd Ali; Meerah, T. Subahan M.; Osman, Kamisah

    2006-01-01

    The complexity of science teaching requires science teachers to encounter a range of tasks. Some tasks are perceived as stressful while others are not. This study aims to investigate the extent to which different teaching situations lead to different stress levels. It also aims to identify the easiest and most difficult conditions to be regarded…

  19. The Calorimeter Trigger Processor Card: the next generation of high speed algorithmic data processing at CMS

    NASA Astrophysics Data System (ADS)

    Svetek, A.; Blake, M.; Cepeda Hermida, M.; Dasu, S.; Dodd, L.; Fobes, R.; Gomber, B.; Gorski, T.; Guo, Z.; Klabbers, P.; Levine, A.; Ojalvo, I.; Ruggles, T.; Smith, N.; Smith, W. H.; Tikalsky, J.; Vicente, M.; Woods, N.

    2016-02-01

    The CMS Level-1 upgraded calorimeter trigger requires a powerful, flexible and compact processing card. The Calorimeter Trigger Processor Card (CTP7) uses the Virtex-7 FPGA as its primary data processor and is the first FPGA based processing card in CMS to employ the ZYNQ System-on-Chip (SoC) running embedded Linux to provide TCP/IP communication and board support functions. The CTP7 was built from the ground up to support AXI infrastructure to provide flexible and modular designs with minimal time from project conception to final implementation.

  20. A 250 MHz Level 1 Trigger and Distribution System for the GlueX experiment

    SciTech Connect

    Abbott, David J.; Cuevas, R. Christopher; Doughty, David Charles; Jastrzembski, Edward A.; Barbosa, Fernando J.; Raydo, Benjamin J.; Dong, Hai T.; Wilson, Jeffrey S.; Gupta, Abishek; Taylor, Mark; Somov, S.

    2009-11-01

    The GlueX detector now under construction at Jefferson Lab will search for exotic mesons though photoproduction (10^8 tagged photons per second) on a liquid hydrogen target. A Level 1 hardware trigger design is being developed to reduce total electromagnetic (>200 MHz) and hadronic (>350 kHz) rates to less than 200 kHz. This trigger is dead timeless and operates on a global synchronized 250 MHz clock. The core of the trigger design is based on a custom pipelined flash ADC board that uses a VXS backplane to collect samples from all ADCs in a VME crate. A custom switch-slot board called a Crate Trigger Processor (CTP) processes this data and passes the crate level data via a multi-lane fiber optic link to the Global Trigger Processing Crate (also VXS). Within this crate detector sub-system processor (SSP) boards can accept all individual crate links. The subsystem data are processed and finally passed to global trigger boards (GTP) where the final L1 decision is made. We present details of the trigger design and report some performance results on current prototype systems.

  1. GPU-Based Tracking Algorithms for the ATLAS High-Level Trigger

    NASA Astrophysics Data System (ADS)

    Emeliyanov, D.; Howard, J.

    2012-12-01

    Results on the performance and viability of data-parallel algorithms on Graphics Processing Units (GPUs) in the ATLAS Level 2 trigger system are presented. We describe the existing trigger data preparation and track reconstruction algorithms, motivation for their optimization, GPU-parallelized versions of these algorithms, and a “client-server” solution for hybrid CPU/GPU event processing used for integration of the GPU-oriented algorithms into existing ATLAS trigger software. The resulting speed-up of event processing times obtained with high-luminosity simulated data is presented and discussed.

  2. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    NASA Astrophysics Data System (ADS)

    Magazzù, G.; Borgese, G.; Costantino, N.; Fanucci, L.; Incandela, J.; Saponara, S.

    2013-02-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  3. L1Track: A fast Level 1 track trigger for the ATLAS high luminosity upgrade

    NASA Astrophysics Data System (ADS)

    Cerri, Alessandro

    2016-07-01

    With the planned high-luminosity upgrade of the LHC (HL-LHC), the ATLAS detector will see its collision rate increase by approximately a factor of 5 with respect to the current LHC operation. The earliest hardware-based ATLAS trigger stage ("Level 1") will have to provide a higher rejection factor in a more difficult environment: a new improved Level 1 trigger architecture is under study, which includes the possibility of extracting with low latency and high accuracy tracking information in time for the decision taking process. In this context, the feasibility of potential approaches aimed at providing low-latency high-quality tracking at Level 1 is discussed.

  4. Level 3 trigger algorithm and Hardware Platform for the HADES experiment

    NASA Astrophysics Data System (ADS)

    Kirschner, Daniel Georg; Agakishiev, Geydar; Liu, Ming; Perez, Tiago; Kühn, Wolfgang; Pechenov, Vladimir; Spataro, Stefano

    2009-01-01

    A next generation real time trigger method to improve the enrichment of lepton events in the High Acceptance DiElectron Spectrometer (HADES) trigger system has been developed. In addition, a flexible Hardware Platform (Gigabit Ethernet-Multi-Node, GE-MN) was developed to implement and test the trigger method. The trigger method correlates the ring information of the HADES Ring Imaging Cherenkov (RICH) detector with the fired wires (drift cells) of the HADES Mini Drift Chamber (MDC) detector. It is demonstrated that this Level 3 trigger method can enhance the number of events which contain leptons by a factor of up to 50 at efficiencies above 80%. The performance of the correlation method in terms of the events analyzed per second has been studied with the GE-MN prototype in a lab test setup by streaming previously recorded experiment data to the module. This paper is a compilation from Kirschner [Level 3 trigger algorithm and Hardware Platform for the HADES experiment, Ph.D. Thesis, II. Physikalisches Institut der Justus-Liebig-Universität Gießen, urn:nbn:de:hebis:26-opus-50784, October 2007 [1

  5. FPGA implementation of image enhancement techniques

    NASA Astrophysics Data System (ADS)

    Kumar, Karan; Jain, Aditya; Srivastava, Atul Kumar

    2009-06-01

    The objective of this paper is designing, modeling, simulation and synthesis of four Image Enhancement techniques on FPGA. Image Enhancement Algorithms can be classified as point processing Techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel. Algorithms of all the techniques are studied and hardware circuits are realized for them. Then hardware logic is modeled in Matlab Simulink using Xilinx System Generator Block set and synthesized onto Virtex4 xc4vsx35-10ff668 FPGA chip. Using hardware co-simulation feature of FPGA kit, the algorithms developed are validated.

  6. Data flow analysis of a highly parallel processor for a level 1 pixel trigger

    SciTech Connect

    Cancelo, G.; Gottschalk, Erik Edward; Pavlicek, V.; Wang, M.; Wu, J.

    2003-01-01

    The present work describes the architecture and data flow analysis of a highly parallel processor for the Level 1 Pixel Trigger for the BTeV experiment at Fermilab. First the Level 1 Trigger system is described. Then the major components are analyzed by resorting to mathematical modeling. Also, behavioral simulations are used to confirm the models. Results from modeling and simulations are fed back into the system in order to improve the architecture, eliminate bottlenecks, allocate sufficient buffering between processes and obtain other important design parameters. An interesting feature of the current analysis is that the models can be extended to a large class of architectures and parallel systems.

  7. Design and Implementation of the New D0 Level-1 Calorimeter Trigger

    SciTech Connect

    Abolins, M.; Adams, M.; Adams, T.; Aguilo, E.; Anderson, J.; Bagby, L.; Ban, J.; Barberis, E.; Beale, S.; Benitez, J.; Biehl, J.; /Columbia U. /DAPNIA, Saclay /Delhi U. /Fermilab /Florida State U. /Indiana U. /Michigan State U. /Northeastern U. /Rice U. /Southern Methodist U. /University Coll., Dublin

    2007-09-01

    Increasing luminosity at the Fermilab Tevatron collider has led the D0 collaboration to make improvements to its detector beyond those already in place for Run IIa, which began in March 2001. One of the cornerstones of this Run IIb upgrade is a completely redesigned level-1 calorimeter trigger system. The new system employs novel architecture and algorithms to retain high efficiency for interesting events while substantially increasing rejection of background. We describe the design and implementation of the new level-1 calorimeter trigger hardware and discuss its performance during Run IIb data taking. In addition to strengthening the physics capabilities of D0, this trigger system will provide valuable insight into the operation of analogous devices to be used at LHC experiments.

  8. The CMS Level-1 Calorimeter Trigger for the LHC Run II

    NASA Astrophysics Data System (ADS)

    Zabi, A.; Beaudette, F.; Cadamuro, L.; Davignon, O.; Romanteau, T.; Strebler, T.; Cepeda, M.; Sauvan, J. B.; Wardle, N.; Aggleton, R.; Ball, F.; Brooke, J.; Newbold, D.; Paramesvaran, S.; Smith, D.; Taylor, J.; Foudas, C.; Baber, M.; Bundock, A.; Breeze, S.; Citron, M.; Elwood, A.; Hall, G.; Iles, G.; Laner, C.; Penning, B.; Rose, A.; Shtipliyski, A.; Tapper, A.; Ojalvo, I.; Durkin, T.; Harder, K.; Harper, S.; Shepherd-Themistocleous, C.; Thea, A.; Williams, T.; Dasu, S.; Dodd, L.; Forbes, R.; Gorski, T.; Klabbers, P.; Levine, A.; Ruggles, T.; Smith, N.; Smith, W.; Svetek, A.; Tikalsky, J.; Vicente, M.

    2017-01-01

    Results from the completed Phase 1 Upgrade of the Compact Muon Solenoid (CMS) Level-1 Calorimeter Trigger are presented. The upgrade was performed in two stages, with the first running in 2015 for proton and heavy ion collisions and the final stage for 2016 data taking. The Level-1 trigger has been fully commissioned and has been used by CMS to collect over 43 fb‑1 of data since the start of the Run II of the Large Hadron Collider (LHC). The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Trigger (TMT), which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the μTCA standard. The trigger processors are instrumented with Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links. The TMT architecture is flexible and the number of trigger processors can be expanded according to the physics needs of CMS. Sophisticated and innovative algorithms are now the core of the first decision layer of the experiment. The system has been able to adapt to the outstanding performance of the LHC, which ran with an instantaneous luminosity well above design. The performance of the system for single physics objects are presented along with the optimizations foreseen to maintain the thresholds for the harsher conditions expected during the LHC Run II and Run III periods.

  9. FPGA Material for the Undergraduate School

    NASA Astrophysics Data System (ADS)

    Yawata, Kazushi

    A set of digital electronis educational material introducing the FPGA is developed and a syllabus is designed for the physics laboratory class in the undergraduate school. The material is developed with Spartan-3 (Xilinx). The syllabus covers the design procedure using ISE with VerilogHDL, a discussion on how the FPGA can realize circuits with the generated RTL and logic level circuit diagrams and observations with an oscilloscope.

  10. The BaBar Level 1 Drift-Chamber Trigger Upgrade With 3D Tracking

    SciTech Connect

    Chai, X.D.; /Iowa U.

    2005-11-29

    At BABAR, the Level 1 Drift Chamber trigger is being upgraded to reduce increasing background rates while the PEP-II luminosity keeps improving. This upgrade uses the drift time information and stereo wires in the drift chamber to perform a 3D track reconstruction that effectively rejects background events spread out along the beam line.

  11. WATER LEVEL DRAWDOWN TRIGGERS SYSTEM-WIDE BUBBLE RELEASE FROM RESERVOIR SEDIMENTS

    EPA Science Inventory

    Reservoirs are an important anthropogenic source of methane and ebullition is a key pathway by which methane stored in reservoir sediments can be released to the atmosphere. Changes in hydrostatic pressure during periods of falling water levels can trigger bubbling events, sugge...

  12. ATLAS level-1 calorimeter trigger: Run-2 performance and Phase-1 upgrades

    NASA Astrophysics Data System (ADS)

    Carlson, Ben; Hong, Tae Min; Atlas Collaboration

    2017-01-01

    The Run-2 performance and Phase-1 upgrade are presented for the hardware-based level-1 calorimeter trigger (L1Calo) for the ATLAS Experiment. This trigger has a latency of about 2.2 microseconds to make a decision to help ATLAS select about 100 kHz of the most interesting collisions from the nominal LHC rate of 40 MHz. We summarize the upgrade after Run-1 (2009-2012) and discuss its performance in Run-2 (2015-current). We also outline the on-going Phase-1 upgrade for the next run (2021-2024) and its expected performance.

  13. The architecture of the CMS Level-1 Trigger Control and Monitoring System using UML

    NASA Astrophysics Data System (ADS)

    Magrans de Abril, Marc; Da Rocha Melo, Jose L.; Ghabrous Larrea, Carlos; Hammer, Josef; Hartl, Christian; Lazaridis, Christos

    2011-12-01

    The architecture of the Compact Muon Solenoid (CMS) Level-1 Trigger Control and Monitoring software system is presented. This system has been installed and commissioned on the trigger online computers and is currently used for data taking. It has been designed to handle the trigger configuration and monitoring during data taking as well as all communications with the main run control of CMS. Furthermore its design has foreseen the provision of the software infrastructure for detailed testing of the trigger system during beam down time. This is a medium-size distributed system that runs over 40 PCs and 200 processes that control about 4000 electronic boards. The architecture of this system is described using the industry-standard Universal Modeling Language (UML). This way the relationships between the different subcomponents of the system become clear and all software upgrades and modifications are simplified. The described architecture has allowed for frequent upgrades that were necessary during the commissioning phase of CMS when the trigger system evolved constantly. As a secondary objective, the paper provides a UML usage example and tries to encourage the standardization of the software documentation of large projects across the LHC and High Energy Physics community.

  14. Online measurement of LHC beam parameters with the ATLAS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Strauss, E.

    2012-06-01

    We present an online measurement of the LHC beamspot parameters in ATLAS using the High Level Trigger (HLT). When a significant change is detected in the measured beamspot, it is distributed to the HLT. There, trigger algorithms like b-tagging which calculate impact parameters or decay lengths benefit from a precise, up-to-date set of beamspot parameters. Additionally, online feedback is sent to the LHC operators in real time. The measurement is performed by an algorithm running on the Level 2 trigger farm, leveraging the high rate of usable events. Dedicated algorithms perform a full scan of the silicon detector to reconstruct event vertices from registered tracks. The distribution of these vertices is aggregated across the farm and their shape is extracted through fits every 60 seconds to determine the beamspot position, size, and tilt. The reconstructed beamspot values are corrected for detector resolution effects, measured in situ using the separation of vertices whose tracks have been split into two collections. Furthermore, measurements for individual bunch crossings have allowed for studies of single-bunch distributions as well as the behavior of bunch trains. This talk will cover the constraints imposed by the online environment and describe how these measurements are accomplished with the given resources. The algorithm tasks must be completed within the time constraints of the Level 2 trigger, with limited CPU and bandwidth allocations. This places an emphasis on efficient algorithm design and the minimization of data requests.

  15. FPGA Verification Accelerator (FVAX)

    NASA Technical Reports Server (NTRS)

    Oh, Jane; Burke, Gary

    2008-01-01

    Is Verification Acceleration Possible? - Increasing the visibility of the internal nodes of the FPGA results in much faster debug time - Forcing internal signals directly allows a problem condition to be setup very quickly center dot Is this all? - No, this is part of a comprehensive effort to improve the JPL FPGA design and V&V process.

  16. Design and performance of the phase I upgrade of the CMS Global Trigger

    NASA Astrophysics Data System (ADS)

    Wittmann, J.; Aradi, G.; Arnold, B.; Bergauer, H.; Jeitler, M.; Matsushita, T.; Wulz, C.-E.

    2017-01-01

    The Global Trigger is the final decision stage of the Level-1 Trigger of the CMS Experiment at the LHC. Previously implemented in VME, it has been redesigned and completely rebuilt in MicroTCA technology, using the Virtex-7 FPGA chip family. This allows implementing trigger algorithms close to the final analysis selection, combining different physical objects. The flexible and compact new system is presented, together with performance tests at a proton-proton centre-of-mass energy of 13 TeV. Firmware and software developments for the operation and validation of the Global Trigger will also be discussed.

  17. A FPGA Implementation of JPEG Baseline Encoder for Wearable Devices.

    PubMed

    Li, Yuecheng; Jia, Wenyan; Luan, Bo; Mao, Zhi-Hong; Zhang, Hong; Sun, Mingui

    2015-04-01

    In this paper, an efficient field-programmable gate array (FPGA) implementation of the JPEG baseline image compression encoder is presented for wearable devices in health and wellness applications. In order to gain flexibility in developing FPGA-specific software and balance between real-time performance and resources utilization, A High Level Synthesis (HLS) tool is utilized in our system design. An optimized dataflow configuration with a padding scheme simplifies the timing control for data transfer. Our experiments with a system-on-chip multi-sensor system have verified our FPGA implementation with respect to real-time performance, computational efficiency, and FPGA resource utilization.

  18. Muon reconstruction and selection at the last trigger level of the ATLAS experiment

    NASA Astrophysics Data System (ADS)

    Crupi, R.

    2010-04-01

    The three-level Trigger and DAQ system of ATLAS is designed to be very selective while preserving the full physics potential of the experiment; out of the ~1 GHz of p-p interactions provided by the LHC at nominal operating conditions, ~200 events/sec are retained. This paper focuses on the muon reconstruction and selection algorithms employed at the last trigger level. One implements an "outside-in" approach; it starts from a reconstruction in the Muon Spectrometer (MS) and performs a backward extrapolation to the interaction point and track combination in the Inner Detector (ID). The other implements an "inside-out" strategy; it starts muon reconstruction from the ID and extrapolates tracks to MS. Algorithm implementations and results on data from real cosmic rays and simulated collisions are described.

  19. Status of the Level 0 Trigger Processor of the NA62 Liquid Krypton Electromagnetic Calorimeter

    NASA Astrophysics Data System (ADS)

    Bonaiuto, V.; de Simone, N.; Federici, L.; Sargeni, F.; Badoni, D.; Fucci, A.; Paoluzzi, G.; Salamon, A.; Salina, G.; Santovetti, E.; Checcucci, B.; Papi, A.; Piccini, M.; Bizzarri, M.; Venditti, S.

    2014-06-01

    The NA62 experiment at the CERN SPS aims to measure the Branching Ratio of the ultra-rare decay K^+ rightarrow π^+νbarν, collecting about 100 events in two years of data taking with a signal to background ratio of 10:1. A hermetic photon veto system has been designed to efficiently reject the π0 background, one of the main background sources, and the 20-ton liquid krypton calorimeter is a fundamental component of such system in the angular acceptance region 1-10 mrad. In this paper, we present the design of the Level 0 trigger processor that is able to identify electromagnetic clusters in the calorimeter providing information on time, position and energy reconstruction for each cluster. In particular, it is composed of 36 readout boards (TEL62), organized in a three layer parallel system, 108 mezzanines and 215 high-performance FPGAs. The system has been designed to sustain an instantaneous hit rate of 40 MHz, to process data with a latency of about 100 μs, and to achieve a time resolution of 1.5 ns on the single cluster. Performance and functionality test results of a trigger slice, together with an updated status report of the whole level 0 trigger project, will be presented.

  20. Dynamic triggering

    USGS Publications Warehouse

    Hill, David P.; Prejean, Stephanie; Schubert, Gerald

    2015-01-01

    Dynamic stresses propagating as seismic waves from large earthquakes trigger a spectrum of responses at global distances. In addition to locally triggered earthquakes in a variety of tectonic environments, dynamic stresses trigger tectonic (nonvolcanic) tremor in the brittle–plastic transition zone along major plate-boundary faults, activity changes in hydrothermal and volcanic systems, and, in hydrologic domains, changes in spring discharge, water well levels, soil liquefaction, and the eruption of mud volcanoes. Surface waves with periods of 15–200 s are the most effective triggering agents; body-wave trigger is less frequent. Triggering dynamic stresses can be < 1 kPa.

  1. Central FPGA-based destination and load control in the LHCb MHz event readout

    NASA Astrophysics Data System (ADS)

    Jacobsson, R.

    2012-10-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  2. Public Key FPGA Software

    SciTech Connect

    Hymel, Ross

    2013-07-25

    The Public Key (PK) FPGA software performs asymmetric authentication using the 163-bit Elliptic Curve Digital Signature Algorithm (ECDSA) on an embedded FPGA platform. A digital signature is created on user-supplied data, and communication with a host system is performed via a Serial Peripheral Interface (SPI) bus. Software includes all components necessary for signing, including custom random number generator for key creation and SHA-256 for data hashing.

  3. Electrons and photons at High Level Trigger in CMS for Run II

    NASA Astrophysics Data System (ADS)

    Anuar, Afiq A.

    2015-12-01

    The CMS experiment has been designed with a 2-level trigger system. The first level is implemented using custom-designed electronics. The second level is the so-called High Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. For Run II of the Large Hadron Collider, the increase in center-of-mass energy and luminosity will raise the event rate to a level challenging for the HLT algorithms. New approaches have been studied to keep the HLT output rate manageable while maintaining thresholds low enough to cover physics analyses. The strategy mainly relies on porting online the ingredients that have been successfully applied in the offline reconstruction, thus allowing to move HLT selection closer to offline cuts. Improvements in HLT electron and photon definitions will be presented, focusing in particular on: updated clustering algorithm and the energy calibration procedure, new Particle-Flow-based isolation approach and pileup mitigation techniques, and the electron-dedicated track fitting algorithm based on Gaussian Sum Filter.

  4. GPU real-time processing in NA62 trigger system

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Chiozzi, S.; Cretaro, P.; Di Lorenzo, S.; Fantechi, R.; Fiorini, M.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P. S.; Pastorelli, E.; Piandani, R.; Piccini, M.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.; Vicini, P.

    2017-01-01

    A commercial Graphics Processing Unit (GPU) is used to build a fast Level 0 (L0) trigger system tested parasitically with the TDAQ (Trigger and Data Acquisition systems) of the NA62 experiment at CERN. In particular, the parallel computing power of the GPU is exploited to perform real-time fitting in the Ring Imaging CHerenkov (RICH) detector. Direct GPU communication using a FPGA-based board has been used to reduce the data transmission latency. The performance of the system for multi-ring reconstrunction obtained during the NA62 physics run will be presented.

  5. Drought-Trigger Ground-Water Levels in Chester County, Pennsylvania, for the Period of Record Ending May 2006

    USGS Publications Warehouse

    Cinotto, Peter J.

    2007-01-01

    This report presents the results of a study by the U.S. Geological Survey (USGS), in cooperation with the Chester County Water Resources Authority (CCWRA), to update the drought-trigger water levels for the Chester County observation-well network. The Chester County observation-well network was established in 1973 through a cooperative agreement between the CCWRA and the USGS to monitor local ground-water levels and trends and to determine drought conditions. In 1990 and again in 1997, drought-warning and drought-emergency water-level triggers were determined for the majority of wells in the existing Chester County observation-well network of 23 wells. Since 1997, the Chester County observation-well network expanded to 29 wells, some of the original wells were destroyed, and additional monthly water-level observations were made to allow for better statistical relations. Because of these changes, new statistics for water-level triggers were required. For this study, 19 of the 29 wells in the observation-well network were used to compute drought-trigger water levels. An additional 'drought-watch water-level trigger' category was developed to make the Chester County drought-trigger water-level categories consistent with those implemented by the Pennsylvania Department of Environmental Protection (PaDEP). The three drought-trigger water-level categories, as defined by PaDEP are 1) 'drought watch' when at the 75th-percentile level; 2) 'drought warning' when at the 90th-percentile level; and 3) 'drought emergency' when at the 95th-percentile level. A revised methodology, resulting from longer periods of record representing ground-water and climatic conditions and changes in local water use, has resulted in some observed differences in drought-trigger water levels. A comparison of current drought-trigger water levels to those calculated in 1997 shows the largest mean annual change in percentile values was in northeastern Chester County. In this northeastern region, the

  6. The upgrade of the PreProcessor system of the ATLAS level-1 calorimeter trigger

    NASA Astrophysics Data System (ADS)

    Andrei, V.; Hanke, P.; Jongmanns, J.; Khomich, A.; Meier, K.; Schmitt, K.; Schultz-Coulon, H.-C.; Stamen, R.; Stock, P.; Wessels, M.

    2012-12-01

    The ATLAS Level-1 Calorimeter Trigger is a pipelined system to identify high-pT objects and to build energy sums within a fixed latency of ~ 2 μs. It consists of a PreProcessor, which conditions and digitises analogue calorimeter signals, and two object-finding processors. The PreProcessor's tasks are implemented on a Multi-Chip Module, holding ADCs, time-adjustment and digital processing ASICs, and LVDS serialisers. A pin-compatible substitute, based on today's technology, like dual-channel ADCs and FPGAs, has been built to improve the BCID and pedestal subtraction algorithms. Test results with the first prototype are presented.

  7. Readout, first- and second-level triggers of the new Belle silicon vertex detector

    NASA Astrophysics Data System (ADS)

    Friedl, M.; Abe, R.; Abe, T.; Aihara, H.; Asano, Y.; Aso, T.; Bakich, A.; Browder, T.; Chang, M. C.; Chao, Y.; Chen, K. F.; Chidzik, S.; Dalseno, J.; Dowd, R.; Dragic, J.; Everton, C. W.; Fernholz, R.; Fujii, H.; Gao, Z. W.; Gordon, A.; Guo, Y. N.; Haba, J.; Hara, K.; Hara, T.; Harada, Y.; Haruyama, T.; Hasuko, K.; Hayashi, K.; Hazumi, M.; Heenan, E. M.; Higuchi, T.; Hirai, H.; Hitomi, N.; Igarashi, A.; Igarashi, Y.; Ikeda, H.; Ishino, H.; Itoh, K.; Iwaida, S.; Kaneko, J.; Kapusta, P.; Karawatzki, R.; Kasami, K.; Kawai, H.; Kawasaki, T.; Kibayashi, A.; Koike, S.; Korpar, S.; Križan, P.; Kurashiro, H.; Kusaka, A.; Lesiak, T.; Limosani, A.; Lin, W. C.; Marlow, D.; Matsumoto, H.; Mikami, Y.; Miyake, H.; Moloney, G. R.; Mori, T.; Nakadaira, T.; Nakano, Y.; Natkaniec, Z.; Nozaki, S.; Ohkubo, R.; Ohno, F.; Okuno, S.; Onuki, Y.; Ostrowicz, W.; Ozaki, H.; Peak, L.; Pernicka, M.; Rosen, M.; Rozanska, M.; Sato, N.; Schmid, S.; Shibata, T.; Stamen, R.; Stanič, S.; Steininger, H.; Sumisawa, K.; Suzuki, J.; Tajima, H.; Tajima, O.; Takahashi, K.; Takasaki, F.; Tamura, N.; Tanaka, M.; Taylor, G. N.; Terazaki, H.; Tomura, T.; Trabelsi, K.; Trischuk, W.; Tsuboyama, T.; Uchida, K.; Ueno, K.; Ueno, K.; Uozaki, N.; Ushiroda, Y.; Vahsen, S.; Varner, G.; Varvell, K.; Velikzhanin, Y. S.; Wang, C. C.; Wang, M. Z.; Watanabe, M.; Watanabe, Y.; Yamada, Y.; Yamamoto, H.; Yamashita, Y.; Yamashita, Y.; Yamauchi, M.; Yanai, H.; Yang, R.; Yasu, Y.; Yokoyama, M.; Ziegler, T.; Žontar, D.

    2004-12-01

    A major upgrade of the Silicon Vertex Detector (SVD 2.0) of the Belle experiment at the KEKB factory was installed along with new front-end and back-end electronics systems during the summer shutdown period in 2003 to cope with higher particle rates, improve the track resolution and meet the increasing requirements of radiation tolerance. The SVD 2.0 detector modules are read out by VA1TA chips which provide "fast or" (hit) signals that are combined by the back-end FADCTF modules to coarse, but immediate level 0 track trigger signals at rates of several tens of a kHz. Moreover, the digitized detector signals are compared to threshold lookup tables in the FADCTFs to pass on hit information on a single strip basis to the subsequent level 1.5 trigger system, which reduces the rate below the kHz range. Both FADCTF and level 1.5 electronics make use of parallel real-time processing in Field Programmable Gate Arrays (FPGAs), while further data acquisition and event building is done by PC farms running Linux. The new readout system hardware is described and the first results obtained with cosmics are shown.

  8. Analysis on current limiting characteristics of a transformer type SFCL with two triggering current levels

    NASA Astrophysics Data System (ADS)

    Lim, Sung-Hun; Ko, Seckcheol; Han, Tae-Hee

    2013-01-01

    In this paper, the transformer type superconducting fault current limiter (SFCL) with two triggering current levels was suggested and its current limiting characteristics were analyzed. The structure of the suggested transformer type SFCL with two triggering current levels largely consists of two parts. One is the transformer with two magnetically coupled coils, which correspond to the primary winding and the secondary one connected with one high-TC superconducting (HTSC) element. The other is third coil, or, another secondary winding with one HTSC element, which is wound on the same iron core together with two coils. This suggested transformer type SFCL can limit the fault current by generating its limiting impedance with two different amplitudes, which are dependent on the initial amplitude of the fault current in case of the fault occurrence. To confirm the usefulness of the proposed SFCL, the current limiting tests of the SFCL according to the fault angle, one of the effective fault conditions to affect the amplitude of the initial fault current, were carried out and its effective limiting operations were discussed.

  9. ADC and TDC implemented using FPGA

    SciTech Connect

    Wu, Jinyuan; Hansen, Sten; Shi, Zonghan; /Fermilab

    2007-11-01

    Several tests of FPGA devices programmed as analog waveform digitizers are discussed. The ADC uses the ramping-comparing scheme. A multi-channel ADC can be implemented with only a few resistors and capacitors as external components. A periodic logic levels are shaped by passive RC network to generate exponential ramps. The FPGA differential input buffers are used as comparators to compare the ramps with the input signals. The times at which these ramps cross the input signals are digitized by time-to-digital-converters (TDCs) implemented within the FPGA. The TDC portion of the logic alone has potentially a broad range of HEP/nuclear science applications. A 96-channel TDC card using FPGAs as TDCs being designed for the Fermilab MIPP electronics upgrade project is discussed. A deserializer circuit based on multisampling circuit used in the TDC, the 'Digital Phase Follower' (DPF) is also documented.

  10. Harmonic analysis and FPGA implementation of SHE controlled three phase CHB 11-level inverter in MV drives using deterministic and stochastic optimization techniques.

    PubMed

    Vesapogu, Joshi Manohar; Peddakotla, Sujatha; Kuppa, Seetha Rama Anjaneyulu

    2013-01-01

    With the advancements in semiconductor technology, high power medium voltage (MV) Drives are extensively used in numerous industrial applications. Challenging technical requirements of MV Drives is to control multilevel inverter (MLI) with less Total harmonic distortion (%THD) which satisfies IEEE standard 519-1992 harmonic guidelines and less switching losses. Among all modulation control strategies for MLI, Selective harmonic elimination (SHE) technique is one of the traditionally preferred modulation control technique at fundamental switching frequency with better harmonic profile. On the other hand, the equations which are formed by SHE technique are highly non-linear in nature, may exist multiple, single or even no solution at particular modulation index (MI). However, in some MV Drive applications, it is required to operate over a range of MI. Providing analytical solutions for SHE equations during the whole range of MI from 0 to 1, has been a challenging task for researchers. In this paper, an attempt is made to solve SHE equations by using deterministic and stochastic optimization methods and comparative harmonic analysis has been carried out. An effective algorithm which minimizes %THD with less computational effort among all optimization algorithms has been presented. To validate the effectiveness of proposed MPSO technique, an experiment is carried out on a low power proto type of three phase CHB 11- level Inverter using FPGA based Xilinx's Spartan -3A DSP Controller. The experimental results proved that MPSO technique has successfully solved SHE equations over all range of MI from 0 to 1, the %THD obtained over major range of MI also satisfies IEEE 519-1992 harmonic guidelines too.

  11. Development of High Level Trigger Software for Belle II at SuperKEKB

    NASA Astrophysics Data System (ADS)

    Lee, S.; Itoh, R.; Katayama, N.; Mineo, S.

    2011-12-01

    The Belle collaboration has been trying for 10 years to reveal the mystery of the current matter-dominated universe. However, much more statistics is required to search for New Physics through quantum loops in decays of B mesons. In order to increase the experimental sensitivity, the next generation B-factory, SuperKEKB, is planned. The design luminosity of SuperKEKB is 8 x 1035cm-2s-1 a factor 40 above KEKB's peak luminosity. At this high luminosity, the level 1 trigger of the Belle II experiment will stream events of 300 kB size at a 30 kHz rate. To reduce the data flow to a manageable level, a high-level trigger (HLT) is needed, which will be implemented using the full offline reconstruction on a large scale PC farm. There, physics level event selection is performed, reducing the event rate by ~ 10 to a few kHz. To execute the reconstruction the HLT uses the offline event processing framework basf2, which has parallel processing capabilities used for multi-core processing and PC clusters. The event data handling in the HLT is totally object oriented utilizing ROOT I/O with a new method of object passing over the UNIX socket connection. Also under consideration is the use of the HLT output as well to reduce the pixel detector event size by only saving hits associated with a track, resulting in an additional data reduction of ~ 100 for the pixel detector. In this contribution, the design and implementation of the Belle II HLT are presented together with a report of preliminary testing results.

  12. Ground-level observation of a terrestrial gamma ray flash initiated by a triggered lightning

    NASA Astrophysics Data System (ADS)

    Hare, B. M.; Uman, M. A.; Dwyer, J. R.; Jordan, D. M.; Biggerstaff, M. I.; Caicedo, J. A.; Carvalho, F. L.; Wilkes, R. A.; Kotovsky, D. A.; Gamerota, W. R.; Pilkey, J. T.; Ngin, T. K.; Moore, R. C.; Rassoul, H. K.; Cummer, S. A.; Grove, J. E.; Nag, A.; Betten, D. P.; Bozarth, A.

    2016-06-01

    We report on a terrestrial gamma ray flash (TGF) that occurred on 15 August 2014 coincident with an altitude-triggered lightning at the International Center for Lightning Research and Testing (ICLRT) in North Central Florida. The TGF was observed by a ground-level network of gamma ray, close electric field, distant magnetic field, Lightning Mapping Array (LMA), optical, and radar measurements. Simultaneous gamma ray and LMA data indicate that the upward positive leader of the triggered lightning flash induced relativistic runaway electron avalanches when the leader tip was at about 3.5 km altitude, resulting in the observed TGF. Channel luminosity and electric field data show that there was an initial continuous current (ICC) pulse in the lightning channel to ground during the time of the TGF. Modeling of the observed ICC pulse electric fields measured at close range (100-200 m) indicates that the ICC pulse current had both a slow and fast component (full widths at half maximum of 235 μs and 59 μs) and that the fast component was more or less coincident with the TGF, suggesting a physical association between the relativistic runaway electron avalanches and the ICC pulse observed at ground. Our ICC pulse model reproduces moderately well the measured close electric fields at the ICLRT as well as three independent magnetic field measurements made about 250 km away. Radar and LMA data suggest that there was negative charge near the region in which the TGF was initiated.

  13. Results from the first p+p runs of the ALICE High Level Trigger at LHC

    NASA Astrophysics Data System (ADS)

    Kanaki, Kalliopi; ALICE HLT Collaboration

    2011-12-01

    The High Level Trigger for the ALICE experiment at LHC is a powerful, sophisticated tool aimed at compressing the raw data volume and issuing selective triggers for events with desirable physics content. At its current state it integrates information from all major ALICE detectors, i. e. the inner tracking system, the time projection chamber, the electromagnetic calorimeters, the transition radiation detector and the muon spectrometer performing real-time event reconstruction. The steam engine behind HLT is a high performance computing cluster of several hundred nodes. It has to reduce the data rate from 25 GB/s to 1.25 GB/s for fitting the DAQ mass storage bandwidth. The cluster is served by a full GigaBit Ethernet network, in addition to an InfiniBand backbone network. To cope with the great challenge of Pb+Pb collisions in autumn 2010, its performance capabilities are being enhanced with the addition of new nodes. Towards the same end the first GPU co-processors are in place. During the first period of data taking with p+p collisions the HLT was extensively used to reconstruct, analyze and display data from the various participating detectors. Among other tasks it contributed to the monitoring of the detector performance, selected events for their calibration and efficiency studies, and estimated primary and secondary vertices from p+p collisions identifying V0 topologies. The experience gained during these first months of online operation will be presented.

  14. Low level laser therapy with trigger points technique: a clinical study on 243 patients.

    PubMed

    Simunovic, Z

    1996-08-01

    Among the various methods of application techniques in low level laser therapy (LLLT) (HeNe 632.8 nm visible red or infrared 820-830 nm continuous wave and 904 nm pulsed emission) there are very promising "trigger points" (TPs), i.e., myofascial zones of particular sensibility and of highest projection of focal pain points, due to ischemic conditions. The effect of LLLT and the results obtained after clinical treatment of more than 200 patients (headaches and facial pain, skeletomuscular ailments, myogenic neck pain, shoulder and arm pain, epicondylitis humery, tenosynovitis, low back and radicular pain, Achilles tendinitis) to whom the "trigger points" were applied were better than we had ever expected. According to clinical parameters, it has been observed that the rigidity decreases, the mobility is restored (functional recovery), and the spontaneous or induced pain decreases or even disappears, by movement, too. LLLT improves local microcirculation and it can also improve oxygen supply to hypoxic cells in the TP areas and at the same time it can remove the collected waste products. The normalization of the microcirculation, obtained due to laser applications, interrupts the "circulus vitiosus" of the origin of the pain and its development (Melzak: muscular tension > pain > increased tension > increased pain, etc.). Results measured according to VAS/VRS/PTM: in acute pain, diminished more than 70%; in chronic pain more than 60%. Clinical effectiveness (success or failure) depends on the correctly applied energy dose--over/underdosage produces opposite, negative effects on cellular metabolism. We did not observe any negative effects on the human body and the use of analgesic drugs could be reduced or completely excluded. LLLT suggests that the laser beam can be used as monotherapy or as a supplementary treatment to other therapeutic procedures for pain treatment.

  15. FPGA based control system for space instrumentation

    NASA Astrophysics Data System (ADS)

    Di Giorgio, Anna M.; Cerulli Irelli, Pasquale; Nuzzolo, Francesco; Orfei, Renato; Spinoglio, Luigi; Liu, Giovanni S.; Saraceno, Paolo

    2008-07-01

    The prototype for a general purpose FPGA based control system for space instrumentation is presented, with particular attention to the instrument control application software. The system HW is based on the LEON3FT processor, which gives the flexibility to configure the chip with only the necessary HW functionalities, from simple logic up to small dedicated processors. The instrument control SW is developed in ANSI C and for time critical (<10μs) commanding sequences implements an internal instructions sequencer, triggered via an interrupt service routine based on a HW high priority interrupt.

  16. Periovulatory follicular fluid levels of estradiol trigger inflammatory and DNA damage responses in oviduct epithelial cells

    PubMed Central

    Palma-Vera, Sergio E.; Schoen, Jennifer; Chen, Shuai

    2017-01-01

    Objective Ovarian steroid hormones (mainly E2 and P4) regulate oviduct physiology. Serum-E2 acts on the oviduct epithelium from the basolateral cell compartment. Upon ovulation, the apical compartment of the oviduct epithelium is temporarily exposed to follicular fluid, which contains much higher levels of E2 than serum. The aim of this study was to evaluate the effects of human periovulatory follicular fluid levels of E2 on oviduct epithelial cells using two porcine in vitro models. Methods A cell line derived from the porcine oviductal epithelium (CCLV-RIE270) was characterized (lineage markers, proliferation characteristics and transformation status). Primary porcine oviduct epithelial cells (POEC) were cultured in air-liquid interface and differentiation was assessed histologically. Both cultures were exposed to E2 (10 ng/ml and 200 ng/ml). Proliferation of CCLV-RIE270 and POEC was determined by real-time impedance monitoring and immunohistochemical detection of Ki67. Furthermore, marker gene expression for DNA damage response (DDR) and inflammation was quantified. Results CCLV-RIE270 was not transformed and exhibited properties of secretory oviduct epithelial cells. Periovulatory follicular fluid levels of E2 (200 ng/ml) upregulated the expression of inflammatory genes in CCLV-RIE270 but not in POEC (except for IL8). Expression of DDR genes was elevated in both models. A significant increase in cell proliferation could not be detected in response to E2. Conclusions CCLV-RIE270 and POEC are complementary models to evaluate the consequences of oviduct exposure to follicular fluid components. Single administration of periovulatory follicular fluid E2 levels trigger inflammatory and DNA damage responses, but not proliferation in oviduct epithelial cells. PMID:28231273

  17. Commodity multi-processor systems in the ATLAS level-2 trigger

    SciTech Connect

    Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

    2000-05-23

    Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems.

  18. Level rise episodes triggered by volcanic eruptions during the desiccation of Lake Lisan

    NASA Astrophysics Data System (ADS)

    Bookman, R.; Filin, S.; Avni, Y.; Marco, S.

    2012-12-01

    The June 1991 Pinatubo volcanic eruption perturbed the atmosphere, triggering short-term worldwide changes in surface and lower troposphere temperatures, precipitation, and runoff. The following winter was anomalously wet in the Levant, with a ~2-meter increase in the Dead Sea level that created a distinct morphological terrace along the lake's shore. Given the global radiative and chemical effects of volcanogenic aerosols on climatic systems, we tested the hypothesis that the 1991-92 winter shore terrace is a modern analogue to the linkage between past volcanic eruptions and a sequence of shore terraces on the cliffs around the Dead Sea Basin (DSB). Sixteen shore terraces, detected using airborne laser scanning data, were interpreted as indicating short-term level rises due to episodes of enhanced precipitation and runoff during the drop in Lake Lisan's (palaeo-Dead Sea) level at the end of the Last Glacial Maximum. The terraces were compared with a dated time series of volcanigenic sulfate from the GISP2 ice core, and similar numbers of sulfate peaks and shore terraces were found with significant correlation (R2=0.8) between the SO4 concentration and the physical and hydrological character of the terraces. We suggest that this correlation indicates a link between the explosivity of past eruptions, the magnitude of stratographic injection, and their impact on the northern hemisphere water balance. The record of such short-term climato-hydrological effects is made possible by the dramatic desiccation of Lake Lisan and may show the amplification of the volcanic atmospheric perturbation during the main climatic transition at the end of the Last Glacial Maximum. Detailed records of such events, albeit rare because of their vulnerability and short longevity, provide an important demonstration of global climatic teleconnections.

  19. Online Reconstruction and Calibration with Feedback Loop in the ALICE High Level Trigger

    NASA Astrophysics Data System (ADS)

    Rohr, David; Shahoyan, Ruben; Zampolli, Chiara; Krzewicki, Mikolaj; Wiechula, Jens; Gorbunov, Sergey; Chauvin, Alex; Schweda, Kai; Lindenstruth, Volker

    2016-11-01

    ALICE (A Large Heavy Ion Experiment) is one of the four large scale experiments at the Large Hadron Collider (LHC) at CERN. The High Level Trigger (HLT) is an online computing farm, which reconstructs events recorded by the ALICE detector in real-time. The most computing-intensive task is the reconstruction of the particle trajectories. The main tracking devices in ALICE are the Time Projection Chamber (TPC) and the Inner Tracking System (ITS). The HLT uses a fast GPU-accelerated algorithm for the TPC tracking based on the Cellular Automaton principle and the Kalman filter. ALICE employs gaseous subdetectors which are sensitive to environmental conditions such as ambient pressure and temperature and the TPC is one of these. A precise reconstruction of particle trajectories requires the calibration of these detectors. As our first topic, we present some recent optimizations to our GPU-based TPC tracking using the new GPU models we employ for the ongoing and upcoming data taking period at LHC. We also show our new approach to fast ITS standalone tracking. As our second topic, we present improvements to the HLT for facilitating online reconstruction including a new flat data model and a new data flow chain. The calibration output is fed back to the reconstruction components of the HLT via a feedback loop. We conclude with an analysis of a first online calibration test under real conditions during the Pb-Pb run in November 2015, which was based on these new features.

  20. FPGA Vision Data Architecture

    NASA Technical Reports Server (NTRS)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  1. From OO to FPGA :

    SciTech Connect

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  2. Graphical processors for HEP trigger systems

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Chiozzi, S.; Cotta Ramusino, A.; Di Lorenzo, S.; Fantechi, R.; Fiorini, M.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P. S.; Pastorelli, E.; Piandani, R.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.; Vicini, P.

    2017-02-01

    General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.

  3. Mapping Parameterized Dataflow Graphs onto FPGA Platforms (Preprint)

    DTIC Science & Technology

    2014-02-01

    realize the potential of dynamic reconfiguration technology . In this paper, we provide background on relevant methods for application mod- eling, and...model [57] into processes for FPGA mapping of dynamically reconfigurable sig- nal processing systems. 2. Background 2.1. FPGA Technology As shown in...memories, special purpose hardware subsystems (e.g., multipliers or higher level signal processing accelerators), and embedded processor cores. A ring

  4. FPGA-Based Pulse Parameter Discovery for Positron Emission Tomography.

    PubMed

    Haselman, Michael; Hauck, Scott; Lewellen, Thomas K; Miyaoka, Robert S

    2009-10-24

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex digital signal processing algorithms with clock rates well above 100MHz. This, combined with FPGA's low expense and ease of use make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a series of high-resolution, small-animal PET scanners that utilize FPGAs as the core of the front-end electronics. For these next generation scanners, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report how we utilize the reconfigurable property of an FPGA to self-calibrate itself to determine pulse parameters necessary for some of the pulse processing steps. Specifically, we show how the FPGA can generate a reference pulse based on actual pulse data instead of a model. We also report how other properties of the photodetector pulse (baseline, pulse length, average pulse energy and event triggers) can be determined automatically by the FPGA.

  5. The rocket-and-wire triggering process: Channel-base currents and ground-level electric fields

    NASA Astrophysics Data System (ADS)

    Ngin, Terry Keo

    Rocket-and-wire triggered lightning flashes were studied from 2011 to 2013 at the International Center for Lightning Research and Testing. Ground-level electric fields and channel-base currents were recorded for 79 rocket launches. An eight-station network of electric field meters along with a milliampere-scale wire-base current measurement and a high-speed video record of the wire ascent allowed the calculation and analysis of the trigger-wire line charge density, generally found to be in the muC m-1 to hundreds of muC m-1 range and to increase quadratically with height. The wire-base currents collected during the wire ascent here are the most comprehensive in the literature to date. The trigger-wire line charge density, electric field at ground level, and characteristics of precursor pulses at the wire tip were examined to determine their usefulness in predicting the success or failure of a triggered-lightning attempt. The usefulness of the PICASSO model of space charge evolution from ground, originally developed by researchers at Paul Sabatier University in the 1980s, as a triggering criterion was also evaluated. An electrostatic model of the corona sheath around the trigger-wire was developed in order to estimate the radial extent of the corona sheath and the charge distribution within the corona sheath as a function of measured electric fields aloft taken from the published literature. The most sensitive measurements to date of channel-base current flowing prior to subsequent return strokes, where the current had generally been considered to be zero, were collected and are analyzed here. The channel-base current before return strokes was found to average 5.3 mA with a 2.8 mA standard deviation prior to 120 measured return strokes.

  6. The use of content addressable memories in the level 2 trigger for the CLAS detector at CEBAF

    SciTech Connect

    Doughty, D.C. Jr.; Hodson, R.F.; Allgood, D.; Bickley, M.; Campbell, S.; Putnam, T.; Spivak, R.; Lemon, S.; Wilson, W.C.

    1996-02-01

    The LEVEL 2 trigger in the CLAS detector will find tracks and associate a momentum and angle with each track within 2 {micro}s after the event. This is done through a hierarchical track finding design in which track segments are found in each drift chamber axial superlayer. An array of 384 custom content addressable (or associative) memories (CAMs) uses independent subfield matching to link these track segments into roads. The track parameters corresponding to each found road are then looked up in a separate memory. The authors present the overall architecture of the LEVEL 2 trigger, the details of how the CAM chip links tracks segments to find roads, and report on the performance of the prototype CAM chips.

  7. Predicting Trigger Level for Ice Jam Flooding of the lower Mohawk River using LiDAR and GIS

    NASA Astrophysics Data System (ADS)

    Foster, J.; Marsellos, A.; Garver, J.

    2011-12-01

    Ice jams are an annual occurrence along the Mohawk River in upstate New York. The jams commonly result in significant flooding especially when the progress of the ice is impeded by obstructions to the channel and flood plain. To minimize flooding hazards it is critical to know the trigger level of flooding so that we can better understand chronic jam points and simulate flooding events as jams occur as the lower Mohawk. A better understanding of jamming and trigger points may facilitate measures to reduce flooding and avoid the costly damage associated with these hazards. To determine the flood trigger level for one segment of the lower Mohawk we used Air-LiDAR elevation data to construct a digital elevation model to simulate a flooding event. The water flood simulation using a LiDAR elevation model allows accurate water level measurements for determining trigger levels of ice dam flooding. The study area comprises three sections of the lower Mohawk River from the (Before location) to the (After location), which are constrained by lock stations centered at the New York State Canal System Lock 9 (E9 Lock) and the B&M Rail Bridge at the Schenectady International (SI) Plant. This area is notorious for ice jams including one that resulted in a major flooding event on January 25th, 2010 which resulted in flood levels at 74.4 m in the upper portion of the second section of the study area (Lock 9) and at 73.4 m in the lower portion (SI plant). Minimum and maximum elevation levels were found to determine the values at which up stream water builds up and when flooding occurs. From these values, we are able to predict the flooding as the ice jam builds up and breaks as it progresses downstream. Similar methodology is applied to find the trigger points for flooding along other sections of the Mohawk River constrained by lock stations, and it may provide critical knowledge as to how to better manage the hazard of flooding due to ice jams.

  8. FPGA Boot Loader and Scrubber

    NASA Technical Reports Server (NTRS)

    Wade, Randall S.; Jones, Bailey

    2009-01-01

    A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

  9. The FPGA based L1 track finding Tracklet approach

    NASA Astrophysics Data System (ADS)

    Kyriacou, Savvas; CMS Collaboration

    2017-01-01

    The High Luminosity upgraded LHC is expected to deliver proton-proton collisions per 25ns with an estimated 140-200 pile up interactions per bunch crossing. Ultrafast track finding is vital for handling trigger rates in such conditions. An FPGA based road search algorithm is developed, the Tracklet approach one of a few currently under consideration, for the CMS L1 trigger system. Based on low/high transverse momentum track discrimination and designed for the HL upgraded outer tracker, the algorithm achieves microsecond scale track reconstruction in the expected high track multiplicity environment. The Tracklet method overview, implementation, hardware demonstrator and performance results are presented and discussed.

  10. Digital electronics for the inclusion of shower max and preshower wire data in the CDF second-level trigger

    SciTech Connect

    Dawson, J.W.; Byrum, K.L.; Haberichter, W.N.; Nodulman, L.J.; Wicklund, A.B.; Turner, K.J.; Gerdes, D.W.

    1993-07-01

    As part of the upgrade program at CDF, electronics has been built to bring the shower max (CES) and preshower (CPR) data into the trigger at level 2. After each crossing, 384 bits from shower max and 192 from the preshower wires are latched. Data from tracks are bussed to this module to provide the wire address and momentum which are then successively compared to the wire data in large look-up tables. Approximately 50 nanoseconds is required to determine a match, write the results in FIFO, and make the results available to track memory. Monte Carlo analysis has indicated that an increase in efficiency of a factor of three in triggering on b decays will be achieved with this hardware.

  11. Performance of Tracking, b-tagging and Jet/MET reconstruction at the CMS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Tosi, Mia

    2015-12-01

    The trigger systems of the LHC detectors play a crucial role in determining the physics capabilities of experiments. In 2015, the center-of-mass energy of proton-proton collisions will reach 13 TeV up to an unprecedented luminosity of 1 × 1034 cm-2s-1. A reduction of several orders of magnitude of the event rate is needed to reach values compatible with detector readout, offline storage and analysis capabilities. The CMS experiment has been designed with a two-level trigger system: the Level-1 Trigger (L1T), implemented on custom-designed electronics, and the High Level Trigger (HLT), a streamlined version of the offline reconstruction software running on a computer farm. A software trigger system requires a trade-off between the complexity of the algorithms, the sustainable output rate, and the selection efficiency. With the computing power available during the 2012 data taking the maximum reconstruction time at HLT was about 200 ms per event, at the nominal L1T rate of 100 kHz. Tracking algorithms are widely used in the HLT in the object reconstruction through particle-flow techniques as well as in the identification of b-jets and lepton isolation. Reconstructed tracks are also used to distinguish the primary vertex, which identifies the hard interaction process, from the pileup ones. This task is particularly important in the LHC environment given the large number of interactions per bunch crossing: on average 25 in 2012, and expected to be around 40 in Run II with a large contribution from out-of-time particles. In order to cope with tougher conditions the tracking and vertexing techniques used in 2012 have been largely improved in terms of timing and efficiency in order to keep the physics reach at the level of Run I conditions. We will present the performance of these newly developed algorithms, discussing their impact on the b-tagging performances as well as on the jet and missing transverse energy reconstruction.

  12. The trigger system of the JEM-EUSO Project

    NASA Astrophysics Data System (ADS)

    Bertaina, M.; Ebisuzaki, T.; Hamada, T.; Ikeda, H.; Kawasai, Y.; Sawabe, T.; Takahashi, Y.; JEM-EUSO Collaboration

    The trigger system of JEM-EUSO should face different major challenging points: a) cope with the limited down-link transmission rate from the ISS to Earth, by operating a severe on-board and on-time data reduction; b) use very fast, low power consuming and radiation hard electronics; c) have a high signal-over-noise performance and flexibility in order to lower as much as possible the energy threshold of the detector, adjust the system to a variable nightglow background, and trigger on different categories of events (images insisting on the same pixels or crossing huge portions of the entire focal surface). Based on the above stringent requirements, the main ingredients for the trigger logic are: the Gate Time Unit (GTU); the minimum number Nthresh of photo-electrons piling up in a GTU in a pixel to be fired; the persistency level Npers, in which fired pixels are over threshold; the localization and correlation in space and time of the fired pixels, that distinguish a real EAS from an accidental background enhancement. The core of the trigger logic is the Track Trigger Algorithm that has been specifically developed for this purpose. Its characteristics, preliminary performance and its possible implementation on FPGA or DSP will be discussed together with a general overview of the architecture of the triggering system of JEM-EUSO.

  13. Impact of sea-level rise on earthquake and landslide triggering offshore the Alentejo margin (SW Iberia)

    NASA Astrophysics Data System (ADS)

    Neves, M. C.; Roque, C.; Luttrell, K. M.; Vázquez, J. T.; Alonso, B.

    2016-12-01

    Earthquakes and submarine landslides are recurrent and widespread manifestations of fault activity offshore SW Iberia. The present work tests the effects of sea-level rise on offshore fault systems using Coulomb stress change calculations across the Alentejo margin. Large-scale faults capable of generating large earthquakes and tsunamis in the region, especially NE-SW trending thrusts and WNW-ESE trending dextral strike-slip faults imaged at basement depths, are either blocked or unaffected by flexural effects related to sea-level changes. Large-magnitude earthquakes occurring along these structures may, therefore, be less frequent during periods of sea-level rise. In contrast, sea-level rise promotes shallow fault ruptures within the sedimentary sequence along the continental slope and upper rise within distances of <100 km from the coast. The results suggest that the occurrence of continental slope failures may either increase (if triggered by shallow fault ruptures) or decrease (if triggered by deep fault ruptures) as a result of sea-level rise. Moreover, observations of slope failures affecting the area of the Sines contourite drift highlight the role of sediment properties as preconditioning factors in this region.

  14. Triggering for Magnetic Field Measurements of the LCLS Undulators

    SciTech Connect

    Hacker, Kirsten

    2010-12-13

    A triggering system for magnetic field measurements of the LCLS undulators has been built with a National Instruments PXI-1002 and a Xylinx FPGA board. The system generates single triggers at specified positions, regardless of encoder sensor jitter about a linear scale.

  15. ENABLE -- A systolic 2nd level trigger processor for track finding and e/[pi] discrimination for ATLAS/LHC

    SciTech Connect

    Klefenz, F.; Noffz, K.H.; Zoz, R. . Lehrstuhl fuer Informatik V); Maenner, R. . Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen)

    1994-08-01

    The Enable Machine is a systolic 2nd level trigger processor for the transition radiation detector (TRD) of ATLAS/LHC. It is developed within the EAST/RD-11 collaboration at CERN. The task of the processor is to find electron tracks and to reject pion tracks according to the EAST benchmark algorithm in less than 10[mu]s. Track are identified by template matching in a ([psi],z) region of interest (RoI) selected by a 1st level trigger. In the ([psi],z) plane tracks of constant curvature are straight lines. The relevant lines form mask templates. Track identification is done by histogramming the coincidences of the templates and the RoI data for each possible track. The Enable Machine is an array processor that handles tracks of the same slope in parallel, and tracks of different slope in a pipeline. It is composed of two units, the Enable histogrammer unit and the Enable z/[psi]-board. The interface daughter board is equipped with a HIPPI-interface developed at JINR/-Dubna, and Xilinx 'corner turning' data converter chips. Enable uses programmable gate arrays (XILINX) for histogramming and synchronous SRAMs for pattern storage. With a clock rate of 40 MHz the trigger decision time is 6.5 [mu]s and the latency 7.0 [mu]s. The Enable machine is scalable in the RoI size as well as in the number of tracks processed. It can be adapted to different recognition tasks and detector setups. The prototype of the Enable Machine has been tested in a beam time of the RD6 collaboration at CERN in October 1993.

  16. Analysis on current limiting characteristics of a flux-lock type SFCL with two triggering current levels

    NASA Astrophysics Data System (ADS)

    Lim, S. H.

    2011-11-01

    In this paper, the flux-lock type superconducting fault current limiter (SFCL) with two triggering current levels was suggested and its current limiting characteristics were analyzed. The structure of the suggested flux-lock type SFCL with two triggering current levels largely consists of two parts. One is the flux-lock type SFCL with two magnetically coupled coils with series or parallel connection and one high-TC superconducting (HTSC) element, which is connected in series or parallel with one of two coils. The other is constructed in the third coil with another HTSC element. This suggested flux-lock type SFCL can limit the fault current by generating its limiting impedance with two different amplitudes, which are dependent on the initial amplitude of the fault current in case of the fault occurrence. To confirm the usefulness of the proposed SFCL, the limiting tests of the SFCL according to the fault angle, which is one of the effective fault conditions to affect the amplitude of the initial fault current, were carried out and its effective limiting operations were discussed.

  17. Correlation between serum ghrelin levels and cocaine-seeking behaviour triggered by cocaine-associated conditioned stimuli in rats.

    PubMed

    Tessari, Michela; Catalano, Antonio; Pellitteri, Michele; Di Francesco, Carla; Marini, Francesca; Gerrard, Philip A; Heidbreder, Christian A; Melotto, Sergio

    2007-03-01

    Ghrelin is a brain-gut peptide with growth hormone-releasing and appetite-inducing activities. A growing body of evidence suggests that ghrelin may affect the central reward system and modulate the activity of the mesolimbic system. Recent clinical studies also showed a significant positive correlation between plasma ghrelin levels and craving in alcoholics. Accordingly, the present study investigated the potential role of serum ghrelin levels in the reinstatement of cocaine-seeking behaviour triggered by cocaine-associated cues. In addition, serum corticosterone levels were determined in the light of evidence suggesting that corticosterone plays a modulatory role in cocaine-seeking behaviour. Male Lister Hooded rats under a restricted diet regime were first trained to intravenously self-administer cocaine under a fixed ratio-1 schedule of reinforcement. Conditioned stimuli (CS: tone and cue-light on for 5 seconds) were presented contingently with cocaine delivery. Once a stable baseline of cocaine self-administration was observed, lever presses were extinguished to less than 30% of baseline rates by removing both cocaine and CS. Reinstatement of responding was then induced by re-exposure to cocaine-associated CS. Blood samples for the enzyme immunoassay determination of serum ghrelin and the radioimmunoassay determination of serum corticosterone levels were collected 30 minutes before the beginning of reinstatement sessions. Rats significantly reinstated their responding when exposed to CS. A positive and significant correlation was observed between ghrelin levels (r = 0.64; P < 0.05), but not corticosterone (r = 0.37; NS), and the increased active lever presses only in animals exposed to CS. These findings suggest a potential role of ghrelin in the modulation of cue-triggered reinstatement of cocaine-seeking behaviour.

  18. Triggering for submaximal exercise level in gastric exercise tonometry: serial lactate, heart rate, or respiratory quotient?

    PubMed

    Otte, Johannes A; Oostveen, Ellie; Mensink, Peter B F; Geelkerken, Robert H; Kolkman, Jeroen J

    2007-08-01

    Gastric exercise tonometry is a functional diagnostic test in chronic gastrointestinal ischemia. As maximal exercise can cause false-positive tests, exercise buildup should be controlled to remain submaximal. We evaluated three parameters for monitoring and adjusting exercise levels (heart rate [HR], respiratory quotient [RQ], and serial lactate measurements) in 178 tests in both healthy volunteers and patients suspected of gastrointestinal ischemia. Exercise levels above submaximal occurred in 20% of HR-, 2% of RQ-, and 5% of lactate-monitored tests (P<0.05 for HR vs. RQ and lactate). Low levels were seen in 5% of HR-, 10% of RQ-, and 41% of lactate-monitored tests (P<0.01 for lactate vs. HR and RQ). High levels resulted in 43% false-positive tonometry results compared to 19% of all tests (P<0.001); low levels did not result in more false negatives (5% vs. 6%). Although RQ monitoring yielded the greatest proportion of optimal exercise tests, serial lactate monitoring is our method of choice, combining optimal diagnostic accuracy, low cost, and simplicity.

  19. Low oxygen levels as a trigger for enhancement of respiratory metabolism in Saccharomyces cerevisiae

    PubMed Central

    Rintala, Eija; Toivari, Mervi; Pitkänen, Juha-Pekka; Wiebe, Marilyn G; Ruohonen, Laura; Penttilä, Merja

    2009-01-01

    Background The industrially important yeast Saccharomyces cerevisiae is able to grow both in the presence and absence of oxygen. However, the regulation of its metabolism in conditions of intermediate oxygen availability is not well characterised. We assessed the effect of oxygen provision on the transcriptome and proteome of S. cerevisiae in glucose-limited chemostat cultivations in anaerobic and aerobic conditions, and with three intermediate (0.5, 1.0 and 2.8% oxygen) levels of oxygen in the feed gas. Results The main differences in the transcriptome were observed in the comparison of fully aerobic, intermediate oxygen and anaerobic conditions, while the transcriptome was generally unchanged in conditions receiving different intermediate levels (0.5, 1.0 or 2.8% O2) of oxygen in the feed gas. Comparison of the transcriptome and proteome data suggested post-transcriptional regulation was important, especially in 0.5% oxygen. In the conditions of intermediate oxygen, the genes encoding enzymes of the respiratory pathway were more highly expressed than in either aerobic or anaerobic conditions. A similar trend was also seen in the proteome and in enzyme activities of the TCA cycle. Further, genes encoding proteins of the mitochondrial translation machinery were present at higher levels in all oxygen-limited and anaerobic conditions, compared to fully aerobic conditions. Conclusion Global upregulation of genes encoding components of the respiratory pathway under conditions of intermediate oxygen suggested a regulatory mechanism to control these genes as a response to the need of more efficient energy production. Further, cells grown in three different intermediate oxygen levels were highly similar at the level of transcription, while they differed at the proteome level, suggesting post-transcriptional mechanisms leading to distinct physiological modes of respiro-fermentative metabolism. PMID:19804647

  20. Between Product Development and Mass Production: Tensions as Triggers for Concept-Level Learning

    ERIC Educational Resources Information Center

    Jalonen, Meri; Ristimäki, Päivi; Toiviainen, Hanna; Pulkkis, Anneli; Lohtander, Mika

    2016-01-01

    Purpose: This paper aims to analyze learning in organizational transformations by focusing on concept-level tensions faced in two young companies, which were searching for a reorientation of activity with a production network between innovative product development and efficient mass production. Design/methodology/approach: An intervention-based…

  1. Critical width of tidal flats triggers marsh collapse in the absence of sea-level rise.

    PubMed

    Mariotti, Giulio; Fagherazzi, Sergio

    2013-04-02

    High rates of wave-induced erosion along salt marsh boundaries challenge the idea that marsh survival is dictated by the competition between vertical sediment accretion and relative sea-level rise. Because waves pounding marshes are often locally generated in enclosed basins, the depth and width of surrounding tidal flats have a pivoting control on marsh erosion. Here, we show the existence of a threshold width for tidal flats bordering salt marshes. Once this threshold is exceeded, irreversible marsh erosion takes place even in the absence of sea-level rise. This catastrophic collapse occurs because of the positive feedbacks among tidal flat widening by wave-induced marsh erosion, tidal flat deepening driven by wave bed shear stress, and local wind wave generation. The threshold width is determined by analyzing the 50-y evolution of 54 marsh basins along the US Atlantic Coast. The presence of a critical basin width is predicted by a dynamic model that accounts for both horizontal marsh migration and vertical adjustment of marshes and tidal flats. Variability in sediment supply, rather than in relative sea-level rise or wind regime, explains the different critical width, and hence erosion vulnerability, found at different sites. We conclude that sediment starvation of coastlines produced by river dredging and damming is a major anthropogenic driver of marsh loss at the study sites and generates effects at least comparable to the accelerating sea-level rise due to global warming.

  2. Using community level strategies to reduce asthma attacks triggered by outdoor air pollution: a case crossover analysis

    PubMed Central

    2014-01-01

    pollutant exposure is important to effectively attribute risk for triggering of an asthma attack, especially as concentrations increase. Improved asthma action plans for Houston individuals should warn of these pollutants, their trends, correlation and cumulative effects. Our Houston based study identifies nitrogen dioxide levels and the three-day exposure to ozone to be of concern whereas current single pollutant based national standards do not. PMID:25012280

  3. Onboard FPGA-based SAR processing for future spaceborne systems

    NASA Technical Reports Server (NTRS)

    Le, Charles; Chan, Samuel; Cheng, Frank; Fang, Winston; Fischman, Mark; Hensley, Scott; Johnson, Robert; Jourdan, Michael; Marina, Miguel; Parham, Bruce; Rogez, Francois; Rosen, Paul; Shah, Biren; Taft, Stephanie

    2004-01-01

    We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

  4. Neurotoxicity and aggressiveness triggered by low-level lead in children: a review.

    PubMed

    Olympio, Kelly Polido Kaneshiro; Gonçalves, Claudia; Günther, Wanda Maria Risso; Bechara, Etelvino José Henriques

    2009-09-01

    Lead-induced neurotoxicity acquired by low-level long-term exposure has special relevance for children. A plethora of recent reports has demonstrated a direct link between low-level lead exposure and deficits in the neurobehavioral-cognitive performance manifested from childhood through adolescence. In many studies, aggressiveness and delinquency have also been suggested as symptoms of lead poisoning. Several environmental, occupational and domestic sources of contaminant lead and consequent health risks are largely identified and understood, but the occurrences of lead poisoning remain numerous. There is an urgent need for public health policies to prevent lead poisoning so as to reduce individual and societal damages and losses. In this paper we describe unsuspected sources of contaminant lead, discuss the economic losses and urban violence possibly associated with lead contamination and review the molecular basis of lead-induced neurotoxicity, emphasizing its effects on the social behavior, delinquency and IQ of children and adolescents.

  5. STRS SpaceWire FPGA Module

    NASA Technical Reports Server (NTRS)

    Lux, James P.; Taylor, Gregory H.; Lang, Minh; Stern, Ryan A.

    2011-01-01

    An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

  6. Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

    SciTech Connect

    Crosetto, Dario B.

    1998-10-30

    The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelf FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.

  7. The concept of an ACEX® cost-effective first level surface detector trigger in the Pierre Auger Observatory

    NASA Astrophysics Data System (ADS)

    Szadkowski, Z.

    2005-10-01

    The paper describes the new design of the first level trigger for the surface array in the Pierre Auger Observatory. The previous design was tested in a small test segment called Engineering Array (EA). It confirmed full functionality and reliability of the PLD approach. However, because of the high price of the chips available at that time, a new cost-effective design was developed. Altera® offered cost-effective family, which allows reducing the total budget of the electronics without compromise in the functionality. The here described concept of a splitting of data processing into two sub-channels implemented into the parallel working chips, the chips synchronization and the automatization of internal processing management, together with the fully pipelined AHDL code became the framework for the further implementation in the environmental condition of the Argentinian pampa.

  8. Using modern software tools to design, simulate and test a Level 1 trigger sub-system for the D Zero Detector

    SciTech Connect

    Angstadt, R.; Borcherding, F.; Johnson, M.E.; Moreira, L.

    1995-06-01

    This paper describes a system which uses a commercial spreadsheet program and commercial hardware on an IBM PC to develop and test a track finding system for the D Zero Level 1 scintillating Fiber Trigger. The trigger system resides in a VME crate. This system allows the user to generate test input, write the pattern to the hardware simulate the results in software, read the hardware result: compare the results and inform the user of any differences.

  9. Small Microprocessor for ASIC or FPGA Implementation

    NASA Technical Reports Server (NTRS)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  10. Computing Models for FPGA-Based Accelerators

    PubMed Central

    Herbordt, Martin C.; Gu, Yongfeng; VanCourt, Tom; Model, Josh; Sukhwani, Bharat; Chiu, Matt

    2011-01-01

    Field-programmable gate arrays are widely considered as accelerators for compute-intensive applications. A critical phase of FPGA application development is finding and mapping to the appropriate computing model. FPGA computing enables models with highly flexible fine-grained parallelism and associative operations such as broadcast and collective response. Several case studies demonstrate the effectiveness of using these computing models in developing FPGA applications for molecular modeling. PMID:21603152

  11. STRS Compliant FPGA Waveform Development

    NASA Technical Reports Server (NTRS)

    Nappier, Jennifer; Downey, Joseph; Mortensen, Dale

    2008-01-01

    The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. A FPGA-based transmit waveform implementation of the proposed standard interfaces on a laboratory breadboard SDR will be discussed.

  12. Copper(II)-Graphitic Carbon Nitride Triggered Synergy: Improved ROS Generation and Reduced Glutathione Levels for Enhanced Photodynamic Therapy.

    PubMed

    Ju, Enguo; Dong, Kai; Chen, Zhaowei; Liu, Zhen; Liu, Chaoqun; Huang, Yanyan; Wang, Zhenzhen; Pu, Fang; Ren, Jinsong; Qu, Xiaogang

    2016-09-12

    Graphitic carbon nitride (g-C3 N4 ) has been used as photosensitizer to generate reactive oxygen species (ROS) for photodynamic therapy (PDT). However, its therapeutic efficiency was far from satisfactory. One of the major obstacles was the overexpression of glutathione (GSH) in cancer cells, which could diminish the amount of generated ROS before their arrival at the target site. Herein, we report that the integration of Cu(2+) and g-C3 N4 nanosheets (Cu(2+) -g-C3 N4 ) led to enhanced light-triggered ROS generation as well as the depletion of intracellular GSH levels. Consequently, the ROS generated under light irradiation could be consumed less by reduced GSH, and efficiency was improved. Importantly, redox-active species Cu(+) -g-C3 N4 could catalyze the reduction of molecular oxygen to the superoxide anion or hydrogen peroxide to the hydroxyl radical, both of which facilitated the generation of ROS. This synergy of improved ROS generation and GSH depletion could enhance the efficiency of PDT for cancer therapy.

  13. Fluoride-Triggered Ring-Opening of Photochromic Diarylpyrans into Merocyanine Dyes: Naked-Eye Sensing in Subppm Levels.

    PubMed

    Mukhopadhyay, Arindam; Maka, Vijay Kumar; Moorthy, Jarugu Narasimha

    2016-09-02

    The fluoride-mediated desilylation reaction has been exploited, for the first time, to trigger ring-opening of photochromic diarylbenzo-/naphthopyrans into highly colored anionic merocyanine dyes with high molar absorptivities to permit naked-eye sensing. The absorption spectral shifts, i.e., differences in the absorption maxima of colorless and colored forms, observed for a rationally designed set of silyloxy-substituted diarylpyrans subsequent to fluoride-induced ring opening are remarkably high (330-480 nm), and are unknown for any colorimetric probe. In particular, the disilyloxy-substituted diphenylnaphthopyran and its analog, in which the diphenyl groups are fused in the form of fluorene, allows "naked-eye" detection of fluoride in subppm levels (<1.0 ppm) in THF as well as in DMSO-H2O. The sensing is specific for fluoride among various other anions. This approach for colorimetric sensing of fluoride by ring-opening of the otherwise photochromic benzo-/naphthopyrans is heretofore unprecedented.

  14. The Development of FPGA-Based Pseudo-Iterative Clustering Algorithms

    NASA Astrophysics Data System (ADS)

    Drueke, Elizabeth; Fisher, Wade; Plucinski, Pawel

    2016-03-01

    The Large Hadron Collider (LHC) in Geneva, Switzerland, is set to undergo major upgrades in 2025 in the form of the High-Luminosity Large Hadron Collider (HL-LHC). In particular, several hardware upgrades are proposed to the ATLAS detector, one of the two general purpose detectors. These hardware upgrades include, but are not limited to, a new hardware-level clustering algorithm, to be performed by a field programmable gate array, or FPGA. In this study, we develop that clustering algorithm and compare the output to a Python-implemented topoclustering algorithm developed at the University of Oregon. Here, we present the agreement between the FPGA output and expected output, with particular attention to the time required by the FPGA to complete the algorithm and other limitations set by the FPGA itself.

  15. Quaternary base-level drops and trigger mechanisms in a closed basin: Geomorphic and sedimentological studies of the Gastre Basin, Argentina

    NASA Astrophysics Data System (ADS)

    Bilmes, Andrés; Veiga, Gonzalo D.; Ariztegui, Daniel; Castelltort, Sébastien; D'Elia, Leandro; Franzese, Juan R.

    2017-04-01

    Evaluating the role of tectonics and climate as possible triggering mechanisms of landscape reconfigurations is essential for paleoenvironmental and paleoclimatic reconstructions. In this study an exceptional receptive closed Quaternary system of Patagonia (the Gastre Basin) is described, and examined in order to analyze factors triggering base-level drops. Based on a geomorphological approach, which includes new tectonic geomorphology investigations combined with sedimentological and stratigraphic analysis, three large-scale geomorphological systems were identified, described and linked to two major lake-level highstands preserved in the basin. The results indicate magnitudes of base-level drops that are several orders of magnitude greater than present-day water-level fluctuations, suggesting a triggering mechanism not observed in recent times. Direct observations indicating the occurrence of Quaternary faults were not recorded in the region. In addition, morphometric analyses that included mountain front sinuosity, valley width-height ratio, and fan apex position dismiss tectonic fault activity in the Gastre Basin during the middle Pleistocene-Holocene. Therefore, we suggest here that upper Pleistocene climate changes may have been the main triggering mechanism of base-level falls in the Gastre Basin as it is observed in other closed basins of central Patagonia (i.e., Carri Laufquen Basin).

  16. Associative Memory Pattern Matching for the L1 Track Trigger of CMS at the HL-LHC

    NASA Astrophysics Data System (ADS)

    Fedi, Giacomo

    2016-11-01

    The High Luminosity LHC (HL-LHC) will deliver a luminosity of up to 5 × 1034cm-2s-1, with an average of about 140 overlapping proton-proton collisions per bunch crossing. These extreme pileup conditions place stringent requirements on the trigger system to be able to cope with the resulting event rates. A key component of the CMS upgrade for HL-LHC is a track trigger system, able to identify tracks with transverse momenta above 2 GeV/c already at the first-level trigger. We present here the status of the implementation of a prototype system, based on the combination of Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices, with the purpose to demonstrate the concept based on state-of-the-art technologies, and to direct the efforts of the necessary R&D toward a final system.

  17. Review of parallel computing methods and tools for FPGA technology

    NASA Astrophysics Data System (ADS)

    Cieszewski, Radosław; Linczuk, Maciej; Pozniak, Krzysztof; Romaniuk, Ryszard

    2013-10-01

    Parallel computing is emerging as an important area of research in computer architectures and software systems. Many algorithms can be greatly accelerated using parallel computing techniques. Specialized parallel computer architectures are used for accelerating speci c tasks. High-Energy Physics Experiments measuring systems often use FPGAs for ne-grained computation. FPGA combines many bene ts of both software and ASIC implementations. Like software, the mapped circuit is exible, and can be recon gured over the lifetime of the system. FPGAs therefore have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. Creating parallel programs implemented in FPGAs is not trivial. This paper presents existing methods and tools for ne-grained computation implemented in FPGA using Behavioral Description and High Level Programming Languages.

  18. A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

    NASA Astrophysics Data System (ADS)

    Dong, Yiping; Li, Ce; Lin, Zhen; Watanabe, Takahiro

    This paper presents a novel architecture for an FPGA-based implementation of multilayer Artificial Neural Network (ANN), which integrates both the layer-multiplexing and pipeline architecture. Given a kind of FPGA to be used, the proposed method aims at enhancing the efficiency of resource usage of the FPGA and improving the forward speed at the module level, so that a larger ANN can be implemented on traditional FPGAs and also a high performance is achieved. Usually FPGA board is not changed for every applications, thus, we need not mind about the usage of it if the application can be implemented within the resource limitation. We developed a new mapping method from ANN schematic to FPGA by using this hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results show that the proposed architecture can produce a very compact circuit for multilayer ANN to meet resource limitation of a given FPGA. Furthermore, higher performance is obtained as compared with conventional methods.

  19. STRS Compliant FPGA Waveform Development

    NASA Technical Reports Server (NTRS)

    Nappier, Jennifer; Downey, Joseph

    2008-01-01

    The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.

  20. Autonomous Lawnmower using FPGA implementation.

    NASA Astrophysics Data System (ADS)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  1. FPGA design and implementation of Gaussian filter

    NASA Astrophysics Data System (ADS)

    Yang, Zhihui; Zhou, Gang

    2015-12-01

    In this paper , we choose four different variances of 1,3,6 and 12 to conduct FPGA design with three kinds of Gaussian filtering algorithm ,they are implementing Gaussian filter with a Gaussian filter template, Gaussian filter approximation with mean filtering and Gaussian filter approximation with IIR filtering. By waveform simulation and synthesis, we get the processing results on the experimental image and the consumption of FPGA resources of the three methods. We set the result of Gaussian filter used in matlab as standard to get the result error. By comparing the FPGA resources and the error of FPGA implementation methods, we get the best FPGA design to achieve a Gaussian filter. Conclusions can be drawn based on the results we have already got. When the variance is small, the FPGA resources is enough for the algorithm to implement Gaussian filter with a Gaussian filter template which is the best choice. But when the variance is so large that there is no more FPGA resources, we can chose the mean to approximate Gaussian filter with IIR filtering.

  2. FPGA Simulation Engine for Customized Construction of Neural Microcircuits.

    PubMed

    Blair, Hugh T; Cong, Jason; Wu, Di

    2013-04-01

    In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.

  3. A 96-channel FPGA-based time-to-digital converter

    SciTech Connect

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Phillips, Thomas J; Wilson, Peter

    2005-02-01

    We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA’s. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

  4. Rad-Hard/HI-REL FPGA

    NASA Technical Reports Server (NTRS)

    Wang, Jih-Jong; Cronquist, Brian E.; McGowan, John E.; Katz, Richard B.

    1997-01-01

    The goals for a radiation hardened (RAD-HARD) and high reliability (HI-REL) field programmable gate array (FPGA) are described. The first qualified manufacturer list (QML) radiation hardened RH1280 and RH1020 were developed. The total radiation dose and single event effects observed on the antifuse FPGA RH1280 are reported on. Tradeoffs and the limitations in the single event upset hardening are discussed.

  5. OpenACC to FPGA: A Framework for Directive-based High-Performance Reconfigurable Computing

    SciTech Connect

    Lee, Seyong; Kim, Jungwon; Vetter, Jeffrey S

    2016-01-01

    This paper presents a directive-based, high-level programming framework for high-performance reconfigurable computing. It takes a standard, portable OpenACC C program as input and generates a hardware configuration file for execution on FPGAs. We implemented this prototype system using our open-source OpenARC compiler; it performs source-to-source translation and optimization of the input OpenACC program into an OpenCL code, which is further compiled into a FPGA program by the backend Altera Offline OpenCL compiler. Internally, the design of OpenARC uses a high- level intermediate representation that separates concerns of program representation from underlying architectures, which facilitates portability of OpenARC. In fact, this design allowed us to create the OpenACC-to-FPGA translation framework with minimal extensions to our existing system. In addition, we show that our proposed FPGA-specific compiler optimizations and novel OpenACC pragma extensions assist the compiler in generating more efficient FPGA hardware configuration files. Our empirical evaluation on an Altera Stratix V FPGA with eight OpenACC benchmarks demonstrate the benefits of our strategy. To demonstrate the portability of OpenARC, we show results for the same benchmarks executing on other heterogeneous platforms, including NVIDIA GPUs, AMD GPUs, and Intel Xeon Phis. This initial evidence helps support the goal of using a directive-based, high-level programming strategy for performance portability across heterogeneous HPC architectures.

  6. Tethered Forth system for FPGA applications

    NASA Astrophysics Data System (ADS)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  7. Forecasting peak daily ozone levels: part 2--A regression with time series errors model having a principal component trigger to forecast 1999 and 2002 ozone levels.

    PubMed

    Liu, Pao-Wen Grace; Johnson, Richard

    2003-12-01

    A modified time series approach, a Box-Jenkins regression with time series errors (RTSE) model plus a principal component (PC) trigger, has been developed to forecast peak daily 1-hr ozone (O3) in real time at the University of Wisconsin-Milwaukee North (UWM-N) during 1999 and 2002. The PC trigger acts as a predictor variable in the RTSE model. It tries to answer the question: will the next day be a possible high O3 day? To answer this question, three PC trigger rules were developed: (1) Hi-Low Checklist, (2) Discriminant Function Approach I, and (3) Discriminant Function Approach II. Also, a pure RTSE model without including the PC trigger and a persistence approach were tested for comparison. The RTSE model with DFA I successfully forecast the only two 1-hr federal exceedances (124 ppb), one in 1999 and one in 2002. In terms of the O3 100-ppb exceedances, 60-80% of the incorrect forecasts occurred with incorrect PC decisions. A few others may have been caused by unexpected O3-weather relations. When the three approaches used UWM-N data to forecast a 100-ppb exceedance somewhere in the Milwaukee, WI, metropolitan area, their performance was dramatically improved: the false alarm rate was reduced from 0.89 to 0.44, and the probability of detection was increased from 0.71 to 0.88.

  8. A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

    PubMed Central

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2014-01-01

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

  9. A FPGA embedded web server for remote monitoring and control of smart sensors networks.

    PubMed

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2013-12-27

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

  10. GPU/MIC Acceleration of the LHC High Level Trigger to Extend the Physics Reach at the LHC

    SciTech Connect

    Halyo, Valerie; Tully, Christopher

    2015-04-14

    The quest for rare new physics phenomena leads the PI [3] to propose evaluation of coprocessors based on Graphics Processing Units (GPUs) and the Intel Many Integrated Core (MIC) architecture for integration into the trigger system at LHC. This will require development of a new massively parallel implementation of the well known Combinatorial Track Finder which uses the Kalman Filter to accelerate processing of data from the silicon pixel and microstrip detectors and reconstruct the trajectory of all charged particles down to momentums of 100 MeV. It is expected to run at least one order of magnitude faster than an equivalent algorithm on a quad core CPU for extreme pileup scenarios of 100 interactions per bunch crossing. The new tracking algorithms will be developed and optimized separately on the GPU and Intel MIC and then evaluated against each other for performance and power efficiency. The results will be used to project the cost of the proposed hardware architectures for the HLT server farm, taking into account the long term projections of the main vendors in the market (AMD, Intel, and NVIDIA) over the next 10 years. Extensive experience and familiarity of the PI with the LHC tracker and trigger requirements led to the development of a complementary tracking algorithm that is described in [arxiv: 1305.4855], [arxiv: 1309.6275] and preliminary results accepted to JINST.

  11. Trigger finger

    MedlinePlus

    ... Redness in your cut or hand Swelling or warmth in your cut or hand Yellow or green drainage from the cut Hand pain or discomfort Fever If your trigger finger returns, call your surgeon. You may need another surgery.

  12. Performance of the L3 second level trigger implemented for the LEP II with the SGS Thomson C104 packet switch

    SciTech Connect

    Blaising, J.J.; Chollet-Le Flour, F.

    1998-08-01

    The L3 experiment is one of the four experiments collecting data at LEP. For the LEP phase 2, the second level trigger has been upgraded to a network of 28 ST T9000 transputers and 2 ST C104 asynchronous packet switches interconnected by IEEE1355 links. It collects trigger data at each LEP crossing (22 {micro}s), builds-up the trigger data block, processes it and rejects online the background events in a few milliseconds. The L3 data acquisition has been running with this system since July 1995. In the data-taking environment and for different hardware and software implementations, the event building throughput rate has been measured. A bandwidth of 5.9 Mbytes per second per link has been measured in a configuration with 12 sources and one processing unit connected with 2 links. The expected global throughput of 70 Mbytes per second has been measured in a farm of 6 processing units. While varying the number of sources and destinations, the authors didn`t observe any significant bandwidth loss. Nevertheless performance relies strongly on some software implementation choices, which are presented and discussed.

  13. Single Event Transients in Voltage Regulators for FPGA Power Supply Applications

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Sanders, Anthony; Kim, Hak; Phan, Anthony; Forney, Jim; LaBel, Kenneth A.; Karsh, Jeremy; Pursley, Scott; Kleyner, Igor; Katz, Richard

    2006-01-01

    As with other bipolar analog devices, voltage regulators are known to be sensitive to single event transients (SET). In typical applications, large output capacitors are used to provide noise immunity. Therefore, since SET amplitude and duration are generally small, they are often of secondary importance due to this capacitance filtering. In low voltage applications, however, even small SET are a concern. Over-voltages may cause destructive conditions. Under-voltages may cause functional interrupts and may also trigger electrical latchup conditions. In addition, internal protection circuits which are affected by load as well as internal thermal effects can also be triggered from heavy ions, causing dropouts or shutdown ranging from milliseconds to seconds. In the case of FPGA power supplies applications, SETS are critical. For example, in the case of Actel FPGA RTAX family, core power supply voltage is 1.5V. Manufacturer specifies an absolute maximum rating of 1.6V and recommended operating conditions between 1.425V and 1.575V. Therefore, according to the manufacturer, any transient of amplitude greater than 75 mV can disrupt normal circuit functions, and overvoltages greater than 100 mV may damage the FPGA. We tested five low dropout voltage regulators for SET sensitivity under a large range of circuit application conditions.

  14. Calorimetry Triggering in ATLAS

    SciTech Connect

    Igonkina, O.; Achenbach, R.; Adragna, P.; Aharrouche, M.; Alexandre, G.; Andrei, V.; Anduaga, X.; Aracena, I.; Backlund, S.; Baines, J.; Barnett, B.M.; Bauss, B.; Bee, C.; Behera, P.; Bell, P.; Bendel, M.; Benslama, K.; Berry, T.; Bogaerts, A.; Bohm, C.; Bold, T.; /UC, Irvine /AGH-UST, Cracow /Birmingham U. /Barcelona, IFAE /CERN /Birmingham U. /Rutherford /Montreal U. /Santa Maria U., Valparaiso /DESY /DESY, Zeuthen /Geneva U. /City Coll., N.Y. /Barcelona, IFAE /CERN /Birmingham U. /Kirchhoff Inst. Phys. /Birmingham U. /Lisbon, LIFEP /Rio de Janeiro Federal U. /City Coll., N.Y. /Birmingham U. /Copenhagen U. /Copenhagen U. /Brookhaven /Rutherford /Royal Holloway, U. of London /Pennsylvania U. /Montreal U. /SLAC /CERN /Michigan State U. /Chile U., Catolica /City Coll., N.Y. /Oxford U. /La Plata U. /McGill U. /Mainz U., Inst. Phys. /Hamburg U. /DESY /DESY, Zeuthen /Geneva U. /Queen Mary, U. of London /CERN /Rutherford /Rio de Janeiro Federal U. /Birmingham U. /Montreal U. /CERN /Kirchhoff Inst. Phys. /Liverpool U. /Royal Holloway, U. of London /Pennsylvania U. /Kirchhoff Inst. Phys. /Geneva U. /Birmingham U. /NIKHEF, Amsterdam /Rutherford /Royal Holloway, U. of London /Rutherford /Royal Holloway, U. of London /AGH-UST, Cracow /Mainz U., Inst. Phys. /Mainz U., Inst. Phys. /Birmingham U. /Hamburg U. /DESY /DESY, Zeuthen /Geneva U. /Kirchhoff Inst. Phys. /Michigan State U. /Stockholm U. /Stockholm U. /Birmingham U. /CERN /Montreal U. /Stockholm U. /Arizona U. /Regina U. /Regina U. /Rutherford /NIKHEF, Amsterdam /Kirchhoff Inst. Phys. /DESY /DESY, Zeuthen /City Coll., N.Y. /University Coll. London /Humboldt U., Berlin /Queen Mary, U. of London /Argonne /LPSC, Grenoble /Arizona U. /Kirchhoff Inst. Phys. /Birmingham U. /Antonio Narino U. /Hamburg U. /DESY /DESY, Zeuthen /Kirchhoff Inst. Phys. /Birmingham U. /Chile U., Catolica /Indiana U. /Manchester U. /Kirchhoff Inst. Phys. /Rutherford /City Coll., N.Y. /Stockholm U. /La Plata U. /Antonio Narino U. /Queen Mary, U. of London /Kirchhoff Inst. Phys. /Antonio Narino U. /Pavia U. /City Coll., N.Y. /Mainz U., Inst. Phys. /Mainz U., Inst. Phys. /Pennsylvania U. /Barcelona, IFAE /Barcelona, IFAE /Chile U., Catolica /Genoa U. /INFN, Genoa /Rutherford /Barcelona, IFAE /Nevis Labs, Columbia U. /CERN /Antonio Narino U. /McGill U. /Rutherford /Santa Maria U., Valparaiso /Rutherford /Chile U., Catolica /Brookhaven /Oregon U. /Mainz U., Inst. Phys. /Barcelona, IFAE /McGill U. /Antonio Narino U. /Antonio Narino U. /Kirchhoff Inst. Phys. /Sydney U. /Rutherford /McGill U. /McGill U. /Pavia U. /Genoa U. /INFN, Genoa /Kirchhoff Inst. Phys. /Kirchhoff Inst. Phys. /Mainz U., Inst. Phys. /Barcelona, IFAE /SLAC /Stockholm U. /Moscow State U. /Stockholm U. /Birmingham U. /Kirchhoff Inst. Phys. /DESY /DESY, Zeuthen /Birmingham U. /Geneva U. /Oregon U. /Barcelona, IFAE /University Coll. London /Royal Holloway, U. of London /Birmingham U. /Mainz U., Inst. Phys. /Birmingham U. /Birmingham U. /Oregon U. /La Plata U. /Geneva U. /Chile U., Catolica /McGill U. /Pavia U. /Barcelona, IFAE /Regina U. /Birmingham U. /Birmingham U. /Kirchhoff Inst. Phys. /Oxford U. /CERN /Kirchhoff Inst. Phys. /UC, Irvine /UC, Irvine /Wisconsin U., Madison /Rutherford /Mainz U., Inst. Phys. /CERN /Geneva U. /Copenhagen U. /City Coll., N.Y. /Wisconsin U., Madison /Rio de Janeiro Federal U. /Wisconsin U., Madison /Stockholm U. /University Coll. London

    2011-12-08

    The ATLAS experiment is preparing for data taking at 14 TeV collision energy. A rich discovery physics program is being prepared in addition to the detailed study of Standard Model processes which will be produced in abundance. The ATLAS multi-level trigger system is designed to accept one event in 2/10{sup 5} to enable the selection of rare and unusual physics events. The ATLAS calorimeter system is a precise instrument, which includes liquid Argon electro-magnetic and hadronic components as well as a scintillator-tile hadronic calorimeter. All these components are used in the various levels of the trigger system. A wide physics coverage is ensured by inclusively selecting events with candidate electrons, photons, taus, jets or those with large missing transverse energy. The commissioning of the trigger system is being performed with cosmic ray events and by replaying simulated Monte Carlo events through the trigger and data acquisition system.

  15. Triggering Klystrons

    SciTech Connect

    Stefan, Kelton D.; /Purdue U. /SLAC

    2010-08-25

    To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

  16. Real-time windowing in imaging radar using FPGA technique

    NASA Astrophysics Data System (ADS)

    Ponomaryov, Volodymyr I.; Escamilla-Hernandez, Enrique

    2005-02-01

    The imaging radar uses the high frequency electromagnetic waves reflected from different objects for estimating of its parameters. Pulse compression is a standard signal processing technique used to minimize the peak transmission power and to maximize SNR, and to get a better resolution. Usually the pulse compression can be achieved using a matched filter. The level of the side-lobes in the imaging radar can be reduced using the special weighting function processing. There are very known different weighting functions: Hamming, Hanning, Blackman, Chebyshev, Blackman-Harris, Kaiser-Bessel, etc., widely used in the signal processing applications. Field Programmable Gate Arrays (FPGAs) offers great benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. This reconfiguration makes FPGAs a better solution over custom-made integrated circuits. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal and pulse compression using Matlab, Simulink, and System Generator. Employing FPGA and mentioned software we have proposed the pulse compression design on FPGA using classical and novel windows technique to reduce the side-lobes level. This permits increasing the detection ability of the small or nearly placed targets in imaging radar. The advantage of FPGA that can do parallelism in real time processing permits to realize the proposed algorithms. The paper also presents the experimental results of proposed windowing procedure in the marine radar with such the parameters: signal is linear FM (Chirp); frequency deviation DF is 9.375MHz; the pulse width T is 3.2μs taps number in the matched filter is 800 taps; sampling frequency 253.125*106 MHz. It has been realized the reducing of side-lobes levels in real time permitting better resolution of the small targets.

  17. Signal-on electrochemical detection of antibiotics at zeptomole level based on target-aptamer binding triggered multiple recycling amplification.

    PubMed

    Wang, Hongzhi; Wang, Yu; Liu, Su; Yu, Jinghua; Guo, Yuna; Xu, Ying; Huang, Jiadong

    2016-06-15

    In the work, a signal-on electrochemical DNA sensor based on multiple amplification for ultrasensitive detection of antibiotics has been reported. In the presence of target, the ingeniously designed hairpin probe (HP1) is opened and the polymerase-assisted target recycling amplification is triggered, resulting in autonomous generation of secondary target. It is worth noting that the produced secondary target could not only hybridize with other HP1, but also displace the Helper from the electrode. Consequently, methylene blue labeled HP2 forms a "close" probe structure, and the increase of signal is monitored. The increasing current provides an ultrasensitive electrochemical detection for antibiotics down to 1.3 fM. To our best knowledge, such work is the first report about multiple recycling amplification combing with signal-on sensing strategy, which has been utilized for quantitative determination of antibiotics. It would be further used as a general strategy associated with more analytical techniques toward the detection of a wide spectrum of analytes. Thus, it holds great potential for the development of ultrasensitive biosensing platform for the applications in bioanalysis, disease diagnostics, and clinical biomedicine.

  18. Optoelectronic date acquisition system based on FPGA

    NASA Astrophysics Data System (ADS)

    Li, Xin; Liu, Chunyang; Song, De; Tong, Zhiguo; Liu, Xiangqing

    2015-11-01

    An optoelectronic date acquisition system is designed based on FPGA. FPGA chip that is EP1C3T144C8 of Cyclone devices from Altera corporation is used as the centre of logic control, XTP2046 chip is used as A/D converter, host computer that communicates with the date acquisition system through RS-232 serial communication interface are used as display device and photo resistance is used as photo sensor. We use Verilog HDL to write logic control code about FPGA. It is proved that timing sequence is correct through the simulation of ModelSim. Test results indicate that this system meets the design requirement, has fast response and stable operation by actual hardware circuit test.

  19. Trigger and Readout System for the Ashra-1 Detector

    NASA Astrophysics Data System (ADS)

    Aita, Y.; Aoki, T.; Asaoka, Y.; Morimoto, Y.; Motz, H. M.; Sasaki, M.; Abiko, C.; Kanokohata, C.; Ogawa, S.; Shibuya, H.; Takada, T.; Kimura, T.; Learned, J. G.; Matsuno, S.; Kuze, S.; Binder, P. M.; Goldman, J.; Sugiyama, N.; Watanabe, Y.

    Highly sophisticated trigger and readout system has been developed for All-sky Survey High Resolution Air-shower (Ashra) detector. Ashra-1 detector has 42 degree diameter field of view. Detection of Cherenkov and fluorescence light from large background in the large field of view requires finely segmented and high speed trigger and readout system. The system is composed of optical fiber image transmission system, 64 × 64 channel trigger sensor and FPGA based trigger logic processor. The system typically processes the image within 10 to 30 ns and opens the shutter on the fine CMOS sensor. 64 × 64 coarse split image is transferred via 64 × 64 precisely aligned optical fiber bundle to a photon sensor. Current signals from the photon sensor are discriminated by custom made trigger amplifiers. FPGA based processor processes 64 × 64 hit pattern and correspondent partial area of the fine image is acquired. Commissioning earth skimming tau neutrino observational search was carried out with this trigger system. In addition to the geometrical advantage of the Ashra observational site, the excellent tau shower axis measurement based on the fine imaging and the night sky background rejection based on the fine and fast imaging allow zero background tau shower search. Adoption of the optical fiber bundle and trigger LSI realized 4k channel trigger system cheaply. Detectability of tau shower is also confirmed by simultaneously observed Cherenkov air shower. Reduction of the trigger threshold appears to enhance the effective area especially in PeV tau neutrino energy region. New two dimensional trigger LSI was introduced and the trigger threshold was lowered. New calibration system of the trigger system was recently developed and introduced to the Ashra detector

  20. Fluence-dependent effects of low-level laser therapy in myofascial trigger spots on modulation of biochemicals associated with pain in a rabbit model.

    PubMed

    Hsieh, Yueh-Ling; Hong, Chang-Zern; Chou, Li-Wei; Yang, Shun-An; Yang, Chen-Chia

    2015-01-01

    Evidence strongly supports that low-level laser therapy (LLLT) is an effective physical modality for the treatment of pain associated with myofascial trigger points (MTrP). However, the effect of laser fluence (energy intensity in J/cm(2)) on biochemical regulation related to pain is unclear. To better understand the biochemical mechanisms modulated by high- and low-fluence LLLT at myofascial trigger spots (MTrSs; similar to human MTrPs) in skeletal muscles of rabbits, the levels of β-endorphin (β-ep), substance P (SP), tumor necrosis factor-α (TNF-α), and cyclooxygenase-2 (COX-2) were investigated in this study. New Zealand rabbits (2.5-3.0 kg in weight) were used in this study. High-fluence LLLT (27 J/cm(2)), low-fluence LLLT (4.5 J/cm(2)), or sham operations were applied on MTrSs of biceps femoris of rabbits for five sessions (one session per day). Effects of LLLT at two different fluences on biceps femoris, dorsal root ganglion (DRG), and serum were determined by β-ep, SP, TNF-α, and COX-2 immunoassays. LLLT irradiation with fluences of 4.5 and 27 J/cm(2) at MTrSs can significantly reduce SP level in DRG. LLLT with lower fluence of 4.5 J/cm(2) exerted lower levels of TNF-α and COX-2 expression in laser-treated muscle, but LLLT with higher fluence of 27 J/cm(2) elevated the levels of β-ep in serum, DRG, and muscle. This study demonstrated fluence-dependent biochemical effects of LLLT in an animal model on management of myofascial pain. The findings can contribute to the development of dosage guideline for LLLT for treating MTrP-induced pain.

  1. FPGA implementation of vision algorithms for small autonomous robots

    NASA Astrophysics Data System (ADS)

    Anderson, J. D.; Lee, D. J.; Archibald, J. K.

    2005-10-01

    The use of on-board vision with small autonomous robots has been made possible by the advances in the field of Field Programmable Gate Array (FPGA) technology. By connecting a CMOS camera to an FPGA board, on-board vision has been used to reduce the computation time inherent in vision algorithms. The FPGA board allows the user to create custom hardware in a faster, safer, and more easily verifiable manner that decreases the computation time and allows the vision to be done in real-time. Real-time vision tasks for small autonomous robots include object tracking, obstacle detection and avoidance, and path planning. Competitions were created to demonstrate that our algorithms work with our small autonomous vehicles in dealing with these problems. These competitions include Mouse-Trapped-in-a-Box, where the robot has to detect the edges of a box that it is trapped in and move towards them without touching them; Obstacle Avoidance, where an obstacle is placed at any arbitrary point in front of the robot and the robot has to navigate itself around the obstacle; Canyon Following, where the robot has to move to the center of a canyon and follow the canyon walls trying to stay in the center; the Grand Challenge, where the robot had to navigate a hallway and return to its original position in a given amount of time; and Stereo Vision, where a separate robot had to catch tennis balls launched from an air powered cannon. Teams competed on each of these competitions that were designed for a graduate-level robotic vision class, and each team had to develop their own algorithm and hardware components. This paper discusses one team's approach to each of these problems.

  2. Testing Microshutter Arrays Using Commercial FPGA Hardware

    NASA Technical Reports Server (NTRS)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  3. FPGA Sequencer for Radar Altimeter Applications

    NASA Technical Reports Server (NTRS)

    Berkun, Andrew C.; Pollard, Brian D.; Chen, Curtis W.

    2011-01-01

    A sequencer for a radar altimeter provides accurate attitude information for a reliable soft landing of the Mars Science Laboratory (MSL). This is a field-programmable- gate-array (FPGA)-only implementation. A table loaded externally into the FPGA controls timing, processing, and decision structures. Radar is memory-less and does not use previous acquisitions to assist in the current acquisition. All cycles complete in exactly 50 milliseconds, regardless of range or whether a target was found. A RAM (random access memory) within the FPGA holds instructions for up to 15 sets. For each set, timing is run, echoes are processed, and a comparison is made. If a target is seen, more detailed processing is run on that set. If no target is seen, the next set is tried. When all sets have been run, the FPGA terminates and waits for the next 50-millisecond event. This setup simplifies testing and improves reliability. A single vertex chip does the work of an entire assembly. Output products require minor processing to become range and velocity. This technology is the heart of the Terminal Descent Sensor, which is an integral part of the Entry Decent and Landing system for MSL. In addition, it is a strong candidate for manned landings on Mars or the Moon.

  4. Experiences on 64 and 150 FPGA Systems

    SciTech Connect

    Storaasli, Olaf O; Strenski, Dave

    2008-01-01

    Four FPGA systems were evaluated: the Cray XD1 system with 6 FPGAs at ORNL and Cray, the Cray XD1 system with 150 FPGAs at NRL* and the 64 FPGAs on Edinburgh s Maxwell . Their hardware and software architectures, programming tools and performance on scientific applications are discussed. FPGA speedup (over a 2.2 GHz Opteron) of 10X was typical for matrix equation solution, molecular dynamics and weather/climate codes and upto 100X for human genome DNA sequencing. Large genome comparisons requiring 12.5 years for an Opteron took less than 24 hours on NRL s Cray XD1 with 150 Virtex FPGAs for a 7,350X speedup. pipeline so each query and database character are compared in parallel, resulting in a table of scores. Genome Sequencing Results: FPGA timing results (for up to 150 FPGAs) were obtained and compared with up to 150 Opterons for sequences of varying size and complexity (e.g. 4GB openfpga.org human DNA benchmark and 155M human vs. 166M mouse DNA). 1 FPGA: Bacillus_anthracis DNA compare: Genomes

  5. The CMS trigger system

    DOE PAGES

    Khachatryan, Vardan

    2017-01-24

    This paper describes the CMS trigger system and its performance during Run 1 of the LHC. The trigger system consists of two levels designed to select events of potential physics interest from a GHz (MHz) interaction rate of proton-proton (heavy ion) collisions. The first level of the trigger is implemented in hardware, and selects events containing detector signals consistent with an electron, photon, muon, tau lepton, jet, or missing transverse energy. A programmable menu of up to 128 object-based algorithms is used to select events for subsequent processing. The trigger thresholds are adjusted to the LHC instantaneous luminosity during datamore » taking in order to restrict the output rate to 100 kHz, the upper limit imposed by the CMS readout electronics. The second level, implemented in software, further refines the purity of the output stream, selecting an average rate of 400 Hz for offline event storage. The objectives, strategy and performance of the trigger system during the LHC Run 1 are described.« less

  6. The CMS trigger system

    NASA Astrophysics Data System (ADS)

    Khachatryan, V.; Sirunyan, A. M.; Tumasyan, A.; Adam, W.; Asilar, E.; Bergauer, T.; Brandstetter, J.; Brondolin, E.; Dragicevic, M.; Erö, J.; Flechl, M.; Friedl, M.; Frühwirth, R.; Ghete, V. M.; Hartl, C.; Hörmann, N.; Hrubec, J.; Jeitler, M.; Knünz, V.; König, A.; Krammer, M.; Krätschmer, I.; Liko, D.; Matsushita, T.; Mikulec, I.; Rabady, D.; Rahbaran, B.; Rohringer, H.; Schieck, J.; Schöfbeck, R.; Strauss, J.; Treberer-Treberspurg, W.; Waltenberger, W.; Wulz, C.-E.; Mossolov, V.; Shumeiko, N.; Suarez Gonzalez, J.; Alderweireldt, S.; Cornelis, T.; De Wolf, E. A.; Janssen, X.; Knutsson, A.; Lauwers, J.; Luyckx, S.; Van De Klundert, M.; Van Haevermaet, H.; Van Mechelen, P.; Van Remortel, N.; Van Spilbeeck, A.; Abu Zeid, S.; Blekman, F.; D'Hondt, J.; Daci, N.; De Bruyn, I.; Deroover, K.; Heracleous, N.; Keaveney, J.; Lowette, S.; Moreels, L.; Olbrechts, A.; Python, Q.; Strom, D.; Tavernier, S.; Van Doninck, W.; Van Mulders, P.; Van Onsem, G. P.; Van Parijs, I.; Barria, P.; Brun, H.; Caillol, C.; Clerbaux, B.; De Lentdecker, G.; Fasanella, G.; Favart, L.; Grebenyuk, A.; Karapostoli, G.; Lenzi, T.; Léonard, A.; Maerschalk, T.; Marinov, A.; Perniè, L.; Randle-conde, A.; Reis, T.; Seva, T.; Vander Velde, C.; Vanlaer, P.; Yonamine, R.; Zenoni, F.; Zhang, F.; Beernaert, K.; Benucci, L.; Cimmino, A.; Crucy, S.; Dobur, D.; Fagot, A.; Garcia, G.; Gul, M.; Mccartin, J.; Ocampo Rios, A. A.; Poyraz, D.; Ryckbosch, D.; Salva, S.; Sigamani, M.; Strobbe, N.; Tytgat, M.; Van Driessche, W.; Yazgan, E.; Zaganidis, N.; Basegmez, S.; Beluffi, C.; Bondu, O.; Brochet, S.; Bruno, G.; Caudron, A.; Ceard, L.; Da Silveira, G. G.; Delaere, C.; Favart, D.; Forthomme, L.; Giammanco, A.; Hollar, J.; Jafari, A.; Jez, P.; Komm, M.; Lemaitre, V.; Mertens, A.; Musich, M.; Nuttens, C.; Perrini, L.; Pin, A.; Piotrzkowski, K.; Popov, A.; Quertenmont, L.; Selvaggi, M.; Vidal Marono, M.; Beliy, N.; Hammad, G. H.; Aldá Júnior, W. L.; Alves, F. L.; Alves, G. A.; Brito, L.; Correa Martins Junior, M.; Hamer, M.; Hensel, C.; Mora Herrera, C.; Moraes, A.; Pol, M. E.; Rebello Teles, P.; Belchior Batista Das Chagas, E.; Carvalho, W.; Chinellato, J.; Custódio, A.; Da Costa, E. M.; Damiao, D. De Jesus; De Oliveira Martins, C.; Fonseca De Souza, S.; Huertas Guativa, L. M.; Malbouisson, H.; Matos Figueiredo, D.; Mundim, L.; Nogima, H.; Prado Da Silva, W. L.; Santoro, A.; Sznajder, A.; Tonelli Manganote, E. J.; Vilela Pereira, A.; Ahuja, S.; Bernardes, C. A.; De Souza Santos, A.; Dogra, S.; Fernandez Perez Tomei, T. R.; Gregores, E. M.; Mercadante, P. G.; Moon, C. S.; Novaes, S. F.; Padula, Sandra S.; Romero Abad, D.; Ruiz Vargas, J. C.; Aleksandrov, A.; Hadjiiska, R.; Iaydjiev, P.; Rodozov, M.; Stoykova, S.; Sultanov, G.; Vutova, M.; Dimitrov, A.; Glushkov, I.; Litov, L.; Pavlov, B.; Petkov, P.; Ahmad, M.; Bian, J. G.; Chen, G. M.; Chen, H. S.; Chen, M.; Cheng, T.; Du, R.; Jiang, C. H.; Plestina, R.; Romeo, F.; Shaheen, S. M.; Spiezia, A.; Tao, J.; Wang, C.; Wang, Z.; Zhang, H.; Asawatangtrakuldee, C.; Ban, Y.; Li, Q.; Liu, S.; Mao, Y.; Qian, S. J.; Wang, D.; Xu, Z.; Avila, C.; Cabrera, A.; Chaparro Sierra, L. F.; Florez, C.; Gomez, J. P.; Gomez Moreno, B.; Sanabria, J. C.; Godinovic, N.; Lelas, D.; Puljak, I.; Ribeiro Cipriano, P. M.; Antunovic, Z.; Kovac, M.; Brigljevic, V.; Kadija, K.; Luetic, J.; Micanovic, S.; Sudic, L.; Attikis, A.; Mavromanolakis, G.; Mousa, J.; Nicolaou, C.; Ptochos, F.; Razis, P. A.; Rykaczewski, H.; Bodlak, M.; Finger, M.; Finger, M., Jr.; Assran, Y.; El Sawy, M.; Elgammal, S.; Ellithi Kamel, A.; Mahmoud, M. A.; Calpas, B.; Kadastik, M.; Murumaa, M.; Raidal, M.; Tiko, A.; Veelken, C.; Eerola, P.; Pekkanen, J.; Voutilainen, M.; Härkönen, J.; Karimäki, V.; Kinnunen, R.; Lampén, T.; Lassila-Perini, K.; Lehti, S.; Lindén, T.; Luukka, P.; Mäenpää, T.; Peltola, T.; Tuominen, E.; Tuominiemi, J.; Tuovinen, E.; Wendland, L.; Talvitie, J.; Tuuva, T.; Besancon, M.; Couderc, F.; Dejardin, M.; Denegri, D.; Fabbro, B.; Faure, J. L.; Favaro, C.; Ferri, F.; Ganjour, S.; Givernaud, A.; Gras, P.; Hamel de Monchenault, G.; Jarry, P.; Locci, E.; Machet, M.; Malcles, J.; Rander, J.; Rosowsky, A.; Titov, M.; Zghiche, A.; Antropov, I.; Baffioni, S.; Beaudette, F.; Busson, P.; Cadamuro, L.; Chapon, E.; Charlot, C.; Dahms, T.; Davignon, O.; Filipovic, N.; Florent, A.; Granier de Cassagnac, R.; Lisniak, S.; Mastrolorenzo, L.; Miné, P.; Naranjo, I. N.; Nguyen, M.; Ochando, C.; Ortona, G.; Paganini, P.; Pigard, P.; Regnard, S.; Salerno, R.; Sauvan, J. B.; Sirois, Y.; Strebler, T.; Yilmaz, Y.; Zabi, A.; Agram, J.-L.; Andrea, J.; Aubin, A.; Bloch, D.; Brom, J.-M.; Buttignol, M.; Chabert, E. C.; Chanon, N.; Collard, C.; Conte, E.; Coubez, X.; Fontaine, J.-C.; Gelé, D.; Goerlach, U.; Goetzmann, C.; Le Bihan, A.-C.; Merlin, J. A.; Skovpen, K.; Van Hove, P.; Gadrat, S.; Beauceron, S.; Bernet, C.; Boudoul, G.; Bouvier, E.; Carrillo Montoya, C. A.; Chierici, R.; Contardo, D.; Courbon, B.; Depasse, P.; El Mamouni, H.; Fan, J.; Fay, J.; Gascon, S.; Gouzevitch, M.; Ille, B.; Lagarde, F.; Laktineh, I. B.; Lethuillier, M.; Mirabito, L.; Pequegnot, A. L.; Perries, S.; Ruiz Alvarez, J. D.; Sabes, D.; Sgandurra, L.; Sordini, V.; Vander Donckt, M.; Verdier, P.; Viret, S.; Toriashvili, T.; Tsamalaidze, Z.; Autermann, C.; Beranek, S.; Edelhoff, M.; Feld, L.; Heister, A.; Kiesel, M. K.; Klein, K.; Lipinski, M.; Ostapchuk, A.; Preuten, M.; Raupach, F.; Schael, S.; Schulte, J. F.; Verlage, T.; Weber, H.; Wittmer, B.; Zhukov, V.; Ata, M.; Brodski, M.; Dietz-Laursonn, E.; Duchardt, D.; Endres, M.; Erdmann, M.; Erdweg, S.; Esch, T.; Fischer, R.; Güth, A.; Hebbeker, T.; Heidemann, C.; Hoepfner, K.; Klingebiel, D.; Knutzen, S.; Kreuzer, P.; Merschmeyer, M.; Meyer, A.; Millet, P.; Olschewski, M.; Padeken, K.; Papacz, P.; Pook, T.; Radziej, M.; Reithler, H.; Rieger, M.; Scheuch, F.; Sonnenschein, L.; Teyssier, D.; Thüer, S.; Cherepanov, V.; Erdogan, Y.; Flügge, G.; Geenen, H.; Geisler, M.; Hoehle, F.; Kargoll, B.; Kress, T.; Kuessel, Y.; Künsken, A.; Lingemann, J.; Nehrkorn, A.; Nowack, A.; Nugent, I. M.; Pistone, C.; Pooth, O.; Stahl, A.; Aldaya Martin, M.; Asin, I.; Bartosik, N.; Behnke, O.; Behrens, U.; Bell, A. J.; Borras, K.; Burgmeier, A.; Campbell, A.; Choudhury, S.; Costanza, F.; Diez Pardos, C.; Dolinska, G.; Dooling, S.; Dorland, T.; Eckerlin, G.; Eckstein, D.; Eichhorn, T.; Flucke, G.; Gallo, E.; Garay Garcia, J.; Geiser, A.; Gizhko, A.; Gunnellini, P.; Hauk, J.; Hempel, M.; Jung, H.; Kalogeropoulos, A.; Karacheban, O.; Kasemann, M.; Katsas, P.; Kieseler, J.; Kleinwort, C.; Korol, I.; Lange, W.; Leonard, J.; Lipka, K.; Lobanov, A.; Lohmann, W.; Mankel, R.; Marfin, I.; Melzer-Pellmann, I.-A.; Meyer, A. B.; Mittag, G.; Mnich, J.; Mussgiller, A.; Naumann-Emme, S.; Nayak, A.; Ntomari, E.; Perrey, H.; Pitzl, D.; Placakyte, R.; Raspereza, A.; Roland, B.; Sahin, M. Ö.; Saxena, P.; Schoerner-Sadenius, T.; Schröder, M.; Seitz, C.; Spannagel, S.; Trippkewitz, K. D.; Walsh, R.; Wissing, C.; Blobel, V.; Centis Vignali, M.; Draeger, A. R.; Erfle, J.; Garutti, E.; Goebel, K.; Gonzalez, D.; Görner, M.; Haller, J.; Hoffmann, M.; Höing, R. S.; Junkes, A.; Klanner, R.; Kogler, R.; Kovalchuk, N.; Lapsien, T.; Lenz, T.; Marchesini, I.; Marconi, D.; Meyer, M.; Nowatschin, D.; Ott, J.; Pantaleo, F.; Peiffer, T.; Perieanu, A.; Pietsch, N.; Poehlsen, J.; Rathjens, D.; Sander, C.; Scharf, C.; Schettler, H.; Schleper, P.; Schlieckau, E.; Schmidt, A.; Schwandt, J.; Sola, V.; Stadie, H.; Steinbrück, G.; Tholen, H.; Troendle, D.; Usai, E.; Vanelderen, L.; Vanhoefer, A.; Vormwald, B.; Akbiyik, M.; Barth, C.; Baus, C.; Berger, J.; Böser, C.; Butz, E.; Chwalek, T.; Colombo, F.; De Boer, W.; Descroix, A.; Dierlamm, A.; Fink, S.; Frensch, F.; Friese, R.; Giffels, M.; Gilbert, A.; Haitz, D.; Hartmann, F.; Heindl, S. M.; Husemann, U.; Katkov, I.; Kornmayer, A.; Lobelle Pardo, P.; Maier, B.; Mildner, H.; Mozer, M. U.; Müller, T.; Müller, Th.; Plagge, M.; Quast, G.; Rabbertz, K.; Röcker, S.; Roscher, F.; Sieber, G.; Simonis, H. J.; Stober, F. M.; Ulrich, R.; Wagner-Kuhr, J.; Wayand, S.; Weber, M.; Weiler, T.; Wöhrmann, C.; Wolf, R.; Anagnostou, G.; Daskalakis, G.; Geralis, T.; Giakoumopoulou, V. A.; Kyriakis, A.; Loukas, D.; Psallidas, A.; Topsis-Giotis, I.; Agapitos, A.; Kesisoglou, S.; Panagiotou, A.; Saoulidou, N.; Tziaferi, E.; Evangelou, I.; Flouris, G.; Foudas, C.; Kokkas, P.; Loukas, N.; Manthos, N.; Papadopoulos, I.; Paradas, E.; Strologas, J.; Bencze, G.; Hajdu, C.; Hazi, A.; Hidas, P.; Horvath, D.; Sikler, F.; Veszpremi, V.; Vesztergombi, G.; Zsigmond, A. J.; Beni, N.; Czellar, S.; Karancsi, J.; Molnar, J.; Szillasi, Z.; Bartók, M.; Makovec, A.; Raics, P.; Trocsanyi, Z. L.; Ujvari, B.; Mal, P.; Mandal, K.; Sahoo, D. K.; Sahoo, N.; Swain, S. K.; Bansal, S.; Beri, S. B.; Bhatnagar, V.; Chawla, R.; Gupta, R.; Bhawandeep, U.; Kalsi, A. K.; Kaur, A.; Kaur, M.; Kumar, R.; Mehta, A.; Mittal, M.; Singh, J. B.; Walia, G.; Kumar, Ashok; Bhardwaj, A.; Choudhary, B. C.; Garg, R. B.; Kumar, A.; Malhotra, S.; Naimuddin, M.; Nishu, N.; Ranjan, K.; Sharma, R.; Sharma, V.; Bhattacharya, S.; Chatterjee, K.; Dey, S.; Dutta, S.; Jain, Sa.; Majumdar, N.; Modak, A.; Mondal, K.; Mukherjee, S.; Mukhopadhyay, S.; Roy, A.; Roy, D.; Chowdhury, S. Roy; Sarkar, S.; Sharan, M.; Abdulsalam, A.; Chudasama, R.; Dutta, D.; Jha, V.; Kumar, V.; Mohanty, A. K.; Pant, L. M.; Shukla, P.; Topkar, A.; Aziz, T.; Banerjee, S.; Bhowmik, S.; Chatterjee, R. M.; Dewanjee, R. K.; Dugad, S.; Ganguly, S.; Ghosh, S.; Guchait, M.; Gurtu, A.; Kole, G.; Kumar, S.; Mahakud, B.; Maity, M.; Majumder, G.; Mazumdar, K.; Mitra, S.; Mohanty, G. B.; Parida, B.; Sarkar, T.; Sur, N.; Sutar, B.; Wickramage, N.; Chauhan, S.; Dube, S.; Kothekar, K.; Sharma, S.; Bakhshiansohi, H.; Behnamian, H.; Etesami, S. M.; Fahim, A.; Goldouzian, R.; Khakzad, M.; Najafabadi, M. Mohammadi; Naseri, M.; Paktinat Mehdiabadi, S.; Rezaei Hosseinabadi, F.; Safarzadeh, B.; Zeinali, M.; Felcini, M.; Grunewald, M.; Abbrescia, M.; Calabria, C.; Caputo, C.; Colaleo, A.; Creanza, D.; Cristella, L.; De Filippis, N.; De Palma, M.; Fiore, L.; Iaselli, G.; Maggi, G.; Maggi, M.; Miniello, G.; My, S.; Nuzzo, S.; Pompili, A.; Pugliese, G.; Radogna, R.; Ranieri, A.; Selvaggi, G.; Silvestris, L.; Venditti, R.; Verwilligen, P.; Abbiendi, G.; Battilana, C.; Benvenuti, A. C.; Bonacorsi, D.; Braibant-Giacomelli, S.; Brigliadori, L.; Campanini, R.; Capiluppi, P.; Castro, A.; Cavallo, F. R.; Chhibra, S. S.; Codispoti, G.; Cuffiani, M.; Dallavalle, G. M.; Fabbri, F.; Fanfani, A.; Fasanella, D.; Giacomelli, P.; Grandi, C.; Guiducci, L.; Marcellini, S.; Masetti, G.; Montanari, A.; Navarria, F. L.; Perrotta, A.; Rossi, A. M.; Rovelli, T.; Siroli, G. P.; Tosi, N.; Travaglini, R.; Cappello, G.; Chiorboli, M.; Costa, S.; Di Mattia, A.; Giordano, F.; Potenza, R.; Tricomi, A.; Tuve, C.; Barbagli, G.; Ciulli, V.; Civinini, C.; D'Alessandro, R.; Focardi, E.; Gonzi, S.; Gori, V.; Lenzi, P.; Meschini, M.; Paoletti, S.; Sguazzoni, G.; Tropiano, A.; Viliani, L.; Benussi, L.; Bianco, S.; Fabbri, F.; Piccolo, D.; Primavera, F.; Calvelli, V.; Ferro, F.; Lo Vetere, M.; Monge, M. R.; Robutti, E.; Tosi, S.; Brianza, L.; Dinardo, M. E.; Fiorendi, S.; Gennai, S.; Gerosa, R.; Ghezzi, A.; Govoni, P.; Malvezzi, S.; Manzoni, R. A.; Marzocchi, B.; Menasce, D.; Moroni, L.; Paganoni, M.; Pedrini, D.; Ragazzi, S.; Redaelli, N.; Tabarelli de Fatis, T.; Buontempo, S.; Cavallo, N.; Di Guida, S.; Esposito, M.; Fabozzi, F.; Iorio, A. O. M.; Lanza, G.; Lista, L.; Meola, S.; Merola, M.; Paolucci, P.; Sciacca, C.; Thyssen, F.; Bacchetta, N.; Bellato, M.; Benato, L.; Bisello, D.; Boletti, A.; Carlin, R.; Checchia, P.; Dall'Osso, M.; Dosselli, U.; Gasparini, F.; Gasparini, U.; Gozzelino, A.; Lacaprara, S.; Margoni, M.; Meneguzzo, A. T.; Montecassiano, F.; Passaseo, M.; Pazzini, J.; Pegoraro, M.; Pozzobon, N.; Simonetto, F.; Torassa, E.; Tosi, M.; Vanini, S.; Ventura, S.; Zanetti, M.; Zotto, P.; Zucchetta, A.; Zumerle, G.; Braghieri, A.; Magnani, A.; Montagna, P.; Ratti, S. P.; Re, V.; Riccardi, C.; Salvini, P.; Vai, I.; Vitulo, P.; Alunni Solestizi, L.; Biasini, M.; Bilei, G. M.; Ciangottini, D.; Fanò, L.; Lariccia, P.; Mantovani, G.; Menichelli, M.; Saha, A.; Santocchia, A.; Androsov, K.; Azzurri, P.; Bagliesi, G.; Bernardini, J.; Boccali, T.; Castaldi, R.; Ciocci, M. A.; Dell'Orso, R.; Donato, S.; Fedi, G.; Foà, L.; Giassi, A.; Grippo, M. T.; Ligabue, F.; Lomtadze, T.; Martini, L.; Messineo, A.; Palla, F.; Rizzi, A.; Savoy-Navarro, A.; Serban, A. T.; Spagnolo, P.; Tenchini, R.; Tonelli, G.; Venturi, A.; Verdini, P. G.; Barone, L.; Cavallari, F.; D'imperio, G.; Del Re, D.; Diemoz, M.; Gelli, S.; Jorda, C.; Longo, E.; Margaroli, F.; Meridiani, P.; Organtini, G.; Paramatti, R.; Preiato, F.; Rahatlou, S.; Rovelli, C.; Santanastasio, F.; Traczyk, P.; Amapane, N.; Arcidiacono, R.; Argiro, S.; Arneodo, M.; Bellan, R.; Biino, C.; Cartiglia, N.; Costa, M.; Covarelli, R.; Degano, A.; Demaria, N.; Finco, L.; Kiani, B.; Mariotti, C.; Maselli, S.; Migliore, E.; Monaco, V.; Monteil, E.; Obertino, M. M.; Pacher, L.; Pastrone, N.; Pelliccioni, M.; Pinna Angioni, G. L.; Ravera, F.; Romero, A.; Ruspa, M.; Sacchi, R.; Solano, A.; Staiano, A.; Tamponi, U.; Belforte, S.; Candelise, V.; Casarsa, M.; Cossutti, F.; Della Ricca, G.; Gobbo, B.; La Licata, C.; Marone, M.; Schizzi, A.; Zanetti, A.; Kropivnitskaya, A.; Nam, S. K.; Kim, D. H.; Kim, G. N.; Kim, M. S.; Kong, D. J.; Lee, S.; Oh, Y. D.; Sakharov, A.; Son, D. C.; Brochero Cifuentes, J. A.; Kim, H.; Kim, T. J.; Song, S.; Choi, S.; Go, Y.; Gyun, D.; Hong, B.; Jo, M.; Kim, H.; Kim, Y.; Lee, B.; Lee, K.; Lee, K. S.; Lee, S.; Park, S. K.; Roh, Y.; Yoo, H. D.; Choi, M.; Kim, H.; Kim, J. H.; Lee, J. S. H.; Park, I. C.; Ryu, G.; Ryu, M. S.; Choi, Y.; Goh, J.; Kim, D.; Kwon, E.; Lee, J.; Yu, I.; Dudenas, V.; Juodagalvis, A.; Vaitkus, J.; Ahmed, I.; Ibrahim, Z. A.; Komaragiri, J. R.; Ali, M. A. B. Md; Mohamad Idris, F.; Abdullah, W. A. T. Wan; Yusli, M. N.; Casimiro Linares, E.; Castilla-Valdez, H.; De La Cruz-Burelo, E.; Heredia-De La Cruz, I.; Hernandez-Almada, A.; Lopez-Fernandez, R.; Sanchez-Hernandez, A.; Carrillo Moreno, S.; Vazquez Valencia, F.; Pedraza, I.; Salazar Ibarguen, H. A.; Morelos Pineda, A.; Krofcheck, D.; Butler, P. H.; Ahmad, A.; Ahmad, M.; Hassan, Q.; Hoorani, H. R.; Khan, W. A.; Khurshid, T.; Shoaib, M.; Bialkowska, H.; Bluj, M.; Boimska, B.; Frueboes, T.; Górski, M.; Kazana, M.; Nawrocki, K.; Romanowska-Rybinska, K.; Szleper, M.; Zalewski, P.; Brona, G.; Bunkowski, K.; Byszuk, A.; Doroba, K.; Kalinowski, A.; Kierzkowski, K.; Konecki, M.; Krolikowski, J.; Misiura, M.; Oklinski, W.; Olszewski, M.; Pozniak, K.; Walczak, M.; Zabolotny, W.; Bargassa, P.; Silva, C. Beirão Da Cruz E.; Di Francesco, A.; Faccioli, P.; Ferreira Parracho, P. G.; Gallinaro, M.; Leonardo, N.; Lloret Iglesias, L.; Nguyen, F.; Rodrigues Antunes, J.; Seixas, J.; Toldaiev, O.; Vadruccio, D.; Varela, J.; Vischia, P.; Afanasiev, S.; Bunin, P.; Gavrilenko, M.; Golutvin, I.; Gorbunov, I.; Kamenev, A.; Karjavin, V.; Konoplyanikov, V.; Lanev, A.; Malakhov, A.; Matveev, V.; Moisenz, P.; Palichik, V.; Perelygin, V.; Shmatov, S.; Shulha, S.; Skatchkov, N.; Smirnov, V.; Zarubin, A.; Golovtsov, V.; Ivanov, Y.; Kim, V.; Kuznetsova, E.; Levchenko, P.; Murzin, V.; Oreshkin, V.; Smirnov, I.; Sulimov, V.; Uvarov, L.; Vavilov, S.; Vorobyev, A.; Andreev, Yu.; Dermenev, A.; Gninenko, S.; Golubev, N.; Karneyeu, A.; Kirsanov, M.; Krasnikov, N.; Pashenkov, A.; Tlisov, D.; Toropin, A.; Epshteyn, V.; Gavrilov, V.; Lychkovskaya, N.; Popov, V.; Pozdnyakov, I.; Safronov, G.; Spiridonov, A.; Vlasov, E.; Zhokin, A.; Bylinkin, A.; Andreev, V.; Azarkin, M.; Dremin, I.; Kirakosyan, M.; Leonidov, A.; Mesyats, G.; Rusakov, S. V.; Baskakov, A.; Belyaev, A.; Boos, E.; Dubinin, M.; Dudko, L.; Ershov, A.; Gribushin, A.; Kaminskiy, A.; Klyukhin, V.; Kodolova, O.; Lokhtin, I.; Myagkov, I.; Obraztsov, S.; Petrushanko, S.; Savrin, V.; Azhgirey, I.; Bayshev, I.; Bitioukov, S.; Kachanov, V.; Kalinin, A.; Konstantinov, D.; Krychkine, V.; Petrov, V.; Ryutin, R.; Sobol, A.; Tourtchanovitch, L.; Troshin, S.; Tyurin, N.; Uzunian, A.; Volkov, A.; Adzic, P.; Milosevic, J.; Rekovic, V.; Alcaraz Maestre, J.; Calvo, E.; Cerrada, M.; Chamizo Llatas, M.; Colino, N.; De La Cruz, B.; Delgado Peris, A.; Domínguez Vázquez, D.; Escalante Del Valle, A.; Fernandez Bedoya, C.; Fernández Ramos, J. P.; Flix, J.; Fouz, M. C.; Garcia-Abia, P.; Gonzalez Lopez, O.; Goy Lopez, S.; Hernandez, J. M.; Josa, M. I.; Navarro De Martino, E.; Pérez-Calero Yzquierdo, A.; Puerta Pelayo, J.; Quintario Olmeda, A.; Redondo, I.; Romero, L.; Santaolalla, J.; Soares, M. S.; Albajar, C.; de Trocóniz, J. F.; Missiroli, M.; Moran, D.; Cuevas, J.; Fernandez Menendez, J.; Folgueras, S.; Gonzalez Caballero, I.; Palencia Cortezon, E.; Vizan Garcia, J. M.; Cabrillo, I. J.; Calderon, A.; Castiñeiras De Saa, J. R.; De Castro Manzano, P.; Duarte Campderros, J.; Fernandez, M.; Garcia-Ferrero, J.; Gomez, G.; Lopez Virto, A.; Marco, J.; Marco, R.; Martinez Rivero, C.; Matorras, F.; Munoz Sanchez, F. J.; Piedra Gomez, J.; Rodrigo, T.; Rodríguez-Marrero, A. Y.; Ruiz-Jimeno, A.; Scodellaro, L.; Trevisani, N.; Vila, I.; Vilar Cortabitarte, R.; Abbaneo, D.; Auffray, E.; Auzinger, G.; Bachtis, M.; Baillon, P.; Ball, A. H.; Barney, D.; Benaglia, A.; Bendavid, J.; Benhabib, L.; Benitez, J. F.; Berruti, G. M.; Bloch, P.; Bocci, A.; Bonato, A.; Botta, C.; Breuker, H.; Camporesi, T.; Castello, R.; Cerminara, G.; D'Alfonso, M.; d'Enterria, D.; Dabrowski, A.; Daponte, V.; David, A.; De Gruttola, M.; De Guio, F.; De Roeck, A.; De Visscher, S.; Di Marco, E.; Dobson, M.; Dordevic, M.; Dorney, B.; du Pree, T.; Dünser, M.; Dupont, N.; Elliott-Peisert, A.; Franzoni, G.; Funk, W.; Gigi, D.; Gill, K.; Giordano, D.; Girone, M.; Glege, F.; Guida, R.; Gundacker, S.; Guthoff, M.; Hammer, J.; Harris, P.; Hegeman, J.; Innocente, V.; Janot, P.; Kirschenmann, H.; Kortelainen, M. J.; Kousouris, K.; Krajczar, K.; Lecoq, P.; Lourenço, C.; Lucchini, M. T.; Magini, N.; Malgeri, L.; Mannelli, M.; Martelli, A.; Masetti, L.; Meijers, F.; Mersi, S.; Meschi, E.; Moortgat, F.; Morovic, S.; Mulders, M.; Nemallapudi, M. V.; Neugebauer, H.; Orfanelli, S.; Orsini, L.; Pape, L.; Perez, E.; Peruzzi, M.; Petrilli, A.; Petrucciani, G.; Pfeiffer, A.; Piparo, D.; Racz, A.; Rolandi, G.; Rovere, M.; Ruan, M.; Sakulin, H.; Schäfer, C.; Schwick, C.; Seidel, M.; Sharma, A.; Silva, P.; Simon, M.; Sphicas, P.; Steggemann, J.; Stieger, B.; Stoye, M.; Takahashi, Y.; Treille, D.; Triossi, A.; Tsirou, A.; Veres, G. I.; Wardle, N.; Wöhri, H. K.; Zagozdzinska, A.; Zeuner, W. D.; Bertl, W.; Deiters, K.; Erdmann, W.; Horisberger, R.; Ingram, Q.; Kaestli, H. C.; Kotlinski, D.; Langenegger, U.; Renker, D.; Rohe, T.; Bachmair, F.; Bäni, L.; Bianchini, L.; Casal, B.; Dissertori, G.; Dittmar, M.; Donegà, M.; Eller, P.; Grab, C.; Heidegger, C.; Hits, D.; Hoss, J.; Kasieczka, G.; Lustermann, W.; Mangano, B.; Marionneau, M.; Martinez Ruiz del Arbol, P.; Masciovecchio, M.; Meister, D.; Micheli, F.; Musella, P.; Nessi-Tedaldi, F.; Pandolfi, F.; Pata, J.; Pauss, F.; Perrozzi, L.; Quittnat, M.; Rossini, M.; Starodumov, A.; Takahashi, M.; Tavolaro, V. R.; Theofilatos, K.; Wallny, R.; Aarrestad, T. K.; Amsler, C.; Caminada, L.; Canelli, M. F.; Chiochia, V.; De Cosa, A.; Galloni, C.; Hinzmann, A.; Hreus, T.; Kilminster, B.; Lange, C.; Ngadiuba, J.; Pinna, D.; Robmann, P.; Ronga, F. J.; Salerno, D.; Yang, Y.; Cardaci, M.; Chen, K. H.; Doan, T. H.; Jain, Sh.; Khurana, R.; Konyushikhin, M.; Kuo, C. M.; Lin, W.; Lu, Y. J.; Yu, S. S.; Kumar, Arun; Bartek, R.; Chang, P.; Chang, Y. H.; Chang, Y. W.; Chao, Y.; Chen, K. F.; Chen, P. H.; Dietz, C.; Fiori, F.; Grundler, U.; Hou, W.-S.; Hsiung, Y.; Liu, Y. F.; Lu, R.-S.; Miñano Moya, M.; Petrakou, E.; Tsai, J. f.; Tzeng, Y. M.; Asavapibhop, B.; Kovitanggoon, K.; Singh, G.; Srimanobhas, N.; Suwonjandee, N.; Adiguzel, A.; Bakirci, M. N.; Demiroglu, Z. S.; Dozen, C.; Eskut, E.; Girgis, S.; Gokbulut, G.; Guler, Y.; Gurpinar, E.; Hos, I.; Kangal, E. E.; Onengut, G.; Ozdemir, K.; Polatoz, A.; Sunar Cerci, D.; Tali, B.; Topakli, H.; Vergili, M.; Zorbilmez, C.; Akin, I. V.; Bilin, B.; Bilmis, S.; Isildak, B.; Karapinar, G.; Yalvac, M.; Zeyrek, M.; Gülmez, E.; Kaya, M.; Kaya, O.; Yetkin, E. A.; Yetkin, T.; Cakir, A.; Cankocak, K.; Sen, S.; Vardarlı, F. I.; Grynyov, B.; Levchuk, L.; Sorokin, P.; Aggleton, R.; Ball, F.; Beck, L.; Brooke, J. J.; Clement, E.; Cussans, D.; Flacher, H.; Goldstein, J.; Grimes, M.; Heath, G. P.; Heath, H. F.; Jacob, J.; Kreczko, L.; Lucas, C.; Meng, Z.; Newbold, D. M.; Paramesvaran, S.; Poll, A.; Sakuma, T.; Seif El Nasr-storey, S.; Senkin, S.; Smith, D.; Smith, V. J.; Bell, K. W.; Belyaev, A.; Brew, C.; Brown, R. M.; Calligaris, L.; Cieri, D.; Cockerill, D. J. A.; Coughlan, J. A.; Harder, K.; Harper, S.; Olaiya, E.; Petyt, D.; Shepherd-Themistocleous, C. H.; Thea, A.; Tomalin, I. R.; Williams, T.; Womersley, W. J.; Worm, S. D.; Baber, M.; Bainbridge, R.; Buchmuller, O.; Bundock, A.; Burton, D.; Casasso, S.; Citron, M.; Colling, D.; Corpe, L.; Cripps, N.; Dauncey, P.; Davies, G.; De Wit, A.; Della Negra, M.; Dunne, P.; Elwood, A.; Ferguson, W.; Fulcher, J.; Futyan, D.; Hall, G.; Iles, G.; Kenzie, M.; Lane, R.; Lucas, R.; Lyons, L.; Magnan, A.-M.; Malik, S.; Nash, J.; Nikitenko, A.; Pela, J.; Pesaresi, M.; Petridis, K.; Raymond, D. M.; Richards, A.; Rose, A.; Seez, C.; Tapper, A.; Uchida, K.; Vazquez Acosta, M.; Virdee, T.; Zenz, S. C.; Cole, J. E.; Hobson, P. R.; Khan, A.; Kyberd, P.; Leggat, D.; Leslie, D.; Reid, I. D.; Symonds, P.; Teodorescu, L.; Turner, M.; Borzou, A.; Call, K.; Dittmann, J.; Hatakeyama, K.; Liu, H.; Pastika, N.; Charaf, O.; Cooper, S. I.; Henderson, C.; Rumerio, P.; Arcaro, D.; Avetisyan, A.; Bose, T.; Fantasia, C.; Gastler, D.; Lawson, P.; Rankin, D.; Richardson, C.; Rohlf, J.; St. John, J.; Sulak, L.; Zou, D.; Alimena, J.; Berry, E.; Bhattacharya, S.; Cutts, D.; Dhingra, N.; Ferapontov, A.; Garabedian, A.; Hakala, J.; Heintz, U.; Laird, E.; Landsberg, G.; Mao, Z.; Narain, M.; Piperov, S.; Sagir, S.; Syarif, R.; Breedon, R.; Breto, G.; Calderon De La Barca Sanchez, M.; Chauhan, S.; Chertok, M.; Conway, J.; Conway, R.; Cox, P. T.; Erbacher, R.; Gardner, M.; Ko, W.; Lander, R.; Mulhearn, M.; Pellett, D.; Pilot, J.; Ricci-Tam, F.; Shalhout, S.; Smith, J.; Squires, M.; Stolp, D.; Tripathi, M.; Wilbur, S.; Yohay, R.; Cousins, R.; Everaerts, P.; Farrell, C.; Hauser, J.; Ignatenko, M.; Saltzberg, D.; Takasugi, E.; Valuev, V.; Weber, M.; Burt, K.; Clare, R.; Ellison, J.; Gary, J. W.; Hanson, G.; Heilman, J.; Ivova PANEVA, M.; Jandir, P.; Kennedy, E.; Lacroix, F.; Long, O. R.; Luthra, A.; Malberti, M.; Olmedo Negrete, M.; Shrinivas, A.; Wei, H.; Wimpenny, S.; Yates, B. R.; Branson, J. G.; Cerati, G. B.; Cittolin, S.; D'Agnolo, R. T.; Derdzinski, M.; Holzner, A.; Kelley, R.; Klein, D.; Letts, J.; Macneill, I.; Olivito, D.; Padhi, S.; Pieri, M.; Sani, M.; Sharma, V.; Simon, S.; Tadel, M.; Vartak, A.; Wasserbaech, S.; Welke, C.; Würthwein, F.; Yagil, A.; Zevi Della Porta, G.; Bradmiller-Feld, J.; Campagnari, C.; Dishaw, A.; Dutta, V.; Flowers, K.; Sevilla, M. Franco; Geffert, P.; George, C.; Golf, F.; Gouskos, L.; Gran, J.; Incandela, J.; Mccoll, N.; Mullin, S. D.; Richman, J.; Stuart, D.; Suarez, I.; West, C.; Yoo, J.; Anderson, D.; Apresyan, A.; Bornheim, A.; Bunn, J.; Chen, Y.; Duarte, J.; Mott, A.; Newman, H. B.; Pena, C.; Pierini, M.; Spiropulu, M.; Vlimant, J. R.; Xie, S.; Zhu, R. Y.; Andrews, M. B.; Azzolini, V.; Calamba, A.; Carlson, B.; Ferguson, T.; Paulini, M.; Russ, J.; Sun, M.; Vogel, H.; Vorobiev, I.; Cumalat, J. P.; Ford, W. T.; Gaz, A.; Jensen, F.; Johnson, A.; Krohn, M.; Mulholland, T.; Nauenberg, U.; Stenson, K.; Wagner, S. R.; Alexander, J.; Chatterjee, A.; Chaves, J.; Chu, J.; Dittmer, S.; Eggert, N.; Mirman, N.; Kaufman, G. Nicolas; Patterson, J. R.; Rinkevicius, A.; Ryd, A.; Skinnari, L.; Soffi, L.; Sun, W.; Tan, S. M.; Teo, W. D.; Thom, J.; Thompson, J.; Tucker, J.; Weng, Y.; Wittich, P.; Abdullin, S.; Albrow, M.; Anderson, J.; Apollinari, G.; Banerjee, S.; Bauerdick, L. A. T.; Beretvas, A.; Berryhill, J.; Bhat, P. C.; Bolla, G.; Burkett, K.; Butler, J. N.; Cheung, H. W. K.; Chlebana, F.; Cihangir, S.; Elvira, V. D.; Fisk, I.; Freeman, J.; Gottschalk, E.; Gray, L.; Green, D.; Grünendahl, S.; Gutsche, O.; Hanlon, J.; Hare, D.; Harris, R. M.; Hasegawa, S.; Hirschauer, J.; Hu, Z.; Jayatilaka, B.; Jindariani, S.; Johnson, M.; Joshi, U.; Jung, A. W.; Klima, B.; Kreis, B.; Kwan, S.; Lammel, S.; Linacre, J.; Lincoln, D.; Lipton, R.; Liu, T.; Lopes De Sá, R.; Lykken, J.; Maeshima, K.; Marraffino, J. M.; Martinez Outschoorn, V. I.; Maruyama, S.; Mason, D.; McBride, P.; Merkel, P.; Mishra, K.; Mrenna, S.; Nahn, S.; Newman-Holmes, C.; O'Dell, V.; Pedro, K.; Prokofyev, O.; Rakness, G.; Sexton-Kennedy, E.; Soha, A.; Spalding, W. J.; Spiegel, L.; Taylor, L.; Tkaczyk, S.; Tran, N. V.; Uplegger, L.; Vaandering, E. W.; Vernieri, C.; Verzocchi, M.; Vidal, R.; Weber, H. A.; Whitbeck, A.; Yang, F.; Acosta, D.; Avery, P.; Bortignon, P.; Bourilkov, D.; Carnes, A.; Carver, M.; Curry, D.; Das, S.; Di Giovanni, G. P.; Field, R. D.; Furic, I. K.; Gleyzer, S. V.; Hugon, J.; Konigsberg, J.; Korytov, A.; Low, J. F.; Ma, P.; Matchev, K.; Mei, H.; Milenovic, P.; Mitselmakher, G.; Rank, D.; Rossin, R.; Shchutska, L.; Snowball, M.; Sperka, D.; Terentyev, N.; Thomas, L.; Wang, J.; Wang, S.; Yelton, J.; Hewamanage, S.; Linn, S.; Markowitz, P.; Martinez, G.; Rodriguez, J. L.; Ackert, A.; Adams, J. R.; Adams, T.; Askew, A.; Bochenek, J.; Diamond, B.; Haas, J.; Hagopian, S.; Hagopian, V.; Johnson, K. F.; Khatiwada, A.; Prosper, H.; Weinberg, M.; Baarmand, M. M.; Bhopatkar, V.; Colafranceschi, S.; Hohlmann, M.; Kalakhety, H.; Noonan, D.; Roy, T.; Yumiceva, F.; Adams, M. R.; Apanasevich, L.; Berry, D.; Betts, R. R.; Bucinskaite, I.; Cavanaugh, R.; Evdokimov, O.; Gauthier, L.; Gerber, C. E.; Hofman, D. J.; Kurt, P.; O'Brien, C.; Sandoval Gonzalez, I. D.; Silkworth, C.; Turner, P.; Varelas, N.; Wu, Z.; Zakaria, M.; Bilki, B.; Clarida, W.; Dilsiz, K.; Durgut, S.; Gandrajula, R. P.; Haytmyradov, M.; Khristenko, V.; Merlo, J.-P.; Mermerkaya, H.; Mestvirishvili, A.; Moeller, A.; Nachtman, J.; Ogul, H.; Onel, Y.; Ozok, F.; Penzo, A.; Snyder, C.; Tiras, E.; Wetzel, J.; Yi, K.; Anderson, I.; Barnett, B. A.; Blumenfeld, B.; Eminizer, N.; Fehling, D.; Feng, L.; Gritsan, A. V.; Maksimovic, P.; Martin, C.; Osherson, M.; Roskes, J.; Sady, A.; Sarica, U.; Swartz, M.; Xiao, M.; Xin, Y.; You, C.; Baringer, P.; Bean, A.; Benelli, G.; Bruner, C.; Kenny, R. P., III; Majumder, D.; Malek, M.; Murray, M.; Sanders, S.; Stringer, R.; Wang, Q.; Ivanov, A.; Kaadze, K.; Khalil, S.; Makouski, M.; Maravin, Y.; Mohammadi, A.; Saini, L. K.; Skhirtladze, N.; Toda, S.; Lange, D.; Rebassoo, F.; Wright, D.; Anelli, C.; Baden, A.; Baron, O.; Belloni, A.; Calvert, B.; Eno, S. C.; Ferraioli, C.; Gomez, J. A.; Hadley, N. J.; Jabeen, S.; Kellogg, R. G.; Kolberg, T.; Kunkle, J.; Lu, Y.; Mignerey, A. C.; Shin, Y. H.; Skuja, A.; Tonjes, M. B.; Tonwar, S. C.; Apyan, A.; Barbieri, R.; Baty, A.; Bierwagen, K.; Brandt, S.; Busza, W.; Cali, I. A.; Demiragli, Z.; Di Matteo, L.; Gomez Ceballos, G.; Goncharov, M.; Gulhan, D.; Iiyama, Y.; Innocenti, G. M.; Klute, M.; Kovalskyi, D.; Lai, Y. S.; Lee, Y.-J.; Levin, A.; Luckey, P. D.; Marini, A. C.; Mcginn, C.; Mironov, C.; Narayanan, S.; Niu, X.; Paus, C.; Ralph, D.; Roland, C.; Roland, G.; Salfeld-Nebgen, J.; Stephans, G. S. F.; Sumorok, K.; Varma, M.; Velicanu, D.; Veverka, J.; Wang, J.; Wang, T. W.; Wyslouch, B.; Yang, M.; Zhukova, V.; Dahmes, B.; Evans, A.; Finkel, A.; Gude, A.; Hansen, P.; Kalafut, S.; Kao, S. C.; Klapoetke, K.; Kubota, Y.; Lesko, Z.; Mans, J.; Nourbakhsh, S.; Ruckstuhl, N.; Rusack, R.; Tambe, N.; Turkewitz, J.; Acosta, J. G.; Oliveros, S.; Avdeeva, E.; Bloom, K.; Bose, S.; Claes, D. R.; Dominguez, A.; Fangmeier, C.; Gonzalez Suarez, R.; Kamalieddin, R.; Keller, J.; Knowlton, D.; Kravchenko, I.; Meier, F.; Monroy, J.; Ratnikov, F.; Siado, J. E.; Snow, G. R.; Alyari, M.; Dolen, J.; George, J.; Godshalk, A.; Harrington, C.; Iashvili, I.; Kaisen, J.; Kharchilava, A.; Kumar, A.; Rappoccio, S.; Roozbahani, B.; Alverson, G.; Barberis, E.; Baumgartel, D.; Chasco, M.; Hortiangtham, A.; Massironi, A.; Morse, D. M.; Nash, D.; Orimoto, T.; Teixeira De Lima, R.; Trocino, D.; Wang, R.-J.; Wood, D.; Zhang, J.; Hahn, K. A.; Kubik, A.; Mucia, N.; Odell, N.; Pollack, B.; Pozdnyakov, A.; Schmitt, M.; Stoynev, S.; Sung, K.; Trovato, M.; Velasco, M.; Brinkerhoff, A.; Dev, N.; Hildreth, M.; Jessop, C.; Karmgard, D. J.; Kellams, N.; Lannon, K.; Lynch, S.; Marinelli, N.; Meng, F.; Mueller, C.; Musienko, Y.; Pearson, T.; Planer, M.; Reinsvold, A.; Ruchti, R.; Smith, G.; Taroni, S.; Valls, N.; Wayne, M.; Wolf, M.; Woodard, A.; Antonelli, L.; Brinson, J.; Bylsma, B.; Durkin, L. S.; Flowers, S.; Hart, A.; Hill, C.; Hughes, R.; Ji, W.; Kotov, K.; Ling, T. Y.; Liu, B.; Luo, W.; Puigh, D.; Rodenburg, M.; Winer, B. L.; Wulsin, H. W.; Driga, O.; Elmer, P.; Hardenbrook, J.; Hebda, P.; Koay, S. A.; Lujan, P.; Marlow, D.; Medvedeva, T.; Mooney, M.; Olsen, J.; Palmer, C.; Piroué, P.; Saka, H.; Stickland, D.; Tully, C.; Zuranski, A.; Malik, S.; Barnes, V. E.; Benedetti, D.; Bortoletto, D.; Gutay, L.; Jha, M. K.; Jones, M.; Jung, K.; Miller, D. H.; Neumeister, N.; Radburn-Smith, B. C.; Shi, X.; Shipsey, I.; Silvers, D.; Sun, J.; Svyatkovskiy, A.; Wang, F.; Xie, W.; Xu, L.; Parashar, N.; Stupak, J.; Adair, A.; Akgun, B.; Chen, Z.; Ecklund, K. M.; Geurts, F. J. M.; Guilbaud, M.; Li, W.; Michlin, B.; Northup, M.; Padley, B. P.; Redjimi, R.; Roberts, J.; Rorie, J.; Tu, Z.; Zabel, J.; Betchart, B.; Bodek, A.; de Barbaro, P.; Demina, R.; Eshaq, Y.; Ferbel, T.; Galanti, M.; Garcia-Bellido, A.; Han, J.; Harel, A.; Hindrichs, O.; Khukhunaishvili, A.; Petrillo, G.; Tan, P.; Verzetti, M.; Arora, S.; Barker, A.; Chou, J. P.; Contreras-Campana, C.; Contreras-Campana, E.; Duggan, D.; Ferencek, D.; Gershtein, Y.; Gray, R.; Halkiadakis, E.; Hidas, D.; Hughes, E.; Kaplan, S.; Kunnawalkam Elayavalli, R.; Lath, A.; Nash, K.; Panwalkar, S.; Park, M.; Salur, S.; Schnetzer, S.; Sheffield, D.; Somalwar, S.; Stone, R.; Thomas, S.; Thomassen, P.; Walker, M.; Foerster, M.; Riley, G.; Rose, K.; Spanier, S.; York, A.; Bouhali, O.; Castaneda Hernandez, A.; Dalchenko, M.; De Mattia, M.; Delgado, A.; Dildick, S.; Eusebi, R.; Gilmore, J.; Kamon, T.; Krutelyov, V.; Mueller, R.; Osipenkov, I.; Pakhotin, Y.; Patel, R.; Perloff, A.; Rose, A.; Safonov, A.; Tatarinov, A.; Ulmer, K. A.; Akchurin, N.; Cowden, C.; Damgov, J.; Dragoiu, C.; Dudero, P. R.; Faulkner, J.; Kunori, S.; Lamichhane, K.; Lee, S. W.; Libeiro, T.; Undleeb, S.; Volobouev, I.; Appelt, E.; Delannoy, A. G.; Greene, S.; Gurrola, A.; Janjam, R.; Johns, W.; Maguire, C.; Mao, Y.; Melo, A.; Ni, H.; Sheldon, P.; Snook, B.; Tuo, S.; Velkovska, J.; Xu, Q.; Arenton, M. W.; Cox, B.; Francis, B.; Goodell, J.; Hirosky, R.; Ledovskoy, A.; Li, H.; Lin, C.; Neu, C.; Sinthuprasith, T.; Sun, X.; Wang, Y.; Wolfe, E.; Wood, J.; Xia, F.; Clarke, C.; Harr, R.; Karchin, P. E.; Kottachchi Kankanamge Don, C.; Lamichhane, P.; Sturdy, J.; Belknap, D. A.; Carlsmith, D.; Cepeda, M.; Dasu, S.; Dodd, L.; Duric, S.; Gomber, B.; Grothe, M.; Hall-Wilton, R.; Herndon, M.; Hervé, A.; Klabbers, P.; Lanaro, A.; Levine, A.; Long, K.; Loveless, R.; Mohapatra, A.; Ojalvo, I.; Perry, T.; Pierro, G. A.; Polese, G.; Ruggles, T.; Sarangi, T.; Savin, A.; Sharma, A.; Smith, N.; Smith, W. H.; Taylor, D.; Woods, N.

    2017-01-01

    This paper describes the CMS trigger system and its performance during Run 1 of the LHC. The trigger system consists of two levels designed to select events of potential physics interest from a GHz (MHz) interaction rate of proton-proton (heavy ion) collisions. The first level of the trigger is implemented in hardware, and selects events containing detector signals consistent with an electron, photon, muon, τ lepton, jet, or missing transverse energy. A programmable menu of up to 128 object-based algorithms is used to select events for subsequent processing. The trigger thresholds are adjusted to the LHC instantaneous luminosity during data taking in order to restrict the output rate to 100 kHz, the upper limit imposed by the CMS readout electronics. The second level, implemented in software, further refines the purity of the output stream, selecting an average rate of 400 Hz for offline event storage. The objectives, strategy and performance of the trigger system during the LHC Run 1 are described.

  7. Results of on-line tests of the ENABLE prototype, a 2nd level trigger processor for the TRT of ATLAS/LHC

    SciTech Connect

    Noffz, K.H.; Kugel, A.; Klefenz, F.; Zoz, R.; Maenner, R.

    1994-12-31

    The Enable Machine is a systolic 2nd level trigger processor for the transition radiation tracker (TRT) of ATLAS/LHC. The task of the processor is to find the best candidate for a lepton track in a high background of pions according to the EAST benchmark algorithm in less than 10 {mu}s. As described earlier, this is done in three steps. First all interesting tracks are histogrammed by accumulating for each track the coincidences between the track mask and the region-of-interest (RoI). Next the best defined track is identified. Eventually this track is classified as e or {pi}. A prototype has been developed and tested within the EAST/RD-11 collaboration at CERN. It operates at 50 MHz and finds up to 400 tracks in less than 10 {mu}s. It is assembled of an interface board and one or more histogrammer boards. The modular design makes the Enable Machine easily scalable. The histogrammer units are systolic arrays consisting of a matrix of 36 field programmable gate arrays. Through this it is possible to optimize the trigger algorithm, to adapt it to a changed detector setup, and even to implement completely new algorithms. For the beam tests in autumn 1993 at CERN the overall functionality within the detector environment could be shown. The authors were able to link successfully the Enable prototype to the detector raw data stream as well as to the data acquisition.

  8. Ground Level Observations of a Possible Downward-Beamed TGF during a Rocket-Triggered Lightning Flash at Camp Blanding, Florida in August 2014

    NASA Astrophysics Data System (ADS)

    Bozarth, A.; Dwyer, J. R.; Cramer, E. S.; Rassoul, H.; Uman, M. A.; Jordan, D.; Grove, J. E.

    2015-12-01

    Ground level high-energy observations of an August 2014 rocket-triggered lightning event at the International Center for Lightning Research and Testing (ICLRT) in Camp Blanding, Florida show a 180 µs burst of multiple-MeV photons during the latter part of the Upward Positive Leader (UPL) phase of an altitude-triggered lightning flash, following the first, truncated return stroke. The timing and waveform profile being atypical from x-ray emissions from lightning leaders, our observations suggest the occurrence of a downward beamed terrestrial gamma ray flash (TGF). Instrumentation operating during this event include a set of 16 NaI(TI)/PMT detectors plus 7 1-m2 plastic scintillation detectors spread across the 1 km2 facility, with 38 additional Na(TI)/PMT detectors located inside the 1"-thick Pb-shielded x-ray camera and an x-ray spectrometer. Comparing the location and energy data from these detectors to Monte Carlo simulations of TGFs from the REAM code developed by Dwyer [2003], our analysis investigates possible TGF production regions and determines the likelihood of the observed high-energy emissions being produced by a TGF inside the thunderstorm.

  9. FPGA Coprocessor for Accelerated Classification of Images

    NASA Technical Reports Server (NTRS)

    Pingree, Paula J.; Scharenbroich, Lucas J.; Werne, Thomas A.

    2008-01-01

    An effort related to that described in the preceding article focuses on developing a spaceborne processing platform for fast and accurate onboard classification of image data, a critical part of modern satellite image processing. The approach again has been to exploit the versatility of recently developed hybrid Virtex-4FX field-programmable gate array (FPGA) to run diverse science applications on embedded processors while taking advantage of the reconfigurable hardware resources of the FPGAs. In this case, the FPGA serves as a coprocessor that implements legacy C-language support-vector-machine (SVM) image-classification algorithms to detect and identify natural phenomena such as flooding, volcanic eruptions, and sea-ice break-up. The FPGA provides hardware acceleration for increased onboard processing capability than previously demonstrated in software. The original C-language program demonstrated on an imaging instrument aboard the Earth Observing-1 (EO-1) satellite implements a linear-kernel SVM algorithm for classifying parts of the images as snow, water, ice, land, or cloud or unclassified. Current onboard processors, such as on EO-1, have limited computing power, extremely limited active storage capability and are no longer considered state-of-the-art. Using commercially available software that translates C-language programs into hardware description language (HDL) files, the legacy C-language program, and two newly formulated programs for a more capable expanded-linear-kernel and a more accurate polynomial-kernel SVM algorithm, have been implemented in the Virtex-4FX FPGA. In tests, the FPGA implementations have exhibited significant speedups over conventional software implementations running on general-purpose hardware.

  10. Pharmacological Levels of Withaferin A (Withania somnifera) Trigger Clinically Relevant Anticancer Effects Specific to Triple Negative Breast Cancer Cells

    PubMed Central

    Szarc vel Szic, Katarzyna; Op de Beeck, Ken; Ratman, Dariusz; Wouters, An; Beck, Ilse M.; Declerck, Ken; Heyninck, Karen; Fransen, Erik; Bracke, Marc; De Bosscher, Karolien; Lardon, Filip; Van Camp, Guy; Berghe, Wim Vanden

    2014-01-01

    Withaferin A (WA) isolated from Withania somnifera (Ashwagandha) has recently become an attractive phytochemical under investigation in various preclinical studies for treatment of different cancer types. In the present study, a comparative pathway-based transcriptome analysis was applied in epithelial-like MCF-7 and triple negative mesenchymal MDA-MB-231 breast cancer cells exposed to different concentrations of WA which can be detected systemically in in vivo experiments. Whereas WA treatment demonstrated attenuation of multiple cancer hallmarks, the withanolide analogue Withanone (WN) did not exert any of the described effects at comparable concentrations. Pathway enrichment analysis revealed that WA targets specific cancer processes related to cell death, cell cycle and proliferation, which could be functionally validated by flow cytometry and real-time cell proliferation assays. WA also strongly decreased MDA-MB-231 invasion as determined by single-cell collagen invasion assay. This was further supported by decreased gene expression of extracellular matrix-degrading proteases (uPA, PLAT, ADAM8), cell adhesion molecules (integrins, laminins), pro-inflammatory mediators of the metastasis-promoting tumor microenvironment (TNFSF12, IL6, ANGPTL2, CSF1R) and concomitant increased expression of the validated breast cancer metastasis suppressor gene (BRMS1). In line with the transcriptional changes, nanomolar concentrations of WA significantly decreased protein levels and corresponding activity of uPA in MDA-MB-231 cell supernatant, further supporting its anti-metastatic properties. Finally, hierarchical clustering analysis of 84 chromatin writer-reader-eraser enzymes revealed that WA treatment of invasive mesenchymal MDA-MB-231 cells reprogrammed their transcription levels more similarly towards the pattern observed in non-invasive MCF-7 cells. In conclusion, taking into account that sub-cytotoxic concentrations of WA target multiple metastatic effectors in therapy

  11. Parallel Hough Transform-based straight line detection and its FPGA implementation in embedded vision.

    PubMed

    Lu, Xiaofeng; Song, Li; Shen, Sumin; He, Kang; Yu, Songyu; Ling, Nam

    2013-07-17

    Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

  12. Studying work practices: a key factor in understanding accidents on the level triggered by a balance disturbance.

    PubMed

    Derosier, C; Leclercq, S; Rabardel, P; Langa, P

    2008-12-01

    Accidents on the level (AOL) rank second amongst the most numerous and serious occupational accidents with days lost in France and are a major health and safety problem in every sector of activity. The case study described in this paper was conducted at a metallurgical company with 300 employees. The aims of this work were dual: 1) to extend the general knowledge required for preventing these accidents; 2) to propose prevention measures to this company. Existing data on company occupational accidents were gathered and analysed to identify a work situation that appeared likely to cause AOL. This work situation was analysed in detail. Several risk factors were identified within this work situation, by way of interviews with 12 operators. These risk factors concerned various dimensions of the work situation, particularly its physical dimension (e.g. templates structure) and organisational dimension (e.g. parts availability). Interviews were conducted, focusing on risk factors perceived by operators and involving allo-confrontations based on accounts of four AOL occurring in this situation. Allo-confrontations were interviews confronting operators with a risk occupational situation that was accidental for one of their colleagues, the latter being absent from the interview. Results highlighted the fact that the work practices implemented are key factors in understanding these accidents. This study underlines the role of work practices in AOL causality and prevention. It also provides explanations associated with various work situation dimensions involving adoption of more or less safe work practices. AOL are serious and frequent in occupational situations. Injury claims analysis and interviews in an industrial company emphasise the specific characteristics of an occupational situation and of prevention actions forming the basis of an intervention. The need for a better understanding of factors affecting work practice is highlighted in relation to research.

  13. EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER.

    SciTech Connect

    HOFF, L.T.

    2005-10-10

    The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control.

  14. RSA Power Analysis Obfuscation: A Dynamic FPGA Architecture

    DTIC Science & Technology

    2012-03-01

    research provides a VHDL coded dynamic architecture for synthesization on a Xilinx Virtex-5 FPGA. This architecture provides two-way communication...Component Under Test (CUT) is the dynamic RSA implementation. This dynamic hardware is synthesized from VHDL onto a Xilinx Virtex-5 FPGA. The built in...The hardware platform used for this research is a the Xil- inx Virtex-5 FX FPGA. VHDL code is synthesized using the Xilinx design suite and downloaded

  15. 3D FFTs on a Single FPGA.

    PubMed

    Humphries, Benjamin; Zhang, Hansen; Sheng, Jiayi; Landaverde, Raphael; Herbordt, Martin C

    2014-05-01

    The 3D FFT is critical in many physical simulations and image processing applications. On FPGAs, however, the 3D FFT was thought to be inefficient relative to other methods such as convolution-based implementations of multi-grid. We find the opposite: a simple design, operating at a conservative frequency, takes 4μs for 16(3), 21μs for 32(3), and 215μs for 64(3) single precision data points. The first two of these compare favorably with the 25μs and 29μs obtained running on a current Nvidia GPU. Some broader significance is that this is a critical piece in implementing a large scale FPGA-based MD engine: even a single FPGA is capable of keeping the FFT off of the critical path for a large fraction of possible MD simulations.

  16. Multigrid shallow water equations on an FPGA

    NASA Astrophysics Data System (ADS)

    Jeffress, Stephen; Duben, Peter; Palmer, Tim

    2015-04-01

    A novel computing technology for multigrid shallow water equations is investigated. As power consumption begins to constrain traditional supercomputing advances, weather and climate simulators are exploring alternative technologies that achieve efficiency gains through massively parallel and low power architectures. In recent years FPGA implementations of reduced complexity atmospheric models have shown accelerated speeds and reduced power consumption compared to multi-core CPU integrations. We continue this line of research by designing an FPGA dataflow engine for a mulitgrid version of the 2D shallow water equations. The multigrid algorithm couples grids of variable resolution to improve accuracy. We show that a significant reduction of precision in the floating point representation of the fine grid variables allows greater parallelism and thus improved overall peformance while maintaining accurate integrations. Preliminary designs have been constructed by software emulation. Results of the hardware implementation will be presented at the conference.

  17. FPGA Based Reconfigurable ATM Switch Test Bed

    NASA Technical Reports Server (NTRS)

    Chu, Pong P.; Jones, Robert E.

    1998-01-01

    Various issues associated with "FPGA Based Reconfigurable ATM Switch Test Bed" are presented in viewgraph form. Specific topics include: 1) Network performance evaluation; 2) traditional approaches; 3) software simulation; 4) hardware emulation; 5) test bed highlights; 6) design environment; 7) test bed architecture; 8) abstract sheared-memory switch; 9) detailed switch diagram; 10) traffic generator; 11) data collection circuit and user interface; 12) initial results; and 13) the following conclusions: Advances in FPGA make hardware emulation feasible for performance evaluation, hardware emulation can provide several orders of magnitude speed-up over software simulation; due to the complexity of hardware synthesis process, development in emulation is much more difficult than simulation and requires knowledge in both networks and digital design.

  18. Algorithm and implementation of muon trigger and data transmission system for barrel-endcap overlap region of the CMS detector

    NASA Astrophysics Data System (ADS)

    Zabolotny, W. M.; Byszuk, A.

    2016-03-01

    The CMS experiment Level-1 trigger system is undergoing an upgrade. In the barrel-endcap transition region, it is necessary to merge data from 3 types of muon detectors—RPC, DT and CSC. The Overlap Muon Track Finder (OMTF) uses the novel approach to concentrate and process those data in a uniform manner to identify muons and their transversal momentum. The paper presents the algorithm and FPGA firmware implementation of the OMTF and its data transmission system in CMS. It is foreseen that the OMTF will be subject to significant changes resulting from optimization which will be done with the aid of physics simulations. Therefore, a special, high-level, parameterized HDL implementation is necessary.

  19. FPGA Flash Memory High Speed Data Acquisition

    NASA Technical Reports Server (NTRS)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  20. An FPGA-based reconfigurable DDC algorithm

    NASA Astrophysics Data System (ADS)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  1. Wearable FPGA based wireless sensor platform.

    PubMed

    Ahola, Tom; Korpinen, Pekka; Rakkola, Juha; Rämö, Teemu; Salminen, Jukka; Savolainen, Jari

    2007-01-01

    A new wearable sensor platform has been developed. It is based on a Field Programmable Gate Array (FPGA) device. Because of this the hardware is very flexible and gives the platform unique opportunities for research of a wide range of architectures, applications and signal processing algorithms. The platform has been named NWSP, for Nokia Wrist- Attached Sensor Platform. This document describes the hardware, the firmware and applications of the platform.

  2. TOT measurement implemented in FPGA TDC

    NASA Astrophysics Data System (ADS)

    Fan, Huan-Huan; Cao, Ping; Liu, Shu-Bin; An, Qi

    2015-11-01

    Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity. This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates. Supported by National Natural Science Foundation of China (11079003, 10979003)

  3. Firearm trigger assembly

    DOEpatents

    Crandall, David L.; Watson, Richard W.

    2010-02-16

    A firearm trigger assembly for use with a firearm includes a trigger mounted to a forestock of the firearm so that the trigger is movable between a rest position and a triggering position by a forwardly placed support hand of a user. An elongated trigger member operatively associated with the trigger operates a sear assembly of the firearm when the trigger is moved to the triggering position. An action release assembly operatively associated with the firearm trigger assembly and a movable assembly of the firearm prevents the trigger from being moved to the triggering position when the movable assembly is not in the locked position.

  4. FPGA Implementation of Heart Rate Monitoring System.

    PubMed

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  5. Implementing a Digital Phasemeter in an FPGA

    NASA Technical Reports Server (NTRS)

    Rao, Shanti R.

    2008-01-01

    Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses, the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains. The firmware also does the following: Causes the FPGA to compute the frequencies of the input signals; Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and Provides data for use in diagnosis of communication failures. The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.

  6. FPGA remote update for nuclear environments

    SciTech Connect

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno; Correia, Carlos M.B.A.

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  7. Do Drug Treatment Facilities Increase Clients’ Exposure to Potential Neighborhood-Level Triggers for Relapse? A Small-Area Assessment of a Large, Public Treatment System

    PubMed Central

    2006-01-01

    Research on drug treatment facility locations has focused narrowly on the issue of geographic proximity to clients. We argue that neighborhood conditions should also enter into the facility location decision and illustrate a formal assessment of neighborhood conditions at facilities in a large, metropolitan area, taking into account conditions clients already face at home. We discuss choice and construction of small-area measures relevant to the drug treatment context, including drug activity, disadvantage, and violence as well as statistical comparisons of clients’ home and treatment locations with respect to these measures. Analysis of 22,707 clients discharged from 494 community-based outpatient and residential treatment facilities that received public funds during 1998–2000 in Los Angeles County revealed no significant mean differences between home and treatment neighborhoods. However, up to 20% of clients are exposed to markedly higher levels of disadvantage, violence, or drug activity where they attend treatment than where they live, suggesting that it is not uncommon for treatment locations to increase clients’ exposure to potential environmental triggers for relapse. Whereas on average both home and treatment locations exhibit higher levels of these measures than the household locations of the general population, substantial variability in public treatment clients’ home neighborhoods calls into question the notion that they hail exclusively from poor, high drug activity areas. Shortcomings of measures available for neighborhood assessment of treatment locations and implications of the findings for other areas of treatment research are also discussed. PMID:16736365

  8. Embedded EMD algorithm within an FPGA-based design to classify nonlinear SDOF systems

    NASA Astrophysics Data System (ADS)

    Jones, Jonathan D.; Pei, Jin-Song; Wright, Joseph P.; Tull, Monte P.

    2010-04-01

    Compared with traditional microprocessor-based systems, rapidly advancing field-programmable gate array (FPGA) technology offers a more powerful, efficient and flexible hardware platform. An FPGA and microprocessor (i.e., hardware and software) co-design is developed to classify three types of nonlinearities (including linear, hardening and softening) of a single-degree-of-freedom (SDOF) system subjected to free vibration. This significantly advances the team's previous work on using FPGAs for wireless structural health monitoring. The classification is achieved by embedding two important algorithms - empirical mode decomposition (EMD) and backbone curve analysis. Design considerations to embed EMD in FPGA and microprocessor are discussed. In particular, the implementation of cubic spline fitting and the challenges encountered using both hardware and software environments are discussed. The backbone curve technique is fully implemented within the FPGA hardware and used to extract instantaneous characteristics from the uniformly distributed data sets produced by the EMD algorithm as presented in a previous SPIE conference by the team. An off-the-shelf high-level abstraction tool along with the MATLAB/Simulink environment is utilized to manage the overall FPGA and microprocessor co-design. Given the limited computational resources of an embedded system, we strive for a balance between the maximization of computational efficiency and minimization of resource utilization. The value of this study lies well beyond merely programming existing algorithms in hardware and software. Among others, extensive and intensive judgment is exercised involving experiences and insights with these algorithms, which renders processed instantaneous characteristics of the signals that are well-suited for wireless transmission.

  9. Time Triggered Protocol (TTP) for Integrated Modular Avionics

    NASA Technical Reports Server (NTRS)

    Motzet, Guenter; Gwaltney, David A.; Bauer, Guenther; Jakovljevic, Mirko; Gagea, Leonard

    2006-01-01

    Traditional avionics computing systems are federated, with each system provided on a number of dedicated hardware units. Federated applications are physically separated from one another and analysis of the systems is undertaken individually. Integrated Modular Avionics (IMA) takes these federated functions and integrates them on a common computing platform in a tightly deterministic distributed real-time network of computing modules in which the different applications can run. IMA supports different levels of criticality in the same computing resource and provides a platform for implementation of fault tolerance through hardware and application redundancy. Modular implementation has distinct benefits in design, testing and system maintainability. This paper covers the requirements for fault tolerant bus systems used to provide reliable communication between IMA computing modules. An overview of the Time Triggered Protocol (TTP) specification and implementation as a reliable solution for IMA systems is presented. Application examples in aircraft avionics and a development system for future space application are covered. The commercially available TTP controller can be also be implemented in an FPGA and the results from implementation studies are covered. Finally future direction for the application of TTP and related development activities are presented.

  10. The effects of paeoniflorin injection on soluble triggering receptor expressed on myeloid-1 (sTREM-1) levels in severe septic rats

    PubMed Central

    Xu, Jie; Wang, Yi-Min; Ji, Ming-Suo; Liu, Fu-Shan

    2016-01-01

    Paeoniflorin (PAE) is the most abundant compound in Xuebijing injection widely used to treat sepsis. We aimed to investigate effect of PAE on expression of soluble triggering receptor expressed on myeloid cells-1 (sTREM-1) in a rat model of sepsis. Wistar rats were divided into Normal, Model, and PAE groups (n=20 each). Endotoxin was administrated at 5 mg/ml/kg in Model and PAE rats to establish rat sepsis model. 1 h after endotoxin administration, PAE was administrated at 4 ml/kg in PAE group once per day for 3 days. Routine blood tests and biochemical indexes were assessed, including aspartate aminotransferase (AST) and creatine kinase-MB (CK-MB). The plasma sTREM-1 level was measured using quantitative ELISA. At the end of experiment, the small intestine, liver, kidney and lung were subjected to pathological examinations. A rat model of sepsis-induced multiple organ dysfunction syndrome (MODS) was established successfully with endotoxin administration (5 mg/ml/kg), evidenced by histo-pathological examinations, routine blood tests and biochemical indexes: platelet count decreased and white blood cell count increased (p<0.05), CK-MB and AST increased (p<0.05). PAE treatment significantly reduced the plasma levels of AST, CK-MB, and sTREM-1, compared to Model group (p<0.05). Meanwhile, sepsis-induced damages in the liver, lung, stomach and intestinal mucosa were also markedly ameliorated by PAE treatment. PAE demonstrated a significantly protective effect in a rat model of sepsis by decreasing plasma sTREM-1 level, reducing inflammation, preventing MODS and protecting organ functions. PMID:27847433

  11. Modulation of TGFbeta 2 levels by lamin A in U2-OS osteoblast-like cells: understanding the osteolytic process triggered by altered lamins

    PubMed Central

    Evangelisti, Camilla; Bernasconi, Pia; Cavalcante, Paola; Cappelletti, Cristina; D'Apice, Maria Rosaria; Sbraccia, Paolo; Novelli, Giuseppe; Prencipe, Sabino; Lemma, Silvia; Baldini, Nicola; Avnet, Sofia; Squarzoni, Stefano; Martelli, Alberto M.; Lattanzi, Giovanna

    2015-01-01

    Transforming growth factor beta (TGFbeta) plays an essential role in bone homeostasis and deregulation of TGFbeta occurs in bone pathologies. Patients affected by Mandibuloacral Dysplasia (MADA), a progeroid disease linked to LMNA mutations, suffer from an osteolytic process. Our previous work showed that MADA osteoblasts secrete excess amount of TGFbeta 2, which in turn elicits differentiation of human blood precursors into osteoclasts. Here, we sought to determine how altered lamin A affects TGFbeta signaling. Our results show that wild-type lamin A negatively modulates TGFbeta 2 levels in osteoblast-like U2-OS cells, while the R527H mutated prelamin A as well as farnesylated prelamin A do not, ultimately leading to increased secretion of TGFbeta 2. TGFbeta 2 in turn, triggers the Akt/mTOR pathway and upregulates osteoprotegerin and cathepsin K. TGFbeta 2 neutralization rescues Akt/mTOR activation and the downstream transcriptional effects, an effect also obtained by statins or RAD001 treatment. Our results unravel an unexpected role of lamin A in TGFbeta 2 regulation and indicate rapamycin analogs and neutralizing antibodies to TGFbeta 2 as new potential therapeutic tools for MADA. PMID:25823658

  12. Optimizing Radiation Dose Levels in Prospectively Electrocardiogram-Triggered Coronary Computed Tomography Angiography Using Iterative Reconstruction Techniques: A Phantom and Patient Study

    PubMed Central

    Hou, Yang; Zheng, Jiahe; Wang, Yuke; Yu, Mei; Vembar, Mani; Guo, Qiyong

    2013-01-01

    Aim To investigate the potential of reducing the radiation dose in prospectively electrocardiogram-triggered coronary computed tomography angiography (CCTA) while maintaining diagnostic image quality using an iterative reconstruction technique (IRT). Methods and Materials Prospectively-gated CCTA were first performed on a phantom using 256-slice multi-detector CT scanner at 120 kVp, with the tube output gradually reduced from 210 mAs (Group A) to 125, 105, 84, and 63 mAs (Group B–E). All scans were reconstructed using filtered back projection (FBP) algorithm and five IRT levels (L2-6), image quality (IQ) assessment was performed. Based on the IQ assessment, Group D(120 kVp, 84 mAs) reconstructed with L5 was found to provide IQ comparable to that of Group A with FBP. In the patient study, 21 patients underwent CCTA using 120 kV, 210 mAs with FBP reconstruction (Group 1) followed by 36 patients scanned with 120 kV, 84 mAs with IRT L5 (Group 2). Subjective and objective IQ and effective radiation dose were compared between two groups. Results In the phantom scans, there were no significant differences in image noise, contrast-to-noise ratio (CNR) and modulation transfer function (MTF) curves between Group A and the 84 mAs, 63 mAs groups (Groups D and E). Group D (120 kV, 84 mAs and L5) provided an optimum balance, producing equivalent image quality to Group A, at the lowest possible radiation dose. In the patient study, there were no significant difference in image noise, signal-to-noise ratio (SNR) and CNR between Group 1 and Group 2 (p = 0.71, 0.31, 0.5, respectively). The effective radiation dose in Group 2 was 1.21±0.14 mSv compared to 3.20±0.58 mSv (Group 1), reflecting dose savings of 62.5% (p<0.05). Conclusion iterative reconstruction technique used in prospectively ECG-triggered 256-slice coronary CTA can provide radiation dose reductions of up to 62.5% with acceptable image quality. PMID:23437110

  13. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA)

    DTIC Science & Technology

    2015-03-01

    microprocessor . 3.1. Asynchronous FPGA Overview In terms of the major building blocks, the asynchronous FPGA (AFPGA) architecture looks like a traditional...devices—from O(N1/2) to O(N1/3), where N is the number of devices in the system. 3D chip stacking has been proposed as a way to improve microprocessor

  14. FPGA development for high altitude subsonic parachute testing

    NASA Technical Reports Server (NTRS)

    Kowalski, James E.; Gromov, Konstantin G.; Konefat, Edward H.

    2005-01-01

    This paper describes a rapid, top down requirements-driven design of a Field Programmable Gate Array (FPGA) used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and control storage of telemetry data from multiple sensors throughout launch, ascent, deployment and descent phases of the subsonic parachute test.

  15. FPGA development for high altitude subsonic parachute testing

    NASA Technical Reports Server (NTRS)

    Kowalski, James E.; Konefat, Edward H.; Gromovt, Konstantin

    2005-01-01

    This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and store data from multiple sensors at multiple rates during launch, ascent, deployment and descent phases of the subsonic parachute test.

  16. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lamanna, G.; Lonardo, A.; Lo Cicero, F.; Paolucci, P. S.; Pantaleo, F.; Rossetti, D.; Simula, F.; Sozzi, M.; Tosoratto, L.; Vicini, P.

    2014-02-01

    NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities.

  17. A digital pulsar backend based on FPGA

    NASA Astrophysics Data System (ADS)

    Luo, Jin-Tao; Chen, Lan; Han, Jin-Lin; Esamdin, Ali; Wu, Ya-Jun; Li, Zhi-Xuan; Hao, Long-Fei; Zhang, Xiu-Zhong

    2017-01-01

    A digital pulsar backend based on a Field Programmable Gate Array (FPGA) is developed. It is designed for incoherent de-dispersion of pulsar observations and has a maximum bandwidth of 512 MHz. The channel bandwidth is fixed to 1 MHz, and the highest time resolution is 10 {{μ }} s. Testing observations were carried out using the Urumqi 25-m telescope administered by Xinjiang Astronomical Observatory and the Kunming 40-m telescope administered by Yunnan Observatories, targeting PSR J0332+5434 in the L band and PSR J0437–4715 in the S band, respectively. The successful observation of PSR J0437–4715 demonstrates its ability to observe millisecond pulsars.

  18. Hardware Demonstrator of a Level-1 Track Finding Algorithm with FPGAs for the Phase II CMS Experiment

    NASA Astrophysics Data System (ADS)

    Cieri, D.; CMS Collaboration

    2016-10-01

    At the HL-LHC, proton bunches collide every 25 ns, producing an average of 140 pp interactions per bunch crossing. To operate in such an environment, the CMS experiment will need a Level-1 (L1) hardware trigger, able to identify interesting events within a latency of 12.5 μs. This novel L1 trigger will make use of data coming from the silicon tracker to constrain the trigger rate. Goal of this new track trigger will be to build L1 tracks from the tracker information. The architecture that will be implemented in future to process tracker data is still under discussion. One possibility is to adopt a system entirely based on FPGA electronic. The proposed track finding algorithm is based on the Hough transform method. The algorithm has been tested using simulated pp collision data and it is currently being demonstrated in hardware, using the “MP7”, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s. Two different implementations of the Hough transform technique are currently under investigation: one utilizes a systolic array to represent the Hough space, while the other exploits a pipelined approach.

  19. The Ordovician Las Chacritas pluton (Sierra de Humaya, NW Argentina): origin and emplacement triggered by lateral shortening and magmatic stoping at mid-crustal level

    NASA Astrophysics Data System (ADS)

    Larrovere, Mariano A.; Alasino, Pablo H.; de los Hoyos, Camilo R.; Willner, Arne P.

    2015-04-01

    Field relationships and structural studies combined with in situ U-Th-Pb dating of monazite from Las Chacritas pluton (LCP), Sierra de Humaya, provide insight into the emplacement of peraluminous magmas triggered by lateral shortening of the host rock and magmatic stoping at a mid-crustal level of a retro-arc zone in a convergent orogen. Modal and chemical compositions indicate that the LCP is composed of two main igneous units of peraluminous granitoids. The predominant two-mica granitoids were generated by interaction of crustal rocks with mafic or mafic-derived magmas and/or crystal-rich magmas that entrained residual phases, whereas less abundant leucocratic granitoids may have been originated by partial melting of metasedimentary rocks. The calculated crystallization age of 474 ± 4 Ma is consistent with Ordovician ages (477-470 Ma) of the high-grade metamorphic rocks, indicating concomitant magmatism and metamorphism during the Famatinian orogeny. The LCP was emplaced in the middle crust at a maximum depth of ~14.5 km, where attendant fracturing and ductile deformation were active. Field evidence shows strong temporal and spatial relationships between host rock ductile deformation and the emplacement of the pluton such as folding and strike deflection of the host rock layering and folded concordant leucocratic sheets with magmatic fabrics. This suggests that material transfer processes like lateral wall rock displacement (lateral shortening) was a viable mechanism for the emplacement of the LCP. However, cross-sectional restoration and field evidence such as wall rock xenoliths and intrusive truncations of the host rock foliation and fold traces suggest that magmatic stoping was a complementary mechanism to create the necessary space for the emplacement of the LCP. This work supports previous studies showing that participation of multiple material transfer processes are the rule rather than the exception in the emplacement of plutons.

  20. Optically triggered infrared photodetector.

    PubMed

    Ramiro, Íñigo; Martí, Antonio; Antolín, Elisa; López, Esther; Datas, Alejandro; Luque, Antonio; Ripalda, José M; González, Yolanda

    2015-01-14

    We demonstrate a new class of semiconductor device: the optically triggered infrared photodetector (OTIP). This photodetector is based on a new physical principle that allows the detection of infrared light to be switched ON and OFF by means of an external light. Our experimental device, fabricated using InAs/AlGaAs quantum-dot technology, demonstrates normal incidence infrared detection in the 2-6 μm range. The detection is optically triggered by a 590 nm light-emitting diode. Furthermore, the detection gain is achieved in our device without an increase of the noise level. The novel characteristics of OTIPs open up new possibilities for third generation infrared imaging systems ( Rogalski, A.; Antoszewski, J.; Faraone, L. J. Appl. Phys. 2009, 105 (9), 091101).

  1. Latency study of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

    NASA Astrophysics Data System (ADS)

    Meng, X. T.; Levin, D. S.; Chapman, J. W.; Li, D. C.; Yao, Z. E.; Zhou, B.

    2017-02-01

    The High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by the CERN Microelectronics group, has been proposed for the digitization of the thin-Resistive Plate Chambers (tRPC) in the ATLAS Muon Spectrometer Phase-1 upgrade project. These chambers, to be staged for higher luminosity LHC operation, will increase trigger acceptance and reduce or eliminate the fake muon trigger rates in the barrel-endcap transition region, corresponding to pseudo-rapidity range 1<|η|<1.3. Low level trigger candidates must be flagged within a maximum latency of 1075 ns, thus imposing stringent signal processing time performance requirements on the readout system in general, and on the digitization electronics in particular. This paper investigates the HPTDC signal latency performance based on a specially designed evaluation board coupled with an external FPGA evaluation board, when operated in triggerless mode, and under hit rate conditions expected in Phase-I. This hardware based study confirms previous simulations and demonstrates that the HPTDC in triggerless operation satisfies the digitization timing requirements in both leading edge and pair modes.

  2. Direct digital synthesis: some options for FPGA implementation

    NASA Astrophysics Data System (ADS)

    Dick, Chris H.; Harris, Fred J.

    1999-08-01

    Direct digital synthesizers (DDS), or numerically controlled oscillators, are a functional requirement of virtually every digital communications system, including modems and software defined radios. Frequency synthesis is commonly realized using application specific standard parts or as software on a DSP processor. With ever increasing amounts of digital signal processing being realized using field programmable gate array (FPGA) based hardware platforms, it is fruitful to explore various DDS architectures and evaluate the many possible architecture/performance tradeoffs with a view to FPGA implementation. This paper describes three DDS architectures and presents several designs that illustrate DDS performance and highlight design considerations for FPGA implementation.

  3. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

    NASA Astrophysics Data System (ADS)

    Abbas, Syed Haider; Jang, Jae-Kyeong; Lee, Jung-Ryul; Kim, Zaeill

    2016-07-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  4. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts.

    PubMed

    Abbas, Syed Haider; Jang, Jae-Kyeong; Lee, Jung-Ryul; Kim, Zaeill

    2016-07-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  5. A distributed Canny edge detector: algorithm and FPGA implementation.

    PubMed

    Xu, Qian; Varadarajan, Srenivas; Chakrabarti, Chaitali; Karam, Lina J

    2014-07-01

    The Canny edge detector is one of the most widely used edge detection algorithms due to its superior performance. Unfortunately, not only is it computationally more intensive as compared with other edge detection algorithms, but it also has a higher latency because it is based on frame-level statistics. In this paper, we propose a mechanism to implement the Canny algorithm at the block level without any loss in edge detection performance compared with the original frame-level Canny algorithm. Directly applying the original Canny algorithm at the block-level leads to excessive edges in smooth regions and to loss of significant edges in high-detailed regions since the original Canny computes the high and low thresholds based on the frame-level statistics. To solve this problem, we present a distributed Canny edge detection algorithm that adaptively computes the edge detection thresholds based on the block type and the local distribution of the gradients in the image block. In addition, the new algorithm uses a nonuniform gradient magnitude histogram to compute block-based hysteresis thresholds. The resulting block-based algorithm has a significantly reduced latency and can be easily integrated with other block-based image codecs. It is capable of supporting fast edge detection of images and videos with high resolutions, including full-HD since the latency is now a function of the block size instead of the frame size. In addition, quantitative conformance evaluations and subjective tests show that the edge detection performance of the proposed algorithm is better than the original frame-based algorithm, especially when noise is present in the images. Finally, this algorithm is implemented using a 32 computing engine architecture and is synthesized on the Xilinx Virtex-5 FPGA. The synthesized architecture takes only 0.721 ms (including the SRAM READ/WRITE time and the computation time) to detect edges of 512 × 512 images in the USC SIPI database when clocked at 100

  6. Multi-variants synthesis of Petri nets for FPGA devices

    NASA Astrophysics Data System (ADS)

    Bukowiec, Arkadiusz; Doligalski, Michał

    2015-09-01

    There is presented new method of synthesis of application specific logic controllers for FPGA devices. The specification of control algorithm is made with use of control interpreted Petri net (PT type). It allows specifying parallel processes in easy way. The Petri net is decomposed into state-machine type subnets. In this case, each subnet represents one parallel process. For this purpose there are applied algorithms of coloring of Petri nets. There are presented two approaches of such decomposition: with doublers of macroplaces or with one global wait place. Next, subnets are implemented into two-level logic circuit of the controller. The levels of logic circuit are obtained as a result of its architectural decomposition. The first level combinational circuit is responsible for generation of next places and second level decoder is responsible for generation output symbols. There are worked out two variants of such circuits: with one shared operational memory or with many flexible distributed memories as a decoder. Variants of Petri net decomposition and structures of logic circuits can be combined together without any restrictions. It leads to existence of four variants of multi-variants synthesis.

  7. The trigger system for the external target experiment in the HIRFL cooling storage ring

    NASA Astrophysics Data System (ADS)

    Li, Min; Zhao, Lei; Liu, Jin-Xin; Lu, Yi-Ming; Liu, Shu-Bin; An, Qi

    2016-08-01

    A trigger system was designed for the external target experiment in the Cooling Storage Ring (CSR) of the Heavy Ion Research Facility in Lanzhou (HIRFL). Considering that different detectors are scattered over a large area, the trigger system is designed based on a master-slave structure and fiber-based serial data transmission technique. The trigger logic is organized in hierarchies, and flexible reconfiguration of the trigger function is achieved based on command register access or overall field-programmable gate array (FPGA) logic on-line reconfiguration controlled by remote computers. We also conducted tests to confirm the function of the trigger electronics, and the results indicate that this trigger system works well. Supported by the National Natural Science Foundation of China (11079003), the Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), and the CAS Center for Excellence in Particle Physics (CCEPP).

  8. A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios

    NASA Astrophysics Data System (ADS)

    Ouedraogo, Ganda Stephane; Gautier, Matthieu; Sentieys, Olivier

    2014-12-01

    The field-programmable gate array (FPGA) technology is expected to play a key role in the development of software-defined radio (SDR) platforms. As this technology evolves, low-level designing methods for prototyping FPGA-based applications did not change throughout the decades. In the outstanding context of SDR, it is important to rapidly implement new waveforms to fulfill such a stringent flexibility paradigm. At the current time, different proposals have defined, through software-based approaches, some efficient methods to prototype SDR waveforms in a processor-based running environment. This paper describes a novel design flow for FPGA-based SDR applications. This flow relies upon high-level synthesis (HLS) principles and leverages the nascent HLS tools. Its entry point is a domain-specific language (DSL) which handles the complexity of programming an FPGA and integrates some SDR features so as to enable automatic waveform control generation from a data frame model. Two waveforms (IEEE 802.15.4 and IEEE 802.11a) have been designed and explored via this new methodology, and the results are highlighted in this paper.

  9. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    PubMed

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  10. Optimization of the Multi-Spectral Euclidean Distance Calculation for FPGA-based Spaceborne Systems

    NASA Technical Reports Server (NTRS)

    Cristo, Alejandro; Fisher, Kevin; Perez, Rosa M.; Martinez, Pablo; Gualtieri, Anthony J.

    2012-01-01

    Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, a FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used.

  11. Wire Position Monitoring with FPGA based Electronics

    SciTech Connect

    Eddy, N.; Lysenko, O.; /Fermilab

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 {Omega} striplines spaced 90{sup o} apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 {Omega} striplines spaced 90{sup o} apart. An FPGA based

  12. Stego on FPGA: an IWT approach.

    PubMed

    Ramalingam, Balakrishnan; Amirtharajan, Rengarajan; Rayappan, John Bosco Balaguru

    2014-01-01

    A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA).

  13. FPGA for Power Control of MSL Avionics

    NASA Technical Reports Server (NTRS)

    Wang, Duo; Burke, Gary R.

    2011-01-01

    A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

  14. FPGA-accelerated adaptive optics wavefront control

    NASA Astrophysics Data System (ADS)

    Mauch, S.; Reger, J.; Reinlein, C.; Appelfelder, M.; Goy, M.; Beckert, E.; Tünnermann, A.

    2014-03-01

    The speed of real-time adaptive optical systems is primarily restricted by the data processing hardware and computational aspects. Furthermore, the application of mirror layouts with increasing numbers of actuators reduces the bandwidth (speed) of the system and, thus, the number of applicable control algorithms. This burden turns out a key-impediment for deformable mirrors with continuous mirror surface and highly coupled actuator influence functions. In this regard, specialized hardware is necessary for high performance real-time control applications. Our approach to overcome this challenge is an adaptive optics system based on a Shack-Hartmann wavefront sensor (SHWFS) with a CameraLink interface. The data processing is based on a high performance Intel Core i7 Quadcore hard real-time Linux system. Employing a Xilinx Kintex-7 FPGA, an own developed PCie card is outlined in order to accelerate the analysis of a Shack-Hartmann Wavefront Sensor. A recently developed real-time capable spot detection algorithm evaluates the wavefront. The main features of the presented system are the reduction of latency and the acceleration of computation For example, matrix multiplications which in general are of complexity O(n3 are accelerated by using the DSP48 slices of the field-programmable gate array (FPGA) as well as a novel hardware implementation of the SHWFS algorithm. Further benefits are the Streaming SIMD Extensions (SSE) which intensively use the parallelization capability of the processor for further reducing the latency and increasing the bandwidth of the closed-loop. Due to this approach, up to 64 actuators of a deformable mirror can be handled and controlled without noticeable restriction from computational burdens.

  15. A Portable Laser Photoacoustic Methane Sensor Based on FPGA

    PubMed Central

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-01-01

    A portable laser photoacoustic sensor for methane (CH4) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated. PMID:27657079

  16. Electronic-generated holograms by FPGA and monochromatic LCD

    NASA Astrophysics Data System (ADS)

    Castillo-Atoche, A.; Pérez-Cortés, M.; López, M. A.; Ortiz-Gutiérrez, M.

    2006-02-01

    The majority of holograms are made using interference of light and computer-generated holograms. In this work we propose a technique in real time to generate digital holograms with a VLSI digital component, being specific FPGA and a liquid crystal device. The digital design with FPGA presents great advantage for its parallel procesing that carry out by its flexible structure, high integration and velocity. The design was verified using the platform MathLab/Simulink and Xilinx System Generator.

  17. A Portable Laser Photoacoustic Methane Sensor Based on FPGA.

    PubMed

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-09-21

    A portable laser photoacoustic sensor for methane (CH₄) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated.

  18. High Precision Digital Frequency Signal Source Based on FPGA

    NASA Astrophysics Data System (ADS)

    Yanbin, SHI; Jian, GUO; Ning, CUI

    The realization method of DDS technology is introduced, and its superior technical characteristics are analyzed in this paper. According to its characteristics, the high accuracy digital frequency signal source based on FPGA is designed. The simulation result indicated, compares with the traditional signal source, this type of signal source realized by the method of FPGA+DDS have many merits such as high precision and fast switch speed, which can satisfies the developing tendency of test facility.

  19. FPGA developments for the SPARTA project: Part 2

    NASA Astrophysics Data System (ADS)

    Goodsell, S. J.; Geng, D.; Fedrigo, E.; Soenke, C.; Donaldson, R.; Saunter, C. D.; Myers, R. M.; Basden, A. G.; Dipper, N. A.

    2006-06-01

    The European Southern Observatory (ESO) and Durham University's Centre for Advanced Instrumentation (CfAI) continue to progress the design of a next generation Adaptive Optics (AO) Real-Time Control System (RTCS). This common flexible platform, labelled SPARTA 'Standard Platform for Adaptive optics Real-Time Applications' will control the AO systems for a set of 2 nd generation VLT instrumentation, and will scale to implement the initial AO systems for the European Extremely Large Telescope (E-ELT). Durham has used Field Programmable Gate Arrays (FPGA) to design a front-end Wavefront Sensor (WFS) Processing Unit (WPU) for SPARTA. FPGA devices have been used to alleviate the highly parallel computationally intensive WPS processing task from system processors to increase the obtainable control loop frequency and reduce the computational latency in the control system. The FPGA device reduces WFS frames to gradient vectors before passing the data to the system processors. The FPGA allows the processors to deal with other tasks such as wavefront reconstruction, telemetry and real-time data recording, allowing for more complex adaptive control algorithms to be executed. Durham has design, coded, implemented and tested a FPGA core incorporating the VITA 17.1 standard serial Front Panel Data Port (sFPDP) protocol to allow a data transfer rate of 2.5Gbps -1 from the WFS Controller to the SPARTA platform. This paper overviews the SPARTA WPU requirements and design, the sFPDP FPGA Core and a description of the platform's implementation phase.

  20. Detector array control and triggering

    SciTech Connect

    Aiello, S.; Anzalone, A.; Bartolucci, M. |

    1998-08-01

    A commercial DSP-based board installed in a host-PC was employed for the fast, on-line and real-time computation of special algorithms, in order to perform event selection and operate as a 2nd level trigger. Moreover an ad hoc build interface, realized using PLDs with a view to connecting the DSP-board to the ADCs and to the data acquisition system, has been tested in order to evaluate the performances of these programmable devices used as a look-up-table and as a decisional part of a 1st level trigger.

  1. L1 track finding for a time multiplexed trigger

    NASA Astrophysics Data System (ADS)

    Cieri, D.; Brooke, J.; Grimes, M.; Newbold, D.; Harder, K.; Shepherd-Themistocleous, C.; Tomalin, I.; Vichoudis, P.; Reid, I.; Iles, G.; Hall, G.; James, T.; Pesaresi, M.; Rose, A.; Tapper, A.; Uchida, K.

    2016-07-01

    At the HL-LHC, proton bunches will cross each other every 25 ns, producing an average of 140 pp-collisions per bunch crossing. To operate in such an environment, the CMS experiment will need a L1 hardware trigger able to identify interesting events within a latency of 12.5 μs. The future L1 trigger will make use also of data coming from the silicon tracker to control the trigger rate. The architecture that will be used in future to process tracker data is still under discussion. One interesting proposal makes use of the Time Multiplexed Trigger concept, already implemented in the CMS calorimeter trigger for the Phase I trigger upgrade. The proposed track finding algorithm is based on the Hough Transform method. The algorithm has been tested using simulated pp-collision data. Results show a very good tracking efficiency. The algorithm will be demonstrated in hardware in the coming months using the MP7, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s.

  2. Asthma triggers (image)

    MedlinePlus

    ... common asthma triggers are mold, pets, dust, grasses, pollen, cockroaches, odors from chemicals, and smoke from cigarettes. ... common asthma triggers are mold, pets, dust, grasses, pollen, cockroaches, odors from chemicals, and smoke from cigarettes.

  3. FPGA-Based, Self-Checking, Fault-Tolerant Computers

    NASA Technical Reports Server (NTRS)

    Some, Raphael; Rennels, David

    2004-01-01

    A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing

  4. SEU mitigation strategies for SRAM-based FPGA

    NASA Astrophysics Data System (ADS)

    Luo, Pei; Zhang, Jian

    2011-08-01

    The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the

  5. Fast semivariogram computation using FPGA architectures

    NASA Astrophysics Data System (ADS)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  6. Protons Trigger Mitochondrial Flashes.

    PubMed

    Wang, Xianhua; Zhang, Xing; Huang, Zhanglong; Wu, Di; Liu, Beibei; Zhang, Rufeng; Yin, Rongkang; Hou, Tingting; Jian, Chongshu; Xu, Jiejia; Zhao, Yan; Wang, Yanru; Gao, Feng; Cheng, Heping

    2016-07-26

    Emerging evidence indicates that mitochondrial flashes (mitoflashes) are highly conserved elemental mitochondrial signaling events. However, which signal controls their ignition and how they are integrated with other mitochondrial signals and functions remain elusive. In this study, we aimed to further delineate the signal components of the mitoflash and determine the mitoflash trigger mechanism. Using multiple biosensors and chemical probes as well as label-free autofluorescence, we found that the mitoflash reflects chemical and electrical excitation at the single-organelle level, comprising bursting superoxide production, oxidative redox shift, and matrix alkalinization as well as transient membrane depolarization. Both electroneutral H(+)/K(+) or H(+)/Na(+) antiport and matrix proton uncaging elicited immediate and robust mitoflash responses over a broad dynamic range in cardiomyocytes and HeLa cells. However, charge-uncompensated proton transport, which depolarizes mitochondria, caused the opposite effect, and steady matrix acidification mildly inhibited mitoflashes. Based on a numerical simulation, we estimated a mean proton lifetime of 1.42 ns and diffusion distance of 2.06 nm in the matrix. We conclude that nanodomain protons act as a novel, to our knowledge, trigger of mitoflashes in energized mitochondria. This finding suggests that mitoflash genesis is functionally and mechanistically integrated with mitochondrial energy metabolism.

  7. REALIZATION OF A CUSTOM DESIGNED FPGA BASED EMBEDDED CONTROLLER.

    SciTech Connect

    SEVERINO,F.; HARVEY, M.; HAYES, T.; HOFF, L.; ODDO, P.; SMITH, K.S.

    2007-10-15

    As part of the Low Level RF (LLRF) upgrade project at Brookhaven National Laboratory's Collider-Accelerator Department (BNL C-AD), we have recently developed and tested a prototype high performance embedded controller. This controller is a custom designed PMC module employing a Xilinx V4FX60 FPGA with a PowerPC405 embedded processor, and a wide variety of on board peripherals (DDR2 SDRAM, FLASH, Ethernet, PCI, multi-gigabit serial transceivers, etc.). The controller is capable of running either an embedded version of LINUX or VxWorks, the standard operating system for RHIC front end computers (FECs). We have successfully demonstrated functionality of this controller as a standard RHIC FEC and tested all on board peripherals. We now have the ability to develop complex, custom digital controllers within the framework of the standard RHIC control system infrastructure. This paper will describe various aspects of this development effort, including the basic hardware, functional capabilities, the development environment, kernel and system integration, and plans for further development.

  8. SRAM Based Re-programmable FPGA for Space Applications

    NASA Technical Reports Server (NTRS)

    Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

    1999-01-01

    An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

  9. A versatile digital camera trigger for telescopes in the Cherenkov Telescope Array

    NASA Astrophysics Data System (ADS)

    Schwanke, U.; Shayduk, M.; Sulanke, K.-H.; Vorobiov, S.; Wischnewski, R.

    2015-05-01

    This paper describes the concept of an FPGA-based digital camera trigger for imaging atmospheric Cherenkov telescopes, developed for the future Cherenkov Telescope Array (CTA). The proposed camera trigger is designed to select images initiated by the Cherenkov emission of extended air showers from very-high energy (VHE, E > 20 GeV) photons and charged particles while suppressing signatures from background light. The trigger comprises three stages. A first stage employs programmable discriminators to digitize the signals arriving from the camera channels (pixels). At the second stage, a grid of low-cost FPGAs is used to process the digitized signals for camera regions with 37 pixels. At the third stage, trigger conditions found independently in any of the overlapping 37-pixel regions are combined into a global camera trigger by few central FPGAs. Trigger prototype boards based on Xilinx FPGAs have been designed, built and tested and were shown to function properly. Using these components a full camera trigger with a power consumption and price per channel of about 0.5 W and 19 €, respectively, can be built. With the described design the camera trigger algorithm can take advantage of pixel information in both the space and the time domain allowing, for example, the creation of triggers sensitive to the time-gradient of a shower image; the time information could also be exploited to online adjust the time window of the acquisition system for pixel data. Combining the results of the parallel execution of different trigger algorithms (optimized, for example, for the lowest and highest energies, respectively) on each FPGA can result in a better response over all photons energies (as demonstrated by Monte Carlo simulation in this work).

  10. Stego on FPGA: An IWT Approach

    PubMed Central

    Ramalingam, Balakrishnan

    2014-01-01

    A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA). PMID:24723794

  11. Real-time panoramic infrared imaging system based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhang, Hao-Jun; Shen, Yong-Ge

    2010-11-01

    During the past decades, signal processing architecture, which is based on FPGA, conventional DSP processor and host computer, is popular for infrared or other electro-optical systems. With the increasing processing requirement, the former architecture starts to show its limitation in several respects. This paper elaborates a solution based on FPGA for panoramic imaging system as our first step of upgrading the processing module to System-on-Chip (SoC) solution. Firstly, we compare this new architecture with the traditional to show its superiority mainly in the video processing ability, reduction in the development workload and miniaturization of the system architecture. Afterwards, this paper provides in-depth description of this imaging system, including the system architecture and its function, and addresses several related issues followed by the future development. FPGA has developed so rapidly during the past years, not only in silicon device but also in the design flow and tools. In the end, we briefly present our future system development and introduce those new design tools to make up the limitation of the traditional FPGA design methodology. The advanced design flow through Simulink and Xilinx System Generator (Sysgen) has been elaborated, which enables engineers to develop sophisticated DSP algorithms and implement them in FPGA more efficiently. It is believed that this new design approach can shorten system design cycle by allowing rapid prototyping and refining design process.

  12. FPGA design and implementation for EIT data acquisition.

    PubMed

    Yue, Xicai; McLeod, Chris

    2008-10-01

    OXBACT-5 was designed to meet the challenges involved in working in the intensive care hospital environment focussed particularly on thoracic imaging of patients with respiratory distress and chronic heart failure (CHF). The FPGA-based wireless LAN linked multi-channel EIT data acquisition system (DAS) providing 16 programmable excitation current channels and 64 voltage measurement channels is presented. It contains function modules of a PCI bus interface, direct digital synthesizers, dual-port memory blocks, digital demodulation and all the command and control logic in the FPGA. The whole EIT data acquisition system is fully programmable and reconfigurable from the host PC. The excitation frequency, excitation patterns, the measuring sequence and the gain of each measurement channel can be set from the host PC before each measurement. The demodulation is implemented in the FPGA chip to reduce the data rate between the DAS and the host PC. In addition, measurement process management is achieved in this FPGA chip. Complemented by analogue devices such as ADCs, DACs, analogue buffers and analogue multiplexers, the new FPGA-based EIT DAS system is implemented in a very compact way for bedside use in intensive care units of hospitals. It is intended for applications such as continuous respiration monitoring with data collection at 25 frames per second. Image reconstruction times depend on the choice of 2D or 3D imaging algorithms and the available processing power.

  13. Novel cascade FPGA accelerator for support vector machines classification.

    PubMed

    Papadonikolakis, Markos; Bouganis, Christos-Savvas

    2012-07-01

    Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.

  14. A novel pipeline based FPGA implementation of a genetic algorithm

    NASA Astrophysics Data System (ADS)

    Thirer, Nonel

    2014-05-01

    To solve problems when an analytical solution is not available, more and more bio-inspired computation techniques have been applied in the last years. Thus, an efficient algorithm is the Genetic Algorithm (GA), which imitates the biological evolution process, finding the solution by the mechanism of "natural selection", where the strong has higher chances to survive. A genetic algorithm is an iterative procedure which operates on a population of individuals called "chromosomes" or "possible solutions" (usually represented by a binary code). GA performs several processes with the population individuals to produce a new population, like in the biological evolution. To provide a high speed solution, pipelined based FPGA hardware implementations are used, with a nstages pipeline for a n-phases genetic algorithm. The FPGA pipeline implementations are constraints by the different execution time of each stage and by the FPGA chip resources. To minimize these difficulties, we propose a bio-inspired technique to modify the crossover step by using non identical twins. Thus two of the chosen chromosomes (parents) will build up two new chromosomes (children) not only one as in classical GA. We analyze the contribution of this method to reduce the execution time in the asynchronous and synchronous pipelines and also the possibility to a cheaper FPGA implementation, by using smaller populations. The full hardware architecture for a FPGA implementation to our target ALTERA development card is presented and analyzed.

  15. FPGA realization of multi-scroll chaotic oscillators

    NASA Astrophysics Data System (ADS)

    Tlelo-Cuautle, E.; Rangel-Magdaleno, J. J.; Pano-Azucena, A. D.; Obeso-Rodelo, P. J.; Nunez-Perez, J. C.

    2015-10-01

    Chaotic oscillators have been realized using field-programmable gate arrays (FPGAs) showing good results. However, only 2-scrolls have been observed experimentally, and all reported works use commercially-available software tools for FPGA synthesis. In this manner, as a first contribution we show the FPGA realization of two multi-scroll chaotic oscillators that are characterized by their maximum Lyapunov exponent (MLE) for generating from 2- to 6-scrolls. The first multi-scroll chaotic oscillator is based on saturated function series and the second on Chua's circuit. As a second contribution, we show their hardware realization by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). The advantage of realizing those multi-scroll chaotic oscillators is that one can avoid the use of multiplier entities, thus optimizing FPGA resources and increasing the processing speed, as we show by realizing single constant multiplication (SCM) blocks. The experiments are verified by performing co-simulation for an FPGA Spartan 3 of Xilinx. Finally, experimental results are shown for different values of MLE (already optimized) for both multi-scroll chaotic oscillators, and the FPGA used resources are listed for generating 6-scrolls when applying FE and RK.

  16. Performance Evaluation of FPGA-Based Biological Applications

    SciTech Connect

    Storaasli, Olaf O; Yu, Weikuan; Strenski, Dave; Maltby, Jim

    2007-01-01

    On the forefront of recent HPC innovations are Field Programmable Gate Arrays (FPGA), which promise to accelerate calculations by one or more orders of magnitude. The performance of two Cray XD1 systems with Virtex-II Pro 50 and Virtex-4 LX160 FPGAs, were evaluated using a computational biological human genome comparisons program. This paper describes scalable, parallel, FPGA-accelerated results for the FASTA application ssearch34, using the Smith-Waterman algorithm for DNA, RNA and protein sequencing contained in the OpenFPGA benchmark suite. Results indicate typical Cray XD1 FPGA speedups of 50x (Virtex-II Pro 50) and 100x (Virtex-4 LX160) compared to a 2.2 GHz Opteron. Similar speedups are expected for the DRC RPU110-L200 modules (Virtex-4 LX200), which fit in an Opteron socket, and selected by Cray for its XT Supercomputers. The FPGA programming challenges, human genome benchmarking, and data verification of results, are discussed.

  17. Performance and advantages of a soft-core based parallel architecture for energy peak detection in the calorimeter Level 0 trigger for the NA62 experiment at CERN

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Barbanera, M.; Bizzarri, M.; Bonaiuto, V.; Ceccucci, A.; Checcucci, B.; De Simone, N.; Fantechi, R.; Federici, L.; Fucci, A.; Lupi, M.; Paoluzzi, G.; Papi, A.; Piccini, M.; Ryjov, V.; Salamon, A.; Salina, G.; Sargeni, F.; Venditti, S.

    2017-03-01

    The NA62 experiment at CERN SPS has started its data-taking. Its aim is to measure the branching ratio of the ultra-rare decay K+ → π+ν ν̅ . In this context, rejecting the background is a crucial topic. One of the main background to the measurement is represented by the K+ → π+π0 decay. In the 1-8.5 mrad decay region this background is rejected by the calorimetric trigger processor (Cal-L0). In this work we present the performance of a soft-core based parallel architecture built on FPGAs for the energy peak reconstruction as an alternative to an implementation completely founded on VHDL language.

  18. An unusual case of death probably triggered by the association of buprenorphine at therapeutic dose with ethanol and benzodiazepines and with very low norbuprenorphine level.

    PubMed

    Bardy, Guillaume; Cathala, Philippe; Eiden, Céline; Baccino, Eric; Petit, Pierre; Mathieu, Olivier

    2015-01-01

    Buprenorphine is largely prescribed for maintenance treatment in opioid dependence due to its safety profile. Nevertheless, fatalities at therapeutic dose have been described when associated with other central nervous system depressants, such as ethanol or benzodiazepines. Here, we report a case of death due to association of buprenorphine at therapeutic dose with benzodiazepines and ethanol. Although toxicity has been often attributed to its metabolite norbuprenorphine rather than to buprenorphine itself, in our case, norbuprenorphine was not detected in urine and bile and only in traces in blood. Moreover, the presence in blood of free buprenorphine but not of glucuronide metabolites argues for an unusual early death, at the beginning of buprenorphine metabolism. We propose that in the context of prior toxic impregnation, buprenorphine directly (and not via its metabolite norbuprenorphine) acted as a triggering factor by blocking the ventilatory response, rapidly leading to fatal respiratory depression.

  19. The H1 Trigger with Emphasis on Tracking Triggers

    NASA Astrophysics Data System (ADS)

    Riedlberger, J.

    1995-11-01

    Since the commissioning of the electron proton collider HERA in 1992 at DESY the H1 experiment collected data with stable performance. The collision frequency of 10.4 MHz necessitates a pipelined design of the data acquisition and the trigger. A multilevel trigger is used to provide the required selectivity on physics processes and to allow for fast rejection of background events. Subdetector-based, deadtime-free triggers are combined to produce a first level trigger. The dcr φ trigger described herein, extracts its data from the central driftchamber. The drifttime of the signals is measured online and logical functions are applied on the digitized time measurements. To account for different performance parameters of the driftchamber the hardware demands a high flexibility, thus leading to a design with Programmable Gate Arrays (XILINX). Track-finding is achieved by means of ten thousand look-up tables, each with typically 20 inputs. Although the signals for one event will arrive within 1.1 μs, it is possible to determine the timing of the event online within one bunchcrossing (0.096 μs).

  20. FPGA-based compression of streaming x-ray photon correlation spectroscopy data

    SciTech Connect

    Madden, Timothy; Jemian, Peter; Narayanan, Surcsh; Sandy, Alec; Sikorski, Marcin; Sprung, Michael; Weizeorick, John

    2011-08-09

    A data acquisition system to perform real-time background subtraction and lower-level-discrimination-based compression of streaming x-ray photon correlation spectroscopy (XPCS) data from a fast charge-coupled device (CCD) area detector has been built and put into service at the Advanced Photon source (APS) at Argonne National Laboratory. A commercial frame grabber with on-board field-programmable gate array (FPGA) was used in the design, and continuously processes 60 frames per second each consisting of 1,024 x 1,024 pixels with up to 64512 photon hits per frame.

  1. Detection of Crosstalk Faults in Field Programmable Gate Arrays (FPGA)

    NASA Astrophysics Data System (ADS)

    Das, N.; Roy, P.; Rahaman, H.

    2015-09-01

    In this work, a Built-in-Self-Test (BIST) technique has been proposed to detect crosstalk faults in FPGA and run time congestion and to provide the crosstalk aware router for FPGA. The proposed BIST circuits require less overhead as compared to earlier techniques. The proposed detector can detect any logic hazard or delay due to crosstalk. A technique has also been proposed to avoid the crosstalk by routing the path in such a way that no interference occurs between the interconnects. The proposed router has achieved better utilization of routing resource to determine the net as compared to the earlier works. The proposed scheme is simulated in MATLAB and verified using Xilinx ISE tools and Modelsim 6.0. The router is implemented by using class provided by JBits for Xilinx, Vertex-II FPGA. It has been found that the results are quite encouraging.

  2. A low-power wave union TDC implemented in FPGA

    SciTech Connect

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas; /Illinois Math. Sci. Acad.

    2011-10-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  3. A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation

    NASA Astrophysics Data System (ADS)

    Lin, Changxing; Zhang, Jian; Shao, Beibei

    This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2dB.

  4. The LUX experiment - trigger and data acquisition systems

    NASA Astrophysics Data System (ADS)

    Druszkiewicz, Eryk

    2013-04-01

    The Large Underground Xenon (LUX) detector is a two-phase xenon time projection chamber designed to detect interactions of dark matter particles with the xenon nuclei. Signals from the detector PMTs are processed by custom-built analog electronics which provide properly shaped signals for the trigger and data acquisition (DAQ) systems. During calibrations, both systems must be able to handle high rates and have large dynamic ranges; during dark matter searches, maximum sensitivity requires low thresholds. The trigger system uses eight-channel 64-MHz digitizers (DDC-8) connected to a Trigger Builder (TB). The FPGA cores on the digitizers perform real-time pulse identification (discriminating between S1 and S2-like signals) and event localization. The TB uses hit patterns, hit maps, and maximum response detection to make trigger decisions, which are reached within few microseconds after the occurrence of an event of interest. The DAQ system is comprised of commercial digitizers with customized firmware. Its real-time baseline suppression allows for a maximum event acquisition rate in excess of 1.5 kHz, which results in virtually no deadtime. The performance of the trigger and DAQ systems during the commissioning runs of LUX will be discussed.

  5. Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

    NASA Astrophysics Data System (ADS)

    Liu, Yangfan; Liu, Peng; Jiang, Yingtao; Yang, Mei; Wu, Kejun; Wang, Weidong; Yao, Qingdong

    2010-10-01

    In this article, we present a highly scalable, flexible hardware-based network-on-chip (NoC) emulation framework, through which NoCs built upon various types of network topologies, routing algorithms, switching protocols and flow control schemes can be explored, compared, and validated with injected or self-generated traffic from both real-life and synthetic applications. This high degree of scalability and flexibility is achieved due to the field programmable gate array (FPGA) design choices made at both functional and physical levels. At the functional level, a NoC system to be emulated can be partitioned into two parts: (i) the processing cores and (ii) the network. Each part is mapped onto a different FPGA so that when there is any change to be made to any one of these parts, only the corresponding FPGA needs to be reconfigured and the rest of the FPGAs will be left untouched. At the physical level, two levels of interconnects are adopted to mimic NoC on-chip communications: high bandwidth and low latency parallel on-board wires, and high-speed serial multigigabit transceivers available in FPGAs. The latter is particularly important as it helps the proposed NoC emulation platform scale well with the size increase of the NoCs.

  6. Design of the Trigger Interface and Distribution Board for CEBAF 12 GeV Upgrade

    SciTech Connect

    Gu, Jianhui; Dong, Hai; Cuevas, R; Gyurjyan, Vardan; Heyes, William; Jastrzembski, Edward; Kaneta, Scott; Nganga, Nicholas; Moffit, Bryan; Raydo, Benjamin; Timmer, Carl; Wilson, Jeffrey

    2012-10-01

    The design of the Trigger Interface and Distribution (TID) board for the 12 GeV Upgrade at the Continuous Electron Beam Accelerator Facility (CEBAF) at TJNAL is described. The TID board distributes a low jitter system clock, synchronized trigger, and synchronized multi-purpose SYNC signal. The TID also initiates data acquisition for the crate. With the TID boards, a multi-crate system can be setup for experiment test and commissioning. The TID board can be selectively populated as a Trigger Interface (TI) board, or a Trigger Distribution (TD) board for the 12 GeV upgrade experiments. When the TID is populated as a TI, it can be located in the VXS crate and distribute the CLOCK/TRIGGER/SYNC through the VXS P0 connector; it can also be located in the standard VME64 crate, and distribute the CLOCK/TRIGGER/SYNC through the VME P2 connector or front panel. It initiates the data acquisition for the front crate where the TI is positioned in. When the TID is populated as a TD, it fans out the CLOCK/TRIGGER/SYNC from trigger supervisor to the front end crates through optical fibres. The TD monitors the trigger processing on the TIs, and gives feedback to the TS for trigger flow control. Field Programmable Gate Arrays (FPGA) is utilised on TID board to provide programmability. The TID boards were intensively tested on the bench, and various setups.

  7. Methods for automatic trigger threshold adjustment

    DOEpatents

    Welch, Benjamin J; Partridge, Michael E

    2014-03-18

    Methods are presented for adjusting trigger threshold values to compensate for drift in the quiescent level of a signal monitored for initiating a data recording event, thereby avoiding false triggering conditions. Initial threshold values are periodically adjusted by re-measuring the quiescent signal level, and adjusting the threshold values by an offset computation based upon the measured quiescent signal level drift. Re-computation of the trigger threshold values can be implemented on time based or counter based criteria. Additionally, a qualification width counter can be utilized to implement a requirement that a trigger threshold criterion be met a given number of times prior to initiating a data recording event, further reducing the possibility of a false triggering situation.

  8. The LHCb trigger and its upgrade

    NASA Astrophysics Data System (ADS)

    Dziurda, A.

    2016-07-01

    The current LHCb trigger system consists of a hardware level, which reduces the LHC inelastic collision rate of 30 MHz, at which the entire detector is read out. In a second level, implemented in a farm of 20 k parallel-processing CPUs, the event rate is reduced to about 5 kHz. We review the performance of the LHCb trigger system during Run I of the LHC. Special attention is given to the use of multivariate analyses in the High Level Trigger. The major bottleneck for hadronic decays is the hardware trigger. LHCb plans a major upgrade of the detector and DAQ system in the LHC shutdown of 2018, enabling a purely software based trigger to process the full 30 MHz of inelastic collisions delivered by the LHC. We demonstrate that the planned architecture will be able to meet this challenge.

  9. Establishment of trigger levels to steer the follow-up of radiation effects in patients undergoing fluoroscopically-guided interventional procedures in Belgium.

    PubMed

    Struelens, L; Bacher, K; Bosmans, H; Bleeser, F; Hoornaert, M T; Malchair, F; Balter, S

    2014-12-01

    The accumulated dose to the skin of the patient during fluoroscopically-guided procedures can exceed the thresholds for tissue reactions. In practice, interventionalists have no direct information about the local procedure-related skin doses in their patient, causing suboptimal or delayed treatment. In current study, the accumulated Kerma-Area-Product (KAP) values were registered, as well as the reference air kerma (Ka,r) values, if available, for almost 200 cases undergoing seven different procedures. A sheet filled with 50 thermoluminescent dosemeters was wrapped around each patient to measure the peak skin dose. In a significant part of the Transjugular Intrahepatic Portosystemic Shunt (TIPSS) procedures, chemo-embolizations of the liver and cerebral embolizations, the threshold values for deterministic skin damage (2 Gy) were attained. Trigger values in terms of KAP, corresponding to a peak skin dose of 2 Gy, were determined. In general, our results comply reasonably well with the values proposed in the NCRP 168 report, with a KAP value of 425 Gy cm² and a Ka,r value of 3 Gy, corresponding to a peak skin dose of 3 Gy. Only for the TIPSS procedure a considerably lower value of 2 Gy was obtained at the published Ka,r and for the RF ablations we obtained a considerably lower value of 250 Gy cm² in terms of KAP.

  10. Radiation Tolerant, FPGA-Based SmallSat Computer System

    NASA Technical Reports Server (NTRS)

    LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

    2015-01-01

    The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

  11. Exploration of a Research Roadmap for Application Development and Execution on Field-Programmable Gate Array (FPGA)-Based Systems

    DTIC Science & Technology

    2008-10-01

    instrumentation of FPGA bitstreams to provide automated debugging capabilities. [ Camera -05] demonstrates debug capabilities by inserting specialized logic ...for run-time support are lagging, especially for verification, analysis, debugging, and optimization at the systemlevel [ Camera -05, Tong-07]. Run...evolution of design tools over the same period. FPGAs in their primordial state were mainly used for glue logic on circuit boards with RTL-level

  12. Proposal of ROS-compliant FPGA component for low-power robotic systems

    NASA Astrophysics Data System (ADS)

    Li, Rong; Quan, Lei; Cai, YouLin

    2015-12-01

    In recent years, robots are required to be autonomous and their robotic software are sophisticated. Robots have a problem of insufficient performance, since it cannot equip with a high-performance microprocessor due to battery-power operation. On the other hand, FPGA devices can accelerate specific functions in a robot system without increasing power consumption by implementing customized circuits. But it is difficult to introduce FPGA devices into a robot due to large development cost of an FPGA circuit compared to software. Therefore, in this study, we propose an FPGA component technology for an easy integration of an FPGA into robots, which is compliant with ROS (Robot Operating System). As a case study, we designed ROS-compliant FPGA component of image labeling using Xilinx Zynq platform. The developed ROS-component FPGA component performs 1.7 times faster compared to the ordinary ROS software component.

  13. Different Levels of T-Cell Receptor Triggering Induce Distinct Functions in Hepatitis B and Hepatitis C Virus-Specific Human CD4+ T-Cell Clones

    PubMed Central

    Diepolder, Helmut M.; Gruener, Norbert H.; Gerlach, J. Tilman; Jung, Maria-Christina; Wierenga, Eddy A.; Pape, Gerd R.

    2001-01-01

    CD4+ T cells play a major role in the host defense against viruses and intracellular microbes. During the natural course of such an infection, specific CD4+ T cells are exposed to a wide range of antigen concentrations depending on the body compartment and the stage of disease. While epitope variants trigger only subsets of T-cell effector functions, the response of virus-specific CD4+ T cells to various concentrations of the wild-type antigen has not been systematically studied. We stimulated hepatitis B virus core- and hepatitis C virus NS3-specific CD4+ T-cell clones which had been isolated from patients with acute hepatitis during viral clearance with a wide range of specific antigen concentrations and determined the phenotypic changes and the induction of T-cell effector functions in relation to T-cell receptor internalization. A low antigen concentration induced the expression of T-cell activation markers and adhesion molecules in CD4+ T-cell clones in the absence of cytokine secretion and proliferation. The expression of CD25, HLA-DR, CD69, and intercellular cell adhesion molecule 1 increased as soon as T-cell receptor internalization became detectable. A 30- to 100-fold-higher antigen concentration, corresponding to the internalization of 20 to 30% of T-cell receptor molecules, however, was required for the induction of proliferation as well as for gamma interferon and interleukin-4 secretion. These data indicate that virus-specific CD4+ T cells can respond to specific antigen in a graded manner depending on the antigen concentration, which may have implications for a coordinate regulation of specific CD4+ T-cell responses. PMID:11483723

  14. Lessons from (triggered) tremor

    USGS Publications Warehouse

    Gomberg, Joan

    2010-01-01

    I test a “clock-advance” model that implies triggered tremor is ambient tremor that occurs at a sped-up rate as a result of loading from passing seismic waves. This proposed model predicts that triggering probability is proportional to the product of the ambient tremor rate and a function describing the efficacy of the triggering wave to initiate a tremor event. Using data mostly from Cascadia, I have compared qualitatively a suite of teleseismic waves that did and did not trigger tremor with ambient tremor rates. Many of the observations are consistent with the model if the efficacy of the triggering wave depends on wave amplitude. One triggered tremor observation clearly violates the clock-advance model. The model prediction that larger triggering waves result in larger triggered tremor signals also appears inconsistent with the measurements. I conclude that the tremor source process is a more complex system than that described by the clock-advance model predictions tested. Results of this and previous studies also demonstrate that (1) conditions suitable for tremor generation exist in many tectonic environments, but, within each, only occur at particular spots whose locations change with time; (2) any fluid flow must be restricted to less than a meter; (3) the degree to which delayed failure and secondary triggering occurs is likely insignificant; and 4) both shear and dilatational deformations may trigger tremor. Triggered and ambient tremor rates correlate more strongly with stress than stressing rate, suggesting tremor sources result from time-dependent weakening processes rather than simple Coulomb failure.

  15. FPGA wavelet processor design using language for instruction-set architectures (LISA)

    NASA Astrophysics Data System (ADS)

    Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

    2007-04-01

    The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

  16. FPGA-based multi-channel fluorescence lifetime analysis of Fourier multiplexed frequency-sweeping lifetime imaging

    PubMed Central

    Zhao, Ming; Li, Yu; Peng, Leilei

    2014-01-01

    We report a fast non-iterative lifetime data analysis method for the Fourier multiplexed frequency-sweeping confocal FLIM (Fm-FLIM) system [ Opt. Express22, 10221 ( 2014)24921725]. The new method, named R-method, allows fast multi-channel lifetime image analysis in the system’s FPGA data processing board. Experimental tests proved that the performance of the R-method is equivalent to that of single-exponential iterative fitting, and its sensitivity is well suited for time-lapse FLIM-FRET imaging of live cells, for example cyclic adenosine monophosphate (cAMP) level imaging with GFP-Epac-mCherry sensors. With the R-method and its FPGA implementation, multi-channel lifetime images can now be generated in real time on the multi-channel frequency-sweeping FLIM system, and live readout of FRET sensors can be performed during time-lapse imaging. PMID:25321778

  17. FPGA-based multi-channel fluorescence lifetime analysis of Fourier multiplexed frequency-sweeping lifetime imaging.

    PubMed

    Zhao, Ming; Li, Yu; Peng, Leilei

    2014-09-22

    We report a fast non-iterative lifetime data analysis method for the Fourier multiplexed frequency-sweeping confocal FLIM (Fm-FLIM) system [Opt. Express 22, 10221 (2014)]. The new method, named R-method, allows fast multi-channel lifetime image analysis in the system's FPGA data processing board. Experimental tests proved that the performance of the R-method is equivalent to that of single-exponential iterative fitting, and its sensitivity is well suited for time-lapse FLIM-FRET imaging of live cells, for example cyclic adenosine monophosphate (cAMP) level imaging with GFP-Epac-mCherry sensors. With the R-method and its FPGA implementation, multi-channel lifetime images can now be generated in real time on the multi-channel frequency-sweeping FLIM system, and live readout of FRET sensors can be performed during time-lapse imaging.

  18. Causality and headache triggers

    PubMed Central

    Turner, Dana P.; Smitherman, Todd A.; Martin, Vincent T.; Penzien, Donald B.; Houle, Timothy T.

    2013-01-01

    Objective The objective of this study was to explore the conditions necessary to assign causal status to headache triggers. Background The term “headache trigger” is commonly used to label any stimulus that is assumed to cause headaches. However, the assumptions required for determining if a given stimulus in fact has a causal-type relationship in eliciting headaches have not been explicated. Methods A synthesis and application of Rubin’s Causal Model is applied to the context of headache causes. From this application the conditions necessary to infer that one event (trigger) causes another (headache) are outlined using basic assumptions and examples from relevant literature. Results Although many conditions must be satisfied for a causal attribution, three basic assumptions are identified for determining causality in headache triggers: 1) constancy of the sufferer; 2) constancy of the trigger effect; and 3) constancy of the trigger presentation. A valid evaluation of a potential trigger’s effect can only be undertaken once these three basic assumptions are satisfied during formal or informal studies of headache triggers. Conclusions Evaluating these assumptions is extremely difficult or infeasible in clinical practice, and satisfying them during natural experimentation is unlikely. Researchers, practitioners, and headache sufferers are encouraged to avoid natural experimentation to determine the causal effects of headache triggers. Instead, formal experimental designs or retrospective diary studies using advanced statistical modeling techniques provide the best approaches to satisfy the required assumptions and inform causal statements about headache triggers. PMID:23534872

  19. AMY trigger system

    SciTech Connect

    Sakai, Yoshihide

    1989-04-01

    A trigger system of the AMY detector at TRISTAN e{sup +}e{sup -} collider is described briefly. The system uses simple track segment and shower cluster counting scheme to classify events to be triggered. It has been operating successfully since 1987.

  20. FPGA based fast synchronous serial multi-wire links synchronization

    NASA Astrophysics Data System (ADS)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  1. Pipelined CPU Design with FPGA in Teaching Computer Architecture

    ERIC Educational Resources Information Center

    Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

    2012-01-01

    This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

  2. Single Event Effects in FPGA Devices 2015-2016

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  3. Single Event Effects in FPGA Devices 2015-2016

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  4. Single Event Effects in FPGA Devices 2014-2015

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2015-01-01

    This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  5. Photoelectric radar servo control system based on ARM+FPGA

    NASA Astrophysics Data System (ADS)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  6. Design of a system based on DSP and FPGA for video recording and replaying

    NASA Astrophysics Data System (ADS)

    Kang, Yan; Wang, Heng

    2013-08-01

    This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA

  7. The D0 run II trigger system

    SciTech Connect

    Schwienhorst, Reinhard; /Michigan State U.

    2004-11-01

    The D0 detector at the Fermilab Tevatron was upgraded for Run II. This upgrade included improvements to the trigger system in order to be able to handle the increased Tevatron luminosity and higher bunch crossing rates compared to Run I. The D0 Run II trigger is a highly exible system to select events to be written to tape from an initial interaction rate of about 2.5 MHz. This is done in a three-tier pipelined, buffered system. The first tier (level 1) processes fast detector pick-off signals in a hardware/firmware based system to reduce the event rate to about 1. 5kHz. The second tier (level 2) uses information from level 1 and forms simple Physics objects to reduce the rate to about 850 Hz. The third tier (level 3) uses full detector readout and event reconstruction on a filter farm to reduce the rate to 20-30 Hz. The D0 trigger menu contains a wide variety of triggers. While the emphasis is on triggering on generic lepton and jet final states, there are also trigger terms for specific final state signatures. In this document we describe the D0 trigger system as it was implemented and is currently operating in Run II.

  8. LHCb Topological Trigger Reoptimization

    NASA Astrophysics Data System (ADS)

    Likhomanenko, Tatiana; Ilten, Philip; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-12-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so- called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all ’interesting” decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. Methods studied include cascading, ensembling and blending techniques. Furthermore, novel boosting techniques have been implemented that will help reduce systematic uncertainties in Run 2 measurements. We demonstrate that the reoptimized topological trigger is expected to significantly improve on the Run 1 performance for a wide range of b-hadron decays.

  9. An enhanced multiwavelength ultraviolet biological trigger lidar

    NASA Astrophysics Data System (ADS)

    Achey, Alexander; Bufton, Jack; Dawson, Jeffrey; Huang, Wen; Lee, Sangmin; Mehta, Nikhil; Prasad, Coorg R.

    2004-12-01

    A compact Ultraviolet Biological Trigger Lidar (UBTL) instrument for detection and discrimination of bio-warfare-agent (BWA) simulant aerosol clouds was developed by us [Prasad, et al, 2004] using a 5mW, 375nm semiconductor UV optical source (SUVOS) laser diode. It underwent successful field tests at Dugway Proving Ground and demonstrated measurement ranges of over 300m for elastic scattering and >100m for fluorescence. The UBTL was modified during mid-2004 to enhance its detection and discrimination performance with increased range of operation and sensitivity. The major optical modifications were: 1. increase in telescope collection aperture to 200 mm diameter: 2. addition of 266nm and 977nm laser transmitters: 3. addition of three detection channels for 266nm and 977nm elastic backscatter and fluorescence centered at 330nm. Also the commercial electronics of the original UBTL were replaced with a multi-channel field programmable gate array (FPGA) chip for laser diode modulation and data acquisition that allowed simultaneous and continuous operation of the UBTL sensor on all of its transmitter and receiver wavelengths. A notebook computer was added for data display and storage. Field tests were performed during July 2004 at the Edgewood Chemical and Biological Center in Maryland to establish the enhanced performance of UBTL subsystems. Results of these tests are presented and discussed.

  10. Software for implementing trigger algorithms on the upgraded CMS Global Trigger System

    NASA Astrophysics Data System (ADS)

    Matsushita, Takashi; Arnold, Bernhard

    2015-12-01

    The Global Trigger is the final step of the CMS Level-1 Trigger and implements a trigger menu, a set of selection requirements applied to the final list of trigger objects. The conditions for trigger object selection, with possible topological requirements on multiobject triggers, are combined by simple combinatorial logic to form the algorithms. The LHC has resumed its operation in 2015, the collision-energy will be increased to 13 TeV with the luminosity expected to go up to 2x1034 cm-2s-1. The CMS Level-1 trigger system will be upgraded to improve its performance for selecting interesting physics events and to operate within the predefined data-acquisition rate in the challenging environment expected at LHC Run 2. The Global Trigger will be re-implemented on modern FPGAs on an Advanced Mezzanine Card in MicroTCA crate. The upgraded system will benefit from the ability to process complex algorithms with DSP slices and increased processing resources with optical links running at 10 Gbit/s, enabling more algorithms at a time than previously possible and allowing CMS to be more flexible in how it handles the trigger bandwidth. In order to handle the increased complexity of the trigger menu implemented on the upgraded Global Trigger, a set of new software has been developed. The software allows a physicist to define a menu with analysis-like triggers using intuitive user interface. The menu is then realised on FPGAs with further software processing, instantiating predefined firmware blocks. The design and implementation of the software for preparing a menu for the upgraded CMS Global Trigger system are presented.

  11. FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

    NASA Astrophysics Data System (ADS)

    Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

    2016-05-01

    This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

  12. Goldfish exposure to cobalt enhances hemoglobin level and triggers tissue-specific elevation of antioxidant defenses in gills, heart and spleen.

    PubMed

    Kubrak, Olga I; Rovenko, Bohdana M; Husak, Viktor V; Vasylkiv, Olena Yu; Storey, Kenneth B; Storey, Janet M; Lushchak, Volodymyr I

    2012-03-01

    Cobalt ions can enhance the generation of reactive oxygen species (ROS), which may be the reason for cobalt toxicity. This study aimed to determine whether Co(2+) toxicity in goldfish is related to induced oxidative stress in gills, heart and spleen, and to assess responses of antioxidant systems. Exposure of goldfish to 50, 100 and 150 mg L(-1) of Co(2+) for 96 h elevated total hemoglobin in blood by 23, 44 and 78%, respectively. In gills, cobalt exposure enhanced lipid peroxide levels and activities of primary antioxidant enzymes; superoxide dismutase (SOD) rose by 125% and glutathione peroxidase (GPx) increased by 53-296%. Glutathione-S-transferase (GST) activity also increased by 117-157% and glucose-6-phosphate dehydrogenase (G6PDH) enhanced by 46-96%. Heart showed limited effects of fish exposure to 50 or 100 mg L(-1) of Co(2+), but the exposure to 150 mg L(-1) of Co(2+) elevated concentrations of lipid peroxides by 123% and activities of GPx by 98% and SOD by 208%. The most substantial effects of goldfish exposure to Co(2+) were observed in spleen: a decrease in total protein concentration by 44-60% and high molecular mass thiols by 59-82%, reduced activities of catalase by 24-58% and GR by 25-68%, whereas the level of low molecular mass thiols increased by 153-279% and activities of GPx, GST, G6PDH were enhanced by 114-120%, 192-769%, and 256-581%, respectively. The data show that fish exposure to 50-150 mg L(-1) of Co(2+) elevates blood hemoglobin level, mimicking effects of hypoxia, and causes the activation of defense systems against ROS.

  13. Dealing with Asthma Triggers

    MedlinePlus

    ... smell given off by paint or gas, and air pollution. If you notice that an irritant triggers your ... or other tobacco products around you. If outdoor air pollution is a problem, running the air conditioner or ...

  14. Dealing with Asthma Triggers

    MedlinePlus

    ... reactions stuff in the air, like smoke and pollution colds or the flu weather conditions exercise continue ... given off by paint or gas, and air pollution. If you notice that an irritant triggers your ...

  15. ELECTRONIC TRIGGER CIRCUIT

    DOEpatents

    Russell, J.A.G.

    1958-01-01

    An electronic trigger circuit is described of the type where an output pulse is obtained only after an input voltage has cqualed or exceeded a selected reference voltage. In general, the invention comprises a source of direct current reference voltage in series with an impedance and a diode rectifying element. An input pulse of preselected amplitude causes the diode to conduct and develop a signal across the impedance. The signal is delivered to an amplifier where an output pulse is produced and part of the output is fed back in a positive manner to the diode so that the amplifier produces a steep wave front trigger pulsc at the output. The trigger point of the described circuit is not subject to variation due to the aging, etc., of multi-electrode tabes, since the diode circuit essentially determines the trigger point.

  16. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators

    PubMed Central

    2016-01-01

    Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors. PMID:27997930

  17. Performance Evaluation and Implementation of FPGA Based SGSF in Smart Diagnostic Applications.

    PubMed

    Agarwal, Shivangi; Rani, Asha; Singh, Vijander; Mittal, A P

    2016-03-01

    The main objective of the paper is to implement Savitzky Golay Smoothing Filter (SGSF) so as to apply in pre-processing of real time smart medical diagnostic systems. As very important information of EEG and ECG waveforms lies in the peak of the signal, hence it becomes absolutely necessary to filter noise and artifacts from the signal. The implemented filter should be able to reject the noise efficiently along with the least distortion from the original signal. The shape preserving characteristics of the filter are determined by introducing different noise levels in the signal. The designed filter is tested on synthetic signals of EEG and ECG by adding different types of noise and the performance is analysed on various parameters, i.e., SNR, SSNR, SNRI, MSE, COR and signal distortion of the final output. The smoothing performance comparison of SGSF with the most commonly used Moving Average Filter (MAF) proves that SGSF is more efficient. Hence it is suggested that MAF can be replaced by SGSF. For real time issues, it is further implemented on reconfigurable architectures so as to achieve high speed, low cost, low power consumption and less area. Therefore SGSF is realized on FPGA platform to combine the advantages of both. Real time EEG and ECG signals are also considered for experimentation. The experimental results show that the proposed methodology (FPGA-SGSF) significantly reduces the processing time and preserves the actual features of the signal.

  18. VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.

    PubMed

    Tlelo-Cuautle, Esteban; Quintas-Valles, Antonio de Jesus; de la Fraga, Luis Gerardo; Rangel-Magdaleno, Jose de Jesus

    2016-01-01

    Nowadays, chaos generators are an attractive field for research and the challenge is their realization for the development of engineering applications. From more than three decades ago, chaotic oscillators have been designed using discrete electronic devices, very few with integrated circuit technology, and in this work we propose the use of field-programmable gate arrays (FPGAs) for fast prototyping. FPGA-based applications require that one be expert on programming with very-high-speed integrated circuits hardware description language (VHDL). In this manner, we detail the VHDL descriptions of chaos generators for fast prototyping from high-level programming using Python. The cases of study are three kinds of chaos generators based on piecewise-linear (PWL) functions that can be systematically augmented to generate even and odd number of scrolls. We introduce new algorithms for the VHDL description of PWL functions like saturated functions series, negative slopes and sawtooth. The generated VHDL-code is portable, reusable and open source to be synthesized in an FPGA. Finally, we show experimental results for observing 2, 10 and 30-scroll attractors.

  19. Reduction in ATP levels triggers immunoproteasome activation by the 11S (PA28) regulator during early antiviral response mediated by IFNβ in mouse pancreatic β-cells.

    PubMed

    Freudenburg, Wieke; Gautam, Madhav; Chakraborty, Pradipta; James, Jared; Richards, Jennifer; Salvatori, Alison S; Baldwin, Aaron; Schriewer, Jill; Buller, R Mark L; Corbett, John A; Skowyra, Dorota

    2013-01-01

    Autoimmune destruction of insulin producing pancreatic β-cells is the hallmark of type I diabetes. One of the key molecules implicated in the disease onset is the immunoproteasome, a protease with multiple proteolytic sites that collaborates with the constitutive 19S and the inducible 11S (PA28) activators to produce immunogenic peptides for presentation by MHC class I molecules. Despite its importance, little is known about the function and regulation of the immunoproteasome in pancreatic β-cells. Of special interest to immunoproteasome activation in β-cells are the effects of IFNβ, a type I IFN secreted by virus-infected cells and implicated in type I diabetes onset, compared to IFNγ, the classic immunoproteasome inducer secreted by cells of the immune system. By qPCR analysis, we show that mouse insulinoma MIN6 cells and mouse islets accumulate the immune proteolytic β1(i), β2(i) and β5(i), and 11S mRNAs upon exposure to IFNβ or IFNγ. Higher concentrations of IFNβ than IFNγ are needed for similar expression, but in each case the expression is transient, with maximal mRNA accumulation in 12 hours, and depends primarily on Interferon Regulatory Factor 1. IFNs do not alter expression of regular proteasome genes, and in the time frame of IFNβ-mediated response, the immune and regular proteolytic subunits co-exist in the 20S particles. In cell extracts with ATP, these particles have normal peptidase activities and degrade polyubiquitinated proteins with rates typical of the regular proteasome, implicating normal regulation by the 19S activator. However, ATP depletion rapidly stimulates the catalytic rates in a manner consistent with levels of the 11S activator. These findings suggest that stochastic combination of regular and immune proteolytic subunits may increase the probability with which unique immunogenic peptides are produced in pancreatic β-cells exposed to IFNβ, but primarily in cells with reduced ATP levels that stimulate the 11S

  20. The CDF silicon vertex trigger

    SciTech Connect

    B. Ashmanskas; A. Barchiesi; A. Bardi

    2003-06-23

    The CDF experiment's Silicon Vertex Trigger is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 {mu}sec pipeline. SVT's 35 {mu}m impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common inter-board data link, and a universal ''Merger'' board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.

  1. Low-level predation by lytic phage phiIPLA-RODI promotes biofilm formation and triggers the stringent response in Staphylococcus aureus.

    PubMed

    Fernández, Lucía; González, Silvia; Campelo, Ana Belén; Martínez, Beatriz; Rodríguez, Ana; García, Pilar

    2017-01-19

    An important lesson from the war on pathogenic bacteria has been the need to understand the physiological responses and evolution of natural microbial communities. Bacterial populations in the environment are generally forming biofilms subject to some level of phage predation. These multicellular communities are notoriously resistant to antimicrobials and, consequently, very difficult to eradicate. This has sparked the search for new therapeutic alternatives, including phage therapy. This study demonstrates that S. aureus biofilms formed in the presence of a non-lethal dose of phage phiIPLA-RODI exhibit a unique physiological state that could potentially benefit both the host and the predator. Thus, biofilms formed under phage pressure are thicker and have a greater DNA content. Also, the virus-infected biofilm displayed major transcriptional differences compared to an untreated control. Significantly, RNA-seq data revealed activation of the stringent response, which could slow down the advance of the bacteriophage within the biofilm. The end result would be an equilibrium that would help bacterial cells to withstand environmental challenges, while maintaining a reservoir of sensitive bacterial cells available to the phage upon reactivation of the dormant carrier population.

  2. Phytophthora infestans-triggered response of growth- and defense-related genes in potato cultivars with different levels of resistance under the influence of nitrogen availability.

    PubMed

    Ros, Barbara; Mohler, Volker; Wenzel, Gerhard; Thümmler, Fritz

    2008-06-01

    The effects of high and low N concentrations on the Solanum tuberosum-Phytophthora infestans interaction were studied in the potato cultivars Bettina, New York 121, Indira and Arkula, which exhibited different levels of resistance. Aboveground biomass and Chl and N content were significantly higher in all cultivars grown in higher N environments, while C:N ratios were lower, confirming successful application of N. High availability of N significantly increased susceptibility of three of the four potato cultivars, and amounts of pathogen within the infected leaflets determined in a quantitative real-time reverse transcriptase-polymerase chain reaction reflected this. Differential gene expression of P. infestans-induced and -repressed genes derived from three subtracted cDNA libraries at 0, 24, 48 and 72 h post-inoculation was studied in parallel. P. infestans attack led to an induction of defense-related and at the same time repression of growth-related potato genes mainly encoding photosynthetic genes. High N supply led to higher transcript abundance of photosynthetic genes such as Chl a/b-binding protein and ribulose bisphosphate carboxylase. N-dependent suppression of defense-related compounds in absence of the pathogen was not observed. Better N nutrition appeared to allow the plants to invest more resources in defense reactions.

  3. Low-level predation by lytic phage phiIPLA-RODI promotes biofilm formation and triggers the stringent response in Staphylococcus aureus

    PubMed Central

    Fernández, Lucía; González, Silvia; Campelo, Ana Belén; Martínez, Beatriz; Rodríguez, Ana; García, Pilar

    2017-01-01

    An important lesson from the war on pathogenic bacteria has been the need to understand the physiological responses and evolution of natural microbial communities. Bacterial populations in the environment are generally forming biofilms subject to some level of phage predation. These multicellular communities are notoriously resistant to antimicrobials and, consequently, very difficult to eradicate. This has sparked the search for new therapeutic alternatives, including phage therapy. This study demonstrates that S. aureus biofilms formed in the presence of a non-lethal dose of phage phiIPLA-RODI exhibit a unique physiological state that could potentially benefit both the host and the predator. Thus, biofilms formed under phage pressure are thicker and have a greater DNA content. Also, the virus-infected biofilm displayed major transcriptional differences compared to an untreated control. Significantly, RNA-seq data revealed activation of the stringent response, which could slow down the advance of the bacteriophage within the biofilm. The end result would be an equilibrium that would help bacterial cells to withstand environmental challenges, while maintaining a reservoir of sensitive bacterial cells available to the phage upon reactivation of the dormant carrier population. PMID:28102347

  4. Triggered Earthquakes Following Parkfield?

    NASA Astrophysics Data System (ADS)

    Hough, S. E.

    2004-12-01

    When the M5.0 Arvin earthquake struck approximately 30 hours after the 28 September 2004 M6.0 Parkfield earthquake, it seemed likely if not obvious that the latter had triggered the former. The odds of a M5.0 or greater event occurring by random chance in a given 2-day window is low, on the order of 2%. However, previously published results suggest that remotely triggered earthquakes are observed only following much larger mainshocks, typically M7 or above. Moreover, using a standard beta-statistic approach, one finds no pervasive regional increase of seismicity in the weeks following the Parkfield mainshock. (Neither were any moderate events observed at regional distances following the 1934 and 1966 Parkfield earthquakes.) Was Arvin a remotely triggered earthquake? To address this issue further I compare the seismicity rate changes following the Parkfield mainshock with those following 14 previous M5.3-7.1 earthquakes in central and southern California. I show that, on average, seismicity increased to a distance of at least 120 km following these events. For all but the M7.1 Hector Mine mainshock, this is well beyond the radius of what would be considered a traditional aftershock zone. Average seismicity rates also increase, albeit more weakly, to a distance of about 220 km. These results suggest that even moderate mainshocks in central and southern California do trigger seismicity at distances up to 220 km, supporting the inference that Arvin was indeed a remotely triggered earthquake. In general, only weak triggering is expected following moderate (M5.5-6.5) mainshocks. However, as illustrated by Arvin and, in retrospect, the 1986 M5.5 Oceanside earthquake, which struck just 5 days after the M5.9 North Palm Springs earthquake, triggered events can sometimes be large enough to generate public interest, and anxiety.

  5. High Levels of EBV-Encoded RNA 1 (EBER1) Trigger Interferon and Inflammation-Related Genes in Keratinocytes Expressing HPV16 E6/E7

    PubMed Central

    Aromseree, Sirinart; Middeldorp, Jaap M.; Pientong, Chamsai; van Eijndhoven, Monique; Ramayanti, Octavia; Lougheed, Sinéad M.; Pegtel, D. Michiel; Steenbergen, Renske D. M.; Ekalaksananan, Tipaya

    2017-01-01

    Different types of cells infected with Epstein-Barr virus (EBV) can release exosomes containing viral components that functionally affect neighboring cells. Previously, we found that EBV was localized mostly in infiltrating lymphocytes within the stromal layer of cervical lesions. In this study, we aimed to determine effects of exosome-transferred EBV-encoded RNAs (EBERs) on keratinocytes expressing human papillomavirus (HPV) 16 E6/E7 (DonorI-HPV16 HFKs). Lipid transfection of in vitro-transcribed EBER1 molecules (ivt EBER1) into DonorI-HPV16 HFKs caused strong induction of interferon (IFN)-related genes and interleukin 6 (IL-6). To gain insights into the physiological situation, monocyte-derived dendritic cells (moDCs), low passage DonorI-HPV16 HFKs and primary keratinocytes were used as recipient cells for internalization of exosomes from wild-type EBV (wt EBV) or B95-8 EBV-infected lymphoblastoid cell lines (LCLs). qRT-PCR was used to determine the expression of EBER1, HPV16 E6/E7, IFN-related genes and IL-6 in recipient cells. The secretion of inflammatory cytokines was investigated using cytometric bead array. Wt EBV-modified exosomes induced both IFN-related genes and IL-6 upon uptake into moDCs, while exosomes from B95-8 EBV LCLs induced only IL-6 in moDCs. Internalization of EBV–modified exosomes was demonstrated in DonorI-HPV16 HFKs, yielding only EBER1 but not EBER2. However, EBER1 transferred by exosomes did not induce IFN-related genes or IL-6 expression and inflammatory cytokine secretion in DonorI-HPV16 HFKs and primary keratinocytes. EBER1 copy numbers in exosomes from wt EBV-infected LCLs were 10-fold higher than in exosomes from B95-8 LCLs (equal cell equivalent), whereas ivt EBER1 was used at approximately 100-fold higher concentration than in exosomes. These results demonstrated that the induction of IFN-related genes and IL-6 by EBER1 depends on quantity of EBER1 and type of recipient cells. High levels of EBER1 in cervical cells or

  6. Pulse-coupled neural network implementation in FPGA

    NASA Astrophysics Data System (ADS)

    Waldemark, Joakim T. A.; Lindblad, Thomas; Lindsey, Clark S.; Waldemark, Karina E.; Oberg, Johnny; Millberg, Mikael

    1998-03-01

    Pulse Coupled Neural Networks (PCNN) are biologically inspired neural networks, mainly based on studies of the visual cortex of small mammals. The PCNN is very well suited as a pre- processor for image processing, particularly in connection with object isolation, edge detection and segmentation. Several implementations of PCNN on von Neumann computers, as well as on special parallel processing hardware devices (e.g. SIMD), exist. However, these implementations are not as flexible as required for many applications. Here we present an implementation in Field Programmable Gate Arrays (FPGA) together with a performance analysis. The FPGA hardware implementation may be considered a platform for further, extended implementations and easily expanded into various applications. The latter may include advanced on-line image analysis with close to real-time performance.

  7. Application of FPGA technology to performance limitations in radiation therapy

    NASA Astrophysics Data System (ADS)

    DeMarco, John J.; Smathers, J. B.; Solberg, Tim D.; Casselman, Steve

    1996-10-01

    The field programmable gate array (FPGA) is a promising technology for increasing computation performance by providing for the design of custom chips through programmable logic blocks. This technology was used to implement and test a hardware random number generator (RNG) versus four software algorithms. The custom hardware consists of a sun SBus-based board (EVC) which has been designed around a Xilinx FPGA. A timing analysis indicates the Sun/EVC hardware generator computes 1 multiplied by 106 random numbers approximately 50 times faster than the multiplicative congruential algorithm. The hardware and software RNGs were also compare using a Monte Carlo photon transport algorithm. For this comparison the Sun/EVC generator produces a performance increase of approximately 2.0 versus the software generators. This comparison is based upon 1 multiplied by 105 photon histories.

  8. A fast and accurate FPGA based QRS detection system.

    PubMed

    Shukla, Ashish; Macchiarulo, Luca

    2008-01-01

    An accurate Field Programmable Gate Array (FPGA) based ECG Analysis system is described in this paper. The design, based on a popular software based QRS detection algorithm, calculates the threshold value for the next peak detection cycle, from the median of eight previously detected peaks. The hardware design has accuracy in excess of 96% in detecting the beats correctly when tested with a subset of five 30 minute data records obtained from the MIT-BIH Arrhythmia database. The design, implemented using a proprietary design tool (System Generator), is an extension of our previous work and uses 76% resources available in a small-sized FPGA device (Xilinx Spartan xc3s500), has a higher detection accuracy as compared to our previous design and takes almost half the analysis time in comparison to software based approach.

  9. High-Performance CCSDS Encapsulation Service Implementation in FPGA

    NASA Technical Reports Server (NTRS)

    Clare, Loren P.; Torgerson, Jordan L.; Pang, Jackson

    2010-01-01

    The Consultative Committee for Space Data Systems (CCSDS) Encapsulation Service is a convergence layer between lower-layer space data link framing protocols, such as CCSDS Advanced Orbiting System (AOS), and higher-layer networking protocols, such as CFDP (CCSDS File Delivery Protocol) and Internet Protocol Extension (IPE). CCSDS Encapsulation Service is considered part of the data link layer. The CCSDS AOS implementation is described in the preceding article. Recent advancement in RF modem technology has allowed multi-megabit transmission over space links. With this increase in data rate, the CCSDS Encapsulation Service needs to be optimized to both reduce energy consumption and operate at a high rate. CCSDS Encapsulation Service has been implemented as an intellectual property core so that the aforementioned problems are solved by way of operating the CCSDS Encapsulation Service inside an FPGA. The CCSDS En capsula tion Service in FPGA implementation consists of both packetizing and de-packetizing features

  10. FPGA-based Klystron linearization implementations in scope of ILC

    SciTech Connect

    Omet, M.; Michizono, S.; Varghese, P.; Schlarb, H.; Branlard, J.; Cichalewski, W.

    2015-01-23

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successful implementation for one algorithm and a proof of principle for two algorithms. Furthermore, the functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation.

  11. FPGA-based Klystron linearization implementations in scope of ILC

    DOE PAGES

    Omet, M.; Michizono, S.; Matsumoto, T.; ...

    2015-01-23

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successfulmore » implementation for one algorithm and a proof of principle for two algorithms. Furthermore, the functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation.« less

  12. Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth

    2015-01-01

    This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

  13. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  14. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth; Pellish, Jonathan

    2015-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  15. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  16. On-chop processing for the wave union TDC implemented in FPGA

    SciTech Connect

    Wu, Jinyan; /Fermilab

    2009-05-01

    The wave union TDC implemented in FPGA utilizes multiple measurement method to reach time resolution beyond the natural carry cell delay in FPGA. Lacking of analog compensation for bin width control available in ASIC, the wave union TDC takes the after-fact digital calibration approach. In addition to the temperature drift, non-uniformity of the carry chain structure in FPGA causes complicate differential nonlinearity pattern which imposes significant on-chip calibration challenge. In this paper, processing strategies for the wave union TDC are discussed. Actual implementations in low-cost FPGA with 20ps and 10ps RMS resolutions are also presented.

  17. Graphics Processing Units for HEP trigger systems

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Bauce, M.; Biagioni, A.; Chiozzi, S.; Cotta Ramusino, A.; Fantechi, R.; Fiorini, M.; Giagu, S.; Gianoli, A.; Lamanna, G.; Lonardo, A.; Messina, A.; Neri, I.; Paolucci, P. S.; Piandani, R.; Pontisso, L.; Rescigno, M.; Simula, F.; Sozzi, M.; Vicini, P.

    2016-07-01

    General-purpose computing on GPUs (Graphics Processing Units) is emerging as a new paradigm in several fields of science, although so far applications have been tailored to the specific strengths of such devices as accelerator in offline computation. With the steady reduction of GPU latencies, and the increase in link and memory throughput, the use of such devices for real-time applications in high-energy physics data acquisition and trigger systems is becoming ripe. We will discuss the use of online parallel computing on GPU for synchronous low level trigger, focusing on CERN NA62 experiment trigger system. The use of GPU in higher level trigger system is also briefly considered.

  18. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  19. Partial reconfiguration of concurrent logic controllers implemented in FPGA devices

    NASA Astrophysics Data System (ADS)

    Wiśniewski, Remigiusz; Grobelna, Iwona; Stefanowicz, Łukasz

    2016-12-01

    Reconfigurable systems are recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers implemented in an FPGA device. An approach of designing of logic controllers oriented for further partial reconfiguration is proposed. A case study of a milling machine is used for an illustration.

  20. FPGA-oriented synthesis of multivalued logical networks

    NASA Astrophysics Data System (ADS)

    Deniziak, S.; Wiśniewski, M.; Kurczyna, K.

    2016-12-01

    Multivalued logical network consists of modules connected by multivalued signals. During synthesis each module is decomposed into smaller ones using the symbolic decomposition. Since the efficiency of the decomposition strongly depends on encoding of multivalued signals, the result of synthesis depends on the order, in which the consecutive modules are implemented. This paper presents the method of FPGA-oriented synthesis of multivalued logical networks. Experimental results showed that our approach significantly reduces the cost of implementation.

  1. Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components

    DTIC Science & Technology

    2007-11-02

    Reconfigurable Computing for Embedded Systems, FPGA Devices and Software Components Graham Bardouleau and James Kulp Mercury Computer Systems... Mercury Computer Systems. This paper describes the approach taken at Mercury to develop such a middleware and framework that supports the execution...ORGANIZATION NAME(S) AND ADDRESS(ES) Mercury Computer Systems, Inc. 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND

  2. Trigger mechanism for engines

    SciTech Connect

    Clark, L.R.

    1989-02-28

    A trigger mechanism is described for a blower-vacuum apparatus having a trigger mounted within a handle and a small engine comprising: a throttle; a ''L'' shaped lever having first and second legs mounted for rotation about an intermediate pivot within the handle when the trigger is depressed, interconnecting the trigger and the throttle, the second leg having first teeth defined therein, the lever further having idle, full throttle and stop positions; a normally raised latch means adapted to be rotated and axially depressed, the latch means having second teeth situated on a cam to engage the first teeth for holding the lever in an intermediate position between the idle and full throttle positions when the latch means is rotated. The latch means further are cam teeth into potential engagement with the lever teeth when the trigger is depressed, lever is biased to the stop position; and idle adjusting means means for intercepting the second leg for preventing the second leg from reaching the stop position when the latch means is raised.

  3. Design of transient light signal simulator based on FPGA

    NASA Astrophysics Data System (ADS)

    Kang, Jing; Chen, Rong-li; Wang, Hong

    2014-11-01

    A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

  4. An FPGA Implementation to Detect Selective Cationic Antibacterial Peptides

    PubMed Central

    Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

    2011-01-01

    Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides. PMID:21738652

  5. FPGA-based klystron linearization implementations in scope of ILC

    NASA Astrophysics Data System (ADS)

    Omet, M.; Michizono, S.; Matsumoto, T.; Miura, T.; Qiu, F.; Chase, B.; Varghese, P.; Schlarb, H.; Branlard, J.; Cichalewski, W.

    2014-12-01

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successful implementation for one algorithm and a proof of principle for two algorithms. The functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation. Besides this, a proof of principle of an FPGA-based klystron and cavity simulator implemented at the High Energy Accelerator Research Organization (KEK), Japan, was demonstrated. Its purpose is to allow the development and test of digital LLRF control systems including klystron linearization algorithms when no actual klystron and cavity are available.

  6. FPGA-based klystron linearization implementations in scope of ILC

    NASA Astrophysics Data System (ADS)

    Omet, M.; Michizono, S.; Matsumoto, T.; Miura, T.; Qiu, F.; Chase, B.; Varghese, P.; Schlarb, H.; Branlard, J.; Cichalewski, W.

    2015-04-01

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successful implementation for one algorithm and a proof of principle for two algorithms. The functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation. Besides this, a proof of principle of an FPGA-based klystron and cavity simulator implemented at the High Energy Accelerator Research Organization (KEK), Japan was demonstrated. Its purpose is to allow the development and test of digital LLRF control systems including klystron linearization algorithms when no actual klystron and cavity are available.

  7. An FPGA implementation to detect selective cationic antibacterial peptides.

    PubMed

    Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

    2011-01-01

    Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides.

  8. FPGA-based architecture for hyperspectral endmember extraction

    NASA Astrophysics Data System (ADS)

    Rosário, João.; Nascimento, José M. P.; Véstias, Mário

    2014-10-01

    Hyperspectral instruments have been incorporated in satellite missions, providing data of high spectral resolution of the Earth. This data can be used in remote sensing applications, such as, target detection, hazard prevention, and monitoring oil spills, among others. In most of these applications, one of the requirements of paramount importance is the ability to give real-time or near real-time response. Recently, onboard processing systems have emerged, in order to overcome the huge amount of data to transfer from the satellite to the ground station, and thus, avoiding delays between hyperspectral image acquisition and its interpretation. For this purpose, compact reconfigurable hardware modules, such as field programmable gate arrays (FPGAs) are widely used. This paper proposes a parallel FPGA-based architecture for endmember's signature extraction. This method based on the Vertex Component Analysis (VCA) has several advantages, namely it is unsupervised, fully automatic, and it works without dimensionality reduction (DR) pre-processing step. The architecture has been designed for a low cost Xilinx Zynq board with a Zynq-7020 SoC FPGA based on the Artix-7 FPGA programmable logic and tested using real hyperspectral data sets collected by the NASA's Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS) over the Cuprite mining district in Nevada. Experimental results indicate that the proposed implementation can achieve real-time processing, while maintaining the methods accuracy, which indicate the potential of the proposed platform to implement high-performance, low cost embedded systems, opening new perspectives for onboard hyperspectral image processing.

  9. Neural harmonic detection approaches for FPGA area efficient implementation

    NASA Astrophysics Data System (ADS)

    Dzondé, S. R. N.; Kom, C.-H.; Berviller, H.; Blondé, J.-P.; Flieller, D.; Kom, M.; Braun, F.

    2011-12-01

    This paper deals with new neural networks based harmonics detection approaches to minimize hardware resources needed for FPGA implementation. A simple type of neural network called Adaline is used to build an intelligent Active Power Filter control unit for harmonics current elimination and reactive power compensation. For this purpose, two different approaches called Improved Three-Monophase (ITM) and Two-Phase Flow (TPF) methods are proposed. The ITM method corresponds to a simplified structure of the three-monophase method whereas the TPF method derives from the Synchronous Reference Frame method. Indeed, for both proposed methods, only 50% of Adalines with regard to the original methods is used. The corresponding designs were implemented on a FPGA Stratix II platform through Altera DSP Builder® development tool. After analyzing those two methods with respect to performance and size criteria, a comparative study with the popular p-q and also the direct method is reported. From there, one can notice that the p-q is still the most powerful method for three-phase compensation but the TPF method is the fastest and the most compact in terms of size. An experimental result is shown to validate the feasibility of FPGA implementation of ANN-based harmonics extraction algorithms.

  10. Design of video interface conversion system based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhao, Heng; Wang, Xiang-jun

    2014-11-01

    This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

  11. JTAG test system for RPC muon trigger in the CMS experiment

    NASA Astrophysics Data System (ADS)

    Pozniak, Krzysztof T.; Romaniuk, Ryszard S.; Rutkowski, Piotr Z.; Kudla, Ignacy M.; Pietrusinski, Michal

    2003-10-01

    Theoretical and practical realization of the JTAG testing system for the RPC Muon Trigger of the CMS experiment at the LHC accelerator at CERN laboratory (Geneva) is presented. The paper covers issues related to tests of connections of the printed circuit boards (PCB) of the RPC Trigger. Functionality test of devices and modules were performed. Special test were designed for large PLD FPGA. Testing environment for the JTAG model is discussed. The model is based on some existing and some newly developed testing algorithms. Practical system realization is presented. The system consists of the hardware interface and the software layer. Software was built using C++ object oriented language and databases. Exemplary test of the RPC Muon Trigger electronics was performed and the results were given.

  12. Microfabricated triggered vacuum switch

    DOEpatents

    Roesler, Alexander W.; Schare, Joshua M.; Bunch, Kyle

    2010-05-11

    A microfabricated vacuum switch is disclosed which includes a substrate upon which an anode, cathode and trigger electrode are located. A cover is sealed over the substrate under vacuum to complete the vacuum switch. In some embodiments of the present invention, a metal cover can be used in place of the trigger electrode on the substrate. Materials used for the vacuum switch are compatible with high vacuum, relatively high temperature processing. These materials include molybdenum, niobium, copper, tungsten, aluminum and alloys thereof for the anode and cathode. Carbon in the form of graphitic carbon, a diamond-like material, or carbon nanotubes can be used in the trigger electrode. Channels can be optionally formed in the substrate to mitigate against surface breakdown.

  13. Triggered Nanoparticles as Therapeutics

    PubMed Central

    Kim, Chang Soo; Duncan, Bradley; Creran, Brian; Rotello, Vincent M.

    2013-01-01

    Summary Drug delivery systems (DDSs) face several challenges including site-specific delivery, stability, and the programmed release of drugs. Engineered nanoparticle (NP) surfaces with responsive moieties can enhance the efficacy of DDSs for in vitro and in vivo systems. This triggering process can be achieved through both endogenous (biologically controlled release) and exogenous (external stimuli controlled release) activation. In this review, we will highlight recent examples of the use of triggered release strategies of engineered nanomaterials for in vitro and in vivo applications. PMID:24159362

  14. Trigger Circuit for Marx Generators

    DTIC Science & Technology

    2001-02-08

    A trigger circuit is provided for a trigger system for a Marx generator column. The column includes a plurality of metal electrode pairs wherein the...electrode (trigatron) spark gap switch forming the first spark gap of the Marx generator column. The triggering circuit includes a trigger

  15. SAD5 Stereo Correlation Line-Striping in an FPGA

    NASA Technical Reports Server (NTRS)

    Villalpando, Carlos Y.; Morfopoulos, Arin C.

    2011-01-01

    High precision SAD5 stereo computations can be performed in an FPGA (field-programmable gate array) at much higher speeds than possible in a conventional CPU (central processing unit), but this uses large amounts of FPGA resources that scale with image size. Of the two key resources in an FPGA, Slices and BRAM (block RAM), Slices scale linearly in the new algorithm with image size, and BRAM scales quadratically with image size. An approach was developed to trade latency for BRAM by sub-windowing the image vertically into overlapping strips and stitching the outputs together to create a single continuous disparity output. In stereo, the general rule of thumb is that the disparity search range must be 1/10 the image size. In the new algorithm, BRAM usage scales linearly with disparity search range and scales again linearly with line width. So a doubling of image size, say from 640 to 1,280, would in the previous design be an effective 4 of BRAM usage: 2 for line width, 2 again for disparity search range. The minimum strip size is twice the search range, and will produce an output strip width equal to the disparity search range. So assuming a disparity search range of 1/10 image width, 10 sequential runs of the minimum strip size would produce a full output image. This approach allowed the innovators to fit 1280 960 wide SAD5 stereo disparity in less than 80 BRAM, 52k Slices on a Virtex 5LX330T, 25% and 24% of resources, respectively. Using a 100-MHz clock, this build would perform stereo at 39 Hz. Of particular interest to JPL is that there is a flight qualified version of the Virtex 5: this could produce stereo results even for very large image sizes at 3 orders of magnitude faster than could be computed on the PowerPC 750 flight computer. The work covered in the report allows the stereo algorithm to run on much larger images than before, and using much less BRAM. This opens up choices for a smaller flight FPGA (which saves power and space), or for other algorithms

  16. Assessment of Proper Bonding Methods and Mechanical Characterization FPGA CQFPs

    NASA Technical Reports Server (NTRS)

    Davis, Milton C.

    2008-01-01

    This presentation discusses fractured leads on field-programmable gate array (FPGA) during flight vibration. Actions taken to determine root cause and resolution of the failure include finite element analysis (FEA) and vibration testing and scanning electron microscopy (with X-ray microanalysis) and energy dispersive spectrometry (SEM/EDS) failure assessment. Bonding methods for surface mount parts is assessed, including critical analysis and assessment of random fatigue damage. Regarding ceramic quad flat pack (CQFP) lead fracture, after disassembling the attitude control electronics (ACE) configuration, photographs showed six leads cracked on FPGA RTSX72SU-1 CQ208B package located on the RWIC card. An identical package (FPGA RTSX32SU-1 CQ208B) mounted on the RWIC did not results in cracked pins due to vibration. FPGA lead failure theories include workmanship issues in the lead-forming, material defect in the leads of the FPGA packages, and the insecure mounting of the board in the card guides, among other theories. Studies were conducted using simple calculations to determine the response and fatigue life of the package. Shorter packages exhibited more response when loaded by out-of-plane displacement of PCB while taller packages exhibit more response when loaded by in-plane acceleration of PCB. Additionally, under-fill did not contribute to reducing stress in leads due to out-of-plane PCB loading or from component twisting, as much as corner bonding. The combination of corner bond and under-fill is best to address mechanical and thermal S/C environment. Test results of bonded parts showed reduced (dampened) amplitude and slightly shifted peaks at the un-bonded natural frequency and an additional response at the bonded frequency. Stress due to PCBB out-of-plane loading was decreased on in the corners when only a corner bond was used. Future work may address CQFP fatigue assessment, including the investigation of discrepancy in predicted fatigue damage, as well as

  17. Economical Implementation of a Filter Engine in an FPGA

    NASA Technical Reports Server (NTRS)

    Kowalski, James E.

    2009-01-01

    A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

  18. An FPGA-based data acquisition system for directional dark matter detection

    NASA Astrophysics Data System (ADS)

    Yang, Chen; Nicoloff, Catherine; Sanaullah, Ahmed; Sridhar, Arvind; Herbordt, Martin; Battat, James; Battat Lab at Wellesley College Team; CAAD Lab at Boston University Team

    2017-01-01

    Directional dark matter detection is a powerful tool in the search for dark matter. Low-pressure gas TPCs are commonly used for directional detection, and dark-matter-induced recoils are mm long. These tracks can be reconstructed by micropatterned readouts. Because large detector volumes are needed, a cost-effective data acquisition system capable of scaling to large channel counts (105 or 106) is required. The Directional Recoil Identification From Tracks (DRIFT) collaboration has pioneered the use of TPCs for directional detection. We employ a negative ion gas with drift speed comparable to the electron drift speed in liquid argon (LAr). We aim to use electronics developed for million-channel readouts in large LAr neutrino detectors. We have built a prototype Micromegas-based directional detector with 103 channels. A FPGA-based back-end system (BE) receives a 12 Gbps data stream from eight ASIC-based front-end boards (FE), each with 128 detector channels. The BE buffers 3 μs of pretrigger data for all channels in DRAM, and streams triggered data to a host PC. We will describe the system architecture and present preliminary measurements from the DAQ. We acknowledge the support of the Research Corporation for Science Advancement, the NSF and the Massachusetts Space Grant Consortium.

  19. A flexible FPGA based QDC and TDC for the HADES and the CBM calorimeters

    NASA Astrophysics Data System (ADS)

    Rost, A.; Galatyuk, T.; Koenig, W.; Michel, J.; Pietraszko, J.; Skott, P.; Traxler, M.

    2017-02-01

    A Charge-to-Digital-Converter (QDC) and Time-to-Digital-Converter (TDC) based on a commercial FPGA (Field Programmable Gate Array) was developed to read out PMT signals of the planned HADES electromagnetic calorimeter (ECAL) at GSI Helmholtzzentrum für Schwerionenforschung GmbH (Darmstadt, Germany). The main idea is to convert the charge measurement of a detector signal into a time measurement, where the charge is encoded in the width of a digital pulse, while the arrival time information is encoded in the leading edge time of the pulse. The PaDiWa-AMPS prototype front-end board for the TRB3 (General Purpose Trigger and Readout Board—version 3) which implements this conversion method was developed and qualified. The already well established TRB3 platform provides the needed precise time measurements and serves as a data acquisition system. We present the read-out concept and the performance of the prototype boards in laboratory and also under beam conditions. First steps have been completed in order to adapt this concept to SiPM signals of the hadron calorimeter in the CBM experiment at the planned FAIR facility (Darmstadt).

  20. AIDS radio triggers.

    PubMed

    Elias, A M

    1991-07-01

    In April 1991, the Ethnic Communities' Council of NSW was granted funding under the Community AIDS Prevention and Education Program through the Department of Community Services and Health, to produce a series of 6x50 second AIDS radio triggers with a 10-second tag line for further information. The triggers are designed to disseminate culturally-sensitive information about HIV/AIDS in English, Italian, Greek, Spanish, Khmer, Turkish, Macedonian, Serbo-Croatian, Arabic, Cantonese, and Vietnamese, with the goal of increasing awareness and decreasing the degree of misinformation about HIV/AIDS among people of non-English-speaking backgrounds through radio and sound. The 6 triggers cover the denial that AIDS exists in the community, beliefs that words and feelings do not protect one from catching HIV, encouraging friends to be compassionate, compassion within the family, AIDS information for a young audience, and the provision of accurate and honest information on HIV/AIDS. The triggers are slated to be completed by the end of July 1991 and will be broadcast on all possible community, ethnic, and commercial radio networks across Australia. They will be available upon request in composite form with an information kit for use by health care professionals and community workers.

  1. Triggered plasma opening switch

    DOEpatents

    Mendel, Clifford W.

    1988-01-01

    A triggerable opening switch for a very high voltage and current pulse includes a transmission line extending from a source to a load and having an intermediate switch section including a plasma for conducting electrons between transmission line conductors and a magnetic field for breaking the plasma conduction path and magnetically insulating the electrons when it is desired to open the switch.

  2. Remotely triggered earthquakes following moderate main shocks

    USGS Publications Warehouse

    Hough, S.E.

    2007-01-01

    Since 1992, remotely triggered earthquakes have been identified following large (M > 7) earthquakes in California as well as in other regions. These events, which occur at much greater distances than classic aftershocks, occur predominantly in active geothermal or volcanic regions, leading to theories that the earthquakes are triggered when passing seismic waves cause disruptions in magmatic or other fluid systems. In this paper, I focus on observations of remotely triggered earthquakes following moderate main shocks in diverse tectonic settings. I summarize evidence that remotely triggered earthquakes occur commonly in mid-continent and collisional zones. This evidence is derived from analysis of both historic earthquake sequences and from instrumentally recorded M5-6 earthquakes in eastern Canada. The latter analysis suggests that, while remotely triggered earthquakes do not occur pervasively following moderate earthquakes in eastern North America, a low level of triggering often does occur at distances beyond conventional aftershock zones. The inferred triggered events occur at the distances at which SmS waves are known to significantly increase ground motions. A similar result was found for 28 recent M5.3-7.1 earthquakes in California. In California, seismicity is found to increase on average to a distance of at least 200 km following moderate main shocks. This supports the conclusion that, even at distances of ???100 km, dynamic stress changes control the occurrence of triggered events. There are two explanations that can account for the occurrence of remotely triggered earthquakes in intraplate settings: (1) they occur at local zones of weakness, or (2) they occur in zones of local stress concentration. ?? 2007 The Geological Society of America.

  3. Development of Data Acquisition Methods for an FPGA-Based Photon Counting Detector

    NASA Astrophysics Data System (ADS)

    Ambily, S.; Sarpotdar, Mayuresh; Mathew, Joice; Sreejith, A. G.; Nirmal, K.; Prakash, Ajin; Safonova, Margarita; Murthy, Jayant

    MCP-based detectors are widely used in the ultraviolet (UV) region due to their low noise levels, high sensitivity and good spatial and temporal resolution. We have developed a compact near-UV (NUV) detector for high-altitude balloon and space flights, using off-the-shelf MCP, CMOS sensor, and optics. The detector is designed to be capable of working in the direct frame transfer mode as well in the photon counting mode for single photon event detection. The identification and centroiding of each photon event are done using an FPGA-based data acquisition and real-time processing system. In this paper, we discuss various algorithms and methods used in both operating modes, as well as their implementation on the hardware.

  4. FPGA-based real-time anisotropic diffusion filtering of 3D ultrasound images

    NASA Astrophysics Data System (ADS)

    Castro-Pareja, Carlos R.; Dandekar, Omkar S.; Shekhar, Raj

    2005-02-01

    Three-dimensional ultrasonic imaging, especially the emerging real-time version of it, is particularly valuable in medical applications such as echocardiography, obstetrics and surgical navigation. A known problem with ultrasound images is their high level of speckle noise. Anisotropic diffusion filtering has been shown to be effective in enhancing the visual quality of 3D ultrasound images and as preprocessing prior to advanced image processing. However, due to its arithmetic complexity and the sheer size of 3D ultrasound images, it is not possible to perform online, real-time anisotropic diffusion filtering using standard software implementations. We present an FPGA-based architecture that allows performing anisotropic diffusion filtering of 3D images at acquisition rates, thus enabling the use of this filtering technique in real-time applications, such as visualization, registration and volume rendering.

  5. Frequency-controlable sine signal based on PWM and its implementation on FPGA

    NASA Astrophysics Data System (ADS)

    Huang, Lianzhen; Li, Jiangang; Zhang, Dongjun

    2012-09-01

    A sine generation method that the different frequent sine signals can be generated by the different Pulse-Width Modulation (PWM) signals generated by Field-Programmable Gate Array (FPGA) through low-pass filter of fixed parameters was proposed. The method just takes a few FPGA resources and was proved feasible by the theory. The experiment results and theory analysis tally.

  6. Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

    NASA Astrophysics Data System (ADS)

    Li, Ce; Dong, Yiping; Watanabe, Takahiro

    An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR[1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

  7. Design for Review - Applying Lessons Learned to Improve the FPGA Review Process

    NASA Technical Reports Server (NTRS)

    Figueiredo, Marco A.; Li, Kenneth E.

    2014-01-01

    Flight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.

  8. A programmable controller based on CAN field bus embedded microprocessor and FPGA

    NASA Astrophysics Data System (ADS)

    Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

    2008-10-01

    One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

  9. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

    SciTech Connect

    Asaad, Sameth W.; Kapur, Mohit

    2016-01-05

    A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

  10. Trigger developments for ARA

    NASA Astrophysics Data System (ADS)

    Lu, Ming-Yuan

    2013-04-01

    The Askaryan Radio Array (ARA) is a planned large-scale neutrino detector at the South Pole aiming at observing ultra-high-energy cosmogenic neutrinos via detecting radio Cherenkov radiation from neutrinos' interaction with Antarctic ice. By the end of the austral summer of 2012/13 three detector stations have been deployed at depths of up to 200 m. A prototype detector station has been taking data for two years. The final array is planned to consist of 37 stations with a 200 km^2 coverage, and provide high sensitivity in the range of 10 PeV to 10 EeV. In order to increase the discover potential of the stations, advanced triggering schemes are in development which take into account the topology of signal events. Here a brief status and the triggering schemes in development will be presented, and based on simulations their improvements to ARA neutrino sensitivity will be discussed.

  11. Neural networks for triggering

    SciTech Connect

    Denby, B. ); Campbell, M. ); Bedeschi, F. ); Chriss, N.; Bowers, C. ); Nesti, F. )

    1990-01-01

    Two types of neural network beauty trigger architectures, based on identification of electrons in jets and recognition of secondary vertices, have been simulated in the environment of the Fermilab CDF experiment. The efficiencies for B's and rejection of background obtained are encouraging. If hardware tests are successful, the electron identification architecture will be tested in the 1991 run of CDF. 10 refs., 5 figs., 1 tab.

  12. GLAST's GBM Burst Trigger

    NASA Technical Reports Server (NTRS)

    Band, D.; Briggs, M.; Connaughton, V.; Kippen, M.; Preece, R.

    2003-01-01

    The GLAST Burst Monitor (GBM) will detect and localize bursts for the GLAST mission, and provide the spectral and temporal context in the traditional 10 keV to 25 MeV band for the high energy observations by the Large Area Telescope (LAT). The GBM will use traditional rate triggers in up to three energy bands, and on a variety of timescales between 16 ms and 16 s.

  13. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    PubMed

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  14. Report of the Odyssey FPGA Independent Assessment Team

    NASA Technical Reports Server (NTRS)

    Mayer, Donald C.; Katz, Richard B.; Osborn, Jon V.; Soden, Jerry M.; Barto, R.; Day, John H. (Technical Monitor)

    2001-01-01

    An independent assessment team (IAT) was formed and met on April 2, 2001, at Lockheed Martin in Denver, Colorado, to aid in understanding a technical issue for the Mars Odyssey spacecraft scheduled for launch on April 7, 2001. An RP1280A field-programmable gate array (FPGA) from a lot of parts common to the SIRTF, Odyssey, and Genesis missions had failed on a SIRTF printed circuit board. A second FPGA from an earlier Odyssey circuit board was also known to have failed and was also included in the analysis by the IAT. Observations indicated an abnormally high failure rate for flight RP1280A devices (the first flight lot produced using this flow) at Lockheed Martin and the causes of these failures were not determined. Standard failure analysis techniques were applied to these parts, however, additional diagnostic techniques unique for devices of this class were not used, and the parts were prematurely submitted to a destructive physical analysis, making a determination of the root cause of failure difficult. Any of several potential failure scenarios may have caused these failures, including electrostatic discharge, electrical overstress, manufacturing defects, board design errors, board manufacturing errors, FPGA design errors, or programmer errors. Several of these mechanisms would have relatively benign consequences for disposition of the parts currently installed on boards in the Odyssey spacecraft if established as the root cause of failure. However, other potential failure mechanisms could have more dire consequences. As there is no simple way to determine the likely failure mechanisms with reasonable confidence before Odyssey launch, it is not possible for the IAT to recommend a disposition for the other parts on boards in the Odyssey spacecraft based on sound engineering principles.

  15. Enhanced Temperature Control Method Using ANFIS with FPGA

    PubMed Central

    Zhou, Jun-Tin

    2014-01-01

    Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS) using a field-programmable gate array (FPGA) to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV) inductively-coupled plasma- (ICP-) type etcher. PMID:24715808

  16. DSP algorithms in FPGA: proposition of a new architecture

    NASA Astrophysics Data System (ADS)

    Kolasinski, Piotr; Zabolotny, Wojciech

    2008-01-01

    This paper presents a new reconfigurable architecture created in FPGA which is optimized for DSP algorithms like digital filters or digital transforms. The architecture tries to combine advantages of typical architectures like DSP processors and datapath architecture, while avoiding their drawbacks. The architecture is built from blocks called Operational Units (OU). Each Operational Unit contains the Control Unit (CU), which controls its operation. The Operational Units may operate in parallel, which shortens the processing time. This structure is also highly flexible, because all OUs may operate independently, executing their own programs. User may customize connections between units and modify architecture by adding new modules.

  17. FPGA implementation of a pyramidal Weightless Neural Networks learning system.

    PubMed

    Al-Alawi, Raida

    2003-08-01

    A hardware architecture of a Probabilistic Logic Neuron (PLN) is presented. The suggested model facilitates the on-chip learning of pyramidal Weightless Neural Networks using a modified probabilistic search reward/penalty training algorithm. The penalization strategy of the training algorithm depends on a predefined parameter called the probabilistic search interval. A complete Weightless Neural Network (WNN) learning system is modeled and implemented on Xilinx XC4005E Field Programmable Gate Array (FPGA), allowing its architecture to be configurable. Various experiments have been conducted to examine the feasibility and performance of the WNN learning system. Results show that the system has a fast convergence rate and good generalization ability.

  18. FPGA implementation of trellis decoders for linear block codes

    NASA Astrophysics Data System (ADS)

    Scholl, S.; Leonardi, E.; Wehn, N.

    2014-11-01

    Forward error correction based on trellises has been widely adopted for convolutional codes. Because of their efficiency, they have also gained a lot of interest from a theoretic and algorithm point of view for the decoding of block codes. In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes. A key feature is the use of a sophisticated permutation network, the Banyan network, to implement the time varying structure of the trellis. We have implemented the Viterbi and the max-log-MAP algorithm in different folded versions on a Xilinx Virtex 6 FPGA.

  19. Adaptive 4~64 QAM real-time coherent optical transmission over 320 km with FPGA-based transmitter and receiver.

    PubMed

    Yoshida, Masato; Hirooka, Toshihiko; Kasai, Keisuke; Nakazawa, Masataka

    2014-06-30

    We demonstrate the first real-time adaptive optical coherent QAM transmission with variable multiplicities (4-, 16- and 64-QAM) using an FPGA-based transmitter and receiver. Rate-variable transmission (20~60 Gbit/s) was successfully achieved with a polarization multiplexing scheme at 5 Gsymbol/s over 320 km, where the OSNR margins were increased by 9 and 17 dB, respectively, by changing the modulation level from 64 to 16 and 4.

  20. FPGA implementation of the hyperspectral Lossy Compression for Exomars (LCE) algorithm

    NASA Astrophysics Data System (ADS)

    García, Aday; Santos, L.; López, S.; Callicó, G. M.; López, J. F.; Sarmiento, R.

    2014-10-01

    The increase of data rates and data volumes in present remote sensing payload instruments, together with the restrictions imposed in the downlink connection requirements, represent at the same time a challenge and a must in the field of data and image compression. This is especially true for the case of hyperspectral images, in which both, reduction of spatial and spectral redundancy is mandatory. Recently the Consultative Committee for Space Data Systems (CCSDS) published the Lossless Multispectral and Hyperespectral Image Compression recommendation (CCSDS 123), a prediction-based technique resulted from the consensus of its members. Although this standard offers a good trade-off between coding performance and computational complexity, the appearance of future hyperspectral and ultraspectral sensors with vast amount of data imposes further efforts from the scientific community to ensure optimal transmission to ground stations based on greater compression rates. Furthermore, hardware implementations with specific features to deal with solar radiation problems play an important role in order to achieve real time applications. In this scenario, the Lossy Compression for Exomars (LCE) algorithm emerges as a good candidate to achieve these characteristics. Its good quality/compression ratio together with its low complexity facilitates the implementation in hardware platforms such as FPGAs or ASICs. In this work the authors present the implementation of the LCE algorithm into an antifuse-based FPGA and the optimizations carried out to obtain the RTL description code using CatapultC, a High Level Synthesis (HLS) Tool. Experimental results show an area occupancy of 75% in an RTAX2000 FPGA from Microsemi, with an operating frequency of 18 MHz. Additionally, the power budget obtained is presented giving an idea of the suitability of the proposed algorithm implementation for onboard compression applications.

  1. 40-Gbps optical backbone network deep packet inspection based on FPGA

    NASA Astrophysics Data System (ADS)

    Zuo, Yuan; Huang, Zhiping; Su, Shaojing

    2014-11-01

    In the era of information, the big data, which contains huge information, brings about some problems, such as high speed transmission, storage and real-time analysis and process. As the important media for data transmission, the Internet is the significant part for big data processing research. With the large-scale usage of the Internet, the data streaming of network is increasing rapidly. The speed level in the main fiber optic communication of the present has reached 40Gbps, even 100Gbps, therefore data on the optical backbone network shows some features of massive data. Generally, data services are provided via IP packets on the optical backbone network, which is constituted with SDH (Synchronous Digital Hierarchy). Hence this method that IP packets are directly mapped into SDH payload is named POS (Packet over SDH) technology. Aiming at the problems of real time process of high speed massive data, this paper designs a process system platform based on ATCA for 40Gbps POS signal data stream recognition and packet content capture, which employs the FPGA as the CPU. This platform offers pre-processing of clustering algorithms, service traffic identification and data mining for the following big data storage and analysis with high efficiency. Also, the operational procedure is proposed in this paper. Four channels of 10Gbps POS signal decomposed by the analysis module, which chooses FPGA as the kernel, are inputted to the flow classification module and the pattern matching component based on TCAM. Based on the properties of the length of payload and net flows, buffer management is added to the platform to keep the key flow information. According to data stream analysis, DPI (deep packet inspection) and flow balance distribute, the signal is transmitted to the backend machine through the giga Ethernet ports on back board. Practice shows that the proposed platform is superior to the traditional applications based on ASIC and NP.

  2. An IO block array in a radiation-hardened SOI SRAM-based FPGA

    NASA Astrophysics Data System (ADS)

    Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

    2012-01-01

    We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

  3. AMPLITUDE DISCRIMINATOR HAVING SEPARATE TRIGGERING AND RECOVERY CONTROLS UTILIZING AUTOMATIC TRIGGERING

    DOEpatents

    Chase, R.L.

    1962-01-23

    A transistorized amplitude discriminator circuit is described in which the initial triggering sensitivity and the recovery threshold are separately adjustable in a convenient manner. The discriminator is provided with two independent bias components, one of which is for circuit hysteresis (recovery) and one of which is for trigger threshold level. A switching circuit is provided to remove the second bias component upon activation of the trigger so that the recovery threshold is always at the point where the trailing edge of the input signal pulse goes through zero or other desired value. (AEC)

  4. GPUs for real-time processing in HEP trigger systems

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Deri, L.; Fiorini, M.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Messina, A.; Sozzi, M.; Pantaleo, F.; Paolucci, Ps; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.; Gap Collaboration

    2014-06-01

    We describe a pilot project (GAP - GPU Application Project) for the use of GPUs (Graphics processing units) for online triggering applications in High Energy Physics experiments. Two major trends can be identified in the development of trigger and DAQ systems for particle physics experiments: the massive use of general-purpose commodity systems such as commercial multicore PC farms for data acquisition, and the reduction of trigger levels implemented in hardware, towards a fully software data selection system ("trigger-less"). The innovative approach presented here aims at exploiting the parallel computing power of commercial GPUs to perform fast computations in software not only in high level trigger levels but also in early trigger stages. General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to the specific strengths of such devices as accelerators in offline computation. With the steady reduction of GPU latencies, and the increase in link and memory throughputs, the use of such devices for real-time applications in high energy physics data acquisition and trigger systems is becoming relevant. We discuss in detail the use of online parallel computing on GPUs for synchronous low-level triggers with fixed latency. In particular we show preliminary results on a first test in the CERN NA62 experiment. The use of GPUs in high level triggers is also considered, the CERN ATLAS experiment being taken as a case study of possible applications.

  5. Bufalin induces G0/G1 phase arrest through inhibiting the levels of cyclin D, cyclin E, CDK2 and CDK4, and triggers apoptosis via mitochondrial signaling pathway in T24 human bladder cancer cells.

    PubMed

    Huang, Wen-Wen; Yang, Jai-Sing; Pai, Shu-Jen; Wu, Ping-Ping; Chang, Shu-Jen; Chueh, Fu-Shin; Fan, Ming-Jen; Chiou, Shang-Ming; Kuo, Hsiu-Maan; Yeh, Chin-Chung; Chen, Po-Yuan; Tsuzuki, Minoru; Chung, Jing-Gung

    2012-04-01

    Most of the chemotherapy treatments for bladder cancer aim to kill the cancer cells, but a high recurrence rate after medical treatments is still occurred. Bufalin from the skin and parotid venom glands of toad has been shown to induce apoptotic cell death in many types of cancer cell lines. However, there is no report addressing that bufalin induced cell death in human bladder cancer cells. The purpose of this study was investigated the mechanisms of bufalin-induced apoptosis in a human bladder cancer cell line (T24). We demonstrated the effects of bufalin on the cell growth and apoptosis in T24 cells by using DAPI/TUNEL double staining, a PI exclusion and flow cytometric analysis. The effects of bufalin on the production of reactive oxygen species (ROS), the level of mitochondrial membrane potential (ΔΨ(m)), and DNA content including sub-G1 (apoptosis) in T24 cells were also determined by flow cytometry. Western blot analysis was used to examine the expression of G(0)/G(1) phase-regulated and apoptosis-associated protein levels in bufalin-treated T24 cells. The results indicated that bufalin significantly decreased the percentage of viability, induced the G(0)/G(1) phase arrest and triggered apoptosis in T24 cells. The down-regulation of the protein levels for cyclin D, CDK4, cyclin E, CDK2, phospho-Rb, phospho-AKT and Bcl-2 with the simultaneous up-regulation of the cytochrome c, Apaf-1, AIF, caspase-3, -7 and -9 and Bax protein expressions and caspase activities were observed in T24 cells after bufalin treatment. Based on our results, bufalin induces apoptotic cell death in T24 cells through suppressing AKT activity and anti-apoptotic Bcl-2 protein as well as inducing pro-apoptotic Bax protein. The levels of caspase-3, -7 and -9 are also mediated apoptosis in bufalin-treated T24 cells. Therefore, bufalin might be used as a therapeutic agent for the treatment of human bladder cancer in the future.

  6. Numerical modeling of shallow fault creep triggered by nearby earthquakes

    NASA Astrophysics Data System (ADS)

    Wei, M.; Liu, Y.; McGuire, J. J.

    2011-12-01

    The 2010 El Mayor-Cucapha Mw 7.2 earthquake is the largest earthquake that strikes southern California in the last 18 years. It has triggered shallow fault creep on many faults in Salton Trough, Southern California, making it at least the 8th time in the last 42 years that a local or regional earthquake has done so. However, the triggering mechanism of fault creep and its implications to seismic hazard and fault mechanics is still poorly understood. For example, what determines the relative importance of static triggering and dynamic triggering of fault creep? What can we learn about the local frictional properties and normal stress from the triggering of fault creep? To understand the triggering mechanism and constrain fault frictional properties, we simulate the triggered fault creep on the Superstition Hills Fault (SHF), Salton Trough, Southern California. We use realistic static and dynamic shaking due to nearby earthquakes as stress perturbations to a 2D (in a 3D medium) planar fault model with rate-and-state frictional property variations both in depth and along strike. Unlike many previous studies, we focus on the simulation of triggered shallow fault creep instead of earthquakes. Our fault model can reproduce the triggering process, by static, dynamic , and combined stress perturbation. Preliminary results show that the magnitude of perturbation relative to the original stress level is an important parameter. In the static case, perturbation of 1% of normal stress trigger delayed fault creep whereas 10% of normal stress generate instantaneous creep. In the dynamic case, a change of two times in magnitude of perturbation can result in difference of triggered creep in several orders of magnitude. We explore combined triggering with different ratio of static and dynamic perturbation. The timing of triggering in a earthquake cycle is also important. With measurements on triggered creep on the SHF, we constrain local stress level and frictional parameters, which

  7. Malleable architecture generator for FPGA computing

    NASA Astrophysics Data System (ADS)

    Gokhale, Maya; Kaba, James; Marks, Aaron; Kim, Jang

    1996-10-01

    The malleable architecture generator (MARGE) is a tool set that translates high-level parallel C to configuration bit streams for field-programmable logic based computing systems. MARGE creates an application-specific instruction set and generates the custom hardware components required to perform exactly those computations specified by the C program. In contrast to traditional fixed-instruction processors, MARGE's dynamic instruction set creation provides for efficient use of hardware resources. MARGE processes intermediate code in which each operation is annotated by the bit lengths of the operands. Each basic block (sequence of straight line code) is mapped into a single custom instruction which contains all the operations and logic inherent in the block. A synthesis phase maps the operations comprising the instructions into register transfer level structural components and control logic which have been optimized to exploit functional parallelism and function unit reuse. As a final stage, commercial technology-specific tools are used to generate configuration bit streams for the desired target hardware. Technology- specific pre-placed, pre-routed macro blocks are utilized to implement as much of the hardware as possible. MARGE currently supports the Xilinx-based Splash-2 reconfigurable accelerator and National Semiconductor's CLAy-based parallel accelerator, MAPA. The MARGE approach has been demonstrated on systolic applications such as DNA sequence comparison.

  8. Efficient Multiplexer FPGA Block Structures Based on G4FETs

    NASA Technical Reports Server (NTRS)

    Vatan, Farrokh; Fijany, Amir

    2009-01-01

    Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few

  9. The D/Ø Silicon Track Trigger

    NASA Astrophysics Data System (ADS)

    Steinbrück, Georg

    2003-09-01

    We describe a trigger preprocessor to be used by the D Ø experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam.

  10. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces

    PubMed Central

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Hidalgo-López, José A.

    2015-01-01

    Direct sensor–digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor. PMID:26694403

  11. Design of extensible meteorological data acquisition system based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhang, Wen; Liu, Yin-hua; Zhang, Hui-jun; Li, Xiao-hui

    2015-02-01

    In order to compensate the tropospheric refraction error generated in the process of satellite navigation and positioning. Temperature, humidity and air pressure had to be used in concerned models to calculate the value of this error. While FPGA XC6SLX16 was used as the core processor, the integrated silicon pressure sensor MPX4115A and digital temperature-humidity sensor SHT75 are used as the basic meteorological parameter detection devices. The core processer was used to control the real-time sampling of ADC AD7608 and to acquire the serial output data of SHT75. The data was stored in the BRAM of XC6SLX16 and used to generate standard meteorological parameters in NEMA format. The whole design was based on Altium hardware platform and ISE software platform. The system was described in the VHDL language and schematic diagram to realize the correct detection of temperature, humidity, air pressure. The 8-channel synchronous sampling characteristics of AD7608 and programmable external resources of FPGA laid the foundation for the increasing of analog or digital meteorological element signal. The designed meteorological data acquisition system featured low cost, high performance, multiple expansions.

  12. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

    PubMed

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2015-12-16

    Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

  13. NUC correction of IR FPA and error analysis with FPGA

    NASA Astrophysics Data System (ADS)

    Ge, Cheng-liang; Liu, Zhi-qiang; Wu, Jian-tao; Li, Zheng-dong; Huang, Zhi-wei; Wan, Min; Hu, Xiao-yang; Fan, Guo-bin; Liang, Zheng

    2008-02-01

    Infrared camera with IR FPA (Focal Plane Array) has often been used in the fields of target detection, temperature test, surface detection, and so on. And it is very important to run the Non Uniformity Correction (NUC) correction firstly to solve the non-uniformity of FPA which is the inherent character of IR FPA. The NUC character is the inherent performance of IR FPA which has different response rate among pixels for the same IR radiant. This NUC can decrease sensitivity of IR FPA and reduce the resolution of sensor. There are two kinds of methods to do this correction. One is hardware method which is using the DSP. Another one is software method. Within this device, two-point correction method is used to correct the NUC. The Field Programmable Gate Array (FPGA) is used. The FPGA can do better parallel arithmetic and has more programmability. After the NUC correction, the error analysis of this correction is also made. After the correction, the BPR (Bad Pixel Replacement) can be more than 98%.

  14. Development of DSP and FPGA based 4-axis motion controller

    NASA Astrophysics Data System (ADS)

    He, Shuai; Gao, Xiaorong; Peng, Chaoyong; Zhang, Yu

    2010-08-01

    This paper presents a DSP and FPGA based 4-axis motion controller, which use host PC as the platform. By adopting the strategy of two stage interpolation, the proposed motion controller supports 2-axis circular interpolation and 3-axis linear interpolation, and its maximum output pulse frequency of each axis can be up to 8 MHz. The controlling algorithms, such as improved coarse interpolation based on the time division principle, T-curve and S-curve velocity profile generation and the error compensation for the position loop, are implemented by DSP to ensure the high performance of the proposed motion controller. Meanwhile, the FPGA integrates PCI bus controller, dual port RAM, second-stage interpolation, encoder feedback logic circuit etc., which allows a flexible, compact, low-cost solution for various applications. Experimental results demonstrate that the presented motion controller features the merits such as the good real-time performance and high machining precision, and it can be used for a wide range of applications in numerical control system.

  15. An FPGA-based open platform for ultrasound biomicroscopy.

    PubMed

    Qiu, Weibao; Yu, Yanyan; Tsang, Fu; Sun, Lei

    2012-07-01

    Ultrasound biomicroscopy (UBM) has been extensively applied to preclinical studies in small animal models. Individual animal study is unique and requires different utilization of the UBM system to accommodate different transducer characteristics, data acquisition strategies, signal processing, and image reconstruction methods. There is a demand for a flexible and open UBM platform to allow users to customize the system for various studies and have full access to experimental data. This paper presents the development of an open UBM platform (center frequency 20 to 80 MHz) for various preclinical studies. The platform design was based on a field-programmable gate array (FPGA) embedded in a printed circuit board to achieve B-mode imaging and directional pulsed-wave Doppler. Instead of hardware circuitry, most functions of the platform, such as filtering, envelope detection, and scan conversion, were achieved by FPGA programs; thus, the system architecture could be easily modified for specific applications. In addition, a novel digital quadrature demodulation algorithm was implemented for fast and accurate Doppler profiling. Finally, test results showed that the platform could offer a minimum detectable signal of 25 μV, allowing a 51 dB dynamic range at 47 dB gain, and real-time imaging at more than 500 frames/s. Phantom and in vivo imaging experiments were conducted and the results demonstrated good system performance.

  16. An FPGA-based rapid wheezing detection system.

    PubMed

    Lin, Bor-Shing; Yen, Tian-Shiue

    2014-01-29

    Wheezing is often treated as a crucial indicator in the diagnosis of obstructive pulmonary diseases. A rapid wheezing detection system may help physicians to monitor patients over the long-term. In this study, a portable wheezing detection system based on a field-programmable gate array (FPGA) is proposed. This system accelerates wheezing detection, and can be used as either a single-process system, or as an integrated part of another biomedical signal detection system. The system segments sound signals into 2-second units. A short-time Fourier transform was used to determine the relationship between the time and frequency components of wheezing sound data. A spectrogram was processed using 2D bilateral filtering, edge detection, multithreshold image segmentation, morphological image processing, and image labeling, to extract wheezing features according to computerized respiratory sound analysis (CORSA) standards. These features were then used to train the support vector machine (SVM) and build the classification models. The trained model was used to analyze sound data to detect wheezing. The system runs on a Xilinx Virtex-6 FPGA ML605 platform. The experimental results revealed that the system offered excellent wheezing recognition performance (0.912). The detection process can be used with a clock frequency of 51.97 MHz, and is able to perform rapid wheezing classification.

  17. An FPGA-Based Rapid Wheezing Detection System

    PubMed Central

    Lin, Bor-Shing; Yen, Tian-Shiue

    2014-01-01

    Wheezing is often treated as a crucial indicator in the diagnosis of obstructive pulmonary diseases. A rapid wheezing detection system may help physicians to monitor patients over the long-term. In this study, a portable wheezing detection system based on a field-programmable gate array (FPGA) is proposed. This system accelerates wheezing detection, and can be used as either a single-process system, or as an integrated part of another biomedical signal detection system. The system segments sound signals into 2-second units. A short-time Fourier transform was used to determine the relationship between the time and frequency components of wheezing sound data. A spectrogram was processed using 2D bilateral filtering, edge detection, multithreshold image segmentation, morphological image processing, and image labeling, to extract wheezing features according to computerized respiratory sound analysis (CORSA) standards. These features were then used to train the support vector machine (SVM) and build the classification models. The trained model was used to analyze sound data to detect wheezing. The system runs on a Xilinx Virtex-6 FPGA ML605 platform. The experimental results revealed that the system offered excellent wheezing recognition performance (0.912). The detection process can be used with a clock frequency of 51.97 MHz, and is able to perform rapid wheezing classification. PMID:24481034

  18. FPGA Implementation of Metastability-Based True Random Number Generator

    NASA Astrophysics Data System (ADS)

    Hata, Hisashi; Ichikawa, Shuichi

    True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps throughput.

  19. Grey relational clustering associated with CAPRI applied to FPGA placement

    NASA Astrophysics Data System (ADS)

    Wu, Jan-Ou; Fan, Yang-Hsin; Wang, San-Fu

    2016-04-01

    Grey relational clustering is used to minimise wire length during field programmable gate arrays (FPGA) placement and routing. The proposed Grey Relational Clustering Apply to Placement (GRAP) algorithm combines grey relational clustering and convex assigned placement for regular ICs method to construct a placement netlist, which was successfully used to solve the problem of minimising wire length in an FPGA placement. Upon calculating the grey relational grade, GRAP can rank the sequence and analyse the minimal distance in configuration logic blocks based on the grey relational sequence and combined connection-based approaches. The experimental results demonstrate that the GRAP effectively compares the Hibert, Z and Snake with bounding box (BB) cost function in the space-filling curve. The GRAP improved BB cost by 0.753%, 0.324% and 0.096% for the Hilbert, Z and Snake, respectively. This study also compares the critical path with the space-filling curve. The GRAP approach improved the critical path for Snake by 1.3% in the space-filling curve; however, the GRAP increased critical path wire by 1.38% and 0.03% over that of the Hilbert and Z of space-filling curve, respectively.

  20. Energy Efficient Biomolecular Simulations with FPGA-based Reconfigurable Computing

    SciTech Connect

    Hampton, Scott S; Agarwal, Pratul K

    2010-05-01

    Reconfigurable computing (RC) is being investigated as a hardware solution for improving time-to-solution for biomolecular simulations. A number of popular molecular dynamics (MD) codes are used to study various aspects of biomolecules. These codes are now capable of simulating nanosecond time-scale trajectories per day on conventional microprocessor-based hardware, but biomolecular processes often occur at the microsecond time-scale or longer. A wide gap exists between the desired and achievable simulation capability; therefore, there is considerable interest in alternative algorithms and hardware for improving the time-to-solution of MD codes. The fine-grain parallelism provided by Field Programmable Gate Arrays (FPGA) combined with their low power consumption make them an attractive solution for improving the performance of MD simulations. In this work, we use an FPGA-based coprocessor to accelerate the compute-intensive calculations of LAMMPS, a popular MD code, achieving up to 5.5 fold speed-up on the non-bonded force computations of the particle mesh Ewald method and up to 2.2 fold speed-up in overall time-to-solution, and potentially an increase by a factor of 9 in power-performance efficiencies for the pair-wise computations. The results presented here provide an example of the multi-faceted benefits to an application in a heterogeneous computing environment.

  1. Anti Theft Mechanism Through Face recognition Using FPGA

    NASA Astrophysics Data System (ADS)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  2. Research on defogging technology of video image based on FPGA

    NASA Astrophysics Data System (ADS)

    Liu, Shuo; Piao, Yan

    2015-03-01

    As the effect of atmospheric particles scattering, the video image captured by outdoor surveillance system has low contrast and brightness, which directly affects the application value of the system. The traditional defogging technology is mostly studied by software for the defogging algorithms of the single frame image. Moreover, the algorithms have large computation and high time complexity. Then, the defogging technology of video image based on Digital Signal Processing (DSP) has the problem of complex peripheral circuit. It can't be realized in real-time processing, and it's hard to debug and upgrade. In this paper, with the improved dark channel prior algorithm, we propose a kind of defogging technology of video image based on Field Programmable Gate Array (FPGA). Compared to the traditional defogging methods, the video image with high resolution can be processed in real-time. Furthermore, the function modules of the system have been designed by hardware description language. At last, the results show that the defogging system based on FPGA can process the video image with minimum resolution of 640×480 in real-time. After defogging, the brightness and contrast of video image are improved effectively. Therefore, the defogging technology proposed in the paper has a great variety of applications including aviation, forest fire prevention, national security and other important surveillance.

  3. Development of FPGA-based safety-related I and C systems

    SciTech Connect

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S.

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  4. GPUs for real-time processing in HEP trigger systems

    NASA Astrophysics Data System (ADS)

    Lamanna, G.; Ammendola, R.; Bauce, M.; Biagioni, A.; Fantechi, R.; Fiorini, M.; Giagu, S.; Graverini, E.; Lamanna, G.; Lonardo, A.; Messina, A.; Pantaleo, F.; Paolucci, P. S.; Piandani, R.; Rescigno, M.; Simula, F.; Sozzi, M.; Vicini, P.

    2014-06-01

    We describe a pilot project for the use of Graphics Processing Units (GPUs) for online triggering applications in High Energy Physics (HEP) experiments. Two major trends can be identified in the development of trigger and DAQ systems for HEP experiments: the massive use of general-purpose commodity systems such as commercial multicore PC farms for data acquisition, and the reduction of trigger levels implemented in hardware, towards a pure software selection system (trigger-less). The very innovative approach presented here aims at exploiting the parallel computing power of commercial GPUs to perform fast computations in software both at low- and high-level trigger stages. General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to the specific strengths of such devices as accelerator in offline computation. With the steady reduction of GPU latencies, and the increase in link and memory throughputs, the use of such devices for real-time applications in high-energy physics data acquisition and trigger systems is becoming very attractive. We discuss in details the use of online parallel computing on GPUs for synchronous low-level trigger with fixed latency. In particular we show preliminary results on a first test in the NA62 experiment at CERN. The use of GPUs in high-level triggers is also considered, the ATLAS experiment (and in particular the muon trigger) at CERN will be taken as a study case of possible applications.

  5. Subnanosecond trigger system for ETA

    SciTech Connect

    Cook, E.G.; Lauer, E.J.; Reginato, L.L.; Rogers D.; Schmidt, J.A.

    1980-05-30

    A high-voltage trigger system capable of triggering 30, 250 kV spark gaps; each with less than +- 1 ns jitter has been constructed. In addition to low jitter rates, the trigger system must be capable of delivering the high voltage pulses to the spark gaps either simultaneously or sequentially as determined by other system requirements. The trigger system consists of several stages of pulse amplification culminating in 160 kV pulses having 30 ns risetime. The trigger system is described and test data provided.

  6. A VXIbus based trigger for the CLAS detector at CEBAF

    SciTech Connect

    Doughty, D.C. Jr.; Englert, J.; Hale, R.; Lemon, S. ); Leung, P. ); Cuevas, C.; Joyce, D. )

    1992-04-01

    This paper discusses a VXIbus based first level triggering system for the CLAS detector at CEBAF which has been designed and prototyped. It uses pipelining and a triple memory lookup to produce a dead-timeless trigger decision with an average latency of 110 ns and a jitter of 20 ns. The VXIbus Extended Start/Stop triggering protocols allow sub-nanosecond time synchronization.

  7. A VXIbus based trigger for the CLAS detector at CEBAF

    SciTech Connect

    D.C. Doughty, Jr.; J. Englert; R. Hale; S. Lemon; P. Leung; C. Cuevas; D. Joyce

    1992-04-01

    A VXIbus based first level triggering system for the CLAS detector at CEBAF has been designed and prototyped. It uses pipelining and a triple memory lookup to produce a dead-timeless trigger decision with an average latency of 110 nS and a jitter of 20 nS. The VXIbus Extended Start/Stop triggering protocols allow sub-nanosecond time synchronization.

  8. FPGA-based floating-point datapath design for geometry processing

    NASA Astrophysics Data System (ADS)

    Xing, Shanzhen; Yu, William W.

    1998-10-01

    Geometry processing comprises of a great many computationally intensive floating-point operations. Real- time graphics systems generally use application-specific custom designed parallel hardware to provide the high performance computation power. When designing a graphics engine on a FPGA-based configurable computing system, cost- effectiveness is important. This paper investigates and proposes a cost-effective FPGA-based floating-point datapath for geometry process. It is designed to be a basic building block for FPGA-based geometry processors. The implemented datapath operates at a frequency of 6.25 Mhz and has an average floating-point operation time of 10.2 microseconds.

  9. The FPGA realization of a real-time Bayer image restoration algorithm with better performance

    NASA Astrophysics Data System (ADS)

    Ma, Huaping; Liu, Shuang; Zhou, Jiangyong; Tang, Zunlie; Deng, Qilin; Zhang, Hongliu

    2014-11-01

    Along with the wide usage of realizing Bayer color interpolation algorithm through FPGA, better performance, real-time processing, and less resource consumption have become the pursuits for the users. In order to realize the function of high speed and high quality processing of the Bayer image restoration with less resource consumption, the color reconstruction is designed and optimized from the interpolation algorithm and the FPGA realization in this article. Then the hardware realization is finished with FPGA development platform, and the function of real-time and high-fidelity image processing with less resource consumption is realized in the embedded image acquisition systems.

  10. Implementation of large kernel 2-D convolution in limited FPGA resource

    NASA Astrophysics Data System (ADS)

    Zhong, Sheng; Li, Yang; Yan, Luxin; Zhang, Tianxu; Cao, Zhiguo

    2007-12-01

    2-D Convolution is a simple mathematical operation which is fundamental to many common image processing operators. Using FPGA to implement the convolver can greatly reduce the DSP's heavy burden in signal processing. But with the limit resource the FPGA can implement a convolver with small 2-D kernel. In this paper, An FIFO type line delayer is presented to serve as the data buffer for convolution to reduce the data fetching operation. A finite state machine is applied to control the reuse of multipliers and adders arrays. With these two techniques, a resource limited FPGA can be used to implement a larger kernel convolver which is commonly used in image process systems.

  11. FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

    DTIC Science & Technology

    2014-06-01

    Document Number: SET 2014-0043 412TW-PA-14298 FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG June 2014 Final Report Test...To) 9/11 -- 8/14 4. TITLE AND SUBTITLE FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG 5a. CONTRACT NUMBER: W900KK-11-C-0032 5b...CA: Air Force Flight Test Center Edwards AFB CA CC: 012100 14. ABSTRACT In this paper, we present an FPGA implementation for

  12. MicroBlaze implementation of GPS/INS integrated system on Virtex-6 FPGA.

    PubMed

    Bhogadi, Lokeswara Rao; Gottapu, Sasi Bhushana Rao; Konala, Vvs Reddy

    2015-01-01

    The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described in this paper. The inertial navigation solution and Kalman filter computations are provided by the MicroBlaze on Virtex-6 FPGA. The real time processed navigation solutions are updated with a rate of 100 Hz.

  13. Leveling

    USGS Publications Warehouse

    1966-01-01

    Geodetic leveling by the U.S. Geological Survey provides a framework of accurate elevations for topographic mapping. Elevations are referred to the Sea Level Datum of 1929. Lines of leveling may be run either with automatic or with precise spirit levels, by either the center-wire or the three-wire method. For future use, the surveys are monumented with bench marks, using standard metal tablets or other marking devices. The elevations are adjusted by least squares or other suitable method and are published in lists of control.

  14. Use of GPUs in Trigger Systems

    NASA Astrophysics Data System (ADS)

    Lamanna, Gianluca

    In recent years the interest for using graphics processor (GPU) in general purpose high performance computing is constantly rising. In this paper we discuss the possible use of GPUs to construct a fast and effective real time trigger system, both in software and hardware levels. In particular, we study the integration of such a system in the NA62 trigger. The first application of GPUs for rings pattern recognition in the RICH will be presented. The results obtained show that there are not showstoppers in trigger systems with relatively low latency. Thanks to the use of off-the-shelf technology, in continous development for purposes related to video game and image processing market, the architecture described would be easily exported to other experiments, to build a versatile and fully customizable online selection.

  15. Tau Trigger at the ATLAS Experiment

    SciTech Connect

    Benslama, K.; Kalinowski, A.; Belanger-Champange, C.; Brenner, R.; Bosman, M.; Casado, P.; Osuna, C.; Perez, E.; Vorwerk, V.; Czyczula, Z.; Dam, M.; Xella, S.; Demers, S.; Farrington, S.; Igonkina, O.; Kanaya, N.; Tsuno, S.; Ptacek, E.; Reinsch, A.; Strom, David M.; Torrence, E.; /Oregon U. /Sydney U. /Lancaster U. /Birmingham U.

    2011-11-09

    Many theoretical models, like the Standard Model or SUSY at large tan({beta}), predict Higgs bosons or new particles which decay more abundantly to final states including tau leptons than to other leptons. At the energy scale of the LHC, the identification of tau leptons, in particular in the hadronic decay mode, will be a challenging task due to an overwhelming QCD background which gives rise to jets of particles that can be hard to distinguish from hadronic tau decays. Equipped with excellent tracking and calorimetry, the ATLAS experiment has developed tau identification tools capable of working at the trigger level. This contribution presents tau trigger algorithms which exploit the main features of hadronic tau decays and describes the current tau trigger commissioning activities. Many of the SM processes being investigated at ATLAS, as well as numerous BSM searches, contain tau leptons in their final states. Being able to trigger effectively on the tau leptons in these events will contribute to the success of the ATLAS experiment. The tau trigger algorithms and monitoring infrastructure are ready for the first data, and are being tested with the data collected with cosmic muons. The development of efficiency measurements methods using QCD and Z {yields} {tau}{tau} events is well advanced.

  16. Extending the BEAGLE library to a multi-FPGA platform

    PubMed Central

    2013-01-01

    Background Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein’s pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein’s pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. Results The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform’s peak memory bandwidth and the implementation’s memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE’s CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE’s GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. Conclusions The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design

  17. Version control friendly project management system for FPGA designs

    NASA Astrophysics Data System (ADS)

    Zabołotny, Wojciech M.

    2016-09-01

    In complex FPGA designs, usage of version control system is a necessity. It is especially important in the case of designs developed by many developers or even by many teams. The standard development mode, however, offered by most FPGA vendors is the GUI based project mode. It is very convenient for a single developer, who can easily experiment with project settings, browse and modify the sources hierarchy, compile and test the design. Unfortunately, the project configuration is stored in files which are not suited for use with Version Control System (VCS). Another important problem in big FPGA designs is reuse of IP cores. Even though there are standard solutions like IEEE 1685-2014, they suffer from some limitations particularly significant for complex systems (e.g. only simple types are allowed for IP-core ports, it is not possible to use parametrized instances of IP-cores). Additionally, the overhead associated with packaging of IP-cores is significant and not justified for simple reusable blocks. This paper presents a system aimed at storing the whole design in a VCS oriented form. The hierarchy of sources is described with textual "extended project (EPRJ) files" which are fully controlled by the user and may also be put in a VCS. The IP blocks may be easily added to the project just by including the accompanying EPRJ file. Both absolute and relative file paths may be used which allows the flexible structure of directories. The sources of locally developed IP blocks may be stored in directories located inside the main source tree, while sources of independently developed blocks, using separate VCS repositories, may be located outside that tree. The environment allows splitting the design into smaller parts, which are synthesized independently. That reduces the time needed to recompile the whole design if only a few blocks are modified. The system creates the standard project, which can be used for convenient interactive work with the design. After the

  18. Gravity triggered neutrino condensates

    SciTech Connect

    Barenboim, Gabriela

    2010-11-01

    In this work we use the Schwinger-Dyson equations to study the possibility that an enhanced gravitational attraction triggers the formation of a right-handed neutrino condensate, inducing dynamical symmetry breaking and generating a Majorana mass for the right-handed neutrino at a scale appropriate for the seesaw mechanism. The composite field formed by the condensate phase could drive an early epoch of inflation. We find that to the lowest order, the theory does not allow dynamical symmetry breaking. Nevertheless, thanks to the large number of matter fields in the model, the suppression by additional powers in G of higher order terms can be compensated, boosting them up to their lowest order counterparts. This way chiral symmetry can be broken dynamically and the infrared mass generated turns out to be in the expected range for a successful seesaw scenario.

  19. Study of the trigger efficiency for SeaQuest Drell-Yan Dimuons

    NASA Astrophysics Data System (ADS)

    Xi, Zhaojia; E906/SeaQuest Collaboration

    2017-01-01

    The SeaQuest (E906) experiment, using the 120 GeV proton beam from the Main Injector at the Fermi National Accelerator Laboratory (FNAL), is studying the quark and antiquark structure of the nucleon using the Drell-Yan process. SeaQuest uses a two magnet focusing spectrometer with four detector stations that include fast plastic scintillator hodoscope planes. The hodoscope arrays along with Field Programmable Gate Arrays(FPGAs) are used to make the SeaQuest trigger system. It is designed to measure events with dimuon pairs from the Drell-Yan process. The signals from each hodoscope, which have adequate timing resolution to determine which 18.9 ns beam pulse the event occurred, are sent to the FPGA trigger modules. In order to get a correct hit pattern, each channel is aligned to the beam RF clock. The trigger is formed when the hits fulfill a dimuon pattern. A program has been developed to analyze and calculate trigger efficiency by using data from hodoscopes. It is important to study trigger efficiency to be used in physics results, such as the cross section of the Drell-Yan process. The method, programming, measurements, and results of this study will be presented. This research was supported by US DOE MENP Grant DE-FG02-03ER41243.

  20. ATLAS trigger operations: Monitoring with ``Xmon'' rate prediction system

    NASA Astrophysics Data System (ADS)

    Aukerman, Andrew; Hong, Tae Min

    2017-01-01

    We present the operations and online monitoring with the ``Xmon'' rate prediction system for the trigger system at the ATLAS Experiment. A two-level trigger system reduces the LHC's bunch-crossing rate, 40 MHz at design capacity, to an average recording rate of about 1 kHz, while maintaining a high efficiency of selecting events of interest. The Xmon system uses the luminosity value to predict trigger rates that are, in turn, compared with incoming rates. The predictions rely on past runs to parameterize the luminosity dependency of the event rate for a trigger algorithm. Some examples are given to illustrate the performance of the tool during recent operations.

  1. FPGA-based gating and logic for multichannel single photon counting

    SciTech Connect

    Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G; Williams, Brian P; Schaake, Jason; Humble, Travis S

    2012-01-01

    We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)

  2. Evaluating system for SRAM-based FPGA single event upset rate

    NASA Astrophysics Data System (ADS)

    Wang, Yunlong; Bao, Bin

    2016-09-01

    This paper takes static random-access-memory (SRAM)-based field-programmable-gate-array (FPGA) as the research object. Attention is focused on the configuration memory of this kind of FPGA, and the research has been devoted to the contents of the configuration memory and the configuration circuit to manage its contents. The single event upset (SEU) happening in the configuration memory doesn't lead to a functional failure necessarily. The dynamic SEU is SEU which happens in the configuration memory and causes necessarily function failure. This paper introduces a test method of dynamic SUE rate for the SRAM-based FPGA by designing a FPGA with self-test function.

  3. FPGA platform for prototyping and evaluation of neural network automotive applications

    NASA Technical Reports Server (NTRS)

    Aranki, N.; Tawel, R.

    2002-01-01

    In this paper we present an FPGA based reconfigurable computing platform for prototyping and evaluation of advanced neural network based applications for control and diagnostics in an automotive sub-systems.

  4. [The testing and verification for interconnect faults based on cluster FPGA configuration].

    PubMed

    Duan, Cheng-Hu; Jia, Jian-Ge

    2005-05-01

    We have developed a hierarchical approach to define a set of FPGA configurations to solve the interconnect testing problem. This technique enables the detection, testing and verification of bridging faults involving intracluster interconnect and extracluster interconnect to be done easily.

  5. A compact multi-standard and non-standard reconfigurable FPGA-based method for embedded real-time video image compilation or conversion

    NASA Astrophysics Data System (ADS)

    Thomas, J.; Megherbi, D.; Sliney, P.

    2005-08-01

    For LADAR systems with an arbitrary or undetermined scanner system, the raw video data produced is not usually in a form that can be used by standard video display devices such as a television monitor or frame grabber. This raw data must first be processed and organized into a standard video format or into a custom digital format for further processing. If this system is designed as an FPGA-based system, it can be combined with an FPGA-based scanner controller for an even more compact unit. This FPGA-based system can be extremely complex or simple depending on the desired input/output format. Even better, the system can be made reconfigurable to allow many input and output data formats. Such a system has already been designed and is being tested. Many programmable constants are provided to allow modification of the raw data from the photo-detector at a 4.195KHz horizontal line scan rate and produce a composite RS-170 compliant video signal with a 15.75KHz horizontal line scan rate. The program can adapt to any set of input and output frequencies, sync pulse width, white and black level.

  6. The Time-of-Flight trigger at CDF

    SciTech Connect

    Bauer, G.; Mulhearn, M.J.; Paus, Ch.; Schieferdecker, P.; Tether, S.; Lewis, J.D.; Shaw, T.; Acosta, D.; Konigsberg, J.; Madorsky, A.; /Florida U.

    2006-05-01

    The Time-of-Flight (TOF) detector measures the arrival time and deposited energy of charged particles reaching scintillator bars surrounding the central tracking region of the CDF detector. Requiring high ionization in the TOF system provides a unique trigger capability, which has been used for a magnetic monopole search. Other uses, with smaller pulse height thresholds, include a high-multiplicity charged-particle trigger useful for QCD studies and a much improved cosmic ray trigger for calibrating other detector components. Although not designed as input to CDF's global Level 1 trigger, the TOF system has been easily adapted to this role by the addition of 24 cables, new firmware, and four custom TOF trigger boards (TOTRIBs). This article describes the TOF trigger.

  7. FPGA implementation of glass-free stereo vision

    NASA Astrophysics Data System (ADS)

    Tang, Weidong; Yan, Xiaolin

    2016-04-01

    This paper presents a real-time efficient glass-free 3D system, which is based on FPGA. The system converts two-view input that is 60 frames per second (fps) 1080P stream into a multi-view video with 30fps and 4K resolution. In order to provide smooth and comfortable viewing experience, glass-free 3D systems must display multi-view videos. To generate a multi-view video from a two-view input includes three steps, the first is to compute disparity maps from two input views; the second is to synthesize a couple of new views based on the computed disparity maps and input views; the last is to produce video from the new views according to the specifications of the lens installed on TV sets.

  8. Implementation of a pulse coupled neural network in FPGA.

    PubMed

    Waldemark, J; Millberg, M; Lindblad, T; Waldemark, K; Becanovic, V

    2000-06-01

    The Pulse Coupled neural network, PCNN, is a biologically inspired neural net and it can be used in various image analysis applications, e.g. time-critical applications in the field of image pre-processing like segmentation, filtering, etc. a VHDL implementation of the PCNN targeting FPGA was undertaken and the results presented here. The implementation contains many interesting features. By pipelining the PCNN structure a very high throughput of 55 million neuron iterations per second could be achieved. By making the coefficients re-configurable during operation, a complete recognition system could be implemented on one, or maybe two, chip(s). Reconsidering the ranges and resolutions of the constants may save a lot of hardware, since the higher resolution requires larger multipliers, adders, memories etc.

  9. A Digitalized Silicon Microgyroscope Based on Embedded FPGA

    PubMed Central

    Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

    2012-01-01

    This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

  10. Design and tuning of FPGA implementations of neural networks

    NASA Astrophysics Data System (ADS)

    Clare, Peter J. C.; Gulley, J. W.; Hickman, Duncan; Smith, Moira I.

    1997-06-01

    Artificial neural network (ANN) algorithms are applicable in a variety of roles for image processing in infrared search and track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of multi-layer perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.

  11. An FPGA-based rapid prototyping platform for wavelet coprocessors

    NASA Astrophysics Data System (ADS)

    Vera, Alonzo; Meyer-Baese, Uwe; Pattichis, Marios

    2007-04-01

    MatLab/Simulink-based design flows are being used by DSP designers to improve time-to-market of FPGA implementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors. Existing CAD tools do not fully address the integration of a DSP coprocessor into an embedded system design. This integration might prove to be time consuming and error prone. It also requires that the DSP designer has an excellent knowledge of embedded systems and computer architecture details. We present a prototyping platform and design flow that allows rapid integration of embedded systems with a wavelet coprocessor. The platform comprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessor with a PowerPC-based embedded system. The platform has a wide range of applications, from industrial to educational environments.

  12. Active cancellation of acoustical resonances with an FPGA FIR filter.

    PubMed

    Ryou, Albert; Simon, Jonathan

    2017-01-01

    We present a novel approach to enhancing the bandwidth of a feedback-controlled mechanical system by digitally canceling acoustical resonances (poles) and anti-resonances (zeros) in the open-loop response via an FPGA FIR filter. By performing a real-time convolution of the feedback error signal with an inverse filter, we can suppress arbitrarily many poles and zeros below 100 kHz, each with a linewidth down to 10 Hz. We demonstrate the efficacy of this technique by canceling the ten largest mechanical resonances and anti-resonances of a high-finesse optical resonator, thereby enhancing the unity gain frequency by more than an order of magnitude. This approach is applicable to a broad array of stabilization problems including optical resonators, external cavity diode lasers, and scanning tunneling microscopes and points the way to applying modern optimal control techniques to intricate linear acoustical systems.

  13. FPGA implementation of Generalized Hebbian Algorithm for texture classification.

    PubMed

    Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

    2012-01-01

    This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs.

  14. Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

    PubMed Central

    Biasizzo, Anton; Novak, Franc

    2013-01-01

    Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load. PMID:23673680

  15. Hardware accelerated compression of LIDAR data using FPGA devices.

    PubMed

    Biasizzo, Anton; Novak, Franc

    2013-05-14

    Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

  16. Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping

    SciTech Connect

    Ceriani, Marco; Palermo, Gianluca; Secchi, Simone; Tumeo, Antonino; Villa, Oreste

    2013-04-29

    We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.

  17. Discrete wavelet transform FPGA design using MatLab/Simulink

    NASA Astrophysics Data System (ADS)

    Meyer-Baese, Uwe; Vera, A.; Meyer-Baese, A.; Pattichis, M.; Perry, R.

    2006-04-01

    Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of the engineering shlls ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink based design flow. This not only allows the over 1 million MatLab users to design FPGAs but also to by-pass the hardware design engineer leading to a significant reduction in development time. Critical however with this design flow are: (1) quality-of-results, (2) sophistication of Simulink block library, (3) compile time, (4) cost and availability of development boards, and (5) cost, functionality, and ease-of-use of the FPGA vendor provided design tools.

  18. FPGA-Based Multiprocessor System for Injection Molding Control

    PubMed Central

    Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

    2012-01-01

    The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

  19. FPGA-based multiprocessor system for injection molding control.

    PubMed

    Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

    2012-10-18

    The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

  20. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  1. FPGA-based RF spectrum merging and adaptive hopset selection

    NASA Astrophysics Data System (ADS)

    McLean, R. K.; Flatley, B. N.; Silvius, M. D.; Hopkinson, K. M.

    The radio frequency (RF) spectrum is a limited resource. Spectrum allotment disputes stem from this scarcity as many radio devices are confined to a fixed frequency or frequency sequence. One alternative is to incorporate cognition within a reconfigurable radio platform, therefore enabling the radio to adapt to dynamic RF spectrum environments. In this way, the radio is able to actively sense the RF spectrum, decide, and act accordingly, thereby sharing the spectrum and operating in more flexible manner. In this paper, we present a novel solution for merging many distributed RF spectrum maps into one map and for subsequently creating an adaptive hopset. We also provide an example of our system in operation, the result of which is a pseudorandom adaptive hopset. The paper then presents a novel hardware design for the frequency merger and adaptive hopset selector, both of which are written in VHDL and implemented as a custom IP core on an FPGA-based embedded system using the Xilinx Embedded Development Kit (EDK) software tool. The design of the custom IP core is optimized for area, and it can process a high-volume digital input via a low-latency circuit architecture. The complete embedded system includes the Xilinx PowerPC microprocessor, UART serial connection, and compact flash memory card IP cores, and our custom map merging/hopset selection IP core, all of which are targeted to the Virtex IV FPGA. This system is then incorporated into a cognitive radio prototype on a Rice University Wireless Open Access Research Platform (WARP) reconfigurable radio.

  2. FPGA-based prototype of portable environmental radiation monitor

    SciTech Connect

    Benahmed, A.; Elkarch, H.

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  3. Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

    NASA Technical Reports Server (NTRS)

    Jamot, Robert F.; Monroe, Ryan M.

    2012-01-01

    With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

  4. FPGA-accelerated adaptive optics wavefront control part II

    NASA Astrophysics Data System (ADS)

    Mauch, S.; Barth, A.; Reger, J.; Reinlein, C.; Appelfelder, M.; Beckert, E.

    2015-03-01

    We present progressive work that is based on our recently developed rapid control prototyping system (RCP), designed for the implementation of high-performance adaptive optical control algorithms using a continuous de-formable mirror (DM). The RCP system, presented in 2014, is resorting to a Xilinx Kintex-7 Field Programmable Gate Array (FPGA), placed on a self-developed PCIe card, and installed on a high-performance computer that runs a hard real-time Linux operating system. For this purpose, algorithms for the efficient evaluation of data from a Shack-Hartmann wavefront sensor (SHWFS) on an FPGA have been developed. The corresponding analog input and output cards are designed for exploiting the maximum possible performance while not being constrained to a specific DM and control algorithm due to the RCP approach. In this second part of our contribution, we focus on recent results that we achieved with this novel experimental setup. By presenting results which are far superior to the former ones, we further justify the deployment of the RCP system and its required time and resources. We conducted various experiments for revealing the effective performance, i.e. the maximum manageable complexity in the controller design that may be achieved in real-time without performance losses. A detailed analysis of the hidden latencies is carried out, showing that these latencies have been drastically reduced. In addition, a series of concepts relating the evaluation of the wavefront as well as designing and synthesizing a wavefront are thoroughly investigated with the goal to overcome some of the prevalent limitations. Furthermore, principal results regarding the closed-loop performance of the low-speed dynamics of the integrated heater in a DM concept are illustrated in detail; to be combined with the piezo-electric high-speed actuators in the next step

  5. A Design of Low Frequency Time-Code Receiver Based on DSP and FPGA

    NASA Astrophysics Data System (ADS)

    Li, Guo-Dong; Xu, Lin-Sheng

    2006-06-01

    The hardware of a low frequency time-code receiver which was designed with FPGA (field programmable gate array) and DSP (digital signal processor) is introduced. The method of realizing the time synchronization for the receiver system is described. The software developed for DSP and FPGA is expounded, and the results of test and simulation are presented. The design is charcterized by high accuracy, good reliability, fair extensibility, etc.

  6. Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

    DTIC Science & Technology

    2013-12-01

    Comparison of FPGA switch technologies (from [25]) b. Flash Based FPGAs Flash-based FPGAs use a switch matrix formed of floating gate ...output may randomly oscillate between the two values. The behavior also may not be consistent, and a floating signal may cause the gate to produce an...input causes a floating output in the associated gate , which appears as a floating input to the next gate . Unlike a physical circuit in the FPGA

  7. Performance analysis and acceleration of cross-correlation computation using FPGA implementation for digital signal processing

    NASA Astrophysics Data System (ADS)

    Selma, R.

    2016-09-01

    Paper describes comparison of cross-correlation computation speed of most commonly used computation platforms (CPU, GPU) with an FPGA-based design. It also describes the structure of cross-correlation unit implemented for testing purposes. Speedup of computations was achieved using FPGA-based design, varying between 16 and 5400 times compared to CPU computations and between 3 and 175 times compared to GPU computations.

  8. Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale.

    PubMed

    Huang, Muhuan; Wu, Di; Yu, Cody Hao; Fang, Zhenman; Interlandi, Matteo; Condie, Tyson; Cong, Jason

    2016-10-01

    With the end of CPU core scaling due to dark silicon limitations, customized accelerators on FPGAs have gained increased attention in modern datacenters due to their lower power, high performance and energy efficiency. Evidenced by Microsoft's FPGA deployment in its Bing search engine and Intel's 16.7 billion acquisition of Altera, integrating FPGAs into datacenters is considered one of the most promising approaches to sustain future datacenter growth. However, it is quite challenging for existing big data computing systems-like Apache Spark and Hadoop-to access the performance and energy benefits of FPGA accelerators. In this paper we design and implement Blaze to provide programming and runtime support for enabling easy and efficient deployments of FPGA accelerators in datacenters. In particular, Blaze abstracts FPGA accelerators as a service (FaaS) and provides a set of clean programming APIs for big data processing applications to easily utilize those accelerators. Our Blaze runtime implements an FaaS framework to efficiently share FPGA accelerators among multiple heterogeneous threads on a single node, and extends Hadoop YARN with accelerator-centric scheduling to efficiently share them among multiple computing tasks in the cluster. Experimental results using four representative big data applications demonstrate that Blaze greatly reduces the programming efforts to access FPGA accelerators in systems like Apache Spark and YARN, and improves the system throughput by 1.7 × to 3× (and energy efficiency by 1.5× to 2.7×) compared to a conventional CPU-only cluster.

  9. FPGA-core defibrillator using wavelet-fuzzy ECG arrhythmia classification.

    PubMed

    Nambakhsh, Mohammad; Tavakoli, Vahid; Sahba, Nima

    2008-01-01

    An electrocardiogram (ECG) feature extraction and classification system has been developed and evaluated using Quartus II 7.1 belong to Altera Ltd. In wavelet domain QRS complexes were detected and each complex was used to locate the peaks of the individual waves. Then, fuzzy classifier block used these features to classify ECG beats. Three types of arrhythmias and abnormalities were detected using the procedure. The completed algorithm was embedded into Field Programmable Gate Array (FPGA). The completed prototype was tested through software-generated signals, in which test scenarios covering several kinds of ECG signals on MIT-BIH Database. For the purpose of feeding signals into the FPGA, a software was designed to read signal files and import them to the LPT port of computer that was connected to FPGA. From the results, it was achieved that the proposed prototype could do real time monitoring of ECG signal for arrhythmia detection. We also implemented algorithm in a sequential structure device like AVR microcontroller with 16 MHZ clock for the same purpose. External clock of FPGA is 50 MHZ and by utilizing of Phase Lock Loop (PLL) component inside device, it was possible to increase the clock up to 1.2 GHZ in internal blocks. Final results compare speed and cost of resource usage in both devices. It shows that in cost of more resource usage, FPGA provides higher speed of computation; because FPGA makes the algorithm able to compute most parts in parallel manner.

  10. Photoconductive semiconductor switches: Laser Q-switch trigger and switch-trigger laser integration

    SciTech Connect

    Loubriel, G.M.; Mar, A.; Hamil, R.A.; Zutavern, F.J.; Helgeson, W.D.

    1997-12-01

    This report provides a summary of the Pulser In a Chip 9000-Discretionary LDRD. The program began in January of 1997 and concluded in September of 1997. The over-arching goal of this LDRD is to study whether laser diode triggered photoconductive semiconductor switches (PCSS) can be used to activate electro-optic devices such as Q-switches and Pockels cells and to study possible laser diode/switch integration. The PCSS switches we used were high gain GaAs switches because they can be triggered with small amounts of laser light. The specific goals of the LDRD were to demonstrate: (1) that small laser diode arrays that are potential candidates for laser-switch integration will indeed trigger the PCSS switch, and (2) that high gain GaAs switches can be used to trigger optical Q-switches in lasers such as the lasers to be used in the X-1 Advanced Radiation Source and the laser used for direct optical initiation (DOI) of explosives. The technology developed with this LDRD is now the prime candidate for triggering the Q switch in the multiple lasers in the laser trigger system of the X-1 Advanced Radiation Source and may be utilized in other accelerators. As part of the LDRD we developed a commercial supplier. To study laser/switch integration we tested triggering the high gain GaAs switches with: edge emitting laser diodes, vertical cavity surface emitting lasers (VCSELs), and transverse junction stripe (TJS) lasers. The first two types of lasers (edge emitting and VCSELs) did activate the PCSS but are harder to integrate with the PCSS for a compact package. The US lasers, while easier to integrate with the switch, did not trigger the PCSS at the US laser power levels we used. The PCSS was used to activate the Q-switch of the compact laser to be used in the X-1 Advanced Radiation Source.

  11. The TOTEM modular trigger system

    NASA Astrophysics Data System (ADS)

    Bagliesi, M. G.; Berretti, M.; Cecchi, R.; Greco, V.; Lami, S.; Latino, G.; Oliveri, E.; Pedreschi, E.; Scribano, A.; Spinella, F.; Turini, N.

    2010-05-01

    The TOTEM experiment will measure the total cross-section with the luminosity independent method and study elastic and diffractive scattering at the LHC. We are developing a modular trigger system, based on programmable logic, that will select meaningful events within 2.5 μs. The trigger algorithm is based on a tree structure in order to obtain information compression. The trigger primitive is generated directly on the readout chip, VFAT, that has a specific fast output that gives low resolution hits information. In two of the TOTEM detectors, Roman Pots and T2, a coincidence chip will perform track recognition directly on the detector readout boards, while for T1 the hits are transferred from the VFATs to the trigger hardware. Starting from more than 2000 bits delivered by the detector electronics, we extract, in a first step, six trigger patterns of 32 LVDS signals each; we build, then, on a dedicated board, a 1-bit (L1) trigger signal for the TOTEM experiment and 16 trigger bits to the CMS experiment global trigger system for future common data taking.

  12. Earthquake triggering by transient and static deformations

    USGS Publications Warehouse

    Gomberg, J.; Beeler, N.M.; Blanpied, M.L.; Bodin, P.

    1998-01-01

    at the initiation of failure, whereas static loads that are applied sufficiently late raise it. Rate-and-state friction predictions differ markedly from those based on Coulomb failure stress changes (??CFS) in which ??t equals the amplitude of the static stress change divided by the background stressing rate. The ??CFS model assumes a stress failure threshold, while the rate-and-state equations require a slip failure threshold. The complete rale-and-state equations predict larger ??t than the ??CFS model does for static stress steps at small t0, and smaller ??t than the ??CFS model for stress steps at large t0. The ??CFS model predicts nonzero ??t only for transient loads that raise the stress to failure stress levels during the transient. In contrast, the rate-and-state model predicts nonzero ??t for smaller loads, and triggered failure may occur well after the transient is finished. We consider heuristically the effects of triggering on a population of faults, as these effects might be evident in seismicity data. Triggering is manifest as an initial increase in seismicity rate that may be followed by a quiescence or by a return to the background rate. Available seismicity data are insufficient to discriminate whether triggered earthquakes are "new" or clock advanced. However, if triggering indeed results from advancing the failure time of inevitable earthquakes, then our modeling suggests that a quiescence always follows transient triggering and that the duration of increased seismicity also cannot exceed the duration of a triggering transient load. Quiescence follows static triggering only if the population of available faults is finite.

  13. Triggering requirements for SSC physics

    SciTech Connect

    Gilchriese, M.G.D.

    1989-04-01

    Some aspects of triggering requirements for high P{sub T} physics processes at the Superconducting Super Collider (SSC) are described. A very wide range of trigger types will be required to enable detection of the large number of potential physics signatures possible at the SSC. Although in many cases trigger rates are not now well understood, it is possible to conclude that the ability to trigger on transverse energy, number and energy of jets, number and energy of leptons (electrons and muons), missing energy and combinations of these will be required. An SSC trigger system must be both highly flexible and redundant to ensure reliable detection of many new physics processes at the SSC.

  14. An "anomalous" triggered lightning flash in Florida

    NASA Astrophysics Data System (ADS)

    Gamerota, W. R.; Uman, M. A.; Hill, J. D.; Pilkey, J.; Ngin, T.; Jordan, D. M.; Mata, C. T.

    2013-04-01

    An "anomalous" rocket-and-wire triggered lightning flash, a flash whose leaders do not follow the triggering wire remnants to ground, is characterized via high-speed video images at 10 and 300 kilo-frames per second, still camera images, 66-72 MHz source locations from a Lightning Mapping Array, channel-base current, and electric field and electric field derivative (dE/dt) measurements. This is the first anomalous flash of about 410 classically triggered flashes in north-central Florida. The flash began with an upward positively charged leader (UPL) initiating from the tip of the upward-moving triggering wire about 280 m above ground level. All but the bottom 17 m of wire exploded (became luminous) 37.6 ms after UPL initiation. A stepped leader initiated, likely from the top of the wire remnants, 282 m above ground level about 1.3 ms after the wire explosion and propagated downward for 2.1 ms, attaching to the top of a grounded utility pole 117 m southwest of the launching facility. The line charge density on the stepped leader is estimated to be of the order of 10-3 C m-1. Contrary to previously reported "anomalous" flashes in France and New Mexico (roughly 16% and 31%, respectively, of their triggered flashes), in our event, there was not a tens of milliseconds current-zero period preceding the stepped leader, there was no observed downward dart leader in the UPL channel prior to the stepped leader to ground, and there was a failed attempt to reestablish current in the exploded-wire channel between the UPL and ground.

  15. First results from the spectral DCT trigger implemented in the Cyclone V Front-End Board used for a detection of very inclined showers in the Pierre Auger surface detector Engineering Array

    SciTech Connect

    Szadkowski, Zbigniew

    2015-07-01

    The paper presents the first results from the trigger based on the Discrete Cosine Transform (DCT) operating in the new Front-End Boards with Cyclone V FPGA deployed in 8 test surface detectors in the Pierre Auger Engineering Array. The patterns of the ADC traces generated by very inclined showers were obtained from the Auger database and from the CORSIKA simulation package supported next by Offline reconstruction Auger platform which gives a predicted digitized signal profiles. Simulations for many variants of the initial angle of shower, initialization depth in the atmosphere, type of particle and its initial energy gave a boundary of the DCT coefficients used next for the on-line pattern recognition in the FPGA. Preliminary results have proven a right approach. We registered several showers triggered by the DCT for 120 MSps and 160 MSps. (authors)

  16. Disaster triggers disaster: Earthquake triggering by tropical cyclones

    NASA Astrophysics Data System (ADS)

    Wdowinski, S.; Tsukanov, I.

    2011-12-01

    Three recent devastating earthquakes, the 1999 M=7.6 Chi-Chi (Taiwan), 2010 M=7.0 Leogane (Haiti), 2010 M=6.4 Kaohsiung (Taiwan), and additional three moderate size earthquakes (6level and frequent typhoon landfall. The three wettest typhoons in Taiwan's past 50 years were Morakot (in 2009, with 2885 mm or rain), Flossie (1969, 2162 mm) and Herb (1996, 1987 mm)[Lin et al., 2010]. Each of this three very wet storms was followed by one or two main-shock M>6 earthquake that occurred in the central mountainous area of Taiwan within three years after the typhoon. The 2009 Morakot typhoon was followed by 2009 M=6.2 Nantou and 2010 M=6.4 Kaohsiung earthquakes; the 1969 Flossie typhoon was followed by an M=6.3 earthquake in 1972; and the 1996 Herb typhoon by the 1998 M=6.2 Rueyli and 1999 M=7.6 Chi-Chi earthquakes. The earthquake catalog of Taiwan lists only two other M>6 main-shocks that occurred in Taiwan's central mountainous belt, one of them was in 1964 only four months after the wet Typhoon Gloria poured heavy rain in the same area. We suggest that the close proximity in time and space between wet tropical cyclones and earthquakes reflects a physical link between the two hazard types in which these earthquakes were triggered by rapid erosion induced by tropical cyclone's heavy rain. Based on remote sensing observations, meshfree finite element modeling, and Coulomb failure stress analysis, we show that the

  17. The BTeV trigger architecture

    SciTech Connect

    Michael H.L.S. Wang

    2003-08-21

    BTeV is a high-statistics B-physics experiment that will achieve new levels of sensitivity in testing the Standard Model explanation of CP violation, mixing, and rare decays in the b and c quark systems by operating in the unique environment of a hadron collider. In order to achieve its goals, it will make use of a state-of-the-art Si-pixel vertex detector and a novel 3-level hierarchical trigger that will look at every single beam crossing to detect the presence of heavy quark decays. This talk will describe the trigger architecture focusing on key design aspects that allow the use of commercially available technology in a highly feasible and practical solution that meets the demanding physics requirements of the BTeV experiment.

  18. Proceedings of the workshop on triggering and data acquisition for experiments at the Supercollider

    SciTech Connect

    Donaldson, R.

    1989-04-01

    This meeting covered the following subjects: triggering requirements for SSC physics; CDF level 3 trigger; D0 trigger design; AMY trigger systems; Zeus calorimeter first level trigger; data acquisition for the Zeus Central Tracking Detector; trigger and data acquisition aspects for SSC tracking; data acquisition systems for the SSC; validating triggers in CDF level 3; optical data transmission at SSC; time measurement system at SSC; SSC/BCD data acquisition system; microprocessors and other processors for triggering and filtering at the SSC; data acquisition, event building, and on-line processing; LAA real-time benchmarks; object-oriented system building at SSC; and software and project management. Selected papers are indexed separately for inclusion in the Energy Science and Technology Database.

  19. Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

    NASA Astrophysics Data System (ADS)

    Badoni, D.; Bizzarri, M.; Bonaiuto, V.; Checcucci, B.; De Simone, N.; Federici, L.; Fucci, A.; Paoluzzi, G.; Papi, A.; Piccini, M.; Salamon, A.; Salina, G.; Santovetti, E.; Sargeni, F.; Venditti, S.

    2014-01-01

    The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K+→π+ ν bar nu with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K+→π+ π0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests.

  20. Ionization and Triggered Star Formation

    NASA Astrophysics Data System (ADS)

    Gritschneder, M.; Lin, D. N. C.; Murray, S. D.; Burkert, A.

    2011-12-01

    We perform a set of high resolution simulations on the impact of the UV-radiation of massive stars on the turbulent interstellar medium with the tree-SPH code iVINE. This parameter study includes different levels and driving scales of the turbulence, different ionizing flux as well as different temperatures and densities of the cold gas. We find a clear correlation between the initial state of the turbulent cloud and the final morphology and physical properties of the structures adjacent to the HII region. From the simulations we are able to derive a criterion for the formation of pillar-like structures and thus the formation of cores and stars. Gravitational collapse occurs regularly on the tips of the structures. We also derive column densities and velocity profiles of our simulations and find these to be in very good agreement with the observations of trunks and cores. In addition, we investigate the further evolution of the pillars once the massive star explodes. This leads to a supernova triggered scenario for the formation of our Solar System.

  1. Triggered Release from Polymer Capsules

    SciTech Connect

    Esser-Kahn, Aaron P.; Odom, Susan A.; Sottos, Nancy R.; White, Scott R.; Moore, Jeffrey S.

    2011-07-06

    Stimuli-responsive capsules are of interest in drug delivery, fragrance release, food preservation, and self-healing materials. Many methods are used to trigger the release of encapsulated contents. Here we highlight mechanisms for the controlled release of encapsulated cargo that utilize chemical reactions occurring in solid polymeric shell walls. Triggering mechanisms responsible for covalent bond cleavage that result in the release of capsule contents include chemical, biological, light, thermal, magnetic, and electrical stimuli. We present methods for encapsulation and release, triggering methods, and mechanisms and conclude with our opinions on interesting obstacles for chemically induced activation with relevance for controlled release.

  2. Seismology: dynamic triggering of earthquakes.

    PubMed

    Gomberg, Joan; Johnson, Paul

    2005-10-06

    After an earthquake, numerous smaller shocks are triggered over distances comparable to the dimensions of the mainshock fault rupture, although they are rare at larger distances. Here we analyse the scaling of dynamic deformations (the stresses and strains associated with seismic waves) with distance from, and magnitude of, their triggering earthquake, and show that they can cause further earthquakes at any distance if their amplitude exceeds several microstrain, regardless of their frequency content. These triggering requirements are remarkably similar to those measured in the laboratory for inducing dynamic elastic nonlinear behaviour, which suggests that the underlying physics is similar.

  3. FPGA Based Real-time Network Traffic Analysis using Traffic Dispersion Patterns

    SciTech Connect

    Khan, F; Gokhale, M; Chuah, C N

    2010-03-26

    The problem of Network Traffic Classification (NTC) has attracted significant amount of interest in the research community, offering a wide range of solutions at various levels. The core challenge is in addressing high amounts of traffic diversity found in today's networks. The problem becomes more challenging if a quick detection is required as in the case of identifying malicious network behavior or new applications like peer-to-peer traffic that have potential to quickly throttle the network bandwidth or cause significant damage. Recently, Traffic Dispersion Graphs (TDGs) have been introduced as a viable candidate for NTC. The TDGs work by forming a network wide communication graphs that embed characteristic patterns of underlying network applications. However, these patterns need to be quickly evaluated for mounting real-time response against them. This paper addresses these concerns and presents a novel solution for real-time analysis of Traffic Dispersion Metrics (TDMs) in the TDGs. We evaluate the dispersion metrics of interest and present a dedicated solution on an FPGA for their analysis. We also present analytical measures and empirically evaluate operating effectiveness of our design. The mapped design on Virtex-5 device can process 7.4 million packets/second for a TDG comprising of 10k flows at very high accuracies of over 96%.

  4. Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems through On-Chip System Evolution

    NASA Astrophysics Data System (ADS)

    Anandaraj, S. P.; Kumar, R. Naveen; Ravi, S.; Sharma, S. S. V. N.

    Nowadays, majority of applications struggle to achieve good behavior of their subsystems by cooperation of systems, which is independently designed, separately located, but mutually affecting subsystems. Such coordinating systems are hard to attain the specific structural models and effective parameters. In such cases, the evolved hardware (EHW) methods with evolutionary Algorithms (EA) to achieve sophisticated level of information [2]. Numeral systems were introduced with evolvable hardware on a single chip to overcome the lack of flexibility, with the support of modifiable evolutionary algorithm stored in software on a built-in processor. This paper proposed the architecture with Xilinx Virtex-II Pro FPGA with interfaced PowerPC processor. Due to this speedy processing, time consumption in hardware and also allows other parts to be easily modifiable software. The proposed technique will provide more benefits in the future work as regards cost and compactness [1]. The system was completely analyzed on physical devices with software executing in parallel with fitness computation in digital logic circuits, and the results determine that the system uses only double the time when compared to a PC running at 10 times faster clock speed[6].

  5. An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks.

    PubMed

    Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, Luigi

    2017-01-01

    In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments.

  6. High-speed real-time OFDM transmission based on FPGA

    NASA Astrophysics Data System (ADS)

    Xiao, Xin; Li, Fan; Yu, Jianjun

    2016-02-01

    In this paper, we review our recent research progresses on real-time orthogonal frequency division multiplexing (OFDM) transmission based on FPGA. We successfully demonstrated four-channel wavelength-division multiplexing (WDM) 256.51Gb/s 16-ary quadrature amplitude modulation (16QAM)-OFDM signal transmission system for short-reach optical amplifier free inter-connection with real-time reception. Four optical carriers are modulated by four different 16QAM-OFDM signals via 10G-class direct modulation lasers (DMLs). We achieved highest capacity real-time reception optical OFDM signal transmission over 2.4-km SMF with the bit-error ratio (BER) under soft-decision forward error correction (SD-FEC) limitation of 2.4×10-2. In order to achieve higher spectrum efficiency (SE), we demonstrate 4-channel high level QAM-OFDM transmission over 20-km SMF-28 with real-time reception. 58.72-Gb/s 256QAM-OFDM and 56.4-Gb/s 128QAM-OFDM signal transmission within 25-GHz grid is achieved with the BER under 2.4×10-2 and real-time reception.

  7. An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks

    PubMed Central

    Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, Luigi

    2017-01-01

    In the last years, the idea to dynamically interface biological neurons with artificial ones has become more and more urgent. The reason is essentially due to the design of innovative neuroprostheses where biological cell assemblies of the brain can be substituted by artificial ones. For closed-loop experiments with biological neuronal networks interfaced with in silico modeled networks, several technological challenges need to be faced, from the low-level interfacing between the living tissue and the computational model to the implementation of the latter in a suitable form for real-time processing. Field programmable gate arrays (FPGAs) can improve flexibility when simple neuronal models are required, obtaining good accuracy, real-time performance, and the possibility to create a hybrid system without any custom hardware, just programming the hardware to achieve the required functionality. In this paper, this possibility is explored presenting a modular and efficient FPGA design of an in silico spiking neural network exploiting the Izhikevich model. The proposed system, prototypically implemented on a Xilinx Virtex 6 device, is able to simulate a fully connected network counting up to 1,440 neurons, in real-time, at a sampling rate of 10 kHz, which is reasonable for small to medium scale extra-cellular closed-loop experiments. PMID:28293163

  8. Tank target recognition used in infrared imaging fuze based on FPGA

    NASA Astrophysics Data System (ADS)

    Chen, Ming; Wang, Ke-yong; Song, Cheng-tian; Jiang, Yi-Ming

    2009-07-01

    Infrared imaging fuze is invulnerable to the electromagnetic interference, and it has the ability to recognize the local image of the target. At present, the infrared imaging fuze technology has become one of the key technologies which perform the target detection and the ignition of the warhead in the complex tactical environment. According to the scanning mechanism of the infrared imaging fuze, based on the analysis of features of the infrared image of tank target, this paper presents a feature extraction method based on knowledge to recognize infrared gray image. The geometric features and gray level features are extracted. The geometric features include the corner features and angular features. The corners of the image are extracted through the SUSAN corner detection principle,the angular feature is extracted by Freeman chain code. The hot-zone gray feature is extracted by the template matching and image binarization principle. In order to realize real-time recognition, this paper uses FPGA technology to achieve recognition circuit. The experiments show that the recognition method has a certain anti-interference ability.

  9. Triggering on New Physics with the CMS Detector

    SciTech Connect

    Bose, Tulika

    2016-07-29

    The BU CMS group led by PI Tulika Bose has made several significant contributions to the CMS trigger and to the analysis of the data collected by the CMS experiment. Group members have played a leading role in the optimization of trigger algorithms, the development of trigger menus, and the online operation of the CMS High-Level Trigger. The group’s data analysis projects have concentrated on a broad spectrum of topics that take full advantage of their strengths in jets and calorimetry, trigger, lepton identification as well as their considerable experience in hadron collider physics. Their publications cover several searches for new heavy gauge bosons, vector-like quarks as well as diboson resonances.

  10. Missing Transverse Momentum Trigger Performance Studies for the ATLAS Calorimeter Trigger Upgrades

    NASA Astrophysics Data System (ADS)

    Stamas, Brianna; Parrish, Elliot; Lisi, Luc; Dudley, Christopher; Majewski, Stephanie

    2016-03-01

    The ATLAS Experiment is one of two general purpose detectors at the Large Hadron Collider at CERN in Geneva, Switzerland. In anticipation of discovering new physics, the detector will undergo numerous hardware upgrades including improvements to the Liquid Argon Calorimeter trigger electronics. For the upgrade, one component of the Level-1 trigger system will be the global feature extractor, gFEX, which will house three field programmable gate arrays (FPGAs). Specifically, in order to improve the missing transverse energy (ETmiss)trigger, an adapted topological clustering algorithm is being investigated for implementation on the FPGAs for reconstruction of proton-proton interactions in the ATLAS detector. Using simulated data, this study analyzes the performance of the adapted algorithm in software.

  11. FPGA-accelerated algorithm for the regular expression matching system

    NASA Astrophysics Data System (ADS)

    Russek, P.; Wiatr, K.

    2015-01-01

    This article describes an algorithm to support a regular expressions matching system. The goal was to achieve an attractive performance system with low energy consumption. The basic idea of the algorithm comes from a concept of the Bloom filter. It starts from the extraction of static sub-strings for strings of regular expressions. The algorithm is devised to gain from its decomposition into parts which are intended to be executed by custom hardware and the central processing unit (CPU). The pipelined custom processor architecture is proposed and a software algorithm explained accordingly. The software part of the algorithm was coded in C and runs on a processor from the ARM family. The hardware architecture was described in VHDL and implemented in field programmable gate array (FPGA). The performance results and required resources of the above experiments are given. An example of target application for the presented solution is computer and network security systems. The idea was tested on nearly 100,000 body-based viruses from the ClamAV virus database. The solution is intended for the emerging technology of clusters of low-energy computing nodes.

  12. FPGA Control System for the Automated Test of Microshutters

    NASA Technical Reports Server (NTRS)

    Lyness, Eric; Rapchun, David A.; Moseley, S. Harvey

    2008-01-01

    The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light with arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

  13. FPGA-based prototype storage system with phase change memory

    NASA Astrophysics Data System (ADS)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  14. LoFASM's FPGA-based Digital Acquisition System

    NASA Astrophysics Data System (ADS)

    Dartez, Louis P.; Jenet, F.; Creighton, T. D.; Ford, A. J.; Hicks, B.; Hinojosa, J.; Kassim, N. E.; Price, R. H.; Stovall, K.; Ray, P. S.; Taylor, G. B.

    2014-01-01

    The Low Frequency All Sky Monitor (LoFASM) is a distributed array of dipole antennas that are sensitive to radio frequencies from 10 to 88 MHz. LoFASM consists of antennas and front end electronics that were originally developed for the Long Wavelength Array (LWA) by the U.S. Naval Research Lab, the University of New Mexico, Virginia Tech, and the Jet Propulsion Laboratory. LoFASM, funded by the U.S. Department of Defense, will initially consist of 4 stations, each consisting of 12 dual-polarization dipole antenna stands. The primary science goals of LoFASM will be the detection and study of low-frequency radio transients, a high priority science goal as deemed by the National Research Council's decadal survey. The data acquisition system for the LoFASM antenna array will be using Field Programmable Gate Array (FPGA) technology to implement a real time full Stokes spectrometer and data recorder. This poster presents an overview of the current design and digital architecture of a single station of the LoFASM array as well as the status of the entire project.

  15. Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

    PubMed

    Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

    2013-08-01

    Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

  16. FPGA based digital phase-coding quantum key distribution system

    NASA Astrophysics Data System (ADS)

    Lu, XiaoMing; Zhang, LiJun; Wang, YongGang; Chen, Wei; Huang, DaJun; Li, Deng; Wang, Shuang; He, DeYong; Yin, ZhenQiang; Zhou, Yu; Hui, Cong; Han, ZhengFu

    2015-12-01

    Quantum key distribution (QKD) is a technology with the potential capability to achieve information-theoretic security. Phasecoding is an important approach to develop practical QKD systems in fiber channel. In order to improve the phase-coding modulation rate, we proposed a new digital-modulation method in this paper and constructed a compact and robust prototype of QKD system using currently available components in our lab to demonstrate the effectiveness of the method. The system was deployed in laboratory environment over a 50 km fiber and continuously operated during 87 h without manual interaction. The quantum bit error rate (QBER) of the system was stable with an average value of 3.22% and the secure key generation rate is 8.91 kbps. Although the modulation rate of the photon in the demo system was only 200 MHz, which was limited by the Faraday-Michelson interferometer (FMI) structure, the proposed method and the field programmable gate array (FPGA) based electronics scheme have a great potential for high speed QKD systems with Giga-bits/second modulation rate.

  17. Cryogenic loss monitors with FPGA TDC signal processing

    SciTech Connect

    Warner, A.; Wu, J.; /Fermilab

    2011-09-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highlight the processing techniques used.

  18. An FPGA computing demo core for space charge simulation

    SciTech Connect

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  19. FPGA-specific decimal sign-magnitude addition and subtraction

    NASA Astrophysics Data System (ADS)

    Vázquez, Martín; Todorovich, Elías

    2016-07-01

    The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten's complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.

  20. OPENCORE NMR: open-source core modules for implementing an integrated FPGA-based NMR spectrometer.

    PubMed

    Takeda, Kazuyuki

    2008-06-01

    A tool kit for implementing an integrated FPGA-based NMR spectrometer [K. Takeda, A highly integrated FPGA-based nuclear magnetic resonance spectrometer, Rev. Sci. Instrum. 78 (2007) 033103], referred to as the OPENCORE NMR spectrometer, is open to public. The system is composed of an FPGA chip and several peripheral boards for USB communication, direct-digital synthesis (DDS), RF transmission, signal acquisition, etc. Inside the FPGA chip have been implemented a number of digital modules including three pulse programmers, the digital part of DDS, a digital quadrature demodulator, dual digital low-pass filters, and a PC interface. These FPGA core modules are written in VHDL, and their source codes are available on our website. This work aims at providing sufficient information with which one can, given some facility in circuit board manufacturing, reproduce the OPENCORE NMR spectrometer presented here. Also, the users are encouraged to modify the design of spectrometer according to their own specific needs. A home-built NMR spectrometer can serve complementary roles to a sophisticated commercial spectrometer, should one comes across such new ideas that require heavy modification to hardware inside the spectrometer. This work can lower the barrier of building a handmade NMR spectrometer in the laboratory, and promote novel and exciting NMR experiments.

  1. OPENCORE NMR: Open-source core modules for implementing an integrated FPGA-based NMR spectrometer

    NASA Astrophysics Data System (ADS)

    Takeda, Kazuyuki

    2008-06-01

    A tool kit for implementing an integrated FPGA-based NMR spectrometer [K. Takeda, A highly integrated FPGA-based nuclear magnetic resonance spectrometer, Rev. Sci. Instrum. 78 (2007) 033103], referred to as the OPENCORE NMR spectrometer, is open to public. The system is composed of an FPGA chip and several peripheral boards for USB communication, direct-digital synthesis (DDS), RF transmission, signal acquisition, etc. Inside the FPGA chip have been implemented a number of digital modules including three pulse programmers, the digital part of DDS, a digital quadrature demodulator, dual digital low-pass filters, and a PC interface. These FPGA core modules are written in VHDL, and their source codes are available on our website. This work aims at providing sufficient information with which one can, given some facility in circuit board manufacturing, reproduce the OPENCORE NMR spectrometer presented here. Also, the users are encouraged to modify the design of spectrometer according to their own specific needs. A home-built NMR spectrometer can serve complementary roles to a sophisticated commercial spectrometer, should one comes across such new ideas that require heavy modification to hardware inside the spectrometer. This work can lower the barrier of building a handmade NMR spectrometer in the laboratory, and promote novel and exciting NMR experiments.

  2. Real-time implementation of camera positioning algorithm based on FPGA & SOPC

    NASA Astrophysics Data System (ADS)

    Yang, Mingcao; Qiu, Yuehong

    2014-09-01

    In recent years, with the development of positioning algorithm and FPGA, to achieve the camera positioning based on real-time implementation, rapidity, accuracy of FPGA has become a possibility by way of in-depth study of embedded hardware and dual camera positioning system, this thesis set up an infrared optical positioning system based on FPGA and SOPC system, which enables real-time positioning to mark points in space. Thesis completion include: (1) uses a CMOS sensor to extract the pixel of three objects with total feet, implemented through FPGA hardware driver, visible-light LED, used here as the target point of the instrument. (2) prior to extraction of the feature point coordinates, the image needs to be filtered to avoid affecting the physical properties of the system to bring the platform, where the median filtering. (3) Coordinate signs point to FPGA hardware circuit extraction, a new iterative threshold selection method for segmentation of images. Binary image is then segmented image tags, which calculates the coordinates of the feature points of the needle through the center of gravity method. (4) direct linear transformation (DLT) and extreme constraints method is applied to three-dimensional reconstruction of the plane array CMOS system space coordinates. using SOPC system on a chip here, taking advantage of dual-core computing systems, which let match and coordinate operations separately, thus increase processing speed.

  3. Performance evaluation of trigger algorithm for the MACE telescope

    NASA Astrophysics Data System (ADS)

    Yadav, Kuldeep; Yadav, K. K.; Bhatt, N.; Chouhan, N.; Sikder, S. S.; Behere, A.; Pithawa, C. K.; Tickoo, A. K.; Rannot, R. C.; Bhattacharyya, S.; Mitra, A. K.; Koul, R.

    The MACE (Major Atmospheric Cherenkov Experiment) telescope with a light collector diameter of 21 m, is being set up at Hanle (32.80 N, 78.90 E, 4200m asl) India, to explore the gamma-ray sky in the tens of GeV energy range. The imaging camera of the telescope comprises 1088 pixels covering a total field-of-view of 4.30 × 4.00 with trigger field-of-view of 2.60 × 3.00 and an uniform pixel resolution of 0.120. In order to achieve low energy trigger threshold of less than 30 GeV, a two level trigger scheme is being designed for the telescope. The first level trigger is generated within 16 pixels of the Camera Integrated Module (CIM) based on 4 nearest neighbour (4NN) close cluster configuration within a coincidence gate window of 5 ns while the second level trigger is generated by combining the first level triggers from neighbouring CIMs. Each pixel of the telescope is expected to operate at a single pixel threshold between 8-10 photo-electrons where the single channel rate dominated by the after- pulsing is expected to be ˜500 kHz. The hardware implementation of the trigger logic is based on complex programmable logic devices (CPLD). The basic design concept, hardware implementation and performance evaluation of the trigger system in terms of threshold energy and trigger rate estimates based on Monte Carlo data for the MACE telescope will be presented in this meeting.

  4. Evaluation of triggering functions in convective parameterization schemes using observations

    NASA Astrophysics Data System (ADS)

    Ettammal, S.; Zhang, G. J.

    2013-12-01

    Realistic simulation of different modes of atmospheric variability ranging from the diurnal cycle to inter-annual variability in global climate models (GCMs) depends crucially on the convection triggering criteria. In this study, using the data from constrained variational analysis by the Atmospheric System Research program for single column models (SCM), the performance of the commonly used convective triggering functions in GCMs is evaluated, based on the equitable threat score (ETS) value, a widely used forecast verification metric. From the ETS score, four consistently better performing triggering functions were identified. They are based on dilute dCAPE, parcel buoyancy at the lifting condensation level (Bechtold scheme), undilute dCAPE and dilute CAPE triggering functions. The key variables used to define these triggering functions were examined in detail. It was found that the skill score value of the dilute dCAPE triggering function does not show much variation among different data sets. Analysis of the composite fields and probability distributions of key variables of the triggering functions, based on the correct-prediction, over-prediction, under-prediction of convection and correct prediction of no convection cases for convection onset, brings to light some critical factors responsible for the performance of the trigger functions.

  5. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    PubMed

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

  6. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications

    PubMed Central

    Sun, Li; Savory, Joshua J.; Warncke, Kurt

    2014-01-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range. PMID:25076864

  7. Analysis of an innovative user threshold programmable photoreceiver monolithically integrated in a multitechnology field programmable gate array (MT-FPGA)

    NASA Astrophysics Data System (ADS)

    Mal, Prosenjit; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-10-01

    In the past decade, Field Programmable Gate Arrays (FPGA) has significantly influenced the landscape of the electronic industry. In particular, in the areas of semiconductor manufacturing, CAD tool designs and a wide range of digital logic applications. Primarily, research efforts in the FPGA community have concentrated on improving the reconfigurability or programmability of present day architecture for digital applications. However, the digital nature of FPGA technologies limits their applicability to a wide range of applications that depend on analog circuitry, photonic and RF based technologies. As with any ASIC design, the turn-around time between design iterations may be several months which is prohibitively long for multi-technology test-bed systems where the system designer depends on a rapid prototyping/experimentation environment that allows for optimization of processing algorithms and system architecture. Therefore, we developed innovative FPGA architecture that merges conventional FPGA technology with mixed signal and other multi-technology device. In this paper we discuss the Multi-Technology-FPGA (MT-FPGA) architecture that allows the user to have flexible rapid prototyping environment and provides him or her with the benefits of a conventional FPGA in a mixed signal domain. We substantiate this concept by implementing this architecture in TSMC 0.35 μm process and discussing the results of a variable threshold optical receiver circuit suitable for photonic information processing.

  8. High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

    NASA Astrophysics Data System (ADS)

    Sau, Suman; Mandal, Swagata; Saini, Jogender; Chakrabarti, Amlan; Chattopadhyay, Subhasis

    2015-12-01

    The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected

  9. A Proposal for the Upgrade of the Muon Drift Tubes Trigger for the CMS Experiment at the HL-LHC

    NASA Astrophysics Data System (ADS)

    Pozzobon, Nicola; Zotto, Pierluigi; Montecassiano, Fabio

    2016-11-01

    A major upgrade of the readout and trigger electronics of the CMS Drift Tubes muon detector is foreseen in order to allow its efficient operation at the High Luminosity LHC. A proposal for a new L1 Trigger Primitives Generator for this detector is presented, featuring an algorithm operating on the time of charge collection measurements provided by the asynchronous readout of the new TDC system being developed. The algorithm is being designed around the implementation in state-of-the-art FPGA devices of the original development of a Compact Hough Transform (CHT) algorithm combined with a Majority Mean-Timer, to identify both the parent bunch crossing and the muon track parameters. The current state of the design is presented along with the performance requirements, focusing on the future developments.

  10. Implementation of total focusing method for phased array ultrasonic imaging on FPGA

    NASA Astrophysics Data System (ADS)

    Guo, JianQiang; Li, Xi; Gao, Xiaorong; Wang, Zeyong; Zhao, Quanke

    2015-02-01

    This paper describes a multi-FPGA imaging system dedicated for the real-time imaging using the Total Focusing Method (TFM) and Full Matrix Capture (FMC). The system was entirely described using Verilog HDL language and implemented on Altera Stratix IV GX FPGA development board. The whole algorithm process is to: establish a coordinate system of image and divide it into grids; calculate the complete acoustic distance of array element between transmitting array element and receiving array element, and transform it into index value; then index the sound pressure values from ROM and superimpose sound pressure values to get pixel value of one focus point; and calculate the pixel values of all focus points to get the final imaging. The imaging result shows that this algorithm has high SNR of defect imaging. And FPGA with parallel processing capability can provide high speed performance, so this system can provide the imaging interface, with complete function and good performance.

  11. An FPGA-based ultrasound imaging system using capacitive micromachined ultrasonic transducers.

    PubMed

    Wong, Lawrence L P; Chen, Albert I; Logan, Andrew S; Yeow, John T W

    2012-07-01

    We report the design and experimental results of a field-programmable gate array (FPGA)-based real-time ultrasound imaging system that uses a 16-element phased-array capacitive micromachined ultrasonic transducer fabricated using a fusion bonding process. The imaging system consists of the transducer, discrete analog components situated on a custom-made circuit board, the FPGA, and a monitor. The FPGA program consists of five functional blocks: a main counter, transmit and receive beamformer, receive signal pre-processing, envelope detection, and display. No dedicated digital signal processor or personal computer is required for the imaging system. An experiment is carried out to obtain the sector B-scan of a 4-wire target. The ultrasound imaging system demonstrates the possibility of an integrated system-in-a-package solution.

  12. Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.

    PubMed

    Matsubara, Takashi; Torikai, Hiroyuki

    2013-05-01

    A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

  13. FPGA implementation of hardware processing modules as coprocessors in brain-machine interfaces.

    PubMed

    Wang, Dong; Hao, Yaoyao; Zhu, Xiaoping; Zhao, Ting; Wang, Yiwen; Chen, Yaowu; Chen, Weidong; Zheng, Xiaoxiang

    2011-01-01

    Real-time computation, portability and flexibility are crucial for practical brain-machine interface (BMI) applications. In this work, we proposed Hardware Processing Modules (HPMs) as a method for accelerating BMI computation. Two HPMs have been developed. One is the field-programmable gate array (FPGA) implementation of spike sorting based on probabilistic neural network (PNN), and the other is the FPGA implementation of neural ensemble decoding based on Kalman filter (KF). These two modules were configured under the same framework and tested with real data from motor cortex recording in rats performing a lever-pressing task for water rewards. Due to the parallelism feature of FPGA, the computation time was reduced by several dozen times, while the results are almost the same as those from Matlab implementations. Such HPMs provide a high performance coprocessor for neural signal computation.

  14. A Real-Time System for Lane Detection Based on FPGA and DSP

    NASA Astrophysics Data System (ADS)

    Xiao, Jing; Li, Shutao; Sun, Bin

    2016-12-01

    This paper presents a real-time lane detection system including edge detection and improved Hough Transform based lane detection algorithm and its hardware implementation with field programmable gate array (FPGA) and digital signal processor (DSP). Firstly, gradient amplitude and direction information are combined to extract lane edge information. Then, the information is used to determine the region of interest. Finally, the lanes are extracted by using improved Hough Transform. The image processing module of the system consists of FPGA and DSP. Particularly, the algorithms implemented in FPGA are working in pipeline and processing in parallel so that the system can run in real-time. In addition, DSP realizes lane line extraction and display function with an improved Hough Transform. The experimental results show that the proposed system is able to detect lanes under different road situations efficiently and effectively.

  15. An optimized ultrasound digital beamformer with dynamic focusing implemented on FPGA.

    PubMed

    Almekkawy, Mohamed; Xu, Jingwei; Chirala, Mohan

    2014-01-01

    We present a resource-optimized dynamic digital beamformer for an ultrasound system based on a field-programmable gate array (FPGA). A comprehensive 64-channel receive beamformer with full dynamic focusing is embedded in the Altera Arria V FPGA chip. To improve spatial and contrast resolution, full dynamic beamforming is implemented by a novel method with resource optimization. This was conceived using the implementation of the delay summation through a bulk (coarse) delay and fractional (fine) delay. The sampling frequency is 40 MHz and the beamformer includes a 240 MHz polyphase filter that enhances the temporal resolution of the system while relaxing the Analog-to-Digital converter (ADC) bandwidth requirement. The results indicate that our 64-channel dynamic beamformer architecture is amenable for a low power FPGA-based implementation in a portable ultrasound system.

  16. Radiometric Calibration of Mars HiRISE High Resolution Imagery Based on Fpga

    NASA Astrophysics Data System (ADS)

    Hou, Yifan; Geng, Xun; Xing, Shuai; Tang, Yonghe; Xu, Qing

    2016-06-01

    Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA) is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  17. Improved Approach for Utilization of FPGA Technology into DAQ, DSP, and Computing Applications

    SciTech Connect

    Isenhower, Larry Donald

    2009-01-28

    Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

  18. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    PubMed

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  19. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    NASA Astrophysics Data System (ADS)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  20. Design of an FPGA-based electronic flow regulator (EFR) for spacecraft propulsion system

    NASA Astrophysics Data System (ADS)

    Manikandan, J.; Jayaraman, M.; Jayachandran, M.

    2011-02-01

    This paper describes a scheme for electronically regulating the flow of propellant to the thruster from a high-pressure storage tank used in spacecraft application. Precise flow delivery of propellant to thrusters ensures propulsion system operation at best efficiency by maximizing the propellant and power utilization for the mission. The proposed field programmable gate array (FPGA) based electronic flow regulator (EFR) is used to ensure precise flow of propellant to the thrusters from a high-pressure storage tank used in spacecraft application. This paper presents hardware and software design of electronic flow regulator and implementation of the regulation logic onto an FPGA.Motivation for proposed FPGA-based electronic flow regulation is on the disadvantages of conventional approach of using analog circuits. Digital flow regulation overcomes the analog equivalent as digital circuits are highly flexible, are not much affected due to noise, accurate performance is repeatable, interface is easier to computers, storing facilities are possible and finally failure rate of digital circuits is less. FPGA has certain advantages over ASIC and microprocessor/micro-controller that motivated us to opt for FPGA-based electronic flow regulator. Also the control algorithm being software, it is well modifiable without changing the hardware. This scheme is simple enough to adopt for a wide range of applications, where the flow is to be regulated for efficient operation.The proposed scheme is based on a space-qualified re-configurable field programmable gate arrays (FPGA) and hybrid micro circuit (HMC). A graphical user interface (GUI) based application software is also developed for debugging, monitoring and controlling the electronic flow regulator from PC COM port.

  1. Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale

    PubMed Central

    Huang, Muhuan; Wu, Di; Yu, Cody Hao; Fang, Zhenman; Interlandi, Matteo; Condie, Tyson; Cong, Jason

    2017-01-01

    With the end of CPU core scaling due to dark silicon limitations, customized accelerators on FPGAs have gained increased attention in modern datacenters due to their lower power, high performance and energy efficiency. Evidenced by Microsoft’s FPGA deployment in its Bing search engine and Intel’s 16.7 billion acquisition of Altera, integrating FPGAs into datacenters is considered one of the most promising approaches to sustain future datacenter growth. However, it is quite challenging for existing big data computing systems—like Apache Spark and Hadoop—to access the performance and energy benefits of FPGA accelerators. In this paper we design and implement Blaze to provide programming and runtime support for enabling easy and efficient deployments of FPGA accelerators in datacenters. In particular, Blaze abstracts FPGA accelerators as a service (FaaS) and provides a set of clean programming APIs for big data processing applications to easily utilize those accelerators. Our Blaze runtime implements an FaaS framework to efficiently share FPGA accelerators among multiple heterogeneous threads on a single node, and extends Hadoop YARN with accelerator-centric scheduling to efficiently share them among multiple computing tasks in the cluster. Experimental results using four representative big data applications demonstrate that Blaze greatly reduces the programming efforts to access FPGA accelerators in systems like Apache Spark and YARN, and improves the system throughput by 1.7 × to 3× (and energy efficiency by 1.5× to 2.7×) compared to a conventional CPU-only cluster. PMID:28317049

  2. The proposed trigger-less TBit/s readout for the Mu3e experiment

    NASA Astrophysics Data System (ADS)

    Bachmann, S.; Berger, N.; Blondel, A.; Bravar, S.; Buniatyan, A.; Dissertori, G.; Eckert, P.; Fischer, P.; Grab, C.; Gredig, R.; Hildebrandt, M.; Kettle, P.-R.; Kiehn, M.; Papa, A.; Perić, I.; Pohl, M.; Ritt, S.; Robmann, P.; Schöning, A.; Schultz-Coulon, H.-C.; Shen, W.; Shresta, S.; Stoykov, A.; Straumann, U.; Wallny, R.; Wiedner, D.; Windelband, B.

    2014-01-01

    The Mu3e experiment searches for charged lepton flavor violation in the rare decay μ→eee with a projected sensitivity of 10-16. A precise measurement of the decay product momenta, decay vertex and time is necessary for background suppression at rates of 109 muons/s. This can be achieved by combining an ultra-lightweight pixel tracker based on HV-MAPS with two timing systems. The trigger-less readout of the detector with three stages of FPGA-boards over multi GBit/s optical links into a GPU filter farm is presented. In this scheme data from all sub-detectors is merged and distributed in time slices to the filter farm.

  3. A novel approach to Hough Transform for implementation in fast triggers

    NASA Astrophysics Data System (ADS)

    Pozzobon, Nicola; Montecassiano, Fabio; Zotto, Pierluigi

    2016-10-01

    Telescopes of position sensitive detectors are common layouts in charged particles tracking, and programmable logic devices, such as FPGAs, represent a viable choice for the real-time reconstruction of track segments in such detector arrays. A compact implementation of the Hough Transform for fast triggers in High Energy Physics, exploiting a parameter reduction method, is proposed, targeting the reduction of the needed storage or computing resources in current, or next future, state-of-the-art FPGA devices, while retaining high resolution over a wide range of track parameters. The proposed approach is compared to a Standard Hough Transform with particular emphasis on their application to muon detectors. In both cases, an original readout implementation is modeled.

  4. JASMONATE-TRIGGERED PLANT IMMUNITY

    PubMed Central

    Campos, Marcelo L.; Kang, Jin-Ho; Howe, Gregg A.

    2014-01-01

    The plant hormone jasmonate (JA) exerts direct control over the production of chemical defense compounds that confer resistance to a remarkable spectrum of plant-associated organisms, ranging from microbial pathogens to vertebrate herbivores. The underlying mechanism of JA-triggered immunity (JATI) can be conceptualized as a multi-stage signal transduction cascade involving: i) pattern recognition receptors (PRRs) that couple the perception of danger signals to rapid synthesis of bioactive JA; ii) an evolutionarily conserved JA signaling module that links fluctuating JA levels to changes in the abundance of transcriptional repressor proteins; and iii) activation (de-repression) of transcription factors that orchestrate the expression of myriad chemical and morphological defense traits. Multiple negative feedback loops act in concert to restrain the duration and amplitude of defense responses, presumably to mitigate potential fitness costs of JATI. The convergence of diverse plant- and non-plant-derived signals on the core JA module indicates that JATI is a general response to perceived danger. However, the modular structure of JATI may accommodate attacker-specific defense responses through evolutionary innovation of PRRs (inputs) and defense traits (outputs). The efficacy of JATI as a defense strategy is highlighted by its capacity to shape natural populations of plant attackers, as well as the propensity of plant-associated organisms to subvert or otherwise manipulate JA signaling. As both a cellular hub for integrating informational cues from the environment and a common target of pathogen effectors, the core JA module provides a focal point for understanding immune system networks and the evolution of chemical diversity in the plant kingdom. PMID:24973116

  5. Global search of triggered non-volcanic tremor

    NASA Astrophysics Data System (ADS)

    Chao, Tzu-Kai Kevin

    Deep non-volcanic tremor is a newly discovered seismic phenomenon with low amplitude, long duration, and no clear P- and S-waves as compared with regular earthquake. Tremor has been observed at many major plate-boundary faults, providing new information about fault slip behaviors below the seismogenic zone. While tremor mostly occurs spontaneously (ambient tremor) or during episodic slow-slip events (SSEs), sometimes tremor can also be triggered during teleseismic waves of distance earthquakes, which is known as "triggered tremor". The primary focus of my Ph.D. work is to understand the physical mechanisms and necessary conditions of triggered tremor by systematic investigations in different tectonic regions. In the first chapter of my dissertation, I conduct a systematic survey of triggered tremor beneath the Central Range (CR) in Taiwan for 45 teleseismic earthquakes from 1998 to 2009 with Mw ≥ 7.5. Triggered tremors are visually identified as bursts of high-frequency (2-8 Hz), non-impulsive, and long-duration seismic energy that are coherent among many seismic stations and modulated by the teleseismic surface waves. A total of 9 teleseismic earthquakes has triggered clear tremor in Taiwan. The peak ground velocity (PGV) of teleseismic surface waves is the most important factor in determining tremor triggering potential, with an apparent threshold of ˜0.1 cm/s, or 7-8 kPa. However, such threshold is partially controlled by the background noise level, preventing triggered tremor with weaker amplitude from being observed. In addition, I find a positive correlation between the PGV and the triggered tremor amplitude, which is consistent with the prediction of the 'clock-advance' model. This suggests that triggered tremor can be considered as a sped-up occurrence of ambient tremor under fast loading from the passing surface waves. Finally, the incident angles of surface waves also play an important rule in controlling the tremor triggering potential. The next

  6. Skier triggering of backcountry avalanches with skilled route selection

    NASA Astrophysics Data System (ADS)

    Sinickas, Alexandra; Haegeli, Pascal; Jamieson, Bruce

    2015-04-01

    Jamieson (2009) provided numerical estimates for the baseline probabilities of triggering an avalanche by a backcountry skier making fresh tracks without skilled route selection as a function of the North American avalanche danger scale (i.e., hazard levels Low, Moderate, Considerable, High and Extreme). Using the results of an expert survey, he showed that triggering probabilities while skiing directly up, down or across a trigger zone without skilled route selection increase roughly by a factor of 10 with each step of the North American avalanche danger scale (i.e. hazard level). The objective of the present study is to examine the effect of skilled route selection on the relationship between triggering probability and hazard level. To assess the effect of skilled route selection on triggering probability by hazard level, we analysed avalanche hazard assessments as well as reports of skiing activity and triggering of avalanches from 11 Canadian helicopter and snowcat operations during two winters (2012-13 and 2013-14). These reports were submitted to the daily information exchange among Canadian avalanche safety operations, and reflect professional decision-making and route selection practices of guides leading groups of skiers. We selected all skier-controlled or accidentally triggered avalanches with a destructive size greater than size 1 according to the Canadian avalanche size classification, triggered by any member of a guided group (guide or guest). These operations forecast the avalanche hazard daily for each of three elevation bands: alpine, treeline and below treeline. In contrast to the 2009 study, an exposure was defined as a group skiing within any one of the three elevation bands, and consequently within a hazard rating, for the day (~4,300 ratings over two winters). For example, a group that skied below treeline (rated Moderate) and treeline (rated Considerable) in one day, would receive one count for exposure to Moderate hazard, and one count for

  7. FPGA-based JPEG-LS encoder for onboard real-time lossless image compression

    NASA Astrophysics Data System (ADS)

    Mert, Yakup Murat

    2015-05-01

    In this study, a hardware efficient field-programmable-gate-array (FPGA) implementation of the JPEG-LS encoder for lossless image compression is introduced. Encoder architecture comprises both regular mode and run mode with run interruption sample encoding procedures for full compliance with the ISO/ITU standard. Differently from former reported implementations, prediction error computation is optimized with pipeline data forwarding technique for optimum delay and minimum complexity. Besides, procedures of the run-length encoding are realized with normalization scheme using look-up tables without update latency. Synthesis results showed that proposed optimizations improved the processing speed of the encoder noticeably while FPGA hardware footprint is significantly reduced.

  8. Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

    PubMed Central

    de Souza, Alisson C. D.; Fernandes, Marcelo A. C.

    2014-01-01

    This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA. PMID:25268918

  9. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    PubMed

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.

  10. Parallel fixed point implementation of a radial basis function network in an FPGA.

    PubMed

    de Souza, Alisson C D; Fernandes, Marcelo A C

    2014-09-29

    This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

  11. Design and Implementation of High Frequency Ultrasound Pulsed-Wave Doppler Using FPGA

    PubMed Central

    Hu, Chang-hong; Zhou, Qifa; Shung, K. Kirk

    2009-01-01

    The development of a field-programmable gate array (FPGA)-based pulsed-wave Doppler processing approach in pure digital domain is reported in this paper. After the ultrasound signals are digitized, directional Doppler frequency shifts are obtained with a digital-down converter followed by a low-pass filter. A Doppler spectrum is then calculated using the complex fast Fourier transform core inside the FPGA. In this approach, a pulsed-wave Doppler implementation core with reconfigurable and real-time processing capability is achieved. PMID:18986909

  12. A Multi-Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices

    NASA Astrophysics Data System (ADS)

    Biasizzo, Anton; Novak, Franc; Korošec, Peter

    2013-01-01

    Arithmetic coding is a lossless compression algorithm with variable-length source coding. It is more flexible and efficient than the well-known Huffman coding. In this paper we present a non-adaptive FPGA implementation of a multi-alphabet arithmetic coding with separated statistical model of the data source. The alphabet of the data source is a 256-symbol ASCII character set and does not include the special end-of-file symbol. No context switching is used in the proposed design which gives maximal throughput without pipelining. We have synthesized the design for Xilinx FPGA devices and used their built-in hardware resources.

  13. Anthropogenic Triggering of Large Earthquakes

    NASA Astrophysics Data System (ADS)

    Mulargia, Francesco; Bizzarri, Andrea

    2014-08-01

    The physical mechanism of the anthropogenic triggering of large earthquakes on active faults is studied on the basis of experimental phenomenology, i.e., that earthquakes occur on active tectonic faults, that crustal stress values are those measured in situ and, on active faults, comply to the values of the stress drop measured for real earthquakes, that the static friction coefficients are those inferred on faults, and that the effective triggering stresses are those inferred for real earthquakes. Deriving the conditions for earthquake nucleation as a time-dependent solution of the Tresca-Von Mises criterion applied in the framework of poroelasticity yields that active faults can be triggered by fluid overpressures < 0.1 MPa. Comparing this with the deviatoric stresses at the depth of crustal hypocenters, which are of the order of 1-10 MPa, we find that injecting in the subsoil fluids at the pressures typical of oil and gas production and storage may trigger destructive earthquakes on active faults at a few tens of kilometers. Fluid pressure propagates as slow stress waves along geometric paths operating in a drained condition and can advance the natural occurrence of earthquakes by a substantial amount of time. Furthermore, it is illusory to control earthquake triggering by close monitoring of minor ``foreshocks'', since the induction may occur with a delay up to several years.

  14. Anthropogenic triggering of large earthquakes.

    PubMed

    Mulargia, Francesco; Bizzarri, Andrea

    2014-08-26

    The physical mechanism of the anthropogenic triggering of large earthquakes on active faults is studied on the basis of experimental phenomenology, i.e., that earthquakes occur on active tectonic faults, that crustal stress values are those measured in situ and, on active faults, comply to the values of the stress drop measured for real earthquakes, that the static friction coefficients are those inferred on faults, and that the effective triggering stresses are those inferred for real earthquakes. Deriving the conditions for earthquake nucleation as a time-dependent solution of the Tresca-Von Mises criterion applied in the framework of poroelasticity yields that active faults can be triggered by fluid overpressures < 0.1 MPa. Comparing this with the deviatoric stresses at the depth of crustal hypocenters, which are of the order of 1-10 MPa, we find that injecting in the subsoil fluids at the pressures typical of oil and gas production and storage may trigger destructive earthquakes on active faults at a few tens of kilometers. Fluid pressure propagates as slow stress waves along geometric paths operating in a drained condition and can advance the natural occurrence of earthquakes by a substantial amount of time. Furthermore, it is illusory to control earthquake triggering by close monitoring of minor "foreshocks", since the induction may occur with a delay up to several years.

  15. Anthropogenic Triggering of Large Earthquakes

    PubMed Central

    Mulargia, Francesco; Bizzarri, Andrea

    2014-01-01

    The physical mechanism of the anthropogenic triggering of large earthquakes on active faults is studied on the basis of experimental phenomenology, i.e., that earthquakes occur on active tectonic faults, that crustal stress values are those measured in situ and, on active faults, comply to the values of the stress drop measured for real earthquakes, that the static friction coefficients are those inferred on faults, and that the effective triggering stresses are those inferred for real earthquakes. Deriving the conditions for earthquake nucleation as a time-dependent solution of the Tresca-Von Mises criterion applied in the framework of poroelasticity yields that active faults can be triggered by fluid overpressures < 0.1 MPa. Comparing this with the deviatoric stresses at the depth of crustal hypocenters, which are of the order of 1–10 MPa, we find that injecting in the subsoil fluids at the pressures typical of oil and gas production and storage may trigger destructive earthquakes on active faults at a few tens of kilometers. Fluid pressure propagates as slow stress waves along geometric paths operating in a drained condition and can advance the natural occurrence of earthquakes by a substantial amount of time. Furthermore, it is illusory to control earthquake triggering by close monitoring of minor “foreshocks”, since the induction may occur with a delay up to several years. PMID:25156190

  16. STAR: FPGA-based software defined satellite transponder

    NASA Astrophysics Data System (ADS)

    Davalle, Daniele; Cassettari, Riccardo; Saponara, Sergio; Fanucci, Luca; Cucchi, Luca; Bigongiari, Franco; Errico, Walter

    2013-05-01

    This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

  17. FPGA-Based Networked Phasemeter for a Heterodyne Interferometer

    NASA Technical Reports Server (NTRS)

    Rao, Shanti

    2009-01-01

    A document discusses a component of a laser metrology system designed to measure displacements along the line of sight with precision on the order of a tenth the diameter of an atom. This component, the phasemeter, measures the relative phase of two electrical signals and transfers that information to a computer. Because the metrology system measures the differences between two optical paths, the phasemeter has two inputs, called measure and reference. The reference signal is nominally a perfect square wave with a 50- percent duty cycle (though only rising edges are used). As the metrology system detects motion, the difference between the reference and measure signal phases is proportional to the displacement of the motion. The phasemeter, therefore, counts the elapsed time between rising edges in the two signals, and converts the time into an estimate of phase delay. The hardware consists of a circuit board that plugs into a COTS (commercial, off-the- shelf) Spartan-III FPGA (field-programmable gate array) evaluation board. It has two BNC inputs, (reference and measure), a CMOS logic chip to buffer the inputs, and an Ethernet jack for transmitting reduced-data to a PC. Two extra BNC connectors can be attached for future expandability, such as external synchronization. Each phasemeter handles one metrology channel. A bank of six phasemeters (and two zero-crossing detector cards) with an Ethernet switch can monitor the rigid body motion of an object. This device is smaller and cheaper than existing zero-crossing phasemeters. Also, because it uses Ethernet for communication with a computer, instead of a VME bridge, it is much easier to use. The phasemeter is a key part of the Precision Deployable Apertures and Structures strategic R&D effort to design large, deployable, segmented space telescopes.

  18. Industrial accidents triggered by lightning.

    PubMed

    Renni, Elisabetta; Krausmann, Elisabeth; Cozzani, Valerio

    2010-12-15

    Natural disasters can cause major accidents in chemical facilities where they can lead to the release of hazardous materials which in turn can result in fires, explosions or toxic dispersion. Lightning strikes are the most frequent cause of major accidents triggered by natural events. In order to contribute towards the development of a quantitative approach for assessing lightning risk at industrial facilities, lightning-triggered accident case histories were retrieved from the major industrial accident databases and analysed to extract information on types of vulnerable equipment, failure dynamics and damage states, as well as on the final consequences of the event. The most vulnerable category of equipment is storage tanks. Lightning damage is incurred by immediate ignition, electrical and electronic systems failure or structural damage with subsequent release. Toxic releases and tank fires tend to be the most common scenarios associated with lightning strikes. Oil, diesel and gasoline are the substances most frequently released during lightning-triggered Natech accidents.

  19. ATP-triggered anticancer drug delivery

    NASA Astrophysics Data System (ADS)

    Mo, Ran; Jiang, Tianyue; Disanto, Rocco; Tai, Wanyi; Gu, Zhen

    2014-03-01

    Stimuli-triggered drug delivery systems have been increasingly used to promote physiological specificity and on-demand therapeutic efficacy of anticancer drugs. Here we utilize adenosine-5'-triphosphate (ATP) as a trigger for the controlled release of anticancer drugs. We demonstrate that polymeric nanocarriers functionalized with an ATP-binding aptamer-incorporated DNA motif can selectively release the intercalating doxorubicin via a conformational switch when in an ATP-rich environment. The half-maximal inhibitory concentration of ATP-responsive nanovehicles is 0.24 μM in MDA-MB-231 cells, a 3.6-fold increase in the cytotoxicity compared with that of non-ATP-responsive nanovehicles. Equipped with an outer shell crosslinked by hyaluronic acid, a specific tumour-targeting ligand, the ATP-responsive nanocarriers present an improvement in the chemotherapeutic inhibition of tumour growth using xenograft MDA-MB-231 tumour-bearing mice. This ATP-triggered drug release system provides a more sophisticated drug delivery system, which can differentiate ATP levels to facilitate the selective release of drugs.

  20. ENSO-triggered floods in South America

    NASA Astrophysics Data System (ADS)

    Isla, Federico Ignacio

    2016-04-01

    ENSO-triggered floods altered completely the annual discharge of most watersheds of South America. Anomalous years as 1941, 1982-83 and 1997-98 signified enormous discharges of rivers draining toward the Pacific but also to the Atlantic Ocean. These floods affected large cities as Porto Alegre, Blumenau, Curitiba, Asunción, Santa Fe and Buenos Aires. Maximum discharge months are particular and easily distinguished at those watersheds located at the South American Arid Diagonal. At watersheds conditioned by precipitations delivered from the Atlantic or Pacific anticyclonic centers the ENSO-triggered floods are difficult to discern. The floods of 1941 affected 70,000 inhabitants in Porto Alegre. In 1983, Blumenau city was flooded during several days; and the Paraná River multiplied 15 times the width of its middle floodplain. The Colorado River in Northern Patagonia connected for the last time to the Desaguadero-Chadileuvú-Curacó system and therefore received saline water. ENSO years modify also the water balance of certain piedmont lakes of Southern Patagonia: the increases in snow accumulations cause high water levels with a lag of 13 months. The correlation between the maximum monthly discharges of 1982-83 and 1997-98 at different regions and watersheds indicates they can be forecasted for future floods triggered by same phenomena. South American rivers can be classified therefore into ENSO-affected, and ENSO-dominated, for those within the Arid Diagonal that are exclusively subject to high discharges during these years.

  1. Upgraded Trigger Readout Electronics for the ATLAS LAr Calorimeters for Future LHC Running

    NASA Astrophysics Data System (ADS)

    Ma, Hong; ATLAS Liquid Argon Calorimeter Group

    2015-02-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that are digitized and processed by the front-end and back-end electronics for every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first- level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 1034cm-2s-1. In order to retain the capability to trigger on low energy electrons and photons when the LHC is upgraded to higher luminosity, an improved LAr calorimeter trigger readout is proposed and being constructed. The new trigger readout system makes available the fine segmentation of the calorimeter at the L1 trigger with high precision in order to reduce the QCD jet background in electron, photon and tau triggers, and to improve jet and missing ET trigger performance. The new LAr Trigger Digitizer Board is designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new Digital Processing System. The reconstructed energies of trigger readout channels after digital filtering are transmitted to the L1 system, allowing the extraction of improved trigger signatures. This contribution presents the motivation for the upgrade, the concept for the new trigger readout and the expected performance of the new trigger, and describes the components being developed for the new system.

  2. BRCA1 Mutation Leads to Deregulated Ubc9 Levels which Triggers Proliferation and Migration of Patient-Derived High Grade Serous Ovarian Cancer and Triple Negative Breast Cancer Cells

    PubMed Central

    Xu, J; Footman, A; Qin, Y; Aysola, K; Black, S; Reddy, V; Singh, K; Grizzle, W; You, S; Moellering, D; Reddy, ES; Fu, Y; Rao, VN

    2016-01-01

    Women who carry a germline mutation in BRCA1 gene typically develop triple negative breast cancers (TNBC) and high grade serous ovarian cancers (HGSOC). Previously, we reported that wild type BRCA1 proteins, unlike the disease-associated mutant BRCA1 proteins to bind the sole sumo E2-conjugating enzyme Ubc9. In this study, we have used clinically relevant cell lines with known BRCA1 mutations and report the in-vivo association of BRCA1 and Ubc9 in normal mammary epithelial cells but not in BRCA1 mutant HGSOC and TNBC cells by immunofluorescence analysis. BRCA1-mutant HGSOC/TNBC cells and ovarian tumor tissues showed increased expression of Ubc9 compared to BRCA1 reconstituted HGSOC, normal mammary epithelial cells and matched normal ovarian tissues. Knockdown of Ubc9 expression resulted in decreased proliferation and migration of BRCA1 mutant TNBC and HGSOC cells. This is the first study demonstrating the functional link between BRCA1 mutation, high Ubc9 expression and increased migration of HGSOC and TNBC cells. High Ubc9 expression due to BRCA1 mutation may trigger an early growth and transformation advantage to normal breast and ovarian epithelial cells resulting in aggressive cancers. Future work will focus on studying whether Ubc9 expression could show a positive correlation with BRCA1 linked HGSOC and basal like TNBC phenotype. PMID:28164176

  3. Continuous infusion of neurotrophin-3 triggers sprouting, decreases the levels of TrkA and TrkC, and inhibits epileptogenesis and activity-dependent axonal growth in adult rats.

    PubMed

    Xu, B; Michalski, B; Racine, R J; Fahnestock, M

    2002-01-01

    Neurotrophin-3 (NT-3), a member of the neurotrophin family of neurotrophic factors, is important for cell survival, axonal growth and neuronal plasticity. Epileptiform activation can regulate the expression of neurotrophins, and increases or decreases in neurotrophins can affect both epileptogenesis and seizure-related axonal growth. Interestingly, the expression of nerve growth factor and brain-derived neurotrophic factor is rapidly up-regulated following seizures, while NT-3 mRNA remains unchanged or undergoes a delayed down-regulation, suggesting that NT-3 might have a different function in epileptogenesis. In the present study, we demonstrate that continuous intraventricular infusion of NT-3 in the absence of kindling triggers mossy fiber sprouting in the inner molecular layer of the dentate gyrus and the stratum oriens of the CA3 region. Furthermore, despite this NT-3-related sprouting effect, continuous infusion of NT-3 retards the development of behavioral seizures and inhibits kindling-induced mossy fiber sprouting in the inner molecular layer of the dentate gyrus. We also show that prolonged infusion of NT-3 leads to a decrease in kindling-induced Trk phosphorylation and a down-regulation of the high-affinity Trk receptors, TrkA and TrkC, suggesting an involvement of both cholinergic nerve growth factor receptors and hippocampal NT-3 receptors in these effects. Our results demonstrate an important inhibitory role for NT-3 in seizure development and seizure-related synaptic reorganization.

  4. Real-time co-registered ultrasound and photoacoustic imaging system based on FPGA and DSP architecture

    NASA Astrophysics Data System (ADS)

    Alqasemi, Umar; Li, Hai; Aguirre, Andres; Zhu, Quing

    2011-03-01

    Co-registering ultrasound (US) and photoacoustic (PA) imaging is a logical extension to conventional ultrasound because both modalities provide complementary information of tumor morphology, tumor vasculature and hypoxia for cancer detection and characterization. In addition, both modalities are capable of providing real-time images for clinical applications. In this paper, a Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) module-based real-time US/PA imaging system is presented. The system provides real-time US/PA data acquisition and image display for up to 5 fps* using the currently implemented DSP board. It can be upgraded to 15 fps, which is the maximum pulse repetition rate of the used laser, by implementing an advanced DSP module. Additionally, the photoacoustic RF data for each frame is saved for further off-line processing. The system frontend consists of eight 16-channel modules made of commercial and customized circuits. Each 16-channel module consists of two commercial 8-channel receiving circuitry boards and one FPGA board from Analog Devices. Each receiving board contains an IC† that combines. 8-channel low-noise amplifiers, variable-gain amplifiers, anti-aliasing filters, and ADC's‡ in a single chip with sampling frequency of 40MHz. The FPGA board captures the LVDSξ Double Data Rate (DDR) digital output of the receiving board and performs data conditioning and subbeamforming. A customized 16-channel transmission circuitry is connected to the two receiving boards for US pulseecho (PE) mode data acquisition. A DSP module uses External Memory Interface (EMIF) to interface with the eight 16-channel modules through a customized adaptor board. The DSP transfers either sub-beamformed data (US pulse-echo mode or PAI imaging mode) or raw data from FPGA boards to its DDR-2 memory through the EMIF link, then it performs additional processing, after that, it transfer the data to the PC** for further image processing. The PC code

  5. The CMS electron and photon trigger for the LHC Run 2

    NASA Astrophysics Data System (ADS)

    Dezoort, Gage; Xia, Fan

    2017-01-01

    The CMS experiment implements a sophisticated two-level triggering system composed of Level-1, instrumented by custom-design hardware boards, and a software High-Level-Trigger. A new Level-1 trigger architecture with improved performance is now being used to maintain the thresholds that were used in LHC Run I for the more challenging luminosity conditions experienced during Run II. The upgrades to the calorimetry trigger will be described along with performance data. The algorithms for the selection of final states with electrons and photons, both for precision measurements and for searches of new physics beyond the Standard Model, will be described in detail.

  6. A programmable systolic trigger processor for FERA-bus data

    NASA Astrophysics Data System (ADS)

    Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

    1992-09-01

    A generic CAMAC based trigger processor module for fast processing of large amounts of Analog to Digital Converter (ADC) data was designed. This module was realized using complex programmable gate arrays. The gate arrays were connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter is used for set up and control but may also be used for data output. Large numbers of ADC's can be served by a hierarchical arrangement of trigger processor modules which process ADC data with pipeline arithmetics and produce the final result at the apex of the pyramid. The trigger decision is transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was developed for the proposed neutral particle search. It was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data, and calculate the particle mass. A suitable mass cut would then deliver the trigger decision.

  7. FPGA-based data acquisition system for a Compton camera

    NASA Astrophysics Data System (ADS)

    Nurdan, K.; Çonka-Nurdan, T.; Besch, H. J.; Freisleben, B.; Pavel, N. A.; Walenta, A. H.

    2003-09-01

    A data acquisition (DAQ) system with custom back-plane and custom readout boards has been developed for a Compton camera prototype. The DAQ system consists of two layers. The first layer has units for parallel high-speed analog-to-digital conversion and online data pre-processing. The second layer has a central board to form a general event trigger and to build the data structure for the event. This modularity and the use of field programmable gate arrays make the whole DAQ system highly flexible and adaptable to modified experimental setups. The design specifications, the general architecture of the Trigger and DAQ system and the implemented readout protocols are presented in this paper.

  8. Remote triggering of non-volcanic tremor around Taiwan

    NASA Astrophysics Data System (ADS)

    Chao, Kevin; Peng, Zhigang; Wu, Chunquan; Tang, Chi-Chia; Lin, Cheng-Horng

    2012-01-01

    We perform a systematic survey of triggered deep 'non-volcanic' tremor beneath the Central Range (CR) in Taiwan for 45 teleseismic earthquakes from 1998 to 2009 with Mw≥ 7.5 and epicentral distance ≥1000 km to the broad-band station TPUB. Triggered tremors are visually identified as bursts of high-frequency (2-8 Hz), non-impulsive and long-duration seismic energy that are coherent among many seismic stations and modulated by the teleseismic surface waves. Out of the 45 earthquakes, we identified nine teleseismic events associated with nine tremor sources in the southern and five in the northern CR. Most of the tremor sources are located within the depth range of 15-25 km in the lower crust above the Moho. We find that the amplitudes of the surface waves play an important role in determining the triggering potential, and the apparent triggering threshold is ˜0.1 cm s-1, or 7-8 KPa. However, such threshold is partially controlled by the background noise level, which could prevent weaker tremor triggered by surface waves with smaller amplitudes from being identified. The amplitudes of the triggered tremor show a positive correlation with the amplitudes of the triggering surface waves, consistent with the predictions by the 'clock-advance' model. In addition to amplitudes, other factors, such as frequency contents and incidence angles, also affect the triggering potential. We find that intermediate-period (30-10 s) surface waves could trigger/modulate tremors, suggesting that long-period (>30 s) surface waves are not always required in long-range triggering. Tremors appear to be triggered by both Love and Rayleigh waves. When the incidence angles are parallel to the strike of the CR, all six events triggered tremor primarily during the Rayleigh waves. For strike normal incidence, only the 2001 Mw7.8 Kunlun earthquake showed predominant Love-wave triggering. This observation can be qualitatively explained by a simple Coulomb failure for a left-lateral shear on the

  9. A New Look at Trigger Point Injections

    PubMed Central

    Wong, Clara S. M.; Wong, Steven H. S.

    2012-01-01

    Trigger point injections are commonly practised pain interventional techniques. However, there is still lack of objective diagnostic criteria for trigger points. The mechanisms of action of trigger point injection remain obscure and its efficacy remains heterogeneous. The advent of ultrasound technology in the noninvasive real-time imaging of soft tissues sheds new light on visualization of trigger points, explaining the effect of trigger point injection by blockade of peripheral nerves, and minimizing the complications of blind injection. PMID:21969825

  10. Suicide Triggers Described by Herodotus

    PubMed Central

    Auchincloss, Stephane; Ahmadi, Jamshid

    2016-01-01

    Objective: The aim of this study was to better understand the triggers of suicide, particularly among the ancient Greek and Persian soldiers and commanders. Method: ‘Herodotus:TheHistories’ is a history of the rulers and soldiery who participated in the Greco-Persian wars (492-449 BCE). A new translation (2013) of this manuscript was studied. Accounts of suicide were collected and collated, with descriptions of circumstances, methods, and probable triggers. Results: Nine accounts of suicide were identified. Eight of these were named individuals (4 Greeks and 4 Persians); of whom, seven were male. Only one (not the female) appeared to act in response to a mental disorder. Other triggers of suicide included guilt, avoidance of dishonour/punishment and altruism. Cutting/ stabbing was the most common method; others included hanging, jumping, poison, and burning (the single female). Conclusion: While soldiers at a time of war do not reflect the general community, they are nevertheless members of their society. Thus, this evidence demonstrates that suicide triggered by burdensome circumstances (in addition to mental disorder) was known to the Greek and Persian people more than two millennia ago. PMID:27437010

  11. LDPC decoder with a limited-precision FPGA-based floating-point multiplication coprocessor

    NASA Astrophysics Data System (ADS)

    Moberly, Raymond; O'Sullivan, Michael; Waheed, Khurram

    2007-09-01

    Implementing the sum-product algorithm, in an FPGA with an embedded processor, invites us to consider a tradeoff between computational precision and computational speed. The algorithm, known outside of the signal processing community as Pearl's belief propagation, is used for iterative soft-decision decoding of LDPC codes. We determined the feasibility of a coprocessor that will perform product computations. Our FPGA-based coprocessor (design) performs computer algebra with significantly less precision than the standard (e.g. integer, floating-point) operations of general purpose processors. Using synthesis, targeting a 3,168 LUT Xilinx FPGA, we show that key components of a decoder are feasible and that the full single-precision decoder could be constructed using a larger part. Soft-decision decoding by the iterative belief propagation algorithm is impacted both positively and negatively by a reduction in the precision of the computation. Reducing precision reduces the coding gain, but the limited-precision computation can operate faster. A proposed solution offers custom logic to perform computations with less precision, yet uses the floating-point format to interface with the software. Simulation results show the achievable coding gain. Synthesis results help theorize the the full capacity and performance of an FPGA-based coprocessor.

  12. FPGA implementation of a biological neural network based on the Hodgkin-Huxley neuron model

    PubMed Central

    Yaghini Bonabi, Safa; Asgharian, Hassan; Safari, Saeed; Nili Ahmadabadi, Majid

    2014-01-01

    A set of techniques for efficient implementation of Hodgkin-Huxley-based (H-H) model of a neural network on FPGA (Field Programmable Gate Array) is presented. The central implementation challenge is H-H model complexity that puts limits on the network size and on the execution speed. However, basics of the original model cannot be compromised when effect of synaptic specifications on the network behavior is the subject of study. To solve the problem, we used computational techniques such as CORDIC (Coordinate Rotation Digital Computer) algorithm and step-by-step integration in the implementation of arithmetic circuits. In addition, we employed different techniques such as sharing resources to preserve the details of model as well as increasing the network size in addition to keeping the network execution speed close to real time while having high precision. Implementation of a two mini-columns network with 120/30 excitatory/inhibitory neurons is provided to investigate the characteristic of our method in practice. The implementation techniques provide an opportunity to construct large FPGA-based network models to investigate the effect of different neurophysiological mechanisms, like voltage-gated channels and synaptic activities, on the behavior of a neural network in an appropriate execution time. Additional to inherent properties of FPGA, like parallelism and re-configurability, our approach makes the FPGA-based system a proper candidate for study on neural control of cognitive robots and systems as well. PMID:25484854

  13. A method of image multi-resolution processing based on FPGA + DSP architecture

    NASA Astrophysics Data System (ADS)

    Peng, Xiaohan; Zhong, Sheng; Lu, Hongqiang

    2015-10-01

    In real-time image processing, with the improvement of resolution and frame rate of camera imaging, not only the requirement of processing capacity is improving, but also the requirement of the optimization of process is improving. With regards to the FPGA + DSP architecture image processing system, there are three common methods to overcome the challenge above. The first is using higher performance DSP. For example, DSP with higher core frequency or with more cores can be used. The second is optimizing the processing method, make the algorithm to accomplish the same processing results but spend less time. Last but not least, pre-processing in the FPGA can make the image processing more efficient. A method of multi-resolution pre-processing by FPGA based on FPGA + DSP architecture is proposed here. It takes advantage of built-in first in first out (FIFO) and external synchronous dynamic random access memory (SDRAM) to buffer the images which come from image detector, and provides down-sampled images or cut-down images for DSP flexibly and efficiently according to the request parameters sent by DSP. DSP can thus get the degraded image instead of the whole image to process, shortening the processing time and transmission time greatly. The method results in alleviating the burden of image processing of DSP and also solving the problem of single method of image resolution reduction cannot meet the requirements of image processing task of DSP.

  14. RHrFPGA Radiation-Hardened Re-programmable Field-Programmable Gate Array

    NASA Technical Reports Server (NTRS)

    Sanders, A. B.; LaBel, K. A.; McCabe, J. F.; Gardner, G. A.; Lintz, J.; Ross, C.; Golke, K.; Burns, B.; Carts, M. A.; Kim, H. S.

    2004-01-01

    Viewgraphs on the development of the Radiation-Hardened Re-programmable Field-Programmable Gate Array (RHrFPGA) are presented. The topics include: 1) Radiation Test Suite; 2) Testing Interface; 3) Test Configuration; 4) Facilities; 5) Test Programs; 6) Test Procedure; and 7) Test Results. A summary of heavy ion and proton testing is also included.

  15. FPGA Implementation of Discrete-Time Neuronal Network for Dynamic Image Segmentation

    NASA Astrophysics Data System (ADS)

    Fujimoto, Ken'ichi; Musashi, Mio; Yoshinaga, Tetsuya

    We have developed a discrete-time dynamical system for dynamic image segmentation. It consists of a global inhibitor and modified chaotic neurons that can generate oscillatory responses. Dynamic image segmentation is performed using its oscillatory responses. This letter presents an implementation of our system in a field programmable gate array (FPGA) device and a successful result of dynamic image segmentation.

  16. A single FPGA-based portable ultrasound imaging system for point-of-care applications.

    PubMed

    Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

    2012-07-01

    We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

  17. FPGA implementation of a biological neural network based on the Hodgkin-Huxley neuron model.

    PubMed

    Yaghini Bonabi, Safa; Asgharian, Hassan; Safari, Saeed; Nili Ahmadabadi, Majid

    2014-01-01

    A set of techniques for efficient implementation of Hodgkin-Huxley-based (H-H) model of a neural network on FPGA (Field Programmable Gate Array) is presented. The central implementation challenge is H-H model complexity that puts limits on the network size and on the execution speed. However, basics of the original model cannot be compromised when effect of synaptic specifications on the network behavior is the subject of study. To solve the problem, we used computational techniques such as CORDIC (Coordinate Rotation Digital Computer) algorithm and step-by-step integration in the implementation of arithmetic circuits. In addition, we employed different techniques such as sharing resources to preserve the details of model as well as increasing the network size in addition to keeping the network execution speed close to real time while having high precision. Implementation of a two mini-columns network with 120/30 excitatory/inhibitory neurons is provided to investigate the characteristic of our method in practice. The implementation techniques provide an opportunity to construct large FPGA-based network models to investigate the effect of different neurophysiological mechanisms, like voltage-gated channels and synaptic activities, on the behavior of a neural network in an appropriate execution time. Additional to inherent properties of FPGA, like parallelism and re-configurability, our approach makes the FPGA-based system a proper candidate for study on neural control of cognitive robots and systems as well.

  18. FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery.

    PubMed

    Haselman, M D; Pasko, J; Hauck, S; Lewellen, T K; Miyaoka, R S

    2012-10-01

    Modern field programmable gate arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz. This, combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilized to add significant signal processing power to produce higher quality images. In this paper we report on an all-digital pulse pile-up correction algorithm that has been developed for the FPGA. The pile-up mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pile-up events. Using pulses acquired from a Zecotech Photonics MAPD-N with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pile-up utilizing a moderate amount of FPGA resources.

  19. Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

    PubMed

    Xia, Fei; Jin, Guoqing

    2014-06-01

    PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

  20. FPGA Based High Speed Data Acquisition System for Electrical Impedance Tomography.

    PubMed

    Khan, S; Borsic, A; Manwaring, Preston; Hartov, Alexander; Halter, Ryan

    2013-03-01

    Electrical Impedance Tomography (EIT) systems are used to image tissue bio-impedance. EIT provides a number of features making it attractive for use as a medical imaging device including the ability to image fast physiological processes (>60 Hz), to meet a range of clinical imaging needs through varying electrode geometries and configurations, to impart only non-ionizing radiation to a patient, and to map the significant electrical property contrasts present between numerous benign and pathological tissues. To leverage these potential advantages for medical imaging, we developed a modular 32 channel data acquisition (DAQ) system using National Instruments' PXI chassis, along with FPGA, ADC, Signal Generator and Timing and Synchronization modules. To achieve high frame rates, signal demodulation and spectral characteristics of higher order harmonics were computed using dedicated FFT-hardware built into the FPGA module. By offloading the computing onto FPGA, we were able to achieve a reduction in throughput required between the FPGA and PC by a factor of 32:1. A custom designed analog front end (AFE) was used to interface electrodes with our system. Our system is wideband, and capable of acquiring data for input signal frequencies ranging from 100 Hz to 12 MHz. The modular design of both the hardware and software will allow this system to be flexibly configured for the particular clinical application.