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Sample records for level fpga trigger

  1. FPGA Trigger System to Run Klystrons

    SciTech Connect

    Gray, Darius; /Texas A-M /SLAC

    2010-08-25

    The Klystron Department is in need of a new trigger system to update the laboratory capabilities. The objective of the research is to develop the trigger system using Field Programmable Gate Array (FPGA) technology with a user interface that will allow one to communicate with the FPGA via a Universal Serial Bus (USB). This trigger system will be used for the testing of klystrons. The key materials used consists of the Xilinx Integrated Software Environment (ISE) Foundation, a Programmable Read Only Memory (Prom) XCF04S, a Xilinx Spartan 3E 35S500E FPGA, Xilinx Platform Cable USB II, a Printed Circuit Board (PCB), a 100 MHz oscillator, and an oscilloscope. Key considerations include eight triggers, two of which have variable phase shifting capabilities. Once the project was completed the output signals were able to be manipulated via a Graphical User Interface by varying the delay and width of the signal. This was as planned; however, the ability to vary the phase was not completed. Future work could consist of being able to vary the phase. This project will give the operators in the Klystron Department more flexibility to run various tests.

  2. FPGA-based Trigger System for the Fermilab SeaQuest Experimentz

    SciTech Connect

    Shiu, Shiuan-Hal; Wu, Jinyuan; McClellan, Randall Evan; Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu; Gilman, Ron; Nakano, Kenichi; Peng, Jen-Chieh; Wang, Su-Yin

    2015-09-10

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ+ and μ-produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system we used consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined against pre-determined trigger matrices to identify candidate muon tracks. Finally, information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.

  3. FPGA-based Trigger System for the Fermilab SeaQuest Experimentz

    DOE PAGES

    Shiu, Shiuan-Hal; Wu, Jinyuan; McClellan, Randall Evan; Chang, Ting-Hua; Chang, Wen-Chen; Chen, Yen-Chu; Gilman, Ron; Nakano, Kenichi; Peng, Jen-Chieh; Wang, Su-Yin

    2015-09-10

    The SeaQuest experiment (Fermilab E906) detects pairs of energetic μ+ and μ-produced in 120 GeV/c proton–nucleon interactions in a high rate environment. The trigger system we used consists of several arrays of scintillator hodoscopes and a set of field-programmable gate array (FPGA) based VMEbus modules. Signals from up to 96 channels of hodoscope are digitized by each FPGA with a 1-ns resolution using the time-to-digital convertor (TDC) firmware. The delay of the TDC output can be adjusted channel-by-channel in 1-ns step and then re-aligned with the beam RF clock. The hit pattern on the hodoscope planes is then examined againstmore » pre-determined trigger matrices to identify candidate muon tracks. Finally, information on the candidate tracks is sent to the 2nd-level FPGA-based track correlator to find candidate di-muon events. The design and implementation of the FPGA-based trigger system for SeaQuest experiment are presented.« less

  4. FPGA based triggers in the Pierre Auger Observatory

    NASA Astrophysics Data System (ADS)

    Szadkowski, Z.

    2008-01-01

    The Pierre Auger Observatory is an international project for research on ultra-high energy cosmic rays (UHECR) above 10 19 eV and currently the world largest "hybrid" experiment. The hybrid technique uses both the detection of particles at the ground in water Cherenkov detectors (WCD) and measurements of fluorescence light generated in the atmosphere by the extensive air showers. This technique offers unique possibilities for cross-calibration and reduction of measurement uncertainties. The surface array will contain 1600 surface detector stations distributed over 3000 km2 in the Southern Hemisphere (under construction in Argentina) and 4000 WCD distributed over 10000 km2 at a Northern Hemisphere site in Colorado (deployment planned for 2008). Four fluorescence stations each containing 6 wide-angle Schmidt telescopes and each equipped with 440 PMTs with 1.5° angle resolution and 30 • 30° of field of view are located on the border of the surface array in the Southern Site. The paper presents implementations of the FPGA used for triggering. The use is illustrated with currently working schemes as well as other possible ideas especially promising for the surface detector in which currently used triggers seems to be not effective enough for very inclined and horizontal showers. Proposed new triggers enlarge a simple 1-bit threshold detection to the online analysis of a FADC trace shape. This corresponds to a charge from PMTs or signal power estimation. The next category is spectral triggers analyzing sequential samples in the frequency domain. Digital sigma-delta filters immunize the trigger circuitry on the pedestal variation as results of huge temperature swings. Presented DCT trigger provides native pedestal independence.

  5. FPGA Based Wavelet Trigger in Radio Detection of Cosmic Rays

    NASA Astrophysics Data System (ADS)

    Szadkowski, Zbigniew; Szadkowska, Anna

    2014-09-01

    Experiments which show coherent radio emission from extensive air showers induced by ultra-high-energy cosmic rays are designed for a detailed study of the development of the electromagnetic part of air showers. Radio detectors can operate with 100 % up time as, e.g., surface detectors based on water-Cherenkov tanks. They are being developed for ground-based experiments (e.g., the Pierre Auger Observatory) as another type of air-shower detector in addition to fluorescence detectors, which operate with only ˜10 % of duty on dark nights. The radio signals from air showers are caused by coherent emission from geomagnetic radiation and charge-excess processes. The self-triggers in radio detectors currently in use often generate a dense stream of data, which is analyzed afterwards. Huge amounts of registered data require significant manpower for off-line analysis. Improvement of trigger efficiency is a relevant factor. The wavelet trigger, which investigates on-line the power of radio signals (˜V2/R), is promising; however, it requires some improvements with respect to current designs. In this work, Morlet wavelets with various scaling factors were used for an analysis of real data from the Auger Engineering Radio Array and for optimization of the utilization of the resources in an FPGA. The wavelet analysis showed that the power of events is concentrated mostly in a limited range of the frequency spectrum (consistent with a range imposed by the input analog band-pass filter). However, we found several events with suspicious spectral characteristics, where the signal power is spread over the full band-width sampled by a 200 MHz digitizer with significant contribution of very high and very low frequencies. These events may not originate from cosmic ray showers but could be the result of human contamination. The engine of the wavelet analysis can be implemented in the modern powerful FPGAs and can remove suspicious events on-line to reduce the trigger rate.

  6. FPGA Based Wavelet Trigger in Radio Detection of Cosmic Rays

    NASA Astrophysics Data System (ADS)

    Szadkowski, Zbigniew; Szadkowska, Anna

    2014-12-01

    Experiments which show coherent radio emission from extensive air showers induced by ultra-high-energy cosmic rays are designed for a detailed study of the development of the electromagnetic part of air showers. Radio detectors can operate with 100 % up time as, e.g., surface detectors based on water-Cherenkov tanks. They are being developed for ground-based experiments (e.g., the Pierre Auger Observatory) as another type of air-shower detector in addition to fluorescence detectors, which operate with only ˜10 % of duty on dark nights. The radio signals from air showers are caused by coherent emission from geomagnetic radiation and charge-excess processes. The self-triggers in radio detectors currently in use often generate a dense stream of data, which is analyzed afterwards. Huge amounts of registered data require significant manpower for off-line analysis. Improvement of trigger efficiency is a relevant factor. The wavelet trigger, which investigates on-line the power of radio signals (˜ V2/ R), is promising; however, it requires some improvements with respect to current designs. In this work, Morlet wavelets with various scaling factors were used for an analysis of real data from the Auger Engineering Radio Array and for optimization of the utilization of the resources in an FPGA. The wavelet analysis showed that the power of events is concentrated mostly in a limited range of the frequency spectrum (consistent with a range imposed by the input analog band-pass filter). However, we found several events with suspicious spectral characteristics, where the signal power is spread over the full band-width sampled by a 200 MHz digitizer with significant contribution of very high and very low frequencies. These events may not originate from cosmic ray showers but could be the result of human contamination. The engine of the wavelet analysis can be implemented in the modern powerful FPGAs and can remove suspicious events on-line to reduce the trigger rate.

  7. A pattern recognition mezzanine based on associative memory and FPGA technology for L1 track triggering at HL-LHC

    NASA Astrophysics Data System (ADS)

    Alunni, L.; Biesuz, N.; Bilei, G. M.; Citraro, S.; Crescioli, F.; Fanò, L.; Fedi, G.; Magalotti, D.; Magazzù, G.; Servoli, L.; Storchi, L.; Palla, F.; Placidi, P.; Papi, A.; Piadyk, Y.; Rossi, E.; Spiezia, A.

    2016-07-01

    The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

  8. Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor

    NASA Astrophysics Data System (ADS)

    Anders, G.; Bertelsen, H.; Boisen, A.; Childers, T.; Dam, M.; Ellis, N.; Farthouat, P.; Gabaldon Ruiz, C.; Ghibaudi, M.; Gorini, B.; Haas, S.; Kaneda, M.; Ohm, C.; Silva Oliveira, M.; Pauly, T.; Pöttgen, R.; Schmieden, K.; Spiwoks, R.; Xella, S.

    2014-01-01

    The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.

  9. The Level 0 Trigger Processor for the NA62 experiment

    NASA Astrophysics Data System (ADS)

    Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.; Soldi, D.

    2016-07-01

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  10. The CMS high level trigger

    NASA Astrophysics Data System (ADS)

    Gori, Valentina

    2014-05-01

    The CMS experiment has been designed with a 2-level trigger system: the Level 1 Trigger, implemented on custom-designed electronics, and the High Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. A software trigger system requires a tradeoff between the complexity of the algorithms running on the available computing power, the sustainable output rate, and the selection efficiency. Here we will present the performance of the main triggers used during the 2012 data taking, ranging from simpler single-object selections to more complex algorithms combining different objects, and applying analysis-level reconstruction and selection. We will discuss the optimisation of the triggers and the specific techniques to cope with the increasing LHC pile-up, reducing its impact on the physics performance.

  11. The CMS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Trocino, Daniele

    2014-06-01

    The CMS experiment has been designed with a two-level trigger system: the Level-1 Trigger, implemented in custom-designed electronics, and the High-Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. A software trigger system requires a tradeoff between the complexity of the algorithms running with the available computing power, the sustainable output rate, and the selection efficiency. We present the performance of the main triggers used during the 2012 data taking, ranging from simple single-object selections to more complex algorithms combining different objects, and applying analysis-level reconstruction and selection. We discuss the optimisation of the trigger and the specific techniques to cope with the increasing LHC pile-up, reducing its impact on the physics performance.

  12. FPGA-based trigger system for the LUX dark matter experiment

    NASA Astrophysics Data System (ADS)

    Akerib, D. S.; Araújo, H. M.; Bai, X.; Bailey, A. J.; Balajthy, J.; Beltrame, P.; Bernard, E. P.; Bernstein, A.; Biesiadzinski, T. P.; Boulton, E. M.; Bradley, A.; Bramante, R.; Cahn, S. B.; Carmona-Benitez, M. C.; Chan, C.; Chapman, J. J.; Chiller, A. A.; Chiller, C.; Currie, A.; Cutter, J. E.; Davison, T. J. R.; de Viveiros, L.; Dobi, A.; Dobson, J. E. Y.; Druszkiewicz, E.; Edwards, B. N.; Faham, C. H.; Fiorucci, S.; Gaitskell, R. J.; Gehman, V. M.; Ghag, C.; Gibson, K. R.; Gilchriese, M. G. D.; Hall, C. R.; Hanhardt, M.; Haselschwardt, S. J.; Hertel, S. A.; Hogan, D. P.; Horn, M.; Huang, D. Q.; Ignarra, C. M.; Ihm, M.; Jacobsen, R. G.; Ji, W.; Kazkaz, K.; Khaitan, D.; Knoche, R.; Larsen, N. A.; Lee, C.; Lenardo, B. G.; Lesko, K. T.; Lindote, A.; Lopes, M. I.; Malling, D. C.; Manalaysay, A. G.; Mannino, R. L.; Marzioni, M. F.; McKinsey, D. N.; Mei, D.-M.; Mock, J.; Moongweluwan, M.; Morad, J. A.; Murphy, A. St. J.; Nehrkorn, C.; Nelson, H. N.; Neves, F.; O`Sullivan, K.; Oliver-Mallory, K. C.; Ott, R. A.; Palladino, K. J.; Pangilinan, M.; Pease, E. K.; Phelps, P.; Reichhart, L.; Rhyne, C.; Shaw, S.; Shutt, T. A.; Silva, C.; Skulski, W.; Solovov, V. N.; Sorensen, P.; Stephenson, S.; Sumner, T. J.; Szydagis, M.; Taylor, D. J.; Taylor, W.; Tennyson, B. P.; Terman, P. A.; Tiedt, D. R.; To, W. H.; Tripathi, M.; Tvrznikova, L.; Uvarov, S.; Verbus, J. R.; Webb, R. C.; White, J. T.; Whitis, T. J.; Witherell, M. S.; Wolfs, F. L. H.; Yin, J.; Young, S. K.; Zhang, C.

    2016-05-01

    LUX is a two-phase (liquid/gas) xenon time projection chamber designed to detect nuclear recoils resulting from interactions with dark matter particles. Signals from the detector are processed with an FPGA-based digital trigger system that analyzes the incoming data in real-time, with just a few microsecond latency. The system enables first pass selection of events of interest based on their pulse shape characteristics and 3D localization of the interactions. It has been shown to be > 99 % efficient in triggering on S2 signals induced by only few extracted liquid electrons. It is continuously and reliably operating since its full underground deployment in early 2013. This document is an overview of the systems capabilities, its inner workings, and its performance.

  13. Implementation of FPGA-based level-1 tracking at CMS for the HL-LHC

    NASA Astrophysics Data System (ADS)

    Chaves, J.

    2014-10-01

    A new approach for track reconstruction is presented to be used in the all-hardware first level of the CMS trigger. The application of the approach is intended for the upgraded all-silicon tracker, which is to be installed for the High Luminosity era of the LHC (HL-LHC). The upgraded LHC machine is expected to deliver a luminosity on the order of 5 × 1034 cm-2s-1. This expected luminosity means there would be about 125 pileup events in each bunch crossing at a frequency of 40 MHz. To keep the CMS trigger rate at a manageable level under these conditions, it is necessary to make quick decisions on the events that will be processed. The timing estimates for the algorithm are expected to be below 5 μs, well within the requirements of the L1 trigger at CMS for track identification. The algorithm is integer-based, allowing it to be implemented on an FPGA. Currently we are working on a demonstrator hardware implementation using a Xilinx Virtex 6 FPGA. Results from simulations in C++ and Verilog are presented to show the algorithm performance in terms of data throughput and parameter resolution.

  14. The CMS Level-1 Trigger Barrel Track Finder

    NASA Astrophysics Data System (ADS)

    Ero, J.; Evangelou, I.; Flouris, G.; Foudas, C.; Guiducci, L.; Loukas, N.; Manthos, N.; Papadopoulos, I.; Paradas, E.; Sotiropoulos, S.; Sphicas, P.; Triossi, A.; Wulz, C.

    2016-03-01

    The design and performance of the upgraded CMS Level-1 Trigger Barrel Muon Track Finder (BMTF) is presented. Monte Carlo simulation data as well as cosmic ray data from a CMS muon detector slice test have been used to study in detail the performance of the new track finder. The design architecture is based on twelve MP7 cards each of which uses a Xilinx Virtex-7 FPGA and can receive and transmit data at 10 Gbps from 72 input and 72 output fibers. According to the CMS Trigger Upgrade TDR the BMTF receives trigger primitive data which are computed using both RPC and DT data and transmits data from a number of muon candidates to the upgraded Global Muon Trigger. Results from detailed studies of comparisons between the BMTF algorithm results and the results of a C++ emulator are also presented. The new BMTF will be commissioned for data taking in 2016.

  15. 4th generation of the 1st level surface detector trigger in the Pierre Auger Observator

    NASA Astrophysics Data System (ADS)

    Szadkowski, Z.

    The proposal of a new 4th generation of the Front-End with the advanced 1st level triggers for the Infill Array of the Pierre Auger Observatory and for the Auger North is described. Newest FPGA chips offer much higher capacity of logic registers and memories, as well as DSP blocks. The calibration channel, previously supported by an external dual-port RAM, has been fully implemented into FPGA chip, through a large internal memory. In turn DSP blocks allowed on implementation of much more sophisticated spectral trigger algorithms. A single chip simplified board design, newer architecture of FPGA reduced resouces utilization and power consumption. Higher sampling in the new Front- End in comparison with previous 40 MHz designs as well as free resources for new detection algotithms can be a good platform for CR radio detection technique at Auger enhancing a duty cycle for the detection of UHECR’s.

  16. An FPGA-based trigger for the phase II of the MEG experiment

    NASA Astrophysics Data System (ADS)

    Baldini, A.; Bemporad, C.; Cei, F.; Galli, L.; Grassi, M.; Morsani, F.; Nicolò, D.; Ritt, S.; Venturini, M.

    2016-07-01

    For the phase II of MEG, we are going to develop a combined trigger and DAQ system. Here we focus on the former side, which operates an on-line reconstruction of detector signals and event selection within 450 μs from event occurrence. Trigger concentrator boards (TCB) are under development to gather data from different crates, each connected to a set of detector channels, to accomplish higher-level algorithms to issue a trigger in the case of a candidate signal event. We describe the major features of the new system, in comparison with phase I, as well as its performances in terms of selection efficiency and background rejection.

  17. The ALICE High Level Trigger: status and plans

    NASA Astrophysics Data System (ADS)

    Krzewicki, Mikolaj; Rohr, David; Gorbunov, Sergey; Breitner, Timo; Lehrbach, Johannes; Lindenstruth, Volker; Berzano, Dario

    2015-12-01

    The ALICE High Level Trigger (HLT) is an online reconstruction, triggering and data compression system used in the ALICE experiment at CERN. Unique among the LHC experiments, it extensively uses modern coprocessor technologies like general purpose graphic processing units (GPGPU) and field programmable gate arrays (FPGA) in the data flow. Realtime data compression is performed using a cluster finder algorithm implemented on FPGA boards. These data, instead of raw clusters, are used in the subsequent processing and storage, resulting in a compression factor of around 4. Track finding is performed using a cellular automaton and a Kalman filter algorithm on GPGPU hardware, where both CUDA and OpenCL technologies can be used interchangeably. The ALICE upgrade requires further development of online concepts to include detector calibration and stronger data compression. The current HLT farm will be used as a test bed for online calibration and both synchronous and asynchronous processing frameworks already before the upgrade, during Run 2. For opportunistic use as a Grid computing site during periods of inactivity of the experiment a virtualisation based setup is deployed.

  18. CDF level 2 trigger upgrade

    SciTech Connect

    Anikeev, K.; Bogdan, M.; DeMaat, R.; Fedorko, W.; Frisch, H.; Hahn, K.; Hakala, M.; Keener, P.; Kim, Y.; Kroll, J.; Kwang, S.; Lewis, J.; Lin, C.; Liu, T.; Marjamaa, F.; Mansikkala, T.; Neu, C.; Pitkanen, S.; Reisert, B.; Rusu, V.; Sanders, H.; /Fermilab /Chicago U. /Pennsylvania U.

    2006-01-01

    We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.

  19. Hash sorter - firmware implementation and an application for the Fermilab BTeV level 1 trigger system

    SciTech Connect

    Jinyuan Wu et al.

    2003-11-05

    A hardware hash sorter for the Fermilab BTeV Level 1 trigger system will be presented. The has sorter examines track-segment data before the data are sent to a system comprised of 2500 Level 1 processors, and rearranges the data into bins based on the slope of track segments. They have found that by using the rearranged data, processing time is significantly reduced allowing the total number of processors required for the Level 1 trigger system to be reduced. The hash sorter can be implemented in an FPGA that is already included as part of the design of the trigger system. Hash sorting has potential applications in a broad area in trigger and DAQ systems. It is a simple O(n) process and is suitable for FPGA implementation. Several implementation strategies will also be discussed in this document.

  20. The CDF LEVEL3 trigger

    SciTech Connect

    Carroll, T.; Joshi, U.; Auchincloss, P.

    1989-04-01

    CDF is currently taking data at a luminosity of 10{sup 30} cm{sup -2} sec{sup -1} using a four level event filtering scheme. The fourth level, LEVEL3, uses ACP (Fermilab`s Advanced Computer Program) designed 32 bit VME based parallel processors (1) capable of executing algorithms written in FORTRAN. LEVEL3 currently rejects about 50% of the events.

  1. The ATLAS level 2 trigger supervisor.

    SciTech Connect

    Abolins, M.; Blair, R. E.; Dawson, J. W.; Owen, D.; Pope, B. G.; Schlereth, J. L.; Weber dos Santos, R.

    1997-04-03

    This paper presents an overview of the hardware and software proposed for the ATLAS level 2 Trigger ROI Builder/Supervisor. The essential requirements of this system are that it operate at the design Level 1 Trigger rate of 100kHz and that it support the technical requirements of the architectures suggested for the ATLAS Level 2 Trigger. Commercial equipment and software support are used to the maximum extent possible, with support from dedicated hardware. Timing requirements and latencies are discussed and simulation results are presented.

  2. Software-based high-level synthesis design of FPGA beamformers for synthetic aperture imaging.

    PubMed

    Amaro, Joao; Yiu, Billy Y S; Falcao, Gabriel; Gomes, Marco A C; Yu, Alfred C H

    2015-05-01

    Field-programmable gate arrays (FPGAs) can potentially be configured as beamforming platforms for ultrasound imaging, but a long design time and skilled expertise in hardware programming are typically required. In this article, we present a novel approach to the efficient design of FPGA beamformers for synthetic aperture (SA) imaging via the use of software-based high-level synthesis techniques. Software kernels (coded in OpenCL) were first developed to stage-wise handle SA beamforming operations, and their corresponding FPGA logic circuitry was emulated through a high-level synthesis framework. After design space analysis, the fine-tuned OpenCL kernels were compiled into register transfer level descriptions to configure an FPGA as a beamformer module. The processing performance of this beamformer was assessed through a series of offline emulation experiments that sought to derive beamformed images from SA channel-domain raw data (40-MHz sampling rate, 12 bit resolution). With 128 channels, our FPGA-based SA beamformer can achieve 41 frames per second (fps) processing throughput (3.44 × 10(8) pixels per second for frame size of 256 × 256 pixels) at 31.5 W power consumption (1.30 fps/W power efficiency). It utilized 86.9% of the FPGA fabric and operated at a 196.5 MHz clock frequency (after optimization). Based on these findings, we anticipate that FPGA and high-level synthesis can together foster rapid prototyping of real-time ultrasound processor modules at low power consumption budgets.

  3. Software-based high-level synthesis design of FPGA beamformers for synthetic aperture imaging.

    PubMed

    Amaro, Joao; Yiu, Billy Y S; Falcao, Gabriel; Gomes, Marco A C; Yu, Alfred C H

    2015-05-01

    Field-programmable gate arrays (FPGAs) can potentially be configured as beamforming platforms for ultrasound imaging, but a long design time and skilled expertise in hardware programming are typically required. In this article, we present a novel approach to the efficient design of FPGA beamformers for synthetic aperture (SA) imaging via the use of software-based high-level synthesis techniques. Software kernels (coded in OpenCL) were first developed to stage-wise handle SA beamforming operations, and their corresponding FPGA logic circuitry was emulated through a high-level synthesis framework. After design space analysis, the fine-tuned OpenCL kernels were compiled into register transfer level descriptions to configure an FPGA as a beamformer module. The processing performance of this beamformer was assessed through a series of offline emulation experiments that sought to derive beamformed images from SA channel-domain raw data (40-MHz sampling rate, 12 bit resolution). With 128 channels, our FPGA-based SA beamformer can achieve 41 frames per second (fps) processing throughput (3.44 × 10(8) pixels per second for frame size of 256 × 256 pixels) at 31.5 W power consumption (1.30 fps/W power efficiency). It utilized 86.9% of the FPGA fabric and operated at a 196.5 MHz clock frequency (after optimization). Based on these findings, we anticipate that FPGA and high-level synthesis can together foster rapid prototyping of real-time ultrasound processor modules at low power consumption budgets. PMID:25965680

  4. Commissioning of the CMS High Level Trigger

    SciTech Connect

    Agostino, Lorenzo; et al.

    2009-08-01

    The CMS experiment will collect data from the proton-proton collisions delivered by the Large Hadron Collider (LHC) at a centre-of-mass energy up to 14 TeV. The CMS trigger system is designed to cope with unprecedented luminosities and LHC bunch-crossing rates up to 40 MHz. The unique CMS trigger architecture only employs two trigger levels. The Level-1 trigger is implemented using custom electronics, while the High Level Trigger (HLT) is based on software algorithms running on a large cluster of commercial processors, the Event Filter Farm. We present the major functionalities of the CMS High Level Trigger system as of the starting of LHC beams operations in September 2008. The validation of the HLT system in the online environment with Monte Carlo simulated data and its commissioning during cosmic rays data taking campaigns are discussed in detail. We conclude with the description of the HLT operations with the first circulating LHC beams before the incident occurred the 19th September 2008.

  5. BTeV level 1 vertex trigger

    SciTech Connect

    Michael H.L.S. Wang

    2001-11-05

    BTeV is a B-physics experiment that expects to begin collecting data at the C0 interaction region of the Fermilab Tevatron in the year 2006. Its primary goal is to achieve unprecedented levels of sensitivity in the study of CP violation, mixing, and rare decays in b and c quark systems. In order to realize this, it will employ a state-of-the-art first-level vertex trigger (Level 1) that will look at every beam crossing to identify detached secondary vertices that provide evidence for heavy quark decays. This talk will briefly describe the BTeV detector and trigger, focus on the software and hardware aspects of the Level 1 vertex trigger, and describe work currently being done in these areas.

  6. The Zeus calorimeter first level trigger

    SciTech Connect

    Smith, W.J.

    1989-04-01

    The design of the Zeus Detector Calorimeter Level Trigger is presented. The Zeus detector is being built for operation at HERA, a new storage ring that will provide collisions between 820 GeV protons and 30 GeV electrons in 1990. The calorimeter is made of depleted uranium plates and plastic scintillator read out by wavelength shifter bars into 12,864 photomultiplier tubes. These signals are combined into 974 trigger towers with separate electromagnetic and hadronic sums. The calorimeter first level trigger is pipelined with a decision provided 5 {mu}sec after each beam crossing, occurring every 96 nsec. The trigger determines the total energy, the total transverse energy, the missing energy, and the energy and number of isolated electrons and muons. It also provides information on the number and energy of clusters. The trigger rate needs to be held to 1 kHz against a rate of proton-beam gas interactions of approximately 500 kHz. The summed trigger tower pulseheights are digitized by flash ADC`s. The digital values are linearized, stored and used for sums and pattern tests.

  7. A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

    NASA Astrophysics Data System (ADS)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

    2005-12-01

    We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC

  8. Performance of the CMS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Perrotta, Andrea

    2015-12-01

    The CMS experiment has been designed with a 2-level trigger system. The first level is implemented using custom-designed electronics. The second level is the so-called High Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. For Run II of the Large Hadron Collider, the increases in center-of-mass energy and luminosity will raise the event rate to a level challenging for the HLT algorithms. The increase in the number of interactions per bunch crossing, on average 25 in 2012, and expected to be around 40 in Run II, will be an additional complication. We present here the expected performance of the main triggers that will be used during the 2015 data taking campaign, paying particular attention to the new approaches that have been developed to cope with the challenges of the new run. This includes improvements in HLT electron and photon reconstruction as well as better performing muon triggers. We will also present the performance of the improved tracking and vertexing algorithms, discussing their impact on the b-tagging performance as well as on the jet and missing energy reconstruction.

  9. THE STAR LEVEL-3 TRIGGER SYSTEM.

    SciTech Connect

    LANGE, J.S.; ADLER, C.; BERGER, J.; DEMELLO, M.; FLIERL, D.; ET AL

    1999-11-15

    The STAR level-3 trigger is a MYRINET interconnected ALPHA processor farm, performing online tracking of N{sub track} {ge} 8000 particles (N{sub point} {le} 45 per track) with a design input rate of R=100 Hz. A large scale prototype system was tested in 12/99 with laser and cosmic particle events.

  10. The ZEUS calorimeter first level trigger

    SciTech Connect

    Foudas, C.; Dawson, J.; Krakauer, D.; Talaga, R.; Ali, I.; Behrens, B.; Fordham, C.; Goussiou, A.; Jaworski, M.; Lackey, J.

    1994-12-31

    The authors present results on the efficiency and performance of the ZEUS detector Calorimeter First Level Trigger (CFLT) using data taken during the 1993 HERA physics run. The CFLT is designed to process events in a digital pipeline applying pattern recognition algorithms and fast digital summation techniques in order to collect interesting physics events and reduce background from beam gas interactions. The total FLT efficiency was 98% for neutral current events and 85% for charged current events above Q{sup 2} of 10 GeV{sup 2}. The introduction of the isolated electron trigger increases the CFLT beam gas rejection by a factor of two.

  11. Level-2 Calorimeter Trigger Upgrade at CDF

    SciTech Connect

    Flanagan, G.U.; /Purdue U.

    2007-04-01

    The CDF Run II Level-2 calorimeter trigger is implemented in hardware and is based on an algorithm used in Run I. This system insured good performance at low luminosity obtained during the Tevatron Run II. However, as the Tevatron instantaneous luminosity increases, the limitations of the current system due to the algorithm start to become clear. In this paper, we will present an upgrade of the Level-2 calorimeter trigger system at CDF. The upgrade is based on the Pulsar board, a general purpose VME board developed at CDF and used for upgrading both the Level-2 tracking and the Level-2 global decision crate. This paper will describe the design, hardware and software implementation, as well as the advantages of this approach over the existing system.

  12. CMS High Level Trigger Timing Measurements

    NASA Astrophysics Data System (ADS)

    Richardson, Clint

    2015-12-01

    The two-level trigger system employed by CMS consists of the Level 1 (L1) Trigger, which is implemented using custom-built electronics, and the High Level Trigger (HLT), a farm of commercial CPUs running a streamlined version of the offline CMS reconstruction software. The operational L1 output rate of 100 kHz, together with the number of CPUs in the HLT farm, imposes a fundamental constraint on the amount of time available for the HLT to process events. Exceeding this limit impacts the experiment's ability to collect data efficiently. Hence, there is a critical need to characterize the performance of the HLT farm as well as the algorithms run prior to start up in order to ensure optimal data taking. Additional complications arise from the fact that the HLT farm consists of multiple generations of hardware and there can be subtleties in machine performance. We present our methods of measuring the timing performance of the CMS HLT, including the challenges of making such measurements. Results for the performance of various Intel Xeon architectures from 2009-2014 and different data taking scenarios are also presented.

  13. 16-point discrete Fourier transform based on the Radix-2 FFT algorithm implemented into cyclone FPGA as the UHECR trigger for horizontal air showers in the Pierre Auger Observatory

    NASA Astrophysics Data System (ADS)

    Szadkowski, Z.

    2006-05-01

    Extremely rare flux of UHERC requires sophisticated detection techniques. Standard methods oriented on the typical events may not be sensitive enough to capture rare events, crucial to fix a discrepancy in the current data or to confirm/reject some new hypothesis. Currently used triggers in water Cherenkov tanks in the Pierre Auger surface detector, which select events above some amplitude thresholds or investigate a length of traces are not optimized to the horizontal and very inclined showers, interesting as potentially generated by neutrinos. Those showers could be triggered using their signatures: i.e. a curvature of the shower front, transformed on the rise time of traces or muon component giving early peak for "old" showers. Currently available powerful and cost-effective FPGAs provide sufficient resources to implement new triggers not available in the past. The paper describes the implementation proposal of 16-point discrete Fourier transform based on the Radix-2 FFT algorithm into Altera Cyclone FPGA, used in the 3rd generation of the surface detector trigger. All complex coefficients are calculated online in heavy pipelined routines. The register performance ˜200 MHz and relatively low resources occupancy ˜2000 logic elements/channel for 10-bit resolution provide a powerful tool to trigger the events on the traces characteristic in the frequency domain. The FFT code has been successively merged to the code of the 1st surface selector level trigger of the Pierre Auger Observatory and is planned to be tested in real pampas environment.

  14. The ALICE high-level trigger read-out upgrade for LHC Run 2

    NASA Astrophysics Data System (ADS)

    Engel, H.; Alt, T.; Breitner, T.; Gomez Ramirez, A.; Kollegger, T.; Krzewicki, M.; Lehrbach, J.; Rohr, D.; Kebschull, U.

    2016-01-01

    The ALICE experiment uses an optical read-out protocol called Detector Data Link (DDL) to connect the detectors with the computing clusters of Data Acquisition (DAQ) and High-Level Trigger (HLT). The interfaces of the clusters to these optical links are realized with FPGA-based PCI-Express boards. The High-Level Trigger is a computing cluster dedicated to the online reconstruction and compression of experimental data. It uses a combination of CPU, GPU and FPGA processing. For Run 2, the HLT has replaced all of its previous interface boards with the Common Read-Out Receiver Card (C-RORC) to enable read-out of detectors at high link rates and to extend the pre-processing capabilities of the cluster. The new hardware also comes with an increased link density that reduces the number of boards required. A modular firmware approach allows different processing and transport tasks to be built from the same source tree. A hardware pre-processing core includes cluster finding already in the C-RORC firmware. State of the art interfaces and memory allocation schemes enable a transparent integration of the C-RORC into the existing HLT software infrastructure. Common cluster management and monitoring frameworks are used to also handle C-RORC metrics. The C-RORC is in use in the clusters of ALICE DAQ and HLT since the start of LHC Run 2.

  15. NaNet-10: a 10GbE network interface card for the GPU-based low-level trigger of the NA62 RICH detector.

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Fiorini, M.; Frezza, O.; Lonardo, A.; Lamanna, G.; Lo Cicero, F.; Martinelli, M.; Neri, I.; Paolucci, P. S.; Pastorelli, E.; Piandani, R.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.; Tosoratto, L.; Vicini, P.

    2016-03-01

    A GPU-based low level (L0) trigger is currently integrated in the experimental setup of the RICH detector of the NA62 experiment to assess the feasibility of building more refined physics-related trigger primitives and thus improve the trigger discriminating power. To ensure the real-time operation of the system, a dedicated data transport mechanism has been implemented: an FPGA-based Network Interface Card (NaNet-10) receives data from detectors and forwards them with low, predictable latency to the memory of the GPU performing the trigger algorithms. Results of the ring-shaped hit patterns reconstruction will be reported and discussed.

  16. Global Trigger Upgrade firmware architecture for the level-1 Trigger of the CMS experiment

    NASA Astrophysics Data System (ADS)

    Rahbaran, B.; Arnold, B.; Bergauer, H.; Wittmann, J.; Matsushita, T.

    2015-02-01

    The Global Trigger (GT) is the final step of the CMS Level-1 Trigger and implements the ``menu'' of triggers, which is a set of selection requirements applied to the final list of objects (such as muons, electrons or jets) to trigger the readout of the detector and serve as basis for further calculations by the High Level Trigger. Operational experience in developing trigger menus from the first LHC run has shown that the requirements increased as the luminosity and pile-up increased. The new GT (μGT) is designed based on Xilinx Virtex-7 FPGAs, which combine unsurpassed flexibility with regard to scalability and high robustness. Furthermore, a custom board which receives signals from legacy electronics and basic binary inputs from less complex trigger sources is presented. Additionally, this paper describes the architecture of a distributed testing framework and the Trigger Menu Editor.

  17. Upgrade of the ATLAS Level-1 Trigger with event topology information

    NASA Astrophysics Data System (ADS)

    Simioni, E.; Artz, S.; Bauβ, B.; Büscher, V.; Jakobi, K.; Kaluza, A.; Kahra, C.; Palka, M.; Reiβ, A.; Schäffer, J.; Schäfer, U.; Schulte, A.; Simon, M.; Tapprogge, S.; Vogel, A.; Zinser, M.

    2015-12-01

    The Large Hadron Collider (LHC) in 2015 will collide proton beams with increased luminosity from 1034 up to 3 × 1034cm-2s-1. ATLAS is an LHC experiment designed to measure decay properties of high energetic particles produced in the protons collisions. The higher luminosity places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events with valuable physics meaning. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than 2.5µs. It is composed of the Calorimeter Trigger (L1Calo), the Muon Trigger (L1Muon) and the Central Trigger Processor (CTP). By 2015, there will be a new electronics element in the chain: the Topological Processor System (L1Topo system). The L1Topo system consist of a single AdvancedTCA shelf equipped with three L1Topo processor blades. It will make it possible to use detailed information from L1Calo and L1Muon processed in individual state-of-the-art FPGA processors. This allows the determination of angles between jets and/or leptons and calculates kinematic variables based on lists of selected/sorted objects. The system is designed to receive and process up to 6Tb/s of real time data. The paper reports the relevant upgrades of the Level-1 trigger with focus on the topological processor design and commissioning.

  18. The CDF level 2 calorimetric trigger upgrade

    SciTech Connect

    Bhatti, A.; Canepa, A.; Casarsa, M.; Convery, M.; Cortiana, G.; Dell'Orso, M.; Donati, S.; Flanagan, G.; Frisch, H.; Fukun, T.; Krop, D.; /Chicago U., EFI /INFN, Pisa /Pisa U. /Pisa, Scuola Normale Superiore

    2009-01-01

    CDF II upgraded the calorimeter trigger to cope with the higher detector occupancy due to the increased Tevatron instantaneous luminosity ({approx} 2.8 x 10{sup 32} cm{sup -2} s{sup -1}). While the original system was implemented in custom hardware and provided to the L2 trigger a limited-quality jet clustering performed using a reduced resolution measurement of the transverse energy in the calorimeter trigger towers, the upgraded system provides offline-quality jet reconstruction of the full resolution calorimeter data. This allows to keep better under control the dependence of the trigger rates on the instantaneous luminosity and to improve the efficiency and purity of the trigger selections. The upgraded calorimeter trigger uses the general purpose VME board Pulsar, developed at CDF II and already widely used to upgrade the L2 tracking and L2 decision systems. A battery of Pulsars is used to merge and send the calorimeter data to the L2 CPUs, where software-implemented algorithms perform offline-like clustering. In this paper we review the design and the performance of the upgraded system.

  19. 76 FR 31295 - WTO Agricultural Safeguard Trigger Levels

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-05-31

    ... Secretary of Agriculture in Presidential Proclamation No. 6763, dated December 23, 1994, 60 FR 1005 (Jan. 4... Trigger Levels, published in the Federal Register at 60 FR 427 (Jan. 4, 1995). Notice: As provided in... Round Agricultural Safeguard Trigger Levels published in the Federal Register, at 60 FR 427 (Jan....

  20. CROC FPGA Firmware

    SciTech Connect

    2009-12-01

    The CROC FPGA firmware code controls the operation of CROC hardware primarily deterinining the location of neutron events and discriminating against false trigger by examining the output of multiple analog comparators. A number of stoical algorithms are encode within the firmware to achieve reliable operation. Other communication and control functions are also part of the firmware.

  1. The upgrade of the ATLAS first-level calorimeter trigger

    NASA Astrophysics Data System (ADS)

    Yamamoto, Shimpei

    2016-07-01

    The first-level calorimeter trigger (L1Calo) had operated successfully through the first data taking phase of the ATLAS experiment at the CERN Large Hadron Collider. Towards forthcoming LHC runs, a series of upgrades is planned for L1Calo to face new challenges posed by the upcoming increases of the beam energy and the luminosity. This paper reviews the ATLAS L1Calo trigger upgrade project that introduces new architectures for the liquid-argon calorimeter trigger readout and the L1Calo trigger processing system.

  2. NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

    NASA Astrophysics Data System (ADS)

    Ammendola, Roberto; Biagioni, Andrea; Fantechi, Riccardo; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Lonardo, Alessandro; Stanislao Paolucci, Pier; Pantaleo, Felice; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

    2014-06-01

    We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  3. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    NASA Astrophysics Data System (ADS)

    Glatzer, Julian

    2015-12-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of two with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the factor of two increase in the number of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to three different subdetector combinations. An overview of the operational software framework of the L1CT system with particular emphasis on the configuration, controls and monitoring aspects is given. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition system. Trigger and dead-time rates are monitored coherently at all stages of processing and are logged by the online computing system for physics analysis, data quality assurance and operational debugging. In addition, the synchronisation of trigger inputs is watched based on bunch-by-bunch trigger information. Several software tools allow for efficient display of the relevant information in the control room in a way useful for shifters and experts. The design of the framework aims at reliability, flexibility, and robustness of the system and takes into account the operational experience gained during Run 1. The Level-1 Central Trigger was successfully operated with high efficiency during the cosmic-ray, beam-splash and first Run 2 data taking with the full ATLAS detector.

  4. Level-3 Calorimetric Resolution available for the Level-1 and Level-2 CDF Triggers

    SciTech Connect

    Canepa, Anadi; Casarsa, M.; Cavaliere, V.; Cortiana, Giorgio; Donati, S.; Flanagan, G.; Greco, V.; Giannetti, P.; Frisch, H.; Krop, D.; Liu, T.; /Fermilab /INFN, Pisa

    2008-06-01

    As the Tevatron luminosity increases sophisticated selections are required to be efficient in selecting rare events among a very huge background. To cope with this problem, CDF has pushed the offline calorimeter algorithm reconstruction resolution up to Level 2 and, when possible, even up to Level 1, increasing efficiency and, at the same time, keeping under control the rates. The CDF Run II Level 2 calorimeter trigger is implemented in hardware and is based on a simple algorithm that was used in Run I. This system has worked well for Run II at low luminosity. As the Tevatron instantaneous luminosity increases, the limitation due to this simple algorithm starts to become clear: some of the most important jet and MET (Missing ET) related triggers have large growth terms in cross section at higher luminosity. In this paper, we present an upgrade of the Level 2 Calorimeter system which makes the calorimeter trigger tower information available directly to a CPU allowing more sophisticated algorithms to be implemented in software. Both Level 2 jets and MET can be made nearly equivalent to offline quality, thus significantly improving the performance and flexibility of the jet and MET related triggers. However in order to fully take advantage of the new L2 triggering capabilities having at Level 1 the same L2 MET resolution is necessary. The new Level-1 MET resolution is calculated by dedicated hardware. This paper describes the design, the hardware and software implementation and the performance of the upgraded calorimeter trigger system both at Level 2 and Level 1.

  5. The ATLAS Data Acquisition and High Level Trigger system

    NASA Astrophysics Data System (ADS)

    The ATLAS TDAQ Collaboration

    2016-06-01

    This paper describes the data acquisition and high level trigger system of the ATLAS experiment at the Large Hadron Collider at CERN, as deployed during Run 1. Data flow as well as control, configuration and monitoring aspects are addressed. An overview of the functionality of the system and of its performance is presented and design choices are discussed.

  6. FPGA Design Practices for I&C in Nuclear Power Plants

    SciTech Connect

    Bobrek, Miljko; Wood, Richard Thomas; Bouldin, Donald; Waterman, Michael E

    2009-01-01

    Safe FPGA design practices can be classified into three major groups covering board-level and FPGA logic-level design practices, FPGA design entry methods, and FPGA design methodology. This paper is presenting the most common hardware and software design practices that are acceptable in safety-critical FPGA systems. It also proposes an FPGA-specific design life cycle including design entry, FPGA synthesis, place and route, and validation and verification.

  7. A massively parallel track-finding system for the LEVEL 2 trigger in the CLAS detector at CEBAF

    SciTech Connect

    Doughty, D.C. Jr.; Collins, P.; Lemon, S. ); Bonneau, P. )

    1994-02-01

    The track segment finding subsystem of the LEVEL 2 trigger in the CLAS detector has been designed and prototyped. Track segments will be found in the 35,076 wires of the drift chambers using a massively parallel array of 768 Xilinx XC-4005 FPGA's. These FPGA's are located on daughter cards attached to the front-end boards distributed around the detector. Each chip is responsible for finding tracks passing through a 4 x 6 slice of an axial superlayer, and reports two segment found bits, one for each pair of cells. The algorithm used finds segments even when one or two layers or cells along the track is missing (this number is programmable), while being highly resistant to false segments arising from noise hits. Adjacent chips share data to find tracks crossing cell and board boundaries. For maximum speed, fully combinatorial logic is used inside each chip, with the result that all segments in the detector are found within 150 ns. Segment collection boards gather track segments from each axial superlayer and pass them via a high speed link to the segment linking subsystem in an additional 400 ns for typical events. The Xilinx chips are ram-based and therefore reprogrammable, allowing for future upgrades and algorithm enhancements.

  8. The LHCb Data Acquisition and High Level Trigger Processing Architecture

    NASA Astrophysics Data System (ADS)

    Frank, M.; Gaspar, C.; Jost, B.; Neufeld, N.

    2015-12-01

    The LHCb experiment at the LHC accelerator at CERN collects collisions of particle bunches at 40 MHz. After a first level of hardware trigger with an output rate of 1 MHz, the physically interesting collisions are selected by running dedicated trigger algorithms in the High Level Trigger (HLT) computing farm. This farm consists of up to roughly 25000 CPU cores in roughly 1750 physical nodes each equipped with up to 4 TB local storage space. This work describes the LHCb online system with an emphasis on the developments implemented during the current long shutdown (LS1). We will elaborate the architecture to treble the available CPU power of the HLT farm and the technicalities to determine and verify precise calibration and alignment constants which are fed to the HLT event selection procedure. We will describe how the constants are fed into a two stage HLT event selection facility using extensively the local disk buffering capabilities on the worker nodes. With the installed disk buffers, the CPU resources can be used during periods of up to ten days without beams. These periods in the past accounted to more than 70% of the total time.

  9. Implementation And Performance of the ATLAS Second Level Jet Trigger

    SciTech Connect

    Conde Muino, Patricia; Aracena, I.; Brelier, B.; Cranmer, K.; Delsart, P.A.; Dufour, M.A.; Eckweiler, S.; Ferland, J.; Idarraga, J.; Johns, K.; LeCompte, T.; Potter, C.; Robertson, S.; Santamarina Rios, C.; Segura, E.; Silverstein, D.; Vachon, B.; /McGill U.

    2011-11-09

    ATLAS is one of the four major LHC experiments, designed to cover a wide range of physics topics. In order to cope with a rate of 40MHz and 25 interactions per bunch crossing, the ATLAS trigger system is divided in three different levels. The jet selection starts at first level with dedicated processors that search for high E{sub T} hadronic energy depositions. At the LVL2, the jet signatures are verified with the execution of a dedicated, fast jet reconstruction algorithm, followed by a calibration algorithm. Three possible granularities have been proposed and are being evaluated: cell based (standard), energy sums calculated at each Front-End Board and the use of the LVL1 Trigger Towers. In this presentation, the design and implementation of the jet trigger of ATLAS will be discussed in detail, emphasazing the major difficulties of each selection step. The performance of the jet algorithm, including timing, efficiencies and rates will also be shown, with detailed comparisons of the different unpacking modes.

  10. Level-1 pixel based tracking trigger algorithm for LHC upgrade

    NASA Astrophysics Data System (ADS)

    Moon, C.-S.; Savoy-Navarro, A.

    2015-10-01

    The Pixel Detector is the innermost detector of the tracking system of the Compact Muon Solenoid (CMS) experiment at CERN Large Hadron Collider (LHC) . It precisely determines the interaction point (primary vertex) of the events and the possible secondary vertexes due to heavy flavours (b and c quarks); it is part of the overall tracking system that allows reconstructing the tracks of the charged particles in the events and combined with the magnetic field to measure their momentum. The pixel detector allows measuring the tracks in the region closest to the interaction point. The Level-1 (real-time) pixel based tracking trigger is a novel trigger system that is currently being studied for the LHC upgrade. An important goal is developing real-time track reconstruction algorithms able to cope with very high rates and high flux of data in a very harsh environment. The pixel detector has an especially crucial role in precisely identifying the primary vertex of the rare physics events from the large pile-up (PU) of events. The goal of adding the pixel information already at the real-time level of the selection is to help reducing the total level-1 trigger rate while keeping an high selection capability. This is quite an innovative and challenging objective for the experiments upgrade for the High Luminosity LHC (HL-LHC) . The special case here addressed is the CMS experiment. This document describes exercises focusing on the development of a fast pixel track reconstruction where the pixel track matches with a Level-1 electron object using a ROOT-based simulation framework.

  11. Run 2 upgrades to the CMS Level-1 calorimeter trigger

    NASA Astrophysics Data System (ADS)

    Kreis, B.; Berryhill, J.; Cavanaugh, R.; Mishra, K.; Rivera, R.; Uplegger, L.; Apanasevich, L.; Zhang, J.; Marrouche, J.; Wardle, N.; Aggleton, R.; Ball, F.; Brooke, J.; Newbold, D.; Paramesvaran, S.; Smith, D.; Baber, M.; Bundock, A.; Citron, M.; Elwood, A.; Hall, G.; Iles, G.; Laner, C.; Penning, B.; Rose, A.; Tapper, A.; Foudas, C.; Beaudette, F.; Cadamuro, L.; Mastrolorenzo, L.; Romanteau, T.; Sauvan, J. B.; Strebler, T.; Zabi, A.; Barbieri, R.; Cali, I. A.; Innocenti, G. M.; Lee, Y.-J.; Roland, C.; Wyslouch, B.; Guilbaud, M.; Li, W.; Northup, M.; Tran, B.; Durkin, T.; Harder, K.; Harper, S.; Shepherd-Themistocleous, C.; Thea, A.; Williams, T.; Cepeda, M.; Dasu, S.; Dodd, L.; Forbes, R.; Gorski, T.; Klabbers, P.; Levine, A.; Ojalvo, I.; Ruggles, T.; Smith, N.; Smith, W.; Svetek, A.; Tikalsky, J.; Vicente, M.

    2016-01-01

    The CMS Level-1 calorimeter trigger is being upgraded in two stages to maintain performance as the LHC increases pile-up and instantaneous luminosity in its second run. In the first stage, improved algorithms including event-by-event pile-up corrections are used. New algorithms for heavy ion running have also been developed. In the second stage, higher granularity inputs and a time-multiplexed approach allow for improved position and energy resolution. Data processing in both stages of the upgrade is performed with new, Xilinx Virtex-7 based AMC cards.

  12. Reduction of Ribosome Level Triggers Flocculation of Fission Yeast Cells

    PubMed Central

    Li, Rongpeng; Li, Xuesong; Sun, Lei; Chen, Feifei; Liu, Zhenxing; Gu, Yuyu; Gong, Xiaoyan; Liu, Zhonghua; Wei, Hua; Huang, Ying

    2013-01-01

    Deletion of ribosomal protein L32 genes resulted in a nonsexual flocculation of fission yeast. Nonsexual flocculation also occurred when two other ribosomal protein genes, rpl21-2 and rpl9-2, were deleted. However, deletion of two nonribosomal protein genes, mpg and fbp, did not cause flocculation. Overall transcript levels of rpl32 in rpl32-1Δ and rpl32-2Δ cells were reduced by 35.9% and 46.9%, respectively, and overall ribosome levels in rpl32-1Δ and rpl32-2Δ cells dropped 31.1% and 27.8%, respectively, compared to wild-type cells. Interestingly, ribosome protein expression levels and ribosome levels were also reduced greatly in sexually flocculating diploid YHL6381/WT (h+/h−) cells compared to a mixture of YHL6381 (h+) and WT (h−) nonflocculating haploid cells. Transcriptome analysis indicated that the reduction of ribosomal levels in sexual flocculating cells was caused by more-extensive suppression of ribosomal biosynthesis gene expression, while the reduction of ribosomal levels caused by deleting ribosomal protein genes in nonsexual flocculating cells was due to an imbalance between ribosomal proteins. We propose that once the reduction of ribosomal levels is below a certain threshold value, flocculation is triggered. PMID:23355005

  13. Can increased atmospheric CO2 levels trigger a runaway greenhouse?

    PubMed

    Ramirez, Ramses M; Kopparapu, Ravi Kumar; Lindner, Valerie; Kasting, James F

    2014-08-01

    Recent one-dimensional (globally averaged) climate model calculations by Goldblatt et al. (2013) suggest that increased atmospheric CO(2) could conceivably trigger a runaway greenhouse on present Earth if CO(2) concentrations were approximately 100 times higher than they are today. The new prediction runs contrary to previous calculations by Kasting and Ackerman (1986), which indicated that CO(2) increases could not trigger a runaway, even at Venus-like CO(2) concentrations. Goldblatt et al. argued that this different behavior is a consequence of updated absorption coefficients for H(2)O that make a runaway more likely. Here, we use a 1-D climate model with similar, up-to-date absorption coefficients, but employ a different methodology, to show that the older result is probably still valid, although our model nearly runs away at ∼12 preindustrial atmospheric levels of CO(2) when we use the most alarmist assumptions possible. However, we argue that Earth's real climate is probably stable given more realistic assumptions, although 3-D climate models will be required to verify this result. Potential CO(2) increases from fossil fuel burning are somewhat smaller than this, 10-fold or less, but such increases could still cause sufficient warming to make much of the planet uninhabitable by humans.

  14. Can increased atmospheric CO2 levels trigger a runaway greenhouse?

    PubMed

    Ramirez, Ramses M; Kopparapu, Ravi Kumar; Lindner, Valerie; Kasting, James F

    2014-08-01

    Recent one-dimensional (globally averaged) climate model calculations by Goldblatt et al. (2013) suggest that increased atmospheric CO(2) could conceivably trigger a runaway greenhouse on present Earth if CO(2) concentrations were approximately 100 times higher than they are today. The new prediction runs contrary to previous calculations by Kasting and Ackerman (1986), which indicated that CO(2) increases could not trigger a runaway, even at Venus-like CO(2) concentrations. Goldblatt et al. argued that this different behavior is a consequence of updated absorption coefficients for H(2)O that make a runaway more likely. Here, we use a 1-D climate model with similar, up-to-date absorption coefficients, but employ a different methodology, to show that the older result is probably still valid, although our model nearly runs away at ∼12 preindustrial atmospheric levels of CO(2) when we use the most alarmist assumptions possible. However, we argue that Earth's real climate is probably stable given more realistic assumptions, although 3-D climate models will be required to verify this result. Potential CO(2) increases from fossil fuel burning are somewhat smaller than this, 10-fold or less, but such increases could still cause sufficient warming to make much of the planet uninhabitable by humans. PMID:25061956

  15. Method for modifying trigger level for adsorber regeneration

    DOEpatents

    Ruth, Michael J.; Cunningham, Michael J.

    2010-05-25

    A method for modifying a NO.sub.x adsorber regeneration triggering variable. Engine operating conditions are monitored until the regeneration triggering variable is met. The adsorber is regenerated and the adsorbtion efficiency of the adsorber is subsequently determined. The regeneration triggering variable is modified to correspond with the decline in adsorber efficiency. The adsorber efficiency may be determined using an empirically predetermined set of values or by using a pair of oxygen sensors to determine the oxygen response delay across the sensors.

  16. Resource Utilization by the ATLAS High Level Trigger during 2010 and 2011 LHC running

    NASA Astrophysics Data System (ADS)

    Lipeles, Elliot; Ospanov, Rustem; Schaefer, Doug

    2012-12-01

    Since starting in 2010, the Large Hadron Collider (LHC) has produced collisions at an ever increasing rate. The ATLAS experiment successfully recorded the collision data with high efficiency and excellent data quality. Events were selected using a three-level trigger system, where each level made a more refined selection. The Level 1 (L1) trigger consisted of a custom-designed hardware trigger which seeded two higher software based trigger levels. Over 300 triggers composed a trigger menu which selected physics signatures such as electrons, muons, particle jets, etc. Each trigger consumed computing resources of the ATLAS Trigger system and offline storage. The LHC instantaneous luminosity conditions, desired physics goals of the collaboration, and the limits of the trigger infrastructure determined the composition of the ATLAS Trigger menu. We describe a trigger monitoring framework called the Cost Monitoring Framework for computing the costs of individual trigger algorithms such as data request rates and CPU consumption. This framework was used to prepare the ATLAS Trigger for data taking during increases of more than six orders of magnitude in the LHC luminosity and has been influential in guiding ATLAS Trigger computing upgrades.

  17. Electrophysiological characteristics according to activity level of myofascial trigger points.

    PubMed

    Yu, Seong Hun; Kim, Hyun Jin

    2015-09-01

    [Purpose] This study compared the differences in electrophysiological characteristics of normal muscles versus muscles with latent or active myofascial trigger points, and identified the neuromuscular physiological characteristics of muscles with active myofascial trigger points, thereby providing a quantitative evaluation of myofascial pain syndrome and clinical foundational data for its diagnosis. [Subjects] Ninety adults in their 20s participated in this study. Subjects were equally divided into three groups: the active myofascial trigger point group, the latent myofascial trigger point group, and the control group. [Methods] Maximum voluntary isometric contraction (MVIC), endurance, median frequency (MDF), and muscle fatigue index were measured in all subjects. [Results] No significant differences in MVIC or endurance were revealed among the three groups. However, the active trigger point group had significantly different MDF and muscle fatigue index compared with the control group. [Conclusion] Given that muscles with active myofascial trigger points had an increased MDF and suffered muscle fatigue more easily, increased recruitment of motor unit action potential of type II fibers was evident. Therefore, electrophysiological analysis of these myofascial trigger points can be applied to evaluate the effect of physical therapy and provide a quantitative diagnosis of myofascial pain syndrome.

  18. FPGA-based multimodal embedded sensor system integrating low- and mid-level vision.

    PubMed

    Botella, Guillermo; Martín H, José Antonio; Santos, Matilde; Meyer-Baese, Uwe

    2011-01-01

    Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

  19. Resource Utilization by the ATLAS High Level Trigger during 2010 and 2011 LHC Running

    NASA Astrophysics Data System (ADS)

    Ospanov, Rustem; ATLAS Collaboration

    In 2010 and 2011, the ATLAS experiment successfully recorded data from LHC collisions with high efficiency and excellent data quality. ATLAS employs a three-level trigger system to select events of interest for physics analyzes and detector commissioning. The trigger system consists of a custom-designed hardware trigger at level-1 and software algorithms at the two higher levels. The trigger selection is defined by a trigger menu which consists of more than 300 individual trigger signatures, such as electrons, muons, particle jets, etc. An execution of a trigger signature incurs computing and data storage costs. The composition of the deployed trigger menu depends on the instantaneous LHC luminosity, the experiment's goals for the recorded data, and the limits imposed by the available computing power, network bandwidth and storage space. This paper describes a trigger monitoring framework for assigning computing costs for individual trigger signatures and trigger menus as a whole. These costs can be extrapolated to higher luminosity allowing development of trigger menus for a higher LHC collision rate than currently achievable.

  20. Operation of the enhanced ATLAS First Level Calorimeter Trigger at the start of Run-2

    NASA Astrophysics Data System (ADS)

    Palka, Marek

    2016-02-01

    In 2015 the LHC is already operating with a higher centre-of-mass energy and proton beam luminosity. To keep high trigger efficiency with the increased event rate ATLAS Level-1 Calorimeter Trigger electronics have been re-designed or newly introduced (Pre-Processors, Merging Modules and Topological Processors). Additionally, to achieve the best possible resolution for the reconstructed physics objects, complex calibration and monitoring systems are employed. Hit rates and energy spectra down to channel level, based on reconstructed events, are supervised with the calorimeter trigger hardware. In this paper the performance of the upgraded Level-1 Calorimeter Trigger at the beginning of LHC Run-2 is described.

  1. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    NASA Astrophysics Data System (ADS)

    Magazzù, G.; Borgese, G.; Costantino, N.; Fanucci, L.; Incandela, J.; Saponara, S.

    2013-02-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  2. The Calorimeter Trigger Processor Card: the next generation of high speed algorithmic data processing at CMS

    NASA Astrophysics Data System (ADS)

    Svetek, A.; Blake, M.; Cepeda Hermida, M.; Dasu, S.; Dodd, L.; Fobes, R.; Gomber, B.; Gorski, T.; Guo, Z.; Klabbers, P.; Levine, A.; Ojalvo, I.; Ruggles, T.; Smith, N.; Smith, W. H.; Tikalsky, J.; Vicente, M.; Woods, N.

    2016-02-01

    The CMS Level-1 upgraded calorimeter trigger requires a powerful, flexible and compact processing card. The Calorimeter Trigger Processor Card (CTP7) uses the Virtex-7 FPGA as its primary data processor and is the first FPGA based processing card in CMS to employ the ZYNQ System-on-Chip (SoC) running embedded Linux to provide TCP/IP communication and board support functions. The CTP7 was built from the ground up to support AXI infrastructure to provide flexible and modular designs with minimal time from project conception to final implementation.

  3. High level triggers for explosive mafic volcanism: Albano Maar, Italy

    NASA Astrophysics Data System (ADS)

    Cross, J. K.; Tomlinson, E. L.; Giordano, G.; Smith, V. C.; De Benedetti, A. A.; Roberge, J.; Manning, C. J.; Wulf, S.; Menzies, M. A.

    2014-03-01

    Colli Albani is a quiescent caldera complex located within the Roman Magmatic Province (RMP), Italy. The recent Via dei Laghi phreatomagmatic eruptions led to the formation of nested maars. Albano Maar is the largest and has erupted seven times between ca 69-33 ka. The highly explosive nature of the Albano Maar eruptions is at odds with the predominant relatively mafic (SiO2 = 48-52 wt.%) foiditic (K2O = 9 wt.%) composition of the magma. The deposits have been previously interpreted as phreatomagmatic, however they contain large amounts (up to 30%vol) of deep seated xenoliths, skarns and all pre-volcanic subsurface units. All of the xenoliths have been excavated from depths of up to 6 km, rather than being limited to the depth at which magma and water interaction is likely to have occurred, suggesting an alternative trigger for eruption. High precision geochemical glass and mineral data of fresh juvenile (magmatic) clasts from the small volume explosive deposits indicate that the magmas have evolved along one of two evolutionary paths towards foidite or phonolite. The foiditic melts record ca. 50% mixing between the most primitive magma and Ca-rich melt, late stage prior to eruption. A major result of our study is finding that the generation of Ca-rich melts via assimilation of limestone, may provide storage for significant amounts of CO2 that can be released during a mixing event with silicate magma. Differences in melt evolution are inferred as having been controlled by variations in storage conditions: residence time and magma volume.

  4. Measuring Science Teachers' Stress Level Triggered by Multiple Stressful Conditions

    ERIC Educational Resources Information Center

    Halim, Lilia; Samsudin, Mohd Ali; Meerah, T. Subahan M.; Osman, Kamisah

    2006-01-01

    The complexity of science teaching requires science teachers to encounter a range of tasks. Some tasks are perceived as stressful while others are not. This study aims to investigate the extent to which different teaching situations lead to different stress levels. It also aims to identify the easiest and most difficult conditions to be regarded…

  5. A 250 MHz Level 1 Trigger and Distribution System for the GlueX experiment

    SciTech Connect

    Abbott, David J.; Cuevas, R. Christopher; Doughty, David Charles; Jastrzembski, Edward A.; Barbosa, Fernando J.; Raydo, Benjamin J.; Dong, Hai T.; Wilson, Jeffrey S.; Gupta, Abishek; Taylor, Mark; Somov, S.

    2009-11-01

    The GlueX detector now under construction at Jefferson Lab will search for exotic mesons though photoproduction (10^8 tagged photons per second) on a liquid hydrogen target. A Level 1 hardware trigger design is being developed to reduce total electromagnetic (>200 MHz) and hadronic (>350 kHz) rates to less than 200 kHz. This trigger is dead timeless and operates on a global synchronized 250 MHz clock. The core of the trigger design is based on a custom pipelined flash ADC board that uses a VXS backplane to collect samples from all ADCs in a VME crate. A custom switch-slot board called a Crate Trigger Processor (CTP) processes this data and passes the crate level data via a multi-lane fiber optic link to the Global Trigger Processing Crate (also VXS). Within this crate detector sub-system processor (SSP) boards can accept all individual crate links. The subsystem data are processed and finally passed to global trigger boards (GTP) where the final L1 decision is made. We present details of the trigger design and report some performance results on current prototype systems.

  6. FPGA Verification Accelerator (FVAX)

    NASA Technical Reports Server (NTRS)

    Oh, Jane; Burke, Gary

    2008-01-01

    Is Verification Acceleration Possible? - Increasing the visibility of the internal nodes of the FPGA results in much faster debug time - Forcing internal signals directly allows a problem condition to be setup very quickly center dot Is this all? - No, this is part of a comprehensive effort to improve the JPL FPGA design and V&V process.

  7. Hierarchical Trigger of the ALICE Calorimeters

    SciTech Connect

    Muller, Hans; Awes, Terry C

    2010-05-01

    The trigger of the ALICE electromagnetic calorimeters is implemented in 2 hierarchically connected layers of electronics. In the lower layer, level-0 algorithms search shower energy above threshold in locally confined Trigger Region Units (TRU). The top layer is implemented as a single, global trigger unit that receives the trigger data from all TRUs as input to the level-1 algorithm. This architecture was first developed for the PHOS high p{sub T} photon trigger before it was adopted by EMCal also for the jet trigger. TRU units digitize up to 112 analogue input signals from the Front End Electronics (FEE) and concentrate their digital stream in a single FPGA. A charge and time summing algorithm is combined with a peakfinder that suppresses spurious noise and is precise to single LHC bunches. With a peak-to-peak noise level of 150 MeV the linear dynamic range above threshold spans from MIP energies at 215 up to 50 GeV. Local level-0 decisions take less than 600 ns after LHC collisions, upon which all TRUs transfer their level-0 trigger data to the upstream global trigger module which searches within the remaining level-1 latency for high p{sub T} gamma showers (PHOS) and/or for Jet cone areas (EMCaL).

  8. Hierarchical trigger of the ALICE calorimeters

    NASA Astrophysics Data System (ADS)

    Muller, Hans; Awes, Terry C.; Novitzky, Norbert; Kral, Jiri; Rak, Jan; Schambach, Jo; Wang, Yaping; Wang, Dong; Zhou, Daicui

    2010-05-01

    The trigger of the ALICE electromagnetic calorimeters is implemented in 2 hierarchically connected layers of electronics. In the lower layer, level-0 algorithms search shower energy above threshold in locally confined Trigger Region Units (TRU). The top layer is implemented as a single, global trigger unit that receives the trigger data from all TRUs as input to the level-1 algorithm. This architecture was first developed for the PHOS high pT photon trigger before it was adopted by EMCal also for the jet trigger. TRU units digitize up to 112 analogue input signals from the Front End Electronics (FEE) and concentrate their digital stream in a single FPGA. A charge and time summing algorithm is combined with a peakfinder that suppresses spurious noise and is precise to single LHC bunches. With a peak-to-peak noise level of 150 MeV the linear dynamic range above threshold spans from MIP energies at 215 up to 50 GeV. Local level-0 decisions take less than 600 ns after LHC collisions, upon which all TRUs transfer their level-0 trigger data to the upstream global trigger module which searches within the remaining level-1 latency for high pT gamma showers (PHOS) and/or for Jet cone areas (EMCaL).

  9. L1Track: A fast Level 1 track trigger for the ATLAS high luminosity upgrade

    NASA Astrophysics Data System (ADS)

    Cerri, Alessandro

    2016-07-01

    With the planned high-luminosity upgrade of the LHC (HL-LHC), the ATLAS detector will see its collision rate increase by approximately a factor of 5 with respect to the current LHC operation. The earliest hardware-based ATLAS trigger stage ("Level 1") will have to provide a higher rejection factor in a more difficult environment: a new improved Level 1 trigger architecture is under study, which includes the possibility of extracting with low latency and high accuracy tracking information in time for the decision taking process. In this context, the feasibility of potential approaches aimed at providing low-latency high-quality tracking at Level 1 is discussed.

  10. Corticosteroid injections in the treatment of trigger finger: a level I and II systematic review.

    PubMed

    Fleisch, Sheryl B; Spindler, Kurt P; Lee, Donald H

    2007-03-01

    Trigger finger is a tendinitis (stenosing tenosynovitis) with multiple management approaches. We conducted an evidence-based medicine systematic review of level I and II prospective randomized controlled trials to determine the effectiveness of corticosteroid injection in managing trigger finger. MEDLINE, Cochrane database, and secondary references were reviewed to locate all English-language prospective randomized controlled trials evaluating trigger finger treatment. Four studies using injectable corticosteroids were identified, based on the following inclusion criteria: all were prospective randomized controlled trials of adults with >85% follow-up. This review indicates that the incidence of trigger finger is greatest in women (75%), with an average patient age range of 52 to 62 years. Combined analysis of these four studies shows that corticosteroid injections are effective in 57% of patients. PMID:17341673

  11. Level 3 trigger algorithm and Hardware Platform for the HADES experiment

    NASA Astrophysics Data System (ADS)

    Kirschner, Daniel Georg; Agakishiev, Geydar; Liu, Ming; Perez, Tiago; Kühn, Wolfgang; Pechenov, Vladimir; Spataro, Stefano

    2009-01-01

    A next generation real time trigger method to improve the enrichment of lepton events in the High Acceptance DiElectron Spectrometer (HADES) trigger system has been developed. In addition, a flexible Hardware Platform (Gigabit Ethernet-Multi-Node, GE-MN) was developed to implement and test the trigger method. The trigger method correlates the ring information of the HADES Ring Imaging Cherenkov (RICH) detector with the fired wires (drift cells) of the HADES Mini Drift Chamber (MDC) detector. It is demonstrated that this Level 3 trigger method can enhance the number of events which contain leptons by a factor of up to 50 at efficiencies above 80%. The performance of the correlation method in terms of the events analyzed per second has been studied with the GE-MN prototype in a lab test setup by streaming previously recorded experiment data to the module. This paper is a compilation from Kirschner [Level 3 trigger algorithm and Hardware Platform for the HADES experiment, Ph.D. Thesis, II. Physikalisches Institut der Justus-Liebig-Universität Gießen, urn:nbn:de:hebis:26-opus-50784, October 2007 [1

  12. Data flow analysis of a highly parallel processor for a level 1 pixel trigger

    SciTech Connect

    Cancelo, G.; Gottschalk, Erik Edward; Pavlicek, V.; Wang, M.; Wu, J.

    2003-01-01

    The present work describes the architecture and data flow analysis of a highly parallel processor for the Level 1 Pixel Trigger for the BTeV experiment at Fermilab. First the Level 1 Trigger system is described. Then the major components are analyzed by resorting to mathematical modeling. Also, behavioral simulations are used to confirm the models. Results from modeling and simulations are fed back into the system in order to improve the architecture, eliminate bottlenecks, allocate sufficient buffering between processes and obtain other important design parameters. An interesting feature of the current analysis is that the models can be extended to a large class of architectures and parallel systems.

  13. Commissioning of the ATLAS High Level Trigger with single beam and cosmic rays

    NASA Astrophysics Data System (ADS)

    Di Mattia, A.; ATLAS Collaboration

    2010-04-01

    ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). The trigger system is responsible for making the online selection of interesting collision events. At the LHC design luminosity of 1034 cm-2s-1 it will need to achieve a rejection factor of the order of 10-7 against random proton-proton interactions, while selecting with high efficiency events that are needed for physics analyses. After a first processing level using custom electronics based on FPGAs and ASICs, the trigger selection is made by software running on two processor farms, containing a total of around two thousand multi-core machines. This system is known as the High Level Trigger (HLT). To reduce the network data traffic and the processing time to manageable levels, the HLT uses seeded, step-wise reconstruction, aiming at the earliest possible rejection of background events. The recent LHC startup and short single-beam run provided a "stress test" of the system and some initial calibration data. Following this period, ATLAS continued to collect cosmic-ray events for detector alignment and calibration purposes. After giving an overview of the trigger design and its innovative features, this paper focuses on the experience gained from operating the ATLAS trigger with single LHC beams and cosmic-rays.

  14. Design and Implementation of the New D0 Level-1 Calorimeter Trigger

    SciTech Connect

    Abolins, M.; Adams, M.; Adams, T.; Aguilo, E.; Anderson, J.; Bagby, L.; Ban, J.; Barberis, E.; Beale, S.; Benitez, J.; Biehl, J.; /Columbia U. /DAPNIA, Saclay /Delhi U. /Fermilab /Florida State U. /Indiana U. /Michigan State U. /Northeastern U. /Rice U. /Southern Methodist U. /University Coll., Dublin

    2007-09-01

    Increasing luminosity at the Fermilab Tevatron collider has led the D0 collaboration to make improvements to its detector beyond those already in place for Run IIa, which began in March 2001. One of the cornerstones of this Run IIb upgrade is a completely redesigned level-1 calorimeter trigger system. The new system employs novel architecture and algorithms to retain high efficiency for interesting events while substantially increasing rejection of background. We describe the design and implementation of the new level-1 calorimeter trigger hardware and discuss its performance during Run IIb data taking. In addition to strengthening the physics capabilities of D0, this trigger system will provide valuable insight into the operation of analogous devices to be used at LHC experiments.

  15. Radiation Tolerant Antifuse FPGA

    NASA Technical Reports Server (NTRS)

    Wang, Jih-Jong; Cronquist, Brian; McCollum, John; Parker, Wanida; Katz, Rich; Kleyner, Igor; Day, John H. (Technical Monitor)

    2002-01-01

    The total dose performance of the antifuse FPGA for space applications is summarized. Optimization of the radiation tolerance in the fabless model is the main theme. Mechanisms to explain the variation in different products are discussed.

  16. CDF trigger final balance: Offline resolution at low level selections to fight against Tevatron increasing luminosity

    SciTech Connect

    Amerio, S.; /Padua U. /INFN, Padua

    2010-01-01

    The CDF detector at Tevatron collider is at present the most long-lasting high energy physics experiment. Since its first data taking in 1992 it has produced many results of primary importance, such as the discovery of top quark and, more recently, the observations of Bs oscillations and single-top production. None of them would have been possible without a fast and efficient trigger system. Based on a three level architecture, the CDF trigger takes decisions on simple calorimetric and tracking objects and assures both high efficiency on signal events and low dead time. It reduces the data flow rate from 2.53 MHz, the collision rate, to 150 Hz, the current limit on tape writing and is flexible enough to be easily adapted to the continuously growing instantaneous luminosity. In the last years the Tevatron instantaneous luminosity has rapidly increased and is now reaching 4 x 10{sup 32} cm{sup -2} s{sup -1}. The CDF trigger system has been widely upgraded to cope with increasing trigger rates. The upgrade result is online reconstruction of missing transverse energy, jets and tracks with a quality comparable to the offline one. Jet energy and direction can be precisely determined and tracks can be subjected to 3-D reconstruction with good resolution. These upgrades reduce high trigger rates to acceptable levels and have provided invaluable tools to increase the purity of the collected samples. They also represent a helpful experience for LHC experiments where background rates will be much more demanding.

  17. Feasibility of a portable morphological scene change detection security system for field programmable gate arrays (FPGA)

    NASA Astrophysics Data System (ADS)

    Tickle, Andrew J.; Smith, Jeremy S.; Wu, Q. Henry

    2008-04-01

    In this paper, there is an investigation into the possibility of executing a Morphological Scene Change Detection (MSCD) system on a Field Programmable Gate Array (FPGA), which would allow its set up in virtually any location, with its purpose to detect intruders and raise an alarm to call security personal, and a signal to initial a lockdown of the local area. This paper will include how the system was scaled down from the full building multi-computer system, to an FPGA without losing any functionality using Altera's DSP Builder development tool. Also included is the analysis of the different situations which the system would encounter in the field, and their respective alarm triggering levels, these include indoors, outdoors, close-up, distance, high-brightness, low-light, bad weather, etc. The triggering mechanism is a pixel counter and threshold system, and its adaptive design will be included. All the results shown in this paper, will also be verified by MATLAB m-files running on a full desktop PC, to show that the results obtained from the FPGA based system are accurate.

  18. Public Key FPGA Software

    SciTech Connect

    Hymel, Ross

    2013-07-25

    The Public Key (PK) FPGA software performs asymmetric authentication using the 163-bit Elliptic Curve Digital Signature Algorithm (ECDSA) on an embedded FPGA platform. A digital signature is created on user-supplied data, and communication with a host system is performed via a Serial Peripheral Interface (SPI) bus. Software includes all components necessary for signing, including custom random number generator for key creation and SHA-256 for data hashing.

  19. WATER LEVEL DRAWDOWN TRIGGERS SYSTEM-WIDE BUBBLE RELEASE FROM RESERVOIR SEDIMENTS

    EPA Science Inventory

    Reservoirs are an important anthropogenic source of methane and ebullition is a key pathway by which methane stored in reservoir sediments can be released to the atmosphere. Changes in hydrostatic pressure during periods of falling water levels can trigger bubbling events, sugge...

  20. 78 FR 37516 - WTO Agricultural Quantity-Based Safeguard Trigger Levels

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-06-21

    ... of Agriculture in Presidential Proclamation No. 6763, dated December 23, 1994, 60 FR 1005 (Jan. 4... Safeguard Trigger Levels, published in the Federal Register at 60 FR 427 (Jan. 4, 1995). Notice: As provided... Safeguard Action published in the Federal Register, at 60 FR 427 (Jan. 4, 1995). Issued at Washington,...

  1. The First Level Trigger of JEM-EUSO: Concept and tests

    NASA Astrophysics Data System (ADS)

    Bertaina, M.; Caruso, R.; Catalano, O.; Contino, G.; Fenu, F.; Mignone, M.; Mulas, R.

    2016-07-01

    The trigger system of JEM-EUSO is designed to meet specific challenging requirements. These include managing a large number of pixels (~3·105) and using a very fast, low power consuming, and radiation hard electronics. It must achieve a high signal-to-noise performance and flexibility and cope with the limited down-link transmission rate from the International Space Station (ISS) to Earth. The general overview of the First Level Trigger for cosmic ray detection is reviewed; tests that validate its performance are discussed.

  2. The architecture of the CMS Level-1 Trigger Control and Monitoring System using UML

    NASA Astrophysics Data System (ADS)

    Magrans de Abril, Marc; Da Rocha Melo, Jose L.; Ghabrous Larrea, Carlos; Hammer, Josef; Hartl, Christian; Lazaridis, Christos

    2011-12-01

    The architecture of the Compact Muon Solenoid (CMS) Level-1 Trigger Control and Monitoring software system is presented. This system has been installed and commissioned on the trigger online computers and is currently used for data taking. It has been designed to handle the trigger configuration and monitoring during data taking as well as all communications with the main run control of CMS. Furthermore its design has foreseen the provision of the software infrastructure for detailed testing of the trigger system during beam down time. This is a medium-size distributed system that runs over 40 PCs and 200 processes that control about 4000 electronic boards. The architecture of this system is described using the industry-standard Universal Modeling Language (UML). This way the relationships between the different subcomponents of the system become clear and all software upgrades and modifications are simplified. The described architecture has allowed for frequent upgrades that were necessary during the commissioning phase of CMS when the trigger system evolved constantly. As a secondary objective, the paper provides a UML usage example and tries to encourage the standardization of the software documentation of large projects across the LHC and High Energy Physics community.

  3. A flexible demonstrator system for the ATLAS level-1 calorimeter trigger

    SciTech Connect

    Brawn, I.; Carney, R.; Connors, A.

    1996-12-31

    The proposed level-1 calorimeter trigger system for ATLAS relies upon several key technologies which we have been testing in a demonstrator programme. We describe here the final phase of this programme, which concentrates on crucial aspects of high-speed data transmission inherent in the trigger architecture while operating with signals from prototype ATLAS calorimeters. The 36-channel trigger demonstrator system has been designed to provide a flexible infrastructure for the study of alternative techniques of communication between the calorimeters and the trigger processor, including both analogue links and high-speed digital optical and electrical links operating at up to 1.6 Gbaud. Data fan-out at 160 Mbit/s between trigger processor modules using serializing Application Specific Integrated Circuits (ASICs) driving transmission-line backplanes is also evaluated. A programmable timing system re-synchronizes all channels before pipeline processing by ASICs executing an electromagnetic cluster-finding algorithm. Some preliminary results are presented from the operation of this demonstrator system installed in the ATLAS test-beam at CERN.

  4. Central FPGA-based destination and load control in the LHCb MHz event readout

    NASA Astrophysics Data System (ADS)

    Jacobsson, R.

    2012-10-01

    The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

  5. Computer vision camera with embedded FPGA processing

    NASA Astrophysics Data System (ADS)

    Lecerf, Antoine; Ouellet, Denis; Arias-Estrada, Miguel

    2000-03-01

    Traditional computer vision is based on a camera-computer system in which the image understanding algorithms are embedded in the computer. To circumvent the computational load of vision algorithms, low-level processing and imaging hardware can be integrated in a single compact module where a dedicated architecture is implemented. This paper presents a Computer Vision Camera based on an open architecture implemented in an FPGA. The system is targeted to real-time computer vision tasks where low level processing and feature extraction tasks can be implemented in the FPGA device. The camera integrates a CMOS image sensor, an FPGA device, two memory banks, and an embedded PC for communication and control tasks. The FPGA device is a medium size one equivalent to 25,000 logic gates. The device is connected to two high speed memory banks, an IS interface, and an imager interface. The camera can be accessed for architecture programming, data transfer, and control through an Ethernet link from a remote computer. A hardware architecture can be defined in a Hardware Description Language (like VHDL), simulated and synthesized into digital structures that can be programmed into the FPGA and tested on the camera. The architecture of a classical multi-scale edge detection algorithm based on a Laplacian of Gaussian convolution has been developed to show the capabilities of the system.

  6. ADC and TDC implemented using FPGA

    SciTech Connect

    Wu, Jinyuan; Hansen, Sten; Shi, Zonghan; /Fermilab

    2007-11-01

    Several tests of FPGA devices programmed as analog waveform digitizers are discussed. The ADC uses the ramping-comparing scheme. A multi-channel ADC can be implemented with only a few resistors and capacitors as external components. A periodic logic levels are shaped by passive RC network to generate exponential ramps. The FPGA differential input buffers are used as comparators to compare the ramps with the input signals. The times at which these ramps cross the input signals are digitized by time-to-digital-converters (TDCs) implemented within the FPGA. The TDC portion of the logic alone has potentially a broad range of HEP/nuclear science applications. A 96-channel TDC card using FPGAs as TDCs being designed for the Fermilab MIPP electronics upgrade project is discussed. A deserializer circuit based on multisampling circuit used in the TDC, the 'Digital Phase Follower' (DPF) is also documented.

  7. A bit-serial first-level calorimeter trigger for LHC detectors

    SciTech Connect

    Bohm, C.; Zhao, X.; Appelquist, G.; Engstroem, M.; Hellman, S.; Holmgren, S.O.; Johansson, E.; Yamdagni, N.

    1994-12-31

    A first-level calorimeter trigger design, implemented as a farm of local bit-serial systolic arrays, is presented. The massive bit-serial operation can achieve higher processing throughput and more compact designs than conventional bit-parallel data representation. The construction is based on high speed optical fiber data transmissions, Application Specific Integrated Circuits (ASICs) and multi-chip modules (MCMs) packaging technologies.

  8. A content addressable memory for use in CEBAF's CLAS detector level 2 triggering system

    SciTech Connect

    R.F. Hodson; D.C. Doughty, Jr.; D.C. Allgood; S.A. Campbell; W.C. Wilson; M.H. Bickley

    1996-06-01

    A collaboration of researchers from CEBAF, CNU and NASA is designing a 256-32 specialized Content Addressable Memory (CAM) for the level 2 triggering system in CEBAF's CLAS detector. These integrated circuits will find tracks and the momentum and angle of each track within 2 microseconds of an event. The custom CAM can operate as conventional memory, performing read and write operations, and can additionally perform independent byte compare operations across all words simultaneously. It is this compare feature which makes these CAMs attractive for identifying tracks passing through drift chambers by linking together segment number triplets within the CAM. Simulations have indicated that less than 16 k triplets need to be stored for each sector of the detector. This implies the level 2 triggering can be performed with 64 CAM chips per sector, or 384 total. Each data channel into a sector CAM array is buffered in a FIFO and is designed to handle aggregate data rates up to 750 Mbs for three channels (one channel/superlayer). The architecture of the level 2 trigger and details of the CAM chip design are discussed along with a performance report on our prototype CAMs

  9. Harmonic analysis and FPGA implementation of SHE controlled three phase CHB 11-level inverter in MV drives using deterministic and stochastic optimization techniques.

    PubMed

    Vesapogu, Joshi Manohar; Peddakotla, Sujatha; Kuppa, Seetha Rama Anjaneyulu

    2013-01-01

    With the advancements in semiconductor technology, high power medium voltage (MV) Drives are extensively used in numerous industrial applications. Challenging technical requirements of MV Drives is to control multilevel inverter (MLI) with less Total harmonic distortion (%THD) which satisfies IEEE standard 519-1992 harmonic guidelines and less switching losses. Among all modulation control strategies for MLI, Selective harmonic elimination (SHE) technique is one of the traditionally preferred modulation control technique at fundamental switching frequency with better harmonic profile. On the other hand, the equations which are formed by SHE technique are highly non-linear in nature, may exist multiple, single or even no solution at particular modulation index (MI). However, in some MV Drive applications, it is required to operate over a range of MI. Providing analytical solutions for SHE equations during the whole range of MI from 0 to 1, has been a challenging task for researchers. In this paper, an attempt is made to solve SHE equations by using deterministic and stochastic optimization methods and comparative harmonic analysis has been carried out. An effective algorithm which minimizes %THD with less computational effort among all optimization algorithms has been presented. To validate the effectiveness of proposed MPSO technique, an experiment is carried out on a low power proto type of three phase CHB 11- level Inverter using FPGA based Xilinx's Spartan -3A DSP Controller. The experimental results proved that MPSO technique has successfully solved SHE equations over all range of MI from 0 to 1, the %THD obtained over major range of MI also satisfies IEEE 519-1992 harmonic guidelines too. PMID:24010030

  10. Harmonic analysis and FPGA implementation of SHE controlled three phase CHB 11-level inverter in MV drives using deterministic and stochastic optimization techniques.

    PubMed

    Vesapogu, Joshi Manohar; Peddakotla, Sujatha; Kuppa, Seetha Rama Anjaneyulu

    2013-01-01

    With the advancements in semiconductor technology, high power medium voltage (MV) Drives are extensively used in numerous industrial applications. Challenging technical requirements of MV Drives is to control multilevel inverter (MLI) with less Total harmonic distortion (%THD) which satisfies IEEE standard 519-1992 harmonic guidelines and less switching losses. Among all modulation control strategies for MLI, Selective harmonic elimination (SHE) technique is one of the traditionally preferred modulation control technique at fundamental switching frequency with better harmonic profile. On the other hand, the equations which are formed by SHE technique are highly non-linear in nature, may exist multiple, single or even no solution at particular modulation index (MI). However, in some MV Drive applications, it is required to operate over a range of MI. Providing analytical solutions for SHE equations during the whole range of MI from 0 to 1, has been a challenging task for researchers. In this paper, an attempt is made to solve SHE equations by using deterministic and stochastic optimization methods and comparative harmonic analysis has been carried out. An effective algorithm which minimizes %THD with less computational effort among all optimization algorithms has been presented. To validate the effectiveness of proposed MPSO technique, an experiment is carried out on a low power proto type of three phase CHB 11- level Inverter using FPGA based Xilinx's Spartan -3A DSP Controller. The experimental results proved that MPSO technique has successfully solved SHE equations over all range of MI from 0 to 1, the %THD obtained over major range of MI also satisfies IEEE 519-1992 harmonic guidelines too.

  11. Deferred High Level Trigger in LHCb: A Boost to CPU Resource Utilization

    NASA Astrophysics Data System (ADS)

    Frank, M.; Gaspar, C.; Herwijnen, E. v.; Jost, B.; Neufeld, N.

    2014-06-01

    The LHCb experiment at the LHC accelerator at CERN collects collisions of particle bunches at 40 MHz. After a first level of hardware trigger with output of 1 MHz, the physically interesting collisions are selected by running dedicated trigger algorithms in the High Level Trigger (HLT) computing farm. This farm consists of up to roughly 25000 CPU cores in roughly 1600 physical nodes each equipped with at least 1 TB of local storage space. This work describes the architecture to treble the available CPU power of the HLT farm given that the LHC collider in previous years delivered stable physics beams about 30% of the time. The gain is achieved by splitting the event selection process in two, a first stage reducing the data taken during stable beams and buffering the preselected particle collisions locally. A second processing stage running constantly at lower priority will then finalize the event filtering process and benefits fully from the time when LHC does not deliver stable beams e.g. while preparing a new physics fill or during periods used for machine development.

  12. Drought-trigger ground-water levels and analysis of historical water-level trends in Chester County, Pennsylvania

    USGS Publications Warehouse

    Schreffler, Curtis L.

    1996-01-01

    The Chester County observation-well network was established in 1973 through a cooperative agreement between the Chester County Water Resources Authority (CCWRA) and the U.S. Geological Survey. The network was established to monitor local ground-water levels, to determine drought conditions, and to monitor ground-water-level trends. Drought-warning and drought-emergency water-level triggers were determined for 20 of the 23 wells in the Chester County observation-well network. A statistical test to determine either rising or declining water-level trends was performed on data for all wells in the network. Water-level data from both of these wells showed a rising trend. A decrease in ground-water pumping in the area near these wells was probably the reason for the rise in water levels.

  13. Integrated upstream parasitic event building architecture for BTeV level 1 pixel trigger system

    SciTech Connect

    Wu, Jin-Yuan; Wang, M.; Gottschalk, E.; Christian, D.; Li, X.; Shi, Z.; Pavlicek, V.; Cancelo, G.; /Fermilab

    2006-03-01

    Contemporary event building approaches use data switches, either homemade or commercial off-the-shelf ones, to merge data from different channels and distribute them among processor nodes. However, in many trigger and DAQ systems, the merging and distributing functions can often be performed in pre-processing stages. By carefully integrating these functions into the upstream pre-processing stages, the events can be built without dedicated switches. In addition to the cost reducing, extra benefits are gain when the event is built early upstream. In this document, an example of the integrated upstream parasitic event building architecture that has been studied for the BTeV level 1 pixel trigger system is described. Several design considerations that experimentalists of other projects might be interested in are also discussed.

  14. Dynamic triggering

    USGS Publications Warehouse

    Hill, David P.; Prejean, Stephanie; Schubert, Gerald

    2015-01-01

    Dynamic stresses propagating as seismic waves from large earthquakes trigger a spectrum of responses at global distances. In addition to locally triggered earthquakes in a variety of tectonic environments, dynamic stresses trigger tectonic (nonvolcanic) tremor in the brittle–plastic transition zone along major plate-boundary faults, activity changes in hydrothermal and volcanic systems, and, in hydrologic domains, changes in spring discharge, water well levels, soil liquefaction, and the eruption of mud volcanoes. Surface waves with periods of 15–200 s are the most effective triggering agents; body-wave trigger is less frequent. Triggering dynamic stresses can be < 1 kPa.

  15. Electrons and photons at High Level Trigger in CMS for Run II

    NASA Astrophysics Data System (ADS)

    Anuar, Afiq A.

    2015-12-01

    The CMS experiment has been designed with a 2-level trigger system. The first level is implemented using custom-designed electronics. The second level is the so-called High Level Trigger (HLT), a streamlined version of the CMS offline reconstruction software running on a computer farm. For Run II of the Large Hadron Collider, the increase in center-of-mass energy and luminosity will raise the event rate to a level challenging for the HLT algorithms. New approaches have been studied to keep the HLT output rate manageable while maintaining thresholds low enough to cover physics analyses. The strategy mainly relies on porting online the ingredients that have been successfully applied in the offline reconstruction, thus allowing to move HLT selection closer to offline cuts. Improvements in HLT electron and photon definitions will be presented, focusing in particular on: updated clustering algorithm and the energy calibration procedure, new Particle-Flow-based isolation approach and pileup mitigation techniques, and the electron-dedicated track fitting algorithm based on Gaussian Sum Filter.

  16. Drought-Trigger Ground-Water Levels in Chester County, Pennsylvania, for the Period of Record Ending May 2006

    USGS Publications Warehouse

    Cinotto, Peter J.

    2007-01-01

    This report presents the results of a study by the U.S. Geological Survey (USGS), in cooperation with the Chester County Water Resources Authority (CCWRA), to update the drought-trigger water levels for the Chester County observation-well network. The Chester County observation-well network was established in 1973 through a cooperative agreement between the CCWRA and the USGS to monitor local ground-water levels and trends and to determine drought conditions. In 1990 and again in 1997, drought-warning and drought-emergency water-level triggers were determined for the majority of wells in the existing Chester County observation-well network of 23 wells. Since 1997, the Chester County observation-well network expanded to 29 wells, some of the original wells were destroyed, and additional monthly water-level observations were made to allow for better statistical relations. Because of these changes, new statistics for water-level triggers were required. For this study, 19 of the 29 wells in the observation-well network were used to compute drought-trigger water levels. An additional 'drought-watch water-level trigger' category was developed to make the Chester County drought-trigger water-level categories consistent with those implemented by the Pennsylvania Department of Environmental Protection (PaDEP). The three drought-trigger water-level categories, as defined by PaDEP are 1) 'drought watch' when at the 75th-percentile level; 2) 'drought warning' when at the 90th-percentile level; and 3) 'drought emergency' when at the 95th-percentile level. A revised methodology, resulting from longer periods of record representing ground-water and climatic conditions and changes in local water use, has resulted in some observed differences in drought-trigger water levels. A comparison of current drought-trigger water levels to those calculated in 1997 shows the largest mean annual change in percentile values was in northeastern Chester County. In this northeastern region, the

  17. First operation of the level-0 trigger of the NA62 liquid krypton calorimeter

    NASA Astrophysics Data System (ADS)

    Barbanera, M.; Bizzarri, M.; Bonaiuto, V.; Checcucci, B.; Cipollone, P.; De Simone, N.; Fantechi, R.; Federici, L.; Fucci, A.; Lupi, M.; Paoluzzi, G.; Papi, A.; Salamon, A.; Salina, G.; Santoni, C.; Sargeni, F.; Venditti, S.

    2015-03-01

    The NA62 experiment at CERN Super Proton Synchrotron aims at studying ultra-rare decays of charged kaons for precise tests of the Standard Model. The complete experimental setup is being commissioned for the first physics data taking in the autumn of 2014. This paper presents the final design and implementation of the Level-0 trigger system of the LKr calorimeter, acting as hermetic photon veto of the experiment in the 1-8.5 mrad region. The first on-field performance tests are presented.

  18. Readout, first- and second-level triggers of the new Belle silicon vertex detector

    NASA Astrophysics Data System (ADS)

    Friedl, M.; Abe, R.; Abe, T.; Aihara, H.; Asano, Y.; Aso, T.; Bakich, A.; Browder, T.; Chang, M. C.; Chao, Y.; Chen, K. F.; Chidzik, S.; Dalseno, J.; Dowd, R.; Dragic, J.; Everton, C. W.; Fernholz, R.; Fujii, H.; Gao, Z. W.; Gordon, A.; Guo, Y. N.; Haba, J.; Hara, K.; Hara, T.; Harada, Y.; Haruyama, T.; Hasuko, K.; Hayashi, K.; Hazumi, M.; Heenan, E. M.; Higuchi, T.; Hirai, H.; Hitomi, N.; Igarashi, A.; Igarashi, Y.; Ikeda, H.; Ishino, H.; Itoh, K.; Iwaida, S.; Kaneko, J.; Kapusta, P.; Karawatzki, R.; Kasami, K.; Kawai, H.; Kawasaki, T.; Kibayashi, A.; Koike, S.; Korpar, S.; Križan, P.; Kurashiro, H.; Kusaka, A.; Lesiak, T.; Limosani, A.; Lin, W. C.; Marlow, D.; Matsumoto, H.; Mikami, Y.; Miyake, H.; Moloney, G. R.; Mori, T.; Nakadaira, T.; Nakano, Y.; Natkaniec, Z.; Nozaki, S.; Ohkubo, R.; Ohno, F.; Okuno, S.; Onuki, Y.; Ostrowicz, W.; Ozaki, H.; Peak, L.; Pernicka, M.; Rosen, M.; Rozanska, M.; Sato, N.; Schmid, S.; Shibata, T.; Stamen, R.; Stanič, S.; Steininger, H.; Sumisawa, K.; Suzuki, J.; Tajima, H.; Tajima, O.; Takahashi, K.; Takasaki, F.; Tamura, N.; Tanaka, M.; Taylor, G. N.; Terazaki, H.; Tomura, T.; Trabelsi, K.; Trischuk, W.; Tsuboyama, T.; Uchida, K.; Ueno, K.; Ueno, K.; Uozaki, N.; Ushiroda, Y.; Vahsen, S.; Varner, G.; Varvell, K.; Velikzhanin, Y. S.; Wang, C. C.; Wang, M. Z.; Watanabe, M.; Watanabe, Y.; Yamada, Y.; Yamamoto, H.; Yamashita, Y.; Yamashita, Y.; Yamauchi, M.; Yanai, H.; Yang, R.; Yasu, Y.; Yokoyama, M.; Ziegler, T.; Žontar, D.

    2004-12-01

    A major upgrade of the Silicon Vertex Detector (SVD 2.0) of the Belle experiment at the KEKB factory was installed along with new front-end and back-end electronics systems during the summer shutdown period in 2003 to cope with higher particle rates, improve the track resolution and meet the increasing requirements of radiation tolerance. The SVD 2.0 detector modules are read out by VA1TA chips which provide "fast or" (hit) signals that are combined by the back-end FADCTF modules to coarse, but immediate level 0 track trigger signals at rates of several tens of a kHz. Moreover, the digitized detector signals are compared to threshold lookup tables in the FADCTFs to pass on hit information on a single strip basis to the subsequent level 1.5 trigger system, which reduces the rate below the kHz range. Both FADCTF and level 1.5 electronics make use of parallel real-time processing in Field Programmable Gate Arrays (FPGAs), while further data acquisition and event building is done by PC farms running Linux. The new readout system hardware is described and the first results obtained with cosmics are shown.

  19. FPGA Vision Data Architecture

    NASA Technical Reports Server (NTRS)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  20. From OO to FPGA :

    SciTech Connect

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  1. Development of High Level Trigger Software for Belle II at SuperKEKB

    NASA Astrophysics Data System (ADS)

    Lee, S.; Itoh, R.; Katayama, N.; Mineo, S.

    2011-12-01

    The Belle collaboration has been trying for 10 years to reveal the mystery of the current matter-dominated universe. However, much more statistics is required to search for New Physics through quantum loops in decays of B mesons. In order to increase the experimental sensitivity, the next generation B-factory, SuperKEKB, is planned. The design luminosity of SuperKEKB is 8 x 1035cm-2s-1 a factor 40 above KEKB's peak luminosity. At this high luminosity, the level 1 trigger of the Belle II experiment will stream events of 300 kB size at a 30 kHz rate. To reduce the data flow to a manageable level, a high-level trigger (HLT) is needed, which will be implemented using the full offline reconstruction on a large scale PC farm. There, physics level event selection is performed, reducing the event rate by ~ 10 to a few kHz. To execute the reconstruction the HLT uses the offline event processing framework basf2, which has parallel processing capabilities used for multi-core processing and PC clusters. The event data handling in the HLT is totally object oriented utilizing ROOT I/O with a new method of object passing over the UNIX socket connection. Also under consideration is the use of the HLT output as well to reduce the pixel detector event size by only saving hits associated with a track, resulting in an additional data reduction of ~ 100 for the pixel detector. In this contribution, the design and implementation of the Belle II HLT are presented together with a report of preliminary testing results.

  2. Results from the first p+p runs of the ALICE High Level Trigger at LHC

    NASA Astrophysics Data System (ADS)

    Kanaki, Kalliopi; ALICE HLT Collaboration

    2011-12-01

    The High Level Trigger for the ALICE experiment at LHC is a powerful, sophisticated tool aimed at compressing the raw data volume and issuing selective triggers for events with desirable physics content. At its current state it integrates information from all major ALICE detectors, i. e. the inner tracking system, the time projection chamber, the electromagnetic calorimeters, the transition radiation detector and the muon spectrometer performing real-time event reconstruction. The steam engine behind HLT is a high performance computing cluster of several hundred nodes. It has to reduce the data rate from 25 GB/s to 1.25 GB/s for fitting the DAQ mass storage bandwidth. The cluster is served by a full GigaBit Ethernet network, in addition to an InfiniBand backbone network. To cope with the great challenge of Pb+Pb collisions in autumn 2010, its performance capabilities are being enhanced with the addition of new nodes. Towards the same end the first GPU co-processors are in place. During the first period of data taking with p+p collisions the HLT was extensively used to reconstruct, analyze and display data from the various participating detectors. Among other tasks it contributed to the monitoring of the detector performance, selected events for their calibration and efficiency studies, and estimated primary and secondary vertices from p+p collisions identifying V0 topologies. The experience gained during these first months of online operation will be presented.

  3. Ground-level observation of a terrestrial gamma ray flash initiated by a triggered lightning

    NASA Astrophysics Data System (ADS)

    Hare, B. M.; Uman, M. A.; Dwyer, J. R.; Jordan, D. M.; Biggerstaff, M. I.; Caicedo, J. A.; Carvalho, F. L.; Wilkes, R. A.; Kotovsky, D. A.; Gamerota, W. R.; Pilkey, J. T.; Ngin, T. K.; Moore, R. C.; Rassoul, H. K.; Cummer, S. A.; Grove, J. E.; Nag, A.; Betten, D. P.; Bozarth, A.

    2016-06-01

    We report on a terrestrial gamma ray flash (TGF) that occurred on 15 August 2014 coincident with an altitude-triggered lightning at the International Center for Lightning Research and Testing (ICLRT) in North Central Florida. The TGF was observed by a ground-level network of gamma ray, close electric field, distant magnetic field, Lightning Mapping Array (LMA), optical, and radar measurements. Simultaneous gamma ray and LMA data indicate that the upward positive leader of the triggered lightning flash induced relativistic runaway electron avalanches when the leader tip was at about 3.5 km altitude, resulting in the observed TGF. Channel luminosity and electric field data show that there was an initial continuous current (ICC) pulse in the lightning channel to ground during the time of the TGF. Modeling of the observed ICC pulse electric fields measured at close range (100-200 m) indicates that the ICC pulse current had both a slow and fast component (full widths at half maximum of 235 μs and 59 μs) and that the fast component was more or less coincident with the TGF, suggesting a physical association between the relativistic runaway electron avalanches and the ICC pulse observed at ground. Our ICC pulse model reproduces moderately well the measured close electric fields at the ICLRT as well as three independent magnetic field measurements made about 250 km away. Radar and LMA data suggest that there was negative charge near the region in which the TGF was initiated.

  4. A highly selective first-level muon trigger with MDT chamber data for ATLAS at HL-LHC

    NASA Astrophysics Data System (ADS)

    Nowak, S.; Kroha, H.

    2016-07-01

    Highly selective triggers are essential for the physics programme of the ATLAS experiment at HL-LHC where the instantaneous luminosity will be about an order of magnitude larger than the LHC instantaneous luminosity in Run 1. The first level muon trigger rate is dominated by low momentum muons below the nominal trigger threshold due to the moderate momentum resolution of the Resistive Plate and Thin Gap trigger chambers. The resulting high trigger rates at HL-LHC can be sufficiently reduced by using the data of the precision Muon Drift Tube chambers for the trigger decision. This requires the implementation of a fast MDT read-out chain and of a fast MDT track reconstruction algorithm with a latency of at most 6 μs. A hardware demonstrator of the fast read-out chain has been successfully tested at the HL-LHC operating conditions at the CERN Gamma Irradiation Facility. The fast track reconstruction algorithm has been implemented on a fast trigger processor.

  5. Using FPGA Devices to Accelerate Biomolecular Simulations

    SciTech Connect

    Alam, Sadaf R; Agarwal, Pratul K; Smith, Melissa C; Vetter, Jeffrey S; Caliga, David E

    2007-03-01

    A field-programmable gate array implementation of the particle-mesh Ewald a molecular dynamics simulation method reduces the microprocessor time-to-solution by a factor of three while using only high-level languages. The application speedup on FPGA devices increases with the problem size. The authors use a performance model to analyze the potential of simulating large-scale biological systems faster than many cluster-based supercomputing platforms.

  6. Novel fast multiplier implemented using FPGA

    NASA Astrophysics Data System (ADS)

    Jabłoński, Janusz; Wegrzyn, Marek

    2015-09-01

    In the paper, the solution dedicated for FPGA devices of a synthesis of parallel multiplication systems with the alternative approach, called mutual exclusion, for results of partial products is presented. There are proposed a reducer with the factor 4:2 for parallel multipliers, based on Wallace tree structures, that are dedicated for 4-input and 1-output Look-Up Table (LUT) function generator used in FPGA devices. The elaboration refers to the solution for multiplying using FPGAs the numbers of 4 and 8 bits. However it can be enlarged up to 16 and 32 bits. The proposed solution gives the opportunity to use the probability of conditional significant partial products and faster service - fewer logic levels for special cases of multiplication related to the specific values of the sums of partial product bits.

  7. Flexible event reconstruction software chains with the ALICE High-Level Trigger

    NASA Astrophysics Data System (ADS)

    Ram, D.; Breitner, T.; Szostak, A.

    2012-12-01

    The ALICE High-Level Trigger (HLT) has a large high-performance computing cluster at CERN whose main objective is to perform real-time analysis on the data generated by the ALICE experiment and scale it down to at-most 4GB/sec - which is the current maximum mass-storage bandwidth available. Data-flow in this cluster is controlled by a custom designed software framework. It consists of a set of components which can communicate with each other via a common control interface. The software framework also supports the creation of different configurations based on the detectors participating in the HLT. These configurations define a logical data processing “chain” of detector data-analysis components. Data flows through this software chain in a pipelined fashion so that several events can be processed at the same time. An instance of such a chain can run and manage a few thousand physics analysis and data-flow components. The HLT software and the configuration scheme used in the 2011 heavy-ion runs of ALICE, has been discussed in this contribution.

  8. Interfacing Detectors to Triggers And DAQ Electronics

    SciTech Connect

    Crosetto, Dario B.

    1999-05-03

    The complete design of the front-end electronics interfacing LHCb detectors, Level-0 trigger and higher levels of trigger with flexible configuration parameters has been made for (a) ASIC implementation, and (b) FPGA implementation. The importance of approaching designs in technology-independent form becomes essential with the actual rapid electronics evolution. Being able to constrain the entire design to a few types of replicated components: (a) the fully programmable 3D-Flow system, and (b) the configurable front-end circuit described in this article, provides even further advantages because only one or two types of components will need to migrate to the newer technologies. To base on today's technology the design of a system such as the LHCb project that is to begin working in 2006 is not cost-effective. The effort required to migrate to a higher-performance will, in that case, be almost equivalent to completely redesigning the architecture from scratch. The proposed technology independent design with the current configurable front-end module described in this article and the scalable 3D-Flow fully programmable system described elsewhere, based on the study of the evolution of electronics during the past few years and the forecasted advances in the years to come, aims to provide a technology-independent design which lends itself to any technology at any time. In this case, technology independence is based mainly on generic-HDL reusable code which allows a very rapid realization of the state-of-the-art circuits in terms of gate density, power dissipation, and clock frequency. The design of four trigger towers presently fits into an OR3T30 FPGA. Preliminary test results (provided in this paper) meet the functional requirements of LHCb and provide sufficient flexibility to introduce future changes. The complete system design is also provided along with the integration of the front-end design in the entire system and the cost and dimension of the electronics.

  9. FPGA Boot Loader and Scrubber

    NASA Technical Reports Server (NTRS)

    Wade, Randall S.; Jones, Bailey

    2009-01-01

    A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

  10. Performance of ATLAS RPC Level-1 muon trigger during the 2015 data taking

    NASA Astrophysics Data System (ADS)

    Corradi, M.

    2016-09-01

    RPCs are used in the ATLAS experiment at the LHC for the muon trigger system in the barrel region, which corresponds to a pseudorapidity range of |η|<1.05. The status of the system during the 2015 data taking is presented, including measurements of the RPC detector efficiencies and of the trigger performance. The RPC system has been active in more than 99.9% of the ATLAS data taking, showing very good reliability. The RPC detector efficiencies were close to Run 1 and to design values. The trigger efficiency for the high-pT thresholds used in single-muon triggers has been approximately 4% lower than in Run 1, mostly because of chambers disconnected from HV due to gas leaks. Two minor upgrades have been performed in preparation of Run 2 by adding the so-called feet and elevator chambers to increase the system acceptance. The feet chambers have been commissioned during 2015 and are included in the trigger since the last 2015 runs. Part of the elevator chambers are still in a commissioning phase and will probably need a replacement at the end of 2016.

  11. Superconducting cavity driving with FPGA controller

    NASA Astrophysics Data System (ADS)

    Czarski, Tomasz; Koprek, Waldemar; Poźniak, Krzysztof T.; Romaniuk, Ryszard S.; Simrock, Stefan; Brandt, Alexander; Chase, Brian; Carcagno, Ruben; Cancelo, Gustavo; Koeth, Timothy W.

    2006-12-01

    A digital control of superconducting cavities for a linear accelerator is presented. FPGA-based controller, supported by Matlab system, was applied. Electrical model of a resonator was used for design of a control system. Calibration of the signal path is considered. Identification of cavity parameters has been carried out for adaptive control algorithm. Feed-forward and feedback modes were applied in operating the cavities. Required performance has been achieved; i.e. driving on resonance during filling and field stabilization during flattop time, while keeping reasonable level of the power consumption. Representative results of the experiments are presented for different levels of the cavity field gradient.

  12. The use of content addressable memories in the level 2 trigger for the CLAS detector at CEBAF

    SciTech Connect

    Doughty, D.C. Jr.; Hodson, R.F.; Allgood, D.; Bickley, M.; Campbell, S.; Putnam, T.; Spivak, R.; Lemon, S.; Wilson, W.C.

    1996-02-01

    The LEVEL 2 trigger in the CLAS detector will find tracks and associate a momentum and angle with each track within 2 {micro}s after the event. This is done through a hierarchical track finding design in which track segments are found in each drift chamber axial superlayer. An array of 384 custom content addressable (or associative) memories (CAMs) uses independent subfield matching to link these track segments into roads. The track parameters corresponding to each found road are then looked up in a separate memory. The authors present the overall architecture of the LEVEL 2 trigger, the details of how the CAM chip links tracks segments to find roads, and report on the performance of the prototype CAM chips.

  13. Onboard FPGA-based SAR processing for future spaceborne systems

    NASA Technical Reports Server (NTRS)

    Le, Charles; Chan, Samuel; Cheng, Frank; Fang, Winston; Fischman, Mark; Hensley, Scott; Johnson, Robert; Jourdan, Michael; Marina, Miguel; Parham, Bruce; Rogez, Francois; Rosen, Paul; Shah, Biren; Taft, Stephanie

    2004-01-01

    We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

  14. Digital electronics for the inclusion of shower max and preshower wire data in the CDF second-level trigger

    SciTech Connect

    Dawson, J.W.; Byrum, K.L.; Haberichter, W.N.; Nodulman, L.J.; Wicklund, A.B.; Turner, K.J.; Gerdes, D.W.

    1993-07-01

    As part of the upgrade program at CDF, electronics has been built to bring the shower max (CES) and preshower (CPR) data into the trigger at level 2. After each crossing, 384 bits from shower max and 192 from the preshower wires are latched. Data from tracks are bussed to this module to provide the wire address and momentum which are then successively compared to the wire data in large look-up tables. Approximately 50 nanoseconds is required to determine a match, write the results in FIFO, and make the results available to track memory. Monte Carlo analysis has indicated that an increase in efficiency of a factor of three in triggering on b decays will be achieved with this hardware.

  15. STRS SpaceWire FPGA Module

    NASA Technical Reports Server (NTRS)

    Lux, James P.; Taylor, Gregory H.; Lang, Minh; Stern, Ryan A.

    2011-01-01

    An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

  16. Performance of Tracking, b-tagging and Jet/MET reconstruction at the CMS High Level Trigger

    NASA Astrophysics Data System (ADS)

    Tosi, Mia

    2015-12-01

    The trigger systems of the LHC detectors play a crucial role in determining the physics capabilities of experiments. In 2015, the center-of-mass energy of proton-proton collisions will reach 13 TeV up to an unprecedented luminosity of 1 × 1034 cm-2s-1. A reduction of several orders of magnitude of the event rate is needed to reach values compatible with detector readout, offline storage and analysis capabilities. The CMS experiment has been designed with a two-level trigger system: the Level-1 Trigger (L1T), implemented on custom-designed electronics, and the High Level Trigger (HLT), a streamlined version of the offline reconstruction software running on a computer farm. A software trigger system requires a trade-off between the complexity of the algorithms, the sustainable output rate, and the selection efficiency. With the computing power available during the 2012 data taking the maximum reconstruction time at HLT was about 200 ms per event, at the nominal L1T rate of 100 kHz. Tracking algorithms are widely used in the HLT in the object reconstruction through particle-flow techniques as well as in the identification of b-jets and lepton isolation. Reconstructed tracks are also used to distinguish the primary vertex, which identifies the hard interaction process, from the pileup ones. This task is particularly important in the LHC environment given the large number of interactions per bunch crossing: on average 25 in 2012, and expected to be around 40 in Run II with a large contribution from out-of-time particles. In order to cope with tougher conditions the tracking and vertexing techniques used in 2012 have been largely improved in terms of timing and efficiency in order to keep the physics reach at the level of Run I conditions. We will present the performance of these newly developed algorithms, discussing their impact on the b-tagging performances as well as on the jet and missing transverse energy reconstruction.

  17. Impact of sea-level rise on earthquake and landslide triggering offshore the Alentejo margin (SW Iberia)

    NASA Astrophysics Data System (ADS)

    Neves, M. C.; Roque, C.; Luttrell, K. M.; Vázquez, J. T.; Alonso, B.

    2016-07-01

    Earthquakes and submarine landslides are recurrent and widespread manifestations of fault activity offshore SW Iberia. The present work tests the effects of sea-level rise on offshore fault systems using Coulomb stress change calculations across the Alentejo margin. Large-scale faults capable of generating large earthquakes and tsunamis in the region, especially NE-SW trending thrusts and WNW-ESE trending dextral strike-slip faults imaged at basement depths, are either blocked or unaffected by flexural effects related to sea-level changes. Large-magnitude earthquakes occurring along these structures may, therefore, be less frequent during periods of sea-level rise. In contrast, sea-level rise promotes shallow fault ruptures within the sedimentary sequence along the continental slope and upper rise within distances of <100 km from the coast. The results suggest that the occurrence of continental slope failures may either increase (if triggered by shallow fault ruptures) or decrease (if triggered by deep fault ruptures) as a result of sea-level rise. Moreover, observations of slope failures affecting the area of the Sines contourite drift highlight the role of sediment properties as preconditioning factors in this region.

  18. Triggering for Magnetic Field Measurements of the LCLS Undulators

    SciTech Connect

    Hacker, Kirsten

    2010-12-13

    A triggering system for magnetic field measurements of the LCLS undulators has been built with a National Instruments PXI-1002 and a Xylinx FPGA board. The system generates single triggers at specified positions, regardless of encoder sensor jitter about a linear scale.

  19. Development and testing of an upgrade to the CMS level-1 calorimeter trigger

    NASA Astrophysics Data System (ADS)

    Baber, M.; Blake, M.; Brooke, J.; Cepeda Hermida, M.; Dasu, S.; Durkin, T.; Fayer, S.; Friis, E. K.; Gorski, T.; Hall, G.; Harder, K.; Iles, G.; Ives, S.; Jones, J.; Klabbers, P. R.; Levine, A. G.; Lucas, C.; Lucas, R.; Newbold, D.; Marrouche, J.; Paramesvaran, S.; Perry, T. M.; Rose, A.; Sankey, D.; Smith, W.; Tapper, A.; Thea, A.; Williams, T.

    2014-01-01

    When the LHC resumes operation in 2015, the higher centre-of-mass energy and high-luminosity conditions will require significantly more sophisticated algorithms to select interesting physics events within the readout bandwidth limitations. The planned upgrade to the CMS calorimeter trigger will achieve this goal by implementing a flexible system based on the μTCA standard, with modules based on Xilinx Virtex-7 FPGAs and up to 144 optical links running at speeds of 10 Gbps. The upgrade will improve the energy and position resolution of physics objects, enable much improved isolation criteria to be applied to electron and tau objects and facilitate pile-up subtraction to mitigate the effect of the increased number of interactions occurring in each bunch crossing. The design of the upgraded system is summarised with particular emphasis placed on the results of prototype testing and the experience gained which is of general application to the design of such systems.

  20. CMS software architecture. Software framework, services and persistency in high level trigger, reconstruction and analysis

    NASA Astrophysics Data System (ADS)

    Innocente, V.; Silvestris, L.; Stickland, D.; CMS Software Group

    2001-10-01

    This paper describes the design of a resilient and flexible software architecture that has been developed to satisfy the data processing requirements of a large HEP experiment, CMS, currently being constructed at the LHC machine at CERN. We describe various components of a software framework that allows integration of physics modules and which can be easily adapted for use in different processing environments both real-time (online trigger) and offline (event reconstruction and analysis). Features such as the mechanisms for scheduling algorithms, configuring the application and managing the dependences among modules are described in detail. In particular, a major effort has been placed on providing a service for managing persistent data and the experience using a commercial ODBMS (Objectivity/DB) is therefore described in detail.

  1. Small Microprocessor for ASIC or FPGA Implementation

    NASA Technical Reports Server (NTRS)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  2. FPGA curved track fitter with very low resource usage

    SciTech Connect

    Wu, Jin-Yuan; Wang, M.; Gottschalk, E.; Shi, Z.; /Fermilab

    2006-11-01

    Standard least-squares curved track fitting process is tailored for FPGA implementation. The coefficients in the fitting matrices are carefully chosen so that only shift and accumulation operations are used in the process. The divisions and full multiplications are eliminated. Comparison in an application example shows that the fitting errors of the low resource usage implementation are less than 4% bigger than the fitting errors of the exact least-squares algorithm. The implementation is suitable for low-cost, low-power applications such as high energy physics detector trigger systems.

  3. STRS Compliant FPGA Waveform Development

    NASA Technical Reports Server (NTRS)

    Nappier, Jennifer; Downey, Joseph; Mortensen, Dale

    2008-01-01

    The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. The extension of STRS to the SSP hardware will promote easier waveform reconfiguration and reuse. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. A FPGA-based transmit waveform implementation of the proposed standard interfaces on a laboratory breadboard SDR will be discussed.

  4. Target-triggered triple isothermal cascade amplification strategy for ultrasensitive microRNA-21 detection at sub-attomole level.

    PubMed

    Cheng, Fang-Fang; Jiang, Nan; Li, Xiaoyan; Zhang, Li; Hu, Lihui; Chen, Xiaojun; Jiang, Li-Ping; Abdel-Halim, E S; Zhu, Jun-Jie

    2016-11-15

    MicroRNA-21 (miR-21) is a promising diagnostic biomarker for breast cancer screening and disease progression, thus the method for the sensitive and selective detection of miR-21 is vital to its clinical diagnosis. Herein, we develop a novel method to quantify miR-21 levels as low as attomolar sensitivity by a target-triggered triple isothermal cascade amplification (3TICA) strategy. An ingenious unimolecular DNA template with three functional parts has been designed: 5'-fragment as the miR-21 recognition unit, middle fragment as the miR-21 analogue amplification unit, and 3'-fragment as the 8-17 DNAzyme production unit. Triggered by miR-21 and accompanied by polymerase-nicking enzyme cascade, new miR-21 analogues autonomously generated for the successive re-triggering and cleavage process. Simultaneously, the 8-17 DNAzyme-contained sequence could be exponentially released and activated for the second cyclic cleavage toward a specific ribonucleotide (rA)-contained substrate, inducing a remarkably amplified generation of HRP-mimicking DNAzyme in the presence of hemin. Finally, the amperometric technique was used to record the catalytic reduction current of 3,3',5,5'-tetramethylbenzidine (TMB) in the presence of H2O2. The increase in the steady-state current was proportional with the increase of the miR-21 concentration from 1 aM to 100 pM. An ultra-low detection limit of 0.5 aM with an excellent selectivity for even discriminating differences between 1-base mismatched target and miR-21 was achieved. This simple and cost-effective 3TICA strategy is promising for the detection of any short oligonucleotides, simply by altering the target recognition unit in the template sequence.

  5. Critical width of tidal flats triggers marsh collapse in the absence of sea-level rise.

    PubMed

    Mariotti, Giulio; Fagherazzi, Sergio

    2013-04-01

    High rates of wave-induced erosion along salt marsh boundaries challenge the idea that marsh survival is dictated by the competition between vertical sediment accretion and relative sea-level rise. Because waves pounding marshes are often locally generated in enclosed basins, the depth and width of surrounding tidal flats have a pivoting control on marsh erosion. Here, we show the existence of a threshold width for tidal flats bordering salt marshes. Once this threshold is exceeded, irreversible marsh erosion takes place even in the absence of sea-level rise. This catastrophic collapse occurs because of the positive feedbacks among tidal flat widening by wave-induced marsh erosion, tidal flat deepening driven by wave bed shear stress, and local wind wave generation. The threshold width is determined by analyzing the 50-y evolution of 54 marsh basins along the US Atlantic Coast. The presence of a critical basin width is predicted by a dynamic model that accounts for both horizontal marsh migration and vertical adjustment of marshes and tidal flats. Variability in sediment supply, rather than in relative sea-level rise or wind regime, explains the different critical width, and hence erosion vulnerability, found at different sites. We conclude that sediment starvation of coastlines produced by river dredging and damming is a major anthropogenic driver of marsh loss at the study sites and generates effects at least comparable to the accelerating sea-level rise due to global warming. PMID:23513219

  6. Ultrasound-triggered regulation of blood glucose levels using injectable nano-network.

    PubMed

    Di, Jin; Price, Jennifer; Gu, Xiao; Jiang, Xiaoning; Jing, Yun; Gu, Zhen

    2014-06-01

    The integration of an injectable insulin-encapsulated nano-network with a focused ultrasound system (FUS) can remotely regulate insulin release both in vitro and in vivo. A single subcutaneous injection of the nano-network with intermittent FUS administration facilitates reduction of the blood glucose levels in type 1 diabetic mice for up to 10 d. PMID:24255016

  7. Critical width of tidal flats triggers marsh collapse in the absence of sea-level rise.

    PubMed

    Mariotti, Giulio; Fagherazzi, Sergio

    2013-04-01

    High rates of wave-induced erosion along salt marsh boundaries challenge the idea that marsh survival is dictated by the competition between vertical sediment accretion and relative sea-level rise. Because waves pounding marshes are often locally generated in enclosed basins, the depth and width of surrounding tidal flats have a pivoting control on marsh erosion. Here, we show the existence of a threshold width for tidal flats bordering salt marshes. Once this threshold is exceeded, irreversible marsh erosion takes place even in the absence of sea-level rise. This catastrophic collapse occurs because of the positive feedbacks among tidal flat widening by wave-induced marsh erosion, tidal flat deepening driven by wave bed shear stress, and local wind wave generation. The threshold width is determined by analyzing the 50-y evolution of 54 marsh basins along the US Atlantic Coast. The presence of a critical basin width is predicted by a dynamic model that accounts for both horizontal marsh migration and vertical adjustment of marshes and tidal flats. Variability in sediment supply, rather than in relative sea-level rise or wind regime, explains the different critical width, and hence erosion vulnerability, found at different sites. We conclude that sediment starvation of coastlines produced by river dredging and damming is a major anthropogenic driver of marsh loss at the study sites and generates effects at least comparable to the accelerating sea-level rise due to global warming.

  8. Between Product Development and Mass Production: Tensions as Triggers for Concept-Level Learning

    ERIC Educational Resources Information Center

    Jalonen, Meri; Ristimäki, Päivi; Toiviainen, Hanna; Pulkkis, Anneli; Lohtander, Mika

    2016-01-01

    Purpose: This paper aims to analyze learning in organizational transformations by focusing on concept-level tensions faced in two young companies, which were searching for a reorientation of activity with a production network between innovative product development and efficient mass production. Design/methodology/approach: An intervention-based…

  9. Fast particles identification in programmable form at level-0 trigger by means of the 3D-Flow system

    SciTech Connect

    Crosetto, Dario B.

    1998-10-30

    The 3D-Flow Processor system is a new, technology-independent concept in very fast, real-time system architectures. Based on either an FPGA or an ASIC implementation, it can address, in a fully programmable manner, applications where commercially available processors would fail because of throughput requirements. Possible applications include filtering-algorithms (pattern recognition) from the input of multiple sensors, as well as moving any input validated by these filtering-algorithms to a single output channel. Both operations can easily be implemented on a 3D-Flow system to achieve a real-time processing system with a very short lag time. This system can be built either with off-the-shelf FPGAs or, for higher data rates, with CMOS chips containing 4 to 16 processors each. The basic building block of the system, a 3D-Flow processor, has been successfully designed in VHDL code written in ''Generic HDL'' (mostly made of reusable blocks that are synthesizable in different technologies, or FPGAs), to produce a netlist for a four-processor ASIC featuring 0.35 micron CBA (Ceil Base Array) technology at 3.3 Volts, 884 mW power dissipation at 60 MHz and 63.75 mm sq. die size. The same VHDL code has been targeted to three FPGA manufacturers (Altera EPF10K250A, ORCA-Lucent Technologies 0R3T165 and Xilinx XCV1000). A complete set of software tools, the 3D-Flow System Manager, equally applicable to ASIC or FPGA implementations, has been produced to provide full system simulation, application development, real-time monitoring, and run-time fault recovery. Today's technology can accommodate 16 processors per chip in a medium size die, at a cost per processor of less than $5 based on the current silicon die/size technology cost.

  10. Reservoir Triggered Seismicity (RTS) and well water level response in the Koyna Warna region, India

    NASA Astrophysics Data System (ADS)

    Chadha, R. K.; Kuempel, H.-J.; Shekar, M.

    2008-08-01

    Water level fluctuations in twenty-one observation wells have been monitored for the last 10 years around the seismically active Koyna-Warna region, western India where earthquakes continue to occur even after four decades of the initiation of the seismic activity in the region. Fourteen of the observation wells act as volume strain meters as their water levels show earth tidal signals. Our analysis suggests three types of response of the well water levels to seismo-tectonic effects, i) one to local earthquakes, ii) to regional and teleseismic events, and iii) to local fluctuations in rock strain on regional scale. We observed five cases of co-seismic step-like well water level changes, of the order of few centimeters in amplitude, related to earthquakes in the magnitude range 4.3 ≤ M ≤ 5.2. All these earthquakes occurred within the network of wells drilled for the study and within 25 km distance of the recording wells. In three cases, drop in well levels preceded co-seismic step-like increases, which may be of premonitory nature. The second type of response is observed to be due to the passing of seismic waves from regional and teleseismic earthquakes like the M 7.7 Bhuj event on January 26, 2001 and the M 9.3 December 26, 2004 Sumatra earthquake. The third type is a well level anomaly of centimeter amplitude coherently occurring in several wells. The anomalies are similar in shape and last for several hours to days. From our studies we conclude that the wells in the network appear to respond to regional strain variations and transient changes due to distant earthquakes. The two factors which are important to co-seismic steps due to local earthquakes are the magnitude and epicentral distance. From the limited number of events we found that all local earthquakes exceeding M ≥ 4.3 have produced co-seismic changes. No such changes were observed for earthquakes below this magnitude threshold.

  11. TESLA cavity driving with FPGA controller

    NASA Astrophysics Data System (ADS)

    Czarski, Tomasz; Pozniak, Krzysztof; Romaniuk, Ryszard; Simrock, Stefan

    2005-09-01

    The digital control of the TESLA (TeV-Energy Superconducting Linear Accelerator) resonator is presented. The laboratory setup of the CHECHIA cavity in DESY-Hamburg has been driven by the FPGA (Field Programmable Gate Array) technology system. This experiment focused attention to the general recognition of the cavity features and projected control methods. The electrical model of the resonator is taken as a consideration origin. The calibration of the signal channel is considered as a key preparation for an efficient cavity driving. The identification of the resonator parameters is confirmed as a proper approach for the required performance: driving on resonance during filling and field stabilization during flattop time with reasonable power consumption. The feed-forward and feedback modes were applied successfully for the CHECHIA cavity driving. Representative results of experiments are presented for different levels of the cavity field gradient.

  12. The Development of FPGA-Based Pseudo-Iterative Clustering Algorithms

    NASA Astrophysics Data System (ADS)

    Drueke, Elizabeth; Fisher, Wade; Plucinski, Pawel

    2016-03-01

    The Large Hadron Collider (LHC) in Geneva, Switzerland, is set to undergo major upgrades in 2025 in the form of the High-Luminosity Large Hadron Collider (HL-LHC). In particular, several hardware upgrades are proposed to the ATLAS detector, one of the two general purpose detectors. These hardware upgrades include, but are not limited to, a new hardware-level clustering algorithm, to be performed by a field programmable gate array, or FPGA. In this study, we develop that clustering algorithm and compare the output to a Python-implemented topoclustering algorithm developed at the University of Oregon. Here, we present the agreement between the FPGA output and expected output, with particular attention to the time required by the FPGA to complete the algorithm and other limitations set by the FPGA itself.

  13. Validation of an FPGA fault simulator.

    SciTech Connect

    Wirthlin, M. J.; Johnson, D. E.; Graham, P. S.; Caffrey, M. P.

    2003-01-01

    This work describes the radiation testing of a fault simulation tool used to study the behavior of FPGA circuits in the presence of configuration memory upsets . There is increasing interest in the use of Field Programmable Gate Arrays (FPGAs) in space-based applications such as remote sensing[1] . The use of reconfigurable Field Programmable Gate Arrays (FPGAs) within a spacecraft allows the use of digital circuits that are both application-specific and reprogrammable. Unlike application-specific integrated circuits (ASICs), FPGAs can be configured after the spacecraft has been launched . This flexibility allows the same FPGA resources to be used for multiple instruments, missions, or changing spacecraft objectives . Errors in an FPGA design can be resolved by fixing the incorrect design and reconfiguring the FPGA with an updated configuration bitstream . Further, custom circuit designs can be created to avoid FPGA resources that have failed during the course of the spacecraft mission .

  14. An alert system for triggering different levels of coastal management urgency: Tunisia case study using rapid environmental assessment data.

    PubMed

    Price, A R G; Jaoui, K; Pearson, M P; Jeudy de Grissac, A

    2014-03-15

    Rapid environmental assessment (REA) involves scoring abundances of ecosystems/species groups and magnitude of pressures, concurrently, using the same logarithmic (0-6) assessment scale. We demonstrate the utility of REA data for an alert system identifying different levels of coastal management concern. Thresholds set for abundances/magnitudes, when crossed, trigger proposed responses. Kerkennah, Tunisia, our case study, has significant natural assets (e.g. exceptional seagrass and invertebrate abundances), subjected to varying levels of disturbance and management concern. Using REA thresholds set, fishing, green algae/eutrophication and oil occurred at 'low' levels (scores 0-1): management not (currently) necessary. Construction and wood litter prevailed at 'moderate' levels (scores 2-4): management alerted for (further) monitoring. Solid waste densities were 'high' (scores 5-6): management alerted for action; quantities of rubbish were substantial (20-200 items m⁻¹ beach) but not unprecedented. REA is considered a robust methodology and complementary to other rapid assessment techniques, environmental frameworks and indicators of ecosystem condition.

  15. Using modern software tools to design, simulate and test a Level 1 trigger sub-system for the D Zero Detector

    SciTech Connect

    Angstadt, R.; Borcherding, F.; Johnson, M.E.; Moreira, L.

    1995-06-01

    This paper describes a system which uses a commercial spreadsheet program and commercial hardware on an IBM PC to develop and test a track finding system for the D Zero Level 1 scintillating Fiber Trigger. The trigger system resides in a VME crate. This system allows the user to generate test input, write the pattern to the hardware simulate the results in software, read the hardware result: compare the results and inform the user of any differences.

  16. A new FPGA architecture suitable for DSP applications

    NASA Astrophysics Data System (ADS)

    Liyun, Wang; Jinmei, Lai; Jiarong, Tong; Pushan, Tang; Xing, Chen; Xueyan, Duan; Liguang, Chen; Jian, Wang; Yuan, Wang

    2011-05-01

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 μm CMOS technology successfully. The die size is 6.3 × 4.5 mm2 with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs.

  17. Review of parallel computing methods and tools for FPGA technology

    NASA Astrophysics Data System (ADS)

    Cieszewski, Radosław; Linczuk, Maciej; Pozniak, Krzysztof; Romaniuk, Ryszard

    2013-10-01

    Parallel computing is emerging as an important area of research in computer architectures and software systems. Many algorithms can be greatly accelerated using parallel computing techniques. Specialized parallel computer architectures are used for accelerating speci c tasks. High-Energy Physics Experiments measuring systems often use FPGAs for ne-grained computation. FPGA combines many bene ts of both software and ASIC implementations. Like software, the mapped circuit is exible, and can be recon gured over the lifetime of the system. FPGAs therefore have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. Creating parallel programs implemented in FPGAs is not trivial. This paper presents existing methods and tools for ne-grained computation implemented in FPGA using Behavioral Description and High Level Programming Languages.

  18. Monitoring the data quality of the real-time event reconstruction in the ALICE High Level Trigger

    NASA Astrophysics Data System (ADS)

    Austrheim Erdal, Hege; Richther, Matthias; Szostak, Artur; Toia, Alberica

    2012-12-01

    ALICE is a dedicated heavy ion experiment at the CERN LHC. The ALICE High Level Trigger was designed to select events with desirable physics properties. Data from several of the major subdetectors in ALICE are processed by the HLT for real-time event reconstruction, for instance the Inner Tracking System, the Time Projection Chamber, the electromagnetc calorimeters, the Transition Radiation Detector and the muon spectrometer. The HLT reconstructs events in real-time and thus provides input for trigger algorithms. It is necessary to monitor the quality of the reconstruction where one focuses on track and event properties. Also, HLT implemented data compression for the TPC during the heavy ion data taking in 2011 to reduce the data rate from the ALICE detector. The key for the data compression is to store clusters (spacepoints) calculated by HLT rather than storing raw data. It is thus very important to monitor the cluster finder performance as a way to monitor the data compression. The data monitoring is divided into two stages. The first stage is performed during data taking. A part of the HLT production chain is dedicated to performing online monitoring and facilities are available in the HLT production cluster to have real-time access to the reconstructed events in the ALICE control room. This includes track and event properties, and in addition, this facility gives a way to display a small fraction of the reconstructed events in an online display. The second part of the monitoring is performed after the data has been transferred to permanent storage. After a post-process of the real-time reconstructed data, one can look in more detail at the cluster finder performance, the quality of the reconstruction of tracks, vertices and vertex position. The monitoring solution is presented in detail, with special attention to the heavy ion data taking of 2011.

  19. STRS Compliant FPGA Waveform Development

    NASA Technical Reports Server (NTRS)

    Nappier, Jennifer; Downey, Joseph

    2008-01-01

    The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.

  20. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    NASA Astrophysics Data System (ADS)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  1. FPGA-based 10-Gbit Ethernet Data Acquisition Interface for the Upgraded Electronics of the ATLAS Liquid Argon Calorimeters

    NASA Astrophysics Data System (ADS)

    Grohs, J. Philipp; Atlas Liquid Argon calorimeter Group

    2014-06-01

    A stepwise upgrade of the LHC is foreseen starting now until the year 2023 to increase the instantaneous luminosity up to five times of its design value. It implies a challenge for the ATLAS experiment coping with the expected event pile-up, especially for the Level-1 calorimeter trigger system. In order to keep the trigger rates within the limited bandwidth new algorithms have to be applied which in turn requires an upgrade of the ATLAS Liquid Argon calorimeter trigger readout electronics. Towards this upgrade, the ATLAS Liquid Argon calorimeter group develops a high-speed data acquisition interface in ATCA standard using commercial hardware instead of complex and expensive in-house developments where possible. This paper gives an overview of the general concepts of the DAQ interface, the engaged technologies and the current status of the development efforts for an FPGA based fast data link with a standard 10 Gbps Ethernet protocol which may also be useful for DAQ systems of other high energy physics experiments.

  2. Association of Serum Soluble Triggering Receptor Expressed on Myeloid Cells Levels in Malignant Febrile Neutropenic Patients with Bacteremia and Fungemia

    PubMed Central

    Arzanian, Mohammad-Taghi; Soltani, Babak; Fahimzad, Alireza; Shiva, Farideh; Shamshiri, Ahmad-Reza; Karimi, Abdollah

    2011-01-01

    Objective Infections are the major cause of morbidity and mortality in febrile neutropenic patients with malignancy. Rapid diagnostic tests are needed for prompt diagnosis and early treatment which is crucial for optimal management. We assessed the utility of soluble triggering receptor expressed on myeloid cells (sTREM-1) in the diagnosis of bacteremia and fungemia in febrile neutropenic patients. Methods Sixty-five febrile neutropenic children with malignancy hospitalized in Mofid Children's Hospital during a period of one year from January 2007 were recruited for this cross sectional study (mean age 66.2± 37 months; 35 females and 30 males). Thirty patients (46.2%) had acute lymphoblastic leukemia, 2 (3.1%) acute myeloid leukemia, one (1.5%) lymphoma and 32 (49.2%) were under treatment for solid tumors. Simultaneous blood samples were collected for measurement of serum sTREM-1 levels and for blood cultures which were grown in BACTEC media. Gold standard for the presence of infection was a positive BACTEC culture as a more sensitive method compared to current blood culture techniques. Findings Blood cultures with BACTEC system were positive in 13(20%) patients (12 bacterial and one fungal culture). The mean serum sTREM-1 level in BACTEC positive patients was 948.2±592.9 pg/ml but in BACTEC negative cases it was 76.3±118.8 pg/ml (P<0.001). The optimal cut-off point of sTREM-1 for detecting patients with positive result of BACTEC was 525 pg/ml with sensitivity and specificity of 84.6% and 100%, respectively. Conclusion Our study revealed a significant association between serum sTREM-1 level and bacteremia and fungemia in febrile neutropenic patients suffering malignancy with acceptable sensitivity and specificity. PMID:23056805

  3. Fluoride-Triggered Ring-Opening of Photochromic Diarylpyrans into Merocyanine Dyes: Naked-Eye Sensing in Subppm Levels.

    PubMed

    Mukhopadhyay, Arindam; Maka, Vijay Kumar; Moorthy, Jarugu Narasimha

    2016-09-01

    The fluoride-mediated desilylation reaction has been exploited, for the first time, to trigger ring-opening of photochromic diarylbenzo-/naphthopyrans into highly colored anionic merocyanine dyes with high molar absorptivities to permit naked-eye sensing. The absorption spectral shifts, i.e., differences in the absorption maxima of colorless and colored forms, observed for a rationally designed set of silyloxy-substituted diarylpyrans subsequent to fluoride-induced ring opening are remarkably high (330-480 nm), and are unknown for any colorimetric probe. In particular, the disilyloxy-substituted diphenylnaphthopyran and its analog, in which the diphenyl groups are fused in the form of fluorene, allows "naked-eye" detection of fluoride in subppm levels (<1.0 ppm) in THF as well as in DMSO-H2O. The sensing is specific for fluoride among various other anions. This approach for colorimetric sensing of fluoride by ring-opening of the otherwise photochromic benzo-/naphthopyrans is heretofore unprecedented. PMID:27447293

  4. Fluoride-Triggered Ring-Opening of Photochromic Diarylpyrans into Merocyanine Dyes: Naked-Eye Sensing in Subppm Levels.

    PubMed

    Mukhopadhyay, Arindam; Maka, Vijay Kumar; Moorthy, Jarugu Narasimha

    2016-09-01

    The fluoride-mediated desilylation reaction has been exploited, for the first time, to trigger ring-opening of photochromic diarylbenzo-/naphthopyrans into highly colored anionic merocyanine dyes with high molar absorptivities to permit naked-eye sensing. The absorption spectral shifts, i.e., differences in the absorption maxima of colorless and colored forms, observed for a rationally designed set of silyloxy-substituted diarylpyrans subsequent to fluoride-induced ring opening are remarkably high (330-480 nm), and are unknown for any colorimetric probe. In particular, the disilyloxy-substituted diphenylnaphthopyran and its analog, in which the diphenyl groups are fused in the form of fluorene, allows "naked-eye" detection of fluoride in subppm levels (<1.0 ppm) in THF as well as in DMSO-H2O. The sensing is specific for fluoride among various other anions. This approach for colorimetric sensing of fluoride by ring-opening of the otherwise photochromic benzo-/naphthopyrans is heretofore unprecedented.

  5. Copper(II)-Graphitic Carbon Nitride Triggered Synergy: Improved ROS Generation and Reduced Glutathione Levels for Enhanced Photodynamic Therapy.

    PubMed

    Ju, Enguo; Dong, Kai; Chen, Zhaowei; Liu, Zhen; Liu, Chaoqun; Huang, Yanyan; Wang, Zhenzhen; Pu, Fang; Ren, Jinsong; Qu, Xiaogang

    2016-09-12

    Graphitic carbon nitride (g-C3 N4 ) has been used as photosensitizer to generate reactive oxygen species (ROS) for photodynamic therapy (PDT). However, its therapeutic efficiency was far from satisfactory. One of the major obstacles was the overexpression of glutathione (GSH) in cancer cells, which could diminish the amount of generated ROS before their arrival at the target site. Herein, we report that the integration of Cu(2+) and g-C3 N4 nanosheets (Cu(2+) -g-C3 N4 ) led to enhanced light-triggered ROS generation as well as the depletion of intracellular GSH levels. Consequently, the ROS generated under light irradiation could be consumed less by reduced GSH, and efficiency was improved. Importantly, redox-active species Cu(+) -g-C3 N4 could catalyze the reduction of molecular oxygen to the superoxide anion or hydrogen peroxide to the hydroxyl radical, both of which facilitated the generation of ROS. This synergy of improved ROS generation and GSH depletion could enhance the efficiency of PDT for cancer therapy.

  6. Rad-Hard/HI-REL FPGA

    NASA Technical Reports Server (NTRS)

    Wang, Jih-Jong; Cronquist, Brian E.; McGowan, John E.; Katz, Richard B.

    1997-01-01

    The goals for a radiation hardened (RAD-HARD) and high reliability (HI-REL) field programmable gate array (FPGA) are described. The first qualified manufacturer list (QML) radiation hardened RH1280 and RH1020 were developed. The total radiation dose and single event effects observed on the antifuse FPGA RH1280 are reported on. Tradeoffs and the limitations in the single event upset hardening are discussed.

  7. Tethered Forth system for FPGA applications

    NASA Astrophysics Data System (ADS)

    Goździkowski, Paweł; Zabołotny, Wojciech M.

    2013-10-01

    This paper presents the tethered Forth system dedicated for testing and debugging of FPGA based electronic systems. Use of the Forth language allows to interactively develop and run complex testing or debugging routines. The solution is based on a small, 16-bit soft core CPU, used to implement the Forth Virtual Machine. Thanks to the use of the tethered Forth model it is possible to minimize usage of the internal RAM memory in the FPGA. The function of the intelligent terminal, which is an essential part of the tethered Forth system, may be fulfilled by the standard PC computer or by the smartphone. System is implemented in Python (the software for intelligent terminal), and in VHDL (the IP core for FPGA), so it can be easily ported to different hardware platforms. The connection between the terminal and FPGA may be established and disconnected many times without disturbing the state of the FPGA based system. The presented system has been verified in the hardware, and may be used as a tool for debugging, testing and even implementing of control algorithms for FPGA based systems.

  8. OpenACC to FPGA: A Framework for Directive-based High-Performance Reconfigurable Computing

    SciTech Connect

    Lee, Seyong; Vetter, Jeffrey S

    2016-01-01

    This paper presents a directive-based, high-level programming framework for high-performance reconfigurable computing. It takes a standard, portable OpenACC C program as input and generates a hardware configuration file for execution on FPGAs. We implemented this prototype system using our open-source OpenARC compiler; it performs source-to-source translation and optimization of the input OpenACC program into an OpenCL code, which is further compiled into a FPGA program by the backend Altera Offline OpenCL compiler. Internally, the design of OpenARC uses a high- level intermediate representation that separates concerns of program representation from underlying architectures, which facilitates portability of OpenARC. In fact, this design allowed us to create the OpenACC-to-FPGA translation framework with minimal extensions to our existing system. In addition, we show that our proposed FPGA-specific compiler optimizations and novel OpenACC pragma extensions assist the compiler in generating more efficient FPGA hardware configuration files. Our empirical evaluation on an Altera Stratix V FPGA with eight OpenACC benchmarks demonstrate the benefits of our strategy. To demonstrate the portability of OpenARC, we show results for the same benchmarks executing on other heterogeneous platforms, including NVIDIA GPUs, AMD GPUs, and Intel Xeon Phis. This initial evidence helps support the goal of using a directive-based, high-level programming strategy for performance portability across heterogeneous HPC architectures.

  9. A 96-channel FPGA-based time-to-digital converter

    SciTech Connect

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Phillips, Thomas J; Wilson, Peter

    2005-02-01

    We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA’s. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

  10. A FPGA embedded web server for remote monitoring and control of smart sensors networks.

    PubMed

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2013-01-01

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

  11. A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

    PubMed Central

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2014-01-01

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

  12. A FPGA embedded web server for remote monitoring and control of smart sensors networks.

    PubMed

    Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

    2013-12-27

    This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

  13. Synthesis of blind source separation algorithms on reconfigurable FPGA platforms

    NASA Astrophysics Data System (ADS)

    Du, Hongtao; Qi, Hairong; Szu, Harold H.

    2005-03-01

    Recent advances in intelligence technology have boosted the development of micro- Unmanned Air Vehicles (UAVs) including Sliver Fox, Shadow, and Scan Eagle for various surveillance and reconnaissance applications. These affordable and reusable devices have to fit a series of size, weight, and power constraints. Cameras used on such micro-UAVs are therefore mounted directly at a fixed angle without any motion-compensated gimbals. This mounting scheme has resulted in the so-called jitter effect in which jitter is defined as sub-pixel or small amplitude vibrations. The jitter blur caused by the jitter effect needs to be corrected before any other processing algorithms can be practically applied. Jitter restoration has been solved by various optimization techniques, including Wiener approximation, maximum a-posteriori probability (MAP), etc. However, these algorithms normally assume a spatial-invariant blur model that is not the case with jitter blur. Szu et al. developed a smart real-time algorithm based on auto-regression (AR) with its natural generalization of unsupervised artificial neural network (ANN) learning to achieve restoration accuracy at the sub-pixel level. This algorithm resembles the capability of the human visual system, in which an agreement between the pair of eyes indicates "signal", otherwise, the jitter noise. Using this non-statistical method, for each single pixel, a deterministic blind sources separation (BSS) process can then be carried out independently based on a deterministic minimum of the Helmholtz free energy with a generalization of Shannon's information theory applied to open dynamic systems. From a hardware implementation point of view, the process of jitter restoration of an image using Szu's algorithm can be optimized by pixel-based parallelization. In our previous work, a parallelly structured independent component analysis (ICA) algorithm has been implemented on both Field Programmable Gate Array (FPGA) and Application

  14. Target-aptamer binding triggered quadratic recycling amplification for highly specific and ultrasensitive detection of antibiotics at the attomole level.

    PubMed

    Wang, Hongzhi; Wang, Yu; Liu, Su; Yu, Jinghua; Xu, Wei; Guo, Yuna; Huang, Jiadong

    2015-05-14

    A novel electrochemical aptasensor for ultrasensitive detection of antibiotics by combining polymerase-assisted target recycling amplification with strand displacement amplification with the help of polymerase and nicking endonuclease has been reported. This work is the first time that target-aptamer binding triggered quadratic recycling amplification has been utilized for electrochemical detection of antibiotics.

  15. Single Event Transients in Voltage Regulators for FPGA Power Supply Applications

    NASA Technical Reports Server (NTRS)

    Poivey, Christian; Sanders, Anthony; Kim, Hak; Phan, Anthony; Forney, Jim; LaBel, Kenneth A.; Karsh, Jeremy; Pursley, Scott; Kleyner, Igor; Katz, Richard

    2006-01-01

    As with other bipolar analog devices, voltage regulators are known to be sensitive to single event transients (SET). In typical applications, large output capacitors are used to provide noise immunity. Therefore, since SET amplitude and duration are generally small, they are often of secondary importance due to this capacitance filtering. In low voltage applications, however, even small SET are a concern. Over-voltages may cause destructive conditions. Under-voltages may cause functional interrupts and may also trigger electrical latchup conditions. In addition, internal protection circuits which are affected by load as well as internal thermal effects can also be triggered from heavy ions, causing dropouts or shutdown ranging from milliseconds to seconds. In the case of FPGA power supplies applications, SETS are critical. For example, in the case of Actel FPGA RTAX family, core power supply voltage is 1.5V. Manufacturer specifies an absolute maximum rating of 1.6V and recommended operating conditions between 1.425V and 1.575V. Therefore, according to the manufacturer, any transient of amplitude greater than 75 mV can disrupt normal circuit functions, and overvoltages greater than 100 mV may damage the FPGA. We tested five low dropout voltage regulators for SET sensitivity under a large range of circuit application conditions.

  16. Real-time windowing in imaging radar using FPGA technique

    NASA Astrophysics Data System (ADS)

    Ponomaryov, Volodymyr I.; Escamilla-Hernandez, Enrique

    2005-02-01

    The imaging radar uses the high frequency electromagnetic waves reflected from different objects for estimating of its parameters. Pulse compression is a standard signal processing technique used to minimize the peak transmission power and to maximize SNR, and to get a better resolution. Usually the pulse compression can be achieved using a matched filter. The level of the side-lobes in the imaging radar can be reduced using the special weighting function processing. There are very known different weighting functions: Hamming, Hanning, Blackman, Chebyshev, Blackman-Harris, Kaiser-Bessel, etc., widely used in the signal processing applications. Field Programmable Gate Arrays (FPGAs) offers great benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. This reconfiguration makes FPGAs a better solution over custom-made integrated circuits. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal and pulse compression using Matlab, Simulink, and System Generator. Employing FPGA and mentioned software we have proposed the pulse compression design on FPGA using classical and novel windows technique to reduce the side-lobes level. This permits increasing the detection ability of the small or nearly placed targets in imaging radar. The advantage of FPGA that can do parallelism in real time processing permits to realize the proposed algorithms. The paper also presents the experimental results of proposed windowing procedure in the marine radar with such the parameters: signal is linear FM (Chirp); frequency deviation DF is 9.375MHz; the pulse width T is 3.2μs taps number in the matched filter is 800 taps; sampling frequency 253.125*106 MHz. It has been realized the reducing of side-lobes levels in real time permitting better resolution of the small targets.

  17. FPGA based Smart Wireless MIMO Control System

    NASA Astrophysics Data System (ADS)

    Usman Ali, Syed M.; Hussain, Sajid; Akber Siddiqui, Ali; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-12-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

  18. Optoelectronic date acquisition system based on FPGA

    NASA Astrophysics Data System (ADS)

    Li, Xin; Liu, Chunyang; Song, De; Tong, Zhiguo; Liu, Xiangqing

    2015-11-01

    An optoelectronic date acquisition system is designed based on FPGA. FPGA chip that is EP1C3T144C8 of Cyclone devices from Altera corporation is used as the centre of logic control, XTP2046 chip is used as A/D converter, host computer that communicates with the date acquisition system through RS-232 serial communication interface are used as display device and photo resistance is used as photo sensor. We use Verilog HDL to write logic control code about FPGA. It is proved that timing sequence is correct through the simulation of ModelSim. Test results indicate that this system meets the design requirement, has fast response and stable operation by actual hardware circuit test.

  19. Common Asthma Triggers

    MedlinePlus

    ... your bedding on the hottest water setting. Outdoor Air Pollution Outdoor air pollution can trigger an asthma attack. This pollution can ... your newspaper to plan your activities for when air pollution levels will be low. Cockroach Allergen Cockroaches and ...

  20. FPGA implementation of vision algorithms for small autonomous robots

    NASA Astrophysics Data System (ADS)

    Anderson, J. D.; Lee, D. J.; Archibald, J. K.

    2005-10-01

    The use of on-board vision with small autonomous robots has been made possible by the advances in the field of Field Programmable Gate Array (FPGA) technology. By connecting a CMOS camera to an FPGA board, on-board vision has been used to reduce the computation time inherent in vision algorithms. The FPGA board allows the user to create custom hardware in a faster, safer, and more easily verifiable manner that decreases the computation time and allows the vision to be done in real-time. Real-time vision tasks for small autonomous robots include object tracking, obstacle detection and avoidance, and path planning. Competitions were created to demonstrate that our algorithms work with our small autonomous vehicles in dealing with these problems. These competitions include Mouse-Trapped-in-a-Box, where the robot has to detect the edges of a box that it is trapped in and move towards them without touching them; Obstacle Avoidance, where an obstacle is placed at any arbitrary point in front of the robot and the robot has to navigate itself around the obstacle; Canyon Following, where the robot has to move to the center of a canyon and follow the canyon walls trying to stay in the center; the Grand Challenge, where the robot had to navigate a hallway and return to its original position in a given amount of time; and Stereo Vision, where a separate robot had to catch tennis balls launched from an air powered cannon. Teams competed on each of these competitions that were designed for a graduate-level robotic vision class, and each team had to develop their own algorithm and hardware components. This paper discusses one team's approach to each of these problems.

  1. Experiences on 64 and 150 FPGA Systems

    SciTech Connect

    Storaasli, Olaf O; Strenski, Dave

    2008-01-01

    Four FPGA systems were evaluated: the Cray XD1 system with 6 FPGAs at ORNL and Cray, the Cray XD1 system with 150 FPGAs at NRL* and the 64 FPGAs on Edinburgh s Maxwell . Their hardware and software architectures, programming tools and performance on scientific applications are discussed. FPGA speedup (over a 2.2 GHz Opteron) of 10X was typical for matrix equation solution, molecular dynamics and weather/climate codes and upto 100X for human genome DNA sequencing. Large genome comparisons requiring 12.5 years for an Opteron took less than 24 hours on NRL s Cray XD1 with 150 Virtex FPGAs for a 7,350X speedup. pipeline so each query and database character are compared in parallel, resulting in a table of scores. Genome Sequencing Results: FPGA timing results (for up to 150 FPGAs) were obtained and compared with up to 150 Opterons for sequences of varying size and complexity (e.g. 4GB openfpga.org human DNA benchmark and 155M human vs. 166M mouse DNA). 1 FPGA: Bacillus_anthracis DNA compare: Genomes

  2. FPGA Sequencer for Radar Altimeter Applications

    NASA Technical Reports Server (NTRS)

    Berkun, Andrew C.; Pollard, Brian D.; Chen, Curtis W.

    2011-01-01

    A sequencer for a radar altimeter provides accurate attitude information for a reliable soft landing of the Mars Science Laboratory (MSL). This is a field-programmable- gate-array (FPGA)-only implementation. A table loaded externally into the FPGA controls timing, processing, and decision structures. Radar is memory-less and does not use previous acquisitions to assist in the current acquisition. All cycles complete in exactly 50 milliseconds, regardless of range or whether a target was found. A RAM (random access memory) within the FPGA holds instructions for up to 15 sets. For each set, timing is run, echoes are processed, and a comparison is made. If a target is seen, more detailed processing is run on that set. If no target is seen, the next set is tried. When all sets have been run, the FPGA terminates and waits for the next 50-millisecond event. This setup simplifies testing and improves reliability. A single vertex chip does the work of an entire assembly. Output products require minor processing to become range and velocity. This technology is the heart of the Terminal Descent Sensor, which is an integral part of the Entry Decent and Landing system for MSL. In addition, it is a strong candidate for manned landings on Mars or the Moon.

  3. Testing Microshutter Arrays Using Commercial FPGA Hardware

    NASA Technical Reports Server (NTRS)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  4. GPU/MIC Acceleration of the LHC High Level Trigger to Extend the Physics Reach at the LHC

    SciTech Connect

    Halyo, Valerie; Tully, Christopher

    2015-04-14

    The quest for rare new physics phenomena leads the PI [3] to propose evaluation of coprocessors based on Graphics Processing Units (GPUs) and the Intel Many Integrated Core (MIC) architecture for integration into the trigger system at LHC. This will require development of a new massively parallel implementation of the well known Combinatorial Track Finder which uses the Kalman Filter to accelerate processing of data from the silicon pixel and microstrip detectors and reconstruct the trajectory of all charged particles down to momentums of 100 MeV. It is expected to run at least one order of magnitude faster than an equivalent algorithm on a quad core CPU for extreme pileup scenarios of 100 interactions per bunch crossing. The new tracking algorithms will be developed and optimized separately on the GPU and Intel MIC and then evaluated against each other for performance and power efficiency. The results will be used to project the cost of the proposed hardware architectures for the HLT server farm, taking into account the long term projections of the main vendors in the market (AMD, Intel, and NVIDIA) over the next 10 years. Extensive experience and familiarity of the PI with the LHC tracker and trigger requirements led to the development of a complementary tracking algorithm that is described in [arxiv: 1305.4855], [arxiv: 1309.6275] and preliminary results accepted to JINST.

  5. Experimental evidence for seismically initiated gas bubble nucleation and growth in groundwater as a mechanism for coseismic borehole water level rise and remotely triggered seismicity

    NASA Astrophysics Data System (ADS)

    Crews, Jackson B.; Cooper, Clay A.

    2014-09-01

    Changes in borehole water levels and remotely triggered seismicity occur in response to near and distant earthquakes at locations around the globe, but the mechanisms for these phenomena are not well understood. Experiments were conducted to show that seismically initiated gas bubble growth in groundwater can trigger a sustained increase in pore fluid pressure consistent in magnitude with observed coseismic borehole water level rise, constituting a physically plausible mechanism for remote triggering of secondary earthquakes through the reduction of effective stress in critically loaded geologic faults. A portion of the CO2 degassing from the Earth's crust dissolves in groundwater where seismic Rayleigh and P waves cause dilational strain, which can reduce pore fluid pressure to or below the bubble pressure, triggering CO2 gas bubble growth in the saturated zone, indicated by a spontaneous buildup of pore fluid pressure. Excess pore fluid pressure was measured in response to the application of 0.1-1.0 MPa, 0.01-0.30 Hz confining stress oscillations to a Berea sandstone core flooded with initially subsaturated aqueous CO2, under conditions representative of a confined aquifer. Confining stress oscillations equivalent to the dynamic stress of the 28 June 1992 Mw 7.3 Landers, California, earthquake Rayleigh wave as it traveled through the Long Valley caldera, and Parkfield, California, increased the pore fluid pressure in the Berea core by an average of 36 ± 15 cm and 23 ± 15 cm of equivalent freshwater head, respectively, in agreement with 41.8 cm and 34 cm rises recorded in wells at those locations.

  6. Trigger finger

    MedlinePlus

    ... Redness in your cut or hand Swelling or warmth in your cut or hand Yellow or green drainage from the cut Hand pain or discomfort Fever If your trigger finger returns, call your surgeon. You may need another surgery.

  7. The LHCb Trigger System

    NASA Astrophysics Data System (ADS)

    Rodrigues, E.; LHCb Collaboration

    2007-08-01

    The LHCb detector has been conceived to study with high precision CP violation and rare decays of b-flavoured hadrons produced at the LHC. The LHCb trigger is of crucial importance in selecting the collisions of interest for b-physics studies. The trigger is based on a two-level system. The first level, Level-0, is implemented in hardware and uses information from the calorimeter, muon and pile-up systems to select events containing particles with relatively large transverse momentum, typically above 1-2 GeV. The Level-0 trigger accepts events at a rate of 1 MHz. All the detector information is then read out and fed into the High Level Trigger. This software trigger runs in the event-filter farm composed of about 1800 CPU nodes. Events are selected at a rate of 2 kHz and sent for mass storage and subsequent offline reconstruction and analysis. The current status and expected performance of the trigger system are described.

  8. FPGA Coprocessor for Accelerated Classification of Images

    NASA Technical Reports Server (NTRS)

    Pingree, Paula J.; Scharenbroich, Lucas J.; Werne, Thomas A.

    2008-01-01

    An effort related to that described in the preceding article focuses on developing a spaceborne processing platform for fast and accurate onboard classification of image data, a critical part of modern satellite image processing. The approach again has been to exploit the versatility of recently developed hybrid Virtex-4FX field-programmable gate array (FPGA) to run diverse science applications on embedded processors while taking advantage of the reconfigurable hardware resources of the FPGAs. In this case, the FPGA serves as a coprocessor that implements legacy C-language support-vector-machine (SVM) image-classification algorithms to detect and identify natural phenomena such as flooding, volcanic eruptions, and sea-ice break-up. The FPGA provides hardware acceleration for increased onboard processing capability than previously demonstrated in software. The original C-language program demonstrated on an imaging instrument aboard the Earth Observing-1 (EO-1) satellite implements a linear-kernel SVM algorithm for classifying parts of the images as snow, water, ice, land, or cloud or unclassified. Current onboard processors, such as on EO-1, have limited computing power, extremely limited active storage capability and are no longer considered state-of-the-art. Using commercially available software that translates C-language programs into hardware description language (HDL) files, the legacy C-language program, and two newly formulated programs for a more capable expanded-linear-kernel and a more accurate polynomial-kernel SVM algorithm, have been implemented in the Virtex-4FX FPGA. In tests, the FPGA implementations have exhibited significant speedups over conventional software implementations running on general-purpose hardware.

  9. Parallel Hough Transform-based straight line detection and its FPGA implementation in embedded vision.

    PubMed

    Lu, Xiaofeng; Song, Li; Shen, Sumin; He, Kang; Yu, Songyu; Ling, Nam

    2013-07-17

    Hough Transform has been widely used for straight line detection in low-definition and still images, but it suffers from execution time and resource requirements. Field Programmable Gate Arrays (FPGA) provide a competitive alternative for hardware acceleration to reap tremendous computing performance. In this paper, we propose a novel parallel Hough Transform (PHT) and FPGA architecture-associated framework for real-time straight line detection in high-definition videos. A resource-optimized Canny edge detection method with enhanced non-maximum suppression conditions is presented to suppress most possible false edges and obtain more accurate candidate edge pixels for subsequent accelerated computation. Then, a novel PHT algorithm exploiting spatial angle-level parallelism is proposed to upgrade computational accuracy by improving the minimum computational step. Moreover, the FPGA based multi-level pipelined PHT architecture optimized by spatial parallelism ensures real-time computation for 1,024 × 768 resolution videos without any off-chip memory consumption. This framework is evaluated on ALTERA DE2-115 FPGA evaluation platform at a maximum frequency of 200 MHz, and it can calculate straight line parameters in 15.59 ms on the average for one frame. Qualitative and quantitative evaluation results have validated the system performance regarding data throughput, memory bandwidth, resource, speed and robustness.

  10. Triggering Klystrons

    SciTech Connect

    Stefan, Kelton D.; /Purdue U. /SLAC

    2010-08-25

    To determine if klystrons will perform to the specifications of the LCLS (Linac Coherent Light Source) project, a new digital trigger controller is needed for the Klystron/Microwave Department Test Laboratory. The controller needed to be programmed and Windows based user interface software needed to be written to interface with the device over a USB (Universal Serial Bus). Programming the device consisted of writing logic in VHDL (VHSIC (Very High Speed Integrated Circuits) hardware description language), and the Windows interface software was written in C++. Xilinx ISE (Integrated Software Environment) was used to compile the VHDL code and program the device, and Microsoft Visual Studio 2005 was used to compile the C++ based Windows software. The device was programmed in such a way as to easily allow read/write operations to it using a simple addressing model, and Windows software was developed to interface with the device over a USB connection. A method of setting configuration registers in the trigger device is absolutely necessary to the development of a new triggering system, and the method developed will fulfill this need adequately. More work is needed before the new trigger system is ready for use. The configuration registers in the device need to be fully integrated with the logic that will generate the RF signals, and this system will need to be tested extensively to determine if it meets the requirements for low noise trigger outputs.

  11. Trigger and Readout System for the Ashra-1 Detector

    NASA Astrophysics Data System (ADS)

    Aita, Y.; Aoki, T.; Asaoka, Y.; Morimoto, Y.; Motz, H. M.; Sasaki, M.; Abiko, C.; Kanokohata, C.; Ogawa, S.; Shibuya, H.; Takada, T.; Kimura, T.; Learned, J. G.; Matsuno, S.; Kuze, S.; Binder, P. M.; Goldman, J.; Sugiyama, N.; Watanabe, Y.

    Highly sophisticated trigger and readout system has been developed for All-sky Survey High Resolution Air-shower (Ashra) detector. Ashra-1 detector has 42 degree diameter field of view. Detection of Cherenkov and fluorescence light from large background in the large field of view requires finely segmented and high speed trigger and readout system. The system is composed of optical fiber image transmission system, 64 × 64 channel trigger sensor and FPGA based trigger logic processor. The system typically processes the image within 10 to 30 ns and opens the shutter on the fine CMOS sensor. 64 × 64 coarse split image is transferred via 64 × 64 precisely aligned optical fiber bundle to a photon sensor. Current signals from the photon sensor are discriminated by custom made trigger amplifiers. FPGA based processor processes 64 × 64 hit pattern and correspondent partial area of the fine image is acquired. Commissioning earth skimming tau neutrino observational search was carried out with this trigger system. In addition to the geometrical advantage of the Ashra observational site, the excellent tau shower axis measurement based on the fine imaging and the night sky background rejection based on the fine and fast imaging allow zero background tau shower search. Adoption of the optical fiber bundle and trigger LSI realized 4k channel trigger system cheaply. Detectability of tau shower is also confirmed by simultaneously observed Cherenkov air shower. Reduction of the trigger threshold appears to enhance the effective area especially in PeV tau neutrino energy region. New two dimensional trigger LSI was introduced and the trigger threshold was lowered. New calibration system of the trigger system was recently developed and introduced to the Ashra detector

  12. FPGA Based Reconfigurable ATM Switch Test Bed

    NASA Technical Reports Server (NTRS)

    Chu, Pong P.; Jones, Robert E.

    1998-01-01

    Various issues associated with "FPGA Based Reconfigurable ATM Switch Test Bed" are presented in viewgraph form. Specific topics include: 1) Network performance evaluation; 2) traditional approaches; 3) software simulation; 4) hardware emulation; 5) test bed highlights; 6) design environment; 7) test bed architecture; 8) abstract sheared-memory switch; 9) detailed switch diagram; 10) traffic generator; 11) data collection circuit and user interface; 12) initial results; and 13) the following conclusions: Advances in FPGA make hardware emulation feasible for performance evaluation, hardware emulation can provide several orders of magnitude speed-up over software simulation; due to the complexity of hardware synthesis process, development in emulation is much more difficult than simulation and requires knowledge in both networks and digital design.

  13. An FPGA-Based Electronic Cochlea

    NASA Astrophysics Data System (ADS)

    Leong, M. P.; Jin, Craig T.; Leong, Philip H. W.

    2003-12-01

    A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  14. FPGA implementation of robust Capon beamformer

    NASA Astrophysics Data System (ADS)

    Guan, Xin; Zmuda, Henry; Li, Jian; Du, Lin; Sheplak, Mark

    2012-03-01

    The Capon Beamforming algorithm is an optimal spatial filtering algorithm used in various signal processing applications where excellent interference rejection performance is required, such as Radar and Sonar systems, Smart Antenna systems for wireless communications. Its lack of robustness, however, means that it is vulnerable to array calibration errors and other model errors. To overcome this problem, numerous robust Capon Beamforming algorithms have been proposed, which are much more promising for practical applications. In this paper, an FPGA implementation of a robust Capon Beamforming algorithm is investigated and presented. This realization takes an array output with 4 channels, computes the complex-valued adaptive weight vectors for beamforming with an 18 bit fixed-point representation and runs at a 100 MHz clock on Xilinx V4 FPGA. This work will be applied in our medical imaging project for breast cancer detection.

  15. EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER.

    SciTech Connect

    HOFF, L.T.

    2005-10-10

    The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control.

  16. Diethyldithiocarbamate induces apoptosis in neuroblastoma cells by raising the intracellular copper level, triggering cytochrome c release and caspase activation.

    PubMed

    Matias, Andreza C; Manieri, Tânia M; Cipriano, Samantha S; Carioni, Vivian M O; Nomura, Cassiana S; Machado, Camila M L; Cerchiaro, Giselle

    2013-02-01

    Dithiocarbamates are nitrogen- and sulfur-containing compounds commonly used in pharmacology, medicine and agriculture. The molecular effects of dithiocarbamates on neuronal cell systems are not fully understood, especially in terms of their ability to accumulate copper ions inside the cell. In this work, the molecular effects of N,N-diethyldithiocarbamate (DEDTC) were studied in human SH-SY5Y neuroblastoma cells to determine the role of copper in the DEDTC toxicity and the pathway trigged in cell by the complex Cu-DEDTC. From concentration-dependent studies, we found that 5 μM of this compound induced a drastic decrease in viable cells with a concomitant accumulation in intracellular copper resulted from complexation with DEDTC, measured by atomic absorption spectroscopy. The mechanism of DEDTC-induced apoptosis in neuronal model cells is thought to occur through the death receptor signaling triggered by DEDTC-copper complex in low concentration that is associated with the activation of caspase 8. Our results indicated that the mechanism of cell death involves cytochrome c release forming the apoptosome together with Apaf-1 and caspase 9, converting the caspase 9 into its active form, allowing it to activate caspase 3 as observed by immunofluorescence. This pathway is induced by the cytotoxic effects that occur when DEDTC forms a complex with the copper ions present in the culture medium and transports them into the cell, suggesting that the DEDTC by itself was not able to cause cell death and the major effect is from its copper-complex in neuroblastoma cells. The present study suggests a role for the influence of copper by low concentrations of DEDTC in the extracellular media, the absorption and accumulation of copper in the cell and apoptotic events, induced by the cytotoxic effects that occur when DEDTC forms a complex with the copper ions. PMID:22951949

  17. Development and implementation of optimal filtering in a Virtex FPGA for the upgrade of the ATLAS LAr calorimeter readout

    NASA Astrophysics Data System (ADS)

    Stärz, S.

    2012-12-01

    In the context of upgraded read-out systems for the Liquid-Argon Calorimeters of the ATLAS detector, modified front-end, back-end and trigger electronics are foreseen for operation in the high-luminosity phase of the LHC. Accuracy and efficiency of the energy measurement and reliability of pile-up suppression are substantial when processing the detector raw-data in real-time. Several digital filter algorithms are investigated for their performance to extract energies from incoming detector signals and for the needs of the future trigger system. The implementation of fast, resource economizing, parameter driven filter algorithms in a modern Virtex FPGA is presented.

  18. FPGA Flash Memory High Speed Data Acquisition

    NASA Technical Reports Server (NTRS)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  19. Implementing a Digital Phasemeter in an FPGA

    NASA Technical Reports Server (NTRS)

    Rao, Shanti R.

    2008-01-01

    Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses, the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains. The firmware also does the following: Causes the FPGA to compute the frequencies of the input signals; Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and Provides data for use in diagnosis of communication failures. The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.

  20. FPGA Implementation of Heart Rate Monitoring System.

    PubMed

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  1. FPGA Implementation of Heart Rate Monitoring System.

    PubMed

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA. PMID:26643079

  2. Fluence-dependent effects of low-level laser therapy in myofascial trigger spots on modulation of biochemicals associated with pain in a rabbit model.

    PubMed

    Hsieh, Yueh-Ling; Hong, Chang-Zern; Chou, Li-Wei; Yang, Shun-An; Yang, Chen-Chia

    2015-01-01

    Evidence strongly supports that low-level laser therapy (LLLT) is an effective physical modality for the treatment of pain associated with myofascial trigger points (MTrP). However, the effect of laser fluence (energy intensity in J/cm(2)) on biochemical regulation related to pain is unclear. To better understand the biochemical mechanisms modulated by high- and low-fluence LLLT at myofascial trigger spots (MTrSs; similar to human MTrPs) in skeletal muscles of rabbits, the levels of β-endorphin (β-ep), substance P (SP), tumor necrosis factor-α (TNF-α), and cyclooxygenase-2 (COX-2) were investigated in this study. New Zealand rabbits (2.5-3.0 kg in weight) were used in this study. High-fluence LLLT (27 J/cm(2)), low-fluence LLLT (4.5 J/cm(2)), or sham operations were applied on MTrSs of biceps femoris of rabbits for five sessions (one session per day). Effects of LLLT at two different fluences on biceps femoris, dorsal root ganglion (DRG), and serum were determined by β-ep, SP, TNF-α, and COX-2 immunoassays. LLLT irradiation with fluences of 4.5 and 27 J/cm(2) at MTrSs can significantly reduce SP level in DRG. LLLT with lower fluence of 4.5 J/cm(2) exerted lower levels of TNF-α and COX-2 expression in laser-treated muscle, but LLLT with higher fluence of 27 J/cm(2) elevated the levels of β-ep in serum, DRG, and muscle. This study demonstrated fluence-dependent biochemical effects of LLLT in an animal model on management of myofascial pain. The findings can contribute to the development of dosage guideline for LLLT for treating MTrP-induced pain. PMID:25190639

  3. Fluence-dependent effects of low-level laser therapy in myofascial trigger spots on modulation of biochemicals associated with pain in a rabbit model.

    PubMed

    Hsieh, Yueh-Ling; Hong, Chang-Zern; Chou, Li-Wei; Yang, Shun-An; Yang, Chen-Chia

    2015-01-01

    Evidence strongly supports that low-level laser therapy (LLLT) is an effective physical modality for the treatment of pain associated with myofascial trigger points (MTrP). However, the effect of laser fluence (energy intensity in J/cm(2)) on biochemical regulation related to pain is unclear. To better understand the biochemical mechanisms modulated by high- and low-fluence LLLT at myofascial trigger spots (MTrSs; similar to human MTrPs) in skeletal muscles of rabbits, the levels of β-endorphin (β-ep), substance P (SP), tumor necrosis factor-α (TNF-α), and cyclooxygenase-2 (COX-2) were investigated in this study. New Zealand rabbits (2.5-3.0 kg in weight) were used in this study. High-fluence LLLT (27 J/cm(2)), low-fluence LLLT (4.5 J/cm(2)), or sham operations were applied on MTrSs of biceps femoris of rabbits for five sessions (one session per day). Effects of LLLT at two different fluences on biceps femoris, dorsal root ganglion (DRG), and serum were determined by β-ep, SP, TNF-α, and COX-2 immunoassays. LLLT irradiation with fluences of 4.5 and 27 J/cm(2) at MTrSs can significantly reduce SP level in DRG. LLLT with lower fluence of 4.5 J/cm(2) exerted lower levels of TNF-α and COX-2 expression in laser-treated muscle, but LLLT with higher fluence of 27 J/cm(2) elevated the levels of β-ep in serum, DRG, and muscle. This study demonstrated fluence-dependent biochemical effects of LLLT in an animal model on management of myofascial pain. The findings can contribute to the development of dosage guideline for LLLT for treating MTrP-induced pain.

  4. FPGA-Based Digital Current Switching Power Amplifiers Used in Magnetic Bearing Systems

    NASA Astrophysics Data System (ADS)

    Wang, Yin; Zhang, Kai; Dong, Jinping

    For a traditional two-level current switching power amplifier (PA) used in a magnetic bearing system, its current ripple is obvious. To increase its current ripple performance, three-level amplifiers are designed and their current control is generally based on analog and logical circuits. So the required hardware is complex and a performance increase from the hardware adjustment is difficult. To solve this problem, a FPGA-based digital current switching power amplifier (DCSPA) was designed. Its current ripple was obviously smaller than a two-level amplifier and its control circuit was much simpler than a tri-level amplifier with an analog control circuit. Because of the field-programmable capability of a FPGA chip used, different control algorithms including complex nonlinear algorithms could be easily implemented in the amplifier and their effects could be compared with the same hardware.

  5. STATUS EPILEPTICUS TRIGGERS EARLY AND LATE ALTERATIONS IN BRAIN-DERIVED NEUROTROPHIC FACTOR AND NMDA GLUTAMATE RECEPTOR GRIN2B DNA METHYLATION LEVELS IN THE HIPPOCAMPUS

    PubMed Central

    Parrish, R. Ryley; Albertson, Asher J.; Buckingham, Susan C.; Hablitz, John J.; Mascia, Katherine L.; Haselden, W. Davis; Lubin, Farah D.

    2013-01-01

    Status epilepticus (SE) triggers abnormal expression of genes in the hippocampus, such as glutamate receptor subunit epsilon-2 (Grin2b/Nr2b) and brain-derived neurotrophic factor (Bdnf), that is thought to occur in temporal lobe epilepsy (TLE). We examined the underlying DNA methylation mechanisms and investigated whether these mechanisms contribute to the expression of these gene targets in the epileptic hippocampus. Experimental TLE was provoked by kainic acid-induced SE. Bisulfite sequencing analysis revealed increased Grin2b/Nr2b and decreased Bdnf DNA methylation levels that corresponded to decreased Grin2b/Nr2b and increased Bdnf mRNA and protein expression in the epileptic hippocampus. Blockade of DNA methyltransferase (DNMT) activity with zebularine decreased global DNA methylation levels and reduced Grin2b/Nr2b, but not Bdnf, DNA methylation levels. Interestingly, we found that DNMT blockade further decreased Grin2b/Nr2b mRNA expression whereas GRIN2B protein expression increased in the epileptic hippocampus, suggesting that a posttranscriptional mechanism may be involved. Using chromatin immunoprecipitation analysis we found that DNMT inhibition restored the decreases in AP2alpha transcription factor levels at the Grin2b/Nr2b promoter in the epileptic hippocampus. DNMT inhibition increased field excitatory postsynaptic potential in hippocampal slices isolated from epileptic rats. EEG monitoring confirmed that DNMT inhibition did not significantly alter disease course, but promoted the latency to seizure onset or SE. Thus, DNA methylation may be an early event triggered by SE that persists late into the epileptic hippocampus to contribute to gene expression changes in TLE. PMID:23811393

  6. Embedded algorithms within an FPGA-based system to process nonlinear time series data

    NASA Astrophysics Data System (ADS)

    Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

    2008-03-01

    This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better

  7. Ground Level Observations of a Possible Downward-Beamed TGF during a Rocket-Triggered Lightning Flash at Camp Blanding, Florida in August 2014

    NASA Astrophysics Data System (ADS)

    Bozarth, A.; Dwyer, J. R.; Cramer, E. S.; Rassoul, H.; Uman, M. A.; Jordan, D.; Grove, J. E.

    2015-12-01

    Ground level high-energy observations of an August 2014 rocket-triggered lightning event at the International Center for Lightning Research and Testing (ICLRT) in Camp Blanding, Florida show a 180 µs burst of multiple-MeV photons during the latter part of the Upward Positive Leader (UPL) phase of an altitude-triggered lightning flash, following the first, truncated return stroke. The timing and waveform profile being atypical from x-ray emissions from lightning leaders, our observations suggest the occurrence of a downward beamed terrestrial gamma ray flash (TGF). Instrumentation operating during this event include a set of 16 NaI(TI)/PMT detectors plus 7 1-m2 plastic scintillation detectors spread across the 1 km2 facility, with 38 additional Na(TI)/PMT detectors located inside the 1"-thick Pb-shielded x-ray camera and an x-ray spectrometer. Comparing the location and energy data from these detectors to Monte Carlo simulations of TGFs from the REAM code developed by Dwyer [2003], our analysis investigates possible TGF production regions and determines the likelihood of the observed high-energy emissions being produced by a TGF inside the thunderstorm.

  8. FPGA development for high altitude subsonic parachute testing

    NASA Technical Reports Server (NTRS)

    Kowalski, James E.; Konefat, Edward H.; Gromovt, Konstantin

    2005-01-01

    This paper describes a rapid, top down requirements-driven design of an FPGA used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and store data from multiple sensors at multiple rates during launch, ascent, deployment and descent phases of the subsonic parachute test.

  9. FPGA development for high altitude subsonic parachute testing

    NASA Technical Reports Server (NTRS)

    Kowalski, James E.; Gromov, Konstantin G.; Konefat, Edward H.

    2005-01-01

    This paper describes a rapid, top down requirements-driven design of a Field Programmable Gate Array (FPGA) used in an Earth qualification test program for a new Mars subsonic parachute. The FPGA is used to process and control storage of telemetry data from multiple sensors throughout launch, ascent, deployment and descent phases of the subsonic parachute test.

  10. FPGA ROM Code for Very Large FIFO Control

    1995-02-22

    The code is used to program a Field Programmable Gate Array (FPGA) controls a 4 megabit FIFO so that a set delay from input to output is maintained. The FPGA is also capable of inserting errors into the data flow in a controlled manner.

  11. A new Pulse-Pattern Generator based on LabVIEW FPGA

    NASA Astrophysics Data System (ADS)

    Ziegler, F.; Beck, D.; Brand, H.; Hahn, H.; Marx, G.; Schweikhard, L.

    2012-07-01

    For the control of experimental sequences composed of triggers, gates and delays a Pulse-Pattern Generator (PPG) has been developed based on a Field Programmable Gate Array (FPGA) addressed in a LabVIEW environment. It allows a highly reproducible timing of measurement procedures by up to 64 individual channels with pulse and delay periods from the nanoseconds to the minutes range. The PPG has been implemented in the context of the development of a new control system for the ClusterTrap setup, an ion storage device for atomic-cluster research, in close contact with the SHIPTRAP and ISOLTRAP collaborations at GSI and CERN, respectively. As the new PPG is not ion-trap specific it can be employed in any experiment based on sequences of triggers, pulses and delays.

  12. Internal interface for RPC muon trigger electronics at CMS experiment

    NASA Astrophysics Data System (ADS)

    Pozniak, Krzysztof T.; Bartoszek, Marcin; Pietrusinski, Michal

    2004-07-01

    The paper describes design and practical realization of an internal communication layer referred to as the Internal Interface (II). The system was realized for the RPC Muon Trigger of the CMS experiment. Fully automatic implementation of the communication layer is realized in the FPGA chips and in the control software. The methodology of implementation was presented in the description form of the interface structure from the sides of hardware and software. The examples of the communication layer realizations were given for the RPC Muon Trigger.

  13. Increased levels of reduced cytochrome b and mitophagy components are required to trigger nonspecific autophagy following induced mitochondrial dysfunction

    PubMed Central

    Deffieu, Maika; Bhatia-Kiššová, Ingrid; Salin, Bénédicte; Klionsky, Daniel J.; Pinson, Benoît; Manon, Stéphen; Camougrand, Nadine

    2013-01-01

    Summary Mitochondria are essential organelles producing most of the energy required for the cell. A selective autophagic process called mitophagy removes damaged mitochondria, which is critical for proper cellular homeostasis; dysfunctional mitochondria can generate excess reactive oxygen species that can further damage the organelle as well as other cellular components. Although proper cell physiology requires the maintenance of a healthy pool of mitochondria, little is known about the mechanism underlying the recognition and selection of damaged organelles. In this study, we investigated the cellular fate of mitochondria damaged by the action of respiratory inhibitors (antimycin A, myxothiazol, KCN) that act on mitochondrial respiratory complexes III and IV, but have different effects with regard to the production of reactive oxygen species and increased levels of reduced cytochromes. Antimycin A and potassium cyanide effectively induced nonspecific autophagy, but not mitophagy, in a wild-type strain of Saccharomyces cerevisiae; however, low or no autophagic activity was measured in strains deficient for genes that encode proteins involved in mitophagy, including ATG32, ATG11 and BCK1. These results provide evidence for a major role of specific mitophagy factors in the control of a general autophagic cellular response induced by mitochondrial alteration. Moreover, increased levels of reduced cytochrome b, one of the components of the respiratory chain, could be the first signal of this induction pathway. PMID:23230142

  14. Increased levels of reduced cytochrome b and mitophagy components are required to trigger nonspecific autophagy following induced mitochondrial dysfunction.

    PubMed

    Deffieu, Maika; Bhatia-Kiššová, Ingrid; Salin, Bénédicte; Klionsky, Daniel J; Pinson, Benoît; Manon, Stéphen; Camougrand, Nadine

    2013-01-15

    Mitochondria are essential organelles producing most of the energy required for the cell. A selective autophagic process called mitophagy removes damaged mitochondria, which is critical for proper cellular homeostasis; dysfunctional mitochondria can generate excess reactive oxygen species that can further damage the organelle as well as other cellular components. Although proper cell physiology requires the maintenance of a healthy pool of mitochondria, little is known about the mechanism underlying the recognition and selection of damaged organelles. In this study, we investigated the cellular fate of mitochondria damaged by the action of respiratory inhibitors (antimycin A, myxothiazol, KCN) that act on mitochondrial respiratory complexes III and IV, but have different effects with regard to the production of reactive oxygen species and increased levels of reduced cytochromes. Antimycin A and potassium cyanide effectively induced nonspecific autophagy, but not mitophagy, in a wild-type strain of Saccharomyces cerevisiae; however, low or no autophagic activity was measured in strains deficient for genes that encode proteins involved in mitophagy, including ATG32, ATG11 and BCK1. These results provide evidence for a major role of specific mitophagy factors in the control of a general autophagic cellular response induced by mitochondrial alteration. Moreover, increased levels of reduced cytochrome b, one of the components of the respiratory chain, could be the first signal of this induction pathway. PMID:23230142

  15. Algorithm and implementation of muon trigger and data transmission system for barrel-endcap overlap region of the CMS detector

    NASA Astrophysics Data System (ADS)

    Zabolotny, W. M.; Byszuk, A.

    2016-03-01

    The CMS experiment Level-1 trigger system is undergoing an upgrade. In the barrel-endcap transition region, it is necessary to merge data from 3 types of muon detectors—RPC, DT and CSC. The Overlap Muon Track Finder (OMTF) uses the novel approach to concentrate and process those data in a uniform manner to identify muons and their transversal momentum. The paper presents the algorithm and FPGA firmware implementation of the OMTF and its data transmission system in CMS. It is foreseen that the OMTF will be subject to significant changes resulting from optimization which will be done with the aid of physics simulations. Therefore, a special, high-level, parameterized HDL implementation is necessary.

  16. Triggers and Effectors of Oxidative Stress at Blood-Brain Barrier Level: Relevance for Brain Ageing and Neurodegeneration

    PubMed Central

    2013-01-01

    As fundamental research advances, it is becoming increasingly clear that a clinically expressed disease implies a mixture of intertwining molecular disturbances. Oxidative stress is one of such pathogenic pathways involved in virtually all central nervous system pathologies, infectious, inflammatory, or degenerative in nature. Since brain homeostasis largely depends on integrity of blood-brain barrier (BBB), many studies focused lately on BBB alteration in a wide spectrum of brain diseases. The proper two-way molecular transfer through BBB depends on several factors, including the functional status of its tight junction (TJ) complexes of proteins sealing neighbour endothelial cells. Although there is abundant experimental work showing that oxidative stress associates BBB permeability alteration, less is known about its implications, at molecular level, in TJ protein expression or TJ-related cell signalling. In this paper, oxidative stress is presented as a common pathway for different brain pathogenic mechanisms which lead to BBB dysregulation. We revise here oxidative-induced molecular mechanisms of BBB disruption and TJ protein expression alteration, in relation to ageing and neurodegeneration. PMID:23533687

  17. Seismically Initiated Carbon Dioxide Gas Bubble Growth in Groundwater: A Mechanism for Co-seismic Borehole Water Level Rise and Remotely Triggered Secondary Seismicity

    NASA Astrophysics Data System (ADS)

    Crews, Jackson B.

    of freshwater. Co-seismic borehole water level increases of the same magnitude were observed in Parkfield, California, and Long Valley caldera, California, in response to the propagation of a Rayleigh wave in the same amplitude and frequency range produced by the June 28, 1992 MW 7.3 Landers, California, earthquake. Co-seismic borehole water level rise is well documented in the literature, but the mechanism is not well understood, and the results of core-scale experiments indicate that seismically initiated CO2 gas bubble nucleation and growth in groundwater is a reasonable mechanism. Remotely triggered secondary seismicity is also well documented, and the reduction of effective stress due to CO2 bubble nucleation and growth in critically loaded faults may potentially explain how, for example, the June 28, 1992 MW 7.3 Landers, California, earthquake triggered seismicity as far away as Yellowstone, Wyoming, 1250 km from the hypocenter. A numerical simulation was conducted using Euler's method and a first-order kinetic model to compute the pore fluid pressure response to confining stress excursions on a Berea sandstone core flooded with initially under-saturated aqueous CO2. The model was calibrated on the pore pressure response to a rapid drop and later recovery of the confining stress. The model predicted decreasing overpressure as the confining stress oscillation frequency increased from 0.05 Hz to 0.30 Hz, in contradiction with the experimental results and field observations, which exhibit larger excess pore fluid pressure in response to higher frequency oscillations. The limitations of the numerical model point to the important influence of non-ideal behavior arising from a discontinuous gas phase and complex dynamics at the gas-liquid interface.

  18. Time Triggered Protocol (TTP) for Integrated Modular Avionics

    NASA Technical Reports Server (NTRS)

    Motzet, Guenter; Gwaltney, David A.; Bauer, Guenther; Jakovljevic, Mirko; Gagea, Leonard

    2006-01-01

    Traditional avionics computing systems are federated, with each system provided on a number of dedicated hardware units. Federated applications are physically separated from one another and analysis of the systems is undertaken individually. Integrated Modular Avionics (IMA) takes these federated functions and integrates them on a common computing platform in a tightly deterministic distributed real-time network of computing modules in which the different applications can run. IMA supports different levels of criticality in the same computing resource and provides a platform for implementation of fault tolerance through hardware and application redundancy. Modular implementation has distinct benefits in design, testing and system maintainability. This paper covers the requirements for fault tolerant bus systems used to provide reliable communication between IMA computing modules. An overview of the Time Triggered Protocol (TTP) specification and implementation as a reliable solution for IMA systems is presented. Application examples in aircraft avionics and a development system for future space application are covered. The commercially available TTP controller can be also be implemented in an FPGA and the results from implementation studies are covered. Finally future direction for the application of TTP and related development activities are presented.

  19. Firearm trigger assembly

    SciTech Connect

    Crandall, David L.; Watson, Richard W.

    2010-02-16

    A firearm trigger assembly for use with a firearm includes a trigger mounted to a forestock of the firearm so that the trigger is movable between a rest position and a triggering position by a forwardly placed support hand of a user. An elongated trigger member operatively associated with the trigger operates a sear assembly of the firearm when the trigger is moved to the triggering position. An action release assembly operatively associated with the firearm trigger assembly and a movable assembly of the firearm prevents the trigger from being moved to the triggering position when the movable assembly is not in the locked position.

  20. Chrestenson transform FPGA embedded factorizations.

    PubMed

    Corinthios, Michael J

    2016-01-01

    Chrestenson generalized Walsh transform factorizations for parallel processing imbedded implementations on field programmable gate arrays are presented. This general base transform, sometimes referred to as the Discrete Chrestenson transform, has received special attention in recent years. In fact, the Discrete Fourier transform and Walsh-Hadamard transform are but special cases of the Chrestenson generalized Walsh transform. Rotations of a base-p hypercube, where p is an arbitrary integer, are shown to produce dynamic contention-free memory allocation, in processor architecture. The approach is illustrated by factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = p (n) , n integer, has a structure that depends on a variable parameter k that denotes the iteration number in the factorization process. The level of parallelism, in the form of M = p (m) processors can be chosen arbitrarily by varying m between zero to its maximum value of n - 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications.

  1. Chrestenson transform FPGA embedded factorizations.

    PubMed

    Corinthios, Michael J

    2016-01-01

    Chrestenson generalized Walsh transform factorizations for parallel processing imbedded implementations on field programmable gate arrays are presented. This general base transform, sometimes referred to as the Discrete Chrestenson transform, has received special attention in recent years. In fact, the Discrete Fourier transform and Walsh-Hadamard transform are but special cases of the Chrestenson generalized Walsh transform. Rotations of a base-p hypercube, where p is an arbitrary integer, are shown to produce dynamic contention-free memory allocation, in processor architecture. The approach is illustrated by factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = p (n) , n integer, has a structure that depends on a variable parameter k that denotes the iteration number in the factorization process. The level of parallelism, in the form of M = p (m) processors can be chosen arbitrarily by varying m between zero to its maximum value of n - 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications. PMID:27652084

  2. The Design of a FPGA-Based Traffic Light Control System: From Theory to Implementation

    NASA Astrophysics Data System (ADS)

    Rodríguez-Osorio, Ramón Martínez; Otero, Miguel Á. Fernández; Ramón, Miguel Calvo; Navarrete, Luis Cuéllar; Ariet, Leandro De Haro

    Most software-defined radio (SDR) prototypes make use of FPGA (Field Programmable Gate Array) devices such as digital filtering that perform operations at high sampling rates. The process from specifications and design to the implementation in FPGA requires the use of a large number of simulation tools. In the first stages of the design, the use of high-level tools such as Matlab, are required to perform intensive simulations. Results will help us to select the best specifications. Once the main design parameters have been established, the overall design is divided into modules following a hierarchical scheme. Each module is defined using a hardware description language (HDL) such as VHDL or Verilog.

  3. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lamanna, G.; Lonardo, A.; Lo Cicero, F.; Paolucci, P. S.; Pantaleo, F.; Rossetti, D.; Simula, F.; Sozzi, M.; Tosoratto, L.; Vicini, P.

    2014-02-01

    NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities.

  4. A distributed Canny edge detector: algorithm and FPGA implementation.

    PubMed

    Xu, Qian; Varadarajan, Srenivas; Chakrabarti, Chaitali; Karam, Lina J

    2014-07-01

    The Canny edge detector is one of the most widely used edge detection algorithms due to its superior performance. Unfortunately, not only is it computationally more intensive as compared with other edge detection algorithms, but it also has a higher latency because it is based on frame-level statistics. In this paper, we propose a mechanism to implement the Canny algorithm at the block level without any loss in edge detection performance compared with the original frame-level Canny algorithm. Directly applying the original Canny algorithm at the block-level leads to excessive edges in smooth regions and to loss of significant edges in high-detailed regions since the original Canny computes the high and low thresholds based on the frame-level statistics. To solve this problem, we present a distributed Canny edge detection algorithm that adaptively computes the edge detection thresholds based on the block type and the local distribution of the gradients in the image block. In addition, the new algorithm uses a nonuniform gradient magnitude histogram to compute block-based hysteresis thresholds. The resulting block-based algorithm has a significantly reduced latency and can be easily integrated with other block-based image codecs. It is capable of supporting fast edge detection of images and videos with high resolutions, including full-HD since the latency is now a function of the block size instead of the frame size. In addition, quantitative conformance evaluations and subjective tests show that the edge detection performance of the proposed algorithm is better than the original frame-based algorithm, especially when noise is present in the images. Finally, this algorithm is implemented using a 32 computing engine architecture and is synthesized on the Xilinx Virtex-5 FPGA. The synthesized architecture takes only 0.721 ms (including the SRAM READ/WRITE time and the computation time) to detect edges of 512 × 512 images in the USC SIPI database when clocked at 100

  5. A distributed Canny edge detector: algorithm and FPGA implementation.

    PubMed

    Xu, Qian; Varadarajan, Srenivas; Chakrabarti, Chaitali; Karam, Lina J

    2014-07-01

    The Canny edge detector is one of the most widely used edge detection algorithms due to its superior performance. Unfortunately, not only is it computationally more intensive as compared with other edge detection algorithms, but it also has a higher latency because it is based on frame-level statistics. In this paper, we propose a mechanism to implement the Canny algorithm at the block level without any loss in edge detection performance compared with the original frame-level Canny algorithm. Directly applying the original Canny algorithm at the block-level leads to excessive edges in smooth regions and to loss of significant edges in high-detailed regions since the original Canny computes the high and low thresholds based on the frame-level statistics. To solve this problem, we present a distributed Canny edge detection algorithm that adaptively computes the edge detection thresholds based on the block type and the local distribution of the gradients in the image block. In addition, the new algorithm uses a nonuniform gradient magnitude histogram to compute block-based hysteresis thresholds. The resulting block-based algorithm has a significantly reduced latency and can be easily integrated with other block-based image codecs. It is capable of supporting fast edge detection of images and videos with high resolutions, including full-HD since the latency is now a function of the block size instead of the frame size. In addition, quantitative conformance evaluations and subjective tests show that the edge detection performance of the proposed algorithm is better than the original frame-based algorithm, especially when noise is present in the images. Finally, this algorithm is implemented using a 32 computing engine architecture and is synthesized on the Xilinx Virtex-5 FPGA. The synthesized architecture takes only 0.721 ms (including the SRAM READ/WRITE time and the computation time) to detect edges of 512 × 512 images in the USC SIPI database when clocked at 100

  6. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts.

    PubMed

    Abbas, Syed Haider; Jang, Jae-Kyeong; Lee, Jung-Ryul; Kim, Zaeill

    2016-07-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  7. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts

    NASA Astrophysics Data System (ADS)

    Abbas, Syed Haider; Jang, Jae-Kyeong; Lee, Jung-Ryul; Kim, Zaeill

    2016-07-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests.

  8. Development of an FPGA-based multipoint laser pyroshock measurement system for explosive bolts.

    PubMed

    Abbas, Syed Haider; Jang, Jae-Kyeong; Lee, Jung-Ryul; Kim, Zaeill

    2016-07-01

    Pyroshock can cause failure to the objective of an aerospace structure by damaging its sensitive electronic equipment, which is responsible for performing decisive operations. A pyroshock is the high intensity shock wave that is generated when a pyrotechnic device is explosively triggered to separate, release, or activate structural subsystems of an aerospace architecture. Pyroshock measurement plays an important role in experimental simulations to understand the characteristics of pyroshock on the host structure. This paper presents a technology to measure a pyroshock wave at multiple points using laser Doppler vibrometers (LDVs). These LDVs detect the pyroshock wave generated due to an explosive-based pyrotechnical event. Field programmable gate array (FPGA) based data acquisition is used in the study to acquire pyroshock signals simultaneously from multiple channels. This paper describes the complete system design for multipoint pyroshock measurement. The firmware architecture for the implementation of multichannel data acquisition on an FPGA-based development board is also discussed. An experiment using explosive bolts was configured to test the reliability of the system. Pyroshock was generated using explosive excitation on a 22-mm-thick steel plate. Three LDVs were deployed to capture the pyroshock wave at different points. The pyroshocks captured were displayed as acceleration plots. The results showed that our system effectively captured the pyroshock wave with a peak-to-peak magnitude of 303 741 g. The contribution of this paper is a specialized architecture of firmware design programmed in FPGA for data acquisition of large amount of multichannel pyroshock data. The advantages of the developed system are the near-field, multipoint, non-contact, and remote measurement of a pyroshock wave, which is dangerous and expensive to produce in aerospace pyrotechnic tests. PMID:27475551

  9. The NA62 trigger system

    NASA Astrophysics Data System (ADS)

    Krivda, M.; NA62 Collaboration

    2013-08-01

    The main aim of the NA62 experiment (NA62 Technical Design Report, [1]) is to study ultra-rare Kaon decays. In order to select rare events over the overwhelming background, central systems with high-performance, high bandwidth, flexibility and configurability are necessary, that minimize dead time while maximizing data collection reliability. The NA62 experiment consists of 12 sub-detector systems and several trigger and control systems, for a total channel count of less than 100,000. The GigaTracKer (GTK) has the largest number of channels (54,000), and the Liquid Krypton (LKr) calorimeter shares with it the largest raw data rate (19 GB/s). The NA62 trigger system works with 3 trigger levels. The first trigger level is based on a hardware central trigger unit, so-called L0 Trigger Processor (L0TP), and Local Trigger Units (LTU), which are all located in the experimental cavern. Other two trigger levels are based on software, and done with a computer farm located on surface. The L0TP receives information from triggering sub-detectors asynchronously via Ethernet; it processes the information, and then transmits a final trigger decision synchronously to each sub-detector through the Trigger and Timing Control (TTC) system. The interface between L0TP and the TTC system, which is used for trigger and clock distribution, is provided by the Local Trigger Unit board (LTU). The LTU can work in two modes: global and stand-alone. In the global mode, the LTU provides an interface between L0TP and TTC system. In the stand-alone mode, the LTU can fully emulate L0TP and so provides an independent way for each sub-detector for testing or calibration purposes. In addition to the emulation functionality, a further functionality is implemented that allows to synchronize the clock of the LTU with the L0TP and the TTC system. For testing and debugging purposes, a Snap Shot Memory (SSM) interface is implemented, that can work

  10. Multi-variants synthesis of Petri nets for FPGA devices

    NASA Astrophysics Data System (ADS)

    Bukowiec, Arkadiusz; Doligalski, Michał

    2015-09-01

    There is presented new method of synthesis of application specific logic controllers for FPGA devices. The specification of control algorithm is made with use of control interpreted Petri net (PT type). It allows specifying parallel processes in easy way. The Petri net is decomposed into state-machine type subnets. In this case, each subnet represents one parallel process. For this purpose there are applied algorithms of coloring of Petri nets. There are presented two approaches of such decomposition: with doublers of macroplaces or with one global wait place. Next, subnets are implemented into two-level logic circuit of the controller. The levels of logic circuit are obtained as a result of its architectural decomposition. The first level combinational circuit is responsible for generation of next places and second level decoder is responsible for generation output symbols. There are worked out two variants of such circuits: with one shared operational memory or with many flexible distributed memories as a decoder. Variants of Petri net decomposition and structures of logic circuits can be combined together without any restrictions. It leads to existence of four variants of multi-variants synthesis.

  11. Wire Position Monitoring with FPGA based Electronics

    SciTech Connect

    Eddy, N.; Lysenko, O.; /Fermilab

    2009-01-01

    This fall the first Tesla-style cryomodule cooldown test is being performed at Fermilab. Instrumentation department is preparing the electronics to handle the data from a set of wire position monitors (WPMs). For simulation purposes a prototype pipe with a WMP has been developed and built. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The wire is stretched along the pipe with a tensioning load of 9.07 kg. The WPM consists of four 50 {Omega} striplines spaced 90{sup o} apart. FPGA based digitizer scans the WPM and transmits the data to a PC via VME interface. The data acquisition is based on the PC running LabView. In order to increase the accuracy and convenience of the measurements some modifications were required. The first is implementation of an average and decimation filter algorithm in the integrator operation in the FPGA. The second is the development of alternative tool for WPM measurements in the PC. The paper describes how these modifications were performed and test results of a new design. The last cryomodule generation has a single chain of seven WPMs (placed in critical positions: at each end, at the three posts and between the posts) to monitor a cold mass displacement during cooldown. The system was developed in Italy in collaboration with DESY. Similar developments have taken place at Fermilab in the frame of cryomodules construction for SCRF research. This fall preliminary cryomodule cooldown test is being performed. In order to prepare an appropriate electronic system for the test a prototype pipe with a WMP has been developed and built, figure 1. The system is based on the measurement of signals induced in pickups by 320 MHz signal carried by a wire through the WPM. The 0.5 mm diameter Cu wire is stretched along the pipe with a tensioning load of 9.07 kg and has a length of 1.1 m. The WPM consists of four 50 {Omega} striplines spaced 90{sup o} apart. An FPGA based

  12. Stego on FPGA: an IWT approach.

    PubMed

    Ramalingam, Balakrishnan; Amirtharajan, Rengarajan; Rayappan, John Bosco Balaguru

    2014-01-01

    A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA).

  13. A frame-based domain-specific language for rapid prototyping of FPGA-based software-defined radios

    NASA Astrophysics Data System (ADS)

    Ouedraogo, Ganda Stephane; Gautier, Matthieu; Sentieys, Olivier

    2014-12-01

    The field-programmable gate array (FPGA) technology is expected to play a key role in the development of software-defined radio (SDR) platforms. As this technology evolves, low-level designing methods for prototyping FPGA-based applications did not change throughout the decades. In the outstanding context of SDR, it is important to rapidly implement new waveforms to fulfill such a stringent flexibility paradigm. At the current time, different proposals have defined, through software-based approaches, some efficient methods to prototype SDR waveforms in a processor-based running environment. This paper describes a novel design flow for FPGA-based SDR applications. This flow relies upon high-level synthesis (HLS) principles and leverages the nascent HLS tools. Its entry point is a domain-specific language (DSL) which handles the complexity of programming an FPGA and integrates some SDR features so as to enable automatic waveform control generation from a data frame model. Two waveforms (IEEE 802.15.4 and IEEE 802.11a) have been designed and explored via this new methodology, and the results are highlighted in this paper.

  14. FPGA for Power Control of MSL Avionics

    NASA Technical Reports Server (NTRS)

    Wang, Duo; Burke, Gary R.

    2011-01-01

    A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

  15. Optimization of the Multi-Spectral Euclidean Distance Calculation for FPGA-based Spaceborne Systems

    NASA Technical Reports Server (NTRS)

    Cristo, Alejandro; Fisher, Kevin; Perez, Rosa M.; Martinez, Pablo; Gualtieri, Anthony J.

    2012-01-01

    Due to the high quantity of operations that spaceborne processing systems must carry out in space, new methodologies and techniques are being presented as good alternatives in order to free the main processor from work and improve the overall performance. These include the development of ancillary dedicated hardware circuits that carry out the more redundant and computationally expensive operations in a faster way, leaving the main processor free to carry out other tasks while waiting for the result. One of these devices is SpaceCube, a FPGA-based system designed by NASA. The opportunity to use FPGA reconfigurable architectures in space allows not only the optimization of the mission operations with hardware-level solutions, but also the ability to create new and improved versions of the circuits, including error corrections, once the satellite is already in orbit. In this work, we propose the optimization of a common operation in remote sensing: the Multi-Spectral Euclidean Distance calculation. For that, two different hardware architectures have been designed and implemented in a Xilinx Virtex-5 FPGA, the same model of FPGAs used by SpaceCube. Previous results have shown that the communications between the embedded processor and the circuit create a bottleneck that affects the overall performance in a negative way. In order to avoid this, advanced methods including memory sharing, Native Port Interface (NPI) connections and Data Burst Transfers have been used.

  16. DNA sequence matching processor using FPGA and JAVA interface.

    PubMed

    Brown, Benjamin O; Yin, Meng-Lai; Cheng, Yi

    2004-01-01

    This study uses an FPGA to perform high-speed DNA sequence matching as an alternative to using general purpose computer CPUs. The FPGA is programmed using the Verilog HDL and interfaced using a graphical user interface programmed in JAVA. Design overviews and details for a small scale design are given as well as plans for larger scale expansion. Encouraging results of the small scale model currently in production are also provided. Results of a successful match and no match are shown.

  17. A Portable Laser Photoacoustic Methane Sensor Based on FPGA

    PubMed Central

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-01-01

    A portable laser photoacoustic sensor for methane (CH4) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated. PMID:27657079

  18. Boosted object hardware trigger development and testing for the Phase I upgrade of the ATLAS Experiment

    NASA Astrophysics Data System (ADS)

    Stark, Giordon; Atlas Collaboration

    2015-04-01

    The Global Feature Extraction (gFEX) module is a Level 1 jet trigger system planned for installation in ATLAS during the Phase 1 upgrade in 2018. The gFEX selects large-radius jets for capturing Lorentz-boosted objects by means of wide-area jet algorithms refined by subjet information. The architecture of the gFEX permits event-by-event local pile-up suppression for these jets using the same subtraction techniques developed for offline analyses. The gFEX architecture is also suitable for other global event algorithms such as missing transverse energy (MET), centrality for heavy ion collisions, and ``jets without jets.'' The gFEX will use 4 processor FPGAs to perform calculations on the incoming data and a Hybrid APU-FPGA for slow control of the module. The gFEX is unique in both design and implementation and substantially enhance the selectivity of the L1 trigger and increases sensitivity to key physics channels.

  19. FPGA-based signal processing for the LHCb silicon strip detectors

    NASA Astrophysics Data System (ADS)

    Haefeli, G.; Bay, A.; Gong, A.

    2006-12-01

    We have developed an electronic board (TELL1) to interface the DAQ system of the LHCb experiment at CERN. Two hundred and eighty-nine TELL1 boards are needed to read out the different subdetectors including the silicon VEertex LOcator (VELO) (172 k strips), the Trigger Tracker (TT) (147 k strips) and the Inner Tracker (129 k strips). Each board can handle either 64 analog or 24 digital optical links. The TELL1 mother board provides common mode correction, zero suppression, data formatting, and a large network interface buffer. To satisfy the different requirements we have adopted a flexible FPGA design and made use of mezzanine cards. Mezzanines are used for data input from digital optical and analog copper links as well as for the Gigabit Ethernet interface to DAQ.

  20. Optically triggered infrared photodetector.

    PubMed

    Ramiro, Íñigo; Martí, Antonio; Antolín, Elisa; López, Esther; Datas, Alejandro; Luque, Antonio; Ripalda, José M; González, Yolanda

    2015-01-14

    We demonstrate a new class of semiconductor device: the optically triggered infrared photodetector (OTIP). This photodetector is based on a new physical principle that allows the detection of infrared light to be switched ON and OFF by means of an external light. Our experimental device, fabricated using InAs/AlGaAs quantum-dot technology, demonstrates normal incidence infrared detection in the 2-6 μm range. The detection is optically triggered by a 590 nm light-emitting diode. Furthermore, the detection gain is achieved in our device without an increase of the noise level. The novel characteristics of OTIPs open up new possibilities for third generation infrared imaging systems ( Rogalski, A.; Antoszewski, J.; Faraone, L. J. Appl. Phys. 2009, 105 (9), 091101). PMID:25490236

  1. Optically triggered infrared photodetector.

    PubMed

    Ramiro, Íñigo; Martí, Antonio; Antolín, Elisa; López, Esther; Datas, Alejandro; Luque, Antonio; Ripalda, José M; González, Yolanda

    2015-01-14

    We demonstrate a new class of semiconductor device: the optically triggered infrared photodetector (OTIP). This photodetector is based on a new physical principle that allows the detection of infrared light to be switched ON and OFF by means of an external light. Our experimental device, fabricated using InAs/AlGaAs quantum-dot technology, demonstrates normal incidence infrared detection in the 2-6 μm range. The detection is optically triggered by a 590 nm light-emitting diode. Furthermore, the detection gain is achieved in our device without an increase of the noise level. The novel characteristics of OTIPs open up new possibilities for third generation infrared imaging systems ( Rogalski, A.; Antoszewski, J.; Faraone, L. J. Appl. Phys. 2009, 105 (9), 091101).

  2. FPGA-Based, Self-Checking, Fault-Tolerant Computers

    NASA Technical Reports Server (NTRS)

    Some, Raphael; Rennels, David

    2004-01-01

    A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing

  3. The trigger system for the external target experiment in the HIRFL cooling storage ring

    NASA Astrophysics Data System (ADS)

    Li, Min; Zhao, Lei; Liu, Jin-Xin; Lu, Yi-Ming; Liu, Shu-Bin; An, Qi

    2016-08-01

    A trigger system was designed for the external target experiment in the Cooling Storage Ring (CSR) of the Heavy Ion Research Facility in Lanzhou (HIRFL). Considering that different detectors are scattered over a large area, the trigger system is designed based on a master-slave structure and fiber-based serial data transmission technique. The trigger logic is organized in hierarchies, and flexible reconfiguration of the trigger function is achieved based on command register access or overall field-programmable gate array (FPGA) logic on-line reconfiguration controlled by remote computers. We also conducted tests to confirm the function of the trigger electronics, and the results indicate that this trigger system works well. Supported by the National Natural Science Foundation of China (11079003), the Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), and the CAS Center for Excellence in Particle Physics (CCEPP).

  4. Energy efficiency analysis and implementation of AES on an FPGA

    NASA Astrophysics Data System (ADS)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  5. Fast semivariogram computation using FPGA architectures

    NASA Astrophysics Data System (ADS)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  6. FPGA implementation of sparse matrix algorithm for information retrieval

    NASA Astrophysics Data System (ADS)

    Bojanic, Slobodan; Jevtic, Ruzica; Nieto-Taladriz, Octavio

    2005-06-01

    Information text data retrieval requires a tremendous amount of processing time because of the size of the data and the complexity of information retrieval algorithms. In this paper the solution to this problem is proposed via hardware supported information retrieval algorithms. Reconfigurable computing may adopt frequent hardware modifications through its tailorable hardware and exploits parallelism for a given application through reconfigurable and flexible hardware units. The degree of the parallelism can be tuned for data. In this work we implemented standard BLAS (basic linear algebra subprogram) sparse matrix algorithm named Compressed Sparse Row (CSR) that is showed to be more efficient in terms of storage space requirement and query-processing timing over the other sparse matrix algorithms for information retrieval application. Although inverted index algorithm is treated as the de facto standard for information retrieval for years, an alternative approach to store the index of text collection in a sparse matrix structure gains more attention. This approach performs query processing using sparse matrix-vector multiplication and due to parallelization achieves a substantial efficiency over the sequential inverted index. The parallel implementations of information retrieval kernel are presented in this work targeting the Virtex II Field Programmable Gate Arrays (FPGAs) board from Xilinx. A recent development in scientific applications is the use of FPGA to achieve high performance results. Computational results are compared to implementations on other platforms. The design achieves a high level of parallelism for the overall function while retaining highly optimised hardware within processing unit.

  7. SRAM Based Re-programmable FPGA for Space Applications

    NASA Technical Reports Server (NTRS)

    Wang, J. J.; Sun, J. S.; Cronquist, B. E.; McCollum, J. L.; Speers, T. M.; Plants, W. C.; Katz, R. B.

    1999-01-01

    An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 micrometers CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor de-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I(sub CC)) measured indicates a device tolerance of approximately 50krad(Si).

  8. REALIZATION OF A CUSTOM DESIGNED FPGA BASED EMBEDDED CONTROLLER.

    SciTech Connect

    SEVERINO,F.; HARVEY, M.; HAYES, T.; HOFF, L.; ODDO, P.; SMITH, K.S.

    2007-10-15

    As part of the Low Level RF (LLRF) upgrade project at Brookhaven National Laboratory's Collider-Accelerator Department (BNL C-AD), we have recently developed and tested a prototype high performance embedded controller. This controller is a custom designed PMC module employing a Xilinx V4FX60 FPGA with a PowerPC405 embedded processor, and a wide variety of on board peripherals (DDR2 SDRAM, FLASH, Ethernet, PCI, multi-gigabit serial transceivers, etc.). The controller is capable of running either an embedded version of LINUX or VxWorks, the standard operating system for RHIC front end computers (FECs). We have successfully demonstrated functionality of this controller as a standard RHIC FEC and tested all on board peripherals. We now have the ability to develop complex, custom digital controllers within the framework of the standard RHIC control system infrastructure. This paper will describe various aspects of this development effort, including the basic hardware, functional capabilities, the development environment, kernel and system integration, and plans for further development.

  9. Stego on FPGA: An IWT Approach

    PubMed Central

    Ramalingam, Balakrishnan

    2014-01-01

    A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8 × 8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk's verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA). PMID:24723794

  10. A novel pipeline based FPGA implementation of a genetic algorithm

    NASA Astrophysics Data System (ADS)

    Thirer, Nonel

    2014-05-01

    To solve problems when an analytical solution is not available, more and more bio-inspired computation techniques have been applied in the last years. Thus, an efficient algorithm is the Genetic Algorithm (GA), which imitates the biological evolution process, finding the solution by the mechanism of "natural selection", where the strong has higher chances to survive. A genetic algorithm is an iterative procedure which operates on a population of individuals called "chromosomes" or "possible solutions" (usually represented by a binary code). GA performs several processes with the population individuals to produce a new population, like in the biological evolution. To provide a high speed solution, pipelined based FPGA hardware implementations are used, with a nstages pipeline for a n-phases genetic algorithm. The FPGA pipeline implementations are constraints by the different execution time of each stage and by the FPGA chip resources. To minimize these difficulties, we propose a bio-inspired technique to modify the crossover step by using non identical twins. Thus two of the chosen chromosomes (parents) will build up two new chromosomes (children) not only one as in classical GA. We analyze the contribution of this method to reduce the execution time in the asynchronous and synchronous pipelines and also the possibility to a cheaper FPGA implementation, by using smaller populations. The full hardware architecture for a FPGA implementation to our target ALTERA development card is presented and analyzed.

  11. Performance Evaluation of FPGA-Based Biological Applications

    SciTech Connect

    Storaasli, Olaf O; Yu, Weikuan; Strenski, Dave; Maltby, Jim

    2007-01-01

    On the forefront of recent HPC innovations are Field Programmable Gate Arrays (FPGA), which promise to accelerate calculations by one or more orders of magnitude. The performance of two Cray XD1 systems with Virtex-II Pro 50 and Virtex-4 LX160 FPGAs, were evaluated using a computational biological human genome comparisons program. This paper describes scalable, parallel, FPGA-accelerated results for the FASTA application ssearch34, using the Smith-Waterman algorithm for DNA, RNA and protein sequencing contained in the OpenFPGA benchmark suite. Results indicate typical Cray XD1 FPGA speedups of 50x (Virtex-II Pro 50) and 100x (Virtex-4 LX160) compared to a 2.2 GHz Opteron. Similar speedups are expected for the DRC RPU110-L200 modules (Virtex-4 LX200), which fit in an Opteron socket, and selected by Cray for its XT Supercomputers. The FPGA programming challenges, human genome benchmarking, and data verification of results, are discussed.

  12. Novel cascade FPGA accelerator for support vector machines classification.

    PubMed

    Papadonikolakis, Markos; Bouganis, Christos-Savvas

    2012-07-01

    Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.

  13. FPGA design and implementation for EIT data acquisition.

    PubMed

    Yue, Xicai; McLeod, Chris

    2008-10-01

    OXBACT-5 was designed to meet the challenges involved in working in the intensive care hospital environment focussed particularly on thoracic imaging of patients with respiratory distress and chronic heart failure (CHF). The FPGA-based wireless LAN linked multi-channel EIT data acquisition system (DAS) providing 16 programmable excitation current channels and 64 voltage measurement channels is presented. It contains function modules of a PCI bus interface, direct digital synthesizers, dual-port memory blocks, digital demodulation and all the command and control logic in the FPGA. The whole EIT data acquisition system is fully programmable and reconfigurable from the host PC. The excitation frequency, excitation patterns, the measuring sequence and the gain of each measurement channel can be set from the host PC before each measurement. The demodulation is implemented in the FPGA chip to reduce the data rate between the DAS and the host PC. In addition, measurement process management is achieved in this FPGA chip. Complemented by analogue devices such as ADCs, DACs, analogue buffers and analogue multiplexers, the new FPGA-based EIT DAS system is implemented in a very compact way for bedside use in intensive care units of hospitals. It is intended for applications such as continuous respiration monitoring with data collection at 25 frames per second. Image reconstruction times depend on the choice of 2D or 3D imaging algorithms and the available processing power.

  14. Identifying asthma triggers.

    PubMed

    McCarty, Justin C; Ferguson, Berrylin J

    2014-02-01

    Asthma has many triggers including rhinosinusitis; allergy; irritants; medications (aspirin in aspirin-exacerbated respiratory disease); and obesity. Paradoxic vocal fold dysfunction mimics asthma and may be present along with asthma. This article reviews each of these triggers, outlining methods of recognizing the trigger and then its management. In many patients more than one trigger may be present. Full appreciation of the complexity of these relationships and targeted therapy to the trigger is needed to best care for the patient with asthma.

  15. A low-power wave union TDC implemented in FPGA

    SciTech Connect

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas; /Illinois Math. Sci. Acad.

    2011-10-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  16. Dual port memory based Heapsort implementation for FPGA

    NASA Astrophysics Data System (ADS)

    Zabołotny, Wojciech M.

    2011-10-01

    This document presents a proposal of implementation of the Heapsort algorithm, which utilizes hardware features of modern Field-Programmable Gate Array (FPGA) chips, such as dual port random access memories (DP RAM), to implement efficient sorting of a data stream. The implemented sorter is able to sort one data record every two clock periods. This throughput does not depend on the capacity of the sorter (defined as number of storage cells in the sorter). The mean latency (expressed in sorting cycles - each equal to two clock periods) when sorting the stream of data is equal to the capacity of the sorter. Due to efficient use of FPGA resources (e.g. data are stored mainly in internal block RAMs), the complexity of the sorter is proportional to the logarithm of sorter capacity. Only the required RAM size is linearly proportional to the sorter capacity. The proposed sorter has been tested in simulations and synthesized for real FPGA chips to verify its correctness.

  17. Landslide triggering modeling in Switzerland

    NASA Astrophysics Data System (ADS)

    Jafari Manesh, Ahoura; Mignan, Arnaud; Giardini, Domenico

    2016-04-01

    Switzerland is prone to hazard interactions due to its mountainous landscape. Historical earthquakes are known to have triggered aftershocks, landslides, rock falls and avalanches, as well as lake tsunamis. Here we present a simple cellular automaton to simulate landslide footprints triggered by both rain and earthquakes. The method is based on the Sandpile model, which dynamics is controlled by the ground slope. Rain levels are approximated by ground water saturation and earthquake-landslide triggering is evaluated using the concept of Newmark displacement. That concept is then modified to estimate stable slopes during shaking at which locations the landslide stops. The cellular automaton is first tested in a virtual region where a parameter sensitivity analysis is made. Then it is tested in a region of Switzerland, where historic landslides triggered by earthquakes are known to have occurred.

  18. FPGA-based compression of streaming x-ray photon correlation spectroscopy data

    SciTech Connect

    Madden, Timothy; Jemian, Peter; Narayanan, Surcsh; Sandy, Alec; Sikorski, Marcin; Sprung, Michael; Weizeorick, John

    2011-08-09

    A data acquisition system to perform real-time background subtraction and lower-level-discrimination-based compression of streaming x-ray photon correlation spectroscopy (XPCS) data from a fast charge-coupled device (CCD) area detector has been built and put into service at the Advanced Photon source (APS) at Argonne National Laboratory. A commercial frame grabber with on-board field-programmable gate array (FPGA) was used in the design, and continuously processes 60 frames per second each consisting of 1,024 x 1,024 pixels with up to 64512 photon hits per frame.

  19. Isolating Triggered Star Formation

    SciTech Connect

    Barton, Elizabeth J.; Arnold, Jacob A.; Zentner, Andrew R.; Bullock, James S.; Wechsler, Risa H.; /KIPAC, Menlo Park /SLAC

    2007-09-12

    Galaxy pairs provide a potentially powerful means of studying triggered star formation from galaxy interactions. We use a large cosmological N-body simulation coupled with a well-tested semi-analytic substructure model to demonstrate that the majority of galaxies in close pairs reside within cluster or group-size halos and therefore represent a biased population, poorly suited for direct comparison to 'field' galaxies. Thus, the frequent observation that some types of galaxies in pairs have redder colors than 'field' galaxies is primarily a selection effect. We use our simulations to devise a means to select galaxy pairs that are isolated in their dark matter halos with respect to other massive subhalos (N= 2 halos) and to select a control sample of isolated galaxies (N= 1 halos) for comparison. We then apply these selection criteria to a volume-limited subset of the 2dF Galaxy Redshift Survey with M{sub B,j} {le} -19 and obtain the first clean measure of the typical fraction of galaxies affected by triggered star formation and the average elevation in the star formation rate. We find that 24% (30.5 %) of these L* and sub-L* galaxies in isolated 50 (30) h{sup -1} kpc pairs exhibit star formation that is boosted by a factor of {approx}> 5 above their average past value, while only 10% of isolated galaxies in the control sample show this level of enhancement. Thus, 14% (20 %) of the galaxies in these close pairs show clear triggered star formation. Our orbit models suggest that 12% (16%) of 50 (30) h{sup -1} kpc close pairs that are isolated according to our definition have had a close ({le} 30 h{sup -1} kpc) pass within the last Gyr. Thus, the data are broadly consistent with a scenario in which most or all close passes of isolated pairs result in triggered star formation. The isolation criteria we develop provide a means to constrain star formation and feedback prescriptions in hydrodynamic simulations and a very general method of understanding the importance of

  20. Radiation Tolerant, FPGA-Based SmallSat Computer System

    NASA Technical Reports Server (NTRS)

    LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

    2015-01-01

    The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

  1. VIRTEX-5 Fpga Implementation of Advanced Encryption Standard Algorithm

    NASA Astrophysics Data System (ADS)

    Rais, Muhammad H.; Qasim, Syed M.

    2010-06-01

    In this paper, we present an implementation of Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Virtex-5 Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a maximum throughput of 4.34 Gbps utilizing a total of 399 slices.

  2. L1 track finding for a time multiplexed trigger

    NASA Astrophysics Data System (ADS)

    Cieri, D.; Brooke, J.; Grimes, M.; Newbold, D.; Harder, K.; Shepherd-Themistocleous, C.; Tomalin, I.; Vichoudis, P.; Reid, I.; Iles, G.; Hall, G.; James, T.; Pesaresi, M.; Rose, A.; Tapper, A.; Uchida, K.

    2016-07-01

    At the HL-LHC, proton bunches will cross each other every 25 ns, producing an average of 140 pp-collisions per bunch crossing. To operate in such an environment, the CMS experiment will need a L1 hardware trigger able to identify interesting events within a latency of 12.5 μs. The future L1 trigger will make use also of data coming from the silicon tracker to control the trigger rate. The architecture that will be used in future to process tracker data is still under discussion. One interesting proposal makes use of the Time Multiplexed Trigger concept, already implemented in the CMS calorimeter trigger for the Phase I trigger upgrade. The proposed track finding algorithm is based on the Hough Transform method. The algorithm has been tested using simulated pp-collision data. Results show a very good tracking efficiency. The algorithm will be demonstrated in hardware in the coming months using the MP7, which is a μTCA board with a powerful FPGA capable of handling data rates approaching 1 Tb/s.

  3. Asthma triggers (image)

    MedlinePlus

    ... common asthma triggers are mold, pets, dust, grasses, pollen, cockroaches, odors from chemicals, and smoke from cigarettes. ... common asthma triggers are mold, pets, dust, grasses, pollen, cockroaches, odors from chemicals, and smoke from cigarettes.

  4. FPGA wavelet processor design using language for instruction-set architectures (LISA)

    NASA Astrophysics Data System (ADS)

    Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

    2007-04-01

    The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

  5. FPGA based image processing for optical surface inspection with real time constraints

    NASA Astrophysics Data System (ADS)

    Hasani, Ylber; Bodenstorfer, Ernst; Brodersen, Jörg; Mayer, Konrad J.

    2015-02-01

    Today, high-quality printing products like banknotes, stamps, or vouchers, are automatically checked by optical surface inspection systems. In a typical optical surface inspection system, several digital cameras acquire the printing products with fine resolution from different viewing angles and at multiple wavelengths of the visible and also near infrared spectrum of light. The cameras deliver data streams with a huge amount of image data that have to be processed by an image processing system in real time. Due to the printing industry's demand for higher throughput together with the necessity to check finer details of the print and its security features, the data rates to be processed tend to explode. In this contribution, a solution is proposed, where the image processing load is distributed between FPGAs and digital signal processors (DSPs) in such a way that the strengths of both technologies can be exploited. The focus lies upon the implementation of image processing algorithms in an FPGA and its advantages. In the presented application, FPGAbased image-preprocessing enables real-time implementation of an optical color surface inspection system with a spatial resolution of 100 μm and for object speeds over 10 m/s. For the implementation of image processing algorithms in the FPGA, pipeline parallelism with clock frequencies up to 150 MHz together with spatial parallelism based on multiple instantiations of modules for parallel processing of multiple data streams are exploited for the processing of image data of two cameras and three color channels. Due to their flexibility and their fast response times, it is shown that FPGAs are ideally suited for realizing a configurable all-digital PLL for the processing of camera line-trigger signals with frequencies about 100 kHz, using pure synchronous digital circuit design.

  6. Pipelined CPU Design with FPGA in Teaching Computer Architecture

    ERIC Educational Resources Information Center

    Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

    2012-01-01

    This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

  7. Single Event Effects in FPGA Devices 2014-2015

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2015-01-01

    This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  8. Single Event Effects in FPGA Devices 2015-2016

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  9. FPGA-based multi-channel fluorescence lifetime analysis of Fourier multiplexed frequency-sweeping lifetime imaging.

    PubMed

    Zhao, Ming; Li, Yu; Peng, Leilei

    2014-09-22

    We report a fast non-iterative lifetime data analysis method for the Fourier multiplexed frequency-sweeping confocal FLIM (Fm-FLIM) system [Opt. Express 22, 10221 (2014)]. The new method, named R-method, allows fast multi-channel lifetime image analysis in the system's FPGA data processing board. Experimental tests proved that the performance of the R-method is equivalent to that of single-exponential iterative fitting, and its sensitivity is well suited for time-lapse FLIM-FRET imaging of live cells, for example cyclic adenosine monophosphate (cAMP) level imaging with GFP-Epac-mCherry sensors. With the R-method and its FPGA implementation, multi-channel lifetime images can now be generated in real time on the multi-channel frequency-sweeping FLIM system, and live readout of FRET sensors can be performed during time-lapse imaging.

  10. FPGA-based multi-channel fluorescence lifetime analysis of Fourier multiplexed frequency-sweeping lifetime imaging

    PubMed Central

    Zhao, Ming; Li, Yu; Peng, Leilei

    2014-01-01

    We report a fast non-iterative lifetime data analysis method for the Fourier multiplexed frequency-sweeping confocal FLIM (Fm-FLIM) system [ Opt. Express22, 10221 ( 2014)24921725]. The new method, named R-method, allows fast multi-channel lifetime image analysis in the system’s FPGA data processing board. Experimental tests proved that the performance of the R-method is equivalent to that of single-exponential iterative fitting, and its sensitivity is well suited for time-lapse FLIM-FRET imaging of live cells, for example cyclic adenosine monophosphate (cAMP) level imaging with GFP-Epac-mCherry sensors. With the R-method and its FPGA implementation, multi-channel lifetime images can now be generated in real time on the multi-channel frequency-sweeping FLIM system, and live readout of FRET sensors can be performed during time-lapse imaging. PMID:25321778

  11. Photoelectric radar servo control system based on ARM+FPGA

    NASA Astrophysics Data System (ADS)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  12. Intracellular calcium levels are differentially regulated in T lymphocytes triggered by anti-CD2 and anti-CD3 monoclonal antibodies.

    PubMed

    Spinozzi, F; Agea, E; Bistoni, O; Belia, S; Travetti, A; Gerli, R; Muscat, C; Bertotto, A

    1995-03-01

    Antigen and/or mitogen-driven T-cell activation is mediated by a rise in intracellular free Ca2+, as second messenger. A regulatory key role for this process is represented by membrane-associated [Ca2+/Mg2+] ATP-ase that is mainly devoted to extrusion of intracellular ion excess. In the present study we have investigated the kinetics of CA2+ fluxes in both resting and already activated (Jurkat T-cell line) T lymphocytes after CD3 and CD2 (T11(2) and T11(3)) triggering and focused our attention on plasma membrane [Ca2+/Mg2+] ATP-ase activity. In both resting T cells and Jurkat cell line, the CD2 stimulation was able to determine a rise in intracellular free Ca2+ higher than that observed after CD3 triggering. In addition, this calcium signal was independent of negative feedback control exerted by [Ca2+/Mg2+] ATP-ase, as well as of IP3 generation. Thus the CD2 molecular system may, together with cell-adhesion properties, act as an amplifier of Ca2+ signals that, if delivered in the context of other molecular systems, such as CD3 or MHC class II antigens, are essentially devoted to the polyclonal co-stimulatory recruitment of a larger cellular repertoire. PMID:7662514

  13. Design of a system based on DSP and FPGA for video recording and replaying

    NASA Astrophysics Data System (ADS)

    Kang, Yan; Wang, Heng

    2013-08-01

    This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA

  14. The LUX experiment - trigger and data acquisition systems

    NASA Astrophysics Data System (ADS)

    Druszkiewicz, Eryk

    2013-04-01

    The Large Underground Xenon (LUX) detector is a two-phase xenon time projection chamber designed to detect interactions of dark matter particles with the xenon nuclei. Signals from the detector PMTs are processed by custom-built analog electronics which provide properly shaped signals for the trigger and data acquisition (DAQ) systems. During calibrations, both systems must be able to handle high rates and have large dynamic ranges; during dark matter searches, maximum sensitivity requires low thresholds. The trigger system uses eight-channel 64-MHz digitizers (DDC-8) connected to a Trigger Builder (TB). The FPGA cores on the digitizers perform real-time pulse identification (discriminating between S1 and S2-like signals) and event localization. The TB uses hit patterns, hit maps, and maximum response detection to make trigger decisions, which are reached within few microseconds after the occurrence of an event of interest. The DAQ system is comprised of commercial digitizers with customized firmware. Its real-time baseline suppression allows for a maximum event acquisition rate in excess of 1.5 kHz, which results in virtually no deadtime. The performance of the trigger and DAQ systems during the commissioning runs of LUX will be discussed.

  15. An unusual case of death probably triggered by the association of buprenorphine at therapeutic dose with ethanol and benzodiazepines and with very low norbuprenorphine level.

    PubMed

    Bardy, Guillaume; Cathala, Philippe; Eiden, Céline; Baccino, Eric; Petit, Pierre; Mathieu, Olivier

    2015-01-01

    Buprenorphine is largely prescribed for maintenance treatment in opioid dependence due to its safety profile. Nevertheless, fatalities at therapeutic dose have been described when associated with other central nervous system depressants, such as ethanol or benzodiazepines. Here, we report a case of death due to association of buprenorphine at therapeutic dose with benzodiazepines and ethanol. Although toxicity has been often attributed to its metabolite norbuprenorphine rather than to buprenorphine itself, in our case, norbuprenorphine was not detected in urine and bile and only in traces in blood. Moreover, the presence in blood of free buprenorphine but not of glucuronide metabolites argues for an unusual early death, at the beginning of buprenorphine metabolism. We propose that in the context of prior toxic impregnation, buprenorphine directly (and not via its metabolite norbuprenorphine) acted as a triggering factor by blocking the ventilatory response, rapidly leading to fatal respiratory depression.

  16. Hormones and clocks: do they disrupt the locks? Fluctuating estrogen levels during menopausal transition may influence clock genes and trigger chronic telogen effluvium.

    PubMed

    Mirmirani, Paradi

    2016-01-01

    Chronic telogen effluvium describes the clinical condition noted mostly in middle-aged women of increased, diffuse scalp hair shedding that is prolonged and often presents with a fluctuating course that may continue for years but does not lead to visible hair thinning. Despite its description almost 20 years ago, the underlying pathologic cause of CTE is yet to be identified. However the culmination of research in the field of hair biology and the burgeoning field of chronobiology may lead to exciting breakthroughs in our understanding of CTE. In this paper the current literature on CTE is reviewed and a hypothesis is put forth that CTE may be triggered by hormonal fluctuations and alterations in circadian control genes. PMID:27617515

  17. An unusual case of death probably triggered by the association of buprenorphine at therapeutic dose with ethanol and benzodiazepines and with very low norbuprenorphine level.

    PubMed

    Bardy, Guillaume; Cathala, Philippe; Eiden, Céline; Baccino, Eric; Petit, Pierre; Mathieu, Olivier

    2015-01-01

    Buprenorphine is largely prescribed for maintenance treatment in opioid dependence due to its safety profile. Nevertheless, fatalities at therapeutic dose have been described when associated with other central nervous system depressants, such as ethanol or benzodiazepines. Here, we report a case of death due to association of buprenorphine at therapeutic dose with benzodiazepines and ethanol. Although toxicity has been often attributed to its metabolite norbuprenorphine rather than to buprenorphine itself, in our case, norbuprenorphine was not detected in urine and bile and only in traces in blood. Moreover, the presence in blood of free buprenorphine but not of glucuronide metabolites argues for an unusual early death, at the beginning of buprenorphine metabolism. We propose that in the context of prior toxic impregnation, buprenorphine directly (and not via its metabolite norbuprenorphine) acted as a triggering factor by blocking the ventilatory response, rapidly leading to fatal respiratory depression. PMID:25348172

  18. FPGA-Based Efficient Hardware/Software Co-Design for Industrial Systems with Consideration of Output Selection

    NASA Astrophysics Data System (ADS)

    Deliparaschos, Kyriakos M.; Michail, Konstantinos; Zolotas, Argyrios C.; Tzafestas, Spyros G.

    2016-05-01

    This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

  19. Real-time machine vision system using FPGA and soft-core processor

    NASA Astrophysics Data System (ADS)

    Malik, Abdul Waheed; Thörnberg, Benny; Meng, Xiaozhou; Imran, Muhammad

    2012-06-01

    This paper presents a machine vision system for real-time computation of distance and angle of a camera from reference points in the environment. Image pre-processing, component labeling and feature extraction modules were modeled at Register Transfer (RT) level and synthesized for implementation on field programmable gate arrays (FPGA). The extracted image component features were sent from the hardware modules to a soft-core processor, MicroBlaze, for computation of distance and angle. A CMOS imaging sensor operating at a clock frequency of 27MHz was used in our experiments to produce a video stream at the rate of 75 frames per second. Image component labeling and feature extraction modules were running in parallel having a total latency of 13ms. The MicroBlaze was interfaced with the component labeling and feature extraction modules through Fast Simplex Link (FSL). The latency for computing distance and angle of camera from the reference points was measured to be 2ms on the MicroBlaze, running at 100 MHz clock frequency. In this paper, we present the performance analysis, device utilization and power consumption for the designed system. The FPGA based machine vision system that we propose has high frame speed, low latency and a power consumption that is much lower compared to commercially available smart camera solutions.

  20. FPGA-based electronics for confocal line scanners with linear detector arrays

    NASA Astrophysics Data System (ADS)

    Abeytunge, Sanjee; Toledo-Crow, Ricardo; Rajadhyaksha, Milind

    2009-02-01

    One-dimensional linear detector arrays have been used in the development of microscopes. Our confocal line scanning microscope electronics incorporate two printed circuit boards: control board and detector board. This architecture separates control electronics from detection electronics allowing us to minimize the footprint at microscope detector head. The Field Programmable Gate array (FPGA) on the control board generates timing and synchronization signals to three systems: detector board, frame grabber and galvanometric mirror scanner. The detector is kept away from its control electronics, and the clock and control signals are sent over a differential twisted-pair cable. These differential signals are translated to single ended signals and forwarded to the detector at the microscope detector head. The synchronization signals for the frame grabber are sent over a shielded cable. The control board also generates a saw tooth analog ramp to drive the galvanometric mirror scanner. The analog video output of the detector is fed into an operational amplifier where the white and the black levels are adjusted. Finally the analog video is send to the frame grabber via a shielded cable. FPGA-based electronics offer an inexpensive convenient means to control and synchronize simple line-scanning confocal microscopes.

  1. Performance Evaluation and Implementation of FPGA Based SGSF in Smart Diagnostic Applications.

    PubMed

    Agarwal, Shivangi; Rani, Asha; Singh, Vijander; Mittal, A P

    2016-03-01

    The main objective of the paper is to implement Savitzky Golay Smoothing Filter (SGSF) so as to apply in pre-processing of real time smart medical diagnostic systems. As very important information of EEG and ECG waveforms lies in the peak of the signal, hence it becomes absolutely necessary to filter noise and artifacts from the signal. The implemented filter should be able to reject the noise efficiently along with the least distortion from the original signal. The shape preserving characteristics of the filter are determined by introducing different noise levels in the signal. The designed filter is tested on synthetic signals of EEG and ECG by adding different types of noise and the performance is analysed on various parameters, i.e., SNR, SSNR, SNRI, MSE, COR and signal distortion of the final output. The smoothing performance comparison of SGSF with the most commonly used Moving Average Filter (MAF) proves that SGSF is more efficient. Hence it is suggested that MAF can be replaced by SGSF. For real time issues, it is further implemented on reconfigurable architectures so as to achieve high speed, low cost, low power consumption and less area. Therefore SGSF is realized on FPGA platform to combine the advantages of both. Real time EEG and ECG signals are also considered for experimentation. The experimental results show that the proposed methodology (FPGA-SGSF) significantly reduces the processing time and preserves the actual features of the signal.

  2. Performance Evaluation and Implementation of FPGA Based SGSF in Smart Diagnostic Applications.

    PubMed

    Agarwal, Shivangi; Rani, Asha; Singh, Vijander; Mittal, A P

    2016-03-01

    The main objective of the paper is to implement Savitzky Golay Smoothing Filter (SGSF) so as to apply in pre-processing of real time smart medical diagnostic systems. As very important information of EEG and ECG waveforms lies in the peak of the signal, hence it becomes absolutely necessary to filter noise and artifacts from the signal. The implemented filter should be able to reject the noise efficiently along with the least distortion from the original signal. The shape preserving characteristics of the filter are determined by introducing different noise levels in the signal. The designed filter is tested on synthetic signals of EEG and ECG by adding different types of noise and the performance is analysed on various parameters, i.e., SNR, SSNR, SNRI, MSE, COR and signal distortion of the final output. The smoothing performance comparison of SGSF with the most commonly used Moving Average Filter (MAF) proves that SGSF is more efficient. Hence it is suggested that MAF can be replaced by SGSF. For real time issues, it is further implemented on reconfigurable architectures so as to achieve high speed, low cost, low power consumption and less area. Therefore SGSF is realized on FPGA platform to combine the advantages of both. Real time EEG and ECG signals are also considered for experimentation. The experimental results show that the proposed methodology (FPGA-SGSF) significantly reduces the processing time and preserves the actual features of the signal. PMID:26671061

  3. Methods for automatic trigger threshold adjustment

    DOEpatents

    Welch, Benjamin J; Partridge, Michael E

    2014-03-18

    Methods are presented for adjusting trigger threshold values to compensate for drift in the quiescent level of a signal monitored for initiating a data recording event, thereby avoiding false triggering conditions. Initial threshold values are periodically adjusted by re-measuring the quiescent signal level, and adjusting the threshold values by an offset computation based upon the measured quiescent signal level drift. Re-computation of the trigger threshold values can be implemented on time based or counter based criteria. Additionally, a qualification width counter can be utilized to implement a requirement that a trigger threshold criterion be met a given number of times prior to initiating a data recording event, further reducing the possibility of a false triggering situation.

  4. The LHCb trigger and its upgrade

    NASA Astrophysics Data System (ADS)

    Dziurda, A.

    2016-07-01

    The current LHCb trigger system consists of a hardware level, which reduces the LHC inelastic collision rate of 30 MHz, at which the entire detector is read out. In a second level, implemented in a farm of 20 k parallel-processing CPUs, the event rate is reduced to about 5 kHz. We review the performance of the LHCb trigger system during Run I of the LHC. Special attention is given to the use of multivariate analyses in the High Level Trigger. The major bottleneck for hadronic decays is the hardware trigger. LHCb plans a major upgrade of the detector and DAQ system in the LHC shutdown of 2018, enabling a purely software based trigger to process the full 30 MHz of inelastic collisions delivered by the LHC. We demonstrate that the planned architecture will be able to meet this challenge.

  5. Myofascial trigger points.

    PubMed

    Lavelle, Elizabeth Demers; Lavelle, William; Smith, Howard S

    2007-03-01

    Painful conditions of the musculoskeletal system, including myofascial pain syndrome, constitute some of the most important chronic problems encountered in a clinical practice. A myofascial trigger points is a hyperirritable spot, usually within a taut band of skeletal muscle, which is painful on compression and can give rise to characteristic referred pain, motor dysfunction, and autonomic phenomena. Trigger points may be relieved through noninvasive measures, such as spray and stretch, transcutaneous electrical stimulation, physical therapy, and massage. Invasive treatments for myofascial trigger points include injections with local anesthetics, corticosteroids, or botulism toxin or dry needling. The etiology, pathophysiology, and treatment of myofascial trigger points are addressed in this article.

  6. FPGA-based Klystron linearization implementations in scope of ILC

    DOE PAGES

    Omet, M.; Michizono, S.; Matsumoto, T.; Miura, T.; Qiu, F.; Chase, B.; Varghese, P.; Schlarb, H.; Branlard, J.; Cichalewski, W.

    2015-01-23

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successfulmore » implementation for one algorithm and a proof of principle for two algorithms. Furthermore, the functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation.« less

  7. An FPGA architecture for MPEG-2 TS demultiplexer

    NASA Astrophysics Data System (ADS)

    Abramowski, Andrzej

    2012-05-01

    This paper presents a novel architecture of a MPEG-2 TS demultiplexer, implemented with a FPGA. The main objective of the design is an ability to separate selected elementary streams in real time, while ensuring minimal resource consumption. This is achieved by the decomposition of the demultiplexer into a number of independent sub-modules, which process the data in parallel. The flexible structure enables adaptation to the specific needs and significantly simplifies potential expansion, what may be important due to a wide range of potential applications of the MPEG-2 TS standard. To improve the functionality, the demultiplexer is equipped with a configuration and status interface. The transport stream and configuration data are supplied to the FPGA by a microcontroller through the External Peripheral Interface (EPI). The data is transmitted to the microcontroller via Ethernet, using the User Datagram Protocol (UDP).

  8. High-Performance CCSDS Encapsulation Service Implementation in FPGA

    NASA Technical Reports Server (NTRS)

    Clare, Loren P.; Torgerson, Jordan L.; Pang, Jackson

    2010-01-01

    The Consultative Committee for Space Data Systems (CCSDS) Encapsulation Service is a convergence layer between lower-layer space data link framing protocols, such as CCSDS Advanced Orbiting System (AOS), and higher-layer networking protocols, such as CFDP (CCSDS File Delivery Protocol) and Internet Protocol Extension (IPE). CCSDS Encapsulation Service is considered part of the data link layer. The CCSDS AOS implementation is described in the preceding article. Recent advancement in RF modem technology has allowed multi-megabit transmission over space links. With this increase in data rate, the CCSDS Encapsulation Service needs to be optimized to both reduce energy consumption and operate at a high rate. CCSDS Encapsulation Service has been implemented as an intellectual property core so that the aforementioned problems are solved by way of operating the CCSDS Encapsulation Service inside an FPGA. The CCSDS En capsula tion Service in FPGA implementation consists of both packetizing and de-packetizing features

  9. CCD fiber Bragg grating sensor demodulation system based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhou, Q.; Ning, T. G.; Pei, L.; Li, J.; Wen, X. D.; Li, Z. X.

    2010-11-01

    A CCD fiber Bragg grating sensor demodulation system based on FPGA is proposed. The system is divided into three units: spectral imaging unit, signal detection unit and signal acquisition and processing unit. The spectral imaging unit uses reflective imaging system, which has few aberration, small size, simple structure and low cost. In the signal detection unit, information of spectrum are accessed by CCD detector, the measurement of spectral line is converted into the measurement of the pixel position of spot, multi point can be simultaneously measured, so the system's reusability, stability and reliability are improved. In the signal acquisition and processing unit, drive circuit and signal acquisition and processing circuit are designed by programmable logic device FPGA, fully use of programmable and high real-time features, simplified system design, improved the system's real-time monitoring capabilities and demodulation speed.

  10. FPGA-based Klystron linearization implementations in scope of ILC

    SciTech Connect

    Omet, M.; Michizono, S.; Varghese, P.; Schlarb, H.; Branlard, J.; Cichalewski, W.

    2015-01-23

    We report the development and implementation of four FPGA-based predistortion-type klystron linearization algorithms. Klystron linearization is essential for the realization of ILC, since it is required to operate the klystrons 7% in power below their saturation. The work presented was performed in international collaborations at the Fermi National Accelerator Laboratory (FNAL), USA and the Deutsches Elektronen Synchrotron (DESY), Germany. With the newly developed algorithms, the generation of correction factors on the FPGA was improved compared to past algorithms, avoiding quantization and decreasing memory requirements. At FNAL, three algorithms were tested at the Advanced Superconducting Test Accelerator (ASTA), demonstrating a successful implementation for one algorithm and a proof of principle for two algorithms. Furthermore, the functionality of the algorithm implemented at DESY was demonstrated successfully in a simulation.

  11. Application of FPGA technology to performance limitations in radiation therapy

    NASA Astrophysics Data System (ADS)

    DeMarco, John J.; Smathers, J. B.; Solberg, Tim D.; Casselman, Steve

    1996-10-01

    The field programmable gate array (FPGA) is a promising technology for increasing computation performance by providing for the design of custom chips through programmable logic blocks. This technology was used to implement and test a hardware random number generator (RNG) versus four software algorithms. The custom hardware consists of a sun SBus-based board (EVC) which has been designed around a Xilinx FPGA. A timing analysis indicates the Sun/EVC hardware generator computes 1 multiplied by 106 random numbers approximately 50 times faster than the multiplicative congruential algorithm. The hardware and software RNGs were also compare using a Monte Carlo photon transport algorithm. For this comparison the Sun/EVC generator produces a performance increase of approximately 2.0 versus the software generators. This comparison is based upon 1 multiplied by 105 photon histories.

  12. A CMOS high speed imaging system design based on FPGA

    NASA Astrophysics Data System (ADS)

    Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

    2015-10-01

    CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

  13. Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; LaBel, Kenneth

    2015-01-01

    This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

  14. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    NASA Technical Reports Server (NTRS)

    Berg, Melanie D.; LaBel, Kenneth; Pellish, Jonathan

    2015-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  15. On-chop processing for the wave union TDC implemented in FPGA

    SciTech Connect

    Wu, Jinyan; /Fermilab

    2009-05-01

    The wave union TDC implemented in FPGA utilizes multiple measurement method to reach time resolution beyond the natural carry cell delay in FPGA. Lacking of analog compensation for bin width control available in ASIC, the wave union TDC takes the after-fact digital calibration approach. In addition to the temperature drift, non-uniformity of the carry chain structure in FPGA causes complicate differential nonlinearity pattern which imposes significant on-chip calibration challenge. In this paper, processing strategies for the wave union TDC are discussed. Actual implementations in low-cost FPGA with 20ps and 10ps RMS resolutions are also presented.

  16. The use of low-level laser therapy (LLLT) in the treatment of trigger points that are associated with rotator cuff tendonitis

    NASA Astrophysics Data System (ADS)

    Al-Shenqiti, A.; Oldham, J.

    2003-12-01

    The purpose of this study was to investigate the efficacy of LLLT in the treatment of trigger points (TrPs) that are associated with rotator cuff tendonitis. A double-blind randomized controlled trail was conducted. Sixty patients were randomly allocated to one of two groups: sham or laser therapy. The laser (Excel, Omega Universal Technologies Ltd, London, UK) parameters used were a wavelength of 820 nm, a power output of 100 mW, a frequency of 5000 Hz (modulated) and energy density of 32 J/cm2. The two groups received a course of 12 treatment sessions for four weeks (3 sessions per week). Pain, functional activities (as measured using the Shoulder Pain and Disability Index, SPADI), pressure pain threshold (PPT) and range of motion (ROM) were assessed pre and post treatment, with a three month follow-up assessment. Significant improvements in pain (p < 0.001) were observed for the laser group (6 cm median improvement on a 10 cm VAS) compared to the sham group (2 cm median improvement) immediately post treatment. The improvements in the laser group continued post treatment with a 7 cm median improvement observed at three month follow-up. Similar between group differences were observed for ROM (p < 0.01), functional activities (p <= 0.001) and PPT (p <= 0.05). The findings of the current study suggested that LLLT is effective in treating patients with TrPs associated with rotator cuff tendonitis, when using the parameters described. However, the mechanism of its action is not yet clear, and will require further investigation.

  17. Lessons from (triggered) tremor

    USGS Publications Warehouse

    Gomberg, Joan

    2010-01-01

    I test a “clock-advance” model that implies triggered tremor is ambient tremor that occurs at a sped-up rate as a result of loading from passing seismic waves. This proposed model predicts that triggering probability is proportional to the product of the ambient tremor rate and a function describing the efficacy of the triggering wave to initiate a tremor event. Using data mostly from Cascadia, I have compared qualitatively a suite of teleseismic waves that did and did not trigger tremor with ambient tremor rates. Many of the observations are consistent with the model if the efficacy of the triggering wave depends on wave amplitude. One triggered tremor observation clearly violates the clock-advance model. The model prediction that larger triggering waves result in larger triggered tremor signals also appears inconsistent with the measurements. I conclude that the tremor source process is a more complex system than that described by the clock-advance model predictions tested. Results of this and previous studies also demonstrate that (1) conditions suitable for tremor generation exist in many tectonic environments, but, within each, only occur at particular spots whose locations change with time; (2) any fluid flow must be restricted to less than a meter; (3) the degree to which delayed failure and secondary triggering occurs is likely insignificant; and 4) both shear and dilatational deformations may trigger tremor. Triggered and ambient tremor rates correlate more strongly with stress than stressing rate, suggesting tremor sources result from time-dependent weakening processes rather than simple Coulomb failure.

  18. Passive coherent location FPGA implementation of the cross ambiguity function

    NASA Astrophysics Data System (ADS)

    Kvasnička, Michal; Heřmánek, Antonín; Kuneš, Michal; Pelant, Martin; Plšek, Radek

    2006-02-01

    One of key problem in passive coherent location (PCL) is effective and accurate computation of the cross ambiguity function (CAF). This function is related to the direct signal and signals reflected from localized targets. PCL systems exploit high-power commercial transmitters of opportunity (FM, TV, etc.) to take advantage of lower frequencies, multistatic geometries and covert deployment. The transmitter does not have to cooperate with the receiver. The CAF represent power spectral density distribution of the cross-correlation between direct and reflected signals. It depends on mutual time delay and frequency shift of the input signals and is considerate as primary information for detection, localization and identification of the tracked targets. Regarding above mentioned reasons has to be important develop optimal (numerically effective and sufficiently accurate) implementation of the HW architecture based on FPGA for CAF computation, which will be suitable for future real-time PCL systems. As a first result which originates on the ongoing mutual cooperation between ERA a.s. and UTIA is design of the PC accelerator card for CAF computation based on Xilinx FPGA processor. The presented contribution gives overall information about used algorithms, FPGA accelerator card design and achieved performance. The future possibilities of the additional enhancements are discussed.

  19. An FPGA Implementation to Detect Selective Cationic Antibacterial Peptides

    PubMed Central

    Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

    2011-01-01

    Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides. PMID:21738652

  20. Design of transient light signal simulator based on FPGA

    NASA Astrophysics Data System (ADS)

    Kang, Jing; Chen, Rong-li; Wang, Hong

    2014-11-01

    A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

  1. Design of video interface conversion system based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhao, Heng; Wang, Xiang-jun

    2014-11-01

    This paper presents a FPGA based video interface conversion system that enables the inter-conversion between digital and analog video. Cyclone IV series EP4CE22F17C chip from Altera Corporation is used as the main video processing chip, and single-chip is used as the information interaction control unit between FPGA and PC. The system is able to encode/decode messages from the PC. Technologies including video decoding/encoding circuits, bus communication protocol, data stream de-interleaving and de-interlacing, color space conversion and the Camera Link timing generator module of FPGA are introduced. The system converts Composite Video Broadcast Signal (CVBS) from the CCD camera into Low Voltage Differential Signaling (LVDS), which will be collected by the video processing unit with Camera Link interface. The processed video signals will then be inputted to system output board and displayed on the monitor.The current experiment shows that it can achieve high-quality video conversion with minimum board size.

  2. High Speed Multichannel Charge Sensitive Data Acquisition System with Self-Triggered Event Timing.

    PubMed

    Tremsin, Anton S; Siegmund, Oswald H W; Vallerga, John V; Raffanti, Rick; Weiss, Shimon; Michalet, Xavier

    2009-06-16

    A number of modern experiments require simultaneous measurement of charges on multiple channels at > MHz event rates with an accuracy of 100-1000 e(-) rms. One widely used data processing scheme relies on application of specific integrated circuits enabling multichannel analog peak detection asserted by an external trigger followed by a serial/sparsified readout. Although this configuration minimizes the back end electronics, its counting rate capability is limited by the speed of the serial readout. Recent advances in analog to digital converters and FPGA devices enable fully parallel high speed multichannel data processing with digital peak detection enhanced by finite impulse response filtering. Not only can accurate charge values be obtained at high event rates, but the timing of the event on each channel can also be determined with high accuracy.We present the concept and first experimental tests of fully parallel 128-channel charge sensitive data processing electronics capable of measuring charges with accuracy of ~1000 e- rms. Our system does not require an external trigger and, in addition to charge values, it provides the event timing with an accuracy of ~1 ns FWHM. One of the possible applications of this system is high resolution position sensitive event counting detectors with microchannel plates combined with cross strip readout. Implementation of fast data acquisition electronics increases the counting rates of those detectors to multi-MHz level, preserving their unique capability of virtually noiseless detection of both position (with accuracy of ~10 μm FWHM) and timing (~1 ns FWHM) of individual particles, including photons, electrons, ions, neutrals, and neutrons.

  3. Social deprivation stress is a triggering factor for the emergence of anxiety- and depression-like behaviours and leads to reduced brain BDNF levels in C57BL/6J mice.

    PubMed

    Berry, Alessandra; Bellisario, Veronica; Capoccia, Sara; Tirassa, Paola; Calza, Arianna; Alleva, Enrico; Cirulli, Francesca

    2012-06-01

    Stress is a main risk factor that can trigger psychiatric disorders, including anxiety and major depression. Neurotrophins, such as Brain-Derived Neurotrophic Factor (BDNF), have been identified as neuroendocrine effectors involved in the response to stress and in the neurobehavioural changes associated with depression. Aim of this paper was to study the relationship between neuroendocrine activation (circulating corticosterone and brain BDNF levels) and a wide array of depression- and anxiety-like behaviours (anhedonia, behavioural despair, generalised and social anxiety) resulting from exposure to chronic stress. To this end, 3-month-old C57BL/6J male mice were exposed to either chronic disruption of the social structure (SS), to a stable social structure (SG) or to social deprivation (SD), a condition lacking social stimuli. Results show that, despite not developing anhedonia (decreased preference for a sucrose solution), SD mice were characterised by increased emotionality and hypothalamic-pituitary-adrenal axis reactivity in addition to reduced BDNF levels. By contrast, SG and SS mice showed increased anhedonia accompanied by no alterations in the behavioural and neuroendocrine profile. The results here reported indicate that mice exposed to different social housing conditions use different behavioural strategies to cope with external challenges. In addition they suggest that social deprivation might represent a stressful condition triggering the emergence of both anxiety- and depression-like behaviours and clearly indicate BDNF as a main neurobiological variable mediating these responses.

  4. Remote Dose-Dependent Effects of Dry Needling at Distant Myofascial Trigger Spots of Rabbit Skeletal Muscles on Reduction of Substance P Levels of Proximal Muscle and Spinal Cords

    PubMed Central

    Hsieh, Yueh-Ling; Liu, Szu-Yu; Hong, Chang-Zern

    2014-01-01

    Background. Dry needling at distant myofascial trigger points is an effective pain management in patients with myofascial pain. However, the biochemical effects of remote dry needling are not well understood. This study evaluates the remote effects of dry needling with different dosages on the expressions of substance P (SP) in the proximal muscle, spinal dorsal horns of rabbits. Methods. Male New Zealand rabbits (2.5–3.0 kg) received dry needling at myofascial trigger spots of a gastrocnemius (distant muscle) in one (1D) or five sessions (5D). Bilateral biceps femoris (proximal muscles) and superficial laminaes of L5-S2, T2-T5, and C2-C5 were sampled immediately and 5 days after dry needling to determine the levels of SP using immunohistochemistry and western blot. Results. Immediately after dry needling for 1D and 5D, the expressions of SP were significantly decreased in ipsilateral biceps femoris and bilateral spinal superficial laminaes (P < .05). Five days after dry needling, these reduced immunoactivities of SP were found only in animals receiving 5D dry needling (P < .05). Conclusions. This remote effect of dry needling involves the reduction of SP levels in proximal muscle and spinal superficial laminaes, which may be closely associated with the control of myofascial pain. PMID:25276839

  5. AMY trigger system

    SciTech Connect

    Sakai, Yoshihide

    1989-04-01

    A trigger system of the AMY detector at TRISTAN e{sup +}e{sup -} collider is described briefly. The system uses simple track segment and shower cluster counting scheme to classify events to be triggered. It has been operating successfully since 1987.

  6. SAD5 Stereo Correlation Line-Striping in an FPGA

    NASA Technical Reports Server (NTRS)

    Villalpando, Carlos Y.; Morfopoulos, Arin C.

    2011-01-01

    High precision SAD5 stereo computations can be performed in an FPGA (field-programmable gate array) at much higher speeds than possible in a conventional CPU (central processing unit), but this uses large amounts of FPGA resources that scale with image size. Of the two key resources in an FPGA, Slices and BRAM (block RAM), Slices scale linearly in the new algorithm with image size, and BRAM scales quadratically with image size. An approach was developed to trade latency for BRAM by sub-windowing the image vertically into overlapping strips and stitching the outputs together to create a single continuous disparity output. In stereo, the general rule of thumb is that the disparity search range must be 1/10 the image size. In the new algorithm, BRAM usage scales linearly with disparity search range and scales again linearly with line width. So a doubling of image size, say from 640 to 1,280, would in the previous design be an effective 4 of BRAM usage: 2 for line width, 2 again for disparity search range. The minimum strip size is twice the search range, and will produce an output strip width equal to the disparity search range. So assuming a disparity search range of 1/10 image width, 10 sequential runs of the minimum strip size would produce a full output image. This approach allowed the innovators to fit 1280 960 wide SAD5 stereo disparity in less than 80 BRAM, 52k Slices on a Virtex 5LX330T, 25% and 24% of resources, respectively. Using a 100-MHz clock, this build would perform stereo at 39 Hz. Of particular interest to JPL is that there is a flight qualified version of the Virtex 5: this could produce stereo results even for very large image sizes at 3 orders of magnitude faster than could be computed on the PowerPC 750 flight computer. The work covered in the report allows the stereo algorithm to run on much larger images than before, and using much less BRAM. This opens up choices for a smaller flight FPGA (which saves power and space), or for other algorithms

  7. Economical Implementation of a Filter Engine in an FPGA

    NASA Technical Reports Server (NTRS)

    Kowalski, James E.

    2009-01-01

    A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be

  8. Assessment of Proper Bonding Methods and Mechanical Characterization FPGA CQFPs

    NASA Technical Reports Server (NTRS)

    Davis, Milton C.

    2008-01-01

    This presentation discusses fractured leads on field-programmable gate array (FPGA) during flight vibration. Actions taken to determine root cause and resolution of the failure include finite element analysis (FEA) and vibration testing and scanning electron microscopy (with X-ray microanalysis) and energy dispersive spectrometry (SEM/EDS) failure assessment. Bonding methods for surface mount parts is assessed, including critical analysis and assessment of random fatigue damage. Regarding ceramic quad flat pack (CQFP) lead fracture, after disassembling the attitude control electronics (ACE) configuration, photographs showed six leads cracked on FPGA RTSX72SU-1 CQ208B package located on the RWIC card. An identical package (FPGA RTSX32SU-1 CQ208B) mounted on the RWIC did not results in cracked pins due to vibration. FPGA lead failure theories include workmanship issues in the lead-forming, material defect in the leads of the FPGA packages, and the insecure mounting of the board in the card guides, among other theories. Studies were conducted using simple calculations to determine the response and fatigue life of the package. Shorter packages exhibited more response when loaded by out-of-plane displacement of PCB while taller packages exhibit more response when loaded by in-plane acceleration of PCB. Additionally, under-fill did not contribute to reducing stress in leads due to out-of-plane PCB loading or from component twisting, as much as corner bonding. The combination of corner bond and under-fill is best to address mechanical and thermal S/C environment. Test results of bonded parts showed reduced (dampened) amplitude and slightly shifted peaks at the un-bonded natural frequency and an additional response at the bonded frequency. Stress due to PCBB out-of-plane loading was decreased on in the corners when only a corner bond was used. Future work may address CQFP fatigue assessment, including the investigation of discrepancy in predicted fatigue damage, as well as

  9. LHCb Topological Trigger Reoptimization

    NASA Astrophysics Data System (ADS)

    Likhomanenko, Tatiana; Ilten, Philip; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-12-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so- called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all ’interesting” decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. Methods studied include cascading, ensembling and blending techniques. Furthermore, novel boosting techniques have been implemented that will help reduce systematic uncertainties in Run 2 measurements. We demonstrate that the reoptimized topological trigger is expected to significantly improve on the Run 1 performance for a wide range of b-hadron decays.

  10. Software for implementing trigger algorithms on the upgraded CMS Global Trigger System

    NASA Astrophysics Data System (ADS)

    Matsushita, Takashi; Arnold, Bernhard

    2015-12-01

    The Global Trigger is the final step of the CMS Level-1 Trigger and implements a trigger menu, a set of selection requirements applied to the final list of trigger objects. The conditions for trigger object selection, with possible topological requirements on multiobject triggers, are combined by simple combinatorial logic to form the algorithms. The LHC has resumed its operation in 2015, the collision-energy will be increased to 13 TeV with the luminosity expected to go up to 2x1034 cm-2s-1. The CMS Level-1 trigger system will be upgraded to improve its performance for selecting interesting physics events and to operate within the predefined data-acquisition rate in the challenging environment expected at LHC Run 2. The Global Trigger will be re-implemented on modern FPGAs on an Advanced Mezzanine Card in MicroTCA crate. The upgraded system will benefit from the ability to process complex algorithms with DSP slices and increased processing resources with optical links running at 10 Gbit/s, enabling more algorithms at a time than previously possible and allowing CMS to be more flexible in how it handles the trigger bandwidth. In order to handle the increased complexity of the trigger menu implemented on the upgraded Global Trigger, a set of new software has been developed. The software allows a physicist to define a menu with analysis-like triggers using intuitive user interface. The menu is then realised on FPGAs with further software processing, instantiating predefined firmware blocks. The design and implementation of the software for preparing a menu for the upgraded CMS Global Trigger system are presented.

  11. FPGA-based real-time anisotropic diffusion filtering of 3D ultrasound images

    NASA Astrophysics Data System (ADS)

    Castro-Pareja, Carlos R.; Dandekar, Omkar S.; Shekhar, Raj

    2005-02-01

    Three-dimensional ultrasonic imaging, especially the emerging real-time version of it, is particularly valuable in medical applications such as echocardiography, obstetrics and surgical navigation. A known problem with ultrasound images is their high level of speckle noise. Anisotropic diffusion filtering has been shown to be effective in enhancing the visual quality of 3D ultrasound images and as preprocessing prior to advanced image processing. However, due to its arithmetic complexity and the sheer size of 3D ultrasound images, it is not possible to perform online, real-time anisotropic diffusion filtering using standard software implementations. We present an FPGA-based architecture that allows performing anisotropic diffusion filtering of 3D images at acquisition rates, thus enabling the use of this filtering technique in real-time applications, such as visualization, registration and volume rendering.

  12. Performance of the ATLAS trigger system

    NASA Astrophysics Data System (ADS)

    Casadei, Diego

    2012-12-01

    The ATLAS trigger has been used very successfully to collect collision data during 2009-2011 LHC running at centre of mass energies between 900 GeV and 7 TeV. The three-level trigger system reduces the event rate from the design bunch-crossing rate of 40 MHz to an average recording rate of about 300 Hz. The first level uses custom electronics to reject most background events, in less than 2.5 μs, using information from the calorimeter and muon detectors. The upper two trigger levels are software-based triggers. The trigger system selects events by identifying signatures of muon, electron, photon, tau lepton, jet, and B meson candidates, as well as using global event signatures, such as missing transverse energy. We give an overview of the performance of these trigger selections based on extensive online running during the 2011 LHC run and discuss issues encountered during 2011 operations. We describe how the trigger has evolved with increasing LHC luminosity coping with pile-up conditions close to LHC design luminosity.

  13. Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

    NASA Astrophysics Data System (ADS)

    Li, Ce; Dong, Yiping; Watanabe, Takahiro

    An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR[1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.

  14. Design for Review - Applying Lessons Learned to Improve the FPGA Review Process

    NASA Technical Reports Server (NTRS)

    Figueiredo, Marco A.; Li, Kenneth E.

    2014-01-01

    Flight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.

  15. Dealing with Asthma Triggers

    MedlinePlus

    ... smell given off by paint or gas, and air pollution. If you notice that an irritant triggers your ... or other tobacco products around you. If outdoor air pollution is a problem, running the air conditioner or ...

  16. ELECTRONIC TRIGGER CIRCUIT

    DOEpatents

    Russell, J.A.G.

    1958-01-01

    An electronic trigger circuit is described of the type where an output pulse is obtained only after an input voltage has cqualed or exceeded a selected reference voltage. In general, the invention comprises a source of direct current reference voltage in series with an impedance and a diode rectifying element. An input pulse of preselected amplitude causes the diode to conduct and develop a signal across the impedance. The signal is delivered to an amplifier where an output pulse is produced and part of the output is fed back in a positive manner to the diode so that the amplifier produces a steep wave front trigger pulsc at the output. The trigger point of the described circuit is not subject to variation due to the aging, etc., of multi-electrode tabes, since the diode circuit essentially determines the trigger point.

  17. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

    DOEpatents

    Asaad, Sameth W.; Kapur, Mohit

    2016-01-05

    A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

  18. Reduction in ATP levels triggers immunoproteasome activation by the 11S (PA28) regulator during early antiviral response mediated by IFNβ in mouse pancreatic β-cells.

    PubMed

    Freudenburg, Wieke; Gautam, Madhav; Chakraborty, Pradipta; James, Jared; Richards, Jennifer; Salvatori, Alison S; Baldwin, Aaron; Schriewer, Jill; Buller, R Mark L; Corbett, John A; Skowyra, Dorota

    2013-01-01

    Autoimmune destruction of insulin producing pancreatic β-cells is the hallmark of type I diabetes. One of the key molecules implicated in the disease onset is the immunoproteasome, a protease with multiple proteolytic sites that collaborates with the constitutive 19S and the inducible 11S (PA28) activators to produce immunogenic peptides for presentation by MHC class I molecules. Despite its importance, little is known about the function and regulation of the immunoproteasome in pancreatic β-cells. Of special interest to immunoproteasome activation in β-cells are the effects of IFNβ, a type I IFN secreted by virus-infected cells and implicated in type I diabetes onset, compared to IFNγ, the classic immunoproteasome inducer secreted by cells of the immune system. By qPCR analysis, we show that mouse insulinoma MIN6 cells and mouse islets accumulate the immune proteolytic β1(i), β2(i) and β5(i), and 11S mRNAs upon exposure to IFNβ or IFNγ. Higher concentrations of IFNβ than IFNγ are needed for similar expression, but in each case the expression is transient, with maximal mRNA accumulation in 12 hours, and depends primarily on Interferon Regulatory Factor 1. IFNs do not alter expression of regular proteasome genes, and in the time frame of IFNβ-mediated response, the immune and regular proteolytic subunits co-exist in the 20S particles. In cell extracts with ATP, these particles have normal peptidase activities and degrade polyubiquitinated proteins with rates typical of the regular proteasome, implicating normal regulation by the 19S activator. However, ATP depletion rapidly stimulates the catalytic rates in a manner consistent with levels of the 11S activator. These findings suggest that stochastic combination of regular and immune proteolytic subunits may increase the probability with which unique immunogenic peptides are produced in pancreatic β-cells exposed to IFNβ, but primarily in cells with reduced ATP levels that stimulate the 11S

  19. Report of the Odyssey FPGA Independent Assessment Team

    NASA Technical Reports Server (NTRS)

    Mayer, Donald C.; Katz, Richard B.; Osborn, Jon V.; Soden, Jerry M.; Barto, R.; Day, John H. (Technical Monitor)

    2001-01-01

    An independent assessment team (IAT) was formed and met on April 2, 2001, at Lockheed Martin in Denver, Colorado, to aid in understanding a technical issue for the Mars Odyssey spacecraft scheduled for launch on April 7, 2001. An RP1280A field-programmable gate array (FPGA) from a lot of parts common to the SIRTF, Odyssey, and Genesis missions had failed on a SIRTF printed circuit board. A second FPGA from an earlier Odyssey circuit board was also known to have failed and was also included in the analysis by the IAT. Observations indicated an abnormally high failure rate for flight RP1280A devices (the first flight lot produced using this flow) at Lockheed Martin and the causes of these failures were not determined. Standard failure analysis techniques were applied to these parts, however, additional diagnostic techniques unique for devices of this class were not used, and the parts were prematurely submitted to a destructive physical analysis, making a determination of the root cause of failure difficult. Any of several potential failure scenarios may have caused these failures, including electrostatic discharge, electrical overstress, manufacturing defects, board design errors, board manufacturing errors, FPGA design errors, or programmer errors. Several of these mechanisms would have relatively benign consequences for disposition of the parts currently installed on boards in the Odyssey spacecraft if established as the root cause of failure. However, other potential failure mechanisms could have more dire consequences. As there is no simple way to determine the likely failure mechanisms with reasonable confidence before Odyssey launch, it is not possible for the IAT to recommend a disposition for the other parts on boards in the Odyssey spacecraft based on sound engineering principles.

  20. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    PubMed

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat). PMID:26451812

  1. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    PubMed

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  2. The CDF silicon vertex trigger

    SciTech Connect

    B. Ashmanskas; A. Barchiesi; A. Bardi

    2003-06-23

    The CDF experiment's Silicon Vertex Trigger is a system of 150 custom 9U VME boards that reconstructs axial tracks in the CDF silicon strip detector in a 15 {mu}sec pipeline. SVT's 35 {mu}m impact parameter resolution enables CDF's Level 2 trigger to distinguish primary and secondary particles, and hence to collect large samples of hadronic bottom and charm decays. We review some of SVT's key design features. Speed is achieved with custom VLSI pattern recognition, linearized track fitting, pipelining, and parallel processing. Testing and reliability are aided by built-in logic state analysis and test-data sourcing at each board's input and output, a common inter-board data link, and a universal ''Merger'' board for data fan-in/fan-out. Speed and adaptability are enhanced by use of modern FPGAs.

  3. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    NASA Astrophysics Data System (ADS)

    Gonzalez, Juan; Núñez, Rafael C.

    2009-07-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  4. Enhanced Temperature Control Method Using ANFIS with FPGA

    PubMed Central

    Zhou, Jun-Tin

    2014-01-01

    Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS) using a field-programmable gate array (FPGA) to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV) inductively-coupled plasma- (ICP-) type etcher. PMID:24715808

  5. Enhanced temperature control method using ANFIS with FPGA.

    PubMed

    Huang, Chiung-Wei; Pan, Shing-Tai; Zhou, Jun-Tin; Chang, Cheng-Yuan

    2014-01-01

    Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS) using a field-programmable gate array (FPGA) to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV) inductively-coupled plasma- (ICP-) type etcher. PMID:24715808

  6. Enhanced temperature control method using ANFIS with FPGA.

    PubMed

    Huang, Chiung-Wei; Pan, Shing-Tai; Zhou, Jun-Tin; Chang, Cheng-Yuan

    2014-01-01

    Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS) using a field-programmable gate array (FPGA) to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV) inductively-coupled plasma- (ICP-) type etcher.

  7. Evaluation of power costs in applying TMR to FPGA designs.

    SciTech Connect

    Rollins, Nathaniel; Wirthlin, M. J.; Graham, P. S.

    2004-01-01

    Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by single event upsets (SEUs). The SEU immunity that TMR provides comes at the cost of increased design area and decreased speed. Additionally, the cost of increased power due to TMR must be considered. This paper evaluates the power costs of TMR and validates the evaluations with actual measurements. Sensitivity to design placement is another important part of this study. Power consumption costs due to TMR are also evaluated in different FPGA architectures. This study shows that power consumption rises in the range of 3x to 7x when TMR is applied to a design.

  8. FPGA systems development based on universal controller module

    NASA Astrophysics Data System (ADS)

    Graczyk, Rafał; Pożniak, Krzysztof T.; Romaniuk, Ryszard S.

    2008-01-01

    This paper describes hardware and software concept of Universal Controller Module (UCM), a FPGA/PowerPC based embedded system designed to work as a part of VME system. UCM, on one hand, provides access to the VME crate with various laboratory or industrial interfaces like gigabit optical links, 10/100 Mbit Ethernet, Universal Serial Bus (USB), Controller Area Network (CAN), on the other hand UCM is a well prepared platform for further investigations and development in IP cores field, in functionality expansion by PCI Mezzanine Card (PMC).

  9. Adaptive 4~64 QAM real-time coherent optical transmission over 320 km with FPGA-based transmitter and receiver.

    PubMed

    Yoshida, Masato; Hirooka, Toshihiko; Kasai, Keisuke; Nakazawa, Masataka

    2014-06-30

    We demonstrate the first real-time adaptive optical coherent QAM transmission with variable multiplicities (4-, 16- and 64-QAM) using an FPGA-based transmitter and receiver. Rate-variable transmission (20~60 Gbit/s) was successfully achieved with a polarization multiplexing scheme at 5 Gsymbol/s over 320 km, where the OSNR margins were increased by 9 and 17 dB, respectively, by changing the modulation level from 64 to 16 and 4.

  10. The new UA1 calorimeter trigger processor

    SciTech Connect

    Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagadera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.

    1989-02-01

    The UA1 First Level Trigger Processor (TP) is a fast digital machine with a highly parallel pipelined architecture of fast TTL combinational and programmable logic controlled by programmable microsequencers. The TP uses 100,000 IC's housed in 18 crates each containing 21 fastbus sized modules. It is hardwired with a very high level of interconnection. The energy deposited in the upgraded calorimeter is digitised into 1700 bytes of input data every beam crossing. The Processor selects in 1.5 microseconds events for further processing. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electro-magnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented.

  11. Graphics Processing Units for HEP trigger systems

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Bauce, M.; Biagioni, A.; Chiozzi, S.; Cotta Ramusino, A.; Fantechi, R.; Fiorini, M.; Giagu, S.; Gianoli, A.; Lamanna, G.; Lonardo, A.; Messina, A.; Neri, I.; Paolucci, P. S.; Piandani, R.; Pontisso, L.; Rescigno, M.; Simula, F.; Sozzi, M.; Vicini, P.

    2016-07-01

    General-purpose computing on GPUs (Graphics Processing Units) is emerging as a new paradigm in several fields of science, although so far applications have been tailored to the specific strengths of such devices as accelerator in offline computation. With the steady reduction of GPU latencies, and the increase in link and memory throughput, the use of such devices for real-time applications in high-energy physics data acquisition and trigger systems is becoming ripe. We will discuss the use of online parallel computing on GPU for synchronous low level trigger, focusing on CERN NA62 experiment trigger system. The use of GPU in higher level trigger system is also briefly considered.

  12. Improvement of FPGA control via high speed but high latency interfaces

    NASA Astrophysics Data System (ADS)

    Zabołotny, Wojciech M.

    2015-09-01

    In last years, the throughput of interfaces used in computer systems to control extension boards or external hardware has increased significantly. Unfortunately, those interfaces have also significant round-trip latency. This fact seriously impairs the efficiency of those control algorithms, which require a tight handshake. In such algorithms, the communication consists of a sequence of write and read operations, where read result (the handshake status) must be checked before the next write command is issued. This problem can be solved by the implementation of an intelligent controller in the controlled hardware. This controller should execute high-level commands locally performing all necessary handshake operations. Unfortunately, such a complex and highly specialized controller would consume a significant amount of FPGA resources. This paper presents an alternative approach which uses a highly simplified versatile controller implemented in FPGA. This simple controller may improve the efficiency of certain, relatively broad class of control algorithms. The proposed controller accepts a set of simple commands, which describe the write operations, read operations, and simple test operations. The control algorithm is described as a sequence of those operations. If the controlled hardware works correctly, all tests are passed, and the controller only notifies the host about successful completion. In case if certain handshake test fails, the host is notified about the position of the failed test and type of failure. That allows the controlling software to investigate and cure the problem. The controller may be also used in a standard mode, where status or result of each command is returned immediately and may be checked before the next command is issued. The paper also proposes a simple method for writing of software, which uses the new controller. This method allows to implement the control procedures that are very similar to those using traditional controllers. That

  13. 40-Gbps optical backbone network deep packet inspection based on FPGA

    NASA Astrophysics Data System (ADS)

    Zuo, Yuan; Huang, Zhiping; Su, Shaojing

    2014-11-01

    In the era of information, the big data, which contains huge information, brings about some problems, such as high speed transmission, storage and real-time analysis and process. As the important media for data transmission, the Internet is the significant part for big data processing research. With the large-scale usage of the Internet, the data streaming of network is increasing rapidly. The speed level in the main fiber optic communication of the present has reached 40Gbps, even 100Gbps, therefore data on the optical backbone network shows some features of massive data. Generally, data services are provided via IP packets on the optical backbone network, which is constituted with SDH (Synchronous Digital Hierarchy). Hence this method that IP packets are directly mapped into SDH payload is named POS (Packet over SDH) technology. Aiming at the problems of real time process of high speed massive data, this paper designs a process system platform based on ATCA for 40Gbps POS signal data stream recognition and packet content capture, which employs the FPGA as the CPU. This platform offers pre-processing of clustering algorithms, service traffic identification and data mining for the following big data storage and analysis with high efficiency. Also, the operational procedure is proposed in this paper. Four channels of 10Gbps POS signal decomposed by the analysis module, which chooses FPGA as the kernel, are inputted to the flow classification module and the pattern matching component based on TCAM. Based on the properties of the length of payload and net flows, buffer management is added to the platform to keep the key flow information. According to data stream analysis, DPI (deep packet inspection) and flow balance distribute, the signal is transmitted to the backend machine through the giga Ethernet ports on back board. Practice shows that the proposed platform is superior to the traditional applications based on ASIC and NP.

  14. Trigger mechanism for engines

    SciTech Connect

    Clark, L.R.

    1989-02-28

    A trigger mechanism is described for a blower-vacuum apparatus having a trigger mounted within a handle and a small engine comprising: a throttle; a ''L'' shaped lever having first and second legs mounted for rotation about an intermediate pivot within the handle when the trigger is depressed, interconnecting the trigger and the throttle, the second leg having first teeth defined therein, the lever further having idle, full throttle and stop positions; a normally raised latch means adapted to be rotated and axially depressed, the latch means having second teeth situated on a cam to engage the first teeth for holding the lever in an intermediate position between the idle and full throttle positions when the latch means is rotated. The latch means further are cam teeth into potential engagement with the lever teeth when the trigger is depressed, lever is biased to the stop position; and idle adjusting means means for intercepting the second leg for preventing the second leg from reaching the stop position when the latch means is raised.

  15. Cygnus Trigger System

    SciTech Connect

    G. Corrow, M. Hansen, D. Henderson, C. Mitton

    2008-02-01

    The Cygnus Dual Beam Radiographic Facility consists of two radiographic sources (Cygnus 1, Cygnus 2) each with a dose rating of 4 rads at 1 m, and a 1-mm diameter spot size. The electrical specifications are: 2.25 MV, 60 kA, 60 ns. This facility is located in an underground environment at the Nevada Test Site (NTS). These sources were developed as a primary diagnostic for subcritical tests, which are single-shot, high-value events. In such an application there is an emphasis on reliability and reproducibility. A robust, low-jitter trigger system is a key element for meeting these goals. The trigger system was developed with both commercial and project-specific equipment. In addition to the traditional functions of a trigger system there are novel features added to protect the investment of a high-value shot. Details of the trigger system, including elements designed specifically for a subcritical test application, will be presented. The individual electronic components have their nominal throughput, and when assembled have a system throughput with a measured range of jitter. The shot-to-shot jitter will be assessed both individually and in combination. Trigger reliability and reproducibility results will be presented for a substantial number of shots executed at the NTS.

  16. Trigger-less readout system with pulse pile-up recovery for the PANDA electromagnetic calorimeter

    NASA Astrophysics Data System (ADS)

    Kavatsyuk, M.; Tambave, G.; Hevinga, M.; Lemmens, P. J. J.; Schakel, P.; Schreuder, F.; Speelman, R.; Löhner, H.; Panda Collaboration

    2013-08-01

    A simple, efficient, and robust on-line data-processing scheme was developed for the digital front-end electronics of the electromagnetic calorimeter of the PANDA spectrometer at FAIR, Darmstadt. The implementation of the processing algorithm in FPGA enables the construction of an almost dead-time free data acquisition system. The prototype of a complete trigger-less readout chain has been developed and evaluated. The precision of time synchronisation commands has been verified. A pile-up recovery algorithm was developed and evaluated over a large dynamic range of signal amplitudes.

  17. Efficient Multiplexer FPGA Block Structures Based on G4FETs

    NASA Technical Reports Server (NTRS)

    Vatan, Farrokh; Fijany, Amir

    2009-01-01

    Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few

  18. Energy Efficient Biomolecular Simulations with FPGA-based Reconfigurable Computing

    SciTech Connect

    Hampton, Scott S; Agarwal, Pratul K

    2010-05-01

    Reconfigurable computing (RC) is being investigated as a hardware solution for improving time-to-solution for biomolecular simulations. A number of popular molecular dynamics (MD) codes are used to study various aspects of biomolecules. These codes are now capable of simulating nanosecond time-scale trajectories per day on conventional microprocessor-based hardware, but biomolecular processes often occur at the microsecond time-scale or longer. A wide gap exists between the desired and achievable simulation capability; therefore, there is considerable interest in alternative algorithms and hardware for improving the time-to-solution of MD codes. The fine-grain parallelism provided by Field Programmable Gate Arrays (FPGA) combined with their low power consumption make them an attractive solution for improving the performance of MD simulations. In this work, we use an FPGA-based coprocessor to accelerate the compute-intensive calculations of LAMMPS, a popular MD code, achieving up to 5.5 fold speed-up on the non-bonded force computations of the particle mesh Ewald method and up to 2.2 fold speed-up in overall time-to-solution, and potentially an increase by a factor of 9 in power-performance efficiencies for the pair-wise computations. The results presented here provide an example of the multi-faceted benefits to an application in a heterogeneous computing environment.

  19. FPGA Implementation of Metastability-Based True Random Number Generator

    NASA Astrophysics Data System (ADS)

    Hata, Hisashi; Ichikawa, Shuichi

    True random number generators (TRNGs) are important as a basis for computer security. Though there are some TRNGs composed of analog circuit, the use of digital circuits is desired for the application of TRNGs to logic LSIs. Some of the digital TRNGs utilize jitter in free-running ring oscillators as a source of entropy, which consume large power. Another type of TRNG exploits the metastability of a latch to generate entropy. Although this kind of TRNG has been mostly implemented with full-custom LSI technology, this study presents an implementation based on common FPGA technology. Our TRNG is comprised of logic gates only, and can be integrated in any kind of logic LSI. The RS latch in our TRNG is implemented as a hard-macro to guarantee the quality of randomness by minimizing the signal skew and load imbalance of internal nodes. To improve the quality and throughput, the output of 64-256 latches are XOR'ed. The derived design was verified on a Xilinx Virtex-4 FPGA (XC4VFX20), and passed NIST statistical test suite without post-processing. Our TRNG with 256 latches occupies 580 slices, while achieving 12.5Mbps throughput.

  20. An FPGA-based rapid wheezing detection system.

    PubMed

    Lin, Bor-Shing; Yen, Tian-Shiue

    2014-02-01

    Wheezing is often treated as a crucial indicator in the diagnosis of obstructive pulmonary diseases. A rapid wheezing detection system may help physicians to monitor patients over the long-term. In this study, a portable wheezing detection system based on a field-programmable gate array (FPGA) is proposed. This system accelerates wheezing detection, and can be used as either a single-process system, or as an integrated part of another biomedical signal detection system. The system segments sound signals into 2-second units. A short-time Fourier transform was used to determine the relationship between the time and frequency components of wheezing sound data. A spectrogram was processed using 2D bilateral filtering, edge detection, multithreshold image segmentation, morphological image processing, and image labeling, to extract wheezing features according to computerized respiratory sound analysis (CORSA) standards. These features were then used to train the support vector machine (SVM) and build the classification models. The trained model was used to analyze sound data to detect wheezing. The system runs on a Xilinx Virtex-6 FPGA ML605 platform. The experimental results revealed that the system offered excellent wheezing recognition performance (0.912). The detection process can be used with a clock frequency of 51.97 MHz, and is able to perform rapid wheezing classification.

  1. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

    PubMed

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2015-01-01

    Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

  2. Grey relational clustering associated with CAPRI applied to FPGA placement

    NASA Astrophysics Data System (ADS)

    Wu, Jan-Ou; Fan, Yang-Hsin; Wang, San-Fu

    2016-04-01

    Grey relational clustering is used to minimise wire length during field programmable gate arrays (FPGA) placement and routing. The proposed Grey Relational Clustering Apply to Placement (GRAP) algorithm combines grey relational clustering and convex assigned placement for regular ICs method to construct a placement netlist, which was successfully used to solve the problem of minimising wire length in an FPGA placement. Upon calculating the grey relational grade, GRAP can rank the sequence and analyse the minimal distance in configuration logic blocks based on the grey relational sequence and combined connection-based approaches. The experimental results demonstrate that the GRAP effectively compares the Hibert, Z and Snake with bounding box (BB) cost function in the space-filling curve. The GRAP improved BB cost by 0.753%, 0.324% and 0.096% for the Hilbert, Z and Snake, respectively. This study also compares the critical path with the space-filling curve. The GRAP approach improved the critical path for Snake by 1.3% in the space-filling curve; however, the GRAP increased critical path wire by 1.38% and 0.03% over that of the Hilbert and Z of space-filling curve, respectively.

  3. Research on defogging technology of video image based on FPGA

    NASA Astrophysics Data System (ADS)

    Liu, Shuo; Piao, Yan

    2015-03-01

    As the effect of atmospheric particles scattering, the video image captured by outdoor surveillance system has low contrast and brightness, which directly affects the application value of the system. The traditional defogging technology is mostly studied by software for the defogging algorithms of the single frame image. Moreover, the algorithms have large computation and high time complexity. Then, the defogging technology of video image based on Digital Signal Processing (DSP) has the problem of complex peripheral circuit. It can't be realized in real-time processing, and it's hard to debug and upgrade. In this paper, with the improved dark channel prior algorithm, we propose a kind of defogging technology of video image based on Field Programmable Gate Array (FPGA). Compared to the traditional defogging methods, the video image with high resolution can be processed in real-time. Furthermore, the function modules of the system have been designed by hardware description language. At last, the results show that the defogging system based on FPGA can process the video image with minimum resolution of 640×480 in real-time. After defogging, the brightness and contrast of video image are improved effectively. Therefore, the defogging technology proposed in the paper has a great variety of applications including aviation, forest fire prevention, national security and other important surveillance.

  4. An FPGA-Based Rapid Wheezing Detection System

    PubMed Central

    Lin, Bor-Shing; Yen, Tian-Shiue

    2014-01-01

    Wheezing is often treated as a crucial indicator in the diagnosis of obstructive pulmonary diseases. A rapid wheezing detection system may help physicians to monitor patients over the long-term. In this study, a portable wheezing detection system based on a field-programmable gate array (FPGA) is proposed. This system accelerates wheezing detection, and can be used as either a single-process system, or as an integrated part of another biomedical signal detection system. The system segments sound signals into 2-second units. A short-time Fourier transform was used to determine the relationship between the time and frequency components of wheezing sound data. A spectrogram was processed using 2D bilateral filtering, edge detection, multithreshold image segmentation, morphological image processing, and image labeling, to extract wheezing features according to computerized respiratory sound analysis (CORSA) standards. These features were then used to train the support vector machine (SVM) and build the classification models. The trained model was used to analyze sound data to detect wheezing. The system runs on a Xilinx Virtex-6 FPGA ML605 platform. The experimental results revealed that the system offered excellent wheezing recognition performance (0.912). The detection process can be used with a clock frequency of 51.97 MHz, and is able to perform rapid wheezing classification. PMID:24481034

  5. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces

    PubMed Central

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A.; Castellanos-Ramos, Julián; Hidalgo-López, José A.

    2015-01-01

    Direct sensor–digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor. PMID:26694403

  6. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

    PubMed

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2015-01-01

    Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor. PMID:26694403

  7. Design of extensible meteorological data acquisition system based on FPGA

    NASA Astrophysics Data System (ADS)

    Zhang, Wen; Liu, Yin-hua; Zhang, Hui-jun; Li, Xiao-hui

    2015-02-01

    In order to compensate the tropospheric refraction error generated in the process of satellite navigation and positioning. Temperature, humidity and air pressure had to be used in concerned models to calculate the value of this error. While FPGA XC6SLX16 was used as the core processor, the integrated silicon pressure sensor MPX4115A and digital temperature-humidity sensor SHT75 are used as the basic meteorological parameter detection devices. The core processer was used to control the real-time sampling of ADC AD7608 and to acquire the serial output data of SHT75. The data was stored in the BRAM of XC6SLX16 and used to generate standard meteorological parameters in NEMA format. The whole design was based on Altium hardware platform and ISE software platform. The system was described in the VHDL language and schematic diagram to realize the correct detection of temperature, humidity, air pressure. The 8-channel synchronous sampling characteristics of AD7608 and programmable external resources of FPGA laid the foundation for the increasing of analog or digital meteorological element signal. The designed meteorological data acquisition system featured low cost, high performance, multiple expansions.

  8. Anti Theft Mechanism Through Face recognition Using FPGA

    NASA Astrophysics Data System (ADS)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  9. Microfabricated triggered vacuum switch

    DOEpatents

    Roesler, Alexander W.; Schare, Joshua M.; Bunch, Kyle

    2010-05-11

    A microfabricated vacuum switch is disclosed which includes a substrate upon which an anode, cathode and trigger electrode are located. A cover is sealed over the substrate under vacuum to complete the vacuum switch. In some embodiments of the present invention, a metal cover can be used in place of the trigger electrode on the substrate. Materials used for the vacuum switch are compatible with high vacuum, relatively high temperature processing. These materials include molybdenum, niobium, copper, tungsten, aluminum and alloys thereof for the anode and cathode. Carbon in the form of graphitic carbon, a diamond-like material, or carbon nanotubes can be used in the trigger electrode. Channels can be optionally formed in the substrate to mitigate against surface breakdown.

  10. The ATLAS trigger - commissioning with cosmic rays

    NASA Astrophysics Data System (ADS)

    Boyd, J.

    2008-07-01

    The ATLAS detector at CERN's LHC will be exposed to proton-proton collisions from beams crossing at 40 MHz. At the design luminosity there are roughly 23 collisions per bunch crossing. ATLAS has designed a three-level trigger system to select potentially interesting events. The first-level trigger, implemented in custom-built electronics, reduces the incoming rate to less than 100 kHz with a total latency of less than 2.5μs. The next two trigger levels run in software on commercial PC farms. They reduce the output rate to 100-200 Hz. In preparation for collision data-taking which is scheduled to commence in May 2008, several cosmic-ray commissioning runs have been performed. Among the first sub-detectors available for commissioning runs are parts of the barrel muon detector including the RPC detectors that are used in the first-level trigger. Data have been taken with a full slice of the muon trigger and readout chain, from the detectors in one sector of the RPC system, to the second-level trigger algorithms and the data-acquisition system. The system is being prepared to include the inner-tracking detector in the readout and second-level trigger. We will present the status and results of these cosmic-ray based commissioning activities. This work will prove to be invaluable not only during the commissioning phase but also for cosmic-ray data-taking during the normal running for detector performance studies.

  11. Development of FPGA-based safety-related I and C systems

    SciTech Connect

    Goto, Y.; Oda, N.; Miyazaki, T.; Hayashi, T.; Sato, T.; Igawa, S.

    2006-07-01

    Toshiba has developed Non-rewritable (NRW) Field Programmable Gate Array (FPGA)-based safety-related Instrumentation and Control (I and C) system [1]. Considering application to safety-related systems, nonvolatile and non-rewritable FPGA which is impossible to be changed after once manufactured has been adopted in Toshiba FPGA-based system. FPGA is a device which consists only of defined digital circuit: hardware, which performs defined processing. FPGA-based system solves issues existing both in the conventional systems operated by analog circuits (analog-based system) and the systems operated by central processing unit (CPU-based system). The advantages of applying FPGA are to keep the long-life supply of products, improving testability (verification), and to reduce the drift which may occur in analog-based system. The system which Toshiba developed this time is Power Range Monitor (PRM). Toshiba is planning to expand application of FPGA-based technology by adopting this development method to the other safety-related systems from now on. (authors)

  12. Video Event Trigger

    NASA Technical Reports Server (NTRS)

    Williams, Glenn L.; Lichter, Michael J.

    1994-01-01

    Video event trigger (VET) processes video image data to generate trigger signal when image shows significant change like motion or appearance, disappearance, change in color, change in brightness, or dilation of object. System aids in efficient utilization of image-data-storage and image-data-processing equipment in applications in which many video frames show no changes and are wasteful to record and analyze all frames when only relatively few frames show changes of interest. Applications include video recording of automobile crash tests, automated video monitoring of entrances, exits, parking lots, and secure areas.

  13. MicroBlaze implementation of GPS/INS integrated system on Virtex-6 FPGA.

    PubMed

    Bhogadi, Lokeswara Rao; Gottapu, Sasi Bhushana Rao; Konala, Vvs Reddy

    2015-01-01

    The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described in this paper. The inertial navigation solution and Kalman filter computations are provided by the MicroBlaze on Virtex-6 FPGA. The real time processed navigation solutions are updated with a rate of 100 Hz.

  14. MicroBlaze implementation of GPS/INS integrated system on Virtex-6 FPGA.

    PubMed

    Bhogadi, Lokeswara Rao; Gottapu, Sasi Bhushana Rao; Konala, Vvs Reddy

    2015-01-01

    The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described in this paper. The inertial navigation solution and Kalman filter computations are provided by the MicroBlaze on Virtex-6 FPGA. The real time processed navigation solutions are updated with a rate of 100 Hz. PMID:26543763

  15. Triggered plasma opening switch

    DOEpatents

    Mendel, Clifford W.

    1988-01-01

    A triggerable opening switch for a very high voltage and current pulse includes a transmission line extending from a source to a load and having an intermediate switch section including a plasma for conducting electrons between transmission line conductors and a magnetic field for breaking the plasma conduction path and magnetically insulating the electrons when it is desired to open the switch.

  16. Disambiguating Syntactic Triggers

    ERIC Educational Resources Information Center

    Sakas, William Gregory; Fodor, Janet Dean

    2012-01-01

    We present data from an artificial language domain that suggest new contributions to the theory of syntactic triggers. Whether a learning algorithm is capable of matching the achievements of child learners depends in part on how much parametric ambiguity there is in the input. For practical reasons this cannot be established for the domain of all…

  17. Triggered plasma opening switch

    SciTech Connect

    Mendel, C W

    1988-02-23

    A triggerable opening switch for a very high voltage and current pulse includes a transmission line extending from a source to a load and having an intermediate switch section including a plasma for conducting electrons between transmission line conductors and a magnetic field for breaking the plasma conduction path and magnetically insulating the electrons when it is desired to open the switch.

  18. Remotely triggered earthquakes following moderate main shocks

    USGS Publications Warehouse

    Hough, S.E.

    2007-01-01

    Since 1992, remotely triggered earthquakes have been identified following large (M > 7) earthquakes in California as well as in other regions. These events, which occur at much greater distances than classic aftershocks, occur predominantly in active geothermal or volcanic regions, leading to theories that the earthquakes are triggered when passing seismic waves cause disruptions in magmatic or other fluid systems. In this paper, I focus on observations of remotely triggered earthquakes following moderate main shocks in diverse tectonic settings. I summarize evidence that remotely triggered earthquakes occur commonly in mid-continent and collisional zones. This evidence is derived from analysis of both historic earthquake sequences and from instrumentally recorded M5-6 earthquakes in eastern Canada. The latter analysis suggests that, while remotely triggered earthquakes do not occur pervasively following moderate earthquakes in eastern North America, a low level of triggering often does occur at distances beyond conventional aftershock zones. The inferred triggered events occur at the distances at which SmS waves are known to significantly increase ground motions. A similar result was found for 28 recent M5.3-7.1 earthquakes in California. In California, seismicity is found to increase on average to a distance of at least 200 km following moderate main shocks. This supports the conclusion that, even at distances of ???100 km, dynamic stress changes control the occurrence of triggered events. There are two explanations that can account for the occurrence of remotely triggered earthquakes in intraplate settings: (1) they occur at local zones of weakness, or (2) they occur in zones of local stress concentration. ?? 2007 The Geological Society of America.

  19. Extending the BEAGLE library to a multi-FPGA platform

    PubMed Central

    2013-01-01

    Background Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein’s pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein’s pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. Results The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform’s peak memory bandwidth and the implementation’s memory efficiency, as 2.03 × peak bandwidth × memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a ~40X speedup when compared with BEAGLE’s CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE’s GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. Conclusions The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design

  20. FPGA-based multiprocessor system for injection molding control.

    PubMed

    Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

    2012-01-01

    The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

  1. Luminance uniformity compensation for OLED panels based on FPGA

    NASA Astrophysics Data System (ADS)

    Ou, Peng; Yang, Gang; Jiang, Quan; Yu, Jun-Sheng; Wu, Qi-Peng; Shang, Fu-Hai; Yin, Wei; Wang, Jun; Zhong, Jian; Luo, Kai-Jun

    2009-09-01

    Aiming at the problem of luminance uniformity for organic lighting-emitting diode (OLED) panels, a new brightness calculating method based on bilinear interpolation is proposed. The irradiance time of each pixel reaching the same luminance is figured out by Matlab. Adopting the 64×32-pixel, single color and passive matrix OLED panel as adjusting luminance uniformity panel, a new circuit compensating scheme based on FPGA is designed. VHDL is used to make each pixel’s irradiance time in one frame period written in program. The irradiance brightness is controlled by changing its irradiance time, and finally, luminance compensation of the panel is realized. The simulation result indicates that the design is reasonable.

  2. FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

    PubMed Central

    Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

    2012-01-01

    This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs. PMID:22778640

  3. Reconfigurable Gabor Filter For Fingerprint Recognition Using FPGA Verilog

    NASA Astrophysics Data System (ADS)

    Rosshidi, H. T.; Hadi, A. R.

    2009-06-01

    This paper present the implementations of Gabor filter for fingerprint recognition using Verilog HDL. This work demonstrates the application of Gabor Filter technique to enhance the fingerprint image. The incoming signal in form of image pixel will be filter out or convolute by the Gabor filter to define the ridge and valley regions of fingerprint. This is done with the application of a real time convolve based on Field Programmable Gate Array (FPGA) to perform the convolution operation. The main characteristic of the proposed approach are the usage of memory to store the incoming image pixel and the coefficient of the Gabor filter before the convolution matrix take place. The result was the signal convoluted with the Gabor coefficient.

  4. Active Cancellation of Acoustical Resonances with an FPGA FIR Filter

    NASA Astrophysics Data System (ADS)

    Ryou, Albert; Simon, Jonathan

    2016-05-01

    We demonstrate a novel approach to enhancing the closed-loop bandwidth of a feedback-controlled mechanical system by digitally cancelling its acoustical resonances and antiresonances with an FPGA FIR filter. By performing a real-time convolution of the feedback error signal with an arbitrary filter, we can suppress arbitrarily many poles and zeros below 100 kHz, each with a linewidth as small as 10 Hz. We demonstrate the efficacy of this technique by cancelling the six largest resonances and antiresonances of a high-finesse optical resonator piezomechanical transfer function, thereby enhancing the unity gain frequency by more than an order of magnitude. More broadly, this approach is applicable to stabilization of optical resonators, external cavity diode lasers, and scanning tunneling microscopes.

  5. An FPGA-based platform for accelerated offline spike sorting.

    PubMed

    Gibson, Sarah; Judy, Jack W; Marković, Dejan

    2013-04-30

    There is a push in electrophysiology experiments to record simultaneously from many channels (upwards of 64) over long time periods (many hours). Given the relatively high sampling rates (10-40 kHz) and resolutions (12-24 bits per sample), these experiments accumulate exorbitantly large amounts of data (e.g., 100 GB per experiment), which can be very time-consuming to process. Here, we present an FPGA-based spike-sorting platform that can increase the speed of offline spike sorting by at least 25 times, effectively reducing the time required to sort data from long experiments from several hours to just a few minutes. We attempted to preserve the flexibility of software by implementing several different algorithms in the design, and by providing user control over parameters such as spike detection thresholds. The results of sorting a published benchmark dataset using this hardware tool are shown to be comparable to those using similar software tools.

  6. Exploring Manycore Multinode Systems for Irregular Applications with FPGA Prototyping

    SciTech Connect

    Ceriani, Marco; Palermo, Gianluca; Secchi, Simone; Tumeo, Antonino; Villa, Oreste

    2013-04-29

    We present a prototype of a multi-core architecture implemented on FPGA, designed to enable efficient execution of irregular applications on distributed shared memory machines, while maintaining high performance on regular workloads. The architecture is composed of off-the-shelf soft-core cores, local interconnection and memory interface, integrated with custom components that optimize it for irregular applications. It relies on three key elements: a global address space, multithreading, and fine-grained synchronization. Global addresses are scrambled to reduce the formation of network hot-spots, while the latency of the transactions is covered by integrating an hardware scheduler within the custom load/store buffers to take advantage from the availability of multiple executions threads, increasing the efficiency in a transparent way to the application. We evaluated a dual node system irregular kernels showing scalability in the number of cores and threads.

  7. FPGA implementation of glass-free stereo vision

    NASA Astrophysics Data System (ADS)

    Tang, Weidong; Yan, Xiaolin

    2016-04-01

    This paper presents a real-time efficient glass-free 3D system, which is based on FPGA. The system converts two-view input that is 60 frames per second (fps) 1080P stream into a multi-view video with 30fps and 4K resolution. In order to provide smooth and comfortable viewing experience, glass-free 3D systems must display multi-view videos. To generate a multi-view video from a two-view input includes three steps, the first is to compute disparity maps from two input views; the second is to synthesize a couple of new views based on the computed disparity maps and input views; the last is to produce video from the new views according to the specifications of the lens installed on TV sets.

  8. Hardware accelerated compression of LIDAR data using FPGA devices.

    PubMed

    Biasizzo, Anton; Novak, Franc

    2013-05-14

    Airborne Light Detection and Ranging (LIDAR) has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

  9. FPGA acceleration of rigid-molecule docking codes

    PubMed Central

    Sukhwani, B.; Herbordt, M.C.

    2011-01-01

    Modelling the interactions of biological molecules, or docking, is critical both to understanding basic life processes and to designing new drugs. The field programmable gate array (FPGA) based acceleration of a recently developed, complex, production docking code is described. The authors found that it is necessary to extend their previous three-dimensional (3D) correlation structure in several ways, most significantly to support simultaneous computation of several correlation functions. The result for small-molecule docking is a 100-fold speed-up of a section of the code that represents over 95% of the original run-time. An additional 2% is accelerated through a previously described method, yielding a total acceleration of 36× over a single core and 10× over a quad-core. This approach is found to be an ideal complement to graphics processing unit (GPU) based docking, which excels in the protein–protein domain. PMID:21857870

  10. Method to implement the CCD timing generator based on FPGA

    NASA Astrophysics Data System (ADS)

    Li, Binhua; Song, Qian; He, Chun; Jin, Jianhui; He, Lin

    2010-07-01

    With the advance of the PFPA technology, the design methodology of digital systems is changing. In recent years we develop a method to implement the CCD timing generator based on FPGA and VHDL. This paper presents the principles and implementation skills of the method. Taking a developed camera as an example, we introduce the structure, input and output clocks/signals of a timing generator implemented in the camera. The generator is composed of a top module and a bottom module. The bottom one is made up of 4 sub-modules which correspond to 4 different operation modes. The modules are implemented by 5 VHDL programs. Frame charts of the architecture of these programs are shown in the paper. We also describe implementation steps of the timing generator in Quartus II, and the interconnections between the generator and a Nios soft core processor which is the controller of this generator. Some test results are presented in the end.

  11. A Digitalized Silicon Microgyroscope Based on Embedded FPGA

    PubMed Central

    Xia, Dunzhu; Yu, Cheng; Wang, Yuliang

    2012-01-01

    This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG) with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA) chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC) loop and software phase-locked loop (SPLL) based on the Coordinated Rotation Digital Computer (CORDIC) algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD) are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system. PMID:23201990

  12. FPGA-Based Multiprocessor System for Injection Molding Control

    PubMed Central

    Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

    2012-01-01

    The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

  13. 160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA)

    PubMed Central

    Li, Isaac TS; Shum, Warren; Truong, Kevin

    2007-01-01

    Background To infer homology and subsequently gene function, the Smith-Waterman (SW) algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching. PMID:17555593

  14. FPGA-based gating and logic for multichannel single photon counting

    SciTech Connect

    Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G; Williams, Brian P; Schaake, Jason; Humble, Travis S

    2012-01-01

    We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)

  15. FPGA platform for prototyping and evaluation of neural network automotive applications

    NASA Technical Reports Server (NTRS)

    Aranki, N.; Tawel, R.

    2002-01-01

    In this paper we present an FPGA based reconfigurable computing platform for prototyping and evaluation of advanced neural network based applications for control and diagnostics in an automotive sub-systems.

  16. Evaluation of a segmentation algorithm designed for an FPGA implementation

    NASA Astrophysics Data System (ADS)

    Schwenk, Kurt; Schönermark, Maria; Huber, Felix

    2013-10-01

    The present work has to be seen in the context of real-time on-board image evaluation of optical satellite data. With on board image evaluation more useful data can be acquired, the time to get requested information can be decreased and new real-time applications are possible. Because of the relative high processing power in comparison to the low power consumption, Field Programmable Gate Array (FPGA) technology has been chosen as an adequate hardware platform for image processing tasks. One fundamental part for image evaluation is image segmentation. It is a basic tool to extract spatial image information which is very important for many applications such as object detection. Therefore a special segmentation algorithm using the advantages of FPGA technology has been developed. The aim of this work is the evaluation of this algorithm. Segmentation evaluation is a difficult task. The most common way for evaluating the performance of a segmentation method is still subjective evaluation, in which human experts determine the quality of a segmentation. This way is not in compliance with our needs. The evaluation process has to provide a reasonable quality assessment, should be objective, easy to interpret and simple to execute. To reach these requirements a so called Segmentation Accuracy Equality norm (SA EQ) was created, which compares the difference of two segmentation results. It can be shown that this norm is capable as a first quality measurement. Due to its objectivity and simplicity the algorithm has been tested on a specially chosen synthetic test model. In this work the most important results of the quality assessment will be presented.

  17. Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

    NASA Technical Reports Server (NTRS)

    Jamot, Robert F.; Monroe, Ryan M.

    2012-01-01

    With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

  18. Performance and upgrade plans of the LHCb trigger system

    NASA Astrophysics Data System (ADS)

    Gligorov, V. V.; LHCb Collaboration

    2013-08-01

    The trigger of the LHCb experiment consists of two stages: an initial hardware trigger, and a high-level trigger implemented in a farm of parallel-processing CPUs. It reduces the event rate from an input of 15 MHz to an output rate of around 4 kHz. In order to maximize efficiencies and minimize biases, the trigger is designed around inclusive selection algorithms, culminating in a novel boosted decision tree which enables the efficient selection of beauty hadron decays based on a robust partial reconstruction of their decay products. In order to improve performance, the LHCb upgrade aims to significantly increase the rate at which the detector will be read out, and hence shift more of the workload onto the high-level trigger. It is demonstrated that the current high-level trigger architecture will be able to meet this challenge, and the expected efficiencies in several key channels are discussed in context of the LHCb upgrade.

  19. GBT link testing and performance measurement on PCIe40 and AMC40 custom design FPGA boards

    NASA Astrophysics Data System (ADS)

    Mitra, Jubin; Khan, Shuaib A.; Barros Marin, Manoel; Cachemiche, Jean-Pierre; David, Erno; Hachon, Frédéric; Rethore, Frédéric; Kiss, Tivadar; Baron, Sophie; Kluge, Alex; Nayak, Tapan K.

    2016-03-01

    The high-energy physics experiments at the CERN's Large Hadron Collider (LHC) are preparing for Run3, which is foreseen to start in the year 2021. Data from the high radiation environment of the detector front-end electronics are transported to the data processing units, located in low radiation zones through GBT (Gigabit transceiver) links. The present work discusses the GBT link performance study carried out on custom FPGA boards, clock calibration logic and its implementation in new Arria 10 FPGA.

  20. Neural networks for triggering

    SciTech Connect

    Denby, B. ); Campbell, M. ); Bedeschi, F. ); Chriss, N.; Bowers, C. ); Nesti, F. )

    1990-01-01

    Two types of neural network beauty trigger architectures, based on identification of electrons in jets and recognition of secondary vertices, have been simulated in the environment of the Fermilab CDF experiment. The efficiencies for B's and rejection of background obtained are encouraging. If hardware tests are successful, the electron identification architecture will be tested in the 1991 run of CDF. 10 refs., 5 figs., 1 tab.

  1. Hardware and Software Design of FPGA-based PCIe Gen3 interface for APEnet+ network interconnect system

    NASA Astrophysics Data System (ADS)

    Ammendola, R.; Biagioni, A.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Rossetti, D.; Simula, F.; Tosoratto, L.; Vicini, P.

    2015-12-01

    In the attempt to develop an interconnection architecture optimized for hybrid HPC systems dedicated to scientific computing, we designed APEnet+, a point-to-point, low-latency and high-performance network controller supporting 6 fully bidirectional off-board links over a 3D torus topology. The first release of APEnet+ (named V4) was a board based on a 40 nm Altera FPGA, integrating 6 channels at 34 Gbps of raw bandwidth per direction and a PCIe Gen2 x8 host interface. It has been the first-of-its-kind device to implement an RDMA protocol to directly read/write data from/to Fermi and Kepler NVIDIA GPUs using NVIDIA peer-to-peer and GPUDirect RDMA protocols, obtaining real zero-copy GPU-to-GPU transfers over the network. The latest generation of APEnet+ systems (now named V5) implements a PCIe Gen3 x8 host interface on a 28 nm Altera Stratix V FPGA, with multi-standard fast transceivers (up to 14.4 Gbps) and an increased amount of configurable internal resources and hardware IP cores to support main interconnection standard protocols. Herein we present the APEnet+ V5 architecture, the status of its hardware and its system software design. Both its Linux Device Driver and the low-level libraries have been redeveloped to support the PCIe Gen3 protocol, introducing optimizations and solutions based on hardware/software co-design.

  2. Dopamine triggers heterosynaptic plasticity.

    PubMed

    Ishikawa, Masago; Otaka, Mami; Huang, Yanhua H; Neumann, Peter A; Winters, Bradley D; Grace, Anthony A; Schlüter, Oliver M; Dong, Yan

    2013-04-17

    As a classic neuromodulator, dopamine has long been thought to modulate, rather than trigger, synaptic plasticity. In contrast, our present results demonstrate that within the parallel projections of dopaminergic and GABAergic terminals from the ventral tegmental area to the nucleus accumbens core (NAcCo), action-potential-activated release of dopamine heterosynaptically triggers LTD at GABAergic synapses, which is likely mediated by activating presynaptically located dopamine D1 class receptors and expressed by inhibiting presynaptic release of GABA. Moreover, this dopamine-mediated heterosynaptic LTD is abolished after withdrawal from cocaine exposure. These results suggest that action-potential-dependent dopamine release triggers very different cellular consequences from those induced by volume release or pharmacological manipulation. Activation of the ventral tegmental area to NAcCo projections is essential for emotional and motivational responses. This dopamine-mediated LTD allows a flexible output of NAcCo neurons, whereas disruption of this LTD may contribute to the rigid emotional and motivational state observed in addicts during cocaine withdrawal.

  3. Decision-making triggers in adaptive management.

    PubMed

    Nie, Martin A; Schultz, Courtney A

    2012-12-01

    We analyzed whether decision-making triggers increase accountability of adaptive-management plans. Triggers are prenegotiated commitments in an adaptive-management plan that specify what actions are to be taken and when on the basis of information obtained from monitoring. Triggers improve certainty that particular actions will be taken by agencies in the future. We conducted an in-depth, qualitative review of the political and legal contexts of adaptive management and its application by U.S. federal agencies. Agencies must satisfy the judiciary that adaptive-management plans meet substantive legal standards and comply with the U.S. National Environmental Policy Act. We examined 3 cases in which triggers were used in adaptive-management plans: salmon (Oncorhynchus spp.) in the Columbia River, oil and gas development by the Bureau of Land Management, and a habitat conservation plan under the U.S. Endangered Species Act. In all the cases, key aspects of adaptive management, including controls and preidentified feedback loops, were not incorporated in the plans. Monitoring and triggered mitigation actions were limited in their enforceability, which was contingent on several factors, including which laws applied in each case and the degree of specificity in how triggers were written into plans. Other controversial aspects of these plans revolved around who designed, conducted, interpreted, and funded monitoring programs. Additional contentious issues were the level of precaution associated with trigger mechanisms and the definition of ecological baselines used as points of comparison. Despite these challenges, triggers can be used to increase accountability, by predefining points at which an adaptive management plan will be revisited and reevaluated, and thus improve the application of adaptive management in its complicated political and legal context. PMID:22891956

  4. AMPLITUDE DISCRIMINATOR HAVING SEPARATE TRIGGERING AND RECOVERY CONTROLS UTILIZING AUTOMATIC TRIGGERING

    DOEpatents

    Chase, R.L.

    1962-01-23

    A transistorized amplitude discriminator circuit is described in which the initial triggering sensitivity and the recovery threshold are separately adjustable in a convenient manner. The discriminator is provided with two independent bias components, one of which is for circuit hysteresis (recovery) and one of which is for trigger threshold level. A switching circuit is provided to remove the second bias component upon activation of the trigger so that the recovery threshold is always at the point where the trailing edge of the input signal pulse goes through zero or other desired value. (AEC)

  5. The central trigger control system of the CMS experiment at CERN

    NASA Astrophysics Data System (ADS)

    Jeitler, M.; Taurok, A.; Bergauer, H.; Kastner, K.; Mikulec, I.; Neuherz, B.; Padrta, M.; Sakulin, H.; Strauss, J.; Wulz, C.-E.

    2010-05-01

    The Level-1 (L1) Trigger of the CMS experiment uses custom-made, fast electronics, while the experiment's high-level trigger is implemented in computer farms. The Central Trigger Control System described in this poster receives physics triggers from the Global Trigger Logic unit, collects information from the various subdetector systems to check if they are ready to accept triggers, reduces excessive trigger rates according to preset rules and finally distributes the trigger ("Level-1 Accept") together with timing signals to the subdetectors over the so-called "Trigger, and Timing and Control" (TTC) network of the experiment. The complete functionality of the Central Trigger Control System is implemented in one 9U-VME module and several ancillary boards for input and output functions. The system has been used successfully during CMS test runs with cosmics and beam.

  6. Bufalin induces G0/G1 phase arrest through inhibiting the levels of cyclin D, cyclin E, CDK2 and CDK4, and triggers apoptosis via mitochondrial signaling pathway in T24 human bladder cancer cells.

    PubMed

    Huang, Wen-Wen; Yang, Jai-Sing; Pai, Shu-Jen; Wu, Ping-Ping; Chang, Shu-Jen; Chueh, Fu-Shin; Fan, Ming-Jen; Chiou, Shang-Ming; Kuo, Hsiu-Maan; Yeh, Chin-Chung; Chen, Po-Yuan; Tsuzuki, Minoru; Chung, Jing-Gung

    2012-04-01

    Most of the chemotherapy treatments for bladder cancer aim to kill the cancer cells, but a high recurrence rate after medical treatments is still occurred. Bufalin from the skin and parotid venom glands of toad has been shown to induce apoptotic cell death in many types of cancer cell lines. However, there is no report addressing that bufalin induced cell death in human bladder cancer cells. The purpose of this study was investigated the mechanisms of bufalin-induced apoptosis in a human bladder cancer cell line (T24). We demonstrated the effects of bufalin on the cell growth and apoptosis in T24 cells by using DAPI/TUNEL double staining, a PI exclusion and flow cytometric analysis. The effects of bufalin on the production of reactive oxygen species (ROS), the level of mitochondrial membrane potential (ΔΨ(m)), and DNA content including sub-G1 (apoptosis) in T24 cells were also determined by flow cytometry. Western blot analysis was used to examine the expression of G(0)/G(1) phase-regulated and apoptosis-associated protein levels in bufalin-treated T24 cells. The results indicated that bufalin significantly decreased the percentage of viability, induced the G(0)/G(1) phase arrest and triggered apoptosis in T24 cells. The down-regulation of the protein levels for cyclin D, CDK4, cyclin E, CDK2, phospho-Rb, phospho-AKT and Bcl-2 with the simultaneous up-regulation of the cytochrome c, Apaf-1, AIF, caspase-3, -7 and -9 and Bax protein expressions and caspase activities were observed in T24 cells after bufalin treatment. Based on our results, bufalin induces apoptotic cell death in T24 cells through suppressing AKT activity and anti-apoptotic Bcl-2 protein as well as inducing pro-apoptotic Bax protein. The levels of caspase-3, -7 and -9 are also mediated apoptosis in bufalin-treated T24 cells. Therefore, bufalin might be used as a therapeutic agent for the treatment of human bladder cancer in the future.

  7. Bufalin induces G0/G1 phase arrest through inhibiting the levels of cyclin D, cyclin E, CDK2 and CDK4, and triggers apoptosis via mitochondrial signaling pathway in T24 human bladder cancer cells.

    PubMed

    Huang, Wen-Wen; Yang, Jai-Sing; Pai, Shu-Jen; Wu, Ping-Ping; Chang, Shu-Jen; Chueh, Fu-Shin; Fan, Ming-Jen; Chiou, Shang-Ming; Kuo, Hsiu-Maan; Yeh, Chin-Chung; Chen, Po-Yuan; Tsuzuki, Minoru; Chung, Jing-Gung

    2012-04-01

    Most of the chemotherapy treatments for bladder cancer aim to kill the cancer cells, but a high recurrence rate after medical treatments is still occurred. Bufalin from the skin and parotid venom glands of toad has been shown to induce apoptotic cell death in many types of cancer cell lines. However, there is no report addressing that bufalin induced cell death in human bladder cancer cells. The purpose of this study was investigated the mechanisms of bufalin-induced apoptosis in a human bladder cancer cell line (T24). We demonstrated the effects of bufalin on the cell growth and apoptosis in T24 cells by using DAPI/TUNEL double staining, a PI exclusion and flow cytometric analysis. The effects of bufalin on the production of reactive oxygen species (ROS), the level of mitochondrial membrane potential (ΔΨ(m)), and DNA content including sub-G1 (apoptosis) in T24 cells were also determined by flow cytometry. Western blot analysis was used to examine the expression of G(0)/G(1) phase-regulated and apoptosis-associated protein levels in bufalin-treated T24 cells. The results indicated that bufalin significantly decreased the percentage of viability, induced the G(0)/G(1) phase arrest and triggered apoptosis in T24 cells. The down-regulation of the protein levels for cyclin D, CDK4, cyclin E, CDK2, phospho-Rb, phospho-AKT and Bcl-2 with the simultaneous up-regulation of the cytochrome c, Apaf-1, AIF, caspase-3, -7 and -9 and Bax protein expressions and caspase activities were observed in T24 cells after bufalin treatment. Based on our results, bufalin induces apoptotic cell death in T24 cells through suppressing AKT activity and anti-apoptotic Bcl-2 protein as well as inducing pro-apoptotic Bax protein. The levels of caspase-3, -7 and -9 are also mediated apoptosis in bufalin-treated T24 cells. Therefore, bufalin might be used as a therapeutic agent for the treatment of human bladder cancer in the future. PMID:22285700

  8. The D/Ø Silicon Track Trigger

    NASA Astrophysics Data System (ADS)

    Steinbrück, Georg

    2003-09-01

    We describe a trigger preprocessor to be used by the D Ø experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam.

  9. CMS muon detector and trigger performance

    NASA Astrophysics Data System (ADS)

    Piccolo, Davide; CMS Collaboration

    2011-02-01

    In the CMS experiment at the LHC proton-proton collider, a key role will be played by the muon system that is embedded inside the iron yoke used to close the magnetic flux of the CMS solenoid. The muon system of the CMS experiment performs three main tasks: triggering of muons, identifying muons, and assisting the central tracker in order to measure the momentum and charge of high-pt muons in the pseudorapidity region |η|≤2.4. The system is composed by a central barrel and two closing endcaps. Three independent technologies are used to reconstruct and trigger muons: Drift Tubes (DT) in the barrel, Cathode Strips Chambers (CSC) in the endcaps and Resistive Plate Chambers (RPC) in both barrel and endcap regions. All the detectors will contribute to the tracking and triggering of muons. Towards the end of 2008 and in 2009 the CMS experiment was commissioned with many millions of cosmic rays. These data have been fundamental to check the performance of the three sub-detectors and of the trigger response. In this paper the results in terms of the detection and trigger performance at the level of each sub-detector and at the level of the full muon system will be reported.

  10. Triggering filamentation using turbulence

    NASA Astrophysics Data System (ADS)

    Eeltink, D.; Berti, N.; Marchiando, N.; Hermelin, S.; Gateau, J.; Brunetti, M.; Wolf, J. P.; Kasparian, J.

    2016-09-01

    We study the triggering of single filaments due to turbulence in the beam path for a laser of power below the filamenting threshold. Turbulence can act as a switch between the beam not filamenting and producing single filaments. This positive effect of turbulence on the filament probability, combined with our observation of off-axis filaments, suggests the underlying mechanism is modulation instability caused by transverse perturbations. We hereby experimentally explore the interaction of modulation instability and turbulence, commonly associated with multiple filaments, in the single-filament regime.

  11. Subnanosecond trigger system for ETA

    SciTech Connect

    Cook, E.G.; Lauer, E.J.; Reginato, L.L.; Rogers D.; Schmidt, J.A.

    1980-05-30

    A high-voltage trigger system capable of triggering 30, 250 kV spark gaps; each with less than +- 1 ns jitter has been constructed. In addition to low jitter rates, the trigger system must be capable of delivering the high voltage pulses to the spark gaps either simultaneously or sequentially as determined by other system requirements. The trigger system consists of several stages of pulse amplification culminating in 160 kV pulses having 30 ns risetime. The trigger system is described and test data provided.

  12. Mark-II Data Acquisition and Trigger system

    SciTech Connect

    Breidenbach, M.

    1984-06-01

    The Mark-II Data Acquisition and Trigger system requirements and general solution are described. The solution takes advantage of the synchronous crossing times and low event rates of an electron positron collider to permit a very highly multiplexed analog scheme to be effective. The system depends on a two level trigger to operate with acceptable dead time. The trigger, multiplexing, data reduction, calibration, and CAMAC systems are described.

  13. A VXIbus based trigger for the CLAS detector at CEBAF

    SciTech Connect

    D.C. Doughty, Jr.; J. Englert; R. Hale; S. Lemon; P. Leung; C. Cuevas; D. Joyce

    1992-04-01

    A VXIbus based first level triggering system for the CLAS detector at CEBAF has been designed and prototyped. It uses pipelining and a triple memory lookup to produce a dead-timeless trigger decision with an average latency of 110 nS and a jitter of 20 nS. The VXIbus Extended Start/Stop triggering protocols allow sub-nanosecond time synchronization.

  14. A VXIbus based trigger for the CLAS detector at CEBAF

    SciTech Connect

    Doughty, D.C. Jr.; Englert, J.; Hale, R.; Lemon, S. ); Leung, P. ); Cuevas, C.; Joyce, D. )

    1992-04-01

    This paper discusses a VXIbus based first level triggering system for the CLAS detector at CEBAF which has been designed and prototyped. It uses pipelining and a triple memory lookup to produce a dead-timeless trigger decision with an average latency of 110 ns and a jitter of 20 ns. The VXIbus Extended Start/Stop triggering protocols allow sub-nanosecond time synchronization.

  15. Trigger point therapy.

    PubMed

    Janssens, L A

    1992-03-01

    Trigger points (TP) are objectively demonstrable foci in muscles. They are painful on compression and trigger pain in a referred area. This area may be the only locus of complaint in humans. In dogs we cannot prove the existence of referred zones of pain. Therefore, we can only diagnose a TP-induced claudication if we cannot find bone, joint, or neurologic abnormalities, and we do find TP that disappear after treatment together with the original lameness. Several methods have been developed to demonstrate TP existence objectively. These are pressure algometry, pressure threshold measurements, magnetic resonance thermography, and histology. In humans, 71% of the TP described are acupuncture points. TP treatment consists of TP stimulation with non-invasive or invasive methods such as dry needling or injections. In the dog, ten TP are described in two categories of clinical patients. First, those with one or few TP reacting favorably on treatment (+/- 80% success in +/- 2-3 weeks). Second, those with many TPs reacting badly on treatment. Most probably the latter group are fibromyalgia patients.

  16. The upgraded HADES trigger and data acquisition system

    NASA Astrophysics Data System (ADS)

    Michel, J.; Böhmer, M.; Kajetanowicz, M.; Korcyl, G.; Maier, L.; Palka, M.; Stroth, J.; Tarantola, A.; Traxler, M.; Ugur, C.; Yurevich, S.

    2011-12-01

    The HADES experiment is a High Acceptance Di-Electron Spectrometer located at GSI in Darmstadt, Germany. Recently, its trigger and data acquisition system was upgraded. The main goal was to substantially increase the event rate capability by a factor of up to 20 to reach 100 kHz in light and 20 kHz in heavy ion reaction systems. The total data rate written to storage is about 400 MByte/s in peak. In this context, the complete read-out system was exchanged to FPGA-based platforms using optical communication. For data transport a general-purpose real-time network protocol was developed to meet the strong requirements of the system. In particular, trigger information has to reach all front-end modules with latencies of less than 5 μs through up to 10 intermediate hubs in a star-like network setup. Monitoring and slow control features as well as readout and trigger distribution were joined in a single network protocol made up by three virtual channels with inherent arbitration by priority and a typical switching time of 100 ns. The full DAQ system includes about 550 FPGAs distributed over the complete detector system. For control and monitoring a virtual address space spanning the whole network is provided. Data are merged by the network hubs into data streams and passed on to a server farm using an Ethernet infrastructure. Due to the electromagnetic noise environment, several transmission error detection and correction features were included. In collaboration with groups from experiments of the FAIR accelerator complex, further developments based on the versatile hardware and communication protocol are being pursued.

  17. Use of GPUs in Trigger Systems

    NASA Astrophysics Data System (ADS)

    Lamanna, Gianluca

    In recent years the interest for using graphics processor (GPU) in general purpose high performance computing is constantly rising. In this paper we discuss the possible use of GPUs to construct a fast and effective real time trigger system, both in software and hardware levels. In particular, we study the integration of such a system in the NA62 trigger. The first application of GPUs for rings pattern recognition in the RICH will be presented. The results obtained show that there are not showstoppers in trigger systems with relatively low latency. Thanks to the use of off-the-shelf technology, in continous development for purposes related to video game and image processing market, the architecture described would be easily exported to other experiments, to build a versatile and fully customizable online selection.

  18. Tau Trigger at the ATLAS Experiment

    SciTech Connect

    Benslama, K.; Kalinowski, A.; Belanger-Champange, C.; Brenner, R.; Bosman, M.; Casado, P.; Osuna, C.; Perez, E.; Vorwerk, V.; Czyczula, Z.; Dam, M.; Xella, S.; Demers, S.; Farrington, S.; Igonkina, O.; Kanaya, N.; Tsuno, S.; Ptacek, E.; Reinsch, A.; Strom, David M.; Torrence, E.; /Oregon U. /Sydney U. /Lancaster U. /Birmingham U.

    2011-11-09

    Many theoretical models, like the Standard Model or SUSY at large tan({beta}), predict Higgs bosons or new particles which decay more abundantly to final states including tau leptons than to other leptons. At the energy scale of the LHC, the identification of tau leptons, in particular in the hadronic decay mode, will be a challenging task due to an overwhelming QCD background which gives rise to jets of particles that can be hard to distinguish from hadronic tau decays. Equipped with excellent tracking and calorimetry, the ATLAS experiment has developed tau identification tools capable of working at the trigger level. This contribution presents tau trigger algorithms which exploit the main features of hadronic tau decays and describes the current tau trigger commissioning activities. Many of the SM processes being investigated at ATLAS, as well as numerous BSM searches, contain tau leptons in their final states. Being able to trigger effectively on the tau leptons in these events will contribute to the success of the ATLAS experiment. The tau trigger algorithms and monitoring infrastructure are ready for the first data, and are being tested with the data collected with cosmic muons. The development of efficiency measurements methods using QCD and Z {yields} {tau}{tau} events is well advanced.

  19. A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

    NASA Astrophysics Data System (ADS)

    Parsons, Aaron; Backer, Donald; Siemion, Andrew; Chen, Henry; Werthimer, Dan; Droz, Pierre; Filiba, Terry; Manley, Jason; McMahon, Peter; Parsa, Arash; MacMahon, David; Wright, Melvyn

    2008-11-01

    A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field of view, by employing high-performance digital signal-processing hardware to phase and correlate signals from large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN2, where BB is the signal bandwidth, MM is the number of independent beams, and NN is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general-purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal-processing libraries that we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal-processing systems, with correlators foremost among them, and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full-Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.

  20. FPGA Based Real-time Network Traffic Analysis using Traffic Dispersion Patterns

    SciTech Connect

    Khan, F; Gokhale, M; Chuah, C N

    2010-03-26

    The problem of Network Traffic Classification (NTC) has attracted significant amount of interest in the research community, offering a wide range of solutions at various levels. The core challenge is in addressing high amounts of traffic diversity found in today's networks. The problem becomes more challenging if a quick detection is required as in the case of identifying malicious network behavior or new applications like peer-to-peer traffic that have potential to quickly throttle the network bandwidth or cause significant damage. Recently, Traffic Dispersion Graphs (TDGs) have been introduced as a viable candidate for NTC. The TDGs work by forming a network wide communication graphs that embed characteristic patterns of underlying network applications. However, these patterns need to be quickly evaluated for mounting real-time response against them. This paper addresses these concerns and presents a novel solution for real-time analysis of Traffic Dispersion Metrics (TDMs) in the TDGs. We evaluate the dispersion metrics of interest and present a dedicated solution on an FPGA for their analysis. We also present analytical measures and empirically evaluate operating effectiveness of our design. The mapped design on Virtex-5 device can process 7.4 million packets/second for a TDG comprising of 10k flows at very high accuracies of over 96%.

  1. Latent myofascial trigger points.

    PubMed

    Ge, Hong-You; Arendt-Nielsen, Lars

    2011-10-01

    A latent myofascial trigger point (MTP) is defined as a focus of hyperirritability in a muscle taut band that is clinically associated with local twitch response and tenderness and/or referred pain upon manual examination. Current evidence suggests that the temporal profile of the spontaneous electrical activity at an MTP is similar to focal muscle fiber contraction and/or muscle cramp potentials, which contribute significantly to the induction of local tenderness and pain and motor dysfunctions. This review highlights the potential mechanisms underlying the sensory-motor dysfunctions associated with latent MTPs and discusses the contribution of central sensitization associated with latent MTPs and the MTP network to the spatial propagation of pain and motor dysfunctions. Treating latent MTPs in patients with musculoskeletal pain may not only decrease pain sensitivity and improve motor functions, but also prevent latent MTPs from transforming into active MTPs, and hence, prevent the development of myofascial pain syndrome.

  2. Gravity triggered neutrino condensates

    SciTech Connect

    Barenboim, Gabriela

    2010-11-01

    In this work we use the Schwinger-Dyson equations to study the possibility that an enhanced gravitational attraction triggers the formation of a right-handed neutrino condensate, inducing dynamical symmetry breaking and generating a Majorana mass for the right-handed neutrino at a scale appropriate for the seesaw mechanism. The composite field formed by the condensate phase could drive an early epoch of inflation. We find that to the lowest order, the theory does not allow dynamical symmetry breaking. Nevertheless, thanks to the large number of matter fields in the model, the suppression by additional powers in G of higher order terms can be compensated, boosting them up to their lowest order counterparts. This way chiral symmetry can be broken dynamically and the infrared mass generated turns out to be in the expected range for a successful seesaw scenario.

  3. FPGA based digital phase-coding quantum key distribution system

    NASA Astrophysics Data System (ADS)

    Lu, XiaoMing; Zhang, LiJun; Wang, YongGang; Chen, Wei; Huang, DaJun; Li, Deng; Wang, Shuang; He, DeYong; Yin, ZhenQiang; Zhou, Yu; Hui, Cong; Han, ZhengFu

    2015-12-01

    Quantum key distribution (QKD) is a technology with the potential capability to achieve information-theoretic security. Phasecoding is an important approach to develop practical QKD systems in fiber channel. In order to improve the phase-coding modulation rate, we proposed a new digital-modulation method in this paper and constructed a compact and robust prototype of QKD system using currently available components in our lab to demonstrate the effectiveness of the method. The system was deployed in laboratory environment over a 50 km fiber and continuously operated during 87 h without manual interaction. The quantum bit error rate (QBER) of the system was stable with an average value of 3.22% and the secure key generation rate is 8.91 kbps. Although the modulation rate of the photon in the demo system was only 200 MHz, which was limited by the Faraday-Michelson interferometer (FMI) structure, the proposed method and the field programmable gate array (FPGA) based electronics scheme have a great potential for high speed QKD systems with Giga-bits/second modulation rate.

  4. LoFASM's FPGA-based Digital Acquisition System

    NASA Astrophysics Data System (ADS)

    Dartez, Louis P.; Jenet, F.; Creighton, T. D.; Ford, A. J.; Hicks, B.; Hinojosa, J.; Kassim, N. E.; Price, R. H.; Stovall, K.; Ray, P. S.; Taylor, G. B.

    2014-01-01

    The Low Frequency All Sky Monitor (LoFASM) is a distributed array of dipole antennas that are sensitive to radio frequencies from 10 to 88 MHz. LoFASM consists of antennas and front end electronics that were originally developed for the Long Wavelength Array (LWA) by the U.S. Naval Research Lab, the University of New Mexico, Virginia Tech, and the Jet Propulsion Laboratory. LoFASM, funded by the U.S. Department of Defense, will initially consist of 4 stations, each consisting of 12 dual-polarization dipole antenna stands. The primary science goals of LoFASM will be the detection and study of low-frequency radio transients, a high priority science goal as deemed by the National Research Council's decadal survey. The data acquisition system for the LoFASM antenna array will be using Field Programmable Gate Array (FPGA) technology to implement a real time full Stokes spectrometer and data recorder. This poster presents an overview of the current design and digital architecture of a single station of the LoFASM array as well as the status of the entire project.

  5. Design and FPGA implementation of VLAN in EPON

    NASA Astrophysics Data System (ADS)

    Liu, Minglai; Lin, Rujian; Huang, Jun

    2005-02-01

    As a promising solution for next-generation broadband access networks, EPON could provide full-service access such as voice, video and data applications. However, EPON"s standard IEEE 802.3ah does not specify a particular supporting mechanism to guarantee QoS and priority requirements of various services, allowing it to be vendor specific. Meanwhile, how to segregate user traffic to guarantee security, remains unsolved. This paper creatively introduced the 802.1Q VLAN (Virtual Local Area Network) technique into the EPON system to solve these problems. Firstly, a brief introduction of EPON system is given. Secondly, the VLAN solution is presented in detail. Unlike VLAN mapping according to port or MAC in Gigabit Ethernet, EPON"s VLAN mapping is based on LLID tag. At last, OLT MAC layer design is given and FPGA implementation is described in detail. Detailed simulation experiments have been conducted to study the performance and validate the effectiveness of the proposed mechanism.

  6. FPGA Control System for the Automated Test of Microshutters

    NASA Technical Reports Server (NTRS)

    Lyness, Eric; Rapchun, David A.; Moseley, S. Harvey

    2008-01-01

    The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light with arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

  7. Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

    PubMed

    Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

    2013-08-01

    Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

  8. An FPGA computing demo core for space charge simulation

    SciTech Connect

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  9. FPGA-specific decimal sign-magnitude addition and subtraction

    NASA Astrophysics Data System (ADS)

    Vázquez, Martín; Todorovich, Elías

    2016-07-01

    The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten's complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.

  10. Cryogenic loss monitors with FPGA TDC signal processing

    SciTech Connect

    Warner, A.; Wu, J.; /Fermilab

    2011-09-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highlight the processing techniques used.

  11. FPGA-accelerated algorithm for the regular expression matching system

    NASA Astrophysics Data System (ADS)

    Russek, P.; Wiatr, K.

    2015-01-01

    This article describes an algorithm to support a regular expressions matching system. The goal was to achieve an attractive performance system with low energy consumption. The basic idea of the algorithm comes from a concept of the Bloom filter. It starts from the extraction of static sub-strings for strings of regular expressions. The algorithm is devised to gain from its decomposition into parts which are intended to be executed by custom hardware and the central processing unit (CPU). The pipelined custom processor architecture is proposed and a software algorithm explained accordingly. The software part of the algorithm was coded in C and runs on a processor from the ARM family. The hardware architecture was described in VHDL and implemented in field programmable gate array (FPGA). The performance results and required resources of the above experiments are given. An example of target application for the presented solution is computer and network security systems. The idea was tested on nearly 100,000 body-based viruses from the ClamAV virus database. The solution is intended for the emerging technology of clusters of low-energy computing nodes.

  12. Real-time implementation of camera positioning algorithm based on FPGA & SOPC

    NASA Astrophysics Data System (ADS)

    Yang, Mingcao; Qiu, Yuehong

    2014-09-01

    In recent years, with the development of positioning algorithm and FPGA, to achieve the camera positioning based on real-time implementation, rapidity, accuracy of FPGA has become a possibility by way of in-depth study of embedded hardware and dual camera positioning system, this thesis set up an infrared optical positioning system based on FPGA and SOPC system, which enables real-time positioning to mark points in space. Thesis completion include: (1) uses a CMOS sensor to extract the pixel of three objects with total feet, implemented through FPGA hardware driver, visible-light LED, used here as the target point of the instrument. (2) prior to extraction of the feature point coordinates, the image needs to be filtered to avoid affecting the physical properties of the system to bring the platform, where the median filtering. (3) Coordinate signs point to FPGA hardware circuit extraction, a new iterative threshold selection method for segmentation of images. Binary image is then segmented image tags, which calculates the coordinates of the feature points of the needle through the center of gravity method. (4) direct linear transformation (DLT) and extreme constraints method is applied to three-dimensional reconstruction of the plane array CMOS system space coordinates. using SOPC system on a chip here, taking advantage of dual-core computing systems, which let match and coordinate operations separately, thus increase processing speed.

  13. SEMICONDUCTOR INTEGRATED CIRCUITS: Design for an IO block array in a tile-based FPGA

    NASA Astrophysics Data System (ADS)

    Guangxin, Ding; Lingdou, Chen; Zhongli, Liu

    2009-08-01

    A design for an IO block array in a tile-based FPGA is presented. Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers. Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area. The local routing pool increases the flexibility of routing and the routability of the whole FPGA. An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards. The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool. This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series. The bond-out schemes of the same FPGA chip in different packages are also considered. The layout is based on SMIC 0.13 μm logic 1P8M salicide 1.2/2.5 V CMOS technology. Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

  14. OPENCORE NMR: Open-source core modules for implementing an integrated FPGA-based NMR spectrometer

    NASA Astrophysics Data System (ADS)

    Takeda, Kazuyuki

    2008-06-01

    A tool kit for implementing an integrated FPGA-based NMR spectrometer [K. Takeda, A highly integrated FPGA-based nuclear magnetic resonance spectrometer, Rev. Sci. Instrum. 78 (2007) 033103], referred to as the OPENCORE NMR spectrometer, is open to public. The system is composed of an FPGA chip and several peripheral boards for USB communication, direct-digital synthesis (DDS), RF transmission, signal acquisition, etc. Inside the FPGA chip have been implemented a number of digital modules including three pulse programmers, the digital part of DDS, a digital quadrature demodulator, dual digital low-pass filters, and a PC interface. These FPGA core modules are written in VHDL, and their source codes are available on our website. This work aims at providing sufficient information with which one can, given some facility in circuit board manufacturing, reproduce the OPENCORE NMR spectrometer presented here. Also, the users are encouraged to modify the design of spectrometer according to their own specific needs. A home-built NMR spectrometer can serve complementary roles to a sophisticated commercial spectrometer, should one comes across such new ideas that require heavy modification to hardware inside the spectrometer. This work can lower the barrier of building a handmade NMR spectrometer in the laboratory, and promote novel and exciting NMR experiments.

  15. The Time-of-Flight trigger at CDF

    SciTech Connect

    Bauer, G.; Mulhearn, M.J.; Paus, Ch.; Schieferdecker, P.; Tether, S.; Lewis, J.D.; Shaw, T.; Acosta, D.; Konigsberg, J.; Madorsky, A.; /Florida U.

    2006-05-01

    The Time-of-Flight (TOF) detector measures the arrival time and deposited energy of charged particles reaching scintillator bars surrounding the central tracking region of the CDF detector. Requiring high ionization in the TOF system provides a unique trigger capability, which has been used for a magnetic monopole search. Other uses, with smaller pulse height thresholds, include a high-multiplicity charged-particle trigger useful for QCD studies and a much improved cosmic ray trigger for calibrating other detector components. Although not designed as input to CDF's global Level 1 trigger, the TOF system has been easily adapted to this role by the addition of 24 cables, new firmware, and four custom TOF trigger boards (TOTRIBs). This article describes the TOF trigger.

  16. The ATLAS Data Acquisition and Trigger: concept, design and status

    NASA Astrophysics Data System (ADS)

    Kordas, K.; Abolins, M.; Alexandrov, I.; Amorim, A.; Aracena, I.; Armstrong, S.; Badescu, E.; Baines, J. T. M.; Barros, N.; Beck, H. P.; Bee, C.; Bellomo, M.; Biglietti, M.; Blair, R.; Bogaerts, J. A. C.; Bold, T.; Bosman, M.; Burckhart-Chromek, D.; Caprini, M.; Caramarcu, C.; Carlino, G.; Caron, B.; Casado, M. P.; Cataldi, G.; Ciobotaru, M.; Comune, G.; Conde-Muino, P.; Conventi, F.; Corso-Radu, A.; Cranfield, R.; Cranmer, K.; Crone, G.; Damazio, D.; Dawson, J.; De Santo, A.; Del Prete, T.; Della Pietra, M.; Di Mattia, A.; Diaz-Gomaz, M.; Dobinson, R. W.; Dobson, M.; Dos Anjos, A.; Dotti, A.; Drake, G.; Ellis, N.; Emeliyanov, D.; Ermoline, Y.; Ertorer, E.; Falciano, S.; Ferrari, R.; Ferrer, M. L.; Francis, D.; Gadomski, S.; Gameiro, S.; Garitaonandia, H.; Gaudio, G.; Gaumer, O.; George, S.; Gesualdi-Mello, A.; Goncalo, R.; Gorini, B.; Gorini, E.; Green, B.; Haas, S.; Haberichter, W. N.; Hadavand, H.; Haeberli, C.; Haller, J.; Hansen, J.; Hauser, R.; Hillier, S. J.; Höcker, A.; Hughes-Jones, R. E.; Joos, M.; Kabana, S.; Kazarov, A.; Khomich, A.; Kieft, G.; Kilvington, G.; Kirk, J.; Klous, S.; Kohno, T.; Kolos, S.; Konstantinidis, N.; Kootz, A.; Korcyl, K.; Kotov, V.; Kugel, A.; Landon, M.; Lankford, A.; Leahu, L.; Leahu, M.; Lehmann-Miotto, G.; Le Vine, M. J.; Liu, W.; Lowe, C.; Luminari, L.; Maeno, T.; Männer, R.; Mapelli, L.; Martin, B.; Marzano, F.; Masik, J.; McLaren, R.; McMahon, T.; Meessen, C.; Meirosu, C.; Mineev, M.; Misiejuk, A.; Moore, R.; Morettini, P.; Mornacchi, G.; Müller, M.; Murillo-García, R.; Nagasaka, Y.; Negri, A.; Nisati, A.; Osuna, C.; Padilla, C.; Panikashvili, N.; Parodi, F.; Pasqualucci, E.; Pauly, T.; Perera, V.; Pérez-Réale, V.; Petersen, J.; Pinfold, J. L.; Pope, B.; Portes de Albuquerque, M.; Potter, C.; Pretzl, K.; Prigent, D.; Primavera, M.; Rheaum, P.; Robertson, S.; Roda, C.; Ryabov, Y.; Salvatore, D.; Santamarina-Rios, C.; Scannicchio, D. A.; Schiavi, C.; Schlereth, J. L.; Scholtes, I.; Seixas, M.; Sidoti, A.; Sivoklokov, S.; Sloper, J.; Sole-Segura, E.; Soloviev, I.; Soluk, R.; Spagnolo, S.; Spiwoks, R.; Stamen, R.; Stancu, S.; Stefanidis, E.; Strong, J.; Sushkov, S.; Sutton, M.; Szymocha, T.; Tapprogge, S.; Tarem, S.; Tarem, Z.; Teixeira-Dias, P.; Thomas, E.; Torres, R.; Touchard, F.; Tremblet, L.; Unel, N. G.; Usai, G.; Vachon, B.; Van Wasen, J.; Vandelli, W.; Vaz Gil Lopes, L.; Ventura, A.; Vercesi, V.; Vermeulen, J.; von der Schmitt, H.; Warburton, A.; Watson, A.; Wengler, T.; Werner, P.; Wheeler, S.; Wickens, F.; Wiedenmann, W.; Wielers, M.; Wiesmann, M.; Woehrling, E. E.; Wu, X.; Yasu, Y.; Yu, M.; Zema, F.; Zobernig, H.

    2007-10-01

    This article presents the base-line design and implementation of the ATLAS Trigger and Data Acquisition system, in particular the Data Flow and High Level Trigger components. The status of the installation and commissioning of the system is also presented.

  17. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    PubMed

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

  18. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications

    PubMed Central

    Sun, Li; Savory, Joshua J.; Warncke, Kurt

    2014-01-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range. PMID:25076864

  19. High speed fault tolerant secure communication for muon chamber using FPGA based GBTx emulator

    NASA Astrophysics Data System (ADS)

    Sau, Suman; Mandal, Swagata; Saini, Jogender; Chakrabarti, Amlan; Chattopadhyay, Subhasis

    2015-12-01

    The Compressed Baryonic Matter (CBM) experiment is a part of the Facility for Antiproton and Ion Research (FAIR) in Darmstadt at the GSI. The CBM experiment will investigate the highly compressed nuclear matter using nucleus-nucleus collisions. This experiment will examine lieavy-ion collisions in fixed target geometry and will be able to measure hadrons, electrons and muons. CBM requires precise time synchronization, compact hardware, radiation tolerance, self-triggered front-end electronics, efficient data aggregation schemes and capability to handle high data rate (up to several TB/s). As a part of the implementation of read out chain of Muon Cliamber(MUCH) [1] in India, we have tried to implement FPGA based emulator of GBTx in India. GBTx is a radiation tolerant ASIC that can be used to implement multipurpose high speed bidirectional optical links for high-energy physics (HEP) experiments and is developed by CERN. GBTx will be used in highly irradiated area and more prone to be affected by multi bit error. To mitigate this effect instead of single bit error correcting RS code we have used two bit error correcting (15, 7) BCH code. It will increase the redundancy which in turn increases the reliability of the coded data. So the coded data will be less prone to be affected by noise due to radiation. The data will go from detector to PC through multiple nodes through the communication channel. The computing resources are connected to a network which can be accessed by authorized person to prevent unauthorized data access which might happen by compromising the network security. Thus data encryption is essential. In order to make the data communication secure, advanced encryption standard [2] (AES - a symmetric key cryptography) and RSA [3], [4] (asymmetric key cryptography) are used after the channel coding. We have implemented GBTx emulator on two Xilinx Kintex-7 boards (KC705). One will act as transmitter and other will act as receiver and they are connected

  20. Improved Approach for Utilization of FPGA Technology into DAQ, DSP, and Computing Applications

    SciTech Connect

    Isenhower, Larry Donald

    2009-01-28

    Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

  1. Parallel performance of the fine-grain pipeline FPGA image processing system

    NASA Astrophysics Data System (ADS)

    Gorgoń, M.

    2012-06-01

    The use of FPGA circuits in imaging systems increases. They compete with other computing environments. The article describes the indications to be followed while choosing the type of image processing computing system taking under consideration the advantages and disadvantages of each technology: general purpose processor, digital signal processor, graphical processing unit, application specific Integrated circuit and field programmable gate array. Attention is drawn to various video transmission standards. The state of research and development trends in the field of FPGA-based image processing are briefly presented. A defining processing performance method for image processing is proposed. It is proven that for a pipeline architecture implemented in FPGA, a linear speedup is achieved and parallel efficiency is equal to one.

  2. Implementation of total focusing method for phased array ultrasonic imaging on FPGA

    NASA Astrophysics Data System (ADS)

    Guo, JianQiang; Li, Xi; Gao, Xiaorong; Wang, Zeyong; Zhao, Quanke

    2015-02-01

    This paper describes a multi-FPGA imaging system dedicated for the real-time imaging using the Total Focusing Method (TFM) and Full Matrix Capture (FMC). The system was entirely described using Verilog HDL language and implemented on Altera Stratix IV GX FPGA development board. The whole algorithm process is to: establish a coordinate system of image and divide it into grids; calculate the complete acoustic distance of array element between transmitting array element and receiving array element, and transform it into index value; then index the sound pressure values from ROM and superimpose sound pressure values to get pixel value of one focus point; and calculate the pixel values of all focus points to get the final imaging. The imaging result shows that this algorithm has high SNR of defect imaging. And FPGA with parallel processing capability can provide high speed performance, so this system can provide the imaging interface, with complete function and good performance.

  3. An FPGA-based ultrasound imaging system using capacitive micromachined ultrasonic transducers.

    PubMed

    Wong, Lawrence L P; Chen, Albert I; Logan, Andrew S; Yeow, John T W

    2012-07-01

    We report the design and experimental results of a field-programmable gate array (FPGA)-based real-time ultrasound imaging system that uses a 16-element phased-array capacitive micromachined ultrasonic transducer fabricated using a fusion bonding process. The imaging system consists of the transducer, discrete analog components situated on a custom-made circuit board, the FPGA, and a monitor. The FPGA program consists of five functional blocks: a main counter, transmit and receive beamformer, receive signal pre-processing, envelope detection, and display. No dedicated digital signal processor or personal computer is required for the imaging system. An experiment is carried out to obtain the sector B-scan of a 4-wire target. The ultrasound imaging system demonstrates the possibility of an integrated system-in-a-package solution.

  4. Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.

    PubMed

    Matsubara, Takashi; Torikai, Hiroyuki

    2013-05-01

    A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

  5. An optimized ultrasound digital beamformer with dynamic focusing implemented on FPGA.

    PubMed

    Almekkawy, Mohamed; Xu, Jingwei; Chirala, Mohan

    2014-01-01

    We present a resource-optimized dynamic digital beamformer for an ultrasound system based on a field-programmable gate array (FPGA). A comprehensive 64-channel receive beamformer with full dynamic focusing is embedded in the Altera Arria V FPGA chip. To improve spatial and contrast resolution, full dynamic beamforming is implemented by a novel method with resource optimization. This was conceived using the implementation of the delay summation through a bulk (coarse) delay and fractional (fine) delay. The sampling frequency is 40 MHz and the beamformer includes a 240 MHz polyphase filter that enhances the temporal resolution of the system while relaxing the Analog-to-Digital converter (ADC) bandwidth requirement. The results indicate that our 64-channel dynamic beamformer architecture is amenable for a low power FPGA-based implementation in a portable ultrasound system.

  6. Radiometric Calibration of Mars HiRISE High Resolution Imagery Based on Fpga

    NASA Astrophysics Data System (ADS)

    Hou, Yifan; Geng, Xun; Xing, Shuai; Tang, Yonghe; Xu, Qing

    2016-06-01

    Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA) is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  7. Photoconductive semiconductor switches: Laser Q-switch trigger and switch-trigger laser integration

    SciTech Connect

    Loubriel, G.M.; Mar, A.; Hamil, R.A.; Zutavern, F.J.; Helgeson, W.D.

    1997-12-01

    This report provides a summary of the Pulser In a Chip 9000-Discretionary LDRD. The program began in January of 1997 and concluded in September of 1997. The over-arching goal of this LDRD is to study whether laser diode triggered photoconductive semiconductor switches (PCSS) can be used to activate electro-optic devices such as Q-switches and Pockels cells and to study possible laser diode/switch integration. The PCSS switches we used were high gain GaAs switches because they can be triggered with small amounts of laser light. The specific goals of the LDRD were to demonstrate: (1) that small laser diode arrays that are potential candidates for laser-switch integration will indeed trigger the PCSS switch, and (2) that high gain GaAs switches can be used to trigger optical Q-switches in lasers such as the lasers to be used in the X-1 Advanced Radiation Source and the laser used for direct optical initiation (DOI) of explosives. The technology developed with this LDRD is now the prime candidate for triggering the Q switch in the multiple lasers in the laser trigger system of the X-1 Advanced Radiation Source and may be utilized in other accelerators. As part of the LDRD we developed a commercial supplier. To study laser/switch integration we tested triggering the high gain GaAs switches with: edge emitting laser diodes, vertical cavity surface emitting lasers (VCSELs), and transverse junction stripe (TJS) lasers. The first two types of lasers (edge emitting and VCSELs) did activate the PCSS but are harder to integrate with the PCSS for a compact package. The US lasers, while easier to integrate with the switch, did not trigger the PCSS at the US laser power levels we used. The PCSS was used to activate the Q-switch of the compact laser to be used in the X-1 Advanced Radiation Source.

  8. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    PubMed

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  9. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    PubMed

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

  10. An FPGA-based High Speed Parallel Signal Processing System for Adaptive Optics Testbed

    NASA Astrophysics Data System (ADS)

    Kim, H.; Choi, Y.; Yang, Y.

    In this paper a state-of-the-art FPGA (Field Programmable Gate Array) based high speed parallel signal processing system (SPS) for adaptive optics (AO) testbed with 1 kHz wavefront error (WFE) correction frequency is reported. The AO system consists of Shack-Hartmann sensor (SHS) and deformable mirror (DM), tip-tilt sensor (TTS), tip-tilt mirror (TTM) and an FPGA-based high performance SPS to correct wavefront aberrations. The SHS is composed of 400 subapertures and the DM 277 actuators with Fried geometry, requiring high speed parallel computing capability SPS. In this study, the target WFE correction speed is 1 kHz; therefore, it requires massive parallel computing capabilities as well as strict hard real time constraints on measurements from sensors, matrix computation latency for correction algorithms, and output of control signals for actuators. In order to meet them, an FPGA based real-time SPS with parallel computing capabilities is proposed. In particular, the SPS is made up of a National Instrument's (NI's) real time computer and five FPGA boards based on state-of-the-art Xilinx Kintex 7 FPGA. Programming is done with NI's LabView environment, providing flexibility when applying different algorithms for WFE correction. It also facilitates faster programming and debugging environment as compared to conventional ones. One of the five FPGA's is assigned to measure TTS and calculate control signals for TTM, while the rest four are used to receive SHS signal, calculate slops for each subaperture and correction signal for DM. With this parallel processing capabilities of the SPS the overall closed-loop WFE correction speed of 1 kHz has been achieved. System requirements, architecture and implementation issues are described; furthermore, experimental results are also given.

  11. FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

    PubMed Central

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2016-01-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

  12. FPGA-Based Networked Phasemeter for a Heterodyne Interferometer

    NASA Technical Reports Server (NTRS)

    Rao, Shanti

    2009-01-01

    A document discusses a component of a laser metrology system designed to measure displacements along the line of sight with precision on the order of a tenth the diameter of an atom. This component, the phasemeter, measures the relative phase of two electrical signals and transfers that information to a computer. Because the metrology system measures the differences between two optical paths, the phasemeter has two inputs, called measure and reference. The reference signal is nominally a perfect square wave with a 50- percent duty cycle (though only rising edges are used). As the metrology system detects motion, the difference between the reference and measure signal phases is proportional to the displacement of the motion. The phasemeter, therefore, counts the elapsed time between rising edges in the two signals, and converts the time into an estimate of phase delay. The hardware consists of a circuit board that plugs into a COTS (commercial, off-the- shelf) Spartan-III FPGA (field-programmable gate array) evaluation board. It has two BNC inputs, (reference and measure), a CMOS logic chip to buffer the inputs, and an Ethernet jack for transmitting reduced-data to a PC. Two extra BNC connectors can be attached for future expandability, such as external synchronization. Each phasemeter handles one metrology channel. A bank of six phasemeters (and two zero-crossing detector cards) with an Ethernet switch can monitor the rigid body motion of an object. This device is smaller and cheaper than existing zero-crossing phasemeters. Also, because it uses Ethernet for communication with a computer, instead of a VME bridge, it is much easier to use. The phasemeter is a key part of the Precision Deployable Apertures and Structures strategic R&D effort to design large, deployable, segmented space telescopes.

  13. STAR: FPGA-based software defined satellite transponder

    NASA Astrophysics Data System (ADS)

    Davalle, Daniele; Cassettari, Riccardo; Saponara, Sergio; Fanucci, Luca; Cucchi, Luca; Bigongiari, Franco; Errico, Walter

    2013-05-01

    This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

  14. Parallel fixed point implementation of a radial basis function network in an FPGA.

    PubMed

    de Souza, Alisson C D; Fernandes, Marcelo A C

    2014-01-01

    This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.

  15. FPGA based digital signal processing for high resolution low energy gamma spectrometery

    NASA Astrophysics Data System (ADS)

    Arriojas, A.; Barros, H.; Walter, J.; Sajó-Bohus, L.

    2014-07-01

    A prototype board based on FPGA for data acquisition in Nuclear Spectrometry is given as part of a continuing project. The FPGA based system, perform functions such as dead-time control, detection and management of stacked pulses during acquisition and the storage of spectra. This device allows viewing digital signals and accurate measurement of the pulse high (energy). The graphical interface for the control of the acquisition card is a LabVIEW virtual instrument. Spectral results were compared with spectra produced by a commercially available spectrometer and indicate that further improvement in energy resolution is needed.

  16. 10 Gbps TCP/IP streams from the FPGA for the CMS DAQ eventbuilder network

    NASA Astrophysics Data System (ADS)

    Bauer, G.; Bawej, T.; Behrens, U.; Branson, J.; Chaze, O.; Cittolin, S.; Coarasa, J. A.; Darlea, G.-L.; Deldicque, C.; Dobson, M.; Dupont, A.; Erhan, S.; Gigi, D.; Glege, F.; Gomez-Ceballos, G.; Gomez-Reino, R.; Hartl, C.; Hegeman, J.; Holzner, A.; Masetti, L.; Meijers, F.; Meschi, E.; Mommsen, R. K.; Morovic, S.; Nunez-Barranco-Fernandez, C.; O'Dell, V.; Orsini, L.; Ozga, W.; Paus, C.; Petrucci, A.; Pieri, M.; Racz, A.; Raginel, O.; Sakulin, H.; Sani, M.; Schwick, C.; Spataru, A. C.; Stieger, B.; Sumorok, K.; Veverka, J.; Wakefield, C. C.; Zejdl, P.

    2013-12-01

    For the upgrade of the DAQ of the CMS experiment in 2013/2014 an interface between the custom detector Front End Drivers (FEDs) and the new DAQ eventbuilder network has to be designed. For a loss-less data collection from more then 600 FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. We present the hardware challenges and protocol modifications made to TCP in order to simplify its FPGA implementation together with a set of performance measurements which were carried out with the current prototype.

  17. Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA

    PubMed Central

    de Souza, Alisson C. D.; Fernandes, Marcelo A. C.

    2014-01-01

    This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA. PMID:25268918

  18. Earthquake triggering by transient and static deformations

    USGS Publications Warehouse

    Gomberg, J.; Beeler, N.M.; Blanpied, M.L.; Bodin, P.

    1998-01-01

    at the initiation of failure, whereas static loads that are applied sufficiently late raise it. Rate-and-state friction predictions differ markedly from those based on Coulomb failure stress changes (??CFS) in which ??t equals the amplitude of the static stress change divided by the background stressing rate. The ??CFS model assumes a stress failure threshold, while the rate-and-state equations require a slip failure threshold. The complete rale-and-state equations predict larger ??t than the ??CFS model does for static stress steps at small t0, and smaller ??t than the ??CFS model for stress steps at large t0. The ??CFS model predicts nonzero ??t only for transient loads that raise the stress to failure stress levels during the transient. In contrast, the rate-and-state model predicts nonzero ??t for smaller loads, and triggered failure may occur well after the transient is finished. We consider heuristically the effects of triggering on a population of faults, as these effects might be evident in seismicity data. Triggering is manifest as an initial increase in seismicity rate that may be followed by a quiescence or by a return to the background rate. Available seismicity data are insufficient to discriminate whether triggered earthquakes are "new" or clock advanced. However, if triggering indeed results from advancing the failure time of inevitable earthquakes, then our modeling suggests that a quiescence always follows transient triggering and that the duration of increased seismicity also cannot exceed the duration of a triggering transient load. Quiescence follows static triggering only if the population of available faults is finite.

  19. Triggering requirements for SSC physics

    SciTech Connect

    Gilchriese, M.G.D.

    1989-04-01

    Some aspects of triggering requirements for high P{sub T} physics processes at the Superconducting Super Collider (SSC) are described. A very wide range of trigger types will be required to enable detection of the large number of potential physics signatures possible at the SSC. Although in many cases trigger rates are not now well understood, it is possible to conclude that the ability to trigger on transverse energy, number and energy of jets, number and energy of leptons (electrons and muons), missing energy and combinations of these will be required. An SSC trigger system must be both highly flexible and redundant to ensure reliable detection of many new physics processes at the SSC.

  20. The BTeV trigger architecture

    SciTech Connect

    Michael H.L.S. Wang

    2003-08-21

    BTeV is a high-statistics B-physics experiment that will achieve new levels of sensitivity in testing the Standard Model explanation of CP violation, mixing, and rare decays in the b and c quark systems by operating in the unique environment of a hadron collider. In order to achieve its goals, it will make use of a state-of-the-art Si-pixel vertex detector and a novel 3-level hierarchical trigger that will look at every single beam crossing to detect the presence of heavy quark decays. This talk will describe the trigger architecture focusing on key design aspects that allow the use of commercially available technology in a highly feasible and practical solution that meets the demanding physics requirements of the BTeV experiment.

  1. Proceedings of the workshop on triggering and data acquisition for experiments at the Supercollider

    SciTech Connect

    Donaldson, R.

    1989-04-01

    This meeting covered the following subjects: triggering requirements for SSC physics; CDF level 3 trigger; D0 trigger design; AMY trigger systems; Zeus calorimeter first level trigger; data acquisition for the Zeus Central Tracking Detector; trigger and data acquisition aspects for SSC tracking; data acquisition systems for the SSC; validating triggers in CDF level 3; optical data transmission at SSC; time measurement system at SSC; SSC/BCD data acquisition system; microprocessors and other processors for triggering and filtering at the SSC; data acquisition, event building, and on-line processing; LAA real-time benchmarks; object-oriented system building at SSC; and software and project management. Selected papers are indexed separately for inclusion in the Energy Science and Technology Database.

  2. Disaster triggers disaster: Earthquake triggering by tropical cyclones

    NASA Astrophysics Data System (ADS)

    Wdowinski, S.; Tsukanov, I.

    2011-12-01

    Three recent devastating earthquakes, the 1999 M=7.6 Chi-Chi (Taiwan), 2010 M=7.0 Leogane (Haiti), 2010 M=6.4 Kaohsiung (Taiwan), and additional three moderate size earthquakes (6level and frequent typhoon landfall. The three wettest typhoons in Taiwan's past 50 years were Morakot (in 2009, with 2885 mm or rain), Flossie (1969, 2162 mm) and Herb (1996, 1987 mm)[Lin et al., 2010]. Each of this three very wet storms was followed by one or two main-shock M>6 earthquake that occurred in the central mountainous area of Taiwan within three years after the typhoon. The 2009 Morakot typhoon was followed by 2009 M=6.2 Nantou and 2010 M=6.4 Kaohsiung earthquakes; the 1969 Flossie typhoon was followed by an M=6.3 earthquake in 1972; and the 1996 Herb typhoon by the 1998 M=6.2 Rueyli and 1999 M=7.6 Chi-Chi earthquakes. The earthquake catalog of Taiwan lists only two other M>6 main-shocks that occurred in Taiwan's central mountainous belt, one of them was in 1964 only four months after the wet Typhoon Gloria poured heavy rain in the same area. We suggest that the close proximity in time and space between wet tropical cyclones and earthquakes reflects a physical link between the two hazard types in which these earthquakes were triggered by rapid erosion induced by tropical cyclone's heavy rain. Based on remote sensing observations, meshfree finite element modeling, and Coulomb failure stress analysis, we show that the

  3. Seismology: dynamic triggering of earthquakes.

    PubMed

    Gomberg, Joan; Johnson, Paul

    2005-10-01

    After an earthquake, numerous smaller shocks are triggered over distances comparable to the dimensions of the mainshock fault rupture, although they are rare at larger distances. Here we analyse the scaling of dynamic deformations (the stresses and strains associated with seismic waves) with distance from, and magnitude of, their triggering earthquake, and show that they can cause further earthquakes at any distance if their amplitude exceeds several microstrain, regardless of their frequency content. These triggering requirements are remarkably similar to those measured in the laboratory for inducing dynamic elastic nonlinear behaviour, which suggests that the underlying physics is similar.

  4. Pulsed thyristor trigger control circuit

    NASA Technical Reports Server (NTRS)

    Nola, F. J. (Inventor)

    1984-01-01

    A trigger control circuit is provided for producing firing pulses for the thyristor of a thyristor control system such as a power factor controller. The control circuit overcomes thyristor triggering problems involved with the current lag associated with controlling inductive loads and utilizes a phase difference signal, already present in the power factor controller, in deriving a signal for inhibiting generation of a firing pulse until no load current is flowing from the preceding half cycle and thereby ensuring that the thyristor is triggered on during each half cycle.

  5. Triggered Release from Polymer Capsules

    SciTech Connect

    Esser-Kahn, Aaron P.; Odom, Susan A.; Sottos, Nancy R.; White, Scott R.; Moore, Jeffrey S.

    2011-07-06

    Stimuli-responsive capsules are of interest in drug delivery, fragrance release, food preservation, and self-healing materials. Many methods are used to trigger the release of encapsulated contents. Here we highlight mechanisms for the controlled release of encapsulated cargo that utilize chemical reactions occurring in solid polymeric shell walls. Triggering mechanisms responsible for covalent bond cleavage that result in the release of capsule contents include chemical, biological, light, thermal, magnetic, and electrical stimuli. We present methods for encapsulation and release, triggering methods, and mechanisms and conclude with our opinions on interesting obstacles for chemically induced activation with relevance for controlled release.

  6. FPGA Implementation of Stereo Disparity with High Throughput for Mobility Applications

    NASA Technical Reports Server (NTRS)

    Villalpando, Carlos Y.; Morfopolous, Arin; Matthies, Larry; Goldberg, Steven

    2011-01-01

    High speed stereo vision can allow unmanned robotic systems to navigate safely in unstructured terrain, but the computational cost can exceed the capacity of typical embedded CPUs. In this paper, we describe an end-to-end stereo computation co-processing system optimized for fast throughput that has been implemented on a single Virtex 4 LX160 FPGA. This system is capable of operating on images from a 1024 x 768 3CCD (true RGB) camera pair at 15 Hz. Data enters the FPGA directly from the cameras via Camera Link and is rectified, pre-filtered and converted into a disparity image all within the FPGA, incurring no CPU load. Once complete, a rectified image and the final disparity image are read out over the PCI bus, for a bandwidth cost of 68 MB/sec. Within the FPGA there are 4 distinct algorithms: Camera Link capture, Bilinear rectification, Bilateral subtraction pre-filtering and the Sum of Absolute Difference (SAD) disparity. Each module will be described in brief along with the data flow and control logic for the system. The system has been successfully fielded upon the Carnegie Mellon University's National Robotics Engineering Center (NREC) Crusher system during extensive field trials in 2007 and 2008 and is being implemented for other surface mobility systems at JPL.

  7. A method of image multi-resolution processing based on FPGA + DSP architecture

    NASA Astrophysics Data System (ADS)

    Peng, Xiaohan; Zhong, Sheng; Lu, Hongqiang

    2015-10-01

    In real-time image processing, with the improvement of resolution and frame rate of camera imaging, not only the requirement of processing capacity is improving, but also the requirement of the optimization of process is improving. With regards to the FPGA + DSP architecture image processing system, there are three common methods to overcome the challenge above. The first is using higher performance DSP. For example, DSP with higher core frequency or with more cores can be used. The second is optimizing the processing method, make the algorithm to accomplish the same processing results but spend less time. Last but not least, pre-processing in the FPGA can make the image processing more efficient. A method of multi-resolution pre-processing by FPGA based on FPGA + DSP architecture is proposed here. It takes advantage of built-in first in first out (FIFO) and external synchronous dynamic random access memory (SDRAM) to buffer the images which come from image detector, and provides down-sampled images or cut-down images for DSP flexibly and efficiently according to the request parameters sent by DSP. DSP can thus get the degraded image instead of the whole image to process, shortening the processing time and transmission time greatly. The method results in alleviating the burden of image processing of DSP and also solving the problem of single method of image resolution reduction cannot meet the requirements of image processing task of DSP.

  8. FPGA Based High Speed Data Acquisition System for Electrical Impedance Tomography.

    PubMed

    Khan, S; Borsic, A; Manwaring, Preston; Hartov, Alexander; Halter, Ryan

    2013-03-01

    Electrical Impedance Tomography (EIT) systems are used to image tissue bio-impedance. EIT provides a number of features making it attractive for use as a medical imaging device including the ability to image fast physiological processes (>60 Hz), to meet a range of clinical imaging needs through varying electrode geometries and configurations, to impart only non-ionizing radiation to a patient, and to map the significant electrical property contrasts present between numerous benign and pathological tissues. To leverage these potential advantages for medical imaging, we developed a modular 32 channel data acquisition (DAQ) system using National Instruments' PXI chassis, along with FPGA, ADC, Signal Generator and Timing and Synchronization modules. To achieve high frame rates, signal demodulation and spectral characteristics of higher order harmonics were computed using dedicated FFT-hardware built into the FPGA module. By offloading the computing onto FPGA, we were able to achieve a reduction in throughput required between the FPGA and PC by a factor of 32:1. A custom designed analog front end (AFE) was used to interface electrodes with our system. Our system is wideband, and capable of acquiring data for input signal frequencies ranging from 100 Hz to 12 MHz. The modular design of both the hardware and software will allow this system to be flexibly configured for the particular clinical application.

  9. FPGA Based High Speed Data Acquisition System for Electrical Impedance Tomography

    NASA Astrophysics Data System (ADS)

    Khan, S.; Borsic, A.; Manwaring, Preston; Hartov, Alexander; Halter, Ryan

    2013-04-01

    Electrical Impedance Tomography (EIT) systems are used to image tissue bio-impedance. EIT provides a number of features making it attractive for use as a medical imaging device including the ability to image fast physiological processes (>60 Hz), to meet a range of clinical imaging needs through varying electrode geometries and configurations, to impart only non-ionizing radiation to a patient, and to map the significant electrical property contrasts present between numerous benign and pathological tissues. To leverage these potential advantages for medical imaging, we developed a modular 32 channel data acquisition (DAQ) system using National Instruments' PXI chassis, along with FPGA, ADC, Signal Generator and Timing and Synchronization modules. To achieve high frame rates, signal demodulation and spectral characteristics of higher order harmonics were computed using dedicated FFT-hardware built into the FPGA module. By offloading the computing onto FPGA, we were able to achieve a reduction in throughput required between the FPGA and PC by a factor of 32:1. A custom designed analog front end (AFE) was used to interface electrodes with our system. Our system is wideband, and capable of acquiring data for input signal frequencies ranging from 100 Hz to 12 MHz. The modular design of both the hardware and software will allow this system to be flexibly configured for the particular clinical application.

  10. FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery.

    PubMed

    Haselman, M D; Pasko, J; Hauck, S; Lewellen, T K; Miyaoka, R S

    2012-10-01

    Modern field programmable gate arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz. This, combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilized to add significant signal processing power to produce higher quality images. In this paper we report on an all-digital pulse pile-up correction algorithm that has been developed for the FPGA. The pile-up mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pile-up events. Using pulses acquired from a Zecotech Photonics MAPD-N with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pile-up utilizing a moderate amount of FPGA resources. PMID:24265508

  11. Remote monitoring and fault recovery for FPGA-based field controllers of telescope and instruments

    NASA Astrophysics Data System (ADS)

    Zhu, Yuhua; Zhu, Dan; Wang, Jianing

    2012-09-01

    As the increasing size and more and more functions, modern telescopes have widely used the control architecture, i.e. central control unit plus field controller. FPGA-based field controller has the advantages of field programmable, which provide a great convenience for modifying software and hardware of control system. It also gives a good platform for implementation of the new control scheme. Because of multi-controlled nodes and poor working environment in scattered locations, reliability and stability of the field controller should be fully concerned. This paper mainly describes how we use the FPGA-based field controller and Ethernet remote to construct monitoring system with multi-nodes. When failure appearing, the new FPGA chip does self-recovery first in accordance with prerecovery strategies. In case of accident, remote reconstruction for the field controller can be done through network intervention if the chip is not being restored. This paper also introduces the network remote reconstruction solutions of controller, the system structure and transport protocol as well as the implementation methods. The idea of hardware and software design is given based on the FPGA. After actual operation on the large telescopes, desired results have been achieved. The improvement increases system reliability and reduces workload of maintenance, showing good application and popularization.

  12. A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

    SciTech Connect

    Quinn, Heather M; Graham, Paul S; Morgan, Keith S; Caffrey, Michael P

    2008-01-01

    Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

  13. FPGA implementation of a biological neural network based on the Hodgkin-Huxley neuron model.

    PubMed

    Yaghini Bonabi, Safa; Asgharian, Hassan; Safari, Saeed; Nili Ahmadabadi, Majid

    2014-01-01

    A set of techniques for efficient implementation of Hodgkin-Huxley-based (H-H) model of a neural network on FPGA (Field Programmable Gate Array) is presented. The central implementation challenge is H-H model complexity that puts limits on the network size and on the execution speed. However, basics of the original model cannot be compromised when effect of synaptic specifications on the network behavior is the subject of study. To solve the problem, we used computational techniques such as CORDIC (Coordinate Rotation Digital Computer) algorithm and step-by-step integration in the implementation of arithmetic circuits. In addition, we employed different techniques such as sharing resources to preserve the details of model as well as increasing the network size in addition to keeping the network execution speed close to real time while having high precision. Implementation of a two mini-columns network with 120/30 excitatory/inhibitory neurons is provided to investigate the characteristic of our method in practice. The implementation techniques provide an opportunity to construct large FPGA-based network models to investigate the effect of different neurophysiological mechanisms, like voltage-gated channels and synaptic activities, on the behavior of a neural network in an appropriate execution time. Additional to inherent properties of FPGA, like parallelism and re-configurability, our approach makes the FPGA-based system a proper candidate for study on neural control of cognitive robots and systems as well.

  14. The P0 feedback control system blurs the line between IOC and FPGA.

    SciTech Connect

    DiMonte, N.; APS Engineering Support Division

    2008-01-01

    The P0 Feedback system is a new design at the Advanced Photon Source (APS) primarily intended to stabilize a single bunch in order to operate at a higher accumulated charge. The algorithm for this project required a high-speed DSP solution for a single channel that would make adjustments on a turn-by-turn basis. A field programmable gate array (FPGA) solution was selected that not only met the requirements of the project but far exceeded them. By using a single FPGA, we were able to adjust up to 324 bunches on two separate channels with a total computational time of {approx} 6 x 10{sup 9} multiply- accumulate operations per second. The IOC is a Coldfire CPU tightly coupled to the FPGA, providing dedicated control and monitoring of the system through EPICS [1] process variables. One of the benefits of this configuration is having a four-channel scope in the FPGA that can be monitored on a continuous basis.

  15. DESIGN AND ANALYSIS OF AN FPGA-BASED ACTIVE FEEDBACK DAMPING SYSTEM

    SciTech Connect

    Xie, Zaipeng; Schulte, Mike; Deibele, Craig Edmond

    2010-01-01

    The Spallation Neutron Source (SNS) at the Oak Ridge National Laboratory is a high-intensity proton-based accelerator that produces neutron beams for neutronscattering research. As the most powerful pulsed neutron source in the world, the SNS accelerator has experienced an unprecedented beam instability that has a wide bandwidth (0 to 300MHz) and fast growth time (10 to100 s). In this paper, we propose and analyze several FPGA-based designs for an active feedback damping system. This signal processing system is the first FPGA-based design for active feedback damping of wideband instabilities in high intensity accelerators. It can effectively mitigate instabilities in highintensity protons beams, reduce radiation, and boost the accelerator s luminosity performance. Unlike existing systems, which are designed using analog components, our FPGA-based active feedback damping system offers programmability while maintaining high performance. To meet the system throughput and latency requirements, our proposed designs are guided by detailed analysis of resource and performance tradeoffs. These designs are mapped onto a reconfigurable platform that includes Xilinx Virtex-II Pro FPGAs and high-speed analog-to-digital and digital-toanalog converters. Our results show that our FPGA-based active feedback damping system can provide increased flexibility and improved signal processing performance that are not feasible with existing analog systems.

  16. A single FPGA-based portable ultrasound imaging system for point-of-care applications.

    PubMed

    Kim, Gi-Duck; Yoon, Changhan; Kye, Sang-Bum; Lee, Youngbae; Kang, Jeeun; Yoo, Yangmo; Song, Tai-kyong

    2012-07-01

    We present a cost-effective portable ultrasound system based on a single field-programmable gate array (FPGA) for point-of-care applications. In the portable ultrasound system developed, all the ultrasound signal and image processing modules, including an effective 32-channel receive beamformer with pseudo-dynamic focusing, are embedded in an FPGA chip. For overall system control, a mobile processor running Linux at 667 MHz is used. The scan-converted ultrasound image data from the FPGA are directly transferred to the system controller via external direct memory access without a video processing unit. The potable ultrasound system developed can provide real-time B-mode imaging with a maximum frame rate of 30, and it has a battery life of approximately 1.5 h. These results indicate that the single FPGA-based portable ultrasound system developed is able to meet the processing requirements in medical ultrasound imaging while providing improved flexibility for adapting to emerging POC applications.

  17. Fine-grained parallelism accelerating for RNA secondary structure prediction with pseudoknots based on FPGA.

    PubMed

    Xia, Fei; Jin, Guoqing

    2014-06-01

    PKNOTS is a most famous benchmark program and has been widely used to predict RNA secondary structure including pseudoknots. It adopts the standard four-dimensional (4D) dynamic programming (DP) method and is the basis of many variants and improved algorithms. Unfortunately, the O(N(6)) computing requirements and complicated data dependency greatly limits the usefulness of PKNOTS package with the explosion in gene database size. In this paper, we present a fine-grained parallel PKNOTS package and prototype system for accelerating RNA folding application based on FPGA chip. We adopted a series of storage optimization strategies to resolve the "Memory Wall" problem. We aggressively exploit parallel computing strategies to improve computational efficiency. We also propose several methods that collectively reduce the storage requirements for FPGA on-chip memory. To the best of our knowledge, our design is the first FPGA implementation for accelerating 4D DP problem for RNA folding application including pseudoknots. The experimental results show a factor of more than 50x average speedup over the PKNOTS-1.08 software running on a PC platform with Intel Core2 Q9400 Quad CPU for input RNA sequences. However, the power consumption of our FPGA accelerator is only about 50% of the general-purpose micro-processors.

  18. FPGA-Based Pulse Pile-Up Correction With Energy and Timing Recovery.

    PubMed

    Haselman, M D; Pasko, J; Hauck, S; Lewellen, T K; Miyaoka, R S

    2012-10-01

    Modern field programmable gate arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates well above 100 MHz. This, combined with FPGA's low expense, ease of use, and selected dedicated hardware make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a high-resolution, small-animal PET scanner that utilizes FPGAs as the core of the front-end electronics. For this scanner, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilized to add significant signal processing power to produce higher quality images. In this paper we report on an all-digital pulse pile-up correction algorithm that has been developed for the FPGA. The pile-up mitigation algorithm will allow the scanner to run at higher count rates without incurring large data losses due to the overlapping of scintillation signals. This correction technique utilizes a reference pulse to extract timing and energy information for most pile-up events. Using pulses acquired from a Zecotech Photonics MAPD-N with an LFS-3 scintillator, we show that good timing and energy information can be achieved in the presence of pile-up utilizing a moderate amount of FPGA resources.

  19. A novel FPGA-based bunch purity monitor system at the APS storage ring.

    SciTech Connect

    Norum, W. E.; APS Engineering Support Division

    2008-01-01

    Bunch purity is an important source quality factor for the magnetic resonance experiments at the Advanced Photon Source. Conventional bunch-purity monitors utilizing time-to-amplitude converters are subject to dead time. We present a novel design based on a single field- programmable gate array (FPGA) that continuously processes pulses at the full speed of the detector and front-end electronics. The FPGA provides 7778 single-channel analyzers (six per rf bucket). The starting time and width of each single-channel analyzer window can be set to a resolution of 178 ps. A detector pulse arriving inside the window of a single-channel analyzer is recorded in an associated 32-bit counter. The analyzer makes no contribution to the system dead time. Two channels for each rf bucket count pulses originating from the electrons in the bucket. The other four channels on the early and late side of the bucket provide estimates of the background. A single-chip microcontroller attached to the FPGA acts as an EPICS IOC to make the information in the FPGA available to the EPICS clients.

  20. FPGA Based High Speed Data Acquisition System for Electrical Impedance Tomography

    PubMed Central

    Khan, S; Borsic, A; Manwaring, Preston; Hartov, Alexander; Halter, Ryan

    2014-01-01

    Electrical Impedance Tomography (EIT) systems are used to image tissue bio-impedance. EIT provides a number of features making it attractive for use as a medical imaging device including the ability to image fast physiological processes (>60 Hz), to meet a range of clinical imaging needs through varying electrode geometries and configurations, to impart only non-ionizing radiation to a patient, and to map the significant electrical property contrasts present between numerous benign and pathological tissues. To leverage these potential advantages for medical imaging, we developed a modular 32 channel data acquisition (DAQ) system using National Instruments’ PXI chassis, along with FPGA, ADC, Signal Generator and Timing and Synchronization modules. To achieve high frame rates, signal demodulation and spectral characteristics of higher order harmonics were computed using dedicated FFT-hardware built into the FPGA module. By offloading the computing onto FPGA, we were able to achieve a reduction in throughput required between the FPGA and PC by a factor of 32:1. A custom designed analog front end (AFE) was used to interface electrodes with our system. Our system is wideband, and capable of acquiring data for input signal frequencies ranging from 100 Hz to 12 MHz. The modular design of both the hardware and software will allow this system to be flexibly configured for the particular clinical application. PMID:24729790

  1. Finger Tendon Travel Associated with Sequential Trigger Nail Gun Use

    PubMed Central

    Lowe, Brian; Albers, James; Hudock, Stephen; Krieg, Edward

    2015-01-01

    TECHNICAL ABSTRACT Background Pneumatic nail guns used in wood framing are equipped with one of two triggering mechanisms. Sequential actuation triggers have been shown to be a safer alternative to contact actuation triggers because they reduce traumatic injury risk. However, the sequential actuation trigger must be depressed for each individual nail fired as opposed to the contact actuation trigger, which allows the trigger to be held depressed as nails are fired repeatedly by bumping the safety tip against the workpiece. As such, concerns have been raised about risks for cumulative trauma injury, and reduced productivity, due to repetitive finger motion with the sequential actuation trigger. Purpose This study developed a method to predict cumulative finger flexor tendon travel associated with the sequential actuation trigger nail gun from finger joint kinematics measured in the trigger actuation and productivity standards for wood-frame construction tasks. Methods Finger motions were measured from six users wearing an instrumented electrogoniometer glove in a simulation of two common framing tasks–wall building and flat nailing of material. Flexor tendon travel was calculated from the ensemble average kinematics for an individual nail fired. Results Finger flexor tendon travel was attributable mostly to proximal interphalangeal and distal interphalangeal joint motion. Tendon travel per nail fired appeared to be slightly greater for a wall-building task than a flat nailing task. The present study data, in combination with construction industry productivity standards, suggest that a high-production workday would be associated with less than 60 m/day cumulative tendon travel per worker (based on 1700 trigger presses/day). Conclusion and Applications These results suggest that exposure to finger tendon travel from sequential actuation trigger nail gun use may be below levels that have been previously associated with high musculoskeletal disorder risk. PMID

  2. Missing Transverse Momentum Trigger Performance Studies for the ATLAS Calorimeter Trigger Upgrades

    NASA Astrophysics Data System (ADS)

    Stamas, Brianna; Parrish, Elliot; Lisi, Luc; Dudley, Christopher; Majewski, Stephanie

    2016-03-01

    The ATLAS Experiment is one of two general purpose detectors at the Large Hadron Collider at CERN in Geneva, Switzerland. In anticipation of discovering new physics, the detector will undergo numerous hardware upgrades including improvements to the Liquid Argon Calorimeter trigger electronics. For the upgrade, one component of the Level-1 trigger system will be the global feature extractor, gFEX, which will house three field programmable gate arrays (FPGAs). Specifically, in order to improve the missing transverse energy (ETmiss)trigger, an adapted topological clustering algorithm is being investigated for implementation on the FPGAs for reconstruction of proton-proton interactions in the ATLAS detector. Using simulated data, this study analyzes the performance of the adapted algorithm in software.

  3. FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

    PubMed

    Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

    2013-09-01

    In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

  4. FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

    PubMed

    Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

    2013-09-01

    In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results. PMID:24808576

  5. Multi-camera synchronization core implemented on USB3 based FPGA platform

    NASA Astrophysics Data System (ADS)

    Sousa, Ricardo M.; Wäny, Martin; Santos, Pedro; Dias, Morgado

    2015-03-01

    Centered on Awaiba's NanEye CMOS image sensor family and a FPGA platform with USB3 interface, the aim of this paper is to demonstrate a new technique to synchronize up to 8 individual self-timed cameras with minimal error. Small form factor self-timed camera modules of 1 mm x 1 mm or smaller do not normally allow external synchronization. However, for stereo vision or 3D reconstruction with multiple cameras as well as for applications requiring pulsed illumination it is required to synchronize multiple cameras. In this work, the challenge of synchronizing multiple selftimed cameras with only 4 wire interface has been solved by adaptively regulating the power supply for each of the cameras. To that effect, a control core was created to constantly monitor the operating frequency of each camera by measuring the line period in each frame based on a well-defined sampling signal. The frequency is adjusted by varying the voltage level applied to the sensor based on the error between the measured line period and the desired line period. To ensure phase synchronization between frames, a Master-Slave interface was implemented. A single camera is defined as the Master, with its operating frequency being controlled directly through a PC based interface. The remaining cameras are setup in Slave mode and are interfaced directly with the Master camera control module. This enables the remaining cameras to monitor its line and frame period and adjust their own to achieve phase and frequency synchronization. The result of this work will allow the implementation of smaller than 3mm diameter 3D stereo vision equipment in medical endoscopic context, such as endoscopic surgical robotic or micro invasive surgery.

  6. Performance evaluation of trigger algorithm for the MACE telescope

    NASA Astrophysics Data System (ADS)

    Yadav, Kuldeep; Yadav, K. K.; Bhatt, N.; Chouhan, N.; Sikder, S. S.; Behere, A.; Pithawa, C. K.; Tickoo, A. K.; Rannot, R. C.; Bhattacharyya, S.; Mitra, A. K.; Koul, R.

    The MACE (Major Atmospheric Cherenkov Experiment) telescope with a light collector diameter of 21 m, is being set up at Hanle (32.80 N, 78.90 E, 4200m asl) India, to explore the gamma-ray sky in the tens of GeV energy range. The imaging camera of the telescope comprises 1088 pixels covering a total field-of-view of 4.30 × 4.00 with trigger field-of-view of 2.60 × 3.00 and an uniform pixel resolution of 0.120. In order to achieve low energy trigger threshold of less than 30 GeV, a two level trigger scheme is being designed for the telescope. The first level trigger is generated within 16 pixels of the Camera Integrated Module (CIM) based on 4 nearest neighbour (4NN) close cluster configuration within a coincidence gate window of 5 ns while the second level trigger is generated by combining the first level triggers from neighbouring CIMs. Each pixel of the telescope is expected to operate at a single pixel threshold between 8-10 photo-electrons where the single channel rate dominated by the after- pulsing is expected to be ˜500 kHz. The hardware implementation of the trigger logic is based on complex programmable logic devices (CPLD). The basic design concept, hardware implementation and performance evaluation of the trigger system in terms of threshold energy and trigger rate estimates based on Monte Carlo data for the MACE telescope will be presented in this meeting.

  7. Evaluation of triggering functions in convective parameterization schemes using observations

    NASA Astrophysics Data System (ADS)

    Ettammal, S.; Zhang, G. J.

    2013-12-01

    Realistic simulation of different modes of atmospheric variability ranging from the diurnal cycle to inter-annual variability in global climate models (GCMs) depends crucially on the convection triggering criteria. In this study, using the data from constrained variational analysis by the Atmospheric System Research program for single column models (SCM), the performance of the commonly used convective triggering functions in GCMs is evaluated, based on the equitable threat score (ETS) value, a widely used forecast verification metric. From the ETS score, four consistently better performing triggering functions were identified. They are based on dilute dCAPE, parcel buoyancy at the lifting condensation level (Bechtold scheme), undilute dCAPE and dilute CAPE triggering functions. The key variables used to define these triggering functions were examined in detail. It was found that the skill score value of the dilute dCAPE triggering function does not show much variation among different data sets. Analysis of the composite fields and probability distributions of key variables of the triggering functions, based on the correct-prediction, over-prediction, under-prediction of convection and correct prediction of no convection cases for convection onset, brings to light some critical factors responsible for the performance of the trigger functions.

  8. Stimuli triggering violence in psychoses.

    PubMed

    Pontius, A A

    1981-01-01

    Various behavioral and neurophysiological models are suggested to objectify and quantify the defense of insanity and to assess dangerousness in someone who is being considered for release from custody. Two cases are presented that show a pattern of specific relationships between traumatic experiences in youth and a later trigger stimulus that releases homicidal action. Until a refined classification system and neurophysiological understanding of sudden aggression can be achieved, forensic psychiatrists should be aware of the psychotic trigger reaction within a clinical psychiatric model.

  9. A novel approach to Hough Transform for implementation in fast triggers

    NASA Astrophysics Data System (ADS)

    Pozzobon, Nicola; Montecassiano, Fabio; Zotto, Pierluigi

    2016-10-01

    Telescopes of position sensitive detectors are common layouts in charged particles tracking, and programmable logic devices, such as FPGAs, represent a viable choice for the real-time reconstruction of track segments in such detector arrays. A compact implementation of the Hough Transform for fast triggers in High Energy Physics, exploiting a parameter reduction method, is proposed, targeting the reduction of the needed storage or computing resources in current, or next future, state-of-the-art FPGA devices, while retaining high resolution over a wide range of track parameters. The proposed approach is compared to a Standard Hough Transform with particular emphasis on their application to muon detectors. In both cases, an original readout implementation is modeled.

  10. Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation.

    PubMed

    Zbrzeski, Adeline; Bornat, Yannick; Hillen, Brian; Siu, Ricardo; Abbas, James; Jung, Ranu; Renaud, Sylvie

    2016-01-01

    Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications.

  11. Connected Component Labeling algorithm for very complex and high-resolution images on an FPGA platform

    NASA Astrophysics Data System (ADS)

    Schwenk, Kurt; Huber, Felix

    2015-10-01

    Connected Component Labeling (CCL) is a basic algorithm in image processing and an essential step in nearly every application dealing with object detection. It groups together pixels belonging to the same connected component (e.g. object). Special architectures such as ASICs, FPGAs and GPUs were utilised for achieving high data throughput, primarily for video processing. In this article, the FPGA implementation of a CCL method is presented, which was specially designed to process high resolution images with complex structure at high speed, generating a label mask. In general, CCL is a dynamic task and therefore not well suited for parallelisation, which is needed to achieve high processing speed with an FPGA. Facing this issue, most of the FPGA CCL implementations are restricted to low or medium resolution images (≤ 2048 ∗ 2048 pixels) with lower complexity, where the fastest implementations do not create a label mask. Instead, they extract object features like size and position directly, which can be realized with high performance and perfectly suits the need for many video applications. Since these restrictions are incompatible with the requirements to label high resolution images with highly complex structures and the need for generating a label mask, a new approach was required. The CCL method presented in this work is based on a two-pass CCL algorithm, which was modified with respect to low memory consumption and suitability for an FPGA implementation. Nevertheless, since not all parts of CCL can be parallelised, a stop-and-go high-performance pipeline processing CCL module was designed. The algorithm, the performance and the hardware requirements of a prototype implementation are presented. Furthermore, a clock-accurate runtime analysis is shown, which illustrates the dependency between processing speed and image complexity in detail. Finally, the performance of the FPGA implementation is compared with that of a software implementation on modern embedded

  12. Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation.

    PubMed

    Zbrzeski, Adeline; Bornat, Yannick; Hillen, Brian; Siu, Ricardo; Abbas, James; Jung, Ranu; Renaud, Sylvie

    2016-01-01

    Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications. PMID:27378844

  13. Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation

    PubMed Central

    Zbrzeski, Adeline; Bornat, Yannick; Hillen, Brian; Siu, Ricardo; Abbas, James; Jung, Ranu; Renaud, Sylvie

    2016-01-01

    Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications. PMID:27378844

  14. High-definition video display based on the FPGA and THS8200

    NASA Astrophysics Data System (ADS)

    Qian, Jia; Sui, Xiubao

    2014-11-01

    This paper presents a high-definition video display solution based on the FPGA and THS8200. THS8200 is a video decoder chip launched by TI company, this chip has three 10-bit DAC channels which can capture video data in both 4:2:2 and 4:4:4 formats, and its data synchronization can be either through the dedicated synchronization signals HSYNC and VSYNC, or extracted from the embedded video stream synchronization information SAV / EAV code. In this paper, we will utilize the address and control signals generated by FPGA to access to the data-storage array, and then the FPGA generates the corresponding digital video signals YCbCr. These signals combined with the synchronization signals HSYNC and VSYNC that are also generated by the FPGA act as the input signals of THS8200. In order to meet the bandwidth requirements of the high-definition TV, we adopt video input in the 4:2:2 format over 2×10-bit interface. THS8200 is needed to be controlled by FPGA with I2C bus to set the internal registers, and as a result, it can generate the synchronous signal that is satisfied with the standard SMPTE and transfer the digital video signals YCbCr into analog video signals YPbPr. Hence, the composite analog output signals YPbPr are consist of image data signal and synchronous signal which are superimposed together inside the chip THS8200. The experimental research indicates that the method presented in this paper is a viable solution for high-definition video display, which conforms to the input requirements of the new high-definition display devices.

  15. Target-triggered three-way junction structure and polymerase/nicking enzyme synergetic isothermal quadratic DNA machine for highly specific, one-step, and rapid microRNA detection at attomolar level.

    PubMed

    Zhang, Qing; Chen, Feng; Xu, Feng; Zhao, Yongxi; Fan, Chunhai

    2014-08-19

    MicroRNAs (miRNAs) play important roles in many biological processes and are regarded as promising cancer biomarkers. Herein, a highly specific, one-step, and rapid miRNAs detection strategy with attomolar sensitivity has been developed on the basis of a target-triggered three-way junction (3-WJ) structure and polymerase/nicking enzyme synergetic isothermal quadratic DNA machine (ESQM). To this end, 3-WJ probes (primer and template) are designed to selectively recognize target miRNA and form the stable 3-WJ structure to trigger ESQM, resulting in a high quadratic amplified signal. A high specificity is demonstrated by the excellent discrimination of even single-base mismatched homologous sequences with mismatched bases in varied locations (close to the 3'-end, the 5'-end, and the middle). In addition, a low detection limit down to 2 amol was achieved within 30 min. This sensitivity is much higher than those of most linear amplification-based approaches and is even comparable to those of some exponential amplification-based methods. Furthermore, the applicability of this method in complex samples was demonstrated by the analysis of cancer cell small RNA extracts, results of which were in good agreement with those obtained by a commercial miRNA kit and previously published data. The miRNA with a 3' end modification (2'-O-methylation), such as plant miRNA, was also successfully detected, confirming the good universality of the proposed strategy. It is worthwhile to point out that several well-established methods using miRNA as primer for polymerization reaction are of relatively poor performance in the analysis of these modified miRNA. Therefore, these merits endow the developed strategy with powerful implications for biological research and an effective diagnostic assay. PMID:25072308

  16. Skier triggering of backcountry avalanches with skilled route selection

    NASA Astrophysics Data System (ADS)

    Sinickas, Alexandra; Haegeli, Pascal; Jamieson, Bruce

    2015-04-01

    Jamieson (2009) provided numerical estimates for the baseline probabilities of triggering an avalanche by a backcountry skier making fresh tracks without skilled route selection as a function of the North American avalanche danger scale (i.e., hazard levels Low, Moderate, Considerable, High and Extreme). Using the results of an expert survey, he showed that triggering probabilities while skiing directly up, down or across a trigger zone without skilled route selection increase roughly by a factor of 10 with each step of the North American avalanche danger scale (i.e. hazard level). The objective of the present study is to examine the effect of skilled route selection on the relationship between triggering probability and hazard level. To assess the effect of skilled route selection on triggering probability by hazard level, we analysed avalanche hazard assessments as well as reports of skiing activity and triggering of avalanches from 11 Canadian helicopter and snowcat operations during two winters (2012-13 and 2013-14). These reports were submitted to the daily information exchange among Canadian avalanche safety operations, and reflect professional decision-making and route selection practices of guides leading groups of skiers. We selected all skier-controlled or accidentally triggered avalanches with a destructive size greater than size 1 according to the Canadian avalanche size classification, triggered by any member of a guided group (guide or guest). These operations forecast the avalanche hazard daily for each of three elevation bands: alpine, treeline and below treeline. In contrast to the 2009 study, an exposure was defined as a group skiing within any one of the three elevation bands, and consequently within a hazard rating, for the day (~4,300 ratings over two winters). For example, a group that skied below treeline (rated Moderate) and treeline (rated Considerable) in one day, would receive one count for exposure to Moderate hazard, and one count for

  17. Single-Chip FPGA Azimuth Pre-Filter for SAR

    NASA Technical Reports Server (NTRS)

    Gudim, Mimi; Cheng, Tsan-Huei; Madsen, Soren; Johnson, Robert; Le, Charles T-C; Moghaddam, Mahta; Marina, Miguel

    2005-01-01

    A field-programmable gate array (FPGA) on a single lightweight, low-power integrated-circuit chip has been developed to implement an azimuth pre-filter (AzPF) for a synthetic-aperture radar (SAR) system. The AzPF is needed to enable more efficient use of data-transmission and data-processing resources: In broad terms, the AzPF reduces the volume of SAR data by effectively reducing the azimuth resolution, without loss of range resolution, during times when end users are willing to accept lower azimuth resolution as the price of rapid access to SAR imagery. The data-reduction factor is selectable at a decimation factor, M, of 2, 4, 8, 16, or 32 so that users can trade resolution against processing and transmission delays. In principle, azimuth filtering could be performed in the frequency domain by use of fast-Fourier-transform processors. However, in the AzPF, azimuth filtering is performed in the time domain by use of finite-impulse-response filters. The reason for choosing the time-domain approach over the frequency-domain approach is that the time-domain approach demands less memory and a lower memory-access rate. The AzPF operates on the raw digitized SAR data. The AzPF includes a digital in-phase/quadrature (I/Q) demodulator. In general, an I/Q demodulator effects a complex down-conversion of its input signal followed by low-pass filtering, which eliminates undesired sidebands. In the AzPF case, the I/Q demodulator takes offset video range echo data to the complex baseband domain, ensuring preservation of signal phase through the azimuth pre-filtering process. In general, in an SAR I/Q demodulator, the intermediate frequency (fI) is chosen to be a quarter of the range-sampling frequency and the pulse-repetition frequency (fPR) is chosen to be a multiple of fI. The AzPF also includes a polyphase spatial-domain pre-filter comprising four weighted integrate-and-dump filters with programmable decimation factors and overlapping phases. To prevent aliasing of signals

  18. Use of Commercial FPGA-Based Evaluation Boards for Single-Event Testing of DDR2 and DDR3 SDRAMs

    NASA Technical Reports Server (NTRS)

    Ladbury, R. L.; Berg, M. D.; Wilcox, E. P.; LaBel, K. A.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2013-01-01

    We investigate the use of commercial FPGA based evaluation boards for radiation testing DDR2 and DDR3 SDRAMs. We evaluate the resulting data quality and the tradeoffs involved in the use of these boards.

  19. Effectiveness of Internal vs. External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

    NASA Technical Reports Server (NTRS)

    Berg, Melanie; Poivey C.; Petrick, D.; Espinosa, D.; Lesea, Austin; LaBel, K. A.; Friendlich, M; Kim, H; Phan, A.

    2008-01-01

    We compare two scrubbing mitigation schemes for Xilinx FPGA devices. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Proton and Heavy Ion data are then presented and analyzed.

  20. L0 trigger unit prototype for BM@N setup

    NASA Astrophysics Data System (ADS)

    Batenkov, O. I.; Bogoslovski, D. N.; Rogov, V. Y.; Sergeev, S. V.; Yurevich, V. I.

    2016-09-01

    The BM@N facility is a fixed target experiment based on heavy ion beams of the Nuclotron-M accelerator. The aim of the BM@N is to study nucleus - nucleus collisions at energies up to 4.5 GeV per nucleon. A level 0 trigger processor unit (Trigger L0 unit, T0U) for the BM@N deuterons and carbon ions at Run'2015 has been developed. The T0U is used to generate a BM@N zero level trigger and a TOF detector precise start.T0U generates trigger signal based on beam line and target area detector signals. This module also provides both control and monitoring of the detector front-end electronics power supplies. This article presents a concept, characteristics and test results of the T0U module during the Run 2015.

  1. JASMONATE-TRIGGERED PLANT IMMUNITY

    PubMed Central

    Campos, Marcelo L.; Kang, Jin-Ho; Howe, Gregg A.

    2014-01-01

    The plant hormone jasmonate (JA) exerts direct control over the production of chemical defense compounds that confer resistance to a remarkable spectrum of plant-associated organisms, ranging from microbial pathogens to vertebrate herbivores. The underlying mechanism of JA-triggered immunity (JATI) can be conceptualized as a multi-stage signal transduction cascade involving: i) pattern recognition receptors (PRRs) that couple the perception of danger signals to rapid synthesis of bioactive JA; ii) an evolutionarily conserved JA signaling module that links fluctuating JA levels to changes in the abundance of transcriptional repressor proteins; and iii) activation (de-repression) of transcription factors that orchestrate the expression of myriad chemical and morphological defense traits. Multiple negative feedback loops act in concert to restrain the duration and amplitude of defense responses, presumably to mitigate potential fitness costs of JATI. The convergence of diverse plant- and non-plant-derived signals on the core JA module indicates that JATI is a general response to perceived danger. However, the modular structure of JATI may accommodate attacker-specific defense responses through evolutionary innovation of PRRs (inputs) and defense traits (outputs). The efficacy of JATI as a defense strategy is highlighted by its capacity to shape natural populations of plant attackers, as well as the propensity of plant-associated organisms to subvert or otherwise manipulate JA signaling. As both a cellular hub for integrating informational cues from the environment and a common target of pathogen effectors, the core JA module provides a focal point for understanding immune system networks and the evolution of chemical diversity in the plant kingdom. PMID:24973116

  2. Anthropogenic triggering of large earthquakes.

    PubMed

    Mulargia, Francesco; Bizzarri, Andrea

    2014-01-01

    The physical mechanism of the anthropogenic triggering of large earthquakes on active faults is studied on the basis of experimental phenomenology, i.e., that earthquakes occur on active tectonic faults, that crustal stress values are those measured in situ and, on active faults, comply to the values of the stress drop measured for real earthquakes, that the static friction coefficients are those inferred on faults, and that the effective triggering stresses are those inferred for real earthquakes. Deriving the conditions for earthquake nucleation as a time-dependent solution of the Tresca-Von Mises criterion applied in the framework of poroelasticity yields that active faults can be triggered by fluid overpressures < 0.1 MPa. Comparing this with the deviatoric stresses at the depth of crustal hypocenters, which are of the order of 1-10 MPa, we find that injecting in the subsoil fluids at the pressures typical of oil and gas production and storage may trigger destructive earthquakes on active faults at a few tens of kilometers. Fluid pressure propagates as slow stress waves along geometric paths operating in a drained condition and can advance the natural occurrence of earthquakes by a substantial amount of time. Furthermore, it is illusory to control earthquake triggering by close monitoring of minor "foreshocks", since the induction may occur with a delay up to several years.

  3. Anthropogenic triggering of large earthquakes.

    PubMed

    Mulargia, Francesco; Bizzarri, Andrea

    2014-01-01

    The physical mechanism of the anthropogenic triggering of large earthquakes on active faults is studied on the basis of experimental phenomenology, i.e., that earthquakes occur on active tectonic faults, that crustal stress values are those measured in situ and, on active faults, comply to the values of the stress drop measured for real earthquakes, that the static friction coefficients are those inferred on faults, and that the effective triggering stresses are those inferred for real earthquakes. Deriving the conditions for earthquake nucleation as a time-dependent solution of the Tresca-Von Mises criterion applied in the framework of poroelasticity yields that active faults can be triggered by fluid overpressures < 0.1 MPa. Comparing this with the deviatoric stresses at the depth of crustal hypocenters, which are of the order of 1-10 MPa, we find that injecting in the subsoil fluids at the pressures typical of oil and gas production and storage may trigger destructive earthquakes on active faults at a few tens of kilometers. Fluid pressure propagates as slow stress waves along geometric paths operating in a drained condition and can advance the natural occurrence of earthquakes by a substantial amount of time. Furthermore, it is illusory to control earthquake triggering by close monitoring of minor "foreshocks", since the induction may occur with a delay up to several years. PMID:25156190

  4. Anthropogenic Triggering of Large Earthquakes

    PubMed Central

    Mulargia, Francesco; Bizzarri, Andrea

    2014-01-01

    The physical mechanism of the anthropogenic triggering of large earthquakes on active faults is studied on the basis of experimental phenomenology, i.e., that earthquakes occur on active tectonic faults, that crustal stress values are those measured in situ and, on active faults, comply to the values of the stress drop measured for real earthquakes, that the static friction coefficients are those inferred on faults, and that the effective triggering stresses are those inferred for real earthquakes. Deriving the conditions for earthquake nucleation as a time-dependent solution of the Tresca-Von Mises criterion applied in the framework of poroelasticity yields that active faults can be triggered by fluid overpressures < 0.1 MPa. Comparing this with the deviatoric stresses at the depth of crustal hypocenters, which are of the order of 1–10 MPa, we find that injecting in the subsoil fluids at the pressures typical of oil and gas production and storage may trigger destructive earthquakes on active faults at a few tens of kilometers. Fluid pressure propagates as slow stress waves along geometric paths operating in a drained condition and can advance the natural occurrence of earthquakes by a substantial amount of time. Furthermore, it is illusory to control earthquake triggering by close monitoring of minor “foreshocks”, since the induction may occur with a delay up to several years. PMID:25156190

  5. ENSO-triggered floods in South America

    NASA Astrophysics Data System (ADS)

    Isla, Federico Ignacio

    2016-04-01

    ENSO-triggered floods altered completely the annual discharge of most watersheds of South America. Anomalous years as 1941, 1982-83 and 1997-98 signified enormous discharges of rivers draining toward the Pacific but also to the Atlantic Ocean. These floods affected large cities as Porto Alegre, Blumenau, Curitiba, Asunción, Santa Fe and Buenos Aires. Maximum discharge months are particular and easily distinguished at those watersheds located at the South American Arid Diagonal. At watersheds conditioned by precipitations delivered from the Atlantic or Pacific anticyclonic centers the ENSO-triggered floods are difficult to discern. The floods of 1941 affected 70,000 inhabitants in Porto Alegre. In 1983, Blumenau city was flooded during several days; and the Paraná River multiplied 15 times the width of its middle floodplain. The Colorado River in Northern Patagonia connected for the last time to the Desaguadero-Chadileuvú-Curacó system and therefore received saline water. ENSO years modify also the water balance of certain piedmont lakes of Southern Patagonia: the increases in snow accumulations cause high water levels with a lag of 13 months. The correlation between the maximum monthly discharges of 1982-83 and 1997-98 at different regions and watersheds indicates they can be forecasted for future floods triggered by same phenomena. South American rivers can be classified therefore into ENSO-affected, and ENSO-dominated, for those within the Arid Diagonal that are exclusively subject to high discharges during these years.

  6. ATP-triggered anticancer drug delivery

    NASA Astrophysics Data System (ADS)

    Mo, Ran; Jiang, Tianyue; Disanto, Rocco; Tai, Wanyi; Gu, Zhen

    2014-03-01

    Stimuli-triggered drug delivery systems have been increasingly used to promote physiological specificity and on-demand therapeutic efficacy of anticancer drugs. Here we utilize adenosine-5'-triphosphate (ATP) as a trigger for the controlled release of anticancer drugs. We demonstrate that polymeric nanocarriers functionalized with an ATP-binding aptamer-incorporated DNA motif can selectively release the intercalating doxorubicin via a conformational switch when in an ATP-rich environment. The half-maximal inhibitory concentration of ATP-responsive nanovehicles is 0.24 μM in MDA-MB-231 cells, a 3.6-fold increase in the cytotoxicity compared with that of non-ATP-responsive nanovehicles. Equipped with an outer shell crosslinked by hyaluronic acid, a specific tumour-targeting ligand, the ATP-responsive nanocarriers present an improvement in the chemotherapeutic inhibition of tumour growth using xenograft MDA-MB-231 tumour-bearing mice. This ATP-triggered drug release system provides a more sophisticated drug delivery system, which can differentiate ATP levels to facilitate the selective release of drugs.

  7. FPGA-based data processing module design of on-board radiometric calibration in visible/near infrared bands

    NASA Astrophysics Data System (ADS)

    Zhou, Guoqing; Li, Chenyang; Yue, Tao; Liu, Na; Jiang, Linjun; Sun, Yue; Li, Mingyan

    2015-12-01

    FPGA technology has long been applied to on-board radiometric calibration data processing however the integration of FPGA program is not good enough. For example, some sensors compressed remote sensing images and transferred to ground station to calculate the calibration coefficients. It will affect the timeliness of on-board radiometric calibration. This paper designs an integrated flow chart of on-board radiometric calibration. Building FPGA-based radiometric calibration data processing modules uses system generator. Thesis focuses on analyzing the calculation accuracy of FPGA-based two-point method and verifies the feasibility of this method. Calibration data was acquired by hardware platform which was built using integrating sphere, CMOS camera (canon 60d), ASD spectrometers and light filter (center wavelength: 690nm, bandwidth: 45nm). The platform can simulate single-band on-board radiometric calibration data acquisition in visible/near infrared band. Making an experiment of calibration coefficients calculation uses obtained data and FPGA modules. Experimental results show that: the camera linearity is above 99% meeting the experimental requirement. Compares with MATLAB the calculation accuracy of two-point method by FPGA are as follows: the error of gain value is 0.0053%; the error of offset value is 0.00038719%. Those results meet experimental accuracy requirement.

  8. Integral magnetic ignition pickup trigger

    SciTech Connect

    King, R.

    1992-10-27

    This patent describes a trigger system for the ignition system of an internal combustion engine having a crankcase with a rotatable crankshaft therein, and a flywheel on one end of the crankcase connected to an end of the crankshaft. It comprises: a nonferromagnetic disk-shaped hub for connection to the crankshaft and rotatable therewith on the end opposite the flywheel; and a stationary sensor mounted adjacent the hub for detecting impulses from the magnetically responsive elements as the hub rotates and utilizing the impulses to trigger the ignition system.

  9. Know Your Smoking Triggers | Smokefree.gov

    Cancer.gov

    Triggers are the things that make you want to smoke. Different people have different triggers, like a stressful situation, sipping coffee, going to a party, or smelling cigarette smoke. Most triggers fall into one of these four categories: Emotional Pattern Social Withdrawal Knowing your triggers and understanding the best way to deal with them is your first line of defense.

  10. FPGA-based Elman neural network control system for linear ultrasonic motor.

    PubMed

    Lin, Faa-Jeng; Hung, Ying-Chih

    2009-01-01

    A field-programmable gate array (FPGA)-based Elman neural network (ENN) control system is proposed to control the mover position of a linear ultrasonic motor (LUSM) in this study. First, the structure and operating principle of the LUSM are introduced. Because the dynamic characteristics and motor parameters of the LUSM are nonlinear and time-varying, an ENN control system is designed to achieve precision position control. The network structure and online learning algorithm using delta adaptation law of the ENN are described in detail. Then, a piecewise continuous function is adopted to replace the sigmoid function in the hidden layer of the ENN to facilitate hardware implementation. In addition, an FPGA chip is adopted to implement the developed control algorithm for possible low-cost and high-performance industrial applications. The effectiveness of the proposed control scheme is verified by some experimental results.

  11. An FPGA Implementation of a Polychronous Spiking Neural Network with Delay Adaptation

    PubMed Central

    Wang, Runchun; Cohen, Gregory; Stiefel, Klaus M.; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, André

    2013-01-01

    We present an FPGA implementation of a re-configurable, polychronous spiking neural network with a large capacity for spatial-temporal patterns. The proposed neural network generates delay paths de novo, so that only connections that actually appear in the training patterns will be created. This allows the proposed network to use all the axons (variables) to store information. Spike Timing Dependent Delay Plasticity is used to fine-tune and add dynamics to the network. We use a time multiplexing approach allowing us to achieve 4096 (4k) neurons and up to 1.15 million programmable delay axons on a Virtex 6 FPGA. Test results show that the proposed neural network is capable of successfully recalling more than 95% of all spikes for 96% of the stored patterns. The tests also show that the neural network is robust to noise from random input spikes. PMID:23408739

  12. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

    DOEpatents

    Asaad, Sameh W.; Kapur, Mohit

    2016-03-15

    A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

  13. An FPGA-based bolometer for the MAST-U Super-X divertor

    NASA Astrophysics Data System (ADS)

    Lovell, Jack; Naylor, Graham; Field, Anthony; Drewelow, Peter; Sharples, Ray

    2016-11-01

    A new resistive bolometer system has been developed for MAST-Upgrade. It will measure radiated power in the new Super-X divertor, with millisecond time resolution, along 16 vertical and 16 horizontal lines of sight. The system uses a Xilinx Zynq-7000 series Field-Programmable Gate Array (FPGA) in the D-TACQ ACQ2106 carrier to perform real time data acquisition and signal processing. The FPGA enables AC-synchronous detection using high performance digital filtering to achieve a high signal-to-noise ratio and will be able to output processed data in real time with millisecond latency. The system has been installed on 8 previously unused channels of the JET vertical bolometer system. Initial results suggest good agreement with data from existing vertical channels but with higher bandwidth and signal-to-noise ratio.

  14. A Secure Content Delivery System Based on a Partially Reconfigurable FPGA

    NASA Astrophysics Data System (ADS)

    Hori, Yohei; Yokoyama, Hiroyuki; Sakane, Hirofumi; Toda, Kenji

    We developed a content delivery system using a partially reconfigurable FPGA to securely distribute digital content on the Internet. With partial reconfigurability of a Xilinx Virtex-II Pro FPGA, the system provides an innovative single-chip solution for protecting digital content. In the system, a partial circuit must be downloaded from a server to the client terminal to play content. Content will be played only when the downloaded circuit is correctly combined (=interlocked) with the circuit built in the terminal. Since each circuit has a unique I/O configuration, the downloaded circuit interlocks with the corresponding built-in circuit designed for a particular terminal. Thus, the interface of the circuit itself provides a novel authentication mechanism. This paper describes the detailed architecture of the system and clarify the feasibility and effectiveness of the system. In addition, we discuss a fail-safe mechanism and future work necessary for the practical application of the system.

  15. Detection of Small Sized GEO Debris Using FPGA Based Stacking Method

    NASA Astrophysics Data System (ADS)

    Yanagisawa, Toshifumi; Hanada, Toshiya; Kurosaki, Hirohisa; Kitazawa, Yukihito; Uetsuhara, Masahiko; Kinoshita, Daisuke

    2012-07-01

    In order to detect faint moving objects such as space debris, asteroids and comet, a FPGA based analysis method has been developed. The original stacking method, which uses multiple images to improve signal-to-noise ratio and runs as a software on PC, has a disadvantage of taking enormous time to analyze. A new algorithm and its installation into a FPGA board solved the problem by reducing analysis time about one thousandth. A collaborative observation between Japan and Taiwan was conducted to search for undiscovered debris fragments generated from a breakup event of US Titan IIIC Transtage. A lot of fragments that may be related to the breakup were discovered by analyzing with the method which verifies the effectiveness of the method.

  16. A Real-Time de novo DNA Sequencing Assembly Platform Based on an FPGA Implementation.

    PubMed

    Hu, Yuanqi; Georgiou, Pantelis

    2016-01-01

    This paper presents an FPGA based DNA comparison platform which can be run concurrently with the sensing phase of DNA sequencing and shortens the overall time needed for de novo DNA assembly. A hybrid overlap searching algorithm is applied which is scalable and can deal with incremental detection of new bases. To handle the incomplete data set which gradually increases during sequencing time, all-against-all comparisons are broken down into successive window-against-window comparison phases and executed using a novel dynamic suffix comparison algorithm combined with a partitioned dynamic programming method. The complete system has been designed to facilitate parallel processing in hardware, which allows real-time comparison and full scalability as well as a decrease in the number of computations required. A base pair comparison rate of 51.2 G/s is achieved when implemented on an FPGA with successful DNA comparison when using data sets from real genomes.

  17. An FPGA Implementation of a Polychronous Spiking Neural Network with Delay Adaptation.

    PubMed

    Wang, Runchun; Cohen, Gregory; Stiefel, Klaus M; Hamilton, Tara Julia; Tapson, Jonathan; van Schaik, André

    2013-01-01

    We present an FPGA implementation of a re-configurable, polychronous spiking neural network with a large capacity for spatial-temporal patterns. The proposed neural network generates delay paths de novo, so that only connections that actually appear in the training patterns will be created. This allows the proposed network to use all the axons (variables) to store information. Spike Timing Dependent Delay Plasticity is used to fine-tune and add dynamics to the network. We use a time multiplexing approach allowing us to achieve 4096 (4k) neurons and up to 1.15 million programmable delay axons on a Virtex 6 FPGA. Test results show that the proposed neural network is capable of successfully recalling more than 95% of all spikes for 96% of the stored patterns. The tests also show that the neural network is robust to noise from random input spikes.

  18. A real-time n/γ digital pulse shape discriminator based on FPGA.

    PubMed

    Li, Shiping; Xu, Xiufeng; Cao, Hongrui; Yuan, Guoliang; Yang, Qingwei; Yin, Zejie

    2013-02-01

    A FPGA-based real-time digital pulse shape discriminator has been employed to distinguish between neutrons (n) and gammas (γ) in the Neutron Flux Monitor (NFM) for International Thermonuclear Experimental Reactor (ITER). The discriminator takes advantages of the Field Programmable Gate Array (FPGA) parallel and pipeline process capabilities to carry out the real-time sifting of neutrons in n/γ mixed radiation fields, and uses the rise time and amplitude inspection techniques simultaneously as the discrimination algorithm to observe good n/γ separation. Some experimental results have been presented which show that this discriminator can realize the anticipated goals of NFM perfectly with its excellent discrimination quality and zero dead time.

  19. An FPGA-based Doppler Processor for a Spaceborne Precipitation Radar

    NASA Technical Reports Server (NTRS)

    Durden, S. L.; Fischman, M. A.; Johnson, R. A.; Chu, A. J.; Jourdan, M. N.; Tanelli, S.

    2007-01-01

    Measurement of precipitation Doppler velocity by spaceborne radar is complicated by the large velocity of the satellite platform. Even if successive pulses are well correlated, the velocity measurement may be biased if the precipitation target does not uniformly fill the radar footprint. It has been previously shown that the bias in such situations can be reduced if full spectral processing is used. The authors present a processor based on field-programmable gate array (FPGA) technology that can be used for spectral processing of data acquired by future spaceborne precipitation radars. The requirements for and design of the Doppler processor are addressed. Simulation and laboratory test results show that the processor can meet real-time constraints while easily fitting in a single FPGA.

  20. Research on acceleration method of reactor physics based on FPGA platforms

    SciTech Connect

    Li, C.; Yu, G.; Wang, K.

    2013-07-01

    The physical designs of the new concept reactors which have complex structure, various materials and neutronic energy spectrum, have greatly improved the requirements to the calculation methods and the corresponding computing hardware. Along with the widely used parallel algorithm, heterogeneous platforms architecture has been introduced into numerical computations in reactor physics. Because of the natural parallel characteristics, the CPU-FPGA architecture is often used to accelerate numerical computation. This paper studies the application and features of this kind of heterogeneous platforms used in numerical calculation of reactor physics through practical examples. After the designed neutron diffusion module based on CPU-FPGA architecture achieves a 11.2 speed up factor, it is proved to be feasible to apply this kind of heterogeneous platform into reactor physics. (authors)

  1. Development of a FPGA&DSP-based experimental GNSS receiver platform

    NASA Astrophysics Data System (ADS)

    Hu, Yongkang; Zhang, Qishan; Yang, Dongkai

    2009-12-01

    In order to match the flexible requirements of GNSS receiver design, the solution of developing such a universal platform has grown in importance. In this light, this paper introduces a work for the realization of an experimental FPGA&DSP-based GNSS receiver platform, which is according to the Software Defined Radio (SDR) philosophy. Starting from the justification for the hardware devices selected, this paper firstly describes the whole structure. Then the design of base band channel based on FPGA is presented. This includes the design of an individual base band channel and the design of local code generation. The realization of signal acquisition and tracking in DSP is introduced. Finally a signal tracking experiment is introduced, which justified the platform's availability.

  2. 10 Gbps TCP/IP streams from the FPGA for High Energy Physics

    SciTech Connect

    Bauer, Gerry; et al.

    2014-01-01

    The DAQ system of the CMS experiment at CERN collects data from more than 600 custom detector Front-End Drivers (FEDs). During 2013 and 2014 the CMS DAQ system will undergo a major upgrade to address the obsolescence of current hardware and the requirements posed by the upgrade of the LHC accelerator and various detector components. For a loss-less data collection from the FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. To limit the TCP hardware implementation complexity the DAQ group developed a simplified and unidirectional but RFC 793 compliant version of the TCP protocol. This allows to use a PC with the standard Linux TCP/IP stack as a receiver. We present the challenges and protocol modifications made to TCP in order to simplify its FPGA implementation. We also describe the interaction between the simplified TCP and Linux TCP/IP stack including the performance measurements.

  3. A Real-Time de novo DNA Sequencing Assembly Platform Based on an FPGA Implementation.

    PubMed

    Hu, Yuanqi; Georgiou, Pantelis

    2016-01-01

    This paper presents an FPGA based DNA comparison platform which can be run concurrently with the sensing phase of DNA sequencing and shortens the overall time needed for de novo DNA assembly. A hybrid overlap searching algorithm is applied which is scalable and can deal with incremental detection of new bases. To handle the incomplete data set which gradually increases during sequencing time, all-against-all comparisons are broken down into successive window-against-window comparison phases and executed using a novel dynamic suffix comparison algorithm combined with a partitioned dynamic programming method. The complete system has been designed to facilitate parallel processing in hardware, which allows real-time comparison and full scalability as well as a decrease in the number of computations required. A base pair comparison rate of 51.2 G/s is achieved when implemented on an FPGA with successful DNA comparison when using data sets from real genomes. PMID:27045828

  4. FPGA implementation of motifs-based neuronal network and synchronization analysis

    NASA Astrophysics Data System (ADS)

    Deng, Bin; Zhu, Zechen; Yang, Shuangming; Wei, Xile; Wang, Jiang; Yu, Haitao

    2016-06-01

    Motifs in complex networks play a crucial role in determining the brain functions. In this paper, 13 kinds of motifs are implemented with Field Programmable Gate Array (FPGA) to investigate the relationships between the networks properties and motifs properties. We use discretization method and pipelined architecture to construct various motifs with Hindmarsh-Rose (HR) neuron as the node model. We also build a small-world network based on these motifs and conduct the synchronization analysis of motifs as well as the constructed network. We find that the synchronization properties of motif determine that of motif-based small-world network, which demonstrates effectiveness of our proposed hardware simulation platform. By imitation of some vital nuclei in the brain to generate normal discharges, our proposed FPGA-based artificial neuronal networks have the potential to replace the injured nuclei to complete the brain function in the treatment of Parkinson's disease and epilepsy.

  5. 10 Gbps TCP/IP streams from the FPGA for High Energy Physics

    NASA Astrophysics Data System (ADS)

    Bauer, Gerry; Bawej, Tomasz; Behrens, Ulf; Branson, James; Chaze, Olivier; Cittolin, Sergio; Coarasa, Jose Antonio; Darlea, Georgiana-Lavinia; Deldicque, Christian; Dobson, Marc; Dupont, Aymeric; Erhan, Samim; Gigi, Dominique; Glege, Frank; Gomez-Ceballos, Guillelmo; Gomez-Reino, Robert; Hartl, Christian; Hegeman, Jeroen; Holzner, Andre; Masetti, Lorenzo; Meijers, Frans; Meschi, Emilio; Mommsen, Remigius K.; Morovic, Srecko; Nunez-Barranco-Fernandez, Carlos; O'Dell, Vivian; Orsini, Luciano; Ozga, Wojciech; Paus, Christoph; Petrucci, Andrea; Pieri, Marco; Racz, Attila; Raginel, Olivier; Sakulin, Hannes; Sani, Matteo; Schwick, Christoph; Cristian Spataru, Andrei; Stieger, Benjamin; Sumorok, Konstanty; Veverka, Jan; Wakefield, Christopher Colin; Zejdl, Petr

    2014-06-01

    The DAQ system of the CMS experiment at CERN collects data from more than 600 custom detector Front-End Drivers (FEDs). During 2013 and 2014 the CMS DAQ system will undergo a major upgrade to address the obsolescence of current hardware and the requirements posed by the upgrade of the LHC accelerator and various detector components. For a loss-less data collection from the FEDs a new FPGA based card implementing the TCP/IP protocol suite over 10Gbps Ethernet has been developed. To limit the TCP hardware implementation complexity the DAQ group developed a simplified and unidirectional but RFC 793 compliant version of the TCP protocol. This allows to use a PC with the standard Linux TCP/IP stack as a receiver. We present the challenges and protocol modifications made to TCP in order to simplify its FPGA implementation. We also describe the interaction between the simplified TCP and Linux TCP/IP stack including the performance measurements.

  6. A new cellular nonlinear network emulation on FPGA for EEG signal processing in epilepsy

    NASA Astrophysics Data System (ADS)

    Müller, Jens; Müller, Jan; Tetzlaff, Ronald

    2011-05-01

    For processing of EEG signals, we propose a new architecture for the hardware emulation of discrete-time Cellular Nonlinear Networks (DT-CNN). Our results show the importance of a high computational accuracy in EEG signal prediction that cannot be achieved with existing analogue VLSI circuits. The refined architecture of the processing elements and its resource schedule, the cellular network structure with local couplings, the FPGA-based embedded system containing the DT-CNN, and the data flow in the entire system will be discussed in detail. The proposed DT-CNN design has been implemented and tested on an Xilinx FPGA development platform. The embedded co-processor with a multi-threading kernel is utilised for control and pre-processing tasks and data exchange to the host via Ethernet. The performance of the implemented DT-CNN has been determined for a popular example and compared to that of a conventional computer.

  7. Advanced image processing package for FPGA-based re-programmable miniature electronics

    NASA Astrophysics Data System (ADS)

    Ovod, Vladimir I.; Baxter, Christopher R.; Massie, Mark A.; McCarley, Paul L.

    2005-05-01

    Nova Sensors produces miniature electronics for a variety of real-time digital video camera systems, including foveal sensors based on Nova's Variable Acuity Superpixel Imager (VASITM) technology. An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical, background velocimetry and target tracking. Currently, the processing package consists of 14 processing operations that cover a broad range of point- and area-applied algorithms. Flexible FPGA designs of these operations and re-programmability of the processing board allows for easy updates of the VASITM sensors, and for low-cost customization of VASITM sensors taking into account specific customer requirements. This paper describes the image processing algorithms implemented and verified in Xilinx FPGAs and provides the major technical performances with figures illustrating practical applications of the processing package.

  8. A New Look at Trigger Point Injections

    PubMed Central

    Wong, Clara S. M.; Wong, Steven H. S.

    2012-01-01

    Trigger point injections are commonly practised pain interventional techniques. However, there is still lack of objective diagnostic criteria for trigger points. The mechanisms of action of trigger point injection remain obscure and its efficacy remains heterogeneous. The advent of ultrasound technology in the noninvasive real-time imaging of soft tissues sheds new light on visualization of trigger points, explaining the effect of trigger point injection by blockade of peripheral nerves, and minimizing the complications of blind injection. PMID:21969825

  9. Hydrodynamical trigger mechanism for pulsar glitches.

    PubMed

    Glampedakis, Kostas; Andersson, Nils

    2009-04-10

    We describe a new instability that may trigger the global unpinning of vortices in a spinning neutron star, leading to the transfer of angular momentum from the superfluid component to the star's crust. The instability, which is associated with the inertial r modes of a superfluid neutron star, sets in once the rotational lag in the system reaches a critical level. We demonstrate that our simple model agrees well with the observed glitch data. This new idea should stimulate work on more detailed neutron star models, which would account for the crustal shear stresses and magnetic field effects we have ignored. PMID:19392421

  10. FPGA-based voltage and current dual drive system for high frame rate electrical impedance tomography.

    PubMed

    Khan, Shadab; Manwaring, Preston; Borsic, Andrea; Halter, Ryan

    2015-04-01

    Electrical impedance tomography (EIT) is used to image the electrical property distribution of a tissue under test. An EIT system comprises complex hardware and software modules, which are typically designed for a specific application. Upgrading these modules is a time-consuming process, and requires rigorous testing to ensure proper functioning of new modules with the existing ones. To this end, we developed a modular and reconfigurable data acquisition (DAQ) system using National Instruments' (NI) hardware and software modules, which offer inherent compatibility over generations of hardware and software revisions. The system can be configured to use up to 32-channels. This EIT system can be used to interchangeably apply current or voltage signal, and measure the tissue response in a semi-parallel fashion. A novel signal averaging algorithm, and 512-point fast Fourier transform (FFT) computation block was implemented on the FPGA. FFT output bins were classified as signal or noise. Signal bins constitute a tissue's response to a pure or mixed tone signal. Signal bins' data can be used for traditional applications, as well as synchronous frequency-difference imaging. Noise bins were used to compute noise power on the FPGA. Noise power represents a metric of signal quality, and can be used to ensure proper tissue-electrode contact. Allocation of these computationally expensive tasks to the FPGA reduced the required bandwidth between PC, and the FPGA for high frame rate EIT. In 16-channel configuration, with a signal-averaging factor of 8, the DAQ frame rate at 100 kHz exceeded 110 frames s (-1), and signal-to-noise ratio exceeded 90 dB across the spectrum. Reciprocity error was found to be for frequencies up to 1 MHz. Static imaging experiments were performed on a high-conductivity inclusion placed in a saline filled tank; the inclusion was clearly localized in the reconstructions obtained for both absolute current and voltage mode data. PMID:25376037

  11. FPGA implementation of high-frequency multiple PWM for variable voltage variable frequency controller

    NASA Astrophysics Data System (ADS)

    Boumaaraf, Abdelâali; Mohamadi, Tayeb; Gourmat, Laïd

    2016-07-01

    In this paper, we present the FPGA implementation of the multiple pulse width modulation (MPWM) signal generation with repetition of data segments, applied to the variable frequency variable voltage systems and specially at to the photovoltaic water pumping system, in order to generate a signal command very easily between 10hz to 60 hz with a small frequency and reduce the cost of the control system.

  12. FPGA-based voltage and current dual drive system for high frame rate electrical impedance tomography.

    PubMed

    Khan, Shadab; Manwaring, Preston; Borsic, Andrea; Halter, Ryan

    2015-04-01

    Electrical impedance tomography (EIT) is used to image the electrical property distribution of a tissue under test. An EIT system comprises complex hardware and software modules, which are typically designed for a specific application. Upgrading these modules is a time-consuming process, and requires rigorous testing to ensure proper functioning of new modules with the existing ones. To this end, we developed a modular and reconfigurable data acquisition (DAQ) system using National Instruments' (NI) hardware and software modules, which offer inherent compatibility over generations of hardware and software revisions. The system can be configured to use up to 32-channels. This EIT system can be used to interchangeably apply current or voltage signal, and measure the tissue response in a semi-parallel fashion. A novel signal averaging algorithm, and 512-point fast Fourier transform (FFT) computation block was implemented on the FPGA. FFT output bins were classified as signal or noise. Signal bins constitute a tissue's response to a pure or mixed tone signal. Signal bins' data can be used for traditional applications, as well as synchronous frequency-difference imaging. Noise bins were used to compute noise power on the FPGA. Noise power represents a metric of signal quality, and can be used to ensure proper tissue-electrode contact. Allocation of these computationally expensive tasks to the FPGA reduced the required bandwidth between PC, and the FPGA for high frame rate EIT. In 16-channel configuration, with a signal-averaging factor of 8, the DAQ frame rate at 100 kHz exceeded 110 frames s (-1), and signal-to-noise ratio exceeded 90 dB across the spectrum. Reciprocity error was found to be for frequencies up to 1 MHz. Static imaging experiments were performed on a high-conductivity inclusion placed in a saline filled tank; the inclusion was clearly localized in the reconstructions obtained for both absolute current and voltage mode data.

  13. Single event upset susceptibility testing of the Xilinx Virtex II FPGA

    NASA Technical Reports Server (NTRS)

    Yui, C.; Swift, G.; Carmichael, C.

    2002-01-01

    Heavy ion testing of the Xilinx Virtex IZ was conducted on the configuration, block RAM and user flip flop cells to determine their single event upset susceptibility using LETs of 1.2 to 60 MeVcm^2/mg. A software program specifically designed to count errors in the FPGA is used to reveal L1/e values and single-event-functional interrupt failures.

  14. Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart Payloads

    NASA Technical Reports Server (NTRS)

    Pingree, Paula J.; Scharenbroich, Lucas J.; Werne, Thomas A.; Hartzell, Christine

    2008-01-01

    Accurate, on-board classification of instrument data is used to increase science return by autonomously identifying regions of interest for priority transmission or generating summary products to conserve transmission bandwidth. Due to on-board processing constraints, such classification has been limited to using the simplest functions on a small subset of the full instrument data. FPGA co-processor designs for SVM1 classifiers will lead to significant improvement in on-board classification capability and accuracy.

  15. A fast readout algorithm for Cluster Counting/Timing drift chambers on a FPGA board

    NASA Astrophysics Data System (ADS)

    Cappelli, L.; Creti, P.; Grancagnolo, F.; Pepino, A.; Tassielli, G.

    2013-08-01

    A fast readout algorithm for Cluster Counting and Timing purposes has been implemented and tested on a Virtex 6 core FPGA board. The algorithm analyses and stores data coming from a Helium based drift tube instrumented by 1 GSPS fADC and represents the outcome of balancing between cluster identification efficiency and high speed performance. The algorithm can be implemented in electronics boards serving multiple fADC channels as an online preprocessing stage for drift chamber signals.

  16. [Design of an FPGA-based image guided surgery hardware platform].

    PubMed

    Zou, Fa-Dong; Qin, Bin-Jie

    2008-07-01

    An FPGA-Based Image Guided Surgery Hardware Platform has been designed and implemented in this paper. The hardware platform can provide hardware acceleration for image guided surgery. It is completed with a video decoder interface, a DDR memory controller, a 12C bus controller, an interrupt controller and so on. It is able to perform real time video endoscopy image capturing in the surgery and to preserve the hardware interface for image guided surgery algorithm module. PMID:18973036

  17. Environmental Triggers of Autoimmune Thyroiditis

    PubMed Central

    Burek, C. Lynne; Talor, Monica V.

    2009-01-01

    Autoimmune thyroiditis is among the most prevalent of all the autoimmunities. Autoimmune thyroiditis is multifactorial with contributions from genetic and environmental factors. Much information has been published about the genetic predisposition to autoimmune thyroiditis both in experimental animals and humans. There is, in contrast, very little data on environmental agents that can serve as the trigger or autoimmunity in a genetically predisposed host. The best-established environmental factor is excess dietary iodine. Increased iodine consumption is strongly implicated as a trigger for thyroiditis, but only in genetically susceptible individuals. However, excess iodine is not the only environmental agent implicated as a trigger leading to autoimmune thyroiditis. There are a wide variety of other synthetic chemicals that affect the thyroid gland or have the ability to promote immune dysfunction in the host. These chemicals are released into the environment by design, such as in pesticides, or as a by-product of industry. Candidate pollutants include polyaromatic hydrocarbons, polybrominated biphenols, and polychlorinated biphenols, among others. Infections are also reputed to trigger autoimmunity and may act alone or in concert with environmental chemicals. We have utilized a unique animal model, the NOD.H2h4 mouse to explore the influence of iodine and other environmental factors on autoimmune thyroiditis. PMID:19818584

  18. Environmental triggers of autoimmune thyroiditis.

    PubMed

    Burek, C Lynne; Talor, Monica V

    2009-01-01

    Autoimmune thyroiditis is among the most prevalent of all the autoimmunities. Autoimmune thyroiditis is multifactorial with contributions from genetic and environmental factors. Much information has been published about the genetic predisposition to autoimmune thyroiditis both in experimental animals and humans. There is, in contrast, very little data on environmental agents that can serve as the trigger for autoimmunity in a genetically predisposed host. The best-established environmental factor is excess dietary iodine. Increased iodine consumption is strongly implicated as a trigger for thyroiditis, but only in genetically susceptible individuals. However, excess iodine is not the only environmental agent implicated as a trigger leading to autoimmune thyroiditis. There are a wide variety of other synthetic chemicals that affect the thyroid gland or have the ability to promote immune dysfunction in the host. These chemicals are released into the environment by design, such as in pesticides, or as a by-product of industry. Candidate pollutants include polyaromatic hydrocarbons, polybrominated biphenols, and polychlorinated biphenols, among others. Infections are also reputed to trigger autoimmunity and may act alone or in concert with environmental chemicals. We have utilized a unique animal model, the NOD.H2(h4) mouse to explore the influence of iodine and other environmental factors on autoimmune thyroiditis. PMID:19818584

  19. Suicide Triggers Described by Herodotus

    PubMed Central

    Auchincloss, Stephane; Ahmadi, Jamshid

    2016-01-01

    Objective: The aim of this study was to better understand the triggers of suicide, particularly among the ancient Greek and Persian soldiers and commanders. Method: ‘Herodotus:TheHistories’ is a history of the rulers and soldiery who participated in the Greco-Persian wars (492-449 BCE). A new translation (2013) of this manuscript was studied. Accounts of suicide were collected and collated, with descriptions of circumstances, methods, and probable triggers. Results: Nine accounts of suicide were identified. Eight of these were named individuals (4 Greeks and 4 Persians); of whom, seven were male. Only one (not the female) appeared to act in response to a mental disorder. Other triggers of suicide included guilt, avoidance of dishonour/punishment and altruism. Cutting/ stabbing was the most common method; others included hanging, jumping, poison, and burning (the single female). Conclusion: While soldiers at a time of war do not reflect the general community, they are nevertheless members of their society. Thus, this evidence demonstrates that suicide triggered by burdensome circumstances (in addition to mental disorder) was known to the Greek and Persian people more than two millennia ago. PMID:27437010

  20. Triggering Reform at Public Schools

    ERIC Educational Resources Information Center

    Kelly, Andrew P.

    2012-01-01

    An intriguing experiment is afoot in some of the nation's struggling public schools. New "Parent Trigger" laws passed in California and on the agenda in New York, Ohio, Colorado, and Chicago, allow parents of chronically failing schools to unseat the schools' leadership and staff. But the initiative has pitfalls. It's easy to mobilize parents to…