Strong, G.H.; Faught, M.L.
1963-12-24
A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)
Optically controllable molecular logic circuits
NASA Astrophysics Data System (ADS)
Nishimura, Takahiro; Fujii, Ryo; Ogura, Yusuke; Tanida, Jun
2015-07-01
Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.
Optically controllable molecular logic circuits
Nishimura, Takahiro Fujii, Ryo; Ogura, Yusuke; Tanida, Jun
2015-07-06
Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.
Logic synthesis of cascade circuits
NASA Astrophysics Data System (ADS)
Zakrevskii, A. D.
The work reviews aspects of the logic design of cascade circuits, particularly programmable logic matrices. Effective methods for solving various problems of the analysis and synthesis of these devices are examined; these methods are based on a matrix representation of the structure of these devices, and a vector-matrix interpretation of certain aspects of Boolean algebra. Particular consideration is given to the theory of elementary matrix circuits, methods for the minimization of Boolean functions, the synthesis of programmable logic matrices, multilevel combinational networks, and the development of automata with memory.
Computerized logic design of digital circuits
NASA Technical Reports Server (NTRS)
Gussow, S.; Oglesby, R.
1974-01-01
Procedure performs all work required for logic design of digital counters or sequential circuits and simplification of Boolean expressions. Program provides simple, accurate, and comprehensive logic design capability to users both experienced and totally inexperienced in logic design
Computerized logic design of digital circuits
NASA Technical Reports Server (NTRS)
Sussow, S.; Oglesby, R.
1973-01-01
This manual presents a computer program that performs all the work required for the logic design of digital counters or sequential circuits and the simplification of Boolean logic expressions. The program provides both the experienced and inexperienced logic designer with a comprehensive logic design capability. The manual contains Boolean simplification and sequential design theory, detailed instructions for use of the program, a large number of illustrative design examples, and complete program documentation.
New Logic Circuit with DC Parametric Excitation
NASA Astrophysics Data System (ADS)
Sugahara, Masanori; Kaneda, Hisayoshi
1982-12-01
It is shown that dc parametric excitation is possible in a circuit named JUDO, which is composed of two resistively-connected Josephson junctions. Simulation study proves that the circuit has large gain and properties suitable for the construction of small, high-speed logic circuits.
Faster Evolution of More Multifunctional Logic Circuits
NASA Technical Reports Server (NTRS)
Stoica, Adrian; Zebulum, Ricardo
2005-01-01
A modification in a method of automated evolutionary synthesis of voltage-controlled multifunctional logic circuits makes it possible to synthesize more circuits in less time. Prior to the modification, the computations for synthesizing a four-function logic circuit by this method took about 10 hours. Using the method as modified, it is possible to synthesize a six-function circuit in less than half an hour. The concepts of automated evolutionary synthesis and voltage-controlled multifunctional logic circuits were described in a number of prior NASA Tech Briefs articles. To recapitulate: A circuit is designed to perform one of several different logic functions, depending on the value of an applied control voltage. The circuit design is synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. In this process, random populations of integer strings that encode electronic circuits play a role analogous to that of chromosomes. An evolved circuit is tested by computational simulation (prior to testing in real hardware to verify a final design). Then, in a fitness-evaluation step, responses of the circuit are compared with specifications of target responses and circuits are ranked according to how close they come to satisfying specifications. The results of the evaluation provide guidance for refining designs through further iteration.
Demonstrating Boolean Logic Using Simple Electrical Circuits
ERIC Educational Resources Information Center
McElhaney, Kevin W.
2004-01-01
While exploring the subject of geometric proofs, boolean logic operators AND and OR can be used to allow students to visualize their true-or-false patterns. An activity in the form of constructing electrical circuits is illustrated to explain the concept.
Synthesis of logic circuits with evolutionary algorithms
JONES,JAKE S.; DAVIDSON,GEORGE S.
2000-01-26
In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.
Nonlinear dynamics based digital logic and circuits
Kia, Behnam; Lindner, John. F.; Ditto, William L.
2015-01-01
We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096
Nonlinear dynamics based digital logic and circuits.
Kia, Behnam; Lindner, John F; Ditto, William L
2015-01-01
We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096
Nanoeletromechanical switch and logic circuits formed therefrom
Nordquist, Christopher D.; Czaplewski, David A.
2010-05-18
A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.
Scaling of pneumatic digital logic circuits.
Duncan, Philip N; Ahrar, Siavash; Hui, Elliot E
2015-03-01
The scaling of integrated circuits to smaller dimensions is critical for achieving increased system complexity and speed. Digital logic circuits composed of pneumatic microfluidic components have to this point been limited to a circuit density of 2-4 gates cm(-2), constraining the complexity of the digital systems that can be achieved. We explored the use of precision machining techniques to reduce the size of pneumatic valves and resistors, and to achieve more accurate and efficient placement of ports and vias. In this way, we attained an order of magnitude increase in circuit density, reaching as high as 36 gates cm(-2). A 12-bit binary counter circuit composed of 96 gates was realized in an area of 360 mm(2). The reduction in size also brought an order of magnitude increase in speed. The frequency of a 13-stage ring oscillator increased from 2.6 Hz to 22.1 Hz, and the maximum clock frequency of a binary counter increased from 1/3 Hz to 6 Hz. PMID:25591784
Superconductive combinational logic circuit using magnetically coupled SQUID array
NASA Astrophysics Data System (ADS)
Yamanashi, Y.; Umeda, K.; Sai, K.
2010-11-01
In this paper, we propose the development of superconductive combinational logic circuits. One of the difficulties in designing superconductive single-flux-quantum (SFQ) digital circuits can be attributed to the fundamental nature of the SFQ circuits, in which all logic gates have latching functions and are based on sequential logic. The design of ultralow-power superconductive digital circuits can be facilitated by the development of superconductive combinational logic circuits in which the output is a function of only the present input. This is because superconductive combinational logic circuits do not require determination of the timing adjustment and clocking scheme. Moreover, semiconductor design tools can be used to design digital circuits because CMOS logic gates are based on combinational logic. The proposed superconductive combinational logic circuits comprise a magnetically coupled SQUID array. By adjusting the circuit parameters and coupling strengths between neighboring SQUIDs, fundamental combinational logic gates, including the AND, OR, and NOT gates, can be built. We have verified the accuracy of the operations of the fundamental logic gates by analog circuit simulations.
Fluid logic control circuit operates nutator actuator motor
NASA Technical Reports Server (NTRS)
1966-01-01
Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.
Design of synthetic biological logic circuits based on evolutionary algorithm.
Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei
2013-08-01
The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose. PMID:23919952
Digital circuits using universal logic gates
NASA Technical Reports Server (NTRS)
Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)
2004-01-01
According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin
2016-06-22
In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved. PMID:27237969
A transition calculus for Boolean functions. [logic circuit analysis
NASA Technical Reports Server (NTRS)
Tucker, J. H.; Bennett, A. W.
1974-01-01
A transition calculus is presented for analyzing the effect of input changes on the output of logic circuits. The method is closely related to the Boolean difference, but it is more powerful. Both differentiation and integration are considered.
Synthesizing genetic sequential logic circuit with clock pulse generator
2014-01-01
Background Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. Results This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. Conclusions A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal. PMID:24884665
Logic Circuits as a Vehicle for Technological Literacy.
ERIC Educational Resources Information Center
Hazeltine, Barrett
1985-01-01
Provides basic information on logic circuits, points out that the topic is a good vehicle for developing technological literacy. The subject could be included in such courses as philosophy, computer science, communications, as well as in courses dealing with electronic circuits. (JN)
Synthetic circuits integrating logic and memory in living cells.
Siuti, Piro; Yazbek, John; Lu, Timothy K
2013-05-01
Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications. PMID:23396014
Asynchronous sequential circuit design using pass transistor iterative logic arrays
NASA Technical Reports Server (NTRS)
Liu, M. N.; Maki, G. K.; Whitaker, S. R.
1991-01-01
The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.
Programmed DNA Self-Assembly and Logic Circuits
NASA Astrophysics Data System (ADS)
Li, Wei
DNA is a unique, highly programmable and addressable biomolecule. Due to its reliable and predictable base recognition behavior, uniform structural properties, and extraordinary stability, DNA molecules are desirable substrates for biological computation and nanotechnology. The field of DNA computation has gained considerable attention due to the possibility of exploiting the massive parallelism that is inherent in natural systems to solve computational problems. This dissertation focuses on building novel types of computational DNA systems based on both DNA reaction networks and DNA nanotechnology. A series of related research projects are presented here. First, a novel, three-input majority logic gate based on DNA strand displacement reactions was constructed. Here, the three inputs in the majority gate have equal priority, and the output will be true if any two of the inputs are true. We subsequently designed and realized a complex, 5-input majority logic gate. By controlling two of the five inputs, the complex gate is capable of realizing every combination of OR and AND gates of the other 3 inputs. Next, we constructed a half adder, which is a basic arithmetic unit, from DNA strand operated XOR and AND gates. The aim of these two projects was to develop novel types of DNA logic gates to enrich the DNA computation toolbox, and to examine plausible ways to implement large scale DNA logic circuits. The third project utilized a two dimensional DNA origami frame shaped structure with a hollow interior where DNA hybridization seeds were selectively positioned to control the assembly of small DNA tile building blocks. The small DNA tiles were directed to fill the hollow interior of the DNA origami frame, guided through sticky end interactions at prescribed positions. This research shed light on the fundamental behavior of DNA based self-assembling systems, and provided the information necessary to build programmed nanodisplays based on the self-assembly of DNA.
A Novel Synthesizing Genetic Logic Circuit: Frequency Multiplier.
Chuang, Chia-Hua; Lin, Chun-Liang
2014-01-01
This paper presents a novel synthesizing genetic logic circuit design based on an existing synthetic genetic oscillator, which provides a function of frequency multiplier to synthesize a clock signal whose frequency is a multiple of that of the genetic oscillator. In the renowned literature, the synthetic genetic oscillator, known as a repressilator, has been successfully built in Escherichia coli to generate a periodic oscillating phenomenon through three repressive genes repress each other in a chain. On the basis of this fact, our proposed genetic frequency multiplier circuit utilizes genetic Buffers in series with a waveform-shaping circuit to reshape the genetic oscillation signal into a crisp logic clock signal. By regulating different threshold levels in the Buffer, the time length of logic high/low levels in a fundamental sinusoidal wave can be engineered to pulse-width-modulated (PWM) signals with various duty cycles. Integrating some of genetic logic XOR gates and PWM signals from the output of the Buffers, a genetic frequency multiplier circuit can be created and the clock signal with the integer-fold of frequency of the genetic oscillator is generated. The synthesized signal can be used in triggering the downstream digital genetic logic circuits. Simulation results show the applicability of the proposed idea. PMID:26356341
The decomposition of an arbitrary reversible logic circuit
NASA Astrophysics Data System (ADS)
DeVos, Alexis; Van Rentergem, Yvan; DeKeyser, Koen
2006-05-01
The (2w)! reversible logic circuits of width w, i.e. reversible logic circuits with w inputs and w outputs, together with the action of cascading, form a group G, isomorphic to the symmetric group {\\bf S}_{2^w} . We define two conjugate subgroups G1 and G2. Together they partition the group G into 2w-1 + 1 double cosets. These allow us to decompose an arbitrary member of G into a cascade of three simpler members. This decomposition is a far relative of the well-known LU decomposition of a square matrix.
Mechanically Flexible and High-Performance CMOS Logic Circuits.
Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu
2015-01-01
Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882
Mechanically Flexible and High-Performance CMOS Logic Circuits
Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu
2015-01-01
Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882
Integrated logic circuits using single-atom transistors
Mol, J. A.; Verduijn, J.; Levine, R. D.; Remacle, F.
2011-01-01
Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal–oxide–semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050
Integrated logic circuits using single-atom transistors.
Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S
2011-08-23
Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch. PMID:21808050
Controlling High Power Devices with Computers or TTL Logic Circuits
ERIC Educational Resources Information Center
Carlton, Kevin
2002-01-01
Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…
Probing Dynamical Character of Neural Circuits by Using Fuzzy Logic
NASA Astrophysics Data System (ADS)
Hu, Hong; Shi, Zhongzhi
2008-11-01
Analytical study or designing of large-scale nonlinear neural circuits, especially for chaotic neural circuits, is a difficult task. Here we analyze the function of neural systems by probing the fuzzy logical framework of the neural cells' dynamical equations. In this paper, the fuzzy logical framework of neural cells is used to understand the nonlinear dynamic attributes of a common neural system, and we proved that if a neural system works in a non-chaotic way, a suitable fuzzy logical framework can be found and we can analyze or design such kind neural system similar to analyze or design a digit computer, but if a neural system works in a chaotic way, an approximation is needed for understanding the function of such neural system.
Efficient G(sup 4)FET-Based Logic Circuits
NASA Technical Reports Server (NTRS)
Vatan, Farrokh
2008-01-01
A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.
Mimicking the biological neural system using electronic logic circuits
NASA Astrophysics Data System (ADS)
Kirikera, Goutham R.; Shinde, Vishal; Kang, Inpil; Schulz, Mark J.; Shanov, Vesselin; Datta, Saurabh; Hurd, Doug; Westheider, Bo; Sundaresan, Mannur; Ghoshal, Anindya
2004-07-01
Detecting and locating cracks in structural components and joints that have high feature densities is a challenging problem in the field of Structural Health Monitoring. There have been advances in piezoelectric sensors, actuators, wave propagation, MEMS, and optical fiber sensors. However, few sensor-signal processing techniques have been applied to the monitoring of joints and complex structural geometries. This is in part because maintaining and analyzing a large amount of data obtained from a large number of sensors that may be needed to monitor joints for cracks is difficult. Reliable low cost assessment of the health of structures is crucial to maintain operational availability and productivity, reduce maintenance cost, and prevent catastrophic failure of large structures such as wind turbines, aircraft, and civil infrastructure. Recently, there have also been advances in development of simple passive techniques for health monitoring including a technique based on mimicking the biological neural system using electronic logic circuits. This technique aids in reducing the required number of data acquisition channels by a factor of ten or more and is able to predict the location of a crack within a rectangular grid or within an arbitrarily arranged network of continuous sensors or neurons. The current paper shows results obtained by implementing this method on an aluminum plate and joint. The plates were tested using simulated acoustic emissions and also loading via an MTS machine. The testing indicates that the neural system can monitor complex joints and detect acoustic emissions due to propagating cracks. High sensitivity of the neural system is needed, and further sensor development and testing on different types of joints is required. Also indicated is that sensor geometry, sensor location, signal filtering, and logic parameters of the neural system will be specific to the particular type of joint (material, thickness, geometry) being monitored. Also, a
Interlocked DNA nanostructures controlled by a reversible logic circuit.
Li, Tao; Lohmann, Finn; Famulok, Michael
2014-01-01
DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207
G(sup 4)FET Implementations of Some Logic Circuits
NASA Technical Reports Server (NTRS)
Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan
2009-01-01
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration
Implementation of a genetic logic circuit: bio-register.
Lin, Chun-Liang; Kuo, Ting-Yu; Chen, Yang-Yi
2015-12-01
We introduce an idea of synthesizing a class of genetic registers based on the existing sequential biological circuits, which are composed of fundamental biological gates. In the renowned literature, biological gates and genetic oscillator have been unveiled and experimentally realized in recent years. These biological circuits have formed a basis for realizing a primitive biocomputer. In the traditional computer architecture, there is an intermediate load-store section, i.e. a register, which serves as a part of the digital processor. With which, the processor can load data from a larger memory into it and proceed to conduct necessary arithmetic or logic operations. Then, manipulated data are stored back to the memory by instruction via the register. We propose here a class of bio-registers for the biocomputer. Four types of register structures are presented. In silicon experiments illustrate results of the proposed design. PMID:26702308
Design automation for integrated nonlinear logic circuits (Conference Presentation)
NASA Astrophysics Data System (ADS)
Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.
2016-05-01
A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite
Topological Properties of Combinational Logic Functions for Very Large Scale Integrated Circuits
NASA Astrophysics Data System (ADS)
Hiteshue, Elizabeth; Irvin, Kelsey; Lanzerotti, Mary; Vernizzi, Graziano; Kujawski, Joseph; Weatherwax, Allan
2014-03-01
This talk presents topological properties of combinational logic functions implemented with basic logic gates. Combinational logic can be implemented in very large scale integrated circuits, including high-performance microprocessors. Prior work has produced an historically-equivalent (HE) interpretation of Mr. E. F. Rent's 1960 memos for today's complex circuitry, an application to modern microprocessors, and topological constraints for electronic circuits. This talk will examine combinational logic blocks which may exhibit different connectivity and will evaluate their topological properties.
DOIND: a technique for leakage reduction in nanoscale domino logic circuits
NASA Astrophysics Data System (ADS)
Prasad Shah, Ambika; Neema, Vaibhav; Daulatabad, Shreeniwas
2016-05-01
A novel DOIND logic approach is proposed for domino logic, which reduces the leakage current with a minimum delay penalty. Simulation is performed at 70 nm technology node with supply voltage 1V for domino logic and DOIND logic based AND, OR, XOR and Half Adder circuits using the tanner EDA tool. Simulation results show that the proposed DOIND approach decreases the average leakage current by 68.83%, 66.6%, 77.86% and 74.34% for 2 input AND, OR, XOR and Half Adder respectively. The proposed approach also has 47.76% improvement in PDAP for the buffer circuit as compared to domino logic.
A novel circuit design for complementary resistive switch-based stateful logic operations
NASA Astrophysics Data System (ADS)
Xiao-Ping, Wang; Lin, Chen; Yi, Shen; Bo-Wen, Xu
2016-05-01
Recently, it has been demonstrated that memristors can be utilized as logic operations and memory elements. In this paper, we present a novel circuit design for complementary resistive switch (CRS)-based stateful logic operations. The proposed circuit can automatically write the destructive CRS cells back to the original states. In addition, the circuit can be used in massive passive crossbar arrays which can reduce sneak path current greatly. Moreover, the steps for CRS logic operations using our proposed circuit are reduced compared with previous circuit designs. We validate the effectiveness of our scheme through Hspice simulations on the logic circuits. Project supported by the National Natural Science Foundation of China (Grant Nos. 61374150 and 11271146), the State Key Program of the National Natural Science Foundation of China (Grant No. 61134012), the Doctoral Fund of Ministry of Education of China (Grant No. 20130142130012), and the Science and Technology Program of Shenzhen City, China (Grant No. JCYJ20140509162710496).
Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics
Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.
2015-02-17
Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.
Automatic Single-Flux-Quantum (SFQ) Logic Synthesis Method for Top-Down Circuit Design
NASA Astrophysics Data System (ADS)
Kameda, Yoshio; Yorozu, Shinichi; Hashimoto, Yoshihito
2006-06-01
Single-flux-quantum (SFQ) logic circuits provide faster operations with lower power consumption, using Josephson junctions as the switching devices. In the top-down flow of SFQ circuit design, we have already developed a place-and-route tool that covers backend circuit design. In this paper, we present an automatic SFQ logic synthesis method that covers front-end circuit design. The logic synthesis is a process that generates a gate-level logic circuit from a functional specification written in hardware description languages. In our SFQ synthesis method, after we generate an intermediate circuit with the help of a synthesis tool for semiconductor circuits, we convert it into a gate-level pipelined SFQ circuit. To do this, an automatic synthesis tool was implemented. To evaluate the effectiveness of the method and the tool, we synthesized arithmetic and logic units (ALUs). It took only two and half minutes to synthesize a 64-bit-width ALU that consisted of about 18, 000 gates.
Liu, Changxia; Yang, Dong; Jin, Qingxian; Zhang, Li; Liu, Minghua
2016-02-01
A chiral logic circuit is proposed based on the multiple chiroptical responsiveness of a supramolecular gel material. The gel is fabricated by mixing a chiral gelator and a spiropyran derivative. Chiral responsiveness including the chiral switch and the logic gate is realized through the combined chirality transfer, photochromism, and acidichromism of the system. PMID:26677055
Modular multi-level circuits from immobilized DNA-based logic gates.
Frezza, Brian M; Cockroft, Scott L; Ghadiri, M Reza
2007-12-01
One of the fundamental goals of molecular computing is to reproduce the tenets of digital logic, such as component modularity and hierarchical circuit design. An important step toward this goal is the creation of molecular logic gates that can be rationally wired into multi-level circuits. Here we report the design and functional characterization of a complete set of modular DNA-based Boolean logic gates (AND, OR, and AND-NOT) and further demonstrate their wiring into a three-level circuit that exhibits Boolean XOR (exclusive OR) function. The approach is based on solid-supported DNA logic gates that are designed to operate with single-stranded DNA inputs and outputs. Since the solution-phase serves as the communication medium between gates, circuit wiring can be achieved by designating the DNA output of one gate as the input to another. Solid-supported logic gates provide enhanced gate modularity versus solution-phase systems by significantly simplifying the task of choosing appropriate DNA input and output sequences used in the construction of multi-level circuits. The molecular logic gates and circuits reported here were characterized by coupling DNA outputs to a single-input REPORT gate and monitoring the resulting fluorescent output signals. PMID:17994734
Automatic test pattern generation for logic circuits using the Boolean tree
Jeong Taegwon.
1991-01-01
The goal of this study was to develop an algorithm that can generate test patterns for combinational circuits and sequential logic circuits automatically. The new proposed algorithm generates a test pattern by using a special tree called a modified Boolean tree. In this algorithm, the construction of a modified Boolean tree is the most time-consuming step. Following the construction of a modified Boolean tree, a test pattern can be found by simply assigning a logic value 1 for even primary inputs and a logic value 0 for odd primary inputs of the constructed modified Boolean tree. The algorithm is applied to several benchmark circuits. The results showed the following: (1) for combinational circuits, the algorithm can generate test patterns 10-15% faster than the FAN algorithm, which is known as one of the most efficient algorithms to-date; (2) for sequential circuits, the algorithm shows more fault coverage than the nine valued algorithm.
Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits
Lashin, A. V. Kozyrev, A. V.
2015-09-15
One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.
A tight-binding study of logic gate circuits for adding numbers inside a molecule
NASA Astrophysics Data System (ADS)
Stadler, R.; Ami, S.; Forshaw, M.; Joachim, C.
2002-06-01
The possibilities for the design of larger diode logic circuits such as a one-bit half-adder inside a molecule are investigated, based on a recent extension of the elastic scattering quantum chemistry technique. Since any diode logic circuit for an adder needs OR-gates and AND-gates as basic components and the properties of OR-gates have already been discussed in the ballistic and tunnelling electron transport regime, we focus on the more complicated AND-gates in the present work. For this case the output current, calculated from the transmission coefficients by using the Landauer-Büttiker formula, shows four different logical levels instead of two. The origin of this level variety is analysed in detail. The concept of programmable gate logic arrays is also addressed, where for intra-molecular circuits distinct deviations from earlier macroscopic or mesoscopic implementations of this scheme are found.
Integrated circuits and logic operations based on single-layer MoS2.
Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras
2011-12-27
Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced. PMID:22073905
Razavi, Shiva; Su, Steven; Inoue, Takanari
2014-09-19
A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top-down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers. PMID:25000210
NASA Astrophysics Data System (ADS)
Fuketa, Hiroshi; Yoshioka, Kazuaki; Fukuda, Koichi; Mori, Takahiro; Ota, Hiroyuki; Takamiya, Makoto; Sakurai, Takayasu
2015-04-01
A tunneling field effect transistor (TFET) attracts attention, because TFET circuits can achieve better energy efficiency than conventional MOSFET circuits. Although design issues in ultra low voltage logic circuits, such as the minimum operatable voltage (VDDmin), have been investigated for MOSFET’s, VDDmin for TFET’s have not been discussed. In this paper, VDDmin of TFET logic circuits is evaluated for the first time and a closed-form expression of VDDmin is derived, which indicates that the within-die threshold voltage variation (σVT) strongly affects VDDmin. In addition, since it is not clear how much the energy of the logic circuits is quantitatively reduced when both the subthreshold swing (S) and the power supply voltage are reduced, an analytical equation of the minimum energy of TFET logic circuits is also derived. From the derived equations, the design guideline is presented for the device engineers of TFET’s that σVT should be reduced as S decreases.
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-01
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956
Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls.
Currivan-Incorvia, J A; Siddiqui, S; Dutta, S; Evarts, E R; Zhang, J; Bono, D; Ross, C A; Baldo, M A
2016-01-01
Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412
Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls
Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.
2016-01-01
Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412
Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls
NASA Astrophysics Data System (ADS)
Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.
2016-01-01
Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.
Cavity-Enhanced Second-Order Nonlinear Photonic Logic Circuits
NASA Astrophysics Data System (ADS)
Trivedi, Rahul; Khankhoje, Uday K.; Majumdar, Arka
2016-05-01
A large obstacle for realizing photonic logic is the weak optical nonlinearity of available materials, which results in large power consumption. In this paper, we present the theoretical design of all-optical logic with second-order (χ(2 )) nonlinear bimodal cavities and their networks. Using semiclassical models derived from the Wigner quasiprobability distribution function, we analyze the power consumption and signal-to-noise ratio (SNR) of networks implementing an optical and gate and an optical latch. A comparison between the second- and third-order (χ(3 )) optical logic reveals that, while the χ(3 ) design outperforms the χ(2 ) design in terms of the SNR for the same input power, employing the χ(3 ) nonlinearity necessitates the use of cavities with ultrahigh-quality factors (Q ˜106) to achieve a gate power consumption comparable to that of the χ(2 ) design at significantly smaller quality factors (Q ˜104). Using realistic estimates of the χ(2 ) and χ(3 ) nonlinear susceptibilities of available materials, we show that, at achievable quality factors (Q ˜104), the χ(2 ) design is an order of magnitude more energy efficient than the corresponding χ(3 ) design.
Energy-Efficient and Secure S-Box circuit using Symmetric Pass Gate Adiabatic Logic
Kumar, Dinesh; Mohammad, Azhar; Singh, Vijay; Perumalla, Kalyan S
2016-01-01
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for lowpower portable electronic devices and Internet-of-Things (IoT) based electronic devices.
A hybrid nanomemristor/transistor logic circuit capable of self-programming.
Borghetti, Julien; Li, Zhiyong; Straznicky, Joseph; Li, Xuema; Ohlberg, Douglas A A; Wu, Wei; Stewart, Duncan R; Williams, R Stanley
2009-02-10
Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing. PMID:19171903
Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits
NASA Technical Reports Server (NTRS)
Bennett, K.; Lala, P. K.; Busaba, F.
1997-01-01
Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.
NASA Technical Reports Server (NTRS)
1975-01-01
Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.
Proposal for all-graphene monolithic logic circuits
NASA Astrophysics Data System (ADS)
Kang, Jiahao; Sarkar, Deblina; Khatami, Yasin; Banerjee, Kaustav
2013-08-01
Since the very inception of integrated circuits, dissimilar materials have been used for fabricating devices and interconnects. Typically, semiconductors are used for devices and metals are used for interconnecting them. This, however, leads to a "contact resistance" between them that degrades device and circuit performance, especially for nanoscale technologies. This letter introduces and explores an "all-graphene" device-interconnect co-design scheme, where a single 2-dimensional sheet of monolayer graphene is proposed to be monolithically patterned to form both active devices (graphene nanoribbon tunnel-field-effect-transistors) as well as interconnects in a seamless manner. Thereby, the use of external contacts is alleviated, resulting in substantial reduction in contact parasitics. Calculations based on tight-binding theory and Non-Equilibrium Green's Function (NEGF) formalism solved self-consistently with the Poisson's equation are used to analyze the intricate properties of the proposed structure. This constitutes the first NEGF simulation based demonstration that devices and interconnects can be built using the "same starting material" - graphene. Moreover, it is also shown that all-graphene circuits can surpass the static performances of the 22 nm complementary metal-oxide-semiconductor devices, including minimum operable supply voltage, static noise margin, and power consumption.
Gentili, Pier Luigi
2011-12-01
1,3-Dihydro-1,3,3-trimethyl-8'-nitro-spiro[2H-indole-2,3'-[3H]naphth[2,1-b][1,4]oxazine] (SpO) is a photochromic, acidichromic and metallochromic compound. Its chromogenic properties are characterized in acetonitrile, at room temperature. They are exploited to process both boolean and Fuzzy logic. By using HClO(4), AlCl(3) and Cu(ClO(4))(2) as chemical inputs, UV radiation as power supply, and the absorbance at specific wavelengths in the visible as optical output, SpO results in a five-states molecular switch whereby some complex boolean logic circuits are implemented. If the chemical inputs are varied in an analog manner, the solution of SpO assumes an infinite number of colours. Therefore, by choosing the RGB colour coordinates as optical outputs, the fundamental operators of the "infinite-valued" Fuzzy logic are implemented. Particularly, two Fuzzy logic systems are built upon a new defuzzification procedure imitating the way humans perceive colours. PMID:21997229
ERIC Educational Resources Information Center
Naval Education and Training Program Development Center, Pensacola, FL.
This textbook is one of a series of publications designed to provide information needed by Navy personnel whose duties require an elementary and general knowledge of the fundamental concepts of number systems, logic circuits, and Boolean algebra. Topic 1, Number Systems, describes the radix; the positional notation; the decimal, binary, octal, and…
Graphene-based non-Boolean logic circuits
NASA Astrophysics Data System (ADS)
Liu, Guanxiong; Ahsan, Sonia; Khitun, Alexander G.; Lake, Roger K.; Balandin, Alexander A.
2013-10-01
Graphene revealed a number of unique properties beneficial for electronics. However, graphene does not have an energy band-gap, which presents a serious hurdle for its applications in digital logic gates. The efforts to induce a band-gap in graphene via quantum confinement or surface functionalization have not resulted in a breakthrough. Here we show that the negative differential resistance experimentally observed in graphene field-effect transistors of "conventional" design allows for construction of viable non-Boolean computational architectures with the gapless graphene. The negative differential resistance—observed under certain biasing schemes—is an intrinsic property of graphene, resulting from its symmetric band structure. Our atomistic modeling shows that the negative differential resistance appears not only in the drift-diffusion regime but also in the ballistic regime at the nanometer-scale—although the physics changes. The obtained results present a conceptual change in graphene research and indicate an alternative route for graphene's applications in information processing.
Macia, Javier; Manzoni, Romilde; Conde, Núria; Urrios, Arturo; de Nadal, Eulàlia; Solé, Ricard; Posas, Francesc
2016-02-01
Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit's complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined. PMID:26829588
Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch.
Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi
2010-01-01
Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch. PMID:20212522
Novel Approach To Synthesis of Logic Circuits Based on Multifunctional Components
NASA Astrophysics Data System (ADS)
Crha, Adam; Růžička, Richard; Šimek, Václav
2016-01-01
Multifunctional logic continuously becomes an important way how to implement compact and cheap circuits with intrinsic reconfiguration features. Polymorphic electronics concept with its substantial technological independency opens a way to fulfil this objective through the adoption of emerging semiconductor technologies and advanced synthesis methods. The paper comes with a proposal of a novel synthesis method oriented on the exploitation of polymorphic electronics principles. Key part of it is based on Boolean divisor identification and function kernelling technique. The proposed method is evaluated with several test circuits.
Application of error correcting codes in fault-tolerant logic design for VLSI circuits
NASA Astrophysics Data System (ADS)
Lala, P. K.; Martin, H. L.
1990-05-01
It is now generally accepted that not all faults in VLSI logic can be represented by the stuck-at-0 and stuck-at-1 models used at the gate level. In order to ensure realistic modeling, faults should be considered at the transistor level, since only at the level the complete circuit structure is known. In other words, test for circuits should be derived based on possible shorts and opens at the transistor level. A stuck-open or stuck-closed transistor can be modeled by replacing the faulty transistor with an open connection or a direct short respectively between the transistor's source and drain.
How Young Children Understand Electric Circuits: Prediction, Explanation and Exploration
ERIC Educational Resources Information Center
Glauert, Esme Bridget
2009-01-01
This paper reports findings from a study of young children's views about electric circuits. Twenty-eight children aged 5 and 6 years were interviewed. They were shown examples of circuits and asked to predict whether they would work and explain why. They were then invited to try out some of the circuit examples or make circuits of their own…
ERIC Educational Resources Information Center
Houghton, Janaye Matteson; Houghton, Robert S.
Today and in the future, critical toolmaking advances will need to be made in the area of circuit design, construction, and implementation. Traditional school curriculum has sidestepped the area of tool design, especially at the elementary level. This publication addresses a calling for a new curriculum direction, based not only on the study of…
A new way of predicting cement strength -- Fuzzy logic
Gao Faliang
1997-06-01
This paper is to analyze the fuzzy logic method of predicting cement strength and to calculate some samples with fuzzy models. In order to compare, samples of them are calculated with regression method. All of results are shown in both root mean square error and scattered map.
Urrios, Arturo; de Nadal, Eulàlia; Solé, Ricard; Posas, Francesc
2016-01-01
Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit’s complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined. PMID:26829588
Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates
Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda
2012-01-01
One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039
Wang, Baojun; Barahona, Mauricio; Buck, Martin
2013-02-15
Cells perceive a wide variety of cellular and environmental signals, which are often processed combinatorially to generate particular phenotypic responses. Here, we employ both single and mixed cell type populations, pre-programmed with engineered modular cell signalling and sensing circuits, as processing units to detect and integrate multiple environmental signals. Based on an engineered modular genetic AND logic gate, we report the construction of a set of scalable synthetic microbe-based biosensors comprising exchangeable sensory, signal processing and actuation modules. These cellular biosensors were engineered using distinct signalling sensory modules to precisely identify various chemical signals, and combinations thereof, with a quantitative fluorescent output. The genetic logic gate used can function as a biological filter and an amplifier to enhance the sensing selectivity and sensitivity of cell-based biosensors. In particular, an Escherichia coli consortium-based biosensor has been constructed that can detect and integrate three environmental signals (arsenic, mercury and copper ion levels) via either its native two-component signal transduction pathways or synthetic signalling sensors derived from other bacteria in combination with a cell-cell communication module. We demonstrate how a modular cell-based biosensor can be engineered predictably using exchangeable synthetic gene circuit modules to sense and integrate multiple-input signals. This study illustrates some of the key practical design principles required for the future application of these biosensors in broad environmental and healthcare areas. PMID:22981411
Spin-based logic in semiconductors for reconfigurable large-scale circuits
NASA Astrophysics Data System (ADS)
Dery, H.; Dalal, P.; Cywiński, Ł.; Sham, L. J.
2007-05-01
Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge. Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors, spin injection into semiconductors from ferromagnetic metals and discoveries of new physical phenomena involving electron spin. Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward-spin accumulation is used as the basis of a semiconductor computer circuit. Although the giant magnetoresistance effect in metals has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow. The basic element in our design is a logic gate that consists of a semiconductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a `spin computer'. As the shrinking of conventional complementary metal-oxide-semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate.
NASA Astrophysics Data System (ADS)
Yuan, Shoucai; Liu, Yamei
2016-08-01
This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.
Bus-controlled power driver circuits for high voltages, using linear compatible I2L logic
NASA Astrophysics Data System (ADS)
Clauss, H.; Kuebler, M.
1986-04-01
A technology for monolithic integration of bipolar transistors, having breakdown voltages greater than or = to 60 V, and I2L-logic was developed. Bipolar transistors with high breakdown voltages must have thick, low doped epitaxial layers and low dc current gain, but I2L-logic with high packing density and short gate delay demands thin epitaxial layers and high dc current gain. A process with two epitaxial layers with buried layer and different intrinsic base doping for the two types of npn-transistor was developed. Bus-controlled power driver circuits for inductive loads in industrial systems were realized. Devices have 60 V maximum supply voltage and, electronically limited, 260 mA max output current.
Bi, Sai; Chen, Min; Jia, Xiaoqiang; Dong, Ying; Wang, Zonghua
2015-07-01
A hyper-branched hybridization chain reaction (HB-HCR) is presented herein, which consists of only six species that can metastably coexist until the introduction of an initiator DNA to trigger a cascade of hybridization events, leading to the self-sustained assembly of hyper-branched and nicked double-stranded DNA structures. The system can readily achieve ultrasensitive detection of target DNA. Moreover, the HB-HCR principle is successfully applied to construct three-input concatenated logic circuits with excellent specificity and extended to design a security-mimicking keypad lock system. Significantly, the HB-HCR-based keypad lock can alarm immediately if the "password" is incorrect. Overall, the proposed HB-HCR with high amplification efficiency is simple, homogeneous, fast, robust, and low-cost, and holds great promise in the development of biosensing, in the programmable assembly of DNA architectures, and in molecular logic operations. PMID:26012841
Plasmonic-multimode-interference-based logic circuit with simple phase adjustment
Ota, Masashi; Sumimura, Asahi; Fukuhara, Masashi; Ishii, Yuya; Fukuda, Mitsuo
2016-01-01
All-optical logic circuits using surface plasmon polaritons have a potential for high-speed information processing with high-density integration beyond the diffraction limit of propagating light. However, a number of logic gates that can be cascaded is limited by complicated signal phase adjustment. In this study, we demonstrate a half-adder operation with simple phase adjustment using plasmonic multimode interference (MMI) devices, composed of dielectric stripes on a metal film, which can be fabricated by a complementary metal-oxide semiconductor (MOS)-compatible process. Also, simultaneous operations of XOR and AND gates are substantiated experimentally by combining 1 × 1 MMI based phase adjusters and 2 × 2 MMI based intensity modulators. An experimental on-off ratio of at least 4.3 dB is confirmed using scanning near-field optical microscopy. The proposed structure will contribute to high-density plasmonic circuits, fabricated by complementary MOS-compatible process or printing techniques. PMID:27086694
Plasmonic-multimode-interference-based logic circuit with simple phase adjustment.
Ota, Masashi; Sumimura, Asahi; Fukuhara, Masashi; Ishii, Yuya; Fukuda, Mitsuo
2016-01-01
All-optical logic circuits using surface plasmon polaritons have a potential for high-speed information processing with high-density integration beyond the diffraction limit of propagating light. However, a number of logic gates that can be cascaded is limited by complicated signal phase adjustment. In this study, we demonstrate a half-adder operation with simple phase adjustment using plasmonic multimode interference (MMI) devices, composed of dielectric stripes on a metal film, which can be fabricated by a complementary metal-oxide semiconductor (MOS)-compatible process. Also, simultaneous operations of XOR and AND gates are substantiated experimentally by combining 1 × 1 MMI based phase adjusters and 2 × 2 MMI based intensity modulators. An experimental on-off ratio of at least 4.3 dB is confirmed using scanning near-field optical microscopy. The proposed structure will contribute to high-density plasmonic circuits, fabricated by complementary MOS-compatible process or printing techniques. PMID:27086694
Plasmonic-multimode-interference-based logic circuit with simple phase adjustment
NASA Astrophysics Data System (ADS)
Ota, Masashi; Sumimura, Asahi; Fukuhara, Masashi; Ishii, Yuya; Fukuda, Mitsuo
2016-04-01
All-optical logic circuits using surface plasmon polaritons have a potential for high-speed information processing with high-density integration beyond the diffraction limit of propagating light. However, a number of logic gates that can be cascaded is limited by complicated signal phase adjustment. In this study, we demonstrate a half-adder operation with simple phase adjustment using plasmonic multimode interference (MMI) devices, composed of dielectric stripes on a metal film, which can be fabricated by a complementary metal-oxide semiconductor (MOS)-compatible process. Also, simultaneous operations of XOR and AND gates are substantiated experimentally by combining 1 × 1 MMI based phase adjusters and 2 × 2 MMI based intensity modulators. An experimental on-off ratio of at least 4.3 dB is confirmed using scanning near-field optical microscopy. The proposed structure will contribute to high-density plasmonic circuits, fabricated by complementary MOS-compatible process or printing techniques.
NASA Technical Reports Server (NTRS)
Athale, R. A.; Lee, S. H.
1978-01-01
The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.
NASA Astrophysics Data System (ADS)
Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernandez-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph
2015-11-01
Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 μm × 10 μm using 6 NEM switches. Each NEM switch device has a footprint of 5 μm × 3 μm, an air gap of 60 μm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.
Electro-optic directed XOR logic circuits based on parallel-cascaded micro-ring resonators.
Tian, Yonghui; Zhao, Yongpeng; Chen, Wenjie; Guo, Anqi; Li, Dezhao; Zhao, Guolin; Liu, Zilong; Xiao, Huifu; Liu, Guipeng; Yang, Jianhong
2015-10-01
We report an electro-optic photonic integrated circuit which can perform the exclusive (XOR) logic operation based on two silicon parallel-cascaded microring resonators (MRRs) fabricated on the silicon-on-insulator (SOI) platform. PIN diodes embedded around MRRs are employed to achieve the carrier injection modulation. Two electrical pulse sequences regarded as two operands of operations are applied to PIN diodes to modulate two MRRs through the free carrier dispersion effect. The final operation result of two operands is output at the Output port in the form of light. The scattering matrix method is employed to establish numerical model of the device, and numerical simulator SG-framework is used to simulate the electrical characteristics of the PIN diodes. XOR operation with the speed of 100Mbps is demonstrated successfully. PMID:26480148
Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R.; Tan, Weihong
2013-01-01
Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo.1 As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy. PMID:23194304
Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R; Tan, Weihong
2012-12-26
Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo. (1) As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here, we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy. PMID:23194304
A novel logic-based approach for quantitative toxicology prediction.
Amini, Ata; Muggleton, Stephen H; Lodhi, Huma; Sternberg, Michael J E
2007-01-01
There is a pressing need for accurate in silico methods to predict the toxicity of molecules that are being introduced into the environment or are being developed into new pharmaceuticals. Predictive toxicology is in the realm of structure activity relationships (SAR), and many approaches have been used to derive such SAR. Previous work has shown that inductive logic programming (ILP) is a powerful approach that circumvents several major difficulties, such as molecular superposition, faced by some other SAR methods. The ILP approach reasons with chemical substructures within a relational framework and yields chemically understandable rules. Here, we report a general new approach, support vector inductive logic programming (SVILP), which extends the essentially qualitative ILP-based SAR to quantitative modeling. First, ILP is used to learn rules, the predictions of which are then used within a novel kernel to derive a support-vector generalization model. For a highly heterogeneous dataset of 576 molecules with known fathead minnow fish toxicity, the cross-validated correlation coefficients (R2CV) from a chemical descriptor method (CHEM) and SVILP are 0.52 and 0.66, respectively. The ILP, CHEM, and SVILP approaches correctly predict 55, 58, and 73%, respectively, of toxic molecules. In a set of 165 unseen molecules, the R2 values from the commercial software TOPKAT and SVILP are 0.26 and 0.57, respectively. In all calculations, SVILP showed significant improvements in comparison with the other methods. The SVILP approach has a major advantage in that it uses ILP automatically and consistently to derive rules, mostly novel, describing fragments that are toxicity alerts. The SVILP is a general machine-learning approach and has the potential of tackling many problems relevant to chemoinformatics including in silico drug design. PMID:17451225
Final report on LDRD project :leaky-mode VCSELs for photonic logic circuits.
Hargett, Terry W.; Hadley, G. Ronald; Serkland, Darwin Keith; Blansett, Ethan L.; Geib, Kent Martin; Sullivan, Charles Thomas; Keeler, Gordon Arthur; Bauer, Thomas; Ongstand, Andrea; Medrano, Melissa R.; Peake, Gregory Merwin; Montano, Victoria A.
2005-11-01
This report describes the research accomplishments achieved under the LDRD Project ''Leaky-mode VCSELs for photonic logic circuits''. Leaky-mode vertical-cavity surface-emitting lasers (VCSELs) offer new possibilities for integration of microcavity lasers to create optical microsystems. A leaky-mode VCSEL output-couples light laterally, in the plane of the semiconductor wafer, which allows the light to interact with adjacent lasers, modulators, and detectors on the same wafer. The fabrication of leaky-mode VCSELs based on effective index modification was proposed and demonstrated at Sandia in 1999 but was not adequately developed for use in applications. The aim of this LDRD has been to advance the design and fabrication of leaky-mode VCSELs to the point where initial applications can be attempted. In the first and second years of this LDRD we concentrated on overcoming previous difficulties in the epitaxial growth and fabrication of these advanced VCSELs. In the third year, we focused on applications of leaky-mode VCSELs, such as all-optical processing circuits based on gain quenching.
NASA Astrophysics Data System (ADS)
Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang
2016-04-01
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.
Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang
2016-01-01
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154
Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang
2016-01-01
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154
Protein secondary structure prediction using logic-based machine learning.
Muggleton, S; King, R D; Sternberg, M J
1992-10-01
Many attempts have been made to solve the problem of predicting protein secondary structure from the primary sequence but the best performance results are still disappointing. In this paper, the use of a machine learning algorithm which allows relational descriptions is shown to lead to improved performance. The Inductive Logic Programming computer program, Golem, was applied to learning secondary structure prediction rules for alpha/alpha domain type proteins. The input to the program consisted of 12 non-homologous proteins (1612 residues) of known structure, together with a background knowledge describing the chemical and physical properties of the residues. Golem learned a small set of rules that predict which residues are part of the alpha-helices--based on their positional relationships and chemical and physical properties. The rules were tested on four independent non-homologous proteins (416 residues) giving an accuracy of 81% (+/- 2%). This is an improvement, on identical data, over the previously reported result of 73% by King and Sternberg (1990, J. Mol. Biol., 216, 441-457) using the machine learning program PROMIS, and of 72% using the standard Garnier-Osguthorpe-Robson method. The best previously reported result in the literature for the alpha/alpha domain type is 76%, achieved using a neural net approach. Machine learning also has the advantage over neural network and statistical methods in producing more understandable results. PMID:1480619
NASA Astrophysics Data System (ADS)
Kitani, Asahi; Kimura, Yoshinari; Kitamura, Masatoshi; Arakawa, Yasuhiko
2016-03-01
The threshold voltage in p-channel organic thin-film transistors (TFTs) having dinaphthothienothiophene as a channel material has been investigated toward their applicability to logic circuits. Oxygen plasma treatment of the gate dielectric surface was carried out to control the threshold voltage. The threshold voltage changed in the range from -6.4 to 9.4 V, depending on plasma treatment time and the thickness of the gate dielectric. The surface charge after plasma treatment was estimated from the dependence of the threshold voltage. Operation of logic inverters consisting of TFTs with different threshold voltages was demonstrated as an application of TFTs with controlled threshold voltage.
NASA Technical Reports Server (NTRS)
Taylor, B.
1990-01-01
The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.
NASA Astrophysics Data System (ADS)
Matrosova, A. Yu.; Mitrofanov, E. V.; Akhynova, D. I.
2016-01-01
Functional reliability is one of the important properties of physical systems provided by reliability of system components, in particular, control logical components. The new approach to fully delay testable circuit design oriented to cut overheads and lengths of circuit paths has been developed. Compact representation of all PDF test pairs is reduced to keeping the corresponding generative vector pairs. The number of generative vector pairs does not exceed the doubled number of internal ROBDD nodes originating from the circuit, while the number of the circuit paths can exponentially depend on the number of these internal nodes. The algorithm of involving the PDF test pair from the proper generative vector pair is suggested. This procedure does not require essential calculations. The algorithm of deriving the generative vector pair has a polynomial complexity.
Predicting the behavior of microfluidic circuits made from discrete elements
Bhargava, Krisna C.; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah
2015-01-01
Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand. PMID:26516059
Predicting the behavior of microfluidic circuits made from discrete elements
NASA Astrophysics Data System (ADS)
Bhargava, Krisna C.; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah
2015-10-01
Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand.
Predicting the behavior of microfluidic circuits made from discrete elements.
Bhargava, Krisna C; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah
2015-01-01
Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand. PMID:26516059
Fluorescence resonance energy transfer-based molecular logic circuit using a DNA scaffold
NASA Astrophysics Data System (ADS)
Nishimura, Takahiro; Ogura, Yusuke; Tanida, Jun
2012-12-01
This paper presents a method of information processing using biomolecular input signals and fluorescence resonance energy transfer (FRET) signaling constructed on a DNA scaffold. Logic operations are achieved by encoding molecular inputs into an arrangement of fluorescence dyes using simple DNA reactions and by evaluating a logic expression using local photonic signaling that is much faster than DNA reactions. Experimental results verify the operation of a complete set of Boolean logic functions (AND, OR, NOT) and combinational logic operations using a FRET-signal cascade.
Reliable Logic Circuit Elements that Exploit Nonlinearity in the Presence of a Noise Floor
NASA Astrophysics Data System (ADS)
Murali, K.; Sinha, Sudeshna; Ditto, William L.; Bulsara, Adi R.
2009-03-01
The response of a noisy nonlinear system to deterministic input signals can be enhanced by cooperative phenomena. We show that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the noise intensity. As one increases the noise (for fixed threshold or nonlinearity), the probability of the output reflecting a NOR/OR operation increases to unity and then decreases. Changing the nonlinearity (or the thresholds) of the system changes the output into another logic operation (NAND/AND) whose probability displays analogous behavior. The interplay of nonlinearity and noise can yield logic behavior, and the emergent outcome of such systems is a logic gate. This “logical stochastic resonance” is demonstrated via an experimental realization of a two-state system with two (adjustable) thresholds.
Reliable logic circuit elements that exploit nonlinearity in the presence of a noise floor.
Murali, K; Sinha, Sudeshna; Ditto, William L; Bulsara, Adi R
2009-03-13
The response of a noisy nonlinear system to deterministic input signals can be enhanced by cooperative phenomena. We show that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the noise intensity. As one increases the noise (for fixed threshold or nonlinearity), the probability of the output reflecting a NOR/OR operation increases to unity and then decreases. Changing the nonlinearity (or the thresholds) of the system changes the output into another logic operation (NAND/AND) whose probability displays analogous behavior. The interplay of nonlinearity and noise can yield logic behavior, and the emergent outcome of such systems is a logic gate. This "logical stochastic resonance" is demonstrated via an experimental realization of a two-state system with two (adjustable) thresholds. PMID:19392115
NASA Astrophysics Data System (ADS)
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-05-01
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V‑1 sec‑1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-01-01
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-01-01
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914
NASA Astrophysics Data System (ADS)
Mitra, S.; Salman, A.; Ioannou, D. P.; Tretz, C.; Ioannou, D. E.
2004-11-01
In this paper we introduce a novel logic gate family based on Double Gate (DG) SOI MOSFETs for low voltage/low power circuits. The logic gates are based on ratioed logic with depletion-mode (i.e., intrinsically on) Symmetric DG (SDG) load transistors and inversion-mode Asymmetric DG (ADG) driver transistors. Using this technique a basic inverter was designed, with better performance compared to "classical" CMOS DG design. This technique was extended to create a complete set of basic logic gates including NOR2, NAND2 and XOR2 gates.
Predicting recycling behaviour: Comparison of a linear regression model and a fuzzy logic model.
Vesely, Stepan; Klöckner, Christian A; Dohnal, Mirko
2016-03-01
In this paper we demonstrate that fuzzy logic can provide a better tool for predicting recycling behaviour than the customarily used linear regression. To show this, we take a set of empirical data on recycling behaviour (N=664), which we randomly divide into two halves. The first half is used to estimate a linear regression model of recycling behaviour, and to develop a fuzzy logic model of recycling behaviour. As the first comparison, the fit of both models to the data included in estimation of the models (N=332) is evaluated. As the second comparison, predictive accuracy of both models for "new" cases (hold-out data not included in building the models, N=332) is assessed. In both cases, the fuzzy logic model significantly outperforms the regression model in terms of fit. To conclude, when accurate predictions of recycling and possibly other environmental behaviours are needed, fuzzy logic modelling seems to be a promising technique. PMID:26774211
Cardiopulmonary Circuit Models for Predicting Injury to the Heart
NASA Astrophysics Data System (ADS)
Ward, Richard; Wing, Sarah; Bassingthwaighte, James; Neal, Maxwell
2004-11-01
Circuit models have been used extensively in physiology to describe cardiopulmonary function. Such models are being used in the DARPA Virtual Soldier (VS) Project* to predict the response to injury or physiological stress. The most complex model consists of systemic circulation, pulmonary circulation, and a four-chamber heart sub-model. This model also includes baroreceptor feedback, airway mechanics, gas exchange, and pleural pressure influence on the circulation. As part of the VS Project, Oak Ridge National Laboratory has been evaluating various cardiopulmonary circuit models for predicting the effects of injury to the heart. We describe, from a physicist's perspective, the concept of building circuit models, discuss both unstressed and stressed models, and show how the stressed models are used to predict effects of specific wounds. *This work was supported by a grant from the DARPA, executed by the U.S. Army Medical Research and Materiel Command/TATRC Cooperative Agreement, Contract # W81XWH-04-2-0012. The submitted manuscript has been authored by the U.S. Department of Energy, Office of Science of the Oak Ridge National Laboratory, managed for the U.S. DOE by UT-Battelle, LLC, under contract No. DE-AC05-00OR22725. Accordingly, the U.S. Government retains a non-exclusive, royalty-free license to publish or reproduce the published form of this contribution, or allow others to do so, for U.S. Government purpose.
NASA Astrophysics Data System (ADS)
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-05-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V‑1 sec‑1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-01-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm(2) V(-1) sec(-)1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 10(4)), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process. PMID:27184121
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-01-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process. PMID:27184121
Fault-tolerant computer study. [logic designs for building block circuits
NASA Technical Reports Server (NTRS)
Rennels, D. A.; Avizienis, A. A.; Ercegovac, M. D.
1981-01-01
A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.
Do institutional logics predict interpretation of contract rules at the dental chair-side?
Harris, Rebecca; Brown, Stephen; Holt, Robin; Perkins, Elizabeth
2014-12-01
In quasi-markets, contracts find purchasers influencing health care providers, although problems exist where providers use personal bias and heuristics to respond to written agreements, tending towards the moral hazard of opportunism. Previous research on quasi-market contracts typically understands opportunism as fully rational, individual responses selecting maximally efficient outcomes from a set of possibilities. We take a more emotive and collective view of contracting, exploring the influence of institutional logics in relation to the opportunistic behaviour of dentists. Following earlier qualitative work where we identified four institutional logics in English general dental practice, and six dental contract areas where there was scope for opportunism; in 2013 we surveyed 924 dentists to investigate these logics and whether they had predictive purchase over dentists' chair-side behaviour. Factor analysis involving 300 responses identified four logics entwined in (often technical) behaviour: entrepreneurial commercialism, duty to staff and patients, managerialism, public good. PMID:25441320
Do institutional logics predict interpretation of contract rules at the dental chair-side?
Harris, Rebecca; Brown, Stephen; Holt, Robin; Perkins, Elizabeth
2014-01-01
In quasi-markets, contracts find purchasers influencing health care providers, although problems exist where providers use personal bias and heuristics to respond to written agreements, tending towards the moral hazard of opportunism. Previous research on quasi-market contracts typically understands opportunism as fully rational, individual responses selecting maximally efficient outcomes from a set of possibilities. We take a more emotive and collective view of contracting, exploring the influence of institutional logics in relation to the opportunistic behaviour of dentists. Following earlier qualitative work where we identified four institutional logics in English general dental practice, and six dental contract areas where there was scope for opportunism; in 2013 we surveyed 924 dentists to investigate these logics and whether they had predictive purchase over dentists' chair-side behaviour. Factor analysis involving 300 responses identified four logics entwined in (often technical) behaviour: entrepreneurial commercialism, duty to staff and patients, managerialism, public good. PMID:25441320
Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations
NASA Technical Reports Server (NTRS)
Slaughter, D. W.
1977-01-01
A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.
Morphological elucidation of basal ganglia circuits contributing reward prediction
Fujiyama, Fumino; Takahashi, Susumu; Karube, Fuyuki
2015-01-01
Electrophysiological studies in monkeys have shown that dopaminergic neurons respond to the reward prediction error. In addition, striatal neurons alter their responsiveness to cortical or thalamic inputs in response to the dopamine signal, via the mechanism of dopamine-regulated synaptic plasticity. These findings have led to the hypothesis that the striatum exhibits synaptic plasticity under the influence of the reward prediction error and conduct reinforcement learning throughout the basal ganglia circuits. The reinforcement learning model is useful; however, the mechanism by which such a process emerges in the basal ganglia needs to be anatomically explained. The actor–critic model has been previously proposed and extended by the existence of role sharing within the striatum, focusing on the striosome/matrix compartments. However, this hypothesis has been difficult to confirm morphologically, partly because of the complex structure of the striosome/matrix compartments. Here, we review recent morphological studies that elucidate the input/output organization of the striatal compartments. PMID:25698913
Morphological elucidation of basal ganglia circuits contributing reward prediction.
Fujiyama, Fumino; Takahashi, Susumu; Karube, Fuyuki
2015-01-01
Electrophysiological studies in monkeys have shown that dopaminergic neurons respond to the reward prediction error. In addition, striatal neurons alter their responsiveness to cortical or thalamic inputs in response to the dopamine signal, via the mechanism of dopamine-regulated synaptic plasticity. These findings have led to the hypothesis that the striatum exhibits synaptic plasticity under the influence of the reward prediction error and conduct reinforcement learning throughout the basal ganglia circuits. The reinforcement learning model is useful; however, the mechanism by which such a process emerges in the basal ganglia needs to be anatomically explained. The actor-critic model has been previously proposed and extended by the existence of role sharing within the striatum, focusing on the striosome/matrix compartments. However, this hypothesis has been difficult to confirm morphologically, partly because of the complex structure of the striosome/matrix compartments. Here, we review recent morphological studies that elucidate the input/output organization of the striatal compartments. PMID:25698913
All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits
Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.
2014-01-21
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.
Data-Mining-Based Coronary Heart Disease Risk Prediction Model Using Fuzzy Logic and Decision Tree
Kim, Jaekwon; Lee, Jongsik
2015-01-01
Objectives The importance of the prediction of coronary heart disease (CHD) has been recognized in Korea; however, few studies have been conducted in this area. Therefore, it is necessary to develop a method for the prediction and classification of CHD in Koreans. Methods A model for CHD prediction must be designed according to rule-based guidelines. In this study, a fuzzy logic and decision tree (classification and regression tree [CART])-driven CHD prediction model was developed for Koreans. Datasets derived from the Korean National Health and Nutrition Examination Survey VI (KNHANES-VI) were utilized to generate the proposed model. Results The rules were generated using a decision tree technique, and fuzzy logic was applied to overcome problems associated with uncertainty in CHD prediction. Conclusions The accuracy and receiver operating characteristic (ROC) curve values of the propose systems were 69.51% and 0.594, proving that the proposed methods were more efficient than other models. PMID:26279953
NASA Astrophysics Data System (ADS)
Liu, Zhe Peng; Li, Qing
2013-04-01
Due to their two-way electromechanical coupling effect, piezoelectric transducers can be used to synthesize passive vibration control schemes, e.g., RLC circuit with the integration of inductance and resistance elements that is conceptually similar to damped vibration absorber. Meanwhile, the wide usage of wireless sensors has led to the recent enthusiasm of developing piezoelectric-based energy harvesting devices that can convert ambient vibratory energy into useful electrical energy. It can be shown that the integration of circuitry elements such as resistance and inductance can benefit the energy harvesting capability. Here we explore a dual-purpose circuit that can facilitate simultaneous vibration suppression and energy harvesting. It is worth noting that the goal of vibration suppression and the goal of energy harvesting may not always complement each other. That is, the maximization of vibration suppression doesn't necessarily lead to the maximization of energy harvesting, and vice versa. In this research, we develop a fuzzy-logic based algorithm to decide the proper selection of circuitry elements to balance between the two goals. As the circuitry elements can be online tuned, this research yields an adaptive circuitry concept for the effective manipulation of system energy and vibration suppression. Comprehensive analyses are carried out to demonstrate the concept and operation.
Total Organic Carbon prediction in shale gas reservoirs using fuzzy logic
NASA Astrophysics Data System (ADS)
Ouadfeul, Sid-Ali; Aliouane, Leila
2015-04-01
Here, we suggest the use the fuzzy logic approach for the prediction of the Total Organic Carbon (TOC) from well-logs data in shale gas reservoirs, two models are used for the estimation of the TOC from well-logs data; the first one is called the Schmoker's model while the second one is called the Passey's model. Scmocker's model requires the continuous measurement of the Bulk density, in case of absence of the bulk density measurement the Schmoker's model is not able to predict the TOC. In this case we suggest the use fuzzy logic system able to predict the total organic carbon in shale gas formations. The input of the fuzzy system is the four raw well-logs data measurements corresponding to the natural gamma ray, the neutron porosity, the slowness of the primary and shear waves. The desired output is the calculated TOC using the Schmoker's model. Application to well-logs data of two horizontal wells drilled in the lower Barnett shale clearly shows the ability of the fuzzy logic approach to suggest values of the total organic carbon in case of no bulk density measurement. Keywords TOC, Schmoker's model, Fuzzy logic, shale gas, Barnett shale, prediction.
Optical flip-flops and sequential logic circuits using a liquid crystal light valve
NASA Technical Reports Server (NTRS)
Fatehi, M. T.; Collins, S. A., Jr.; Wasmundt, K. C.
1984-01-01
This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.
Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI
NASA Astrophysics Data System (ADS)
Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander
2016-03-01
In this paper, the recently proposed gate level body bias (GLBB) technique is evaluated for low voltage logic design in state-of-the-art 28 nm ultra-thin body and box (UTBB) fully-depleted silicon-on-insulator (FD-SOI) technology. The inherent benefits of the low-granularity body-bias control, provided by the GLBB approach, are emphasized by the efficiency of forward body bias (FBB) in the FD-SOI technology. In addition, the possibility to integrate PMOS and NMOS devices into a single common well configuration allows significant area reduction, as compared to an equivalent triple well implementation. Some arithmetic circuits were designed using GLBB approach and compared to their conventional CMOS and DTMOS counterparts under different running conditions at low voltage regime. Simulation results shows that, for 300 mV of supply voltage, a 4 × 4-bit GLBB Baugh Wooley multiplier allows performance improvement of about 30% and area reduction of about 35%, while maintaining low energy consumption as compared to the conventional CMOS ⧹ DTMOS solutions. Performance and energy benefits are maintained over a wide range of process-voltage-temperature (PVT) variations.
NASA Astrophysics Data System (ADS)
Lanzalaco, Felix; Pissanetzky, Sergio
2013-12-01
A recent theory of physical information based on the fundamental principles of causality and thermodynamics has proposed that a large number of observable life and intelligence signals can be described in terms of the Causal Mathematical Logic (CML), which is proposed to encode the natural principles of intelligence across any physical domain and substrate. We attempt to expound the current definition of CML, the "Action functional" as a theory in terms of its ability to possess a superior explanatory power for the current neuroscientific data we use to measure the mammalian brains "intelligence" processes at its most general biophysical level. Brain simulation projects define their success partly in terms of the emergence of "non-explicitly programmed" complex biophysical signals such as self-oscillation and spreading cortical waves. Here we propose to extend the causal theory to predict and guide the understanding of these more complex emergent "intelligence Signals". To achieve this we review whether causal logic is consistent with, can explain and predict the function of complete perceptual processes associated with intelligence. Primarily those are defined as the range of Event Related Potentials (ERP) which include their primary subcomponents; Event Related Desynchronization (ERD) and Event Related Synchronization (ERS). This approach is aiming for a universal and predictive logic for neurosimulation and AGi. The result of this investigation has produced a general "Information Engine" model from translation of the ERD and ERS. The CML algorithm run in terms of action cost predicts ERP signal contents and is consistent with the fundamental laws of thermodynamics. A working substrate independent natural information logic would be a major asset. An information theory consistent with fundamental physics can be an AGi. It can also operate within genetic information space and provides a roadmap to understand the live biophysical operation of the phenotype
NASA Technical Reports Server (NTRS)
Richardson, Albert O.
1997-01-01
This research has investigated the use of fuzzy logic, via the Matlab Fuzzy Logic Tool Box, to design optimized controller systems. The engineering system for which the controller was designed and simulate was the container crane. The fuzzy logic algorithm that was investigated was the 'predictive control' algorithm. The plant dynamics of the container crane is representative of many important systems including robotic arm movements. The container crane that was investigated had a trolley motor and hoist motor. Total distance to be traveled by the trolley was 15 meters. The obstruction height was 5 meters. Crane height was 17.8 meters. Trolley mass was 7500 kilograms. Load mass was 6450 kilograms. Maximum trolley and rope velocities were 1.25 meters per sec. and 0.3 meters per sec., respectively. The fuzzy logic approach allowed the inclusion, in the controller model, of performance indices that are more effectively defined in linguistic terms. These include 'safety' and 'cargo swaying'. Two fuzzy inference systems were implemented using the Matlab simulation package, namely the Mamdani system (which relates fuzzy input variables to fuzzy output variables), and the Sugeno system (which relates fuzzy input variables to crisp output variable). It is found that the Sugeno FIS is better suited to including aspects of those plant dynamics whose mathematical relationships can be determined.
Feasibility of using adaptive logic networks to predict compressor unit failure
Armstrong, W.W.; Chungying Chu; Thomas, M.M.
1995-12-31
In this feasibility study, an adaptive logic network (ALN) was trained to predict failures of turbine-driven compressor units using a large database of measurements. No expert knowledge about compressor systems was involved. The predictions used only the statistical properties of the measurements and the indications of failure types. A fuzzy set was used to model measurements typical of normal operation. It was constrained by a requirement imposed during ALN training, that it should have a shape similar to a Gaussian density, more precisely, that its logarithm should be convex-up. Initial results obtained using this approach to knowledge discovery in the database were encouraging.
Zhou, Jingyu; Tian, Shulin; Yang, Chenglin
2014-01-01
Few researches pay attention to prediction about analog circuits. The few methods lack the correlation with circuit analysis during extracting and calculating features so that FI (fault indicator) calculation often lack rationality, thus affecting prognostic performance. To solve the above problem, this paper proposes a novel prediction method about single components of analog circuits based on complex field modeling. Aiming at the feature that faults of single components hold the largest number in analog circuits, the method starts with circuit structure, analyzes transfer function of circuits, and implements complex field modeling. Then, by an established parameter scanning model related to complex field, it analyzes the relationship between parameter variation and degeneration of single components in the model in order to obtain a more reasonable FI feature set via calculation. According to the obtained FI feature set, it establishes a novel model about degeneration trend of analog circuits' single components. At last, it uses particle filter (PF) to update parameters for the model and predicts remaining useful performance (RUP) of analog circuits' single components. Since calculation about the FI feature set is more reasonable, accuracy of prediction is improved to some extent. Finally, the foregoing conclusions are verified by experiments. PMID:25147853
Ferrite logic reliability study
NASA Technical Reports Server (NTRS)
Baer, J. A.; Clark, C. B.
1973-01-01
Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)
Performance evaluation of cost-based vs. fuzzy-logic-based prediction approaches in PRIDE
NASA Astrophysics Data System (ADS)
Kootbally, Z.; Schlenoff, C.; Madhavan, R.; Foufou, S.
2008-04-01
PRIDE (PRediction In Dynamic Environments) is a hierarchical multi-resolutional framework for moving object prediction. PRIDE incorporates multiple prediction algorithms into a single, unifying framework. To date, we have applied this framework to predict the future location of autonomous vehicles during on-road driving. In this paper, we describe two different approaches to compute long-term predictions (on the order of seconds into the future) within PRIDE. The first is a cost-based approach that uses a discretized set of vehicle motions and costs associated with states and actions to compute probabilities of vehicle motion. The cost-based approach is the first prediction approach we have been using within PRIDE. The second is a fuzzy-logic-based approach that deals with the pervasive presence of uncertainty in the environment to negotiate complex traffic situations. Using the high-fidelity physics-based framework for the Unified System for Automation and Robot Simulation (USARSim), we will compare the performance of the two approaches in different driving situations at traffic intersections. Consequently, we will show how the two approaches complement each other and how their combination performs better than the cost-based approach only.
Valencia-Palomo, G; Rossiter, J A
2011-01-01
This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules. PMID:21056412
Discovery of Drug Synergies in Gastric Cancer Cells Predicted by Logical Modeling
Flobak, Åsmund; Baudot, Anaïs; Remy, Elisabeth; Thommesen, Liv; Thieffry, Denis; Kuiper, Martin; Lægreid, Astrid
2015-01-01
Discovery of efficient anti-cancer drug combinations is a major challenge, since experimental testing of all possible combinations is clearly impossible. Recent efforts to computationally predict drug combination responses retain this experimental search space, as model definitions typically rely on extensive drug perturbation data. We developed a dynamical model representing a cell fate decision network in the AGS gastric cancer cell line, relying on background knowledge extracted from literature and databases. We defined a set of logical equations recapitulating AGS data observed in cells in their baseline proliferative state. Using the modeling software GINsim, model reduction and simulation compression techniques were applied to cope with the vast state space of large logical models and enable simulations of pairwise applications of specific signaling inhibitory chemical substances. Our simulations predicted synergistic growth inhibitory action of five combinations from a total of 21 possible pairs. Four of the predicted synergies were confirmed in AGS cell growth real-time assays, including known effects of combined MEK-AKT or MEK-PI3K inhibitions, along with novel synergistic effects of combined TAK1-AKT or TAK1-PI3K inhibitions. Our strategy reduces the dependence on a priori drug perturbation experimentation for well-characterized signaling networks, by demonstrating that a model predictive of combinatorial drug effects can be inferred from background knowledge on unperturbed and proliferating cancer cells. Our modeling approach can thus contribute to preclinical discovery of efficient anticancer drug combinations, and thereby to development of strategies to tailor treatment to individual cancer patients. PMID:26317215
King, R.D.; Srinivasan, A.
1996-10-01
The machine learning program Progol was applied to the problem of forming the structure-activity relationship (SAR) for a set of compounds tested for carcinogenicity in rodent bioassays by the U.S. National Toxicology Program (NTP). Progol is the first inductive logic programming (ILP) algorithm to use a fully relational method for describing chemical structure in SARs, based on using atoms and their bond connectivities. Progol is well suited to forming SARs for carcinogenicity as it is designed to produce easily understandable rules (structural alerts) for sets of noncongeneric compounds. The Progol SAR method was tested by prediction of a set of compounds that have been widely predicted by other SAR methods (the compounds used in the NTP`s first round of carcinogenesis predictions). For these compounds no method (human or machine) was significantly more accurate than Progol. Progol was the most accurate method that did not use data from biological tests on rodents (however, the difference in accuracy is not significant). The Progol predictions were based solely on chemical structure and the results of tests for Salmonella mutagenicity. Using the full NTP database, the prediction accuracy of Progol was estimated to be 63% ({+-}3%) using 5-fold cross validation. A set of structural alerts for carcinogenesis was automatically generated and the chemical rationale for them investigated-these structural alerts are statistically independent of the Salmonella mutagenicity. Carcinogenicity is predicted for the compounds used in the NTP`s second round of carcinogenesis predictions. The results for prediction of carcinogenesis, taken together with the previous successful applications of predicting mutagenicity in nitroaromatic compounds, and inhibition of angiogenesis by suramin analogues, show that Progol has a role to play in understanding the SARs of cancer-related compounds. 29 refs., 2 figs., 4 tabs.
King, R D; Srinivasan, A
1996-01-01
The machine learning program Progol was applied to the problem of forming the structure-activity relationship (SAR) for a set of compounds tested for carcinogenicity in rodent bioassays by the U.S. National Toxicology Program (NTP). Progol is the first inductive logic programming (ILP) algorithm to use a fully relational method for describing chemical structure in SARs, based on using atoms and their bond connectivities. Progol is well suited to forming SARs for carcinogenicity as it is designed to produce easily understandable rules (structural alerts) for sets of noncongeneric compounds. The Progol SAR method was tested by prediction of a set of compounds that have been widely predicted by other SAR methods (the compounds used in the NTP's first round of carcinogenesis predictions). For these compounds no method (human or machine) was significantly more accurate than Progol. Progol was the most accurate method that did not use data from biological tests on rodents (however, the difference in accuracy is not significant). The Progol predictions were based solely on chemical structure and the results of tests for Salmonella mutagenicity. Using the full NTP database, the prediction accuracy of Progol was estimated to be 63% (+/- 3%) using 5-fold cross validation. A set of structural alerts for carcinogenesis was automatically generated and the chemical rationale for them investigated- these structural alerts are statistically independent of the Salmonella mutagenicity. Carcinogenicity is predicted for the compounds used in the NTP's second round of carcinogenesis predictions. The results for prediction of carcinogenesis, taken together with the previous successful applications of predicting mutagenicity in nitroaromatic compounds, and inhibition of angiogenesis by suramin analogues, show that Progol has a role to play in understanding the SARs of cancer-related compounds. PMID:8933051
NASA Technical Reports Server (NTRS)
Burns, J. L.; Choma, J., Jr.
1982-01-01
A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.
NASA Technical Reports Server (NTRS)
Jafri, Madiha J.; Ely, Jay J.; Vahala, Linda L.
2007-01-01
In this paper, neural network (NN) modeling is combined with fuzzy logic to estimate Interference Path Loss measurements on Airbus 319 and 320 airplanes. Interference patterns inside the aircraft are classified and predicted based on the locations of the doors, windows, aircraft structures and the communication/navigation system-of-concern. Modeled results are compared with measured data. Combining fuzzy logic and NN modeling is shown to improve estimates of measured data over estimates obtained with NN alone. A plan is proposed to enhance the modeling for better prediction of electromagnetic coupling problems inside aircraft.
NASA Astrophysics Data System (ADS)
Tapoglou, Evdokia; Karatzas, George P.; Trichakis, Ioannis C.; Varouchakis, Emmanouil A.
2014-05-01
The purpose of this study is to examine the use of Artificial Neural Networks (ANN) combined with kriging interpolation method, in order to simulate the hydraulic head both spatially and temporally. Initially, ANNs are used for the temporal simulation of the hydraulic head change. The results of the most appropriate ANNs, determined through a fuzzy logic system, are used as an input for the kriging algorithm where the spatial simulation is conducted. The proposed algorithm is tested in an area located across Isar River in Bayern, Germany and covers an area of approximately 7800 km2. The available data extend to a time period from 1/11/2008 to 31/10/2012 (1460 days) and include the hydraulic head at 64 wells, temperature and rainfall at 7 weather stations and surface water elevation at 5 monitoring stations. One feedforward ANN was trained for each of the 64 wells, where hydraulic head data are available, using a backpropagation algorithm. The most appropriate input parameters for each wells' ANN are determined considering their proximity to the measuring station, as well as their statistical characteristics. For the rainfall, the data for two consecutive time lags for best correlated weather station, as well as a third and fourth input from the second best correlated weather station, are used as an input. The surface water monitoring stations with the three best correlations for each well are also used in every case. Finally, the temperature for the best correlated weather station is used. Two different architectures are considered and the one with the best results is used henceforward. The output of the ANNs corresponds to the hydraulic head change per time step. These predictions are used in the kriging interpolation algorithm. However, not all 64 simulated values should be used. The appropriate neighborhood for each prediction point is constructed based not only on the distance between known and prediction points, but also on the training and testing error of
Logic programming to predict cell fate patterns and retrodict genotypes in organogenesis
Hall, Benjamin A.; Jackson, Ethan; Hajnal, Alex; Fisher, Jasmin
2014-01-01
Caenorhabditis elegans vulval development is a paradigm system for understanding cell differentiation in the process of organogenesis. Through temporal and spatial controls, the fate pattern of six cells is determined by the competition of the LET-23 and the Notch signalling pathways. Modelling cell fate determination in vulval development using state-based models, coupled with formal analysis techniques, has been established as a powerful approach in predicting the outcome of combinations of mutations. However, computing the outcomes of complex and highly concurrent models can become prohibitive. Here, we show how logic programs derived from state machines describing the differentiation of C. elegans vulval precursor cells can increase the speed of prediction by four orders of magnitude relative to previous approaches. Moreover, this increase in speed allows us to infer, or ‘retrodict’, compatible genomes from cell fate patterns. We exploit this technique to predict highly variable cell fate patterns resulting from dig-1 reduced-function mutations and let-23 mosaics. In addition to the new insights offered, we propose our technique as a platform for aiding the design and analysis of experimental data. PMID:24966232
Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki
2016-07-20
We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter. PMID:27348479
Yu, Xue; Lian, Wenjing; Zhang, Jiannan; Liu, Hongyun
2016-06-15
Herein, poly(N-isopropylacrylamide-co-N,N'-dimethylaminoethylmethacrylate) copolymer films were polymerized on electrode surface with a simple one-step method, and the enzyme horseradish peroxidase (HRP) was embedded in the films simultaneously, which were designated as P(NiPAAm-co-DMEM)-HRP. The films exhibited a reversible structure change with the external stimuli, such as pH, CO2, temperature and SO4(2-), causing the cyclic voltammetric (CV) response of electroactive K3Fe(CN)6 at the film electrodes to display the corresponding multi-stimuli sensitive ON-OFF behavior. Based on the switchable CV property of the system and the electrochemical reduction of H2O2 catalyzed by HRP in the films and mediated by Fe(CN)6(3-) in solution, a 5-input/3-output logic gate was established. To further increase the complexity of the logic system, another enzyme glucose oxidase (GOD) was added into the films, designated as P(NiPAAm-co-DMEM)-HRP-GOD. In the presence of oxygen, the oxidation of glucose in the solution was catalyzed by GOD in the films, and the produced H2O2 in situ was recognized and electrocatalytically reduced by HRP and mediated by Fe(CN)6(3-). Based on the bienzyme films, a cascaded or concatenated 4-input/3-output logic gate system was proposed. The present work combined the multi-responsive interface with bioelectrocatalysis to construct cascaded logic circuits, which might open a new avenue to develop biocomputing elements with more sophisticated functions and design novel glucose biosensors. PMID:26901460
NASA Astrophysics Data System (ADS)
Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2015-04-01
Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.
Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan
2016-02-23
We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices. PMID:26768020
Simulated Laboratory in Digital Logic.
ERIC Educational Resources Information Center
Cleaver, Thomas G.
Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…
NASA Astrophysics Data System (ADS)
Sakurai, Atsushi; Zhao, Bo; Zhang, Zhuomin M.
2014-12-01
Metamaterial thermal emitters and absorbers have been widely studied for different geometric patterns by exciting a variety of electromagnetic resonances. A resistor-inductor-capacitor (RLC) circuit model is developed to describe the magnetic resonances (i.e. magnetic polaritons) inside the structures. The RLC circuit model allows the prediction of not only the resonance frequency, but also the full width at half maximum and quality factor for various geometric patterns. The parameters predicted by the RLC model are compared with the finite-difference time-domain simulation. The magnetic field distribution and the power dissipation density profile are also used to justify the RLC circuit model. The geometric effects on the resonance characteristics are elucidated in the wire (or strip), cross, and square patterned metamaterial in the infrared region. This study will facilitate the design of metamaterial absorbers and emitters based on magnetic polaritons.
A comparative study of fuzzy logic systems approach for river discharge prediction
NASA Astrophysics Data System (ADS)
Jayawardena, A. W.; Perera, E. D. P.; Zhu, Bing; Amarasekara, J. D.; Vereivalu, V.
2014-06-01
In recent years, flood disasters resulting from extreme rainfall have been on the increase in many regions of the world. In developed countries, the usual practice of mitigating flood disasters is by structural means which can reduce infrastructural damages as well as casualties but are unaffordable in most developing countries. The alternative then is to look for non-structural means that involve, among other things, early warning systems which can reduce casualties. The basic technical components of an early warning system involves a measurable input data set that trigger floods, a measurable output data set that quantify the extent of flood and an appropriate mathematical model that transforms the input data set into a corresponding output data set. There are many types of mathematical models that can be used to transform the input data into corresponding output data. The crux of this paper is on one type of data driven mathematical models, namely the use of fuzzy logic approach. The reliability and robustness of the approach are demonstrated with daily and 6-hourly discharge predictions in 4 rivers in 3 countries having contrasting climatological, geographical and land use characteristics. The first application is for two tropical rivers in Sri Lanka using daily upstream rainfall and discharge data to predict downstream discharge with the minimum implication function type Mamdani fuzzy inference system. The second application is for another tropical river in Fiji using similar type of data with daily and 6-h time scales. Both Mamdani type fuzzy inference system with minimum and product implication functions as well as Larsen type inference systems were used. In the third application, daily upstream and tributary discharges were used to predict downstream discharges in a temperate-climate river in China using the TSK type fuzzy inference system with clustering. The methods are robust and the results obtained are within reasonable agreement with observations.
Jeon, Pyo Jin; Kim, Jin Sung; Lim, June Yeong; Cho, Youngsuk; Pezeshki, Atiye; Lee, Hee Sung; Yu, Sanghyuck; Min, Sung-Wook; Im, Seongil
2015-10-14
Two-dimensional (2D) semiconductor materials with discrete bandgap become important because of their interesting physical properties and potentials toward future nanoscale electronics. Many 2D-based field effect transistors (FETs) have thus been reported. Several attempts to fabricate 2D complementary (CMOS) logic inverters have been made too. However, those CMOS devices seldom showed the most important advantage of typical CMOS: low power consumption. Here, we adopted p-WSe2 and n-MoS2 nanosheets separately for the channels of bottom-gate-patterned FETs, to fabricate 2D dichalcogenide-based hetero-CMOS inverters on the same glass substrate. Our hetero-CMOS inverters with electrically isolated FETs demonstrate novel and superior device performances of a maximum voltage gain as ∼27, sub-nanowatt power consumption, almost ideal noise margin approaching 0.5VDD (supply voltage, VDD=5 V) with a transition voltage of 2.3 V, and ∼800 μs for switching delay. Moreover, our glass-substrate CMOS device nicely performed digital logic (NOT, OR, and AND) and push-pull circuits for organic light-emitting diode switching, directly displaying the prospective of practical applications. PMID:26399664
Electrically reconfigurable logic array
NASA Technical Reports Server (NTRS)
Agarwal, R. K.
1982-01-01
To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.
Plastic corollary discharge predicts sensory consequences of movements in a cerebellum-like circuit.
Requarth, Tim; Sawtell, Nathaniel B
2014-05-21
The capacity to predict the sensory consequences of movements is critical for sensory, motor, and cognitive function. Though it is hypothesized that internal signals related to motor commands, known as corollary discharge, serve to generate such predictions, this process remains poorly understood at the neural circuit level. Here we demonstrate that neurons in the electrosensory lobe (ELL) of weakly electric mormyrid fish generate negative images of the sensory consequences of the fish's own movements based on ascending spinal corollary discharge signals. These results generalize previous findings describing mechanisms for generating negative images of the effects of the fish's specialized electric organ discharge (EOD) and suggest that a cerebellum-like circuit endowed with associative synaptic plasticity acting on corollary discharge can solve the complex and ubiquitous problem of predicting sensory consequences of movements. PMID:24853945
Reversible logic gates on Physarum Polycephalum
Schumann, Andrew
2015-03-10
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.
Fundamentals of Digital Logic.
ERIC Educational Resources Information Center
Noell, Monica L.
This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…
NASA Astrophysics Data System (ADS)
Aliouane, Leila; Ouadfeul, Sid-Ali; Boudella, Amar
2015-04-01
The main goal of the proposed idea is to use the artificial intelligence such as the neural network and fuzzy logic to predict the pore pressure in shale gas reservoirs. Pore pressure is a very important parameter that will be used or estimation of effective stress. This last is used to resolve well-bore stability problems, failure plan identification from Mohr-Coulomb circle and sweet spots identification. Many models have been proposed to estimate the pore pressure from well-logs data; we can cite for example the equivalent depth model, the horizontal model for undercompaction called the Eaton's model…etc. All these models require a continuous measurement of the slowness of the primary wave, some thing that is not easy during well-logs data acquisition in shale gas formtions. Here, we suggest the use the fuzzy logic and the multilayer perceptron neural network to predict the pore pressure in two horizontal wells drilled in the lower Barnett shale formation. The first horizontal well is used for the training of the fuzzy set and the multilayer perecptron, the input is the natural gamma ray, the neutron porosity, the slowness of the compression and shear wave, however the desired output is the estimated pore pressure using Eaton's model. Data of another horizontal well are used for generalization. Obtained results clearly show the power of the fuzzy logic system than the multilayer perceptron neural network machine to predict the pore pressure in shale gas reservoirs. Keywords: artificial intelligence, fuzzy logic, pore pressure, multilayer perecptron, Barnett shale.
Poisson's ratio prediction through dual stimulated fuzzy logic by ACE and GA-PS
NASA Astrophysics Data System (ADS)
Bagheripour, Parisa; Asoodeh, Mojtaba
2014-08-01
Poisson's ratio is one of the most important rock mechanical parameters having significance in both planning and post analysis of wellbore operations. Laboratory measurement of this parameter covers a broad range of costs, including sidewall sampling, preservation, and laboratory tests. This study proposes an improved strategy, called dual stimulated fuzzy logic by ACE and GA-PS for determining Poisson's ratio from conventional well log data in a rapid, precise, and cost-effective way. Firstly, conventional well log data are transformed to a higher correlated data space with Poisson's ratio through the use of alternative condition expectation (ACE) algorithm. This step simplifies the convoluted space of the problem and makes it easier to solve for fuzzy logic. Subsequently, transformed conventional well log data are fed to fuzzy logic model. To ensure that optimal fuzzy model is constructed, a hybrid genetic algorithm-pattern search (GA-PS) technique is employed for extracting fuzzy clusters (or rules). This step sets fuzzy logic to its optimal performance. The propounded strategy was successfully applied to data from carbonate reservoir rocks of an Iranian Oil Field. A comparison between present model and previous models showed superiority of current study.
Predicting conversion time of circuit design file by artificial neural networks
NASA Astrophysics Data System (ADS)
Jang, Sung-Hoon; Lee, Jee-Hyong; Ahn, Byoung-Sup; Ki, Won-Tai; Choi, Ji-Hyeon; Woo, Sang-Gyun; Cho, Han-Ku
2008-03-01
GDSII is a data format of the circuit design file for producing semiconductor. GDSII is also used as a transfer format for fabricating photo mask as well. As design rules are getting smaller and RET (Resolution Enhancement Technology) is getting more complicated, the time of converting GDSII to a mask data format has been increased, which influences the period of mask production. Photo mask shops all over the world are widely using computer clusters which are connected through a network, that is, called distributed computing method, to reduce the converting time. Commonly computing resource for conversion is assigned based on the input file size. However, the result of experiments showed that the input file size was improper to predict the computing resource usage. In this paper, we propose the methodology of artificial intelligence with considering the properties of GDSII file to handle circuit design files more efficiently. The conversion time will be optimized by controlling the hardware resource for data conversion as long as the conversion time is predictable through analyzing the design data. Neural networks are used to predict the conversion time for this research. In this paper, the application of neural networks for the time prediction will be discussed and experimental results will be shown with comparing to statistical model based approaches.
Gallium Arsenide Domino Circuit
NASA Technical Reports Server (NTRS)
Yang, Long; Long, Stephen I.
1990-01-01
Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.
NASA Astrophysics Data System (ADS)
Merkle, Ralph C.; Drexler, K. Eric
1996-12-01
Helical logic is a theoretical proposal for a future computing technology using the presence or absence of individual electrons (or holes) to encode 1s and 0s. The electrons are constrained to move along helical paths, driven by a rotating electric field in which the entire circuit is immersed. The electric field remains roughly orthogonal to the major axis of the helix and confines each charge carrier to a fraction of a turn of a single helical loop, moving it like water in an Archimedean screw. Each loop could in principle hold an independent carrier, permitting high information density. One computationally universal logic operation involves two helices, one of which splits into two `descendant' helices. At the point of divergence, differences in the electrostatic potential resulting from the presence or absence of a carrier in the adjacent helix controls the direction taken by a carrier in the splitting helix. The reverse of this sequence can be used to merge two initially distinct helical paths into a single outgoing helical path without forcing a dissipative transition. Because these operations are both logically and thermodynamically reversible, energy dissipation can be reduced to extremely low levels. This is the first proposal known to the authors that combines thermodynamic reversibility with the use of single charge carriers. It is important to note that this proposal permits a single electron to switch another single electron, and does not require that many electrons be used to switch one electron. The energy dissipated per logic operation can very likely be reduced to less than 0957-4484/7/4/004/img5 at a temperature of 1 K and a speed of 10 GHz, though further analysis is required to confirm this. Irreversible operations, when required, can be easily implemented and should have a dissipation approaching the fundamental limit of 0957-4484/7/4/004/img6.
Neural logic molecular, counter-intuitive.
Egorov, Igor K
2007-09-01
A hypothesis is proposed that multiple "LOGIC" genes control Boolean logic in a neuron. Each hypothetical LOGIC gene encodes a transcription factor that regulates another LOGIC gene(s). Through transcription regulation, LOGIC genes connect into a complex circuit, such as a XOR logic gate or a two-input flip-flop logic circuit capable of retaining information. LOGIC gene duplication, mutation and recombination may result in the diversification of Boolean logic gates. Creative thinking may sometimes require counter-intuitive reasoning, rather than common sense. Such reasoning is likely to engage novel logic circuits produced by LOGIC somatic mutations. An individual's logic maturates by a mechanism of somatic hypermutation, gene conversion and recombination of LOGIC genes in precursor cells followed by selection of neurons in the brain for functional competence. In this model, a single neuron among billions in the brain may contain a unique logic circuit being the key to a hard intellectual problem. The output of a logic neuron is likely to be a neurotransmitter. This neuron is connected to other neurons in the spiking neural network. The LOGIC gene hypothesis is testable by molecular techniques. Understanding mechanisms of authentic human ingenuity may help to invent digital systems capable of creative thinking. PMID:17509937
Pass transistor implementations of multivalued logic
NASA Technical Reports Server (NTRS)
Maki, G.; Whitaker, S.
1990-01-01
A simple straight-forward Karnaugh map logic design procedure for realization of multiple-valued logic circuits is presented in this paper. Pass transistor logic gates are used to realize multiple-valued networks. This work is an extension of pass transistor implementations for binary-valued logic.
Wang, Chen; Zhao, Wu; Wang, Jie; Chen, Ling; Luo, Chun-Jing
2016-06-01
The printed circuit boards basis of electronic equipment have seen a rapid growth in recent years and played a significant role in modern life. Nowadays, the fact that electronic devices upgrade quickly necessitates a proper management of waste printed circuit boards. Non-destructive desoldering of waste printed circuit boards becomes the first and the most crucial step towards recycling electronic components. Owing to the diversity of materials and components, the separation process is difficult, which results in complex and expensive recovery of precious materials and electronic components from waste printed circuit boards. To cope with this problem, we proposed an innovative approach integrating Theory of Inventive Problem Solving (TRIZ) evolution theory and technology maturity mapping system to forecast the evolution trends of desoldering technology of waste printed circuit boards. This approach can be applied to analyse the technology evolution, as well as desoldering technology evolution, then research and development strategy and evolution laws can be recommended. As an example, the maturity of desoldering technology is analysed with a technology maturity mapping system model. What is more, desoldering methods in different stages are analysed and compared. According to the analysis, the technological evolution trends are predicted to be 'the law of energy conductivity' and 'increasing the degree of idealisation'. And the potential technology and evolutionary state of waste printed circuit boards are predicted, offering reference for future waste printed circuit boards recycling. PMID:27067430
Crespo, Isaac; Krishna, Abhimanyu; Le Béchec, Antony; del Sol, Antonio
2013-01-01
The development of new high-throughput technologies enables us to measure genome-wide transcription levels, protein abundance, metabolite concentration, etc. Nevertheless, these experimental data are often noisy and incomplete, which hinders data analysis, modeling and prediction. Here, we propose a method to predict expression values of genes involved in stable cellular phenotypes from the expression values of the remaining genes in a literature-based gene regulatory network. The consistency between predicted and known stable states from experimental data is used to guide an iterative network pruning that contextualizes the network to the biological conditions under which the expression data were obtained. Using the contextualized network and the property of network stability we predict gene expression values missing from experimental data. The prediction method assumes a Boolean model to compute steady states of networks and an evolutionary algorithm to iteratively prune the networks. The evolutionary algorithm samples the probability distribution of positive feedback loops or positive circuits and individual interactions within the subpopulation of the best-pruned networks at each iteration. The resulting expression inference is based not only on previous knowledge about local connectivity but also on a global network property (stability), providing robustness in the predictions. PMID:22941654
ECG Prediction Based on Classification via Neural Networks and Linguistic Fuzzy Logic Forecaster.
Volna, Eva; Kotyrba, Martin; Habiballa, Hashim
2015-01-01
The paper deals with ECG prediction based on neural networks classification of different types of time courses of ECG signals. The main objective is to recognise normal cycles and arrhythmias and perform further diagnosis. We proposed two detection systems that have been created with usage of neural networks. The experimental part makes it possible to load ECG signals, preprocess them, and classify them into given classes. Outputs from the classifiers carry a predictive character. All experimental results from both of the proposed classifiers are mutually compared in the conclusion. We also experimented with the new method of time series transparent prediction based on fuzzy transform with linguistic IF-THEN rules. Preliminary results show interesting results based on the unique capability of this approach bringing natural language interpretation of particular prediction, that is, the properties of time series. PMID:26221620
ECG Prediction Based on Classification via Neural Networks and Linguistic Fuzzy Logic Forecaster
Volna, Eva; Kotyrba, Martin; Habiballa, Hashim
2015-01-01
The paper deals with ECG prediction based on neural networks classification of different types of time courses of ECG signals. The main objective is to recognise normal cycles and arrhythmias and perform further diagnosis. We proposed two detection systems that have been created with usage of neural networks. The experimental part makes it possible to load ECG signals, preprocess them, and classify them into given classes. Outputs from the classifiers carry a predictive character. All experimental results from both of the proposed classifiers are mutually compared in the conclusion. We also experimented with the new method of time series transparent prediction based on fuzzy transform with linguistic IF-THEN rules. Preliminary results show interesting results based on the unique capability of this approach bringing natural language interpretation of particular prediction, that is, the properties of time series. PMID:26221620
The Use of a Predictive Habitat Model and a Fuzzy Logic Approach for Marine Management and Planning
Hattab, Tarek; Ben Rais Lasram, Frida; Albouy, Camille; Sammari, Chérif; Romdhane, Mohamed Salah; Cury, Philippe; Leprieur, Fabien; Le Loc’h, François
2013-01-01
Bottom trawl survey data are commonly used as a sampling technique to assess the spatial distribution of commercial species. However, this sampling technique does not always correctly detect a species even when it is present, and this can create significant limitations when fitting species distribution models. In this study, we aim to test the relevance of a mixed methodological approach that combines presence-only and presence-absence distribution models. We illustrate this approach using bottom trawl survey data to model the spatial distributions of 27 commercially targeted marine species. We use an environmentally- and geographically-weighted method to simulate pseudo-absence data. The species distributions are modelled using regression kriging, a technique that explicitly incorporates spatial dependence into predictions. Model outputs are then used to identify areas that met the conservation targets for the deployment of artificial anti-trawling reefs. To achieve this, we propose the use of a fuzzy logic framework that accounts for the uncertainty associated with different model predictions. For each species, the predictive accuracy of the model is classified as ‘high’. A better result is observed when a large number of occurrences are used to develop the model. The map resulting from the fuzzy overlay shows that three main areas have a high level of agreement with the conservation criteria. These results align with expert opinion, confirming the relevance of the proposed methodology in this study. PMID:24146867
Complementary transistor-transistor logic /CTTL/ - An approach to high-speed micropower logic.
NASA Technical Reports Server (NTRS)
Stehlin, R. A.; Niemann, G. W.
1972-01-01
Description of a new approach to micropower integrated circuits that is called complementary transistor-transistor logic (CTTL). This logic combines the inherent low standby power of a complementary inverter with the high speed of the TTL-type input. Results of monolithic fabricated circuits are presented. These circuits are shown to be equally adaptable to hybrid and discrete circuitry.
Vianco, P.T.; Erickson, K.L.; Hopkins, P.L.
1997-12-31
A mathematical model was developed to quantitatively describe the intermetallic compound (IMC) layer growth that takes place between a Sn-based solder and a noble metal thick film conductor material used in hybrid microcircuit (HMC) assemblies. The model combined the reaction kinetics of the solder/substrate interaction, as determined from ancillary isothermal aging experiments, with a 2-D finite element mesh that took account of the porous morphology of the thick film coating. The effect of the porous morphology on the IMC layer growth when compared to the traditional 1-D computations was significant. The previous 1-D calculations under-predicted the nominal IMC layer thickness relative to the 2-D case. The 2-D model showed greater substrate consumption by IMC growth and lesser solder consumption that was determined with the 1-D computation. The new 2-D model allows the design engineer to better predict circuit aging and hence, the reliability of HMC hardware that is placed in the field.
Electronic logic for enhanced switch reliability
Cooper, J.A.
1984-01-20
A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and fail-safe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.
Abrams, Daniel A; Chen, Tianwen; Odriozola, Paola; Cheng, Katherine M; Baker, Amanda E; Padmanabhan, Aarthi; Ryali, Srikanth; Kochalka, John; Feinstein, Carl; Menon, Vinod
2016-05-31
The human voice is a critical social cue, and listeners are extremely sensitive to the voices in their environment. One of the most salient voices in a child's life is mother's voice: Infants discriminate their mother's voice from the first days of life, and this stimulus is associated with guiding emotional and social function during development. Little is known regarding the functional circuits that are selectively engaged in children by biologically salient voices such as mother's voice or whether this brain activity is related to children's social communication abilities. We used functional MRI to measure brain activity in 24 healthy children (mean age, 10.2 y) while they attended to brief (<1 s) nonsense words produced by their biological mother and two female control voices and explored relationships between speech-evoked neural activity and social function. Compared to female control voices, mother's voice elicited greater activity in primary auditory regions in the midbrain and cortex; voice-selective superior temporal sulcus (STS); the amygdala, which is crucial for processing of affect; nucleus accumbens and orbitofrontal cortex of the reward circuit; anterior insula and cingulate of the salience network; and a subregion of fusiform gyrus associated with face perception. The strength of brain connectivity between voice-selective STS and reward, affective, salience, memory, and face-processing regions during mother's voice perception predicted social communication skills. Our findings provide a novel neurobiological template for investigation of typical social development as well as clinical disorders, such as autism, in which perception of biologically and socially salient voices may be impaired. PMID:27185915
Abrams, Daniel A.; Chen, Tianwen; Odriozola, Paola; Cheng, Katherine M.; Baker, Amanda E.; Padmanabhan, Aarthi; Ryali, Srikanth; Kochalka, John; Feinstein, Carl; Menon, Vinod
2016-01-01
The human voice is a critical social cue, and listeners are extremely sensitive to the voices in their environment. One of the most salient voices in a child’s life is mother's voice: Infants discriminate their mother’s voice from the first days of life, and this stimulus is associated with guiding emotional and social function during development. Little is known regarding the functional circuits that are selectively engaged in children by biologically salient voices such as mother’s voice or whether this brain activity is related to children’s social communication abilities. We used functional MRI to measure brain activity in 24 healthy children (mean age, 10.2 y) while they attended to brief (<1 s) nonsense words produced by their biological mother and two female control voices and explored relationships between speech-evoked neural activity and social function. Compared to female control voices, mother’s voice elicited greater activity in primary auditory regions in the midbrain and cortex; voice-selective superior temporal sulcus (STS); the amygdala, which is crucial for processing of affect; nucleus accumbens and orbitofrontal cortex of the reward circuit; anterior insula and cingulate of the salience network; and a subregion of fusiform gyrus associated with face perception. The strength of brain connectivity between voice-selective STS and reward, affective, salience, memory, and face-processing regions during mother’s voice perception predicted social communication skills. Our findings provide a novel neurobiological template for investigation of typical social development as well as clinical disorders, such as autism, in which perception of biologically and socially salient voices may be impaired. PMID:27185915
Assessment and prediction of air quality using fuzzy logic and autoregressive models
NASA Astrophysics Data System (ADS)
Carbajal-Hernández, José Juan; Sánchez-Fernández, Luis P.; Carrasco-Ochoa, Jesús A.; Martínez-Trinidad, José Fco.
2012-12-01
In recent years, artificial intelligence methods have been used for the treatment of environmental problems. This work, presents two models for assessment and prediction of air quality. First, we develop a new computational model for air quality assessment in order to evaluate toxic compounds that can harm sensitive people in urban areas, affecting their normal activities. In this model we propose to use a Sigma operator to statistically asses air quality parameters using their historical data information and determining their negative impact in air quality based on toxicity limits, frequency average and deviations of toxicological tests. We also introduce a fuzzy inference system to perform parameter classification using a reasoning process and integrating them in an air quality index describing the pollution levels in five stages: excellent, good, regular, bad and danger, respectively. The second model proposed in this work predicts air quality concentrations using an autoregressive model, providing a predicted air quality index based on the fuzzy inference system previously developed. Using data from Mexico City Atmospheric Monitoring System, we perform a comparison among air quality indices developed for environmental agencies and similar models. Our results show that our models are an appropriate tool for assessing site pollution and for providing guidance to improve contingency actions in urban areas.
NASA Astrophysics Data System (ADS)
Coops, Nicholas C.; Catling, Peter C.
2001-08-01
The identification of forest habitat, its spatial pattern and use by selected taxa is a vital step for the protection of biodiversity. The use of airborne videography and frequency distribution models based on historical habitat complexity data can provide detailed information on the spatial and temporal variation of habitat, respectively. The two techniques, however, have not been jointly applied to link the temporal variation in habitat to the spatial variation of habitat over the landscape to provide a complete historical picture of the variation of habitat quality of a forest estate. In this paper, a processing methodology is developed which allows the current spatial distribution of habitat quality to be used as a base to make retrospective predictions of the spatial extent and pattern of habitat quality over the landscape. This is achieved by projecting the spatial distribution of habitat complexity scores derived from the videography, backward in time using a combination of simple Boolean logic, estimated binomial distributions, and the use of random fluctuations to mimic natural forest dynamics that are likely to have occurred over the modeling period. The simulations provide information on the type and condition of habitat in recent history and can be linked to models predicting the abundance of a variety of common and endangered taxa.
Radiation tolerant combinational logic cell
NASA Technical Reports Server (NTRS)
Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)
2009-01-01
A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.
Superconducting flux flow digital circuits
Hietala, V.M.; Martens, J.S.; Zipperian, T.E.
1995-02-14
A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.
Superconducting flux flow digital circuits
Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.
1995-01-01
A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.
Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices.
Vanhoestenberghe, A; Donaldson, N
2013-06-01
Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants. PMID:23685410
New Approach on Logic Application of Ferroelectric Random Access Memory Technology
NASA Astrophysics Data System (ADS)
Takayama, Masao; Koyama, Shinzo; Nozawa, Hiroshi
2002-11-01
In this paper, a new approach is described to solve some problems that occur when ferroelectric random access memory (FeRAM) is applied to logic circuits, particularly RSA cryptography. Application of a programmable switch device to RSA-based cryptography processing circuits was explored. RSA-based cryptography processing circuits have been designed as code conversion circuits. The capacity of the code conversion programmable AND gate and FeRAM and the translation rate have been investigated as a function of bit length. As a result, a problem of huge capacity at the practical bit length can be predicted theoretically. To solve this problem, we propose a new scheme for circuits and a new algorithm of logic operation using the binomial theorem.
Albert, Réka; Thakar, Juilee
2014-01-01
The biomolecules inside or near cells form a complex interacting system. Cellular phenotypes and behaviors arise from the totality of interactions among the components of this system. A fruitful way of modeling interacting biomolecular systems is by network-based dynamic models that characterize each component by a state variable, and describe the change in the state variables due to the interactions in the system. Dynamic models can capture the stable state patterns of this interacting system and can connect them to different cell fates or behaviors. A Boolean or logic model characterizes each biomolecule by a binary state variable that relates the abundance of that molecule to a threshold abundance necessary for downstream processes. The regulation of this state variable is described in a parameter free manner, making Boolean modeling a practical choice for systems whose kinetic parameters have not been determined. Boolean models integrate the body of knowledge regarding the components and interactions of biomolecular systems, and capture the system's dynamic repertoire, for example the existence of multiple cell fates. These models were used for a variety of systems and led to important insights and predictions. Boolean models serve as an efficient exploratory model, a guide for follow-up experiments, and as a foundation for more quantitative models. PMID:25269159
Implementing Exclusive-OR Logic
NASA Technical Reports Server (NTRS)
Hough, M. E.
1983-01-01
Two integrated circuits, BCD-to-decimal decoder and four-input NAND gate, form basic four, input XOR circuit. Multiple-input exclusive-OR logic is implemented by combining several basic elements. 16-input XOR gate is assembled from five NAND gates and five decoders. Same principle extended to handle more inputs.
A Formalized Design Process for Bacterial Consortia That Perform Logic Computing
Sun, Rui; Xi, Jingyi; Wen, Dingqiao; Feng, Jingchen; Chen, Yiwei; Qin, Xiao; Ma, Yanrong; Luo, Wenhan; Deng, Linna; Lin, Hanchi; Yu, Ruofan; Ouyang, Qi
2013-01-01
The concept of microbial consortia is of great attractiveness in synthetic biology. Despite of all its benefits, however, there are still problems remaining for large-scaled multicellular gene circuits, for example, how to reliably design and distribute the circuits in microbial consortia with limited number of well-behaved genetic modules and wiring quorum-sensing molecules. To manage such problem, here we propose a formalized design process: (i) determine the basic logic units (AND, OR and NOT gates) based on mathematical and biological considerations; (ii) establish rules to search and distribute simplest logic design; (iii) assemble assigned basic logic units in each logic operating cell; and (iv) fine-tune the circuiting interface between logic operators. We in silico analyzed gene circuits with inputs ranging from two to four, comparing our method with the pre-existing ones. Results showed that this formalized design process is more feasible concerning numbers of cells required. Furthermore, as a proof of principle, an Escherichia coli consortium that performs XOR function, a typical complex computing operation, was designed. The construction and characterization of logic operators is independent of “wiring” and provides predictive information for fine-tuning. This formalized design process provides guidance for the design of microbial consortia that perform distributed biological computation. PMID:23468999
Electronics. Module 3: Digital Logic Application. Instructor's Guide.
ERIC Educational Resources Information Center
Carter, Ed; Murphy, Mark
This guide contains instructor's materials for a 10-unit secondary school course on digital logic application. The units are introduction to digital, logic gates, digital integrated circuits, combination logic, flip-flops, counters and shift registers, encoders and decoders, arithmetic circuits, memory, and analog/digital and digital/analog…
Benchmarking emerging logic devices
NASA Astrophysics Data System (ADS)
Nikonov, Dmitri
2014-03-01
As complementary metal-oxide-semiconductor field-effect transistors (CMOS FET) are being scaled to ever smaller sizes by the semiconductor industry, the demand is growing for emerging logic devices to supplement CMOS in various special functions. Research directions and concepts of such devices are overviewed. They include tunneling, graphene based, spintronic devices etc. The methodology to estimate future performance of emerging (beyond CMOS) devices and simple logic circuits based on them is explained. Results of benchmarking are used to identify more promising concepts and to map pathways for improvement of beyond CMOS computing.
NASA Technical Reports Server (NTRS)
Agarwal, R. K.
1983-01-01
The source code for the SPICE 2 program was deblocked in order to isolate and compile the subroutine in an effort to provide a software simulation of discrete and combinatorial electronic components. Incompatibilities between the UNIVAC 1180 FORTRAN and the Sigma V CP-V FORTRAN 4 were resolved. The SPICE 2 model is to be used to determine gate and fan-out delays, logic state conditions, and signal race conditions for transistor array elements and circuit logic to be patterned in the (SPI) 7101 CMOS silicon gate semicustom array. The simulator is to be operable from the CP-V time sharing terminals.
The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations
NASA Astrophysics Data System (ADS)
Lee, Junwoo; Suh, Dong Ik; Park, Wanjun
2015-05-01
The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.
Turkdogan-Aydinol, F Ilter; Yetilmezsoy, Kaan
2010-10-15
A MIMO (multiple inputs and multiple outputs) fuzzy-logic-based model was developed to predict biogas and methane production rates in a pilot-scale 90-L mesophilic up-flow anaerobic sludge blanket (UASB) reactor treating molasses wastewater. Five input variables such as volumetric organic loading rate (OLR), volumetric total chemical oxygen demand (TCOD) removal rate (R(V)), influent alkalinity, influent pH and effluent pH were fuzzified by the use of an artificial intelligence-based approach. Trapezoidal membership functions with eight levels were conducted for the fuzzy subsets, and a Mamdani-type fuzzy inference system was used to implement a total of 134 rules in the IF-THEN format. The product (prod) and the centre of gravity (COG, centroid) methods were employed as the inference operator and defuzzification methods, respectively. Fuzzy-logic predicted results were compared with the outputs of two exponential non-linear regression models derived in this study. The UASB reactor showed a remarkable performance on the treatment of molasses wastewater, with an average TCOD removal efficiency of 93 (+/-3)% and an average volumetric TCOD removal rate of 6.87 (+/-3.93) kg TCOD(removed)/m(3)-day, respectively. Findings of this study clearly indicated that, compared to non-linear regression models, the proposed MIMO fuzzy-logic-based model produced smaller deviations and exhibited a superior predictive performance on forecasting of both biogas and methane production rates with satisfactory determination coefficients over 0.98. PMID:20609515
NASA Astrophysics Data System (ADS)
Zhang, Chao; Santhanagopalan, Shriram; Sprague, Michael A.; Pesaran, Ahmad A.
2015-09-01
In order to better understand the behavior of lithium-ion batteries under mechanical abuse, a coupled modeling methodology encompassing the mechanical, electrical and thermal response is presented for predicting short-circuit under external crush. The combined mechanical-electrical-thermal response is simulated in a commercial finite element software LS-DYNA® using a representative-sandwich finite-element model, where electrical-thermal modeling is conducted after an instantaneous mechanical crush. The model includes an explicit representation of each individual component such as the active material, current collector, separator, etc., and predicts their mechanical deformation under quasi-static indentation. Model predictions show good agreement with experiments: the fracture of the battery structure under an indentation test is accurately predicted. The electrical-thermal simulation predicts the current density and temperature distribution in a reasonable manner. Whereas previously reported models consider the mechanical response exclusively, we use the electrical contact between active materials following the failure of the separator as a criterion for short-circuit. These results are used to build a lumped representative sandwich model that is computationally efficient and captures behavior at the cell level without resolving the individual layers.
Magnetic Circuit Model of PM Motor-Generator to Predict Radial Forces
NASA Technical Reports Server (NTRS)
McLallin, Kerry (Technical Monitor); Kascak, Peter E.; Dever, Timothy P.; Jansen, Ralph H.
2004-01-01
A magnetic circuit model is developed for a PM motor for flywheel applications. A sample motor is designed and modeled. Motor configuration and selection of materials is discussed, and the choice of winding configuration is described. A magnetic circuit model is described, which includes the stator back iron, rotor yoke, permanent magnets, air gaps and the stator teeth. Iterative solution of this model yields flux linkages, back EMF, torque, power, and radial force at the rotor caused by eccentricity. Calculated radial forces are then used to determine motor negative stiffness.
NASA Technical Reports Server (NTRS)
1972-01-01
Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.
Flexible programmable logic module
Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.
2001-01-01
The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.
Introducing Exclusion Logic as a Deontic Logic
NASA Astrophysics Data System (ADS)
Evans, Richard
This paper introduces Exclusion Logic - a simple modal logic without negation or disjunction. We show that this logic has an efficient decision procedure. We describe how Exclusion Logic can be used as a deontic logic. We compare this deontic logic with Standard Deontic Logic and with more syntactically restricted logics.
NASA Astrophysics Data System (ADS)
Xavier, Marcelo A.; Trimboli, M. Scott
2015-07-01
This paper introduces a novel application of model predictive control (MPC) to cell-level charging of a lithium-ion battery utilizing an equivalent circuit model of battery dynamics. The approach employs a modified form of the MPC algorithm that caters for direct feed-though signals in order to model near-instantaneous battery ohmic resistance. The implementation utilizes a 2nd-order equivalent circuit discrete-time state-space model based on actual cell parameters; the control methodology is used to compute a fast charging profile that respects input, output, and state constraints. Results show that MPC is well-suited to the dynamics of the battery control problem and further suggest significant performance improvements might be achieved by extending the result to electrochemical models.
Xavier, MA; Trimboli, MS
2015-07-01
This paper introduces a novel application of model predictive control (MPC) to cell-level charging of a lithium-ion battery utilizing an equivalent circuit model of battery dynamics. The approach employs a modified form of the MPC algorithm that caters for direct feed-though signals in order to model near-instantaneous battery ohmic resistance. The implementation utilizes a 2nd-order equivalent circuit discrete-time state-space model based on actual cell parameters; the control methodology is used to compute a fast charging profile that respects input, output, and state constraints. Results show that MPC is well-suited to the dynamics of the battery control problem and further suggest significant performance improvements might be achieved by extending the result to electrochemical models. (C) 2015 Elsevier B.V. All rights reserved.
Ciaccio, Edward J; Ashikaga, Hiroshi; Kaba, Riyaz A; Cervantes, Daniel; Hopenfeld, Bruce; Wit, Andrew L; Peters, Nicholas S; McVeigh, Elliot R; Garan, Hasan; Coromilas, James
2008-01-01
Background Infarct border zone (IBZ) geometry likely affects inducibility and characteristics of postinfarction reentrant ventricular tachycardia, but the connection has not been established. Objective To determine characteristics of post infarction ventricular tachycardia in the IBZ. Methods A geometric model describing the relationship between IBZ geometry and wavefront propagation in reentrant circuits was developed. Based on the formulation, slow conduction and block was expected to coincide with areas where IBZ thickness (T) is minimal and the local spatial gradient in thickness (ΔT) is maximal, so that the degree of wavefront curvature ρ ∝ ΔT/T is maximal. Regions of fastest conduction velocity were predicted to coincide with areas of minimum ΔT. In seven arrhythmogenic postinfarction canine heart experiments, tachycardia was induced by programmed stimulation, and activation maps were constructed from multichannel recordings. IBZ thickness was measured in excised hearts from histologic analysis or magnetic resonance imaging. Reentrant circuit properties were predicted from IBZ geometry and compared with ventricular activation maps following tachycardia induction. Results Mean IBZ thickness was 231±140µm at the reentry isthmus and 1440±770µm in the outer pathway (p<0.001). Mean curvature ρ was 1.63±0.45mm−1 at functional block line locations, 0.71±0.18mm−1 at isthmus entrance-exit points, and 0.33±0.13mm−1 in the outer reentrant circuit pathway. The mean conduction velocity about the circuit during reentrant tachycardia was 0.32±0.04mm/ms at entrance-exit points, 0.42±0.13mm/ms for the entire outer pathway, and 0.64±0.16mm/ms at outer pathway regions with minimum ΔT. Model sensitivity and specificity to detect isthmus location was 75.0±5.7% and 97.2±0.7%. Conclusions Reentrant circuit features as determined by activation mapping can be predicted on the basis of IBZ geometrical relationships. PMID:17675078
Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch.
Gao, Shuang; Zeng, Fei; Wang, Minjuan; Wang, Guangyue; Song, Cheng; Pan, Feng
2015-01-01
The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods-in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits-are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage. PMID:26486231
Zadeh, L.A.
1988-01-01
The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived. 7 references.
NASA Technical Reports Server (NTRS)
Le Balleur, J. C.
1988-01-01
The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.
MLS, a magnetic logic simulator for magnetic bubble logic design
NASA Astrophysics Data System (ADS)
Kinsman, Thomas B.; Cendes, Zoltan J.
1987-04-01
A computer program that simulates the logic functions of magnetic bubble devices has been developed. The program uses a color graphics screen to display the locations of bubbles on a chip during operation. It complements the simulator previously developed for modeling bubble devices on the gate level [Smith et al., IEEE Trans. Magn. MAG-19, 1835 (1983); Smith and Kryder, ibid. MAG-21, 1779 (1985)]. This new tool simplifies the design and testing of bubble logic devices, and facilitates the development of complicated LSI bubble circuits. The program operation is demonstrated with the design of an in-stream faulty loop compensator using bubble logic.
Logical error rate in the Pauli twirling approximation
Katabarwa, Amara; Geller, Michael R.
2015-01-01
The performance of error correction protocols are necessary for understanding the operation of potential quantum computers, but this requires physical error models that can be simulated efficiently with classical computers. The Gottesmann-Knill theorem guarantees a class of such error models. Of these, one of the simplest is the Pauli twirling approximation (PTA), which is obtained by twirling an arbitrary completely positive error channel over the Pauli basis, resulting in a Pauli channel. In this work, we test the PTA’s accuracy at predicting the logical error rate by simulating the 5-qubit code using a 9-qubit circuit with realistic decoherence and unitary gate errors. We find evidence for good agreement with exact simulation, with the PTA overestimating the logical error rate by a factor of 2 to 3. Our results suggest that the PTA is a reliable predictor of the logical error rate, at least for low-distance codes. PMID:26419417
ERIC Educational Resources Information Center
Dyrud, Marilyn A.
To make introducing logic to college students in speech and expository writing classes more interesting, letters to the editor can be used to teach logical fallacies. Letters to the editor are particularly useful because they give students a sense of the community they live in (issues, concerns, and the spectrum of opinion), they are easily…
A bit serial sequential circuit
NASA Technical Reports Server (NTRS)
Hu, S.; Whitaker, S.
1990-01-01
Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.
NASA Astrophysics Data System (ADS)
Kaul, Richard; Adkins, Kenneth; Bibyk, Steven
The hardware and algorithms used to vector quantize (VQ) predicted pixel intensity differences for real-time video compression are described. The hardware is designed for rapid vector quantization performance, which entails the development of application-specific associative memory circuits. A modified DPCM algorithm is originally examined to determine how neural circuitry could enhance its operation. It was determined that quantization and encoding could be improved by consolidating these two functions into one, and by increasing the amount of information (i.e. number of pixels) quantized at a time. The result is a predictive scheme that vector quantizes differential values. Some of the disadvantages of VQ algorithms are solved using associative memories. The video compression algorithm and the associative memory design are described.
Xu, Xiaolun; Li, Yongqian; Wang, Binbin; Zhou, Zili
2015-10-01
The resonance characteristics of plasmonic metamaterials absorbers (PMAs) are strongly dependent on geometric parameters. A resistor-inductor-capacitor (RLC) circuit model has been extended to predict the resonance wavelengths and the bandwidths of multiple magnetic polaritons modes in PMAs. For a typical metallic-dielectric-metallic structure absorber working in the infrared region, the developed model describes the correlation between the resonance characteristics and the dimensional sizes. In particular, the RLC model is suitable for not only the fundamental resonance mode, but also for the second- and third-order resonance modes. The prediction of the resonance characteristics agrees fairly well with those calculated by the finite-difference time-domain simulation and the experimental results. The developed RLC model enables the facilitation of designing multi-band PMAs for infrared radiation detectors and thermal emitters. PMID:26421549
All-optical symmetric ternary logic gate
NASA Astrophysics Data System (ADS)
Chattopadhyay, Tanay
2010-09-01
Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.
Linnman, Clas; Zeidan, Mohamed A.; Furtak, Sharon C.; Pitman, Roger K.; Quirk, Gregory J.; Milad, Mohammed R.
2014-01-01
Objective Individual differences in ability to control fear have been linked to activation of dorsal anterior cingulate cortex, ventromedial prefrontal cortex, and amygdala. This study investigated whether functional variance in this network can be predicted by resting metabolism in these same regions. Methods Healthy subject volunteers were studied with positron emission tomography using [18F]-deoxyglucose to measure resting brain metabolism. This was followed by a two-day fear conditioning and extinction training paradigm in a functional magnetic resonance imaging scanner to measure brain activation during fear extinction and its recall. Skin conductance response was used to index conditioned responding. Resting metabolism in amygdala, dorsal anterior cingulate cortex and ventromedial prefrontal cortex were used to predict responses during fear extinction and extinction recall. Results During extinction training, resting amygdala metabolism positively predicted ventromedial prefrontal cortex, and negatively predicted dorsal anterior cingulate cortex, activation. In contrast, during extinction recall, resting amygdala metabolism negatively predicted ventromedial prefrontal cortex, and positively predicted dorsal anterior cingulate cortex, activation. Resting dorsal anterior cingulate cortex metabolism predicted fear expression (skin conductance response) during extinction recall. Conclusions Brain metabolism at rest predicts neuronal reactivity and skin conductance changes associated with recall of the fear extinction memory. PMID:22318762
NASA Astrophysics Data System (ADS)
Baader, Franz
Description Logics (DLs) are a well-investigated family of logic-based knowledge representation formalisms, which can be used to represent the conceptual knowledge of an application domain in a structured and formally well-understood way. They are employed in various application domains, such as natural language processing, configuration, and databases, but their most notable success so far is the adoption of the DL-based language OWL as standard ontology language for the semantic web.
Miniaturization of magnetic logic circuitry
NASA Technical Reports Server (NTRS)
Baba, P. D.
1969-01-01
Magnetic logic circuit design features two ferrite materials, with different formulation and magnetic characteristics, which are bonded into a continuous structure by preparing the materials as a slurry and using the doctor blade method to form flexible ferrite sheets. After firing, the sintering process was continuous across the bond.
Electronic design with integrated circuits
NASA Astrophysics Data System (ADS)
Comer, D. J.
The book is concerned with the application of integrated circuits and presents the material actually needed by the system designer to do an effective job. The operational amplifier (op amp) is discussed, taking into account the electronic amplifier, the basic op amp, the practical op amp, analog applications, and digital applications. Digital components are considered along with combinational logic, digital subsystems, the microprocessor, special circuits, communications, and integrated circuit building blocks. Attention is given to logic gates, logic families, multivibrators, the digital computer, digital methods, communicating with a computer, computer organization, register and timing circuits for data transfer, arithmetic circuits, memories, the microprocessor chip, the control unit, communicating with the microprocessor, examples of microprocessor architecture, programming a microprocessor, the voltage-controlled oscillator, the phase-locked loop, analog-to-digital conversion, amplitude modulation, frequency modulation, pulse and digital transmission, the semiconductor diode, the bipolar transistor, and the field-effect transistor.
Avoidant symptoms in PTSD predict fear circuit activation during multimodal fear extinction
Sripada, Rebecca K.; Garfinkel, Sarah N.; Liberzon, Israel
2013-01-01
Convergent evidence suggests that individuals with posttraumatic stress disorder (PTSD) exhibit exaggerated avoidance behaviors as well as abnormalities in Pavlonian fear conditioning. However, the link between the two features of this disorder is not well understood. In order to probe the brain basis of aberrant extinction learning in PTSD, we administered a multimodal classical fear conditioning/extinction paradigm that incorporated affectively relevant information from two sensory channels (visual and tactile) while participants underwent fMRI scanning. The sample consisted of fifteen OEF/OIF veterans with PTSD. In response to conditioned cues and contextual information, greater avoidance symptomatology was associated with greater activation in amygdala, hippocampus, vmPFC, dmPFC, and insula, during both fear acquisition and fear extinction. Heightened responses to previously conditioned stimuli in individuals with more severe PTSD could indicate a deficiency in safety learning, consistent with PTSD symptomatology. The close link between avoidance symptoms and fear circuit activation suggests that this symptom cluster may be a key component of fear extinction deficits in PTSD and/or may be particularly amenable to change through extinction-based therapies. PMID:24146643
Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch
Gao, Shuang; Zeng, Fei; Wang, Minjuan; Wang, Guangyue; Song, Cheng; Pan, Feng
2015-01-01
The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods—in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits—are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage. PMID:26486231
Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch
NASA Astrophysics Data System (ADS)
Gao, Shuang; Zeng, Fei; Wang, Minjuan; Wang, Guangyue; Song, Cheng; Pan, Feng
2015-10-01
The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods—in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits—are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage.
Tan, Li Hai; Chen, Lin; Yip, Virginia; Chan, Alice H. D.; Yang, Jing; Gao, Jia-Hong; Siok, Wai Ting
2011-01-01
How second language (L2) learning is achieved in the human brain remains one of the fundamental questions of neuroscience and linguistics. Previous neuroimaging studies with bilinguals have consistently shown overlapping cortical organization of the native language (L1) and L2, leading to a prediction that a common neurobiological marker may be responsible for the development of the two languages. Here, by using functional MRI, we show that later skills to read in L2 are predicted by the activity level of the fusiform–caudate circuit in the left hemisphere, which nonetheless is not predictive of the ability to read in the native language. We scanned 10-y-old children while they performed a lexical decision task on L2 (and L1) stimuli. The subjects’ written language (reading) skills were behaviorally assessed twice, the first time just before we performed the fMRI scan (time 1 reading) and the second time 1 y later (time 2 reading). A whole-brain based analysis revealed that activity levels in left caudate and left fusiform gyrus correlated with L2 literacy skills at time 1. After controlling for the effects of time 1 reading and nonverbal IQ, or the effect of in-scanner lexical performance, the development in L2 literacy skills (time 2 reading) was also predicted by activity in left caudate and fusiform regions that are thought to mediate language control functions and resolve competition arising from L1 during L2 learning. Our findings suggest that the activity level of left caudate and fusiform regions serves as an important neurobiological marker for predicting accomplishment in reading skills in a new language. PMID:21262807
Nanowire NMOS Logic Inverter Characterization.
Hashim, Yasir
2016-06-01
This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly. PMID:27427653
Adaptive parallel logic networks
NASA Technical Reports Server (NTRS)
Martinez, Tony R.; Vidal, Jacques J.
1988-01-01
Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.
Back to basics: Making predictions in the orbitofrontal-amygdala circuit.
Sharpe, Melissa J; Schoenbaum, Geoffrey
2016-05-01
Underlying many complex behaviors are simple learned associations that allow humans and animals to anticipate the consequences of their actions. The orbitofrontal cortex and basolateral amygdala are two regions which are crucial to this process. In this review, we go back to basics and discuss the literature implicating both these regions in simple paradigms requiring the development of associations between stimuli and the motivationally-significant outcomes they predict. Much of the functional research surrounding this ability has suggested that the orbitofrontal cortex and basolateral amygdala play very similar roles in making these predictions. However, electrophysiological data demonstrates critical differences in the way neurons in these regions respond to predictive cues, revealing a difference in their functional role. On the basis of these data and theories that have come before, we propose that the basolateral amygdala is integral to updating information about cue-outcome contingencies whereas the orbitofrontal cortex is critical to forming a wider network of past and present associations that are called upon by the basolateral amygdala to benefit future learning episodes. The tendency for orbitofrontal neurons to encode past and present contingencies in distinct neuronal populations may facilitate its role in the formation of complex, high-dimensional state-specific associations. PMID:27112314
A verification logic representation of indeterministic signal states
NASA Technical Reports Server (NTRS)
Gambles, J. W.; Windley, P. J.
1991-01-01
The integration of modern CAD tools with formal verification environments require translation from hardware description language to verification logic. A signal representation including both unknown state and a degree of strength indeterminacy is essential for the correct modeling of many VLSI circuit designs. A higher-order logic theory of indeterministic logic signals is presented.
Dynamic Divisive Normalization Predicts Time-Varying Value Coding in Decision-Related Circuits
LoFaro, Thomas; Webb, Ryan; Glimcher, Paul W.
2014-01-01
Normalization is a widespread neural computation, mediating divisive gain control in sensory processing and implementing a context-dependent value code in decision-related frontal and parietal cortices. Although decision-making is a dynamic process with complex temporal characteristics, most models of normalization are time-independent and little is known about the dynamic interaction of normalization and choice. Here, we show that a simple differential equation model of normalization explains the characteristic phasic-sustained pattern of cortical decision activity and predicts specific normalization dynamics: value coding during initial transients, time-varying value modulation, and delayed onset of contextual information. Empirically, we observe these predicted dynamics in saccade-related neurons in monkey lateral intraparietal cortex. Furthermore, such models naturally incorporate a time-weighted average of past activity, implementing an intrinsic reference-dependence in value coding. These results suggest that a single network mechanism can explain both transient and sustained decision activity, emphasizing the importance of a dynamic view of normalization in neural coding. PMID:25429145
Dynamic divisive normalization predicts time-varying value coding in decision-related circuits.
Louie, Kenway; LoFaro, Thomas; Webb, Ryan; Glimcher, Paul W
2014-11-26
Normalization is a widespread neural computation, mediating divisive gain control in sensory processing and implementing a context-dependent value code in decision-related frontal and parietal cortices. Although decision-making is a dynamic process with complex temporal characteristics, most models of normalization are time-independent and little is known about the dynamic interaction of normalization and choice. Here, we show that a simple differential equation model of normalization explains the characteristic phasic-sustained pattern of cortical decision activity and predicts specific normalization dynamics: value coding during initial transients, time-varying value modulation, and delayed onset of contextual information. Empirically, we observe these predicted dynamics in saccade-related neurons in monkey lateral intraparietal cortex. Furthermore, such models naturally incorporate a time-weighted average of past activity, implementing an intrinsic reference-dependence in value coding. These results suggest that a single network mechanism can explain both transient and sustained decision activity, emphasizing the importance of a dynamic view of normalization in neural coding. PMID:25429145
Zhi, Shuai; Li, Qiaozhi; Yasui, Yutaka; Banting, Graham; Edge, Thomas A; Topp, Edward; McAllister, Tim A; Neumann, Norman F
2016-10-01
Several studies have demonstrated that E. coli appears to display some level of host adaptation and specificity. Recent studies in our laboratory support these findings as determined by logic regression modeling of single nucleotide polymorphisms (SNP) in intergenic regions (ITGRs). We sought to determine the degree of host-specific information encoded in various ITGRs across a library of animal E. coli isolates using both whole genome analysis and a targeted ITGR sequencing approach. Our findings demonstrated that ITGRs across the genome encode various degrees of host-specific information. Incorporating multiple ITGRs (i.e., concatenation) into logic regression model building resulted in greater host-specificity and sensitivity outcomes in biomarkers, but the overall level of polymorphism in an ITGR did not correlate with the degree of host-specificity encoded in the ITGR. This suggests that distinct SNPs in ITGRs may be more important in defining host-specificity than overall sequence variation, explaining why traditional unsupervised learning phylogenetic approaches may be less informative in terms of revealing host-specific information encoded in DNA sequence. In silico analysis of 80 candidate ITGRs from publically available E. coli genomes was performed as a tool for discovering highly host-specific ITGRs. In one ITGR (ydeR-yedS) we identified a SNP biomarker that was 98% specific for cattle and for which 92% of all E. coli isolates originating from cattle carried this unique biomarker. In the case of humans, a host-specific biomarker (98% specificity) was identified in the concatenated ITGR sequences of rcsD-ompC, ydeR-yedS, and rclR-ykgE, and for which 78% of E. coli originating from humans carried this biomarker. Interestingly, human-specific biomarkers were dominant in ITGRs regulating antibiotic resistance, whereas in cattle host-specific biomarkers were found in ITGRs involved in stress regulation. These data suggest that evolution towards host
Sequential circuit design for radiation hardened multiple voltage integrated circuits
Clark, Lawrence T.; McIver, III, John K.
2009-11-24
The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.
NASA Astrophysics Data System (ADS)
Gentili, Pier Luigi; Gotoda, Hiroshi; Dolnik, Milos; Epstein, Irving R.
2015-01-01
Forecasting of aperiodic time series is a compelling challenge for science. In this work, we analyze aperiodic spectrophotometric data, proportional to the concentrations of two forms of a thermoreversible photochromic spiro-oxazine, that are generated when a cuvette containing a solution of the spiro-oxazine undergoes photoreaction and convection due to localized ultraviolet illumination. We construct the phase space for the system using Takens' theorem and we calculate the Lyapunov exponents and the correlation dimensions to ascertain the chaotic character of the time series. Finally, we predict the time series using three distinct methods: a feed-forward neural network, fuzzy logic, and a local nonlinear predictor. We compare the performances of these three methods.
Al-Kasasbeh, Riad; Korenevskiy, Nikolay; Ionescu, Florin; Alshamasin, Mahdi; Smith, Andrew P; Alwadie, Abdullah
2013-02-01
We propose a biotech measurement scheme and software based on new features for the diagnosis of backbone osteochondrosis. Together with the traditional methods of diagnosis, the energy characteristics of biologically active points (acupuncture points, or APs) are used. This new software is based on mathematical models of the internal and biologically active points of meridian structures' interaction. The information from the APs is used in the solving rules based on fuzzy logic for decision-making, together with the factors of confidence of Shortliffe, the membership functions of Zadeh, and Kullback's informativeness measures. In terms of prognostic decision rules, clinical test shows that the quality of prediction using only the energy characteristics of APs is high, with high coefficient of confidence for the control sample as well. A check on control samples allows us to recommend the obtained results for use in medical practice as a part of corresponding systems of support for decision-making. PMID:23370903
Gentili, Pier Luigi; Gotoda, Hiroshi; Dolnik, Milos; Epstein, Irving R.
2015-01-15
Forecasting of aperiodic time series is a compelling challenge for science. In this work, we analyze aperiodic spectrophotometric data, proportional to the concentrations of two forms of a thermoreversible photochromic spiro-oxazine, that are generated when a cuvette containing a solution of the spiro-oxazine undergoes photoreaction and convection due to localized ultraviolet illumination. We construct the phase space for the system using Takens' theorem and we calculate the Lyapunov exponents and the correlation dimensions to ascertain the chaotic character of the time series. Finally, we predict the time series using three distinct methods: a feed-forward neural network, fuzzy logic, and a local nonlinear predictor. We compare the performances of these three methods.
NASA Technical Reports Server (NTRS)
Zadeh, Lofti A.
1988-01-01
The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.
HDL to verification logic translator
NASA Astrophysics Data System (ADS)
Gambles, J. W.; Windley, P. J.
The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.
HDL to verification logic translator
NASA Technical Reports Server (NTRS)
Gambles, J. W.; Windley, P. J.
1992-01-01
The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.
Towards programmable plant genetic circuits.
Medford, June I; Prasad, Ashok
2016-07-01
Synthetic biology enables the construction of genetic circuits with predictable gene functions in plants. Detailed quantitative descriptions of the transfer function or input-output function for genetic parts (promoters, 5' and 3' untranslated regions, etc.) are collected. These data are then used in computational simulations to determine their robustness and desired properties, thereby enabling the best components to be selected for experimental testing in plants. In addition, the process forms an iterative workflow which allows vast improvement to validated elements with sub-optimal function. These processes enable computational functions such as digital logic in living plants and follow the pathway of technological advances which took us from vacuum tubes to cell phones. PMID:27297052
GMAG Dissertation Award Talk: All Spin Logic -- Multimagnet Networks interacting via Spin currents
NASA Astrophysics Data System (ADS)
Srinivasan, Srikant
2012-02-01
Digital logic circuits have traditionally been based on storing information as charge on capacitors, and the stored information is transferred by controlling the flow of charge. However, electrons carry both charge and spin, the latter being responsible for magnetic phenomena. In the last few decades, there has been a significant improvement in our ability to control spins and their interaction with magnets. All Spin Logic (ASL) represents a new approach to information processing where spins and magnets now mirror the roles of charges and capacitors in conventional logic circuits. In this talk I first present a model [1] that couples non-collinear spin transport with magnet-dynamics to predict the switching behavior of the basic ASL device. This model is based on established physics and is benchmarked against available experimental data that demonstrate spin-torque switching in lateral structures. Next, the model is extended to simulate multi-magnet networks coupled with spin transport channels. The simulations suggest ASL devices have the essential characteristics for building logic circuits. In particular, (1) the example of an ASL ring oscillator [2, 3] is used to provide a clear signature of directed information transfer in cascaded ASL devices without the need for external control circuitry and (2) a simulated NAND [4] gate with fan-out of 2 suggests that ASL can implement universal logic and drive subsequent stages. Finally I will discuss how ASL based circuits could also have potential use in the design of neuromorphic circuits suitable for hybrid analog/digital information processing because of the natural mapping of ASL devices to neurons [4]. [4pt] [1] B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, ``Switching Energy-Delay of All-Spin Logic devices,'' Appl. Phys. Lett., 98, 123510 (2011).[0pt] [2] S. Srinivasan, A. Sarkar, B. Behin-Aein, and S. Datta, ``All Spin Logic Device with Inbuilt Non-reciprocity,'' IEEE Trans. Magn., 47, 10 (2011).[0pt] [3
Bruder, Slawa; Babbar-Sebens, Meghna; Tedesco, Lenore; Soyeux, Emmanuel
2014-03-01
Mechanistic modeling of how algal species produce metabolites (e.g., taste and odor compounds geosmin and 2-methyl isoborneol (2-MIB)) as a biological response is currently not well understood. However, water managers and water utilities using these reservoirs often need methods for predicting metabolite production, so that appropriate water treatment procedures can be implemented. In this research, a heuristic approach using Adaptive Network-based Fuzzy Inference System (ANFIS) was developed to determine the underlying nonlinear and uncertain quantitative relationship between observed cyanobacterial metabolites (2-MIB and geosmin), various algal species, and physical and chemical variables. The model is proposed to be used in conjunction with numerical water quality models that can predict spatial-temporal distribution of flows, velocities, water quality parameters, and algal functional groups. The coupling of the proposed metabolite model with the numerical water quality models would assist various utilities which use mechanistic water quality models to also be able to predict distribution of taste and odor metabolites, especially when monitoring of metabolites is limited. The proposed metabolite model was developed and tested for the Eagle Creek Reservoir in Indiana (USA) using observations over a 3-year period (2008-2010). Results show that the developed models performed well for geosmin (R (2) = 0.83 for all training data and R (2) = 0.78 for validation of all 10 data points in the validation dataset) and reasonably well for the 2-MIB (R (2) = 0.82 for all training data and R (2) = 0.70 for 7 out of 10 data points in the validation dataset). PMID:24242080
Development of ferrite logic devices for an arithmetic processor
NASA Technical Reports Server (NTRS)
Heckler, C. H., Jr.
1972-01-01
A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.
Physical synthesis of quantum circuits using templates
NASA Astrophysics Data System (ADS)
Mirkhani, Zahra; Mohammadzadeh, Naser
2016-06-01
Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of "physical synthesis" was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.
Design automation for integrated circuits
NASA Astrophysics Data System (ADS)
Newell, S. B.; de Geus, A. J.; Rohrer, R. A.
1983-04-01
Consideration is given to the development status of the use of computers in automated integrated circuit design methods, which promise the minimization of both design time and design error incidence. Integrated circuit design encompasses two major tasks: error specification, in which the goal is a logic diagram that accurately represents the desired electronic function, and physical specification, in which the goal is an exact description of the physical locations of all circuit elements and their interconnections on the chip. Design automation not only saves money by reducing design and fabrication time, but also helps the community of systems and logic designers to work more innovatively. Attention is given to established design automation methodologies, programmable logic arrays, and design shortcuts.
Small circuits for cryptography.
Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik
2005-10-01
This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.
NASA Astrophysics Data System (ADS)
Whitfield, James; Faccin, Mauro; Biamonte, Jacob
2013-03-01
Designing and optimizing cost functions and energy landscapes is a problem encountered in many fields of science and engineering. These landscapes and cost functions can be embedded and annealed in experimentally controllable spin Hamiltonians. Using an approach based on group theory and symmetries, we examine the embedding of Boolean logic gates into the ground-state subspace of such spin systems. We describe parameterized families of diagonal Hamiltonians and symmetry operations which preserve the ground-state subspace encoding the truth tables of Boolean formulas. The ground-state embeddings of adder circuits are used to illustrate how gates are combined and simplified using symmetry. Our work is relevant for experimental demonstrations of ground-state embeddings found in both classical optimization as well as adiabatic quantum optimization.
Kaushik, Aman Chandra; Sahi, Shakti
2015-06-01
Systems biology addresses challenges in the analysis of genomics data, especially for complex genes and protein interactions using Meta data approach on various signaling pathways. In this paper, we report systems biology and biological circuits approach to construct pathway and identify early gene and protein interactions for predicting GPR142 responses in Type 2 diabetes. The information regarding genes, proteins and other molecules involved in Type 2 diabetes were retrieved from literature and kinetic simulation of GPR142 was carried out in order to determine the dynamic interactions. The major objective of this work was to design a GPR142 biochemical pathway using both systems biology as well as biological circuits synthetically. The term 'synthetically' refers to building biological circuits for cell signaling pathway especially for hormonal pathway disease. The focus of the paper is on logical components and logical circuits whereby using these applications users can create complex virtual circuits. Logic gates process represents only true or false and investigates whether biological regulatory circuits are active or inactive. The basic gates used are AND, NAND, OR, XOR and NOT gates and Integrated circuit composition of many such basic gates and some derived gates. Biological circuits may have a futuristic application in biomedical sciences which may involve placing a micro chip in human cells to modulate the down or up regulation of hormonal disease. PMID:25972988
Adaptive parallel logic networks
Martinez, T.R.; Vidal, J.J.
1988-02-01
This paper presents a novel class of special purpose processors referred to as ASOCS (adaptive self-organizing concurrent systems). Intended applications include adaptive logic devices, robotics, process control, system malfunction management, and in general, applications of logic reasoning. ASOCS combines massive parallelism with self-organization to attain a distributed mechanism for adaptation. The ASOCS approach is based on an adaptive network composed of many simple computing elements (nodes) which operate in a combinational and asynchronous fashion. Problem specification (programming) is obtained by presenting to the system if-then rules expressed as Boolean conjunctions. New rules are added incrementally. In the current model, when conflicts occur, precedence is given to the most recent inputs. With each rule, desired network response is simply presented to the system, following which the network adjusts itself to maintain consistency and parsimony of representation. Data processing and adaptation form two separate phases of operation. During processing, the network acts as a parallel hardware circuit. Control of the adaptive process is distributed among the network nodes and efficiently exploits parallelism.
Bilayer avalanche spin-diode logic
Friedman, Joseph S. Querlioz, Damien; Fadel, Eric R.; Wessels, Bruce W.; Sahakian, Alan V.
2015-11-15
A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.
Bilayer avalanche spin-diode logic
NASA Astrophysics Data System (ADS)
Friedman, Joseph S.; Fadel, Eric R.; Wessels, Bruce W.; Querlioz, Damien; Sahakian, Alan V.
2015-11-01
A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.
Engineering genetic circuits that compute and remember.
Siuti, Piro; Yazbek, John; Lu, Timothy K
2014-01-01
Memory and logic are central to complex state-dependent computing, and state-dependent behaviors are a feature of natural biological systems. Recently, we created a platform for integrated logic and memory by using synthetic gene circuits, and we demonstrated the implementation of all two-input logic gates with memory in living cells. Here we provide a detailed protocol for the construction of two-input Boolean logic functions with concomitant DNA-based memory. This technology platform allows for straightforward assembly of integrated logic-and-memory circuits that implement desired behaviors within a couple of weeks. It should enable the encoding of advanced computational operations in living cells, including sequential-logic and biological-state machines, for a broad range of applications in biotechnology, basic science and biosensing. PMID:24810038
Deng, Dongdong; Arevalo, Hermenegild; Pashakhanloo, Farhad; Prakosa, Adityo; Ashikaga, Hiroshi; McVeigh, Elliot; Halperin, Henry; Trayanova, Natalia
2015-01-01
Identification of optimal ablation sites in hearts with infarct-related ventricular tachycardia (VT) remains difficult to achieve with the current catheter-based mapping techniques. Limitations arise from the ambiguities in determining the reentrant pathways location(s). The goal of this study was to develop experimentally validated, individualized computer models of infarcted swine hearts, reconstructed from high-resolution ex-vivo MRI and to examine the accuracy of the reentrant circuit location prediction when models of the same hearts are instead reconstructed from low clinical-resolution MRI scans. To achieve this goal, we utilized retrospective data obtained from four pigs ~10 weeks post infarction that underwent VT induction via programmed stimulation and epicardial activation mapping via a multielectrode epicardial sock. After the experiment, high-resolution ex-vivo MRI with late gadolinium enhancement was acquired. The Hi-res images were downsampled into two lower resolutions (Med-res and Low-res) in order to replicate image quality obtainable in the clinic. The images were segmented and models were reconstructed from the three image stacks for each pig heart. VT induction similar to what was performed in the experiment was simulated. Results of the reconstructions showed that the geometry of the ventricles including the infarct could be accurately obtained from Med-res and Low-res images. Simulation results demonstrated that induced VTs in the Med-res and Low-res models were located close to those in Hi-res models. Importantly, all models, regardless of image resolution, accurately predicted the VT morphology and circuit location induced in the experiment. These results demonstrate that MRI-based computer models of hearts with ischemic cardiomyopathy could provide a unique opportunity to predict and analyze VT resulting for from specific infarct architecture, and thus may assist in clinical decisions to identify and ablate the reentrant circuit(s). PMID
Simple digital pulse-programing circuit
NASA Technical Reports Server (NTRS)
Langston, J. L.
1979-01-01
Pulse-sequencing circuit uses only shift register and Exclusive-OR gates. Circuit also serves as date-transition edge detector (for rising or falling edges). It is used in sample-and-hold, analog-to-digital conversion sequence control, multiphase clock logic, precise delay control computer control logic, edge detectors, other timing applications, and provides simple means to generate timing and control signals for data transfer, addressing, or mode control in microprocessors and minicomputers.
Logical operations realized on the Ising chain of N qubits
Asano, Masanari; Tateda, Norihiro; Ishii, Chikara
2004-08-01
Multiqubit logical gates are proposed as implementations of logical operations on N qubits realized physically by the local manipulation of qubits before and after the one-time evolution of an Ising chain. This construction avoids complicated tuning of the interactions between qubits. The general rules of the action of multiqubit logical gates are derived by decomposing the process into the product of two-qubit logical operations. The formalism is demonstrated by the construction of a special type of multiqubit logical gate that is simulated by a quantum circuit composed of controlled-NOT gates.
Sun, Shan C.; Chaprnka, Anthony G.
1977-01-11
An automatic gain control circuit functions to adjust the magnitude of an input signal supplied to a measuring circuit to a level within the dynamic range of the measuring circuit while a log-ratio circuit adjusts the magnitude of the output signal from the measuring circuit to the level of the input signal and optimizes the signal-to-noise ratio performance of the measuring circuit.
Digital system provides superregulation of nanosecond amplifier-discriminator circuit
NASA Technical Reports Server (NTRS)
Forges, K. G.
1966-01-01
Feedback system employing a digital logic comparator to detect and correct amplifier drift provides stable gain characteristics for nanosecond amplifiers used in counting applications. Additional anticoincidence logic enables application of the regulation circuit to the amplifier and discriminator while they are mounted in an operable circuit.
Cooper, James A.
1986-01-01
A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and failsafe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.
2013-12-21
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.
Toward spin-based Magneto Logic Gate in Graphene
NASA Astrophysics Data System (ADS)
Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland
Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.
Attenuation of single event induced pulses in CMOS combinational logic
Baze, M.P.; Buchner, S.P.
1997-12-01
Results are presented of a study of SEU generated transient pulse attenuation in combinational logic structures built using common digital CMOS design practices. SPICE circuit analysis, heavy ion tests, and pulsed, focused laser simulations were used to examine the response characteristics of transient pulse behavior in long logic strings. Results show that while there is an observable effect, it cannot be generally assumed that attenuation will significantly reduce observed circuit bit error rates.
Picosecond Imaging Circuit Analysis
NASA Astrophysics Data System (ADS)
Kash, Jeffrey A.
1998-03-01
With ever-increasing complexity, probing the internal operation of a silicon IC becomes more challenging. Present methods of internal probing are becoming obsolete. We have discovered that a very weak picosecond pulse of light is emitted by each FET in a CMOS circuit whenever the circuit changes logic state. This pulsed emission can be simultaneously imaged and time resolved, using a technique we have named Picosecond Imaging Circuit Analysis (PICA). With a suitable imaging detector, PICA allows time resolved measurement on thousands of devices simultaneously. Computer videos made from measurements on real IC's will be shown. These videos, along with a more quantitative evaluation of the light emission, permit the complete operation of an IC to be measured in a non-invasive way with picosecond time resolution.
Synthetic Aperture Radar Image Formation in Reconfigurable Logic
DUDLEY,PETER A.
2001-06-01
This paper studies the implementation of polar format, synthetic aperture radar image formation in modern Field Programmable Gate Arrays (FPGA's). The polar format algorithm is described in rough terms and each of the processing steps is mapped to FPGA logic. This FPGA logic is analyzed with respect to throughput and circuit size for compatibility with airborne image formation.
Implementation of field programmable logic arrays. Final report
Anderson, J.D.
1981-03-01
Field Programmable Logic Arrays (FPLAs) were incorporated into a fire set tester and a development tester used to test a signal generator's logic boards. Other circuits were designed using the FPLA in code conversion and sequential control applications. A Curtiss Electro Devices FPLA programmer was purchased to program Signetics 82S100 and 82S101 devices.
Giving Programming Students a Logical Step Up.
ERIC Educational Resources Information Center
Brown, David W.
1990-01-01
Presents a method to enhance the teaching of computer programing to secondary students that establishes a connection between logic, truth tables, switching circuits, gating symbols, flow charts, and pseudocode. The author asserts that the method prepares students for thinking processes related to programing. (MDH)
Quantum logic gates for superconducting resonator qudits
Strauch, Frederick W.
2011-11-15
We study quantum information processing using superpositions of Fock states in superconducting resonators as quantum d-level systems (qudits). A universal set of single and coupled logic gates is theoretically proposed for resonators coupled by superconducting circuits of Josephson junctions. These gates use experimentally demonstrated interactions and provide an attractive route to quantum information processing using harmonic oscillator modes.
Low power SEU immune CMOS memory circuits
NASA Technical Reports Server (NTRS)
Liu, M. N.; Whitaker, Sterling
1992-01-01
The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.
Introduction to lethal circuit transformations
NASA Astrophysics Data System (ADS)
Fišer, Petr; Schmidt, Jan
2015-12-01
Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network in a reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic synthesis and optimization processes, both academic and commercial, and suggest actions to mitigate the disturbing effects.
Electronic systems miniaturization using programmable logic devices
Ashton, E.C.; Bergeson, G.C.
1990-10-01
This report describes the steps which were taken to miniaturize a target circuit using Erasable Programmable Logic Devices (EPLDs). The original objective of this project was to explore the miniaturization of a circuit using both Application Specific Integrated Circuits (ASICs) and EPLDs to meet the following goals: balance cost and circuit density; reduce fabrication time; improve quality control issues by keeping much of the design in-house; and eliminate security risks by partitioning the design into ASIC and PLD (EPLD) sections. Due to cost considerations, the target circuit was miniaturized using only PLDs. The results of this project indicate that PLDs are capable of realizing fairly dense circuitry, are considerably less expensive than ASICs (by a factor of 500--1000), and are able to eliminate security risks and reduce fabrication time by keeping the design completely in-house.
Low Power Pulse Generator Design Using Hybrid Logic
NASA Astrophysics Data System (ADS)
Lin, Jin-Fa; Hwang, Yin-Tsung; Sheu, Ming-Hwa
A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.
Implementing neural nets with programmable logic
NASA Technical Reports Server (NTRS)
Vidal, Jacques J.
1988-01-01
Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.
Electro-optical graphene plasmonic logic gates.
Ooi, Kelvin J A; Chu, Hong Son; Bai, Ping; Ang, Lay Kee
2014-03-15
The versatile control of graphene's plasmonic modes via an external gate-voltage inspires us to design efficient electro-optical graphene plasmonic logic gates at the midinfrared wavelengths. We show that these devices are superior to the conventional optical logic gates because the former possess cut-off states and interferometric effects. Moreover, the designed six basic logic gates (i.e., NOR/AND, NAND/OR, XNOR/XOR) achieved not only ultracompact size lengths of less than λ/28 with respect to the operating wavelength of 10 μm, but also a minimum extinction ratio as high as 15 dB. These graphene plasmonic logic gates are potential building blocks for future nanoscale midinfrared photonic integrated circuits. PMID:24690855
Multi-input regulation and logic with T7 promoters in cells and cell free systems
Iyer, Sukanya; Karig, David K; Norred, Sarah E; Simpson, Michael L; Doktycz, Mitchel John
2014-01-01
Engineered gene circuits offer an opportunity to harness biological systems for biotechnological and biomedical applications. However, reliance on host E. coli promoters for the construction of circuit elements, such as logic gates, makes implementation of predictable, independently functioning circuits difficult. In contrast, T7 promoters offer a simple orthogonal expression system for use in a variety of cellular backgrounds and even in cell free systems. Here we develop a T7 promoter system that can be regulated by two different transcriptional repressors for the construction of a logic gate that functions in cells and in cell free systems. We first present LacI repressible T7lacO promoters that are regulated from a distal lac operator site for repression. We next explore the positioning of a tet operator site within the T7lacO framework to create T7 promoters that respond to tet and lac repressors and realize an IMPLIES gate. Finally, we demonstrate that these dual input sensitive promoters function in a commercially available E. coli cell-free protein expression system. Together, our results contribute to the first demonstration of multi-input regulation of T7 promoters and expand the utility of T7 promoters in cell based as well as cell-free gene circuits.
NASA Technical Reports Server (NTRS)
1973-01-01
Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.
Gas-Sensing Flip-Flop Circuits
NASA Technical Reports Server (NTRS)
Buehler, Martin G.; Blaes, Brent R.; Williams, Roger; Ryan, Margaret A.
1995-01-01
Gas-sensing integrated circuits consisting largely of modified static random-access memories (SRAMs) undergoing development, building on experience gained in use of modified SRAMs as radiation sensors. Each SRAM memory cell includes flip-flop circuit; sensors exploit metastable state that lies between two stable states (corresponding to binary logic states) of flip-flop circuit. Voltages of metastable states vary with exposures of gas-sensitive resistors.
Integrated-Circuit Pseudorandom-Number Generator
NASA Technical Reports Server (NTRS)
Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur
1992-01-01
Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.
Genetic Dissection of Neural Circuits
Luo, Liqun; Callaway, Edward M.; Svoboda, Karel
2009-01-01
Understanding the principles of information processing in neural circuits requires systematic characterization of the participating cell types and their connections, and the ability to measure and perturb their activity. Genetic approaches promise to bring experimental access to complex neural systems, including genetic stalwarts such as the fly and mouse, but also to nongenetic systems such as primates. Together with anatomical and physiological methods, cell-type-specific expression of protein markers and sensors and transducers will be critical to construct circuit diagrams and to measure the activity of genetically defined neurons. Inactivation and activation of genetically defined cell types will establish causal relationships between activity in specific groups of neurons, circuit function, and animal behavior. Genetic analysis thus promises to reveal the logic of the neural circuits in complex brains that guide behaviors. Here we review progress in the genetic analysis of neural circuits and discuss directions for future research and development. PMID:18341986
Genetic circuit design automation.
Nielsen, Alec A K; Der, Bryan S; Shin, Jonghyeon; Vaidyanathan, Prashant; Paralanov, Vanya; Strychalski, Elizabeth A; Ross, David; Densmore, Douglas; Voigt, Christopher A
2016-04-01
Computation can be performed in living cells by DNA-encoded circuits that process sensory information and control biological functions. Their construction is time-intensive, requiring manual part assembly and balancing of regulator expression. We describe a design environment, Cello, in which a user writes Verilog code that is automatically transformed into a DNA sequence. Algorithms build a circuit diagram, assign and connect gates, and simulate performance. Reliable circuit design requires the insulation of gates from genetic context, so that they function identically when used in different circuits. We used Cello to design 60 circuits forEscherichia coli(880,000 base pairs of DNA), for which each DNA sequence was built as predicted by the software with no additional tuning. Of these, 45 circuits performed correctly in every output state (up to 10 regulators and 55 parts), and across all circuits 92% of the output states functioned as predicted. Design automation simplifies the incorporation of genetic circuits into biotechnology projects that require decision-making, control, sensing, or spatial organization. PMID:27034378
Reconfigurable nanoelectronics using graphene based spintronic logic gates
NASA Astrophysics Data System (ADS)
Dery, Hanan; Wu, Hui; Ciftcioglu, Berkehan; Huang, Michael; Song, Yang; Kawakami, Roland K.; Shi, Jing; Krivorotov, Ilya N.; Telesca, Donald A.; Žutić, Igor; Sham, Lu J.
2011-10-01
This paper presents a novel design concept for spintronic nanoelectronics that emphasizes a seamless integration of spin-based memory and logic circuits. The building blocks are magneto-logic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and present a spin-based circuit design with smaller area, faster speed, and lower energy consumption than the state-of-the-art CMOS counterparts. This design can also be applied in applications such as data compression, coding and image recognition. In the proposed scheme, over 100 spin-based logic operations are carried out before any need for a spin-charge conversion. Consequently, supporting CMOS electronics requires little power consumption. The spintronic-CMOS integrated system can be implemented on a single 3-D chip. These nonvolatile logic circuits hold potential for a paradigm shift in computing applications.
Interfacing synthetic DNA logic operations with protein outputs.
Prokup, Alexander; Deiters, Alexander
2014-11-24
DNA logic gates are devices composed entirely of DNA that perform Boolean logic operations on one or more oligonucleotide inputs. Typical outputs of DNA logic gates are oligonucleotides or fluorescent signals. Direct activation of protein function has not been engineered as an output of a DNA-based computational circuit. Explicit control of protein activation enables the immediate triggering of enzyme function and could yield DNA computation outputs that are otherwise difficult to generate. By using zinc-finger proteins, AND, OR, and NOR logic gates were created that respond to short oligonucleotide inputs and lead to the activation or deactivation of a split-luciferase enzyme. The gate designs are simple and modular, thus enabling integration with larger multigate circuits, and the modular structure gives flexibility in the choice of protein output. The gates were also modified with translator circuits to provide protein activation in response to microRNA inputs as potential cellular cancer markers. PMID:25283524
CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories
Ganesh Saripalli
2002-12-31
Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35{micro} CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.
Compact modeling of perpendicular nanomagnetic logic based on threshold gates
NASA Astrophysics Data System (ADS)
Breitkreutz, Stephan; Eichwald, Irina; Kiermaier, Josef; Csaba, Gyorgy; Schmitt-Landsiedel, Doris; Becherer, Markus
2014-05-01
In this work, we show that physical-based compact modeling of perpendicular Nanomagnetic Logic is crucial for the design and simulation of complex circuitry. A compact model for field-coupled nanomagnets based on an Arrhenius switching model and finite element calculations is introduced. As physical parameters have an enormous influence on the behavior of the circuit, their modeling is of great importance. Exemplarily, a 1-bit full adder based on threshold logic gates is analyzed due to its reliability. The obtained findings are used to design a pure magnetic arithmetic logic unit, which can be used for basic Boolean and logic operations.
Pattern recognition using linguistic fuzzy logic predictors
NASA Astrophysics Data System (ADS)
Habiballa, Hashim
2016-06-01
The problem of pattern recognition has been solved with numerous methods in the Artificial Intelligence field. We present an unconventional method based on Lingustic Fuzzy Logic Forecaster which is primarily used for the task of time series analysis and prediction through logical deduction wtih linguistic variables. This method should be used not only to the time series prediction itself, but also for recognition of patterns in a signal with seasonal component.
Jacobsohn, D.H.; Merrill, L.C.
1959-01-20
An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.
Digital Optical Circuit Technology
NASA Technical Reports Server (NTRS)
Dove, B. L. (Editor)
1985-01-01
The Proceedings for the 48th Meeting of the AGARD Avionics Panel contain the 18 papers presented a Technical Evaluation Report, and discussions that followed the presentations of papers. Seven papers were presented in the session devoted to optical bistability. Optical logic was addressed by three papers. The session on sources, modulators and demodulators presented three papers. Five papers were given in the final session on all optical systems. The purpose of this Specialists' Meeting was to present the research and development status of digital optical circuit technology and to examine its relevance in the broad context of digital processing, communication, radar, avionics and flight control systems implementation.
Fuzzy logic controller optimization
Sepe, Jr., Raymond B; Miller, John Michael
2004-03-23
A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.
NASA Astrophysics Data System (ADS)
Chiara, Maria Luisa Dalla; Giuntini, Roberto
1989-07-01
Paraconsistent quantum logics are weak forms of quantum logic, where the noncontradiction and the excluded-middle laws are violated. These logics find interesting applications in the operational approach to quantum mechanics. In this paper, we present an axiomatization, a Kripke-style, and an algebraic semantical characterization for two forms of paraconsistent quantum logic. Further developments are contained in Giuntini and Greuling's paper in this issue.
A circuit design for multi-inputs stateful OR gate
NASA Astrophysics Data System (ADS)
Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-09-01
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
Nonlinear interferometry approach to photonic sequential logic
NASA Astrophysics Data System (ADS)
Mabuchi, Hideo
2011-10-01
Motivated by rapidly advancing capabilities for extensive nanoscale patterning of optical materials, I propose an approach to implementing photonic sequential logic that exploits circuit-scale phase coherence for efficient realizations of fundamental components such as a NAND-gate-with-fanout and a bistable latch. Kerr-nonlinear optical resonators are utilized in combination with interference effects to drive the binary logic. Quantum-optical input-output models are characterized numerically using design parameters that yield attojoule-scale energy separation between the latch states.
Universal programmable logic gate and routing method
NASA Technical Reports Server (NTRS)
Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)
2009-01-01
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
OncoLogic^{TM} - A Computer System to Evaluate the Carcinogenic Potential of Chemicals
OncoLogic^{TM} is a software program that evaluates the likelihood that a chemical may cause cancer. OncoLogic^{TM} has been peer reviewed and is being rele...
Magnetic tunnel junction based spintronic logic and memory devices
NASA Astrophysics Data System (ADS)
Yao, Xiaofeng
2011-12-01
The development of semiconductor devices is limited by the high power consumption and further physical dimension reduction. Spintronic devices, especially the magnetic tunnel junction (MTJ) based devices, have advantages of non-volatility, reconfigurable capability, fast-switching speed, small-dimension, and compatibility to semiconductor devices, which is a promising candidate for future logic and memory devices. However, the previously proposed MTJ logic devices have been operated independently and therefore are limited to only basic logic operations. Consequently, the MTJ device has only been used as ancillary device in the circuit, rather than the main computation component. In this thesis, study has been done on both spintronic logic and memory devices. In the first part, systematic study has been performed on MTJ based logic devices in order to expand the functionalities and properties of MTJ devices. Basic logic cell with three-input has been designed and simulated. Nano-magnetic-channel has been proposed, which is the first design to realize the communication between the MTJ logic cells. With basic logic unit as a building block, a spintronic logic circuit has been designed with MTJ as the dominant component. HSPICE simulation has been done for this spintronic logic circuit, which acts as an Arithmetic Logic Unit. In the spintronic memory device part, study has been focused on the fundamental study on the current induced switching in MTJ devices with hybrid free layer. With hybrid free layer, magnetic non-uniformity is introduced along the current direction, which induces extra spin torque component. Unique current-induced switching has been observed and studied in the hybrid free layer MTJ. Adiabatic spin torque, which is introduced by spatial non-uniform magnetization in the hybrid free layer, plays an important role for the unique switching. By tuning the bias field, single-polar current switching was achieved in this hybrid MTJ device, which gives the
Design of a Ferroelectric Programmable Logic Gate Array
NASA Technical Reports Server (NTRS)
MacLeod, Todd C.; Ho, Fat Duen
2003-01-01
A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.
High-speed dynamic domino circuit implemented with gaas mesfets
NASA Technical Reports Server (NTRS)
Yang, Long (Inventor); Long, Stephen I. (Inventor)
1990-01-01
A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.
Digital circuits for computer applications: A compilation
NASA Technical Reports Server (NTRS)
1972-01-01
The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.
Auto-programmable impulse neural circuits
NASA Technical Reports Server (NTRS)
Watula, D.; Meador, J.
1990-01-01
Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.
A novel, efficient CNTFET Galois design as a basic ternary-valued logic field
Keshavarzian, Peiman; Mirzaee, Mahla Mohammad
2012-01-01
This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs). Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued) logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption. PMID:24198492
Automated ILA design for synchronous sequential circuits
NASA Technical Reports Server (NTRS)
Liu, M. N.; Liu, K. Z.; Maki, G. K.; Whitaker, S. R.
1991-01-01
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.
Logic Design Pathology and Space Flight Electronics
NASA Technical Reports Server (NTRS)
Katz, Richard; Barto, Rod L.; Erickson, K.
1997-01-01
Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.
Spin gated transistors for reprogrammable logic
NASA Astrophysics Data System (ADS)
Ciccarelli, Chiara; Gonzalez-Zalba, Fernando; Irvine, Andrew; Campion, Richard; Zarbo, Liviu; Gallagher, Brian; Ferguson, Andrew; Jungwirth, Tomas; Wunderlich, Joerg; Institute of Physics ASCR Collaboration; University of Nottingham Collaboration; Hitachi Cambridge Laboratory Team; Institute of Physics ASCR Collaboration; University of Nottingham Collaboration; University of Cambridge Team
2014-03-01
In spin-orbit coupled magnetic materials the chemical potential depends on the orientation of the magnetisation. By making the gate of a field effect transistor magnetic, it is possible to tune the channel conductance not only electrically but also magnetically. We show that these magnetic transistor can be used to realise non-volatile reprogrammable Boolean logic. The non-volatile reconfigurable capability resides in the magnetization-dependent band structure of the magnetic stack. A change in magnetization orientation produces a change in the electrochemical potential, which induces a charge accumulation in the correspondent gate electrode. This is readily sensed by a field-effect device such as standard field-effect transistors or more exotic single-electron transistors. We propose circuits for low power consumption applications that can be magnetically switched between NAND and OR logic functions and between NOR and AND logic functions.
"Glitch Logic" and Applications to Computing and Information Security
NASA Technical Reports Server (NTRS)
Stoica, Adrian; Katkoori, Srinivas
2009-01-01
This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.
Reliability concerns with logical constants in Xilinx FPGA designs
Quinn, Heather M; Graham, Paul; Morgan, Keith; Ostler, Patrick; Allen, Greg; Swift, Gary; Tseng, Chen W
2009-01-01
In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.
Plastic Logic quits e-reader market
NASA Astrophysics Data System (ADS)
Perks, Simon
2012-07-01
A UK firm spun out from the University of Cambridge that sought to be a world leader in flexible organic electronic circuits and displays has pulled out of the competitive e-reader market as it struggles to find a commercial outlet for its technology. Plastic Logic announced in May that it is to close its development facility in Mountain View, California, with the loss of around 40 jobs.
Design Techniques for Power-Aware Combinational Logic SER Mitigation
NASA Astrophysics Data System (ADS)
Mahatme, Nihaar N.
The history of modern semiconductor devices and circuits suggests that technologists have been able to maintain scaling at the rate predicted by Moore's Law [Moor-65]. With improved performance, speed and lower area, technology scaling has also exacerbated reliability issues such as soft errors. Soft errors are transient errors that occur in microelectronic circuits due to ionizing radiation particle strikes on reverse biased semiconductor junctions. These radiation induced errors at the terrestrial-level are caused due to radiation particle strikes by (1) alpha particles emitted as decay products of packing material (2) cosmic rays that produce energetic protons and neutrons, and (3) thermal neutrons [Dodd-03], [Srou-88] and more recently muons and electrons [Ma-79] [Nara-08] [Siew-10] [King-10]. In the space environment radiation induced errors are a much bigger threat and are mainly caused by cosmic heavy-ions, protons etc. The effects of radiation exposure on circuits and measures to protect against them have been studied extensively for the past 40 years, especially for parts operating in space. Radiation particle strikes can affect memory as well as combinational logic. Typically when these particles strike semiconductor junctions of transistors that are part of feedback structures such as SRAM memory cells or flip-flops, it can lead to an inversion of the cell content. Such a failure is formally called a bit-flip or single-event upset (SEU). When such particles strike sensitive junctions part of combinational logic gates they produce transient voltage spikes or glitches called single-event transients (SETs) that could be latched by receiving flip-flops. As the circuits are clocked faster, there are more number of clocking edges which increases the likelihood of latching these transients. In older technology generations the probability of errors in flip-flops due to SETs being latched was much lower compared to direct strikes on flip-flops or SRAMs leading to
Ternary logic and mass quantum numbers
Sheppeard, M. D.
2010-06-15
Koide's prediction of the tau mass may be formulated as a condition on the three eigenvalues of a quantum Fourier series, using simple parameters, and similar triplets have been found for neutrino and hadron masses [2]. Assuming these parameters arise from quantum gravity, one would like to understand them from the more abstract context of category theory. In particular, whereas the logic of lepton spin is a linear analogue of the ordinary Boolean logic of the category of sets, mass triplets suggest an analogous ternary logic, requiring higher dimensional categorical structures.
Content-addressable-memory for the three key operations of fuzzy logic
NASA Astrophysics Data System (ADS)
Jiang, Tao; Li, Yao
1999-03-01
Today, most fuzzy logic operations are performed via software means, which is inevitably slow. While searching for long term hardware solutions to realize analog fuzzy logic operations, the use of the well-developed Boolean logic hardware with analog to digital and digital to analog converters to implement the digitized fuzzy logic could provide an efficient solution. Similar to Boolean logic, digitized fuzzy logic operations can be written as a minimized sum-of-product term format, which can then be implemented based on programmable logic arrays. We address a fundamental issue of the computational complexity of this method. We derive the minimum number of the Boolean sum-of-product terms for some key fuzzy logic operations, such as Union, Intersection, and Complement operators. Our derivations provide ways to estimate the general computational complexity or memory capacity of using binary circuits, electronic or optoelectronic, to implement the digitized analog logic operations.
NASA Astrophysics Data System (ADS)
Saleh, F.; Flipo, N.; de Fouquet, C.
2012-04-01
The main objective of this study is to provide a realistic simulation of river stage in regional river networks in order to improve the quantification of stream-aquifer exchanges and better assess the associated aquifer responses that are often impacted by the magnitude and the frequency of the river stage fluctuations. The study focuses on the Oise basin (17 000 km2, part of the 65 000 km2 Seine basin in Northern France) where stream-aquifer exchanges cannot be assessed directly by experimental methods. Nowadays numerical methods are the most appropriate approaches for assessing stream-aquifer exchanges at this scale. A regional distributed process-based hydro(geo)logical model, Eau-Dyssée, is used, which aims at the integrated modeling of the hydrosystem to manage the various elements involved in the quantitative and qualitative aspects of water resources. Eau-Dyssée simulates pseudo 3D flow in aquifer systems solving the diffusivity equation with a finite difference numerical scheme. River flow is simulated with a Muskingum model. In addition to the in-stream discharge, a river stage estimate is needed to calculate the water exchange at the stream-aquifer interface using the Darcy law. Three methods for assessing in-stream river stages are explored to determine the most appropriate representation at regional scale over 25 years (1980-2005). The first method consists in defining rating curves for each cell of a 1D Saint-Venant hydraulic model. The second method consists in interpolating observed rating curves (at gauging stations) onto the river cells of the hydro(geo)logical model. The interpolation technique is based on geostatistics. The last method assesses river stage using Manning equation with a simplified rectangular cross-section (water depth equals the hydraulic radius). Compared to observations, the geostatistical and the Manning methodologies lead to slightly less accurate (but still acceptable) results offering a low computational cost opportunity
NASA Astrophysics Data System (ADS)
Nomura, Fumimasa; Hattori, Akihiro; Terazono, Hideyuki; Kim, Hyonchol; Odaka, Masao; Sugio, Yoshihiro; Yasuda, Kenji
2016-06-01
For the prediction of lethal arrhythmia occurrence caused by abnormality of cell-to-cell conduction, we have developed a next-generation in vitro cell-to-cell conduction assay, i.e., a quasi in vivo assay, in which the change in spatial cell-to-cell conduction is quantitatively evaluated from the change in waveforms of the convoluted electrophysiological signals from lined-up cardiomyocytes on a single closed loop of a microelectrode of 1 mm diameter and 20 µm width in a cultivation chip. To evaluate the importance of the closed-loop arrangement of cardiomyocytes for prediction, we compared the change in waveforms of convoluted signals of the responses in the closed-loop circuit arrangement with that of the response of cardiomyocyte clusters using a typical human ether a go-go related gene (hERG) ion channel blocker, E-4031. The results showed that (1) waveform prolongation and fluctuation both in the closed loops and clusters increased depending on the E-4031 concentration increase. However, (2) only the waveform signals in closed loops showed an apparent temporal change in waveforms from ventricular tachycardia (VT) to ventricular fibrillation (VF), which is similar to the most typical cell-to-cell conductance abnormality. The results indicated the usefulness of convoluted waveform signals of a closed-loop cell network for acquiring reproducible results acquisition and more detailed temporal information on cell-to-cell conduction.
Closed circuit TV system automatically guides welding arc
NASA Technical Reports Server (NTRS)
Stephans, D. L.; Wall, W. A., Jr.
1968-01-01
Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.
Providing Reliability of Physical Systems: Partially Programmable Circuit Design
NASA Astrophysics Data System (ADS)
Matrosova, A. Yu.; Ostanin, S. A.; Kirienko, I. E.
2014-10-01
One of the important properties of physical systems is reliability.of their functioning, in particular, reliability of functioning of logical control components of the systems. A new approach to partially programmable circuit design that allows masking stuck-at faults at gate poles of logical circuits is considered. The logical circuit consists of gates. It is supposed that only one gate pole may be fault. There are reserved programmable blocks configurable logic blocks (CLBs) based on Look Up Table (LUT) technology that may mask the fault. First, the suggested approach in contrast to the well-known ones, allows masking any stuck-at fault rather than a part of them. Second, the approach is oriented to deriving more simple masking circuit from CLBs based on a compact description of incompletely specified functions of subcircuits.
NASA Technical Reports Server (NTRS)
Preston, K., Jr.
1972-01-01
The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.
Foundations of logic programming
Lloyd, J.W.
1987-01-01
This is the second edition of the first book to give an account of the mathematical foundations of Logic Programming. Its purpose is to collect the basic theoretical results of Logic Programming, which have previously only been available in widely scattered research papers. In addition to presenting the technical results, the book also contains many illustrative examples. Many of the examples and problems are part of the folklore of Logic Programming and are not easily obtainable elsewhere.
Digital Microfluidic Logic Gates
NASA Astrophysics Data System (ADS)
Zhao, Yang; Xu, Tao; Chakrabarty, Krishnendu
Microfluidic computing is an emerging application for microfluidics technology. We propose microfluidic logic gates based on digital microfluidics. Using the principle of electrowetting-on-dielectric, AND, OR, NOT and XOR gates are implemented through basic droplet-handling operations such as transporting, merging and splitting. The same input-output interpretation enables the cascading of gates to create nontrivial computing systems. We present a potential application for microfluidic logic gates by implementing microfluidic logic operations for on-chip HIV test.
NASA Technical Reports Server (NTRS)
Howard, Ayanna
2005-01-01
The Fuzzy Logic Engine is a software package that enables users to embed fuzzy-logic modules into their application programs. Fuzzy logic is useful as a means of formulating human expert knowledge and translating it into software to solve problems. Fuzzy logic provides flexibility for modeling relationships between input and output information and is distinguished by its robustness with respect to noise and variations in system parameters. In addition, linguistic fuzzy sets and conditional statements allow systems to make decisions based on imprecise and incomplete information. The user of the Fuzzy Logic Engine need not be an expert in fuzzy logic: it suffices to have a basic understanding of how linguistic rules can be applied to the user's problem. The Fuzzy Logic Engine is divided into two modules: (1) a graphical-interface software tool for creating linguistic fuzzy sets and conditional statements and (2) a fuzzy-logic software library for embedding fuzzy processing capability into current application programs. The graphical- interface tool was developed using the Tcl/Tk programming language. The fuzzy-logic software library was written in the C programming language.
Thomas, R.E.
1959-01-20
An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses
Merrill, L.C.
1958-10-14
Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.
NASA Astrophysics Data System (ADS)
Whitfield, J. D.; Faccin, M.; Biamonte, J. D.
2012-09-01
Designing and optimizing cost functions and energy landscapes is a problem encountered in many fields of science and engineering. These landscapes and cost functions can be embedded and annealed in experimentally controllable spin Hamiltonians. Using an approach based on group theory and symmetries, we examine the embedding of Boolean logic gates into the ground-state subspace of such spin systems. We describe parameterized families of diagonal Hamiltonians and symmetry operations which preserve the ground-state subspace encoding the truth tables of Boolean formulas. The ground-state embeddings of adder circuits are used to illustrate how gates are combined and simplified using symmetry. Our work is relevant for experimental demonstrations of ground-state embeddings found in both classical optimization as well as adiabatic quantum optimization.
NASA Astrophysics Data System (ADS)
Behin-Aein, Behtash; Datta, Deepanjan; Salahuddin, Sayeef; Datta, Supriyo
2009-03-01
Switching of a magnetic free layer using spin polarized current has been demonstrated in Magnetic Tunnel Junction (MTJ) devices. Currently MTJ's are being studied for memory and microwave oscillator applications. The purpose of this talk is to explore a modified MTJ where a clock pulse via the fixed layer facilities the switching of the free layer in accordance with a weak bias provided by an input magnet in the form of a spin current. Based on the Landau-Lifshitz-Gilbert equation (LLG) augmented with spin torque functions, we show the switching energy and the switching time of the free layer which indicates the possibility of very low power digital logic applications. Ordinary digital circuits store information in the form of capacitor charges that communicate through electrical interconnects. The purpose of this paper is to show that modified MTJ's can be the basis for all spin digital circuits. Our primary objective is to stimulate proof of concept experiments that could usher in a whole new set of devices suitable for spintronic circuits.
Optical Circuit Switched Protocol
NASA Technical Reports Server (NTRS)
Monacos, Steve P. (Inventor)
2000-01-01
The present invention is a system and method embodied in an optical circuit switched protocol for the transmission of data through a network. The optical circuit switched protocol is an all-optical circuit switched network and includes novel optical switching nodes for transmitting optical data packets within a network. Each optical switching node comprises a detector for receiving the header, header detection logic for translating the header into routing information and eliminating the header, and a controller for receiving the routing information and configuring an all optical path within the node. The all optical path located within the node is solely an optical path without having electronic storage of the data and without having optical delay of the data. Since electronic storage of the header is not necessary and the initial header is eliminated by the first detector of the first switching node. multiple identical headers are sent throughout the network so that subsequent switching nodes can receive and read the header for setting up an optical data path.
Integrated-Circuit Controller For Brushless dc Motor
NASA Technical Reports Server (NTRS)
Le, Dong Tuan
1994-01-01
Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.
Photonic encryption using all optical logic.
Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.; Robertson, Perry J.; Vawter, Gregory Allen; Tarman, Thomas David; Pierson, Lyndon George
2003-12-01
With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an
Uncertainty, energy, and multiple-valued logics
Hayes, J.P.
1986-02-01
The multiple-valued logics obtained by introducing uncertainty and energy considerations into classical switching theory are studied in this paper. First, the nature of uncertain or unknown signals is examined, and two general uncertainty types called U-values and P-values are identified. It is shown that multiple-valued logics composed of U/P-values can be systematically derived from 2-valued Boolean algebra. These are useful for timing and hazard analysis, and provide a rigorous framework for designing gate-level logic simulation programs. Next, signals of the form (..nu..,S) are considered where ..nu.. and S denote logic level and strength, respectively, and the product vs corresponds to energy flow or power. It is shown that these signals from a type of lattice called a Pseudo-Boolean algebra. Such algebras characterize the behavior of digital circuits at a level (the switch level) intermediate between the conventional analog and logical levels. They provide the mathematical basis for an efficient new class of switch-level simulation programs used in MOS VLSI design.
Partition algebraic design of asynchronous sequential circuits
NASA Technical Reports Server (NTRS)
Maki, Gary K.; Chen, Kristen Q.; Gopalakrishnan, Suresh K.
1993-01-01
Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that partitioning variables derived from Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.
Table-top mirror based parallel programmable optical logic device
NASA Astrophysics Data System (ADS)
Chattopadhyay, Tanay
2014-12-01
Light rays can easily be reflected to different path by mechanical movement of mirrors. Using this basic operational principle we can design parallel programmable optical logic device (PPOLD) by arranging mirrors on a table. The ‘table-top mirror' models of this proposed circuit have been shown here. We can program it to design all the two input 16-Boolean logical expressions from a single design. The design is based on only plane mirrors. No active optical material is used in this design. Not only that the proposed circuit is optically reversible in nature. Moreover this design is very simple in sense. It can be fabricated in MEMS based optical switches.
Lees, G.W.; McCormick, E.D.
1962-05-22
A tripping circuit employing a magnetic amplifier for tripping a reactor in response to power level, period, or instrument failure is described. A reference winding and signal winding are wound in opposite directions on the core. Current from an ion chamber passes through both windings. If the current increases at too fast a rate, a shunt circuit bypasses one or the windings and the amplifier output reverses polarity. (AEC)
Magnetic tunnel junction based spintronic logic devices
NASA Astrophysics Data System (ADS)
Lyle, Andrew Paul
The International Technology Roadmap for Semiconductors (ITRS) predicts that complimentary metal oxide semiconductor (CMOS) based technologies will hit their last generation on or near the 16 nm node, which we expect to reach by the year 2025. Thus future advances in computational power will not be realized from ever-shrinking device sizes, but rather by 'outside the box' designs and new physics, including molecular or DNA based computation, organics, magnonics, or spintronic. This dissertation investigates magnetic logic devices for post-CMOS computation. Three different architectures were studied, each relying on a different magnetic mechanism to compute logic functions. Each design has it benefits and challenges that must be overcome. This dissertation focuses on pushing each design from the drawing board to a realistic logic technology. The first logic architecture is based on electrically connected magnetic tunnel junctions (MTJs) that allow direct communication between elements without intermediate sensing amplifiers. Two and three input logic gates, which consist of two and three MTJs connected in parallel, respectively were fabricated and are compared. The direct communication is realized by electrically connecting the output in series with the input and applying voltage across the series connections. The logic gates rely on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin transfer torque switching the output. The change in resistance at the input resulted in a voltage margin of 50--200 mV and 250--300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three input logic function realizes the Majority, AND, NAND, NOR, and OR logic operations. The second logic architecture utilizes magnetostatically coupled nanomagnets to compute logic functions, which is the basis of
Principles of Intelligence: On Evolutionary Logic of the Brain
Tsien, Joe Z.
2016-01-01
Humans and animals may encounter numerous events, objects, scenes, foods and countless social interactions in a lifetime. This means that the brain is constructed by evolution to deal with uncertainties and various possibilities. What is the architectural abstraction of intelligence that enables the brain to discover various possible patterns and knowledge about complex, evolving worlds? Here, I discuss the Theory of Connectivity–a “power-of-two” based, operational principle that can serve as a unified wiring and computational logic for organizing and constructing cell assemblies into the microcircuit-level building block, termed as functional connectivity motif (FCM). Defined by the power-of-two based equation, N = 2i−1, each FCM consists of the principal projection neuron cliques (N), ranging from those specific cliques receiving specific information inputs (i) to those general and sub-general cliques receiving various combinatorial convergent inputs. As the evolutionarily conserved logic, its validation requires experimental demonstrations of the following three major properties: (1) Anatomical prevalence—FCMs are prevalent across neural circuits, regardless of gross anatomical shapes; (2) Species conservancy—FCMs are conserved across different animal species; and (3) Cognitive universality—FCMs serve as a universal computational logic at the cell assembly level for processing a variety of cognitive experiences and flexible behaviors. More importantly, this Theory of Connectivity further predicts that the specific-to-general combinatorial connectivity pattern within FCMs should be preconfigured by evolution, and emerge innately from development as the brain’s computational primitives. This proposed design-principle can also explain the general purpose of the layered cortex and serves as its core computational algorithm. PMID:26869892
Principles of Intelligence: On Evolutionary Logic of the Brain.
Tsien, Joe Z
2015-01-01
Humans and animals may encounter numerous events, objects, scenes, foods and countless social interactions in a lifetime. This means that the brain is constructed by evolution to deal with uncertainties and various possibilities. What is the architectural abstraction of intelligence that enables the brain to discover various possible patterns and knowledge about complex, evolving worlds? Here, I discuss the Theory of Connectivity-a "power-of-two" based, operational principle that can serve as a unified wiring and computational logic for organizing and constructing cell assemblies into the microcircuit-level building block, termed as functional connectivity motif (FCM). Defined by the power-of-two based equation, N = 2 (i) -1, each FCM consists of the principal projection neuron cliques (N), ranging from those specific cliques receiving specific information inputs (i) to those general and sub-general cliques receiving various combinatorial convergent inputs. As the evolutionarily conserved logic, its validation requires experimental demonstrations of the following three major properties: (1) Anatomical prevalence-FCMs are prevalent across neural circuits, regardless of gross anatomical shapes; (2) Species conservancy-FCMs are conserved across different animal species; and (3) Cognitive universality-FCMs serve as a universal computational logic at the cell assembly level for processing a variety of cognitive experiences and flexible behaviors. More importantly, this Theory of Connectivity further predicts that the specific-to-general combinatorial connectivity pattern within FCMs should be preconfigured by evolution, and emerge innately from development as the brain's computational primitives. This proposed design-principle can also explain the general purpose of the layered cortex and serves as its core computational algorithm. PMID:26869892
Programmable Logic Controllers.
ERIC Educational Resources Information Center
Insolia, Gerard; Anderson, Kathleen
This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…
AROUSAL AND LOGICAL INFERENCE.
ERIC Educational Resources Information Center
KOEN, FRANK
THE PURPOSE OF THE EXPERIMENT WAS TO DETERMINE THE DEGREE TO WHICH PHYSIOLOGICAL AROUSAL, AS INDEXED BY THE GRASON STADLER TYPE OPERANT CONDITIONING APPARATUS (GSR), IS RELATED TO THE ACCURACY OF LOGICAL REASONING. THE STIMULI WERE 12 SYLLOGISMS, THREE OF EACH OF FOUR DIFFERENT LOGICAL FORMS. THE 14 SUBJECTS (SS) INDICATED THEIR AGREEMENT OR…
ERIC Educational Resources Information Center
Yopp, David
2010-01-01
Understanding logical necessity is an important component of proof and reasoning for teachers of grades K-8. The ability to determine exactly where young students' arguments are faulty offers teachers the chance to give youngsters feedback as they progress toward writing mathematically valid deductive proofs. As defined, logical necessity is the…
Logic via Computer Programming.
ERIC Educational Resources Information Center
Wieschenberg, Agnes A.
This paper proposed the question "How do we teach logical thinking and sophisticated mathematics to unsophisticated college students?" One answer among many is through the writing of computer programs. The writing of computer algorithms is mathematical problem solving and logic in disguise and it may attract students who would otherwise stop…
Single event upsets in gallium arsenide dynamic logic
Fouts, D.J. . ECE Dept.); Weatherford, T. ); McMorrow, C.; Melinger, J.S.; Campbell, A.B. )
1994-12-01
The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and digital systems are briefly discussed, especially with respect to space applications. A short introduction to the topology and operation of GaAs Two-Phase Dynamic FET Logic (TDFL) circuits is presented. Experiments for testing the SEU sensitivity of GaAs TDFL, using a laser to create charge collection events, are described. Results are used to estimate the heavy-ion, soft error rate for TDFL in a spacecraft in geosynchronous orbit, and the dependence of the SEU sensitivity on clock frequency, clock voltage, and clock phase. Analysis of the data includes a comparison between the SEU sensitivities of TDFL and the more common static form of GaAs logic, Directly Coupled FET Logic (DCFL). This is the first reported SEU testing of GaAs dynamic logic.
NASA Astrophysics Data System (ADS)
Malhas, Othman Qasim
1993-10-01
The concept of “abacus logic” has recently been developed by the author (Malhas, n.d.). In this paper the relation of abacus logic to the concept of fuzziness is explored. It is shown that if a certain “regularity” condition is met, concepts from fuzzy set theory arise naturally within abacus logics. In particular it is shown that every abacus logic then has a “pre-Zadeh orthocomplementation”. It is also shown that it is then possible to associate a fuzzy set with every proposition of abacus logic and that the collection of all such sets satisfies natural conditions expected in systems of fuzzy logic. Finally, the relevance to quantum mechanics is discussed.
Microelectromechanical reprogrammable logic device
Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.
2016-01-01
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295
Microelectromechanical reprogrammable logic device.
Hafiz, M A A; Kosuru, L; Younis, M I
2016-01-01
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295
Microelectromechanical reprogrammable logic device
NASA Astrophysics Data System (ADS)
Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.
2016-03-01
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.
Regulatory Conformance Checking: Logic and Logical Form
ERIC Educational Resources Information Center
Dinesh, Nikhil
2010-01-01
We consider the problem of checking whether an organization conforms to a body of regulation. Conformance is studied in a runtime verification setting. The regulation is translated to a logic, from which we synthesize monitors. The monitors are evaluated as the state of an organization evolves over time, raising an alarm if a violation is…
NASA Astrophysics Data System (ADS)
Joo, Sung-Jun; Park, Buhm; Kim, Do-Hyoung; Kwak, Dong-Ok; Park, Junhong; Kim, Hak-Sung
2016-04-01
Warpage of multi-layered printed circuit boards (PCB) during the reflow process is a serious problem which affects the reliability of solder ball connections between the PCB and the mounted semi-conductor packages in electronic devices. It is essential to predict the warpage of the PCB accurately; however, the complicated copper patterns in multi-layered PCBs render a full modeling analysis impossible due to the excessive computing time required. To overcome this problem, we have developed analytical equations of three Cu patterns (line, square, and grid) for the application of thermo-mechanical properties simply by equivalent modeling of Cu patterns. In the proposed equations, the effect of thermo-viscoelastic properties as well as the influence of surrounding layers such as woven glass fabric/BT (bismaleimide triazine), composite laminate (BT core), and photoimageable solder resist (PSR) were considered. To verify the developed equations, vibration tests based on the wave propagation approach were performed at various temperatures. Good agreement was observed between the equivalent model and the experimental results.
Black, Sylvester M; Whitson, Bryan A; Velayutham, Murugesan
2014-05-01
Liver transplantation is a highly successful treatment for end-stage liver disease. While liver transplantation is often the only effective treatment for cirrhosis there is a critical shortage of donor organs, leading to death of many potential recipients on the waiting list. Marginal liver grafts are increasingly being used in an attempt to increase the number of donor livers utilized for transplantation. Marginal donor livers often have complications and worse outcomes for recipients receiving these types of transplant. The ability to predict the outcome with the use of marginal grafts is difficult and often imprecise leading decreased use of potentially suitable grafts. The development and maturation of normothermic ex vivo perfusion as a platform for the assessment of donor organs presents an opportunity to increase the number of usable donor livers available for transplantation. Furthermore, direct measurement of reactive oxygen species (ROS) present in the donor liver on an ex vivo perfusion circuit by electron paramagnetic resonance (EPR) spectroscopy would allow for precise real-time quantification of donor organ injury. The combination normothermic ex vivo liver perfusion with EPR spectroscopy could therefore present a powerful platform to increase the number of donor organs utilized for transplantation. PMID:24629357
Three-Function Logic Gate Controlled by Analog Voltage
NASA Technical Reports Server (NTRS)
Zebulum, Ricardo; Stoica, Adrian
2006-01-01
The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If
Logic-controlled solid state switchgear for 270 volts dc
NASA Technical Reports Server (NTRS)
Sundberg, G. R.; Waddington, D.; Buchanan, E. E., Jr.
1973-01-01
A feasibility study to design and demonstrate solid state switchgear in the form of circuit breakers and a power transfer switch is described. The switchgear operates on a nominal 270 V dc circuit and controls power to a load of up to 15 amperes. One circuit breaker may be interconnected to a second breaker to form a power transfer switch. On-off and transfer functions of the breakers or the transfer switch are remotely controlled. A number of reclosures with variable time delay between tripout and reclosure are programmed and controlled by integrated analog and COSMOS logic circuits. A unique commutation circuit, that generates only minimal transient disturbance to either source or load, was developed to interrupt current flow through the main SCR switching element. Laboratory tests demonstrated performance of the solid state circuit breakers over specified voltage and temperature ranges.
Assigning functional meaning to digital circuits
Eckmann, S.T.; Chisholm, G.H.
1997-07-01
During computer-aided design, the problem of how to determine the logical function of a digital circuit arises in many contexts. For example, assigning functional meaning to a circuit is a fundamental operation in both reverse engineering and implementation validation. This report describes such a determination by discussing how a higher-level functional representation is constructed from a detailed circuit description (i.e., a gate-level netlist, which is a list of logic gates and their interconnections). The approach used involves transforming parts of the netlist into a functional representation and then manipulating this representation. Two types of functional representations are described: (1) a mathematical representation based on the logical operators ``exor`` and ``and`` and (2) a directed acyclic graph representation based on binary decision trees. Each representation provides a canonical form of the logical function being implemented (i.e., a form that is independent of implementation details). Such forms, however, have a well-known problem associated with the ordering of inputs: for each order, a unique form exists. A solution to this problem is given for both representations. Experimental results that demonstrate the use of these representations in the process of assigning functional meaning to a circuit are provided. The report also identifies and discusses issues critical to the performance required of this fundamental operation.
Zargham, M.R.
1995-06-01
Recently, fuzzy logic has been applied to many areas, such as process control, image understanding, robots, expert systems, and decision support systems. This paper will explain the basic concepts of fuzzy logic and its application in different fields. The steps to design a control system will be explained in detail. Fuzzy control is the first successful industrial application of fuzzy logic. A fuzzy controller is able to control systems which previously could only be controlled by skilled operators. In recent years Japan has achieved significant progress in this area and has applied it to variety of products such as cruise control for cars, video cameras, rice cookers, washing machines, etc.
Implications of Tracey's theorem to asynchronous sequential circuit design
NASA Technical Reports Server (NTRS)
Gopalakrishnan, S.; Kim, G.; Maki, G.
1990-01-01
Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.
Computer circuit will fit on single silicon chip
NASA Technical Reports Server (NTRS)
Smith, C.
1964-01-01
A simplified computer logic circuit of two NAND/NOR gates and three additional inputs to accomplish the count and shift function is described. The circuit has capacity for parallel read-in, counting, serial shiftout, complement input and set and reset.
Test results for SEU and SEL immune memory circuits
NASA Technical Reports Server (NTRS)
Wiseman, D.; Canaris, J.; Whitaker, S.; Gambles, J.; Arave, K.; Arave, L.
1993-01-01
Test results for three SEU logic/circuit hardened CMOS memory circuits verify upset and latch-up immunity for two configurations to be in excess of 120 MeV cm(exp 2)/mg using a commercial, non-radiation hardened CMOS process. Test chips from three separate fabrication runs in two different process were evaluated.
Chase, R.L.
1963-05-01
An electronic fast multiplier circuit utilizing a transistor controlled voltage divider network is presented. The multiplier includes a stepped potentiometer in which solid state or transistor switches are substituted for mechanical wipers in order to obtain electronic switching that is extremely fast as compared to the usual servo-driven mechanical wipers. While this multiplier circuit operates as an approximation and in steps to obtain a voltage that is the product of two input voltages, any desired degree of accuracy can be obtained with the proper number of increments and adjustment of parameters. (AEC)
Perrot, Nathalie; Baudrit, Cédric; Brousset, Jean Marie; Abbal, Philippe; Guillemin, Hervé; Perret, Bruno; Goulet, Etienne; Guerin, Laurence; Barbeau, Gérard; Picque, Daniel
2015-01-01
Agri-food is one of the most important sectors of the industry and a major contributor to the global warming potential in Europe. Sustainability issues pose a huge challenge for this sector. In this context, a big issue is to be able to predict the multiscale dynamics of those systems using computing science. A robust predictive mathematical tool is implemented for this sector and applied to the wine industry being easily able to be generalized to other applications. Grape berry maturation relies on complex and coupled physicochemical and biochemical reactions which are climate dependent. Moreover one experiment represents one year and the climate variability could not be covered exclusively by the experiments. Consequently, harvest mostly relies on expert predictions. A big challenge for the wine industry is nevertheless to be able to anticipate the reactions for sustainability purposes. We propose to implement a decision support system so called FGRAPEDBN able to (1) capitalize the heterogeneous fragmented knowledge available including data and expertise and (2) predict the sugar (resp. the acidity) concentrations with a relevant RMSE of 7 g/l (resp. 0.44 g/l and 0.11 g/kg). FGRAPEDBN is based on a coupling between a probabilistic graphical approach and a fuzzy expert system. PMID:26230334
Brousset, Jean Marie; Abbal, Philippe; Guillemin, Hervé; Perret, Bruno; Goulet, Etienne; Guerin, Laurence; Barbeau, Gérard; Picque, Daniel
2015-01-01
Agri-food is one of the most important sectors of the industry and a major contributor to the global warming potential in Europe. Sustainability issues pose a huge challenge for this sector. In this context, a big issue is to be able to predict the multiscale dynamics of those systems using computing science. A robust predictive mathematical tool is implemented for this sector and applied to the wine industry being easily able to be generalized to other applications. Grape berry maturation relies on complex and coupled physicochemical and biochemical reactions which are climate dependent. Moreover one experiment represents one year and the climate variability could not be covered exclusively by the experiments. Consequently, harvest mostly relies on expert predictions. A big challenge for the wine industry is nevertheless to be able to anticipate the reactions for sustainability purposes. We propose to implement a decision support system so called FGRAPEDBN able to (1) capitalize the heterogeneous fragmented knowledge available including data and expertise and (2) predict the sugar (resp. the acidity) concentrations with a relevant RMSE of 7 g/l (resp. 0.44 g/l and 0.11 g/kg). FGRAPEDBN is based on a coupling between a probabilistic graphical approach and a fuzzy expert system. PMID:26230334
Tanida, J.; Ichioka, Y.
1983-01-01
A simple method for optically implementing digital logic gates in parallel has been developed. Parallel logic gates can be achieved by using a lensless shadow-casting system with a light emitting diode array as an incoherent light source. All the sixteen logic functions for two binary variables, which are the fundamental computations of Boolean algebra, can be simply realised in parallel with these gates by changing the switching modes of a led array. Parallel computation structures of the developed optical digital array processor are demonstrated by implementing pattern logics for two binary images with high space-bandwidth product. Applications of the proposed method to parallel shift operation of the image, differentiation, and processing of gray-level image are shown. 9 references.
N channel JFET based digital logic gate structure
NASA Technical Reports Server (NTRS)
Krasowski, Michael J. (Inventor)
2010-01-01
A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.
ERIC Educational Resources Information Center
Nelson, Jane B.
1998-01-01
Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)
Gallium arsenide processing for gate array logic
NASA Technical Reports Server (NTRS)
Cole, Eric D.
1989-01-01
The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.
Design Techniques for Power-Aware Combinational Logic SER Mitigation
NASA Astrophysics Data System (ADS)
Mahatme, Nihaar N.
The history of modern semiconductor devices and circuits suggests that technologists have been able to maintain scaling at the rate predicted by Moore's Law [Moor-65]. With improved performance, speed and lower area, technology scaling has also exacerbated reliability issues such as soft errors. Soft errors are transient errors that occur in microelectronic circuits due to ionizing radiation particle strikes on reverse biased semiconductor junctions. These radiation induced errors at the terrestrial-level are caused due to radiation particle strikes by (1) alpha particles emitted as decay products of packing material (2) cosmic rays that produce energetic protons and neutrons, and (3) thermal neutrons [Dodd-03], [Srou-88] and more recently muons and electrons [Ma-79] [Nara-08] [Siew-10] [King-10]. In the space environment radiation induced errors are a much bigger threat and are mainly caused by cosmic heavy-ions, protons etc. The effects of radiation exposure on circuits and measures to protect against them have been studied extensively for the past 40 years, especially for parts operating in space. Radiation particle strikes can affect memory as well as combinational logic. Typically when these particles strike semiconductor junctions of transistors that are part of feedback structures such as SRAM memory cells or flip-flops, it can lead to an inversion of the cell content. Such a failure is formally called a bit-flip or single-event upset (SEU). When such particles strike sensitive junctions part of combinational logic gates they produce transient voltage spikes or glitches called single-event transients (SETs) that could be latched by receiving flip-flops. As the circuits are clocked faster, there are more number of clocking edges which increases the likelihood of latching these transients. In older technology generations the probability of errors in flip-flops due to SETs being latched was much lower compared to direct strikes on flip-flops or SRAMs leading to
The Development of a Digital Logic Concept Inventory
ERIC Educational Resources Information Center
Herman, Geoffrey Lindsay
2011-01-01
Instructors in electrical and computer engineering and in computer science have developed innovative methods to teach digital logic circuits. These methods attempt to increase student learning, satisfaction, and retention. Although there are readily accessible and accepted means for measuring satisfaction and retention, there are no widely…
NASA Astrophysics Data System (ADS)
Gabelli, J.; Fève, G.; Berroir, J.-M.; Plaçais, B.
2012-12-01
We review the first experiment on dynamic transport in a phase-coherent quantum conductor. In our discussion, we highlight the use of time-dependent transport as a means of gaining insight into charge relaxation on a mesoscopic scale. For this purpose, we studied the ac conductance of a model quantum conductor, i.e. the quantum RC circuit. Prior to our experimental work, Büttiker et al (1993 Phys. Lett. A 180 364-9) first worked on dynamic mesoscopic transport in the 1990s. They predicted that the mesoscopic RC circuit can be described by a quantum capacitance related to the density of states in the capacitor and a constant charge-relaxation resistance equal to half of the resistance quantum h/2e2, when a single mode is transmitted between the capacitance and a reservoir. By applying a microwave excitation to a gate located on top of a coherent submicronic quantum dot that is coupled to a reservoir, we validate this theoretical prediction on the ac conductance of the quantum RC circuit. Our study demonstrates that the ac conductance is directly related to the dwell time of electrons in the capacitor. Thereby, we observed a counterintuitive behavior of a quantum origin: as the transmission of the single conducting mode decreases, the resistance of the quantum RC circuit remains constant while the capacitance oscillates.
Circuit for high resolution decoding of multi-anode microchannel array detectors
NASA Technical Reports Server (NTRS)
Kasle, David B. (Inventor)
1995-01-01
A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.
Teleology as Logical Phenomenology: Some Therapeutic Implications.
ERIC Educational Resources Information Center
Rychlak, Joseph F.
Phenomenology is an important force in the development of psychological theory, rather than a variant type of counseling method. A distinction must be drawn between the sensory phenomenology in which gestaltists focus on sensory receptors, and logical pheomenology in which the grounding of belief or self-identity is viewed as a prediction or…
``Spin inverter'' as building block of All Spin Logic devices
NASA Astrophysics Data System (ADS)
Sarkar, Angik; Srinivasan, Srikant; Datta, Supriyo
2012-02-01
All-spin logic (ASL) represents a new approach to information processing where the roles of charges and capacitors in charge based transistors are played by spins and magnets, without the need for repeated spin-charge conversion. In our past work, we have presented numerical simulations based on a coupled spin transport and Landau Lifshitz Gilbert model showing that ring oscillators and logic circuits with intrinsic directionality [IEEE Trans. Magn. 47,10, 4026, 2011; Proc. IEDM, 2011)] can be implemented by manipulation of spins in magnetic nanostructures. The aim of this talk is (1) to identify a basic ASL unit that can be interconnected to build up spin circuits analogous to the way transistors are interconnected to build conventional circuits and (2) to present a compact model for this basic unit that can be used to design and analyze large scale spin circuits. We will show that this basic ASL unit is a one-magnet ``spin inverter'' with gain that can be cascaded to accomplish a spin circuit implementation of almost any logic functionality
NASA Astrophysics Data System (ADS)
Kreutz, M.; Richalet, J.; Mocha, K.; Haber, R.
2014-12-01
HVAC systems of industrial buildings consume a lot of energy. Therefore it is important to know the performance of these systems and strategies to optimize the hardware and the control. Tackling the temperature control of the HVAC system promises quick savings by tuning the control within specified tolerance limits, which mostly can be done by low investment. This paper mainly deals with the implementation strategy of a new controller in a PLC using the predictive functional control for temperature control. The different stages of the implementation from the simulation over the SCL code till to the real-time operation are presented. A bumpless switch between the PI(D) and the PFC control was realized, as well.
Mechanical passive logic module
NASA Astrophysics Data System (ADS)
Chattopadhyay, Tanay; Caulfield, H. John
2015-02-01
Nothing from nothing gives simple simile, but something from nothing is an interesting and challenging task. Adolf Lohmann once proposed 'do nothing machine' in optics, which only copies input to output. Passive logic module (PALM) is a special type of 'do nothing machine' which can converts inputs into one of 16 possible binary outputs. This logic module is not like the conventional irreversible one. It is a simple type of reversible Turing machine. In this manuscript we discussed and demonstrated PALM using mechanical movement of plane mirrors. Also we discussed the theoretical model of micro electro mechanical system (MEMS) based PALM in this manuscript. It may have several valuable properties such as passive operation (no need for nonlinear elements as other logic device require) and modular logic (one device implementing any Boolean logic function with simple internal changes). The result is obtained from the demonstration by only looking up the output. No calculation is required to get the result. Not only that, PALM is a simple type of the famous 'billiard ball machine', which also discussed in this manuscript.
Pathway to the Piezoelectronic Transduction Logic Device
NASA Astrophysics Data System (ADS)
Solomon, P. M.; Bryce, B. A.; Kuroda, M. A.; Keech, R.; Shetty, S.; Shaw, T. M.; Copel, M.; Hung, L.-W.; Schrott, A. G.; Armstrong, C.; Gordon, M. S.; Reuter, K. B.; Theis, T. N.; Haensch, W.; Rossnagel, S. M.; Miyazoe, H.; Elmegreen, B. G.; Liu, X.-H.; Trolier-McKinstry, S.; Martyna, G. J.; Newns, D. M.
2015-04-01
The information age challenges computer technology to process an exponentially increasing computational load on a limited energy budget - a requirement that demands an exponential reduction in energy per operation. In digital logic circuits, the switching energy of present FET devices is intimately connected with the switching voltage, and can no longer be lowered sufficiently, limiting the ability of current technology to address the challenge. Quantum computing offers a leap forward in capability, but a clear advantage requires algorithms presently developed for only a small set of applications. Therefore, a new, general purpose, classical technology based on a different paradigm is needed to meet the ever increasing demand for data processing.
A Simple Memristor Model for Circuit Simulations
NASA Astrophysics Data System (ADS)
Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team
This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.
Diagnosable structured logic array
NASA Technical Reports Server (NTRS)
Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)
2009-01-01
A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.
Genetic programs constructed from layered logic gates in single cells
Moon, Tae Seok; Lou, Chunbo; Tamsir, Alvin; Stanton, Brynne C.; Voigt, Christopher A.
2014-01-01
Genetic programs function to integrate environmental sensors, implement signal processing algorithms and control expression dynamics1. These programs consist of integrated genetic circuits that individually implement operations ranging from digital logic to dynamic circuits2–6, and they have been used in various cellular engineering applications, including the implementation of process control in metabolic networks and the coordination of spatial differentiation in artificial tissues. A key limitation is that the circuits are based on biochemical interactions occurring in the confined volume of the cell, so the size of programs has been limited to a few circuits1,7. Here we apply part mining and directed evolution to build a set of transcriptional AND gates in Escherichia coli. Each AND gate integrates two promoter inputs and controls one promoter output. This allows the gates to be layered by having the output promoter of an upstream circuit serve as the input promoter for a downstream circuit. Each gate consists of a transcription factor that requires a second chaperone protein to activate the output promoter. Multiple activator–chaperone pairs are identified from type III secretion pathways in different strains of bacteria. Directed evolution is applied to increase the dynamic range and orthogonality of the circuits. These gates are connected in different permutations to form programs, the largest of which is a 4-input AND gate that consists of 3 circuits that integrate 4 inducible systems, thus requiring 11 regulatory proteins. Measuring the performance of individual gates is sufficient to capture the behaviour of the complete program. Errors in the output due to delays (faults), a common problem for layered circuits, are not observed. This work demonstrates the successful layering of orthogonal logic gates, a design strategy that could enable the construction of large, integrated circuits in single cells. PMID:23041931
Single event upsets in gallium arsenide pseudo-complementary MESFET logic
Fouts, D.J.; Wolfe, K.; Van Dyk, S.E.; Weatherford, T.R.; McMorrow, D.; Melinger, J.S.; Tran, L.H.; Campbell, A.B.
1995-12-01
An introduction to gallium arsenide (GaAs) Pseudo-Complementary MESFET Logic (PCML) circuits is presented. PCML was developed to reduce the sensitivity of high-speed GaAs logic to radiation-induced single event upsets (SEUs). Experiments for testing the single-event upset (SEU) sensitivity of GaAs PCML integrated circuits (ICs) are described. The results of the experiments are analyzed. This new type of high-speed, low-power, GaAs logic provides decreased sensitivity to SEUs compared to more traditional circuit designs such as Directly-Coupled FET Logic (DCFL). PCML is fully compatible with existing GaAs E/D MESFET fabrication processes, such as those commonly used to make DCFL.
NASA Astrophysics Data System (ADS)
Choi, Changmin; Lee, Jieun; Park, Sungwook; Chung, In-Young; Kim, Chang-Joon; Park, Byung-Gook; Kim, Dong Myong; Kim, Dae Hwan
2009-06-01
The performance and the power consumption of single-electron transistor (SET) technology-based ultra-energy-efficient signal processing circuits are compared based on the SPICE model including non-ideal effects of the experimental data for the first time. In terms of ultra-energy-efficient logic circuits, the binary decision diagram (BDD) logic circuit is the most promising with a dissipated power of 0.29 nW at Vdd = 0.1 V and fin = 50 MHz among the static complementary metal-oxide-semiconductor (CMOS)-like SET logic, the dynamic SET/CMOS hybrid logic, cellular nonlinear network (CNN) and BDD. This result means that the transition of a paradigm substituting the current for the voltage as a state variable of a signal processing is strongly required in post-CMOS signal processing and ultra-energy-efficient applications.
Modeling and simulation of single-event effect in CMOS circuit
NASA Astrophysics Data System (ADS)
Suge, Yue; Xiaolin, Zhang; Yuanfu, Zhao; Lin, Liu; Hanning, Wang
2015-11-01
This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ionization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.
NASA Technical Reports Server (NTRS)
1979-01-01
The U-shaped wire devices in the upper photo are Digi-Klipsm; aids to compact packaging of electrical and electronic devices. They serve as connectors linking the circuitry of one circuit board with another in multi-board systems. Digi-Klips were originally developed for Goddard Space Flight Center to meet a need for lightweight, reliable connectors to replace hand-wired connections formerly used in spacecraft. They are made of beryllium copper wire, noted for its excellent conductivity and its spring-like properties, which assure solid electrical contact over a long period of time.
Fuzzy logic and neural network technologies
NASA Technical Reports Server (NTRS)
Villarreal, James A.; Lea, Robert N.; Savely, Robert T.
1992-01-01
Applications of fuzzy logic technologies in NASA projects are reviewed to examine their advantages in the development of neural networks for aerospace and commercial expert systems and control. Examples of fuzzy-logic applications include a 6-DOF spacecraft controller, collision-avoidance systems, and reinforcement-learning techniques. The commercial applications examined include a fuzzy autofocusing system, an air conditioning system, and an automobile transmission application. The practical use of fuzzy logic is set in the theoretical context of artificial neural systems (ANSs) to give the background for an overview of ANS research programs at NASA. The research and application programs include the Network Execution and Training Simulator and faster training algorithms such as the Difference Optimized Training Scheme. The networks are well suited for pattern-recognition applications such as predicting sunspots, controlling posture maintenance, and conducting adaptive diagnoses.
Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic
NASA Astrophysics Data System (ADS)
Ayala, Christopher Lawrence
Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using
NASA Astrophysics Data System (ADS)
Kapit, Eliot
Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven SQUID couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multi-qubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of forty or more compared to the individual qubit T1 and T2 using this technique.
Temporal logics meet telerobotics
NASA Technical Reports Server (NTRS)
Rutten, Eric; Marce, Lionel
1989-01-01
The specificity of telerobotics being the presence of a human operator, decision assistance tools are necessary for the operator, especially in hostile environments. In order to reduce execution hazards due to a degraded ability for quick and efficient recovery of unexpected dangerous situations, it is of importance to have the opportunity, amongst others, to simulate the possible consequences of a plan before its actual execution, in order to detect these problematic situations. Hence the idea of providing the operator with a simulator enabling him to verify the temporal and logical coherence of his plans. Therefore, the power of logical formalisms is used for representation and deduction purposes. Starting from the class of situations that are represented, a STRIPS (the STanford Research Institute Problem Solver)-like formalism and its underlying logic are adapted to the simulation of plans of actions in time. The choice of a temporal logic enables to build a world representation, on which the effects of plans, grouping actions into control structures, will be transcribed by the simulation, resulting in a verdict and information about the plan's coherence.
Quantum probabilistic logic programming
NASA Astrophysics Data System (ADS)
Balu, Radhakrishnan
2015-05-01
We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.
ERIC Educational Resources Information Center
Straumanis, Joan
A major problem in teaching symbolic logic is that of providing individualized and early feedback to students who are learning to do proofs. To overcome this difficulty, a computer program was developed which functions as a line-by-line proof checker in Sentential Calculus. The program, DEMON, first evaluates any statement supplied by the student…
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
2000-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard; Day, John H. (Technical Monitor)
2001-01-01
This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.
Logical Graphics Design Technique for Drawing Distribution Networks
NASA Astrophysics Data System (ADS)
Al-A`Ali, Mansoor
Electricity distribution networks normally consist of tens of primary feeders, thousands of substations and switching stations spread over large geographical areas and thus require a complex system in order to manage them properly from within the distribution control centre. We show techniques for using Delphi Object Oriented components to automatically generate, display and manage graphically and logically the circuits of the network. The graphics components are dynamically interactive and thus the system allows switching operations as well as displays. The object oriented approach was developed to replace an older system, which used Microstation with MDL as the programming language and ORACLE as the DBMS. Before this, the circuits could only be displayed schematically, which has many inherent problems in speed and readability of large displays. Schematic graphics displays were cumbersome when adding or deleting stations; this problem is now resolved using our approach by logically generating the graphics from the database connectivity information. This paper demonstrates the method of designing these Object Oriented components and how they can be used in specially created algorithms to generate the necessary interactive graphics. Four different logical display algorithms were created and in this study we present samples of the four different outputs of these algorithms which prove that distribution engineers can work with logical display of the circuits which are aimed to speed up the switching operations and for better clarity of the display.
OptCircuit: An optimization based method for computational design of genetic circuits
Dasika, Madhukar S; Maranas, Costas D
2008-01-01
Background Recent years has witnessed an increasing number of studies on constructing simple synthetic genetic circuits that exhibit desired properties such as oscillatory behavior, inducer specific activation/repression, etc. It has been widely acknowledged that that task of building circuits to meet multiple inducer-specific requirements is a challenging one. This is because of the incomplete description of component interactions compounded by the fact that the number of ways in which one can chose and interconnect components, increases exponentially with the number of components. Results In this paper we introduce OptCircuit, an optimization based framework that automatically identifies the circuit components from a list and connectivity that brings about the desired functionality. Multiple literature sources are used to compile a comprehensive compilation of kinetic descriptions of promoter-protein pairs. The dynamics that govern the interactions between the elements of the genetic circuit are currently modeled using deterministic ordinary differential equations but the framework is general enough to accommodate stochastic simulations. The desired circuit response is abstracted as the maximization/minimization of an appropriately constructed objective function. Computational results for a toggle switch example demonstrate the ability of the framework to generate the complete list of circuit designs of varying complexity that exhibit the desired response. Designs identified for a genetic decoder highlight the ability of OptCircuit to suggest circuit configurations that go beyond the ones compatible with digital logic-based design principles. Finally, the results obtained from the concentration band detector example demonstrate the ability of OptCircuit to design circuits whose responses are contingent on the level of external inducer as well as pinpoint parameters for modification to rectify an existing (non-functional) biological circuit and restore
'Memristive' switches enable 'stateful' logic operations via material implication.
Borghetti, Julien; Snider, Gregory S; Kuekes, Philip J; Yang, J Joshua; Stewart, Duncan R; Williams, R Stanley
2010-04-01
The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable. PMID:20376145
Sandia ATM SONET Interface Logic
1994-07-21
SASIL is used to program the EPLD's (Erasable Programmable Logic Devices) and PAL's (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.
Intramolecular circuits connected to N electrodes using a scattering matrix approach
NASA Astrophysics Data System (ADS)
Ami, S.; Joachim, C.
2002-04-01
The scattering matrix technique is extended to describe the electronic transport characteristics of intramolecular circuits driven in a ballistic or a tunnel transport regime. The circuit is assumed to be connected by N electrodes. As a working example, the electronic properties of a T-node circuit are presented leading to the design of an OR logic gate working in a ballistic regime. In the tunnel regime, only the ``node'' Kirchhoff law of circuit remains valid at the nodes of an intramolecular tunnel circuit and the electronic characteristics of the branches composing the circuit are mutually independent. It results in a difficult design of a logic OR intramolecular gate of high performance and stability, pointing out the urge for new architectures to implement complex logic functions inside a single molecule.
Photonic encryption : modeling and functional analysis of all optical logic.
Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.
2004-10-01
With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay
Synthesis of Genetic Clock with Combinational Biologic Circuits.
Chen, Po-Kuei; Lin, Chun-Liang
2015-01-01
The potential of genetic clock lies in its role to triggering logic reaction for sequential biological circuits. In general, biochemical reaction of the biological system is extremely slow. However, a square wave generator used as a genetic clock the transient response should be fast enough to catch the reaction change between two logic levels. Therefore, the requirement for instantaneous changes in logic status is not likely to exist in biological systems. This paper presents a method of synthesizing a genetic clock generator based on the combination of a toggle switch with two biological logic gates. A dual repressor is used to connect the two fundamental biologic circuits. Analysis of the characteristic responses of this genetic clock with its relation to the key parameters is provided. PMID:26451832
Automatic ranging circuit for a digital panel meter
Mueller, Theodore R.; Ross, Harley H.
1976-01-01
This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to insure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit.
Conditional Logic and Primary Children.
ERIC Educational Resources Information Center
Ennis, Robert H.
Conditional logic, as interpreted in this paper, means deductive logic characterized by "if-then" statements. This study sought to investigate the knowledge of conditional logic possessed by primary children and to test their readiness to learn such concepts. Ninety students were designated the experimental group and participated in a 15-week…
NASA Astrophysics Data System (ADS)
Pascal, Robert; Pross, Addy
2016-04-01
In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the `regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both `regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.
INDEP approach for leakage reduction in nanoscale CMOS circuits
NASA Astrophysics Data System (ADS)
Sharma, Vijay Kumar; Pattanaik, Manisha; Raj, Balwinder
2015-02-01
Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.
Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell
NASA Astrophysics Data System (ADS)
Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng
2016-06-01
Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis
Commutation circuit for an HVDC circuit breaker
Premerlani, William J.
1981-01-01
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.
Commutation circuit for an HVDC circuit breaker
Premerlani, W.J.
1981-11-10
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
1998-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
1998-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.
Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo
2015-03-25
A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. PMID:25418881
A tight-binding study of a 1-bit half-adder based on diode logic integrated inside a single molecule
NASA Astrophysics Data System (ADS)
Stadler, R.; Ami, S.; Forshaw, M.; Joachim, C.
2003-07-01
The design of a 1-bit half-adder diode logic circuit inside a single molecule is investigated, with the chemical groups for diodes and wires bonded together to form the molecular circuit. With a circuit working in the ballistic transport regime, interference effects between the different electron paths in the circuit make the optimization of the circuit's logic function very delicate. In the tunnelling regime, these effects are partly suppressed. But the exponential decay of the current with the wire length imposes additional constraints for circuit design. A programmable gate logic array-like architecture would be expected be more useful for the design of a 1-bit adder in the ballistic regime due to the regularity of the circuit lattice, which might reduce interferences. On the other hand, a dedicated design which minimizes the amount of wiring might be the better choice for the tunnelling regime. However, we find that the logic output of classical diode logic circuits cannot be reproduced in either regime because Kirchhoff-like circuit rules do not apply. Furthermore, the geometry dependence of electron transmission in both regimes would make it impractical to build up logical functions like the SUM of an adder from simple OR- and AND-gates, even if the output pattern of these gates could be perfectly reproduced.
NASA Astrophysics Data System (ADS)
Giordano, P.
2010-06-01
We introduce a ring of the so-called Fermat reals, which is an extension of the real field containing nilpotent infinitesimals. The construction is inspired by Smooth Infinitesimal Analysis (SIA) and provides a powerful theory of actual infinitesimals without any background in mathematical logic. In particular, in contrast to SIA, which admits models in intuitionistic logic only, the theory of Fermat reals is consistent with the classical logic. We face the problem of deciding whether or not a product of powers of nilpotent infinitesimals vanishes, study the identity principle for polynomials, and discuss the definition and properties of the total order relation. The construction is highly constructive, and every Fermat real admits a clear and order-preserving geometrical representation. Using nilpotent infinitesimals, every smooth function becomes a polynomial because the remainder in Taylor’s formulas is now zero. Finally, we present several applications to informal classical calculations used in physics, and all these calculations now become rigorous, and at the same time, formally equal to the informal ones. In particular, an interesting rigorous deduction of the wave equation is given, which clarifies how to formalize the approximations tied with Hooke’s law using the language of nilpotent infinitesimals.
Kompa, K. L.; Levine, R. D.
2001-01-01
We propose a scheme for molecule-based information processing by combining well-studied spectroscopic techniques and recent results from chemical dynamics. Specifically it is discussed how optical transitions in single molecules can be used to rapidly perform classical (Boolean) logical operations. In the proposed way, a restricted number of states in a single molecule can act as a logical gate equivalent to at least two switches. It is argued that the four-level scheme can also be used to produce gain, because it allows an inversion, and not only a switching ability. The proposed scheme is quantum mechanical in that it takes advantage of the discrete nature of the energy levels but, we here discuss the temporal evolution, with the use of the populations only. On a longer time range we suggest that the same scheme could be extended to perform quantum logic, and a tentative suggestion, based on an available experiment, is discussed. We believe that the pumping can provide a partial proof of principle, although this and similar experiments were not interpreted thus far in our terms. PMID:11209046
Zhou, Chunyang; Liu, Dali; Dong, Shaojun
2016-08-17
Herein, a novel logic operation of prime discriminator is first performed for the function of identifying the prime numbers from natural numbers less than 10. The prime discriminator logic operation is developed by DNA hybridizations and the conjugation of graphene oxide and single-stranded DNA as a reacting platform. On the basis of the similar reaction principle, an odd parity checker is also developed. The odd parity checker logic operation can identify the even numbers and odd numbers from natural numbers less than 10. Such advanced logic operations with digital recognition ability can provide a new field of vision toward prototypical DNA-based logic operations and promote the development of advanced logic circuits. PMID:27459592
Leveling circuits and crustal movements
NASA Technical Reports Server (NTRS)
Chi, S. C.; Reilinger, R. E.; Brown, L. D.; Oliver, J. E.
1980-01-01
An investigation of further possible vertical crustal movements in the Western United States made with circuit microclosure analysis is presented. The San Andreas fault in Cal., the Nevada seismic zone in Nev., and the Sierra Nevada in Calif. were studied based on supposition that in areas undergoing crustal movement the misclosure for a particular circuit should have the smallest value when the circuit is formed from the most temporarily homogeneous survey data; it should have larger, predictable values when the circuit is closed with surveys conducted at other times. Leveling surveys along the San Andreas fault and the Nevada seismic zone are discussed, noting the possibility of regional tilting in the Great Basin between 1934 and 1955, and of elevation changes in the Northern Nevada Range using results of leveling surveys between Roseville, Cal. and Reno, Nev.
Nanomagnet Logic: Architectures, design, and benchmarking
NASA Astrophysics Data System (ADS)
Kurtz, Steven J.
Nanomagnet Logic (NML) is an emerging technology being studied as a possible replacement or supplementary device for Complimentary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FET) by the year 2020. NML devices offer numerous potential advantages including: low energy operation, steady state non-volatility, radiation hardness and a clear path to fabrication and integration with CMOS. However, maintaining both low-energy operation and non-volatility while scaling from the device to the architectural level is non-trivial as (i) nearest neighbor interactions within NML circuits complicate the modeling of ensemble nanomagnet behavior and (ii) the energy intensive clock structures required for re-evaluation and NML's relatively high latency challenge its ability to offer system-level performance wins against other emerging nanotechnologies. Thus, further research efforts are required to model more complex circuits while also identifying circuit design techniques that balance low-energy operation with steady state non-volatility. In addition, further work is needed to design and model low-power on-chip clocks while simultaneously identifying application spaces where NML systems (including clock overhead) offer sufficient energy savings to merit their inclusion in future processors. This dissertation presents research advancing the understanding and modeling of NML at all levels including devices, circuits, and line clock structures while also benchmarking NML against both scaled CMOS and tunneling FETs (TFET) devices. This is accomplished through the development of design tools and methodologies for (i) quantifying both energy and stability in NML circuits and (ii) evaluating line-clocked NML system performance. The application of these newly developed tools improves the understanding of ideal design criteria (i.e., magnet size, clock wire geometry, etc.) for NML architectures. Finally, the system-level performance evaluation tool offers the ability to
LOGSIM user's manual. [Logic Simulation Program for computer aided design of logic circuits
NASA Technical Reports Server (NTRS)
Mitchell, C. L.; Taylor, J. F.
1972-01-01
The user's manual for the LOGSIM Program is presented. All program options are explained and a detailed definition of the format of each input card is given. LOGSIM Program operations, and the preparation of LOGSIM input data are discused along with data card formats, postprocessor data cards, and output interpretation.
Logic as Marr's Computational Level: Four Case Studies.
Baggio, Giosuè; van Lambalgen, Michiel; Hagoort, Peter
2015-04-01
We sketch four applications of Marr's levels-of-analysis methodology to the relations between logic and experimental data in the cognitive neuroscience of language and reasoning. The first part of the paper illustrates the explanatory power of computational level theories based on logic. We show that a Bayesian treatment of the suppression task in reasoning with conditionals is ruled out by EEG data, supporting instead an analysis based on defeasible logic. Further, we describe how results from an EEG study on temporal prepositions can be reanalyzed using formal semantics, addressing a potential confound. The second part of the article demonstrates the predictive power of logical theories drawing on EEG data on processing progressive constructions and on behavioral data on conditional reasoning in people with autism. Logical theories can constrain processing hypotheses all the way down to neurophysiology, and conversely neuroscience data can guide the selection of alternative computational level models of cognition. PMID:25417838
Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model
NASA Technical Reports Server (NTRS)
MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.
2005-01-01
A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.
A programmable heater control circuit for spacecraft
NASA Technical Reports Server (NTRS)
Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.
1994-01-01
Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.
The development of an interim generalized gate logic software simulator
NASA Technical Reports Server (NTRS)
Mcgough, J. G.; Nemeroff, S.
1985-01-01
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
ERIC Educational Resources Information Center
Scriven, Michael
2007-01-01
Noting that there has been extensive discussion of the relation of evaluation to: (1) research; (2) explanations (a.k.a. theory-driven, logic model, or realistic evaluation); and (3) recommendations, the author introduces: (4) prediction. He advocates that unlike the first three concepts, prediction is necessarily part of most kinds of evaluation,…
A reliable ground bounce noise reduction technique for nanoscale CMOS circuits
NASA Astrophysics Data System (ADS)
Sharma, Vijay Kumar; Pattanaik, Manisha
2015-11-01
Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.
NASA Technical Reports Server (NTRS)
Dimeff, J.
1972-01-01
Electric circuit to measure frequency of repetitive sinusoidal or rectangular wave is presented. Components of electric circuit and method of operation are explained. Application of circuit as tachometer for automobile is discussed.
Photomultiplier blanking circuit
NASA Technical Reports Server (NTRS)
Mcclenahan, J. O.
1972-01-01
Circuit for protecting photomultiplier equipment from current surges which occur when exposed to brilliant illumination is discussed. Components of circuit and details of operation are provided. Circuit diagram to show action of blanking pulse on zener diode is included.
Self-checking sequential circuit design using m-out-of-n codes
NASA Astrophysics Data System (ADS)
Busaba, F. Y.; Lala, P. K.
1993-01-01
A technique for designing sequential circuits which are totally self-checking for single stuck at faults is presented. This technique uses m-out-of-n codes for state assignments and for output encoding. The next stage logic and the output logic are implemented such that any stuck-at-fault will either create a single bit error or unidirectional multibit error at the output. The technique has been applied to MCNC benchmark circuits and the overhead is estimated.
Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits
NASA Technical Reports Server (NTRS)
Beagles, Grant; Winters, Kel; Eldin, A. G.
1992-01-01
A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.
Use of Fuzzy Logic Systems for Assessment of Primary Faults
NASA Astrophysics Data System (ADS)
Petrović, Ivica; Jozsa, Lajos; Baus, Zoran
2015-09-01
In electric power systems, grid elements are often subjected to very complex and demanding disturbances or dangerous operating conditions. Determining initial fault or cause of those states is a difficult task. When fault occurs, often it is an imperative to disconnect affected grid element from the grid. This paper contains an overview of possibilities for using fuzzy logic in an assessment of primary faults in the transmission grid. The tool for this task is SCADA system, which is based on information of currents, voltages, events of protection devices and status of circuit breakers in the grid. The function model described with the membership function and fuzzy logic systems will be presented in the paper. For input data, diagnostics system uses information of protection devices tripping, states of circuit breakers and measurements of currents and voltages before and after faults.
Black, Dolores A.; Robinson, William H.; Limbrick, Daniel B.; Black, Jeffrey D.; Wilcox, Ian Z.
2015-08-07
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. An accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. A small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. Furthermore, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.
Black, Dolores A.; Robinson, William H.; Limbrick, Daniel B.; Black, Jeffrey D.; Wilcox, Ian Z.
2015-08-07
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. An accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional modelmore » based on one double-exponential source can be incomplete. A small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. Furthermore, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.« less
Black, Dolores Archuleta; Robinson, William H.; Wilcox, Ian Zachary; Limbrick, Daniel B.; Black, Jeffrey D.
2015-08-07
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. Likewise, an accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. Furthermore, a small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. As a result, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.
Black, Dolores Archuleta; Robinson, William H.; Wilcox, Ian Zachary; Limbrick, Daniel B.; Black, Jeffrey D.
2015-08-07
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. Likewise, an accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventionalmore » model based on one double-exponential source can be incomplete. Furthermore, a small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. As a result, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.« less
Optical logic gates using binary decision diagram with mirrors
NASA Astrophysics Data System (ADS)
Chattopadhyay, Tanay
2013-12-01
Optical circuits of different logical operations using binary decision diagram (BDD) are proposed and described in this paper. A simple table-top model using plane mirrors based on this architecture has been shown in this manuscript. This model is the macroscopic form of micro-electromechanical (MEMS) optical switch, which is also described in this manuscript. Numerical simulations using torsion type micromirrors have been done to find its operational performance. The design is simple and easy to implement for higher bit also.
Feasibility study for a generalized gate logic software simulator
NASA Technical Reports Server (NTRS)
Mcgough, J. G.
1983-01-01
Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
1999-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.
Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs
NASA Astrophysics Data System (ADS)
Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.
2015-03-01
This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
NASA Astrophysics Data System (ADS)
Chen, Lei; Horiyama, Takashi; Nakamura, Yuichi; Kimura, Shinji
Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
2D photonic crystal logic gates based on self-collimated effect
NASA Astrophysics Data System (ADS)
Fan, Ranran; Yang, Xiulun; Meng, Xiangfeng; Sun, Xiaowen
2016-08-01
Four kinds of logic gates are proposed using interference between the self-collimated beams in photonic crystals, namely NOT, OR, AND and XOR gates, which can be used in the design of photonic integrated circuits. The radius of the splitter and the optical path difference between splitters are adjusted to produce certain phase difference between the reflected and transmitted beams, which may interfere constructively or destructively to realize logical operation. They have high contrast ratios and low power consumption, the extinction ratio between logic 1 and logic 0 for NOT and AND gates can reach 24.7 dB, 30 dB and 12.6 dB for the wavelength used by optical communication (1550 nm), respectively, which makes it potentially applicable for photonic integrated circuits.
FPGA-based gating and logic for multichannel single photon counting
Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G; Williams, Brian P; Schaake, Jason; Humble, Travis S
2012-01-01
We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)
NASA Technical Reports Server (NTRS)
Canaris, J.
1991-01-01
A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.
Barriers in Concurrent Separation Logic
NASA Astrophysics Data System (ADS)
Hobor, Aquinas; Gherghina, Cristian
We develop and prove sound a concurrent separation logic for Pthreads-style barriers. Although Pthreads barriers are widely used in systems, and separation logic is widely used for verification, there has not been any effort to combine the two. Unlike locks and critical sections, Pthreads barriers enable simultaneous resource redistribution between multiple threads and are inherently stateful, leading to significant complications in the design of the logic and its soundness proof. We show how our logic can be applied to a specific example program in a modular way. Our proofs are machine-checked in Coq.
Test generation for highly sequential circuits
NASA Astrophysics Data System (ADS)
Ghosh, Abhijit; Devadas, Srinivas; Newton, A. Richard
1989-08-01
We address the problem of generating test sequences for stuck-at faults in non-scan synchronous sequential circuits. We present a novel test procedure that exploits both the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit. In contrast to previous approaches, we decompose the problem of sequential test generation into three subproblems of combinational test generation, fault-free state justification and fault-free state differentiation. We describe fast algorithms for state justification and state differentiation using the ON-sets and OFF-sets of flip-flop inputs and primary outputs. The decomposition of the testing problems into three subproblems rather than the traditional two, performing the justification and differentiation steps on the fault free rather than the faulty machine and the use of efficient techniques for cube intersection results in significant performance improvements over previous approaches.
Function does not follow form in gene regulatory circuits
Payne, Joshua L.; Wagner, Andreas
2015-01-01
Gene regulatory circuits are to the cell what arithmetic logic units are to the chip: fundamental components of information processing that map an input onto an output. Gene regulatory circuits come in many different forms, distinct structural configurations that determine who regulates whom. Studies that have focused on the gene expression patterns (functions) of circuits with a given structure (form) have examined just a few structures or gene expression patterns. Here, we use a computational model to exhaustively characterize the gene expression patterns of nearly 17 million three-gene circuits in order to systematically explore the relationship between circuit form and function. Three main conclusions emerge. First, function does not follow form. A circuit of any one structure can have between twelve and nearly thirty thousand distinct gene expression patterns. Second, and conversely, form does not follow function. Most gene expression patterns can be realized by more than one circuit structure. And third, multifunctionality severely constrains circuit form. The number of circuit structures able to drive multiple gene expression patterns decreases rapidly with the number of these patterns. These results indicate that it is generally not possible to infer circuit function from circuit form, or vice versa. PMID:26290154
Engineering modular and orthogonal genetic logic gates for robust digital-like synthetic biology
Wang, Baojun; Kitney, Richard I; Joly, Nicolas; Buck, Martin
2011-01-01
Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ54-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts. PMID:22009040
Realization of a quantum Hamiltonian Boolean logic gate on the Si(001):H surface.
Kolmer, Marek; Zuzak, Rafal; Dridi, Ghassen; Godlewski, Szymon; Joachim, Christian; Szymonski, Marek
2015-08-01
The design and construction of the first prototypical QHC (Quantum Hamiltonian Computing) atomic scale Boolean logic gate is reported using scanning tunnelling microscope (STM) tip-induced atom manipulation on an Si(001):H surface. The NOR/OR gate truth table was confirmed by dI/dU STS (Scanning Tunnelling Spectroscopy) tracking how the surface states of the QHC quantum circuit on the Si(001):H surface are shifted according to the input logical status. PMID:26144212
Thermionic integrated circuit program: Final report
Wilde, D.K.; Lynn, D.K.; Hamilton, D.
1988-05-01
This report describes the development of an operational amplifier using radiation hardened Thermionic Integrated Circuits (TICs). The report is written as a tutorial to cover all aspects of the fabrication process and circuit development as well as the process and circuit modifications required to meet the integration requirements of the operational amplifier. Recent experimental results are discussed in which both devices and test circuit data are compared to theoretical computer code predictions. The development of compatible high-temperature thin-film resistors is also presented. Because the project is being terminated prior to the completion of the amplifier, suggestions are made for additional advance development.
Energy efficient circuit design using nanoelectromechanical relays
NASA Astrophysics Data System (ADS)
Venkatasubramanian, Ramakrishnan
Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS
A diagnostic expert system for digital circuits
NASA Astrophysics Data System (ADS)
Backlund, R. W.; Wilson, J. D.
1992-04-01
A scheme is presented for a diagnostic expert system which is capable of troubleshooting a faulty digital circuit or producing a reduced test vector set for a non-faulty digital circuit. It is based on practical fault-finding logic and utilizes artificial intelligence techniques. The program uses expert knowledge comprised of two components: that which is contained within the program in the form of rules and heuristics, and that which is derived from the circuit under test in the form of specific device information. Using both forward and backward tracking algorithms, signal paths comprised of device and gate interconnections are identified from each output pin to the primary input pins which have effect on them. Beginning at the output, the program proceeds to validate each device in each signal path by forward propagating test values through the device to the output, and backward propagating the same values to the primary inputs. All devices in the circuit are monitored for each test applied and their performance is recorded. Device or gate validation occurs when the recorded history shows that a device has been toggled successfully through all necessary states. When run on a circuit which does not contain a fault, the program determines a reduced test vector set for that circuit.
Delay test generation for synchronous sequential circuits
NASA Astrophysics Data System (ADS)
Devadas, Srinivas
1989-05-01
We address the problem of generating tests for delay faults in non-scan synchronous sequential circuits. Delay test generation for sequential circuits is a considerably more difficult problem than delay testing of combinational circuits and has received much less attention. In this paper, we present a method for generating test sequences to detect delay faults in sequential circuits using the stuck-at fault sequential test generator STALLION. The method is complete in that it will generate a delay test sequence for a targeted fault given sufficient CPU time, if such a sequence exists. We term faults for which no delay test sequence exists, under out test methodology, sequentially delay redundant. We describe means of eliminating sequential delay redundancies in logic circuits. We present a partial-scan methodology for enhancing the testability of difficult-to-test of untestable sequential circuits, wherein a small number of flip-flops are selected and made controllable/observable. The selection process guarantees the elimination of all sequential delay redundancies. We show that an intimate relationship exists between state assignment and delay testability of a sequential machine. We describe a state assignment algorithm for the synthesis of sequential machines with maximal delay fault testability. Preliminary experimental results using the test generation, partial-scan and synthesis algorithm are presented.
Parallel algorithm strategies for circuit simulation.
Thornquist, Heidi K.; Schiek, Richard Louis; Keiter, Eric Richard
2010-01-01
Circuit simulation tools (e.g., SPICE) have become invaluable in the development and design of electronic circuits. However, they have been pushed to their performance limits in addressing circuit design challenges that come from the technology drivers of smaller feature scales and higher integration. Improving the performance of circuit simulation tools through exploiting new opportunities in widely-available multi-processor architectures is a logical next step. Unfortunately, not all traditional simulation applications are inherently parallel, and quickly adapting mature application codes (even codes designed to parallel applications) to new parallel paradigms can be prohibitively difficult. In general, performance is influenced by many choices: hardware platform, runtime environment, languages and compilers used, algorithm choice and implementation, and more. In this complicated environment, the use of mini-applications small self-contained proxies for real applications is an excellent approach for rapidly exploring the parameter space of all these choices. In this report we present a multi-core performance study of Xyce, a transistor-level circuit simulation tool, and describe the future development of a mini-application for circuit simulation.
Fuzzy logic and coarse coding using programmable logic devices
NASA Astrophysics Data System (ADS)
Brooks, Geoffrey
2009-05-01
Naturally-occurring sensory signal processing algorithms, such as those that inspired fuzzy-logic control, can be integrated into non-naturally-occurring high-performance technology, such as programmable logic devices, to realize novel bio-inspired designs. Research is underway concerning an investigation into using field programmable logic devices (FPLD's) to implement fuzzy logic sensory processing. A discussion is provided concerning the commonality between bio-inspired fuzzy logic algorithms and coarse coding that is prevalent in naturally-occurring sensory systems. Undergraduate design projects using fuzzy logic for an obstacle-avoidance robot has been accomplished at our institution and other places; numerous other successful fuzzy logic applications can be found as well. The long-term goal is to leverage such biomimetic algorithms for future applications. This paper outlines a design approach for implementing fuzzy-logic algorithms into reconfigurable computing devices. This paper is presented in an effort to connect with others who may be interested in collaboration as well as to establish a starting point for future research.
Robust circuit & architecture design in the nanoscale regime
NASA Astrophysics Data System (ADS)
Ashraf, Rehman
Silicon based integrated circuit (IC) technology is approaching its physical limits. For sub 10nm technology nodes, the carbon nanotube (CNT) based field effect transistor has emerged as a promising device because of its excellent electronic properties. One of the major challenges faced by the CNT technology is the unwanted growth of metallic tubes. At present, there is no known CNT fabrication technology which allows the fabrication of 100% semiconducting CNTs. The presence of metallic tubes creates a short between the drain and source terminals of the transistor and has a detrimental impact on the delay, static power and yield of CNT based gates. This thesis will address the challenge of designing robust carbon nanotube based circuits in the presence of metallic tubes. For a small percentage of metallic tubes, circuit level solutions are proposed to increase the functional yield of CNT based gates in the presence of metallic tubes. Accurate analytical models with less than a 3% inaccuracy rate are developed to estimate the yield of CNT based circuit for a different percentage of metallic tubes and different drive strengths of logic gates. Moreover, a design methodology is developed for yield-aware carbon nanotube based circuits in the presence of metallic tubes using different CNFET transistor configurations. Architecture based on regular logic bricks with underlying hybrid CNFET configurations are developed which gives better trade-offs in terms of performance, power, and functional yield. In the case when the percentage of metallic tubes is large, the proposed circuit level techniques are not sufficient. Extra processing techniques must be applied to remove the metallic tubes. The tube removal techniques have trade-offs, as the removal process is not perfect and removes semiconducting tubes in addition to removing unwanted metallic tubes. As a result, stochastic removal of tubes from the drive and fanout gate(s) results in large variation in the performance of
Logic elements for reactor period meter
McDowell, William P.; Bobis, James P.
1976-01-01
Logic elements are provided for a reactor period meter trip circuit. For one element, first and second inputs are applied to first and second chopper comparators, respectively. The output of each comparator is O if the input applied to it is greater than or equal to a trip level associated with each input and each output is a square wave of frequency f if the input applied to it is less than the associated trip level. The outputs of the comparators are algebraically summed and applied to a bandpass filter tuned to f. For another element, the output of each comparator is applied to a bandpass filter which is tuned to f to give a sine wave of frequency f. The outputs of the filters are multiplied by an analog multiplier whose output is 0 if either input is 0 and a sine wave of frequency 2f if both inputs are a frequency f.
NASA Technical Reports Server (NTRS)
2005-01-01
A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true
Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell.
Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng
2016-07-01
Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future. PMID:27297542
Rapidly Reconfigurable All-Optical Universal Logic Gates
Goddard, L L; Kallman, J S; Bond, T C
2006-06-21
We present designs and simulations for a highly cascadable, rapidly reconfigurable, all-optical, universal logic gate. We will discuss the gate's expected performance, e.g. speed, fanout, and contrast ratio, as a function of the device layout and biasing conditions. The gate is a three terminal on-chip device that consists of: (1) the input optical port, (2) the gate selection port, and (3) the output optical port. The device can be built monolithically using a standard multiple quantum well graded index separate confinement heterostructure laser configuration. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog electrical or optical signal at the gate selection port. Specifically, the same gate can be selected to execute one of the 2 basic unary operations (NOT or COPY), or one of the 6 binary operations (OR, XOR, AND, NOR, XNOR, or NAND), or one of the many logic operations involving more than two inputs. The speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal modulation speed of a laser, which can be on the order of tens of GHz. The reprogrammable nature of the universal gate offers maximum flexibility and interchangeability for the end user since the entire application of a photonic integrated circuit built from cascaded universal logic gates can be changed simply by adjusting the gate selection port signals.
Kronberg, James W.
1992-01-01
A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable.
Kronberg, J.W.
1992-06-02
A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable. 2 figs.
NASA Technical Reports Server (NTRS)
Cleaveland, Rance; Luettgen, Gerald; Bushnell, Dennis M. (Technical Monitor)
2002-01-01
This paper presents the Logical Process Calculus (LPC), a formalism that supports heterogeneous system specifications containing both operational and declarative subspecifications. Syntactically, LPC extends Milner's Calculus of Communicating Systems with operators from the alternation-free linear-time mu-calculus (LT(mu)). Semantically, LPC is equipped with a behavioral preorder that generalizes Hennessy's and DeNicola's must-testing preorder as well as LT(mu's) satisfaction relation, while being compositional for all LPC operators. From a technical point of view, the new calculus is distinguished by the inclusion of: (1) both minimal and maximal fixed-point operators and (2) an unimple-mentability predicate on process terms, which tags inconsistent specifications. The utility of LPC is demonstrated by means of an example highlighting the benefits of heterogeneous system specification.
Kenny, A.
1985-01-01
In The Logic of Deterrence, Kenny presents a guide to the theory and ethics of the complicated subject of deterrence. Kenny begins by examining the necessary conditions for any war to be just and then applies these principles to the cases of limited and total nuclear war. He then critiques current deterrence policies of both East and West, concluding that they are based on a willingness to kill millions of innocent people and are morally wrong. In the final section of the book, Kenny offers proposals for nuclear disarmament. Charting a course ''between the illusory hopes of the multilateralists who seek disarmament by negotiating and the impractical idealism of those who call for immediate and total unilateral disarmament by the West,'' Kenny proposes a series of phased and partial unilateral steps by the West, coupled with pressure on the East to reciprocate.
Borresen, Jon; Lynch, Stephen
2012-01-01
In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034
Partial quantum logics revisited
NASA Astrophysics Data System (ADS)
Vetterlein, Thomas
2011-01-01
Partial Boolean algebras (PBAs) were introduced by Kochen and Specker as an algebraic model reflecting the mutual relationships among quantum-physical yes-no tests. The fact that not all pairs of tests are compatible was taken into special account. In this paper, we review PBAs from two sides. First, we generalise the concept, taking into account also those yes-no tests which are based on unsharp measurements. Namely, we introduce partial MV-algebras, and we define a corresponding logic. Second, we turn to the representation theory of PBAs. In analogy to the case of orthomodular lattices, we give conditions for a PBA to be isomorphic to the PBA of closed subspaces of a complex Hilbert space. Hereby, we do not restrict ourselves to purely algebraic statements; we rather give preference to conditions involving automorphisms of a PBA. We conclude by outlining a critical view on the logico-algebraic approach to the foundational problem of quantum physics.
Quantificational logic of context
Buvac, Sasa
1996-12-31
In this paper we extend the Propositional Logic of Context, to the quantificational (predicate calculus) case. This extension is important in the declarative representation of knowledge for two reasons. Firstly, since contexts are objects in the semantics which can be denoted by terms in the language and which can be quantified over, the extension enables us to express arbitrary first-order properties of contexts. Secondly, since the extended language is no longer only propositional, we can express that an arbitrary predicate calculus formula is true in a context. The paper describes the syntax and the semantics of a quantificational language of context, gives a Hilbert style formal system, and outlines a proof of the system`s completeness.
NASA Technical Reports Server (NTRS)
2003-01-01
The same software controlling autonomous and crew-assisted operations for the International Space Station (ISS) is enabling commercial enterprises to integrate and automate manual operations, also known as decision logic, in real time across complex and disparate networked applications, databases, servers, and other devices, all with quantifiable business benefits. Auspice Corporation, of Framingham, Massachusetts, developed the Auspice TLX (The Logical Extension) software platform to effectively mimic the human decision-making process. Auspice TLX automates operations across extended enterprise systems, where any given infrastructure can include thousands of computers, servers, switches, and modems that are connected, and therefore, dependent upon each other. The concept behind the Auspice software spawned from a computer program originally developed in 1981 by Cambridge, Massachusetts-based Draper Laboratory for simulating tasks performed by astronauts aboard the Space Shuttle. At the time, the Space Shuttle Program was dependent upon paper-based procedures for its manned space missions, which typically averaged 2 weeks in duration. As the Shuttle Program progressed, NASA began increasing the length of manned missions in preparation for a more permanent space habitat. Acknowledging the need to relinquish paper-based procedures in favor of an electronic processing format to properly monitor and manage the complexities of these longer missions, NASA realized that Draper's task simulation software could be applied to its vision of year-round space occupancy. In 1992, Draper was awarded a NASA contract to build User Interface Language software to enable autonomous operations of a multitude of functions on Space Station Freedom (the station was redesigned in 1993 and converted into the international venture known today as the ISS)
Japanese Logic Puzzles and Proof
ERIC Educational Resources Information Center
Wanko, Jeffrey J.
2009-01-01
An understanding of proof does not start in a high school geometry course. Rather, attention to logical reasoning throughout a student's school experience can help the development of proof readiness. In the spirit of problem solving, the author has begun to use some Japanese logic puzzles other than sudoku to help students develop additional…
Programmable Logic Controllers. Teacher Edition.
ERIC Educational Resources Information Center
Rauh, Bob; Kaltwasser, Stan
These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…
Molecular 'OR' and 'AND' logic gates integrated in a single molecule
NASA Astrophysics Data System (ADS)
Ami, S.; Hliwa, M.; Joachim, C.
2003-01-01
Based on the N electrodes elastic scattering quantum chemistry (NESQC) technique, an intramolecular circuit simulator is presented for the design of electronic logic functions integrated inside a single molecule interconnected to the N electrodes. Using molecular rectifier groups, a molecule-OR and a molecule-AND are designed, their current-voltage characteristics calculated and their logic response presented. Both the OR and AND molecules have approximatively the targeted function. The running current of the OR gate, 10 fA, is quite low and the AND gate works only in an output voltage mode. This forbids the design of larger logic functions inside a single molecule with molecular rectifiers.
Reconfigurable magnetic logic combined with non-volatile memory in silicon
NASA Astrophysics Data System (ADS)
Luo, Zhaochu; Zhang, Xiaozhong
Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.
Biosensors with Built-In Biomolecular Logic Gates for Practical Applications
Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh
2014-01-01
Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423
Biosensors with built-in biomolecular logic gates for practical applications.
Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh
2014-09-01
Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating "sense and act" schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423
Reconfigurable threshold logic gates with nanoscale DG-MOSFETs
NASA Astrophysics Data System (ADS)
Kaya, Savas; Hamed, Hesham F. A.; Ting, Darwin T.; Creech, Gregory
2007-10-01
The benefits in using double-gate (DG) MOSFETs as components of threshold logic gates (TLG) have been analyzed for the first time. A novel, variable-weight DG-TLG has also been proposed, which can greatly widen the range of reconfigurable functions accessible to users. Both fixed and variable-weight DG-TLG circuits operate correctly at a low supply voltage of 1.0 V, and outperform the conventional CMOS equivalents in terms of the most important metrics such as power, speed and area. It is found that variable-weight DG-TLG circuits with analog weight and threshold control have attractive features such as expanded TLG functionality, reduced transistor count, low programming voltages and power-scaling capability, particularly for circuits with four or fewer inputs.
Power optimization in logic isomers
NASA Technical Reports Server (NTRS)
Panwar, Ramesh; Rennels, David; Alkalaj, Leon
1993-01-01
Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.
Spintronic logic design methodology based on spin Hall effect-driven magnetic tunnel junctions
NASA Astrophysics Data System (ADS)
Kang, Wang; Wang, Zhaohao; Zhang, Youguang; Klein, Jacques-Olivier; Lv, Weifeng; Zhao, Weisheng
2016-02-01
Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau-Lifshitz-Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing.
Slime mould logic gates based on frequency changes of electrical potential oscillation.
Whiting, James G H; de Lacy Costello, Ben P J; Adamatzky, Andrew
2014-10-01
Physarum polycephalum is a large single amoeba cell, which in its plasmodial phase, forages and connects nearby food sources with protoplasmic tubes. The organism forages for food by growing these tubes towards detected foodstuff, this foraging behaviour is governed by simple rules of photoavoidance and chemotaxis. The electrical activity of the tubes oscillates, creating a peristaltic like action within the tubes, forcing cytoplasm along the lumen; the frequency of this oscillation controls the speed and direction of growth. External stimuli such as light and food cause changes in the oscillation frequency. We demonstrate that using these stimuli as logical inputs we can approximate logic gates using these tubes and derive combinational logic circuits by cascading the gates, with software analysis providing the output of each gate and determining the input of the following gate. Basic gates OR, AND and NOT were correct 90%, 77.8% and 91.7% of the time respectively. Derived logic circuits XOR, half adder and full adder were 70.8%, 65% and 58.8% accurate respectively. Accuracy of the combinational logic decreases as the number of gates is increased, however they are at least as accurate as previous logic approximations using spatial growth of P. polycephalum and up to 30 times as fast at computing the logical output. The results shown here demonstrate a significant advancement in organism-based computing, providing a solid basis for hybrid computers of the future. PMID:25102081
NASA Technical Reports Server (NTRS)
Johnson, Steven D.; Byers, Jerry W.; Martin, James A.
2012-01-01
A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.
Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation
NASA Astrophysics Data System (ADS)
Volkmann, M. H.; Sahu, A.; Fourie, C. J.; Mukhanov, O. A.
2013-01-01
We report the first experimental demonstration of recently proposed energy efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic, eliminating the dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ˜0.8 aJ/bit operation. Two types of demonstration eSFQ circuit, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA cm-2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing.
Closed terminologies in description logics
Weida, R.A. |
1996-12-31
We introduce a predictive concept recognition methodology for description logics based on a new closed terminology assumption. During knowledge engineering, our system adopts the standard open terminology assumption as it automatically classifies concept descriptions into a taxonomy via subsumption inferences. However, for applications like configuration, the terminology becomes fixed during problem solving. Then, closed terminology reasoning is more appropriate. In our interactive configuration application, a user incrementally specifies an individual computer system in collaboration with a configuration engine. Choices can be made in any order and at any level of abstraction. We distinguish between abstract and concrete concepts to formally define when an individual`s description may be considered finished. We also take advantage of the closed terminology assumption, together with the terminology`s subsumption-based organization, to efficiently track the types of systems and components consistent with current choices, infer additional constraints on current choices, and appropriately guide future choices. Thus, we can help focus the efforts of both user and configuration engine.
Effects of smoke on functional circuits
Tanaka, T.J.
1997-10-01
Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs.
Generalized Majority Logic Criterion to Analyze the Statistical Strength of S-Boxes
NASA Astrophysics Data System (ADS)
Hussain, Iqtadar; Shah, Tariq; Gondal, Muhammad Asif; Mahmood, Hasan
2012-05-01
The majority logic criterion is applicable in the evaluation process of substitution boxes used in the advanced encryption standard (AES). The performance of modified or advanced substitution boxes is predicted by processing the results of statistical analysis by the majority logic criteria. In this paper, we use the majority logic criteria to analyze some popular and prevailing substitution boxes used in encryption processes. In particular, the majority logic criterion is applied to AES, affine power affine (APA), Gray, Lui J, residue prime, S8 AES, Skipjack, and Xyi substitution boxes. The majority logic criterion is further extended into a generalized majority logic criterion which has a broader spectrum of analyzing the effectiveness of substitution boxes in image encryption applications. The integral components of the statistical analyses used for the generalized majority logic criterion are derived from results of entropy analysis, contrast analysis, correlation analysis, homogeneity analysis, energy analysis, and mean of absolute deviation (MAD) analysis.
G4-FETs as Universal and Programmable Logic Gates
NASA Technical Reports Server (NTRS)
Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin
2007-01-01
An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.
Integrating logic functions inside a single molecule
NASA Astrophysics Data System (ADS)
Stadler, R.; Ami, S.; Joachim, C.; Forshaw, M.
2004-04-01
In Stadler et al (2003 Nanotechnology 14 138), a scheme for a molecular memory was presented. It was based on the influence of the positions of chemical side-groups attached to aromatic molecules on the paths for electrons propagating through these molecules in the ballistic and tunnelling transport regimes. Here we extend this concept in the following ways. (i) A graphical method is derived from an electron scattering formalism based on a topological Hückel description, which allows us to estimate whether the electron transport between two electrodes attached to specific atomic sites in an arbitrary molecule is finite or zero at the Fermi level. (ii) The same scheme that was used for the implementation of the molecular memory is extended to logic functions, in particular a half-adder. (iii) A more realistic description of the chemical nature of the proposed intra-molecular circuits is achieved by using the elastic scattering quantum chemistry (ESQC) technique in an extended Hückel implementation and by specifying the side-groups as nitro-groups, which are rotated in order to feed the signal inputs into the computational circuit.
Zhao, Y G; O'Connell, N E; Yan, T
2016-06-01
Development of effective methane (CH) mitigation strategies for grazing sheep requires accurate prediction tools. The present study aimed to identify key parameters influencing enteric CH emissions and develop prediction equations for enteric CH emissions from sheep offered fresh grass. The data used were collected from 82 sheep offered fresh perennial ryegrass () as sole diets in 6 metabolism experiments (data from non-grass-only diets were not used). Sheep were from breeds of Highlander, Texel, Scottish Blackface, and Swaledale at the age of 5 to 18 mo and weighing from 24.5 to 62.7 kg. Grass was harvested daily from 6 swards on contrasting harvest dates (May to December). Before the commencement of each study, the experimental sward was harvested at a residual height of 4 cm and allowed to grow for 2 to 4 wk. The feeding trials commenced when the grass sward was suitable to zero grazing (average grass height = 15 cm), thus offering grass of a quality similar to what grazing animals would receive under routine grazing management. Sheep were housed in individual pens for 14 d and then moved to individual calorimeter chambers for 4 d. Feed intake, fecal and urine outputs, and CH emissions were measured during the final 4 d. Data were analyzed using the REML procedure to develop prediction equations for CH emissions. Linear and multiple prediction equations were developed using BW, DMI, GE intake (GEI), and grass chemical concentrations (DM, OM, water-soluble carbohydrates [WSC], NDF, ADF, nitrogen [N], GE, DE, and ME) as explanatory variables. The mean CH production was 21.1 g/kg DMI or 0.062 MJ/MJ GEI. Dry matter intake and GEI were much more accurate predictors for CH emissions than BW ( < 0.001, = 0.86 and = 0.87 vs. = 0.09, respectively). Adding grass DE and ME concentrations and grass nutrient concentrations (e.g., OM, N, GE, NDF, and WSC) to the relationships between DMI or GEI and CH emissions improved prediction accuracy with values increased to 0
Contradicting logics in everyday practice.
Kristiansen, Margrethe; Obstfelder, Aud; Lotherington, Ann Therese
2016-03-21
Purpose - Performance management is criticised as a direct challenge to the dominant logic of professionalism in health care organisations. The purpose of this paper is to report an ethnographic study that investigates how performance management and professionalism as contradicting logics are interpreted and implemented by managers and nurses in everyday practice within Norwegian nursing homes. Design/methodology/approach - The paper presents an analysis of 18 semistructured interviews and 100 hours of observation of managers and nurses from three nursing homes. The study draws on the institutional logic perspective as a theoretical framework. In the analysis, the authors searched for patterns of activities and interactions that reflected managers and nurses' coping strategies for handling contradicting logics. Qualitative content analysis was used to systematically code the data, supported by NVIVO software. Findings - The authors identified three forms of coping strategies: the adjustment of professionalism to standards, the reinforcement of professional flexibility and problem solving, and the strategic adoption of documentation. These patterns of activities and interactions reflect new organisational structures that allowed contradicting logics to co-exist. The study demonstrates that a new complex dimension of governing processes within nursing homes is the way in which managers and nurses handle the tension between contradicting logics in their daily work and clinicians' everyday practice. Originality/value - The study provides new insight into how managers and nurses reshape internal organisational structures to cope with contradicting logics in nursing homes. PMID:26964849
Fuzzy logic in control systems: Fuzzy logic controller. I, II
NASA Technical Reports Server (NTRS)
Lee, Chuen Chien
1990-01-01
Recent advances in the theory and applications of fuzzy-logic controllers (FLCs) are examined in an analytical review. The fundamental principles of fuzzy sets and fuzzy logic are recalled; the basic FLC components (fuzzification and defuzzification interfaces, knowledge base, and decision-making logic) are described; and the advantages of FLCs for incorporating expert knowledge into a control system are indicated. Particular attention is given to fuzzy implication functions, the interpretation of sentence connectives (and, also), compositional operators, and inference mechanisms. Applications discussed include the FLC-guided automobile developed by Sugeno and Nishida (1985), FLC hardware systems, FLCs for subway trains and ship-loading cranes, fuzzy-logic chips, and fuzzy computers.
Kral, M J
1994-01-01
Although suicide is not viewed as a mental disorder per se, it is viewed by many if not most clinicians, researchers, and lay people as a real or natural symptom of depression. It is at least most typically seen as the unfortunate, severe, yet logical end result of a chain of negative self-appraisals, negative events, and hopelessness. Extending an approach articulated by the early French sociologist Gabriel Tarde, in this paper I argue that suicide is merely an idea, albeit a very bad one, having more in common with societal beliefs and norms regarding such things as divorce, abortion, sex, politics, consumer behavior, and fashion. I make a sharp contrast between perturbation and lethality, concepts central to Edwin S. Shneidman's theory of suicide. Evidence supportive of suicide as an idea is discussed based on what we are learning from the study of history and culture, and about contagion/cluster phenomena, media/communication, and choice of method. It is suggested that certain individuals are more vulnerable to incorporate the idea and act of suicide into their concepts of self, based on the same principles by which ideas are spread throughout society. Just as suicide impacts on society, so does society impact on suicide. PMID:7825197
NASA Technical Reports Server (NTRS)
Smith, David E.; Jonsson, Ari K.; Clancy, Daniel (Technical Monitor)
2001-01-01
In recent years, Graphplan style reachability analysis and mutual exclusion reasoning have been used in many high performance planning systems. While numerous refinements and extensions have been developed, the basic plan graph structure and reasoning mechanisms used in these systems are tied to the very simple STRIPS model of action. In 1999, Smith and Weld generalized the Graphplan methods for reachability and mutex reasoning to allow actions to have differing durations. However, the representation of actions still has some severe limitations that prevent the use of these techniques for many real-world planning systems. In this paper, we 1) separate the logic of reachability from the particular representation and inference methods used in Graphplan, and 2) extend the notions of reachability and mutual exclusion to more general notions of time and action. As it turns out, the general rules for mutual exclusion reasoning take on a remarkably clean and simple form. However, practical instantiations of them turn out to be messy, and require that we make representation and reasoning choices.
Ball, Don G.
1992-01-01
A charge regulation circuit provides regulation of an unregulated voltage supply in the range of 0.01%. The charge regulation circuit is utilized in a preferred embodiment in providing regulated voltage for controlling the operation of a laser.
NASA Astrophysics Data System (ADS)
Young, T.
This book is intended to be used as a textbook in a one-semester course at a variety of levels. Because of self-study features incorporated, it may also be used by practicing electronic engineers as a formal and thorough introduction to the subject. The distinction between linear and digital integrated circuits is discussed, taking into account digital and linear signal characteristics, linear and digital integrated circuit characteristics, the definitions for linear and digital circuits, applications of digital and linear integrated circuits, aspects of fabrication, packaging, and classification and numbering. Operational amplifiers are considered along with linear integrated circuit (LIC) power requirements and power supplies, voltage and current regulators, linear amplifiers, linear integrated circuit oscillators, wave-shaping circuits, active filters, DA and AD converters, demodulators, comparators, instrument amplifiers, current difference amplifiers, analog circuits and devices, and aspects of troubleshooting.
Hayashi, Kenta; Gotoda, Hiroshi; Gentili, Pier Luigi
2016-05-01
The convective motions within a solution of a photochromic spiro-oxazine being irradiated by UV only on the bottom part of its volume, give rise to aperiodic spectrophotometric dynamics. In this paper, we study three nonlinear properties of the aperiodic time series: permutation entropy, short-term predictability and long-term unpredictability, and degree distribution of the visibility graph networks. After ascertaining the extracted chaotic features, we show how the aperiodic time series can be exploited to implement all the fundamental two-inputs binary logic functions (AND, OR, NAND, NOR, XOR, and XNOR) and some basic arithmetic operations (half-adder, full-adder, half-subtractor). This is possible due to the wide range of states a nonlinear system accesses in the course of its evolution. Therefore, the solution of the convective photochemical oscillator results in hardware for chaos-computing alternative to conventional complementary metal-oxide semiconductor-based integrated circuits. PMID:27249942
NASA Astrophysics Data System (ADS)
Hayashi, Kenta; Gotoda, Hiroshi; Gentili, Pier Luigi
2016-05-01
The convective motions within a solution of a photochromic spiro-oxazine being irradiated by UV only on the bottom part of its volume, give rise to aperiodic spectrophotometric dynamics. In this paper, we study three nonlinear properties of the aperiodic time series: permutation entropy, short-term predictability and long-term unpredictability, and degree distribution of the visibility graph networks. After ascertaining the extracted chaotic features, we show how the aperiodic time series can be exploited to implement all the fundamental two-inputs binary logic functions (AND, OR, NAND, NOR, XOR, and XNOR) and some basic arithmetic operations (half-adder, full-adder, half-subtractor). This is possible due to the wide range of states a nonlinear system accesses in the course of its evolution. Therefore, the solution of the convective photochemical oscillator results in hardware for chaos-computing alternative to conventional complementary metal-oxide semiconductor-based integrated circuits.
Electrical Circuits and Water Analogies
ERIC Educational Resources Information Center
Smith, Frederick A.; Wilson, Jerry D.
1974-01-01
Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)
NASA Technical Reports Server (NTRS)
Bohning, Oliver D. (Inventor)
1976-01-01
A unique, two-node sense circuit is disclosed. The circuit includes a bridge comprised of resistance elements and a differential amplifier. The two-node circuit is suitably adapted to be arranged in an array comprised of a plurality of discrete bridge-amplifiers which can be selectively energized. The circuit is arranged so as to form a configuration with minimum power utilization and a reduced number of components and interconnections therebetween.
Voltage-driven spintronic logic gates in graphene nanoribbons
Zhang, WenXing
2014-01-01
Electronic devices lose efficacy due to quantum effect when the line-width of gate decreases to sub-10 nm. Spintronics overcome this bottleneck and logic gates are building blocks of integrated circuits. Thus, it is essential to control electronic transport of opposite spins for designing a spintronic logic gate, and spin-selective semiconductors are natural candidates such as zigzag graphene nanoribbons (ZGNR) whose edges are ferromagnetically ordered and antiferromagnetically coupled with each other. Moreover, it is necessary to sandwich ZGNR between two ferromagnetic electrodes for making a spintronic logic gate and also necessary to apply magnetic field to change the spin orientation for modulating the spin transport. By first principle calculations, we propose a method to manipulate the spin transport in graphene nanoribbons with electric field only, instead of magnetic field. We find that metal gates with specific bias nearby edges of ZGNR build up an in-plane inhomogeneous electric field which modulates the spin transport by localizing the spin density in device. The specific manipulation of spin transport we have proposed doesn't need spin-charge conversion for output and suggests a possible base for designing spintronic integrated circuit in atomic scale. PMID:25204808
Majority logic gate for 3D magnetic computing.
Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus
2014-08-22
For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities. PMID:25073985
Majority logic gate for 3D magnetic computing
NASA Astrophysics Data System (ADS)
Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus
2014-08-01
For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states ‘0’ and ‘1.’ Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.
Periodic binary sequence generators: VLSI circuits considerations
NASA Technical Reports Server (NTRS)
Perlman, M.
1984-01-01
Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.
Electrical Circuit Simulation Code
2001-08-09
Massively-Parallel Electrical Circuit Simulation Code. CHILESPICE is a massively-arallel distributed-memory electrical circuit simulation tool that contains many enhanced radiation, time-based, and thermal features and models. Large scale electronic circuit simulation. Shared memory, parallel processing, enhance convergence. Sandia specific device models.
Treu, C.A. Jr.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.
Treu, Jr., Charles A.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.
Knowledge representation in fuzzy logic
NASA Technical Reports Server (NTRS)
Zadeh, Lotfi A.
1989-01-01
The author presents a summary of the basic concepts and techniques underlying the application of fuzzy logic to knowledge representation. He then describes a number of examples relating to its use as a computational system for dealing with uncertainty and imprecision in the context of knowledge, meaning, and inference. It is noted that one of the basic aims of fuzzy logic is to provide a computational framework for knowledge representation and inference in an environment of uncertainty and imprecision. In such environments, fuzzy logic is effective when the solutions need not be precise and/or it is acceptable for a conclusion to have a dispositional rather than categorical validity. The importance of fuzzy logic derives from the fact that there are many real-world applications which fit these conditions, especially in the realm of knowledge-based systems for decision-making and control.
Fuzzy logic and neural networks
Loos, J.R.
1994-11-01
Combine fuzzy logic`s fuzzy sets, fuzzy operators, fuzzy inference, and fuzzy rules - like defuzzification - with neural networks and you can arrive at very unfuzzy real-time control. Fuzzy logic, cursed with a very whimsical title, simply means multivalued logic, which includes not only the conventional two-valued (true/false) crisp logic, but also the logic of three or more values. This means one can assign logic values of true, false, and somewhere in between. This is where fuzziness comes in. Multi-valued logic avoids the black-and-white, all-or-nothing assignment of true or false to an assertion. Instead, it permits the assignment of shades of gray. When assigning a value of true or false to an assertion, the numbers typically used are {open_quotes}1{close_quotes} or {open_quotes}0{close_quotes}. This is the case for programmed systems. If {open_quotes}0{close_quotes} means {open_quotes}false{close_quotes} and {open_quotes}1{close_quotes} means {open_quotes}true,{close_quotes} then {open_quotes}shades of gray{close_quotes} are any numbers between 0 and 1. Therefore, {open_quotes}nearly true{close_quotes} may be represented by 0.8 or 0.9, {open_quotes}nearly false{close_quotes} may be represented by 0.1 or 0.2, and {close_quotes}your guess is as good as mine{close_quotes} may be represented by 0.5. The flexibility available to one is limitless. One can associate any meaning, such as {open_quotes}nearly true{close_quotes}, to any value of any granularity, such as 0.9999. 2 figs.
Heat exchanger expert system logic
NASA Technical Reports Server (NTRS)
Cormier, R.
1988-01-01
The reduction is described of the operation and fault diagnostics of a Deep Space Network heat exchanger to a rule base by the application of propositional calculus to a set of logic statements. The value of this approach lies in the ease of converting the logic and subsequently implementing it on a computer as an expert system. The rule base was written in Process Intelligent Control software.
NASA Astrophysics Data System (ADS)
Wang, Tiansi; Pei, Lei; Wang, Tingting; Lu, Rengui; Zhu, Chunbo
2016-01-01
Effective capacity-loss diagnosis and life-time prediction are the foundations of battery second-use technology and will play an important role in the development of the new energy industry. Of the two, the capacity-loss diagnostic, as a precondition of the life-time prediction, needs to be studied first. Performing a capacity-loss diagnosis for an aging cell consists of finding the decisive degradation mechanisms for the cell's capacity degradation. Because a cell's capacity just equals the span of the open-circuit voltage (OCV), when suspect degradation mechanisms affect a cell's capacity, they will leave corresponding and particular clues in the OCV curve. Taking a cell's OCV as the diagnostic indicator, a multi-mechanistic and non-destructive diagnostic method is developed in this paper. To establish an unambiguous relationship between OCV changes and the combinations of the decisive mechanisms, all the possible OCV changes under various aging situations are systematically analyzed based on a novel simultaneous coordinate system, in which the effects of each suspect capacity-loss mechanism on the OCV curve can be clearly represented. As a summary of the analysis results, a straightforward diagnostic flowchart is presented. By following the flowchart, an aging cell can be diagnosed within three steps by observation of the OCV changes.
CIRCUITS FOR CURRENT MEASUREMENTS
Cox, R.J.
1958-11-01
Circuits are presented for measurement of a logarithmic scale of current flowing in a high impedance. In one form of the invention the disclosed circuit is in combination with an ionization chamber to measure lonization current. The particular circuit arrangement lncludes a vacuum tube having at least one grid, an ionization chamber connected in series with a high voltage source and the grid of the vacuum tube, and a d-c amplifier feedback circuit. As the ionization chamber current passes between the grid and cathode of the tube, the feedback circuit acts to stabilize the anode current, and the feedback voltage is a measure of the logaritbm of the ionization current.
Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition
NASA Astrophysics Data System (ADS)
Aghasi, Hamidreza; Iraei, Rouhollah Mousavi; Naeemi, Azad; Afshari, Ehsan
2016-05-01
We present a new circuit for non-Boolean recognition of binary images. Employing all-spin logic (ASL) devices, we design logic comparators and non-Boolean decision blocks for compact and efficient computation. By manipulation of fan-in number in different stages of the circuit, the structure can be extended for larger training sets or larger images. Operating based on the mainly similarity idea, the system is capable of constructing a mean image and compare it with a separate input image within a short decision time. Taking advantage of the non-volatility of ASL devices, the proposed circuit is capable of hybrid memory/logic operation. Compared with existing CMOS pattern recognition circuits, this work achieves a smaller footprint, lower power consumption, faster decision time and a lower operational voltage. To the best of our knowledge, this is the first fully spin-based complete pattern recognition circuit demonstrated using spintronic devices.
Material Targets for Scaling All-Spin Logic
NASA Astrophysics Data System (ADS)
Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.
2016-01-01
All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.
Logic implementations using a single nanoparticle-protein hybrid.
Medalsy, Izhar; Klein, Michael; Heyman, Arnon; Shoseyov, Oded; Remacle, F; Levine, R D; Porath, Danny
2010-06-01
A Set-Reset machine is the simplest logic circuit with a built-in memory. Its output is a (nonlinear) function of the input and of the state stored in the machine's memory. Here, we report a nanoscale Set-Reset machine operating at room temperature that is based on a 5-nm silicon nanoparticle attached to the inner pore of a stable circular protein. The nanoparticle-protein hybrid can also function as a balanced ternary multiplier. Conductive atomic force microscopy is used to implement the logic input and output operations, and the processing of the logic Set and Reset operations relies on the finite capacitance of the nanoparticle provided by the good electrical isolation given by the protein, thus enabling stability of the logic device states. We show that the machine can be cycled, such that in every successive cycle, the previous state in the memory is retained as the present state. The energy cost of one cycle of computation is minimized to the cost of charging this state. PMID:20400968
Modeling and optimization of ultra high speed devices and circuits
Jandaghi-Semnani, M.
1989-01-01
This thesis consists of two parts. In part one, we have developed an optimization scheme for designing submicron metal-oxide-semiconductor field effect transistors (MOSFETs). The scheme, which is based on the concepts of a mathematical programming problem, considers all the necessary performance and reliability issues and attempts to approach a desired set of target values. The modified pattern search method is used to implement the optimization scheme selected in this work. Simulated results have been compared with experimental data, and excellent agreement has been observed. Using the optimization scheme, a 0.6 {mu}m channel length MOSFET for possible dynamic random access memory (DRAM) applications has been designed. The other part of this thesis is devoted to the design of an ultra-fast 8 x 8-bit multiplier/accumulator circuit based on a resonant tunneling transistor (RTT) technology. The multiplier circuit has a parallel architecture and uses the carry save adder technique. The design of all the logic gates of the multiplier/accumulator circuit is based on the three logics: NAND, NOR, and NOT. The number of transistors applied in the RTT circuit is 2371, and the active chip area is about 0.30mm{sup 2}. The multiplier speed is 79 ps with an average power dissipation of 2.28 miliwatts (mW). The clock signals required for the operation of the chip are generated by a clock driver circuit which was designed by a ring oscillator and a binary counter circuit.
Application of linear logic to simulation
NASA Astrophysics Data System (ADS)
Clarke, Thomas L.
1998-08-01
Linear logic, since its introduction by Girard in 1987 has proven expressive and powerful. Linear logic has provided natural encodings of Turing machines, Petri nets and other computational models. Linear logic is also capable of naturally modeling resource dependent aspects of reasoning. The distinguishing characteristic of linear logic is that it accounts for resources; two instances of the same variable are considered differently from a single instance. Linear logic thus must obey a form of the linear superposition principle. A proportion can be reasoned with only once, unless a special operator is applied. Informally, linear logic distinguishes two kinds of conjunction, two kinds of disjunction, and also introduces a modal storage operator that explicitly indicates propositions that can be reused. This paper discuses the application of linear logic to simulation. A wide variety of logics have been developed; in addition to classical logic, there are fuzzy logics, affine logics, quantum logics, etc. All of these have found application in simulations of one sort or another. The special characteristics of linear logic and its benefits for simulation will be discussed. Of particular interest is a connection that can be made between linear logic and simulated dynamics by using the concept of Lie algebras and Lie groups. Lie groups provide the connection between the exponential modal storage operators of linear logic and the eigen functions of dynamic differential operators. Particularly suggestive are possible relations between complexity result for linear logic and non-computability results for dynamical systems.
Micromagnetic simulation of exploratory magnetic logic device with missing corner defect
NASA Astrophysics Data System (ADS)
Yang, Xiaokuo; Cai, Li; Zhang, Bin; Cui, Huanqing; Zhang, Mingliang
2015-11-01
Magnetic film nanostructures are attractive components of nonvolatile magnetoresistive memories and nanomagnet logic circuits. Recently, we studied switching properties (i.e., null logic preserving) of rectangle shape nanomagnet subjected to fabrication imperfections. Specifically, we presented typical missing corner material-related imperfections and adopted an isosceles triangle to model this defect for nanomagnets. Micromagnetic simulation shows that this kind of imperfections modeling method agrees well with previous experimental observations. Using the proposed defect modeling scheme, we investigate in detail the switching characteristics of different defective stand-alone and coupled nanomagnets. The results suggest that the state transition of defective nanomagnet element highly depends on defect type and device's aspect ratio, and the defect type Bd needs the largest coercive field, while the defect type D requires the largest null field for switching. These findings can provide key technical parameters and guides for nanomagnet logic circuit design.
Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices
NASA Astrophysics Data System (ADS)
Cricchio, Dario; Fiordilino, Emilio
2016-01-01
We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device.
Wavelet analysis and HHG in nanorings: their applications in logic gates and memory mass devices.
Cricchio, Dario; Fiordilino, Emilio
2016-01-28
We study the application of one nanoring driven by a laser field in different states of polarization in logic circuits. In particular we show that assigning Boolean values to different states of the incident laser field and to the emitted signals, we can create logic gates such as OR, XOR and AND. We also show the possibility of making logic circuits such as half-adder and full-adder using one and two nanorings respectively. Using two nanorings we made the Toffoli gate. Finally we use the final angular momentum acquired by the electron to store information and hence show the possibility of using an array of nanorings as a mass memory device. PMID:26662194
An efficient current-based logic cell model for crosstalk delay analysis
NASA Astrophysics Data System (ADS)
Nazarian, Shahin; Das, Debasish
2013-04-01
Logic cell modelling is an important component in the analysis and design of CMOS integrated circuits, mostly due to nonlinear behaviour of CMOS cells with respect to the voltage signal at their input and output pins. A current-based model for CMOS logic cells is presented, which can be used for effective crosstalk noise and delta delay analysis in CMOS VLSI circuits. Existing current source models are expensive and need a new set of Spice-based characterisation, which is not compatible with typical EDA tools. In this article we present Imodel, a simple nonlinear logic cell model that can be derived from the typical cell libraries such as NLDM, with accuracy much higher than NLDM-based cell delay models. In fact, our experiments show an average error of 3% compared to Spice. This level of accuracy comes with a maximum runtime penalty of 19% compared to NLDM-based cell delay models on medium-sized industrial designs.
NASA Astrophysics Data System (ADS)
Proskuryakov, K. N.; Fedorov, A. I.; Zaporozhets, M. V.
2015-08-01
The accident at the Japanese Fukushima Daiichi nuclear power plant (NPP) caused by an earthquake showed the need of taking further efforts aimed at improving the design and engineering solutions for ensuring seismic resistance of NPPs with due regard to mutual influence of the dynamic processes occurring in the NPP building structures and process systems. Resonance interaction between the vibrations of NPP equipment and coolant pressure pulsations leads to an abnormal growth of dynamic stresses in structural materials, accelerated exhaustion of equipment service life, and increased number of sudden equipment failures. The article presents the results from a combined calculation-theoretical and experimental substantiation of mutual amplification of two kinds of external periodic loads caused by rotation of the reactor coolant pump (RCP) rotor and an earthquake. The data of vibration measurements at an NPP are presented, which confirm the predicted multiple amplification of vibrations in the steam generator and RCP at a certain combination of coolant thermal-hydraulic parameters. It is shown that the vibration frequencies of the main equipment may fall in the frequency band corresponding to the maximal values in the envelope response spectra constructed on the basis of floor accelerograms. The article presents the results from prediction of conditions under which vibroacoustic resonances with external periodic loads take place, which confirm the occurrence of additional earthquake-induced multiple growth of pressure pulsation intensity in the steam generator at the 8.3 Hz frequency and additional multiple growth of vibrations of the RCP and the steam generator cold header at the 16.6 Hz frequency. It is shown that at the elastic wave frequency equal to 8.3 Hz in the coolant, resonance occurs with the frequency of forced vibrations caused by the rotation of the RCP rotor. A conclusion is drawn about the possibility of exceeding the design level of equipment vibrations
Unit testing-based approach for reconfigurable logic controllers verification
NASA Astrophysics Data System (ADS)
Doligalski, Michał; Tkacz, Jacek; Bukowiec, Arkadiusz; Gratkowski, Tomasz
2015-09-01
The paper presents unit testing-based approach to FPGA design in-circuit verification. Presented methodology is dedicated to modular reconfigurable logic controllers, but other ip-cores and systems can be verified as well. The speed and reproducibility of tests is key for rapid system prototyping, where the quality and reliability of the system is significance. Typically FPGA are programmed by means single (full) bitstream. Specific devices are able to be reconfigured partially. Usually the partial reconfiguration is a part of the design functionality. It enables the minimization of used resources or provides specific functionality like system adaptation. The paper presents the use of the partial reconfiguration as a toll for the designer. The unit testing approach well know form software engineering was adopted to modular logic controllers development. The simulation process results waveform files, the waveform can be used for synthesizable test bench generation.
Novel latch for adiabatic quantum-flux-parametron logic
Takeuchi, Naoki Yamanashi, Yuki; Yoshikawa, Nobuyuki; Ortlepp, Thomas
2014-03-14
We herein propose the quantum-flux-latch (QFL) as a novel latch for adiabatic quantum-flux-parametron (AQFP) logic. A QFL is very compact and compatible with AQFP logic gates and can be read out in one clock cycle. Simulation results revealed that the QFL operates at 5 GHz with wide parameter margins of more than ±22%. The calculated energy dissipation was only ∼0.1 aJ/bit, which yields a small energy delay product of 20 aJ·ps. We also designed shift registers using QFLs to demonstrate more complex circuits with QFLs. Finally, we experimentally demonstrated correct operations of the QFL and a 1-bit shift register (a D flip-flop)
Thermally reliable clocked non-volatile spin wave logic device
NASA Astrophysics Data System (ADS)
Dutta, Sourav; Nikonov, Dmitri; Manipatruni, Sasikanth; Young, Ian; Naeemi, Azad
The possibility of utilizing spin waves for information transmission and computation has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits. Here, we present a comprehensive scheme for building a thermally reliable clocked non-volatile spin wave logic device (SWLD) by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, exploiting the magneto-electric effect for spin wave transmission, detection and non-volatile memory, utilizing the phase of the spin wave as information token, ensuring phase-dependent deterministic switching of the magnetoelectric spin wave detector in the presence of thermal noise via compensation of demagnetization and a novel clocking scheme that ensures sequential transmission of information in a cascaded SWLD and non- reciprocity
Rationally designed logic integration of regulatory signals in mammalian cells
NASA Astrophysics Data System (ADS)
Leisner, Madeleine; Bleris, Leonidas; Lohmueller, Jason; Xie, Zhen; Benenson, Yaakov
2010-09-01
Molecular-level information processing is essential for `smart' in vivo nanosystems. Natural molecular computing, such as the regulation of messenger RNA (mRNA) synthesis by special proteins called transcription factors, has inspired engineered systems that can control the levels of mRNA with certain combinations of transcription factors. Here, we show an alternative approach to achieving general-purpose control of mRNA and protein levels by logic integration of transcription factor input signals in mammalian cells. The transcription factors regulate synthetic genes coding for small regulatory RNAs (called microRNAs), which, in turn, control the mRNA of interest (the output) via an RNA interference pathway. The simplicity of these modular interactions makes it possible, in theory, to implement any arbitrary logic relation between the transcription factors and the output. We construct, test and optimize increasingly complex circuits with up to three transcription factor inputs, establishing a platform for in vivo molecular computing.
Memristive Sisyphus circuit for clock signal generation
Pershin, Yuriy V.; Shevchenko, Sergey N.; Nori, Franco
2016-01-01
Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as “dripping ants” or drops from leaky faucets. PMID:27199243
TRIAC/SCR proportional control circuit
Hughes, Wallace J.
1999-01-01
A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.
TRIAC/SCR proportional control circuit
Hughes, W.J.
1999-04-06
A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.
Memristive Sisyphus circuit for clock signal generation.
Pershin, Yuriy V; Shevchenko, Sergey N; Nori, Franco
2016-01-01
Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as "dripping ants" or drops from leaky faucets. PMID:27199243
Memristive Sisyphus circuit for clock signal generation
NASA Astrophysics Data System (ADS)
Pershin, Yuriy V.; Shevchenko, Sergey N.; Nori, Franco
2016-05-01
Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as “dripping ants” or drops from leaky faucets.
NASA Astrophysics Data System (ADS)
Eriguchi, Koji
2014-10-01
An increasing demand for high performance field-effect transistors (FETs) leads to the aggressive critical dimension shrinkage and the currently-emerging three dimensional (3D) geometry. Plasma processing is widely used also in the scaled- and 3D-FET (e.g. FinFET) manufacturing, where precise control of the reaction on the (sidewall) surfaces is a prime issue. In this study, damage creation mechanism during plasma etching--plasma-induced physical damage (PPD)--was investigated in such structures on the basis of the PPD range theory, atomistic simulations, and experiments. Compared to PPD in planar FETs (e.g. Si recess [2,3]), a stochastic modeling and atomistic simulations predicted that, during etching of ``fins'' in a 3D-FET, the following two mechanisms are responsible for damage creation in addition to an ion impact on the sidewall at an oblique incident angle: 1) incoming ions penetrate into the Si substrate and undergo scattering by Si atoms in the lateral direction even if the incident angle is normal to the surface and 2) some of Si atoms and ions sputtered at the surface being etched impact on the sidewall with energies sufficient to break Si-Si bonds. These straggling and sputtering processes are stochastic and fundamental, thus, result in 3D structure damage (``fin-damage''). The ``fin-damage'' induced by straggling was modeled by the PPD range theory. Molecular dynamics simulations clarified the mechanisms under the various plasma conditions. Quantum mechanical calculations showed that created defect structures play the role of a carrier trap site, which was experimentally verified by an electrical measurement. Since they are intrinsic natures of etching, both straggling and sputtering noted here should be implemented to design a low-damage etching process. This work was supported in part by Grant-in-Aid for Scientific Research (B) 23360321 from JSPS and STARC project.
Design structure for in-system redundant array repair in integrated circuits
Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.
2008-11-25
A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.
Equivalent Circuit Modeling of Hysteresis Motors
Nitao, J J; Scharlemann, E T; Kirkendall, B A
2009-08-31
We performed a literature review and found that many equivalent circuit models of hysteresis motors in use today are incorrect. The model by Miyairi and Kataoka (1965) is the correct one. We extended the model by transforming it to quadrature coordinates, amenable to circuit or digital simulation. 'Hunting' is an oscillatory phenomenon often observed in hysteresis motors. While several works have attempted to model the phenomenon with some partial success, we present a new complete model that predicts hunting from first principles.
Chain Of Test Contacts For Integrated Circuits
NASA Technical Reports Server (NTRS)
Lieneweg, Udo
1989-01-01
Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.
Heuristics and criteria for constructing logical patterns in data
NASA Astrophysics Data System (ADS)
Antamoshkin, A. N.; Masich, I. S.; Kuzmich, R. I.
2015-10-01
The article considers various optimization models for constructing patterns in the method of logical analysis of data. Application techniques of the proposed models are specified and comparison of their classification against the accuracy on the task of predicting complications of myocardial infarction is provided
Superconducting Complementary Output Switching Logic Operating at 10 - 18 GHz
NASA Astrophysics Data System (ADS)
Jeffery, Mark; van Duzer, T.; Perold, Willem
1998-03-01
We have developed a new type of superconducting voltage-state logic called Complementary Output Switching Logic (COSL)(M. Jeffery, W. Perold, and T. Van Duzer, Appl. Phys. Lett., 69) (18), 2746 (1996). The basic COSL gates have been demonstrated at 10 GHz and complex 2-bit encoder circuits have operated at 5 - 8 GHz. The COSL gates have extremely low power dissipation, of order 10 μW/gate, and we have measured bit error rates less than 10-12 at 2 GHz. For these results we used the HYPRES 1 kA/cm^2 critical current density Nb Josephson fabrication process. In the present work we describe our recent test results using the new HYPRES 2.5 kA/cm^2 process. The increased critical current density process significantly improves the switching speed of the COSL devices. We will describe the Monte Carlo method used to optimize the COSL gates for 20 - 30 GHz operation, and the optimal circuit layouts including moats, or ground plane holes, to shield the circuits from trapped magnetic flux. Experimental test results will be presented for the basic COSL devices operating at 10 - 18 GHz. These are the fastest superconducting voltage-state logic devices ever reported, and may have many applications in low power ultra-high-speed digital systems of the future.
Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling
NASA Astrophysics Data System (ADS)
Lent, Craig S.; Liu, Mo; Lu, Yuhui
2006-08-01
We examine power dissipation in different clocking schemes for molecular quantum-dot cellular automata (QCA) circuits. 'Landauer clocking' involves the adiabatic transition of a molecular cell from the null state to an active state carrying data. Cell layout creates devices which allow data in cells to interact and thereby perform useful computation. We perform direct solutions of the equation of motion for the system in contact with the thermal environment and see that Landauer's Principle applies: one must dissipate an energy of at least kBT per bit only when the information is erased. The ideas of Bennett can be applied to keep copies of the bit information by echoing inputs to outputs, thus embedding any logically irreversible circuit in a logically reversible circuit, at the cost of added circuit complexity. A promising alternative which we term 'Bennett clocking' requires only altering the timing of the clocking signals so that bit information is simply held in place by the clock until a computational block is complete, then erased in the reverse order of computation. This approach results in ultralow power dissipation without additional circuit complexity. These results offer a concrete example in which to consider recent claims regarding the fundamental limits of binary logic scaling.
Source circuit design considerations
NASA Astrophysics Data System (ADS)
Noel, G. T.
1983-11-01
The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.
Source circuit design considerations
NASA Technical Reports Server (NTRS)
Noel, G. T.
1983-01-01
The cost of several circuit configurations for large (5MW) array fields were investigated to assess the relative costs of high and low voltage configurations. Three source circuit NOC voltages were evaluated: 400V (ungrounded), 800V (+ or 400V center grounded), and 2000V (+ or - 1000V center grounded). Four source circuit configurations were considered for each of the three NOC voltages. The configurations correspond to source circuit currents of 15, 30, 45, and 60 amperes, respectively. Conceptual layouts for 5MW building blocks for each of the above configurations were developed. The designs were optimized to minimize BOS electrical and structural costs. Only the BOS electrical costs were evaluated. The designs were broken down into the following elements for cost: (1) basic source circuit intermodule wiring, bypass diodes and associated hardware, source circuit to J-Box wiring, etc; (2) J-Box blocking diodes, varistors, heat sinks, and housing; (3) disconnects source circuit disconnects, fuses, and housing; (4) bus cabling J-Box to PCU interface wiring, and trenching; (5) interface bus bar, group disconnects, and fuses; and (6) fault detection shunts, signal wire, electronics, and alarm. It is concluded that high voltage low current circuits are not economical, at higher currents high and low voltage circuit costs approach each other, high voltage circuits are not likely to offer near term advantage, and development work/manufacturer stimulation is needed to develop low cost high voltage hardware.
Fuzzy diagnostic system for oleo-pneumatic drive mechanism of high-voltage circuit breakers.
Nicolau, Viorel
2013-01-01
Many oil-based high-voltage circuit breakers are still in use in national power networks of developing countries, like those in Eastern Europe. Changing these breakers with new more reliable ones is not an easy task, due to their implementing costs. The acting device, called oleo-pneumatic mechanism (MOP), presents the highest fault rate from all components of circuit breaker. Therefore, online predictive diagnosis and early detection of the MOP fault tendencies are very important for their good functioning state. In this paper, fuzzy logic approach is used for the diagnosis of MOP-type drive mechanisms. Expert rules are generated to estimate the MOP functioning state, and a fuzzy system is proposed for predictive diagnosis. The fuzzy inputs give information about the number of starts and time of functioning per hour, in terms of short-term components, and their mean values. Several fuzzy systems were generated, using different sets of membership functions and rule bases, and their output performances are studied. Simulation results are presented based on an input data set, which contains hourly records of operating points for a time horizon of five years. The fuzzy systems work well, making an early detection of the MOP fault tendencies. PMID:24319349