Strong, G.H.; Faught, M.L.
1963-12-24
A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)
Optically controllable molecular logic circuits
Nishimura, Takahiro Fujii, Ryo; Ogura, Yusuke; Tanida, Jun
2015-07-06
Molecular logic circuits represent a promising technology for observation and manipulation of biological systems at the molecular level. However, the implementation of molecular logic circuits for temporal and programmable operation remains challenging. In this paper, we demonstrate an optically controllable logic circuit that uses fluorescence resonance energy transfer (FRET) for signaling. The FRET-based signaling process is modulated by both molecular and optical inputs. Based on the distance dependence of FRET, the FRET pathways required to execute molecular logic operations are formed on a DNA nanostructure as a circuit based on its molecular inputs. In addition, the FRET pathways on the DNA nanostructure are controlled optically, using photoswitching fluorescent molecules to instruct the execution of the desired operation and the related timings. The behavior of the circuit can thus be controlled using external optical signals. As an example, a molecular logic circuit capable of executing two different logic operations was studied. The circuit contains functional DNAs and a DNA scaffold to construct two FRET routes for executing Input 1 AND Input 2 and Input 1 AND NOT Input 3 operations on molecular inputs. The circuit produced the correct outputs with all possible combinations of the inputs by following the light signals. Moreover, the operation execution timings were controlled based on light irradiation and the circuit responded to time-dependent inputs. The experimental results demonstrate that the circuit changes the output for the required operations following the input of temporal light signals.
Computerized logic design of digital circuits
NASA Technical Reports Server (NTRS)
Gussow, S.; Oglesby, R.
1974-01-01
Procedure performs all work required for logic design of digital counters or sequential circuits and simplification of Boolean expressions. Program provides simple, accurate, and comprehensive logic design capability to users both experienced and totally inexperienced in logic design
Tribotronic Logic Circuits and Basic Operations.
Zhang, Chi; Zhang, Li Min; Tang, Wei; Han, Chang Bao; Wang, Zhong Lin
2015-06-17
A tribotronic logic device is fabricated to convert external mechanical stimuli into logic level signals, and tribotronic logic circuits such as NOT, AND, OR, NAND, NOR, XOR, and XNOR gates are demonstrated for performing mechanical-electrical coupled tribotronic logic operations, which realize the direct interaction between the external environment and the current silicon integrated circuits.
Logic circuits from zero forcing.
Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael
We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.
Computerized logic design of digital circuits
NASA Technical Reports Server (NTRS)
Sussow, S.; Oglesby, R.
1973-01-01
This manual presents a computer program that performs all the work required for the logic design of digital counters or sequential circuits and the simplification of Boolean logic expressions. The program provides both the experienced and inexperienced logic designer with a comprehensive logic design capability. The manual contains Boolean simplification and sequential design theory, detailed instructions for use of the program, a large number of illustrative design examples, and complete program documentation.
New Logic Circuit with DC Parametric Excitation
NASA Astrophysics Data System (ADS)
Sugahara, Masanori; Kaneda, Hisayoshi
1982-12-01
It is shown that dc parametric excitation is possible in a circuit named JUDO, which is composed of two resistively-connected Josephson junctions. Simulation study proves that the circuit has large gain and properties suitable for the construction of small, high-speed logic circuits.
Detection of Floating Inputs in Logic Circuits
NASA Technical Reports Server (NTRS)
Cash, B.; Thornton, M. G.
1984-01-01
Simple modification of oscilloscope probe allows easy detection of floating inputs or tristate outputs in digital-IC's. Oscilloscope probe easily modified with 1/4 W resistor and switch for detecting floating inputs in CMOS logic circuits.
Logic circuits based on molecular spider systems.
Mo, Dandan; Lakin, Matthew R; Stefanovic, Darko
2016-08-01
Spatial locality brings the advantages of computation speed-up and sequence reuse to molecular computing. In particular, molecular walkers that undergo localized reactions are of interest for implementing logic computations at the nanoscale. We use molecular spider walkers to implement logic circuits. We develop an extended multi-spider model with a dynamic environment wherein signal transmission is triggered via localized reactions, and use this model to implement three basic gates (AND, OR, NOT) and a cascading mechanism. We develop an algorithm to automatically generate the layout of the circuit. We use a kinetic Monte Carlo algorithm to simulate circuit computations, and we analyze circuit complexity: our design scales linearly with formula size and has a logarithmic time complexity.
Demonstrating Boolean Logic Using Simple Electrical Circuits
ERIC Educational Resources Information Center
McElhaney, Kevin W.
2004-01-01
While exploring the subject of geometric proofs, boolean logic operators AND and OR can be used to allow students to visualize their true-or-false patterns. An activity in the form of constructing electrical circuits is illustrated to explain the concept.
Starting Circuit For Erasable Programmable Logic Device
NASA Technical Reports Server (NTRS)
Cole, Steven W.
1990-01-01
Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.
Synthesis of logic circuits with evolutionary algorithms
JONES,JAKE S.; DAVIDSON,GEORGE S.
2000-01-26
In the last decade there has been interest and research in the area of designing circuits with genetic algorithms, evolutionary algorithms, and genetic programming. However, the ability to design circuits of the size and complexity required by modern engineering design problems, simply by specifying required outputs for given inputs has as yet eluded researchers. This paper describes current research in the area of designing logic circuits using an evolutionary algorithm. The goal of the research is to improve the effectiveness of this method and make it a practical aid for design engineers. A novel method of implementing the algorithm is introduced, and results are presented for various multiprocessing systems. In addition to evolving standard arithmetic circuits, work in the area of evolving circuits that perform digital signal processing tasks is described.
Nonlinear dynamics based digital logic and circuits.
Kia, Behnam; Lindner, John F; Ditto, William L
2015-01-01
We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two.
Nonlinear dynamics based digital logic and circuits
Kia, Behnam; Lindner, John. F.; Ditto, William L.
2015-01-01
We discuss the role and importance of dynamics in the brain and biological neural networks and argue that dynamics is one of the main missing elements in conventional Boolean logic and circuits. We summarize a simple dynamics based computing method, and categorize different techniques that we have introduced to realize logic, functionality, and programmability. We discuss the role and importance of coupled dynamics in networks of biological excitable cells, and then review our simple coupled dynamics based method for computing. In this paper, for the first time, we show how dynamics can be used and programmed to implement computation in any given base, including but not limited to base two. PMID:26029096
Nanoeletromechanical switch and logic circuits formed therefrom
Nordquist, Christopher D.; Czaplewski, David A.
2010-05-18
A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.
Scaling of pneumatic digital logic circuits.
Duncan, Philip N; Ahrar, Siavash; Hui, Elliot E
2015-03-07
The scaling of integrated circuits to smaller dimensions is critical for achieving increased system complexity and speed. Digital logic circuits composed of pneumatic microfluidic components have to this point been limited to a circuit density of 2-4 gates cm(-2), constraining the complexity of the digital systems that can be achieved. We explored the use of precision machining techniques to reduce the size of pneumatic valves and resistors, and to achieve more accurate and efficient placement of ports and vias. In this way, we attained an order of magnitude increase in circuit density, reaching as high as 36 gates cm(-2). A 12-bit binary counter circuit composed of 96 gates was realized in an area of 360 mm(2). The reduction in size also brought an order of magnitude increase in speed. The frequency of a 13-stage ring oscillator increased from 2.6 Hz to 22.1 Hz, and the maximum clock frequency of a binary counter increased from 1/3 Hz to 6 Hz.
Simulation Approach for Timing Analysis of Genetic Logic Circuits.
Baig, Hasan; Madsen, Jan
2017-02-01
Constructing genetic logic circuits is an application of synthetic biology in which parts of the DNA of a living cell are engineered to perform a dedicated Boolean function triggered by an appropriate concentration of certain proteins or by different genetic components. These logic circuits work in a manner similar to electronic logic circuits, but they are much more stochastic and hence much harder to characterize. In this article, we introduce an approach to analyze the threshold value and timing of genetic logic circuits. We show how this approach can be used to analyze the timing behavior of single and cascaded genetic logic circuits. We further analyze the timing sensitivity of circuits by varying the degradation rates and concentrations. Our approach can be used not only to characterize the timing behavior but also to analyze the timing constraints of cascaded genetic logic circuits, a capability that we believe will be important for design automation in synthetic biology.
Superconductive combinational logic circuit using magnetically coupled SQUID array
NASA Astrophysics Data System (ADS)
Yamanashi, Y.; Umeda, K.; Sai, K.
2010-11-01
In this paper, we propose the development of superconductive combinational logic circuits. One of the difficulties in designing superconductive single-flux-quantum (SFQ) digital circuits can be attributed to the fundamental nature of the SFQ circuits, in which all logic gates have latching functions and are based on sequential logic. The design of ultralow-power superconductive digital circuits can be facilitated by the development of superconductive combinational logic circuits in which the output is a function of only the present input. This is because superconductive combinational logic circuits do not require determination of the timing adjustment and clocking scheme. Moreover, semiconductor design tools can be used to design digital circuits because CMOS logic gates are based on combinational logic. The proposed superconductive combinational logic circuits comprise a magnetically coupled SQUID array. By adjusting the circuit parameters and coupling strengths between neighboring SQUIDs, fundamental combinational logic gates, including the AND, OR, and NOT gates, can be built. We have verified the accuracy of the operations of the fundamental logic gates by analog circuit simulations.
Predicting the reliability of electronic circuits.
Loescher, Douglas H.
2004-06-01
Procedures to predict the reliability of electrical circuits are discussed. Three cases are introduced and discussed. In Case 1, an analyst predicts the probability of any failure in the intended relations between circuit inputs and circuit outputs. In Case 2, an analyst predicts the probability that specified unintended outputs would occur. In Case 3, an analyst considers coupling between circuits. Logic models are given for the three cases, and sources of failure probabilities of components are mentioned. Methods of analysis are given, software tools are mentioned, and recommendations for presentation and review of results are discussed.
Exclusive-or logic circuit has useful properties
NASA Technical Reports Server (NTRS)
Batte, W. G.
1966-01-01
Single, simple exclusive-or logic connective eliminates excessive hardware and the number of interconnections between logic modules. This circuit performs the necessary switching for the exclusive-or operation and amplifies, restores, and inverts the signal.
A parity checker circuit based on microelectromechanical resonator logic elements
NASA Astrophysics Data System (ADS)
Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein
2017-03-01
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.
Fluid logic control circuit operates nutator actuator motor
NASA Technical Reports Server (NTRS)
1966-01-01
Fluid logic control circuit operates a pneumatic nutator actuator motor. It has no moving parts and consists of connected fluid interaction devices. The operation of this circuit demonstrates the ability of fluid interaction devices to operate in a complex combination of series and parallel logic sequence.
Digital circuits using universal logic gates
NASA Technical Reports Server (NTRS)
Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor); Cameron, Eric G. (Inventor); Donohoe, Gregory W. (Inventor); Gambles, Jody W. (Inventor)
2004-01-01
According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
A transition calculus for Boolean functions. [logic circuit analysis
NASA Technical Reports Server (NTRS)
Tucker, J. H.; Bennett, A. W.
1974-01-01
A transition calculus is presented for analyzing the effect of input changes on the output of logic circuits. The method is closely related to the Boolean difference, but it is more powerful. Both differentiation and integration are considered.
Logic Circuits as a Vehicle for Technological Literacy.
ERIC Educational Resources Information Center
Hazeltine, Barrett
1985-01-01
Provides basic information on logic circuits, points out that the topic is a good vehicle for developing technological literacy. The subject could be included in such courses as philosophy, computer science, communications, as well as in courses dealing with electronic circuits. (JN)
Novel Ferroelectric CMOS Circuits as a Nonvolatile Logic
NASA Astrophysics Data System (ADS)
Takahashi, M.; Horiuchi, T.; Li, Q.-H.; Wang, S.; Yun, K. Y.; Sakai, S.
2008-03-01
We propose a novel and promising nonvolatile-logic circuit constructed by p channel type (Pch) and n channel type (Nch) ferroelectric gate field effect transistors (FeFETs), which we named a ferroelectric CMOS (FeCMOS) circuit. The circuit works as both logic and memory. We fabricated a NOT logic FeCMOS device which have Pt metal gates and gate oxides of ferroelectric SrBi2Ta2O9 (SBT) and high-k HfAlO on Si. Key technology was adjusting threshold voltages of the FeFETs as well as preparing those of high quality. We demonstrate basic operations of the NOT-logic response, memory writing, holding and non-destructive reading. The memory writing is done by amplifying the input node voltage to a higher level when the node was logically high and to a lower one when it was logically low just before the writing operation. The data retention was also measured. The retained high and low voltages were almost unchanged for 1.2 days. The idea of this FeCMOS will enhance flexibility of circuit designing by merging logic and memory functions. This work was partially supported by NEDO.
Delay modeling of bipolar ECL/EFL (Emitter-Coupled Logic/Emitter-Follower-Logic) circuits
NASA Astrophysics Data System (ADS)
Yang, Andrew T.
1986-08-01
This report deals with the development of a delay-time model for timing simulation of large circuits consisting of Bipolar ECL(Emitter-Coupled Logic) and EFL (Emitter-Follower-Logic) networks. This model can provide adequate information on the performance of the circuits with a minimum expenditure of computation time. This goal is achieved by the use of proper circuit transient models on which analytical delay expressions can be derived with accurate results. The delay-model developed in this report is general enough to handle complex digital circuits with multiple inputs or/and multiple levels. The important effects of input slew rate are also included in the model.
Synthetic circuits integrating logic and memory in living cells.
Siuti, Piro; Yazbek, John; Lu, Timothy K
2013-05-01
Logic and memory are essential functions of circuits that generate complex, state-dependent responses. Here we describe a strategy for efficiently assembling synthetic genetic circuits that use recombinases to implement Boolean logic functions with stable DNA-encoded memory of events. Application of this strategy allowed us to create all 16 two-input Boolean logic functions in living Escherichia coli cells without requiring cascades comprising multiple logic gates. We demonstrate long-term maintenance of memory for at least 90 cell generations and the ability to interrogate the states of these synthetic devices with fluorescent reporters and PCR. Using this approach we created two-bit digital-to-analog converters, which should be useful in biotechnology applications for encoding multiple stable gene expression outputs using transient inputs of inducers. We envision that this integrated logic and memory system will enable the implementation of complex cellular state machines, behaviors and pathways for therapeutic, diagnostic and basic science applications.
Asynchronous sequential circuit design using pass transistor iterative logic arrays
NASA Technical Reports Server (NTRS)
Liu, M. N.; Maki, G. K.; Whitaker, S. R.
1991-01-01
The iterative logic array (ILA) is introduced as a new architecture for asynchronous sequential circuits. This is the first ILA architecture for sequential circuits reported in the literature. The ILA architecture produces a very regular circuit structure. Moreover, it is immune to both 1-1 and 0-0 crossovers and is free of hazards. This paper also presents a new critical race free STT state assignment which produces a simple form of design equations that greatly simplifies the ILA realizations.
Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors
Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C. P.; Gelinck, Gerwin H.; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon
2016-01-01
Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics. PMID:27762321
Reconfigurable Optical Directed-Logic Circuits
2015-11-20
advantage of the fast and low-loss propagation of light . DL can enhance the performance of digital systems for real-time applications that are... light . For instance, directed-logic architectures could find applications in packet-switched optical interconnect networks by providing fast...a) The transmission spectra of a switch in block/pass mode for light at working wavelength λL. The red dashed line and the black solid line are the
Mechanically Flexible and High-Performance CMOS Logic Circuits
Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu
2015-01-01
Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882
Mechanically Flexible and High-Performance CMOS Logic Circuits.
Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu
2015-10-13
Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits
NASA Astrophysics Data System (ADS)
Ogawa, Taichi; Hirose, Tetsuya; Asai, Tetsuya; Amemiya, Yoshihito
A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
Integrated logic circuits using single-atom transistors.
Mol, J A; Verduijn, J; Levine, R D; Remacle, F; Rogge, S
2011-08-23
Scaling down the size of computing circuits is about to reach the limitations imposed by the discrete atomic structure of matter. Reducing the power requirements and thereby dissipation of integrated circuits is also essential. New paradigms are needed to sustain the rate of progress that society has become used to. Single-atom transistors, SATs, cascaded in a circuit are proposed as a promising route that is compatible with existing technology. We demonstrate the use of quantum degrees of freedom to perform logic operations in a complementary-metal-oxide-semiconductor device. Each SAT performs multilevel logic by electrically addressing the electronic states of a dopant atom. A single electron transistor decodes the physical multivalued output into the conventional binary output. A robust scalable circuit of two concatenated full adders is reported, where by utilizing charge and quantum degrees of freedom, the functionality of the transistor is pushed far beyond that of a simple switch.
Majority-voted logic fail-sense circuit
NASA Technical Reports Server (NTRS)
Mclyman, W. T.
1977-01-01
Fail-sense circuit has majority-voted logic component which receives three error voltage signals that are sensed at single point by three error amplifiers. If transistor shorts, only one signal is required to operate; if transistor opens, two signals are required.
Controlling High Power Devices with Computers or TTL Logic Circuits
ERIC Educational Resources Information Center
Carlton, Kevin
2002-01-01
Computers are routinely used to control experiments in modern science laboratories. This should be reflected in laboratories in an educational setting. There is a mismatch between the power that can be delivered by a computer interfacing card or a TTL logic circuit and that required by many practical pieces of laboratory equipment. One common way…
Efficient G(sup 4)FET-Based Logic Circuits
NASA Technical Reports Server (NTRS)
Vatan, Farrokh
2008-01-01
A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.
A logical circuit for the regulation of fission yeast growth modes.
Bähler, Jürg; Svetina, Sasa
2005-11-21
Growth of fission yeast at the ends of its cylindrical cells switches from a monopolar to a bipolar mode, before it ceases during mitosis and cell division. Here we assume that these growth modes correspond to three stable states of an underlying regulatory circuit, which is a relatively simple and to a large degree autonomous subsystem of an otherwise complex cellular control system. We develop a switch-like logical circuit based on three elements defined as binary variables. Effects of circuit variables on each other are expressed in terms of logical operations. We analyse this circuit for its behavior ("phenotypes") after removing single or multiple operations ("mutants"). Known fission yeast polarity mutants such as those defective in the switch to bipolar growth can be classified based on these predicted 'phenotypes'. Differences in growth patterns between daughter cells in different bipolar growth mutants are also predicted by the circuit model. The model presented here should provide a useful framework to guide future experiments into mechanisms of cellular polarity. This paper illustrates the usefulness of simple logical circuits to describe and dissect features of complex regulatory processes such as the fission yeast growth patterns in both wild type and mutant cells.
Interlocked DNA nanostructures controlled by a reversible logic circuit
Li, Tao; Lohmann, Finn; Famulok, Michael
2014-01-01
DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207
Magnonic interferometric switch for multi-valued logic circuits
NASA Astrophysics Data System (ADS)
Balynsky, Michael; Kozhevnikov, Alexander; Khivintsev, Yuri; Bhowmick, Tonmoy; Gutierrez, David; Chiang, Howard; Dudko, Galina; Filimonov, Yuri; Liu, Guanxiong; Jiang, Chenglong; Balandin, Alexander A.; Lake, Roger; Khitun, Alexander
2017-01-01
We investigated a possible use of the magnonic interferometric switches in multi-valued logic circuits. The switch is a three-terminal device consisting of two spin channels where input, control, and output signals are spin waves. Signal modulation is achieved via the interference between the source and gate spin waves. We report experimental data on a micrometer scale prototype based on the Y3Fe2(FeO4)3 structure. The output characteristics are measured at different angles of the bias magnetic field. The On/Off ratio of the prototype exceeds 13 dB at room temperature. Experimental data are complemented by the theoretical analysis and the results of micro magnetic simulations showing spin wave propagation in a micrometer size magnetic junction. We also present the results of numerical modeling illustrating the operation of a nanometer-size switch consisting of just 20 spins in the source-drain channel. The utilization of spin wave interference as a switching mechanism makes it possible to build nanometer-scale logic gates, and minimize energy per operation, which is limited only by the noise margin. The utilization of phase in addition to amplitude for information encoding offers an innovative route towards multi-state logic circuits. We describe possible implementation of the three-value logic circuits based on the magnonic interferometric switches. The advantages and shortcomings inherent in interferometric switches are also discussed.
G(sup 4)FET Implementations of Some Logic Circuits
NASA Technical Reports Server (NTRS)
Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan
2009-01-01
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration
Implementation of a genetic logic circuit: bio-register.
Lin, Chun-Liang; Kuo, Ting-Yu; Chen, Yang-Yi
2015-12-01
We introduce an idea of synthesizing a class of genetic registers based on the existing sequential biological circuits, which are composed of fundamental biological gates. In the renowned literature, biological gates and genetic oscillator have been unveiled and experimentally realized in recent years. These biological circuits have formed a basis for realizing a primitive biocomputer. In the traditional computer architecture, there is an intermediate load-store section, i.e. a register, which serves as a part of the digital processor. With which, the processor can load data from a larger memory into it and proceed to conduct necessary arithmetic or logic operations. Then, manipulated data are stored back to the memory by instruction via the register. We propose here a class of bio-registers for the biocomputer. Four types of register structures are presented. In silicon experiments illustrate results of the proposed design.
Design automation for integrated nonlinear logic circuits (Conference Presentation)
NASA Astrophysics Data System (ADS)
Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.
2016-05-01
A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite
THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE
COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS
Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics
Mitra, Kalyan Yoti E-mail: enrico.sowade@mb.tu-chemnitz.de; Sowade, Enrico E-mail: enrico.sowade@mb.tu-chemnitz.de; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.
2015-02-17
Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as 'Bridging Platform'. This transfer to 'Bridging Platform' from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.
Potential up-scaling of inkjet-printed devices for logical circuits in flexible electronics
NASA Astrophysics Data System (ADS)
Mitra, Kalyan Yoti; Sowade, Enrico; Martínez-Domingo, Carme; Ramon, Eloi; Carrabina, Jordi; Gomes, Henrique Leonel; Baumann, Reinhard R.
2015-02-01
Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.
Interconnect-free parallel logic circuits in a single mechanical resonator.
Mahboob, I; Flurin, E; Nishiguchi, K; Fujiwara, A; Yamaguchi, H
2011-02-15
In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.
Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.
LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J
2014-06-02
We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.
Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model.
Fadl, Omnia S; Abu-Elyazeed, Mohamed F; Abdelhalim, Mohamed B; Amer, Hassanein H; Madian, Ahmed H
2016-01-01
Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes' toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes' toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits
Lashin, A. V. Kozyrev, A. V.
2015-09-15
One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.
2014-01-01
A negating functionality is fundamental to information processing of logic circuits within cells and computers. Aiming to adapt unutilized electronic concepts to the interrogation of signaling circuits in cells, we first took a bottom-up strategy whereby we created protein-based devices that perform negating Boolean logic operations such as NOT, NOR, NAND, and N-IMPLY. These devices function in living cells within a minute by precisely commanding the localization of an activator molecule among three subcellular spaces. We networked these synthetic gates to an endogenous signaling circuit and devised a physiological output. In search of logic functions in signal transduction, we next took a top–down approach and computationally screened 108 signaling pathways to identify commonalities and differences between these biological pathways and electronic circuits. This combination of synthetic and systems approaches will guide us in developing foundations for deconstruction of intricate cell signaling, as well as construction of biomolecular computers. PMID:25000210
Monolithic three-dimensional tunnel FET–nanoelectromechanical hybrid reconfigurable logic circuits
NASA Astrophysics Data System (ADS)
Kim, Seung Kyu; Choi, Woo Young
2017-04-01
Monolithic three-dimensional (M3D) reconfigurable logic (RL) circuits of tunnel field-effect transistors (TFETs)–nanoelectromechanical (NEM) memory switches have been proposed, simulated and demonstrated in order to overcome the limitations of CMOS-only RL circuits. A TFET is considered as one of the most promising extremely-low-power logic devices thanks to its abrupt on–off transition as well as low off-current (I off) and a NEM memory switch is a good solution to signal path routing thanks to its nonvolatile storage of data signal paths and stable rail-to-rail voltage swing. In our proposed RL circuits, NEM memory switch routing parts are integrated over complementary TFET logic circuits by using conventional CMOS backend process.
Realization of reliable and flexible logic gates using noisy nonlinear circuits
NASA Astrophysics Data System (ADS)
Murali, K.; Rajamohamed, I.; Sinha, Sudeshna; Ditto, William L.; Bulsara, Adi R.
2009-11-01
It was shown recently [Murali et al., Phys. Rev. Lett. 102, 104101 (2009)] that when one presents two square waves as input to a two-state system, the response of the system can produce a logical output (NOR/OR) with a probability controlled by the interplay between the system noise and the nonlinearity (that characterizes the bistable dynamics). One can switch or "morph" the output into another logic operation (NAND/AND) whose probability displays analogous behavior; the switching is accomplished via a controlled symmetry-breaking dc input. Thus, the interplay of nonlinearity and noise yields flexible and reliable logic behavior, and the natural outcome is, effectively, a logic gate. This "logical stochastic resonance" is demonstrated here via a circuit implementation using a linear resistor, a linear capacitor and four CMOS-transistors with a battery to produce a cubiclike nonlinearity. This circuit is simple, robust, and capable of operating in very high frequency regimes; further, its ease of implementation with integrated circuits and nanoelectronic devices should prove very useful in the context of reliable logic gate implementation in the presence of circuit noise.
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-01
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits
NASA Astrophysics Data System (ADS)
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-01
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.
Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.
Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang
2014-01-27
Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.
Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls
NASA Astrophysics Data System (ADS)
Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.
2016-01-01
Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.
Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls
Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.
2016-01-01
Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412
Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls.
Currivan-Incorvia, J A; Siddiqui, S; Dutta, S; Evarts, E R; Zhang, J; Bono, D; Ross, C A; Baldo, M A
2016-01-12
Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation.
Towards electromechanical computation: An alternative approach to realize complex logic circuits
NASA Astrophysics Data System (ADS)
Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.
2016-08-01
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.
Quaternary Galois field adder based all-optical multivalued logic circuits.
Chattopadhyay, Tanay; Taraphdar, Chinmoy; Roy, Jitendra Nath
2009-08-01
Galois field (GF) algebraic expressions have been found to be promising choices for reversible and quantum implementation of multivalued logic. For the first time to our knowledge, we developed GF(4) adder multivalued (four valued) logic circuits in an all-optical domain. The principle and possibilities of an all-optical GF(4) adder circuit are described. The theoretical model is presented and verified through numerical simulation. The quaternary inverter, successor, clockwise cycle, and counterclockwise cycle gates are proposed with the help of the all-optical GF(4) adder circuit. In this scheme different quaternary logical states are represented by different polarized light. A terahertz optical asymmetric demultiplexer interferometric switch plays an important role in this scheme.
Experimental investigation of a four-qubit linear-optical quantum logic circuit
Stárek, R.; Mičuda, M.; Miková, M.; Straka, I.; Dušek, M.; Ježek, M.; Fiurášek, J.
2016-01-01
We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C3Z gate and several two-qubit and single-qubit gates. The C3Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses. PMID:27647176
Experimental investigation of a four-qubit linear-optical quantum logic circuit
NASA Astrophysics Data System (ADS)
Stárek, R.; Mičuda, M.; Miková, M.; Straka, I.; Dušek, M.; Ježek, M.; Fiurášek, J.
2016-09-01
We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C3Z gate and several two-qubit and single-qubit gates. The C3Z gate introduces a sign flip if and only if all four qubits are in the computational state |1>. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.
CMOS-based carbon nanotube pass-transistor logic integrated circuits.
Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao
2012-02-14
Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.
Energy-Efficient and Secure S-Box circuit using Symmetric Pass Gate Adiabatic Logic
Kumar, Dinesh; Thapliyal, Himanshu; Mohammad, Azhar; Singh, Vijay; Perumalla, Kalyan S
2016-01-01
Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for lowpower portable electronic devices and Internet-of-Things (IoT) based electronic devices.
Novel shift register eliminates logic gates and power switching circuits
NASA Technical Reports Server (NTRS)
Cliff, R. A.
1971-01-01
Register requiring two integrated circuits per stage has nominal power dissipation of 3.5 mW per stage, its use eliminates reset pulse, allowing data transfer to occur in less than 1 microsecond, and eliminates power application to both right and left portions of the register simultaneously.
Off-Line Testing for Bridge Faults in CMOS Domino Logic Circuits
NASA Technical Reports Server (NTRS)
Bennett, K.; Lala, P. K.; Busaba, F.
1997-01-01
Bridge faults, especially in CMOS circuits, have unique characteristics which make them difficult to detect during testing. This paper presents a technique for detecting bridge faults which have an effect on the output of CMOS Domino logic circuits. The faults are modeled at the transistor level and this technique is based on analyzing the off-set of the function during off-line testing.
NASA Technical Reports Server (NTRS)
1975-01-01
Technological information is presented electronic circuits and systems which have potential utility outside the aerospace community. Topics discussed include circuit components such as filters, converters, and integrators, circuits designed for use with specific equipment or systems, and circuits designed primarily for use with optical equipment or displays.
Quantum Approaches to Logic Circuit Synthesis and Testing
2006-06-01
STATEMENT APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED. PA#06-445 13. SUPPLEMENTARY NOTES 14 . ABSTRACT The overall objective of this...i Table of Contents 1. Executive Summary 1 2. Introduction 2 3. Synthesis of Quantum Circuits 14 4...used by the Apply operation with xi = Var( vf ), xj = Var(vg) and xi < xj meaning that that xi precedes xj in the variable ordering. 11
Rhee, Minsoung
2010-01-01
We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730
Rhee, Minsoung; Burns, Mark A
2009-11-07
We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.
Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.
Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J
2017-01-01
The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.
Designing reversible arithmetic, logic circuit to implement micro-operation in quantum computation
NASA Astrophysics Data System (ADS)
Kalita, Gunajit; Saikia, Navajit
2016-10-01
The futuristic computing is desired to be more power full with low-power consumption. That is why quantum computing has been a key area of research for quite some time and is getting more and more attention. Quantum logic being reversible, a significant amount of contributions has been reported on reversible logic in recent times. Reversible circuits are essential parts of quantum computers, and hence their designs are of great importance. In this paper, designs of reversible circuits are proposed using a recently proposed reversible gate for arithmetic and logic operations to implement various micro-operations (simple add and subtract, add with carry, subtract with borrow, transfer, incrementing, decrementing etc., and logic operations like XOR, XNOR, complementing etc.) in a reversible computer like quantum computer. The two new reversible designs proposed here for half adder and full adders are also used in the presented reversible circuits to implement various microoperations. The quantum costs of these designs are comparable. Many of the implemented micro-operations are not seen in previous literatures. The performances of the proposed circuits are compared with existing designs wherever available.
An RNAi-Enhanced Logic Circuit for Cancer Specific Detection and Destruction
2013-02-01
cancer specific detection and destruction. PRINCIPAL INVESTIGATOR: Ron Weiss...2013 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER An RNAi-enhanced logic circuit for cancer specific detection and destruction. 5b. GRANT NUMBER...ABSTRACT Modern breast cancer therapies utilize non-specific approaches to kill or remove cancerous cells, inflicting significant collateral damage to
NASA Astrophysics Data System (ADS)
Yamanashi, Yuki; Masubuchi, Kota; Yoshikawa, Nobuyuki
2016-11-01
The relationship between the timing margin and the error rate of the large-scale single flux quantum logic circuits is quantitatively investigated to establish a timing design guideline. We observed that the fluctuation in the set-up/hold time of single flux quantum logic gates caused by thermal noises is the most probable origin of the logical error of the large-scale single flux quantum circuit. The appropriate timing margin for stable operation of the large-scale logic circuit is discussed by taking the fluctuation of setup/hold time and the timing jitter in the single flux quantum circuits. As a case study, the dependence of the error rate of the 1-million-bit single flux quantum shift register on the timing margin is statistically analyzed. The result indicates that adjustment of timing margin and the bias voltage is important for stable operation of a large-scale SFQ logic circuit.
Graphene-based non-Boolean logic circuits
NASA Astrophysics Data System (ADS)
Liu, Guanxiong; Ahsan, Sonia; Khitun, Alexander G.; Lake, Roger K.; Balandin, Alexander A.
2013-10-01
Graphene revealed a number of unique properties beneficial for electronics. However, graphene does not have an energy band-gap, which presents a serious hurdle for its applications in digital logic gates. The efforts to induce a band-gap in graphene via quantum confinement or surface functionalization have not resulted in a breakthrough. Here we show that the negative differential resistance experimentally observed in graphene field-effect transistors of "conventional" design allows for construction of viable non-Boolean computational architectures with the gapless graphene. The negative differential resistance—observed under certain biasing schemes—is an intrinsic property of graphene, resulting from its symmetric band structure. Our atomistic modeling shows that the negative differential resistance appears not only in the drift-diffusion regime but also in the ballistic regime at the nanometer-scale—although the physics changes. The obtained results present a conceptual change in graphene research and indicate an alternative route for graphene's applications in information processing.
Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch
Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi
2010-01-01
Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and ‘memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch. PMID:20212522
Novel Approach To Synthesis of Logic Circuits Based on Multifunctional Components
NASA Astrophysics Data System (ADS)
Crha, Adam; Růžička, Richard; Šimek, Václav
2016-01-01
Multifunctional logic continuously becomes an important way how to implement compact and cheap circuits with intrinsic reconfiguration features. Polymorphic electronics concept with its substantial technological independency opens a way to fulfil this objective through the adoption of emerging semiconductor technologies and advanced synthesis methods. The paper comes with a proposal of a novel synthesis method oriented on the exploitation of polymorphic electronics principles. Key part of it is based on Boolean divisor identification and function kernelling technique. The proposed method is evaluated with several test circuits.
Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates
NASA Astrophysics Data System (ADS)
Li, Zhiqiang; Chen, Sai; Song, Xiaoyu; Perkowski, Marek; Chen, Hanwu; Zhu, Wei
2017-04-01
Since Controlled-Square-Root-of-NOT (CV, CV‡) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.
Quantum Circuit Synthesis using a New Quantum Logic Gate Library of NCV Quantum Gates
NASA Astrophysics Data System (ADS)
Li, Zhiqiang; Chen, Sai; Song, Xiaoyu; Perkowski, Marek; Chen, Hanwu; Zhu, Wei
2016-12-01
Since Controlled-Square-Root-of-NOT (CV, CV‡) gates are not permutative quantum gates, many existing methods cannot effectively synthesize optimal 3-qubit circuits directly using the NOT, CNOT, Controlled-Square-Root-of-NOT quantum gate library (NCV), and the key of effective methods is the mapping of NCV gates to four-valued quantum gates. Firstly, we use NCV gates to create the new quantum logic gate library, which can be directly used to get the solutions with smaller quantum costs efficiently. Further, we present a novel generic method which quickly and directly constructs this new optimal quantum logic gate library using CNOT and Controlled-Square-Root-of-NOT gates. Finally, we present several encouraging experiments using these new permutative gates, and give a careful analysis of the method, which introduces a new idea to quantum circuit synthesis.
How Young Children Understand Electric Circuits: Prediction, Explanation and Exploration
ERIC Educational Resources Information Center
Glauert, Esme Bridget
2009-01-01
This paper reports findings from a study of young children's views about electric circuits. Twenty-eight children aged 5 and 6 years were interviewed. They were shown examples of circuits and asked to predict whether they would work and explain why. They were then invited to try out some of the circuit examples or make circuits of their own…
ERIC Educational Resources Information Center
Houghton, Janaye Matteson; Houghton, Robert S.
Today and in the future, critical toolmaking advances will need to be made in the area of circuit design, construction, and implementation. Traditional school curriculum has sidestepped the area of tool design, especially at the elementary level. This publication addresses a calling for a new curriculum direction, based not only on the study of…
Urrios, Arturo; de Nadal, Eulàlia; Solé, Ricard; Posas, Francesc
2016-01-01
Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit’s complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined. PMID:26829588
Wang, Baojun; Barahona, Mauricio; Buck, Martin
2013-01-01
Cells perceive a wide variety of cellular and environmental signals, which are often processed combinatorially to generate particular phenotypic responses. Here, we employ both single and mixed cell type populations, pre-programmed with engineered modular cell signalling and sensing circuits, as processing units to detect and integrate multiple environmental signals. Based on an engineered modular genetic AND logic gate, we report the construction of a set of scalable synthetic microbe-based biosensors comprising exchangeable sensory, signal processing and actuation modules. These cellular biosensors were engineered using distinct signalling sensory modules to precisely identify various chemical signals, and combinations thereof, with a quantitative fluorescent output. The genetic logic gate used can function as a biological filter and an amplifier to enhance the sensing selectivity and sensitivity of cell-based biosensors. In particular, an Escherichia coli consortium-based biosensor has been constructed that can detect and integrate three environmental signals (arsenic, mercury and copper ion levels) via either its native two-component signal transduction pathways or synthetic signalling sensors derived from other bacteria in combination with a cell-cell communication module. We demonstrate how a modular cell-based biosensor can be engineered predictably using exchangeable synthetic gene circuit modules to sense and integrate multiple-input signals. This study illustrates some of the key practical design principles required for the future application of these biosensors in broad environmental and healthcare areas. PMID:22981411
Wang, Baojun; Barahona, Mauricio; Buck, Martin
2013-02-15
Cells perceive a wide variety of cellular and environmental signals, which are often processed combinatorially to generate particular phenotypic responses. Here, we employ both single and mixed cell type populations, pre-programmed with engineered modular cell signalling and sensing circuits, as processing units to detect and integrate multiple environmental signals. Based on an engineered modular genetic AND logic gate, we report the construction of a set of scalable synthetic microbe-based biosensors comprising exchangeable sensory, signal processing and actuation modules. These cellular biosensors were engineered using distinct signalling sensory modules to precisely identify various chemical signals, and combinations thereof, with a quantitative fluorescent output. The genetic logic gate used can function as a biological filter and an amplifier to enhance the sensing selectivity and sensitivity of cell-based biosensors. In particular, an Escherichia coli consortium-based biosensor has been constructed that can detect and integrate three environmental signals (arsenic, mercury and copper ion levels) via either its native two-component signal transduction pathways or synthetic signalling sensors derived from other bacteria in combination with a cell-cell communication module. We demonstrate how a modular cell-based biosensor can be engineered predictably using exchangeable synthetic gene circuit modules to sense and integrate multiple-input signals. This study illustrates some of the key practical design principles required for the future application of these biosensors in broad environmental and healthcare areas.
Designing sequential transcription logic: a simple genetic circuit for conditional memory.
Fritz, Georg; Buchler, Nicolas E; Hwa, Terence; Gerland, Ulrich
2007-04-01
The ability to learn and respond to recurrent events depends on the capacity to remember transient biological signals received in the past. Moreover, it may be desirable to remember or ignore these transient signals conditioned upon other signals that are active at specific points in time or in unique environments. Here, we propose a simple genetic circuit in bacteria that is capable of conditionally memorizing a signal in the form of a transcription factor concentration. The circuit behaves similarly to a "data latch" in an electronic circuit, i.e. it reads and stores an input signal only when conditioned to do so by a "read command." Our circuit is of the same size as the well-known genetic toggle switch (an unconditional latch) which consists of two mutually repressing genes, but is complemented with a "regulatory front end" involving protein heterodimerization as a simple way to implement conditional control. Deterministic and stochastic analysis of the circuit dynamics indicate that an experimental implementation is feasible based on well-characterized genes and proteins. It is not known, to which extent molecular networks are able to conditionally store information in natural contexts for bacteria. However, our results suggest that such sequential logic elements may be readily implemented by cells through the combination of existing protein-protein interactions and simple transcriptional regulation.
Si-nanowire-array-based NOT-logic circuits constructed on plastic substrates using top-down methods.
Jeon, Youngin; Kang, Jeongmin; Lee, Myeongwon; Moon, Taeho; Kim, Sangsig
2013-05-01
Si-nanowire (NW)-array-based NOT-logic circuits were constructed on plastic substrates. The Si-NW arrays were fabricated on a Si wafer through top-down methods, including conventional photolithography and crystallographic wet etching, and transferred onto the plastic substrates. Two field-effect transistors were fabricated on a single Si-NW array composed of five nanowires aligned in parallel and connected in series to form NOT-logic circuits. The excellent flexibility of the fabricated device was confirmed by bending-cycling tests. The voltage-transfer curve of the NOT-logic circuits showed an inverting operation with a logic swing of -92% and voltage gain of -2.5.
Bi, Sai; Chen, Min; Jia, Xiaoqiang; Dong, Ying; Wang, Zonghua
2015-07-06
A hyper-branched hybridization chain reaction (HB-HCR) is presented herein, which consists of only six species that can metastably coexist until the introduction of an initiator DNA to trigger a cascade of hybridization events, leading to the self-sustained assembly of hyper-branched and nicked double-stranded DNA structures. The system can readily achieve ultrasensitive detection of target DNA. Moreover, the HB-HCR principle is successfully applied to construct three-input concatenated logic circuits with excellent specificity and extended to design a security-mimicking keypad lock system. Significantly, the HB-HCR-based keypad lock can alarm immediately if the "password" is incorrect. Overall, the proposed HB-HCR with high amplification efficiency is simple, homogeneous, fast, robust, and low-cost, and holds great promise in the development of biosensing, in the programmable assembly of DNA architectures, and in molecular logic operations.
NASA Astrophysics Data System (ADS)
Rahmani Nejad, Akbar
2009-08-01
In this paper, it is tried to provide an innovative method to overcome several limitations of state of the art of logical gates and microprocessors, by implementation of micron-scaled optical gates. This technology can overcome such limitations, i.e. processing speed, heat dissipation, electromagnetic radiation and electrical noise immunity. This technology can be fully or partially feasible by substitution of common semiconductor technology with optical logic gates. By implementation of micron-scale optical fiber, optical couplers, fiber optical amplifiers, or fiber lasers, optical attenuators, optical fiber brag grating, femto-second optical lasers, and implementation of fundamental properties of optical coherent light, e.g. superposition, interference, phase delay, etc, it is possible to fabricate micron-scale universal logical gates, i.e. optical NAND gates, optical NOR gates, optical Exclusive-OR, optical exclusive-NOR gates and subsequently fabrication of sequential circuits (optical flip-flops), that all are fundamental blocks of microprocessors. Optical coherent light is produced by femtosecond lasers and is supplied to a network of micron-scaled fiber optics, fiber optical lasers, attenuators, fiber optical couplers, and finally are supplied to opto-couplers that change optical signals to electrical signals to be read by output console or to be written on memory cells. It is also possible to implement a combination of optical and semiconductor gates to decrease above mentioned limitations. The method of fabrication of optical gates is discussed in details and all necessary logical and technical aspects are provided too. The fundamental implemented aspect is superposition of coherent lights in fiber optic couplers. By implementation of femtosecond laser pulses, it is possible to reach to much higher frequencies of about hundreds to thousands of terahertz. Alternative optical method is provided here, e.g. implementation of fiber loops as clock circuit or
Materials Integration and Doping of Carbon Nanotube-based Logic Circuits
NASA Astrophysics Data System (ADS)
Geier, Michael
Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and
Plasmonic-multimode-interference-based logic circuit with simple phase adjustment
NASA Astrophysics Data System (ADS)
Ota, Masashi; Sumimura, Asahi; Fukuhara, Masashi; Ishii, Yuya; Fukuda, Mitsuo
2016-04-01
All-optical logic circuits using surface plasmon polaritons have a potential for high-speed information processing with high-density integration beyond the diffraction limit of propagating light. However, a number of logic gates that can be cascaded is limited by complicated signal phase adjustment. In this study, we demonstrate a half-adder operation with simple phase adjustment using plasmonic multimode interference (MMI) devices, composed of dielectric stripes on a metal film, which can be fabricated by a complementary metal-oxide semiconductor (MOS)-compatible process. Also, simultaneous operations of XOR and AND gates are substantiated experimentally by combining 1 × 1 MMI based phase adjusters and 2 × 2 MMI based intensity modulators. An experimental on-off ratio of at least 4.3 dB is confirmed using scanning near-field optical microscopy. The proposed structure will contribute to high-density plasmonic circuits, fabricated by complementary MOS-compatible process or printing techniques.
Plasmonic-multimode-interference-based logic circuit with simple phase adjustment.
Ota, Masashi; Sumimura, Asahi; Fukuhara, Masashi; Ishii, Yuya; Fukuda, Mitsuo
2016-04-18
All-optical logic circuits using surface plasmon polaritons have a potential for high-speed information processing with high-density integration beyond the diffraction limit of propagating light. However, a number of logic gates that can be cascaded is limited by complicated signal phase adjustment. In this study, we demonstrate a half-adder operation with simple phase adjustment using plasmonic multimode interference (MMI) devices, composed of dielectric stripes on a metal film, which can be fabricated by a complementary metal-oxide semiconductor (MOS)-compatible process. Also, simultaneous operations of XOR and AND gates are substantiated experimentally by combining 1 × 1 MMI based phase adjusters and 2 × 2 MMI based intensity modulators. An experimental on-off ratio of at least 4.3 dB is confirmed using scanning near-field optical microscopy. The proposed structure will contribute to high-density plasmonic circuits, fabricated by complementary MOS-compatible process or printing techniques.
NASA Technical Reports Server (NTRS)
Athale, R. A.; Lee, S. H.
1978-01-01
The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.
Tian, Yonghui; Zhang, Lei; Ji, Ruiqiang; Yang, Lin; Zhou, Ping; Chen, Hongtao; Ding, Jianfeng; Zhu, Weiwei; Lu, Yangyang; Jia, Lianxi; Fang, Qing; Yu, Mingbin
2011-05-01
We propose and demonstrate a directed OR/NOR and AND/NAND logic circuit consisting of two parallel microring resonators (MRRs). We use two electrical signals representing the two operands of the logical operation to modulate the two MRRs through the thermo-optic effect, respectively. The final operation results are represented by the output optical signals. Both OR/NOR and AND/NAND operations at 10 kbps are demonstrated.
Glover, J C
2009-11-10
The first Kavli Prize in Neuroscience recognizes a confluence of career achievements that together provide a fundamental understanding of how brain and spinal cord circuits are assembled during development and function in the adult. The members of the Kavli Neuroscience Prize Committee have decided to reward three scientists (Sten Grillner, Thomas Jessell, and Pasko Rakic) jointly "for discoveries on the developmental and functional logic of neuronal circuits". Pasko Rakic performed groundbreaking studies of the developing cerebral cortex, including the discovery of how radial glia guide the neuronal migration that establishes cortical layers and for the radial unit hypothesis and its implications for cortical connectivity and evolution. Thomas Jessell discovered molecular principles governing the specification and patterning of different neuron types and the development of their synaptic interconnection into sensorimotor circuits. Sten Grillner elucidated principles of network organization in the vertebrate locomotor central pattern generator, along with its command systems and sensory and higher order control. The discoveries of Rakic, Jessell and Grillner provide a framework for how neurons obtain their identities and ultimate locations, establish appropriate connections with each other, and how the resultant neuronal networks operate. Their work has significantly advanced our understanding of brain development and function and created new opportunities for the treatment of neurological disorders. Each has pioneered an important area of neuroscience research and left a legacy of exceptional scientific achievement, insight, communication, mentoring and leadership.
Electro-optic directed XOR logic circuits based on parallel-cascaded micro-ring resonators.
Tian, Yonghui; Zhao, Yongpeng; Chen, Wenjie; Guo, Anqi; Li, Dezhao; Zhao, Guolin; Liu, Zilong; Xiao, Huifu; Liu, Guipeng; Yang, Jianhong
2015-10-05
We report an electro-optic photonic integrated circuit which can perform the exclusive (XOR) logic operation based on two silicon parallel-cascaded microring resonators (MRRs) fabricated on the silicon-on-insulator (SOI) platform. PIN diodes embedded around MRRs are employed to achieve the carrier injection modulation. Two electrical pulse sequences regarded as two operands of operations are applied to PIN diodes to modulate two MRRs through the free carrier dispersion effect. The final operation result of two operands is output at the Output port in the form of light. The scattering matrix method is employed to establish numerical model of the device, and numerical simulator SG-framework is used to simulate the electrical characteristics of the PIN diodes. XOR operation with the speed of 100Mbps is demonstrated successfully.
NASA Astrophysics Data System (ADS)
Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Patil, Nishant; Lin, Albert; Mitra, Subhasish; Wong, H.-S. Philip; Zhou, Chongwu
2008-07-01
In this paper, high-performance back-gated carbon nanotube field-effect transistors based on transferred aligned carbon nanotubes were fabricated and studies found that the on/off ratio can reach 107 and the current density can reach 1.6μA/μm after electrical breakdown. In addition, chemical doping with hydrazine was used to convert the p-type aligned nanotube devices into n-type. These devices were further utilized to demonstrate various logic circuits, including p-type metal-oxide-semiconductor inverters, diode-loaded inverters, complementary metal-oxide-semiconductor inverters, NAND, and NOR gates. This approach could work as the platform for future nanotube-based nanoelectronics.
Han, Da; Zhu, Zhi; Wu, Cuichen; Peng, Lu; Zhou, Leiji; Gulbakan, Basri; Zhu, Guizhi; Williams, Kathryn R; Tan, Weihong
2012-12-26
Researchers increasingly envision an important role for artificial biochemical circuits in biological engineering, much like electrical circuits in electrical engineering. Similar to electrical circuits, which control electromechanical devices, biochemical circuits could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expressions in vivo. (1) As a consequence of their relative robustness and potential applicability for controlling a wide range of in vitro chemistries, synthetic cell-free biochemical circuits promise to be useful in manipulating the functions of biological molecules. Here, we describe the first logical circuit based on DNA-protein interactions with accurate threshold control, enabling autonomous, self-sustained and programmable manipulation of protein activity in vitro. Similar circuits made previously were based primarily on DNA hybridization and strand displacement reactions. This new design uses the diverse nucleic acid interactions with proteins. The circuit can precisely sense the local enzymatic environment, such as the concentration of thrombin, and when it is excessively high, a coagulation inhibitor is automatically released by a concentration-adjusted circuit module. To demonstrate the programmable and autonomous modulation, a molecular circuit with different threshold concentrations of thrombin was tested as a proof of principle. In the future, owing to tunable regulation, design modularity and target specificity, this prototype could lead to the development of novel DNA biochemical circuits to control the delivery of aptamer-based drugs in smart and personalized medicine, providing a more efficient and safer therapeutic strategy.
Large scale MoS2 nanosheet logic circuits integrated by photolithography on glass
NASA Astrophysics Data System (ADS)
Kwon, Hyeokjae; Jeon, Pyo Jin; Kim, Jin Sung; Kim, Tae-Young; Yun, Hoyeol; Lee, Sang Wook; Lee, Takhee; Im, Seongil
2016-12-01
We demonstrate 500 × 500 μm2 large scale polygrain MoS2 nanosheets and field effect transistor (FET) circuits integrated using those nanosheets, which are initially grown on SiO2/p+-Si by chemical vapor deposition but transferred onto glass substrate to be patterned by photolithography. In fact, large scale growth of two-dimensional MoS2 and its conventional way of patterning for integrated devices have remained as one of the unresolved important issues. In the present study, we achieved maximum linear mobility of ˜9 cm2 V-1 s-1 from single-domain MoS2 FET on SiO2/p+-Si substrate and 0.5˜3.0 cm2 V-1 s-1 from large scale MoS2 sheet transferred onto glass. Such reduced mobility is attributed to the transfer process-induced wrinkles and crevices, domain boundaries, residue on MoS2, and loss of the back gate-charging effects that might exist due to SiO2/p+-Si substrate. Among 16 MoS2-based FETs, 13 devices successfully work (yield was more than 80%) producing NOT, NOR, and NAND logic circuits. Inverter (NOT gate) shows quite a high voltage gain over 12 at a supply voltage of 5 V, also displaying 60 μs switching speed in kilohertz dynamics.
Final report on LDRD project :leaky-mode VCSELs for photonic logic circuits.
Hargett, Terry W.; Hadley, G. Ronald; Serkland, Darwin Keith; Blansett, Ethan L.; Geib, Kent Martin; Sullivan, Charles Thomas; Keeler, Gordon Arthur; Bauer, Thomas; Ongstand, Andrea; Medrano, Melissa R.; Peake, Gregory Merwin; Montano, Victoria A.
2005-11-01
This report describes the research accomplishments achieved under the LDRD Project ''Leaky-mode VCSELs for photonic logic circuits''. Leaky-mode vertical-cavity surface-emitting lasers (VCSELs) offer new possibilities for integration of microcavity lasers to create optical microsystems. A leaky-mode VCSEL output-couples light laterally, in the plane of the semiconductor wafer, which allows the light to interact with adjacent lasers, modulators, and detectors on the same wafer. The fabrication of leaky-mode VCSELs based on effective index modification was proposed and demonstrated at Sandia in 1999 but was not adequately developed for use in applications. The aim of this LDRD has been to advance the design and fabrication of leaky-mode VCSELs to the point where initial applications can be attempted. In the first and second years of this LDRD we concentrated on overcoming previous difficulties in the epitaxial growth and fabrication of these advanced VCSELs. In the third year, we focused on applications of leaky-mode VCSELs, such as all-optical processing circuits based on gain quenching.
Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang
2016-01-01
The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154
A synergistic DNA logic predicts genome-wide chromatin accessibility
Hashimoto, Tatsunori; Sherwood, Richard I.; Kang, Daniel D.; Rajagopal, Nisha; Barkal, Amira A.; Zeng, Haoyang; Emons, Bart J.M.; Srinivasan, Sharanya; Jaakkola, Tommi; Gifford, David K.
2016-01-01
Enhancers and promoters commonly occur in accessible chromatin characterized by depleted nucleosome contact; however, it is unclear how chromatin accessibility is governed. We show that log-additive cis-acting DNA sequence features can predict chromatin accessibility at high spatial resolution. We develop a new type of high-dimensional machine learning model, the Synergistic Chromatin Model (SCM), which when trained with DNase-seq data for a cell type is capable of predicting expected read counts of genome-wide chromatin accessibility at every base from DNA sequence alone, with the highest accuracy at hypersensitive sites shared across cell types. We confirm that a SCM accurately predicts chromatin accessibility for thousands of synthetic DNA sequences using a novel CRISPR-based method of highly efficient site-specific DNA library integration. SCMs are directly interpretable and reveal that a logic based on local, nonspecific synergistic effects, largely among pioneer TFs, is sufficient to predict a large fraction of cellular chromatin accessibility in a wide variety of cell types. PMID:27456004
NASA Astrophysics Data System (ADS)
Kitowski, J.; Ksiażek, E.
1985-10-01
The paper presents some preliminary results of diagnostic analysis of the stimulated primary circuit of the THTR-300 nuclear power plant, based on the fuzzy sets theory. Two methods are used: the solution of the fuzzy relational equations and its extension to fuzzy logic. The first stage of the diagnostic system is the identification of the plant in the sense of fuzzy relations and the second stage is the failure or disturbance recognition. According to the fuzzy logic, lower and upper bounds of the failure vectors are obtained. Such an expert system can supply the operator in a correct recognition of the current state of the complex plant.
NASA Technical Reports Server (NTRS)
Taylor, B.
1990-01-01
The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.
Zhu, Jinbo; Zhang, Libing; Dong, Shaojun; Wang, Erkang
2013-11-26
We introduced a four-way DNA junction-driven toehold-mediated strand displacement method. Separation of the different functional domains on different strands in the four-way junction structure and usage of glue strand to recombine them for different logic gates make the design more flexible. On the basis of this mechanism, a majority logic circuit fabricated by DNA strands was designed and constructed by assembling three AND gates and one OR gate together. The output strand drew the G-rich segments together to form a split G-quadruplex, which could specifically bind PPIX and enhance its fluorescence. Just like a poll with three voters, the high fluorescence signal would be given off only when two or three voters vote in favor. Upon slight modification, the majority circuit was utilized to select the composite number from 0 to 9 represented by excess-three code. It is a successful attempt to integrate the logic gates into a circuit and to achieve desired functions.
All-optical logic circuits based on the polarization properties of non-degenerate four-wave mixing
NASA Astrophysics Data System (ADS)
Bhardwaj, Ashish Ishwar Singh
2001-10-01
This thesis investigates a new class of all-optical logic circuits that are based on the polarization properties of non-degenerate Four-Wave Mixing. Such circuits would be used in conjunction with a data modulation format where the information is coded on the states of polarization of the electric field. Schemes to perform multiple triple- product logic functions are discussed and it is shown that higher-level Boolean operations involving several bits can be implemented without resorting to the standard 2-input gates that are based on some form of switching. Instead, an entire hierarchy of more complex Boolean functions can be derived based on the selection rules of multi-photon scattering processes that can form a new classes of primitive building blocks for digital circuits. Possible applications of these circuits could involve some front-end signal processing to be performed all- optically in shared computer back-planes. As a simple illustration of this idea, a circuit performing error correction on a (3,1) Hamming Code is demonstrated. Error-free performance (Bit Error Rate of <10-9) at 2.5 Gbit/s is achieved after single-error correction on the Hamming word with 50 percent errors. The bit-rate is only limited by the bandwidth of available resources. Since Four-Wave Mixing is an ultrafast nonlinearity, these circuits offer the potential of computing at several terabits per second. Furthermore, it is shown that several Boolean functions can be performed in parallel in the same set of devices using different multi-photon scattering processes. The main objective of this thesis is to motivate a new paradigm of thought in digital circuit design. Challenges pertaining to the feasibility of these ideas are discussed.
Predicting the behavior of microfluidic circuits made from discrete elements.
Bhargava, Krisna C; Thompson, Bryant; Iqbal, Danish; Malmstadt, Noah
2015-10-30
Microfluidic devices can be used to execute a variety of continuous flow analytical and synthetic chemistry protocols with a great degree of precision. The growing availability of additive manufacturing has enabled the design of microfluidic devices with new functionality and complexity. However, these devices are prone to larger manufacturing variation than is typical of those made with micromachining or soft lithography. In this report, we demonstrate a design-for-manufacturing workflow that addresses performance variation at the microfluidic element and circuit level, in context of mass-manufacturing and additive manufacturing. Our approach relies on discrete microfluidic elements that are characterized by their terminal hydraulic resistance and associated tolerance. Network analysis is employed to construct simple analytical design rules for model microfluidic circuits. Monte Carlo analysis is employed at both the individual element and circuit level to establish expected performance metrics for several specific circuit configurations. A protocol based on osmometry is used to experimentally probe mixing behavior in circuits in order to validate these approaches. The overall workflow is applied to two application circuits with immediate use at on the bench-top: series and parallel mixing circuits that are modularly programmable, virtually predictable, highly precise, and operable by hand.
NASA Astrophysics Data System (ADS)
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-05-01
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V‑1 sec‑1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-01-01
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914
Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo
2016-05-09
Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.
New dynamic FET logic and serial memory circuits for VLSI GaAs technology
NASA Technical Reports Server (NTRS)
Eldin, A. G.
1991-01-01
The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.
NASA Astrophysics Data System (ADS)
Matsuzaki, F.; Yoshikawa, N.; Tanaka, M.; Fujimaki, A.; Takai, Y.
2003-10-01
Recently many single flux quantum (SFQ) logic circuits containing several thousands of Josephson junctions have been designed successfully by using digital domain simulation based on the hard ware description language (HDL). In the present HDL-based design of SFQ circuits, a structure-level HDL description has been used, where circuits are made up of basic gate cells. However, in order to analyze large-scale SFQ digital systems, such as a microprocessor, more higher-level circuit abstraction is necessary to reduce the circuit simulation time. In this paper we have investigated the way to describe functionality of the large-scale SFQ digital circuits by a behavior-level HDL description. In this method, the functionality and the timing of the circuit block is defined directly by describing their behavior by the HDL. Using this method, we can dramatically reduce the simulation time of large-scale SFQ digital circuits.
Predicting recycling behaviour: Comparison of a linear regression model and a fuzzy logic model.
Vesely, Stepan; Klöckner, Christian A; Dohnal, Mirko
2016-03-01
In this paper we demonstrate that fuzzy logic can provide a better tool for predicting recycling behaviour than the customarily used linear regression. To show this, we take a set of empirical data on recycling behaviour (N=664), which we randomly divide into two halves. The first half is used to estimate a linear regression model of recycling behaviour, and to develop a fuzzy logic model of recycling behaviour. As the first comparison, the fit of both models to the data included in estimation of the models (N=332) is evaluated. As the second comparison, predictive accuracy of both models for "new" cases (hold-out data not included in building the models, N=332) is assessed. In both cases, the fuzzy logic model significantly outperforms the regression model in terms of fit. To conclude, when accurate predictions of recycling and possibly other environmental behaviours are needed, fuzzy logic modelling seems to be a promising technique.
Cardiopulmonary Circuit Models for Predicting Injury to the Heart
NASA Astrophysics Data System (ADS)
Ward, Richard; Wing, Sarah; Bassingthwaighte, James; Neal, Maxwell
2004-11-01
Circuit models have been used extensively in physiology to describe cardiopulmonary function. Such models are being used in the DARPA Virtual Soldier (VS) Project* to predict the response to injury or physiological stress. The most complex model consists of systemic circulation, pulmonary circulation, and a four-chamber heart sub-model. This model also includes baroreceptor feedback, airway mechanics, gas exchange, and pleural pressure influence on the circulation. As part of the VS Project, Oak Ridge National Laboratory has been evaluating various cardiopulmonary circuit models for predicting the effects of injury to the heart. We describe, from a physicist's perspective, the concept of building circuit models, discuss both unstressed and stressed models, and show how the stressed models are used to predict effects of specific wounds. *This work was supported by a grant from the DARPA, executed by the U.S. Army Medical Research and Materiel Command/TATRC Cooperative Agreement, Contract # W81XWH-04-2-0012. The submitted manuscript has been authored by the U.S. Department of Energy, Office of Science of the Oak Ridge National Laboratory, managed for the U.S. DOE by UT-Battelle, LLC, under contract No. DE-AC05-00OR22725. Accordingly, the U.S. Government retains a non-exclusive, royalty-free license to publish or reproduce the published form of this contribution, or allow others to do so, for U.S. Government purpose.
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-01-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V−1 sec−1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process. PMID:27184121
NASA Astrophysics Data System (ADS)
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-05-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V‑1 sec‑1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-05-17
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm(2) V(-1) sec(-)1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 10(4)), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.
Fault-tolerant computer study. [logic designs for building block circuits
NASA Technical Reports Server (NTRS)
Rennels, D. A.; Avizienis, A. A.; Ercegovac, M. D.
1981-01-01
A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.
Application of Error Correcting Codes in Fault-Tolerant Logic Design for VLSI Circuits
1992-08-14
Difference between par Erroneous bit( s ) expected and actual (do) (unidirectional) residue(dr) 8(5) 0 d7d6 10 (3) 0 d5d4 3( 10 ) 0 d4d3 4(9) 0 d2dl 9(4) 0...indicating the presence of the s -on transistor. Since C for any fault, the circuit never produces an incorrect code word i.e. 10 instead of 01 or vice...way that P2 82 P for any defect (break or s -on) in the circuit the outputs 1 P4 -- will assume a value of 01 or 10 . For a fault-free circuit the
NASA Astrophysics Data System (ADS)
Frégonèse, Sébastien; Maneux, Cristell; Zimmer, Thomas
2009-10-01
This paper investigates the impact of the metallic nanotube (M-NT) presence within CNTFET circuits: circuit yield and performances are analyzed using calibrated compact models for both the CNTFET and the M-NT. The major cause of technological dispersion in CNTFET technology comes from the control of the carbon nanotube chirality. This lack of control may lead to the presence of metallic nanotubes in the transistor. These M-NTs create shorts which dramatically increase the source-drain leakage current. The random presence and position of M-NT in the ring oscillator circuit is analyzed using Monte Carlo simulation. Two inverter layout configurations are considered in the study and we deduce that a strong improvement in term of yield and power consumption can be obtained using a specific layout configuration where the tubes are shared for the P-CNTFET and the N-CNTFET.
Boolean Reasoning and Informed Search in the Minimization of Logic Circuits
1992-03-01
problem, he developed the substan- tial part of what is now called the Quine -McCluskey method for logic minimization. McCluskey’s ( McClu 56...Boolean Simplification. .. .. .. .. ... ... ... ... ... ..... 518 Map-Based Approaches. .. .. .. ... ... ... ... ... ...... 522 Quine -McCluskey Method...function is indicated by a capital letter, e.g., F. 5 which represents a function corresponds with the two-level design with the fewest AND gates. Quine
Do institutional logics predict interpretation of contract rules at the dental chair-side?
Harris, Rebecca; Brown, Stephen; Holt, Robin; Perkins, Elizabeth
2014-01-01
In quasi-markets, contracts find purchasers influencing health care providers, although problems exist where providers use personal bias and heuristics to respond to written agreements, tending towards the moral hazard of opportunism. Previous research on quasi-market contracts typically understands opportunism as fully rational, individual responses selecting maximally efficient outcomes from a set of possibilities. We take a more emotive and collective view of contracting, exploring the influence of institutional logics in relation to the opportunistic behaviour of dentists. Following earlier qualitative work where we identified four institutional logics in English general dental practice, and six dental contract areas where there was scope for opportunism; in 2013 we surveyed 924 dentists to investigate these logics and whether they had predictive purchase over dentists' chair-side behaviour. Factor analysis involving 300 responses identified four logics entwined in (often technical) behaviour: entrepreneurial commercialism, duty to staff and patients, managerialism, public good. PMID:25441320
Do institutional logics predict interpretation of contract rules at the dental chair-side?
Harris, Rebecca; Brown, Stephen; Holt, Robin; Perkins, Elizabeth
2014-12-01
In quasi-markets, contracts find purchasers influencing health care providers, although problems exist where providers use personal bias and heuristics to respond to written agreements, tending towards the moral hazard of opportunism. Previous research on quasi-market contracts typically understands opportunism as fully rational, individual responses selecting maximally efficient outcomes from a set of possibilities. We take a more emotive and collective view of contracting, exploring the influence of institutional logics in relation to the opportunistic behaviour of dentists. Following earlier qualitative work where we identified four institutional logics in English general dental practice, and six dental contract areas where there was scope for opportunism; in 2013 we surveyed 924 dentists to investigate these logics and whether they had predictive purchase over dentists' chair-side behaviour. Factor analysis involving 300 responses identified four logics entwined in (often technical) behaviour: entrepreneurial commercialism, duty to staff and patients, managerialism, public good.
Nucleic acid based logical systems.
Han, Da; Kang, Huaizhi; Zhang, Tao; Wu, Cuichen; Zhou, Cuisong; You, Mingxu; Chen, Zhuo; Zhang, Xiaobing; Tan, Weihong
2014-05-12
Researchers increasingly visualize a significant role for artificial biochemical logical systems in biological engineering, much like digital logic circuits in electrical engineering. Those logical systems could be utilized as a type of servomechanism to control nanodevices in vitro, monitor chemical reactions in situ, or regulate gene expression in vivo. Nucleic acids (NA), as carriers of genetic information with well-regulated and predictable structures, are promising materials for the design and engineering of biochemical circuits. A number of logical devices based on nucleic acids (NA) have been designed to handle various processes for technological or biotechnological purposes. This article focuses on the most recent and important developments in NA-based logical devices and their evolution from in vitro, through cellular, even towards in vivo biological applications.
NASA Astrophysics Data System (ADS)
Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng
2014-11-01
In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfOx thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ~46.2 cm2 V-1 s-1, 105 and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 μs. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism
NASA Astrophysics Data System (ADS)
Venkatesh, P. R.; Venkatesan, A.
2016-10-01
We report the occurrence of vibrational resonance in piecewise-linear non-autonomous system. Especially, we show that an optimal amplitude of the high frequency second harmonic driving enhances the response of a piece-wise linear non-autonomous Murali-Lakshmanan-Chua (MLC) system to a low frequency first harmonic signal. This phenomenon is illustrated with the analytical solutions of circuit equations characterising the system and finally compared with the numerical method. Further, it has been enunciated explicitly, the implementation of the fundamental NOR/NAND gate via vibrational resonance, both by numerical and analytical solutions. In addition, these logical behaviours (AND/NAND/OR/NOR) can be decided by the amplitude of the input square waves without altering the system parameters.
Xu, Weiwei; Liu, Zhen; Zhao, Jianwen; Xu, Wenya; Gu, Weibing; Zhang, Xiang; Qian, Long; Cui, Zheng
2014-12-21
In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfO(x) thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ∼ 46.2 cm(2) V(-1) s(-1), 10(5) and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 μs. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.
SET Characterization in Logic Gates Circuits Fabricated in a 3DIC Technology
2011-08-22
characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section between the three tiers...were characterized simultaneously on each tier during exposure to krypton heavy Ions. The difference In SET pulse width and cross-section between...test circuits was performed at Lawrence Berkeley National Laboratory with the 16 MeV ion cocktail using krypton (Kr) at normal incidence and in air
Fuzzy logic-based prognostic score for outcome prediction in esophageal cancer.
Wang, Chang-Yu; Lee, Tsair-Fwu; Fang, Chun-Hsiung; Chou, Jyh-Horng
2012-11-01
Given the poor prognosis of esophageal cancer and the invasiveness of combined modality treatment, improved prognostic scoring systems are needed. We developed a fuzzy logic-based system to improve the predictive performance of a risk score based on the serum concentrations of C-reactive protein (CRP) and albumin in a cohort of 271 patients with esophageal cancer before radiotherapy. Univariate and multivariate survival analyses were employed to validate the independent prognostic value of the fuzzy risk score. To further compare the predictive performance of the fuzzy risk score with other prognostic scoring systems, time-dependent receiver operating characteristic curve (ROC) analysis was used. Application of fuzzy logic to the serum values of CRP and albumin increased predictive performance for 1-year overall survival (AUC=0.773) compared with that of a single marker (AUC=0.743 and 0.700 for CRP and albumin, respectively), where the AUC denotes the area under curve. This fuzzy logic-based approach also performed consistently better than the Glasgow Prognostic Score (GPS) (AUC=0.745). Thus, application of fuzzy logic to the analysis of serum markers can more accurately predict the outcome for patients with esophageal cancer.
Optical flip-flops and sequential logic circuits using a liquid crystal light valve
NASA Technical Reports Server (NTRS)
Fatehi, M. T.; Collins, S. A., Jr.; Wasmundt, K. C.
1984-01-01
This paper is concerned with the application of optics to digital computing. A Hughes liquid crystal light valve is used as an active optical element where a weak light beam can control a strong light beam with either a positive or negative gain characteristic. With this device as the central element the ability to produce bistable states from which different types of flip-flop can be implemented is demonstrated. In this paper, some general comments are first presented on digital computing as applied to optics. This is followed by a discussion of optical implementation of various types of flip-flop. These flip-flops are then used in the design of optical equivalents to a few simple sequential circuits such as shift registers and accumulators. As a typical sequential machine, a schematic layout for an optical binary temporal integrator is presented. Finally, a suggested experimental configuration for an optical master-slave flip-flop array is given.
NASA Astrophysics Data System (ADS)
Di Pendina, G.; Prenat, G.; Dieny, B.; Torki, K.
2012-04-01
Since the advent of the MOS transistor, the performance of microelectronic circuits has followed Moore's law, stating that their speed and density would double every 18 months. Today, this trend tends to get out of breath: the continuously decreasing size of devices and increasing operation frequency result in power consumption and heating issues. Among the solutions investigated to circumvent these limitations, the use of non-volatile devices appears particularly promising. It allows easing, for example, the power gating technique, which consists in cutting-off the power supply of inactive blocks without losing information, drastically reducing the standby power consumption. In this approach, the advantages of magnetic tunnel junctions (MTJs) compared with other non-volatile devices allow one to design hybrid CMOS/magnetic circuits with high performance and new functionalities. Designing such circuits requires integrating MTJs in standard microelectronics design suites. This is performed by means of a process design kit (PDK) for the hybrid CMOS/magnetic technology. We present here a full magnetic PDK, which contains a compact model of the MTJ for electrical simulation, technology files for layout and physical verifications, and standard cells for the design of complex logic circuits and which is compatible with standard design suites. This PDK allows designers to accurately and comfortably design high-performance hybrid CMOS/magnetic logic circuits in the same way as standard CMOS circuits.
Noise-Aided Logic in an Electronic Analog of Synthetic Genetic Networks
Hellen, Edward H.; Dana, Syamal K.; Kurths, Jürgen; Kehler, Elizabeth; Sinha, Sudeshna
2013-01-01
We report the experimental verification of noise-enhanced logic behaviour in an electronic analog of a synthetic genetic network, composed of two repressors and two constitutive promoters. We observe good agreement between circuit measurements and numerical prediction, with the circuit allowing for robust logic operations in an optimal window of noise. Namely, the input-output characteristics of a logic gate is reproduced faithfully under moderate noise, which is a manifestation of the phenomenon known as Logical Stochastic Resonance. The two dynamical variables in the system yield complementary logic behaviour simultaneously. The system is easily morphed from AND/NAND to OR/NOR logic. PMID:24124531
NASA Astrophysics Data System (ADS)
Lanzalaco, Felix; Pissanetzky, Sergio
2013-12-01
A recent theory of physical information based on the fundamental principles of causality and thermodynamics has proposed that a large number of observable life and intelligence signals can be described in terms of the Causal Mathematical Logic (CML), which is proposed to encode the natural principles of intelligence across any physical domain and substrate. We attempt to expound the current definition of CML, the "Action functional" as a theory in terms of its ability to possess a superior explanatory power for the current neuroscientific data we use to measure the mammalian brains "intelligence" processes at its most general biophysical level. Brain simulation projects define their success partly in terms of the emergence of "non-explicitly programmed" complex biophysical signals such as self-oscillation and spreading cortical waves. Here we propose to extend the causal theory to predict and guide the understanding of these more complex emergent "intelligence Signals". To achieve this we review whether causal logic is consistent with, can explain and predict the function of complete perceptual processes associated with intelligence. Primarily those are defined as the range of Event Related Potentials (ERP) which include their primary subcomponents; Event Related Desynchronization (ERD) and Event Related Synchronization (ERS). This approach is aiming for a universal and predictive logic for neurosimulation and AGi. The result of this investigation has produced a general "Information Engine" model from translation of the ERD and ERS. The CML algorithm run in terms of action cost predicts ERP signal contents and is consistent with the fundamental laws of thermodynamics. A working substrate independent natural information logic would be a major asset. An information theory consistent with fundamental physics can be an AGi. It can also operate within genetic information space and provides a roadmap to understand the live biophysical operation of the phenotype
NASA Technical Reports Server (NTRS)
Richardson, Albert O.
1997-01-01
This research has investigated the use of fuzzy logic, via the Matlab Fuzzy Logic Tool Box, to design optimized controller systems. The engineering system for which the controller was designed and simulate was the container crane. The fuzzy logic algorithm that was investigated was the 'predictive control' algorithm. The plant dynamics of the container crane is representative of many important systems including robotic arm movements. The container crane that was investigated had a trolley motor and hoist motor. Total distance to be traveled by the trolley was 15 meters. The obstruction height was 5 meters. Crane height was 17.8 meters. Trolley mass was 7500 kilograms. Load mass was 6450 kilograms. Maximum trolley and rope velocities were 1.25 meters per sec. and 0.3 meters per sec., respectively. The fuzzy logic approach allowed the inclusion, in the controller model, of performance indices that are more effectively defined in linguistic terms. These include 'safety' and 'cargo swaying'. Two fuzzy inference systems were implemented using the Matlab simulation package, namely the Mamdani system (which relates fuzzy input variables to fuzzy output variables), and the Sugeno system (which relates fuzzy input variables to crisp output variable). It is found that the Sugeno FIS is better suited to including aspects of those plant dynamics whose mathematical relationships can be determined.
Knijnenburg, Theo A.; Klau, Gunnar W.; Iorio, Francesco; Garnett, Mathew J.; McDermott, Ultan; Shmulevich, Ilya; Wessels, Lodewyk F. A.
2016-01-01
Mining large datasets using machine learning approaches often leads to models that are hard to interpret and not amenable to the generation of hypotheses that can be experimentally tested. We present ‘Logic Optimization for Binary Input to Continuous Output’ (LOBICO), a computational approach that infers small and easily interpretable logic models of binary input features that explain a continuous output variable. Applying LOBICO to a large cancer cell line panel, we find that logic combinations of multiple mutations are more predictive of drug response than single gene predictors. Importantly, we show that the use of the continuous information leads to robust and more accurate logic models. LOBICO implements the ability to uncover logic models around predefined operating points in terms of sensitivity and specificity. As such, it represents an important step towards practical application of interpretable logic models. PMID:27876821
NASA Astrophysics Data System (ADS)
Knijnenburg, Theo A.; Klau, Gunnar W.; Iorio, Francesco; Garnett, Mathew J.; McDermott, Ultan; Shmulevich, Ilya; Wessels, Lodewyk F. A.
2016-11-01
Mining large datasets using machine learning approaches often leads to models that are hard to interpret and not amenable to the generation of hypotheses that can be experimentally tested. We present ‘Logic Optimization for Binary Input to Continuous Output’ (LOBICO), a computational approach that infers small and easily interpretable logic models of binary input features that explain a continuous output variable. Applying LOBICO to a large cancer cell line panel, we find that logic combinations of multiple mutations are more predictive of drug response than single gene predictors. Importantly, we show that the use of the continuous information leads to robust and more accurate logic models. LOBICO implements the ability to uncover logic models around predefined operating points in terms of sensitivity and specificity. As such, it represents an important step towards practical application of interpretable logic models.
Feasibility of using adaptive logic networks to predict compressor unit failure
Armstrong, W.W.; Chungying Chu; Thomas, M.M.
1995-12-31
In this feasibility study, an adaptive logic network (ALN) was trained to predict failures of turbine-driven compressor units using a large database of measurements. No expert knowledge about compressor systems was involved. The predictions used only the statistical properties of the measurements and the indications of failure types. A fuzzy set was used to model measurements typical of normal operation. It was constrained by a requirement imposed during ALN training, that it should have a shape similar to a Gaussian density, more precisely, that its logarithm should be convex-up. Initial results obtained using this approach to knowledge discovery in the database were encouraging.
Discovery of Drug Synergies in Gastric Cancer Cells Predicted by Logical Modeling.
Flobak, Åsmund; Baudot, Anaïs; Remy, Elisabeth; Thommesen, Liv; Thieffry, Denis; Kuiper, Martin; Lægreid, Astrid
2015-08-01
Discovery of efficient anti-cancer drug combinations is a major challenge, since experimental testing of all possible combinations is clearly impossible. Recent efforts to computationally predict drug combination responses retain this experimental search space, as model definitions typically rely on extensive drug perturbation data. We developed a dynamical model representing a cell fate decision network in the AGS gastric cancer cell line, relying on background knowledge extracted from literature and databases. We defined a set of logical equations recapitulating AGS data observed in cells in their baseline proliferative state. Using the modeling software GINsim, model reduction and simulation compression techniques were applied to cope with the vast state space of large logical models and enable simulations of pairwise applications of specific signaling inhibitory chemical substances. Our simulations predicted synergistic growth inhibitory action of five combinations from a total of 21 possible pairs. Four of the predicted synergies were confirmed in AGS cell growth real-time assays, including known effects of combined MEK-AKT or MEK-PI3K inhibitions, along with novel synergistic effects of combined TAK1-AKT or TAK1-PI3K inhibitions. Our strategy reduces the dependence on a priori drug perturbation experimentation for well-characterized signaling networks, by demonstrating that a model predictive of combinatorial drug effects can be inferred from background knowledge on unperturbed and proliferating cancer cells. Our modeling approach can thus contribute to preclinical discovery of efficient anticancer drug combinations, and thereby to development of strategies to tailor treatment to individual cancer patients.
Ferrite logic reliability study
NASA Technical Reports Server (NTRS)
Baer, J. A.; Clark, C. B.
1973-01-01
Development and use of digital circuits called all-magnetic logic are reported. In these circuits the magnetic elements and their windings comprise the active circuit devices in the logic portion of a system. The ferrite logic device belongs to the all-magnetic class of logic circuits. The FLO device is novel in that it makes use of a dual or bimaterial ferrite composition in one physical ceramic body. This bimaterial feature, coupled with its potential for relatively high speed operation, makes it attractive for high reliability applications. (Maximum speed of operation approximately 50 kHz.)
Zhou, Jingyu; Tian, Shulin; Yang, Chenglin
2014-01-01
Few researches pay attention to prediction about analog circuits. The few methods lack the correlation with circuit analysis during extracting and calculating features so that FI (fault indicator) calculation often lack rationality, thus affecting prognostic performance. To solve the above problem, this paper proposes a novel prediction method about single components of analog circuits based on complex field modeling. Aiming at the feature that faults of single components hold the largest number in analog circuits, the method starts with circuit structure, analyzes transfer function of circuits, and implements complex field modeling. Then, by an established parameter scanning model related to complex field, it analyzes the relationship between parameter variation and degeneration of single components in the model in order to obtain a more reasonable FI feature set via calculation. According to the obtained FI feature set, it establishes a novel model about degeneration trend of analog circuits' single components. At last, it uses particle filter (PF) to update parameters for the model and predicts remaining useful performance (RUP) of analog circuits' single components. Since calculation about the FI feature set is more reasonable, accuracy of prediction is improved to some extent. Finally, the foregoing conclusions are verified by experiments.
Mehri, M
2013-04-01
Application of appropriate models to approximate the performance function warrants more precise prediction and helps to make the best decisions in the poultry industry. This study reevaluated the factors affecting hatchability in laying hens from 29 to 56 wk of age. Twenty-eight data lines representing 4 inputs consisting of egg weight, eggshell thickness, egg sphericity, and yolk/albumin ratio and 1 output, hatchability, were obtained from the literature and used to train an artificial neural network (ANN). The prediction ability of ANN was compared with that of fuzzy logic to evaluate the fitness of these 2 methods. The models were compared using R(2), mean absolute deviation (MAD), mean squared error (MSE), mean absolute percentage error (MAPE), and bias. The developed model was used to assess the relative importance of each variable on the hatchability by calculating the variable sensitivity ratio. The statistical evaluations showed that the ANN-based model predicted hatchability more accurately than fuzzy logic. The ANN-based model had a higher determination of coefficient (R(2) = 0.99) and lower residual distribution (MAD = 0.005; MSE = 0.00004; MAPE = 0.732; bias = 0.0012) than fuzzy logic (R(2) = 0.87; MAD = 0.014; MSE = 0.0004; MAPE = 2.095; bias = 0.0046). The sensitivity analysis revealed that the most important variable in the ANN-based model of hatchability was egg weight (variable sensitivity ratio, VSR = 283.11), followed by yolk/albumin ratio (VSR = 113.16), eggshell thickness (VSR = 16.23), and egg sphericity (VSR = 3.63). The results of this research showed that the universal approximation capability of ANN made it a powerful tool to approximate complex functions such as hatchability in the incubation process.
Gómez, Antonio; Cedano, Juan; Espadaler, Jordi; Hermoso, Antonio; Piñol, Jaume; Querol, Enrique
2008-02-01
The functional annotation of the new protein sequences represents a major drawback for genomic science. The best way to suggest the function of a protein from its sequence is by finding a related one for which biological information is available. Current alignment algorithms display a list of protein sequence stretches presenting significant similarity to different protein targets, ordered by their respective mathematical scores. However, statistical and biological significance do not always coincide, therefore, the rearrangement of the program output according to more biological characteristics than the mathematical scoring would help functional annotation. A new method that predicts the putative function for the protein integrating the results from the PSI-BLAST program and a fuzzy logic algorithm is described. Several protein sequence characteristics have been checked in their ability to rearrange a PSI-BLAST profile according more to their biological functions. Four of them: amino acid content, matched segment length and hydropathic and flexibility profiles positively contributed, upon being integrated by a fuzzy logic algorithm into a program, BYPASS, to the accurate prediction of the function of a protein from its sequence.
Valencia-Palomo, G; Rossiter, J A
2011-01-01
This paper makes two key contributions. First, it tackles the issue of the availability of constrained predictive control for low-level control loops. Hence, it describes how the constrained control algorithm is embedded in an industrial programmable logic controller (PLC) using the IEC 61131-3 programming standard. Second, there is a definition and implementation of a novel auto-tuned predictive controller; the key novelty is that the modelling is based on relatively crude but pragmatic plant information. Laboratory experiment tests were carried out in two bench-scale laboratory systems to prove the effectiveness of the combined algorithm and hardware solution. For completeness, the results are compared with a commercial proportional-integral-derivative (PID) controller (also embedded in the PLC) using the most up to date auto-tuning rules.
King, R D; Srinivasan, A
1996-01-01
The machine learning program Progol was applied to the problem of forming the structure-activity relationship (SAR) for a set of compounds tested for carcinogenicity in rodent bioassays by the U.S. National Toxicology Program (NTP). Progol is the first inductive logic programming (ILP) algorithm to use a fully relational method for describing chemical structure in SARs, based on using atoms and their bond connectivities. Progol is well suited to forming SARs for carcinogenicity as it is designed to produce easily understandable rules (structural alerts) for sets of noncongeneric compounds. The Progol SAR method was tested by prediction of a set of compounds that have been widely predicted by other SAR methods (the compounds used in the NTP's first round of carcinogenesis predictions). For these compounds no method (human or machine) was significantly more accurate than Progol. Progol was the most accurate method that did not use data from biological tests on rodents (however, the difference in accuracy is not significant). The Progol predictions were based solely on chemical structure and the results of tests for Salmonella mutagenicity. Using the full NTP database, the prediction accuracy of Progol was estimated to be 63% (+/- 3%) using 5-fold cross validation. A set of structural alerts for carcinogenesis was automatically generated and the chemical rationale for them investigated- these structural alerts are statistically independent of the Salmonella mutagenicity. Carcinogenicity is predicted for the compounds used in the NTP's second round of carcinogenesis predictions. The results for prediction of carcinogenesis, taken together with the previous successful applications of predicting mutagenicity in nitroaromatic compounds, and inhibition of angiogenesis by suramin analogues, show that Progol has a role to play in understanding the SARs of cancer-related compounds. PMID:8933051
NASA Technical Reports Server (NTRS)
Burns, J. L.; Choma, J., Jr.
1982-01-01
A circuit model for an existing silicon integrated bipolar junction transistor (IBJT) is used to evaluate presently achievable high frequency circuit performance. The relationship between circuit model and processing parameters are semi-quantitatively explored to make predictions on the frequency response, which can be achieved through realistic device fabrication modifications. A new figure of merit is introduced, which is defined as the signal frequency at which an integrated bipolar junction transistor can deliver a power gain of G. The most sensitive parameter influencing attainable high frequency IBJT performance is base resistance.
NASA Technical Reports Server (NTRS)
Jafri, Madiha J.; Ely, Jay J.; Vahala, Linda L.
2007-01-01
In this paper, neural network (NN) modeling is combined with fuzzy logic to estimate Interference Path Loss measurements on Airbus 319 and 320 airplanes. Interference patterns inside the aircraft are classified and predicted based on the locations of the doors, windows, aircraft structures and the communication/navigation system-of-concern. Modeled results are compared with measured data. Combining fuzzy logic and NN modeling is shown to improve estimates of measured data over estimates obtained with NN alone. A plan is proposed to enhance the modeling for better prediction of electromagnetic coupling problems inside aircraft.
NASA Astrophysics Data System (ADS)
Tapoglou, Evdokia; Karatzas, George P.; Trichakis, Ioannis C.; Varouchakis, Emmanouil A.
2014-05-01
The purpose of this study is to examine the use of Artificial Neural Networks (ANN) combined with kriging interpolation method, in order to simulate the hydraulic head both spatially and temporally. Initially, ANNs are used for the temporal simulation of the hydraulic head change. The results of the most appropriate ANNs, determined through a fuzzy logic system, are used as an input for the kriging algorithm where the spatial simulation is conducted. The proposed algorithm is tested in an area located across Isar River in Bayern, Germany and covers an area of approximately 7800 km2. The available data extend to a time period from 1/11/2008 to 31/10/2012 (1460 days) and include the hydraulic head at 64 wells, temperature and rainfall at 7 weather stations and surface water elevation at 5 monitoring stations. One feedforward ANN was trained for each of the 64 wells, where hydraulic head data are available, using a backpropagation algorithm. The most appropriate input parameters for each wells' ANN are determined considering their proximity to the measuring station, as well as their statistical characteristics. For the rainfall, the data for two consecutive time lags for best correlated weather station, as well as a third and fourth input from the second best correlated weather station, are used as an input. The surface water monitoring stations with the three best correlations for each well are also used in every case. Finally, the temperature for the best correlated weather station is used. Two different architectures are considered and the one with the best results is used henceforward. The output of the ANNs corresponds to the hydraulic head change per time step. These predictions are used in the kriging interpolation algorithm. However, not all 64 simulated values should be used. The appropriate neighborhood for each prediction point is constructed based not only on the distance between known and prediction points, but also on the training and testing error of
Deng, Shijie; Morrison, Alan P
2012-09-15
This Letter presents an active quench-and-reset circuit for Geiger-mode avalanche photodiodes (GM-APDs). The integrated circuit was fabricated using a conventional 0.35 μm complementary metal oxide semiconductor process. Experimental results show that the circuit is capable of linearly setting the hold-off time from several nanoseconds to microseconds with a resolution of 6.5 ns. This allows the selection of the optimal afterpulse-free hold-off time for the GM-APD via external digital inputs or additional signal processing circuitry. Moreover, this circuit resets the APD automatically following the end of the hold-off period, thus simplifying the control for the end user. Results also show that a minimum dead time of 28.4 ns is achieved, demonstrating a saturated photon-counting rate of 35.2 Mcounts/s.
Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki
2016-07-20
We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.
Logic programming to predict cell fate patterns and retrodict genotypes in organogenesis
Hall, Benjamin A.; Jackson, Ethan; Hajnal, Alex; Fisher, Jasmin
2014-01-01
Caenorhabditis elegans vulval development is a paradigm system for understanding cell differentiation in the process of organogenesis. Through temporal and spatial controls, the fate pattern of six cells is determined by the competition of the LET-23 and the Notch signalling pathways. Modelling cell fate determination in vulval development using state-based models, coupled with formal analysis techniques, has been established as a powerful approach in predicting the outcome of combinations of mutations. However, computing the outcomes of complex and highly concurrent models can become prohibitive. Here, we show how logic programs derived from state machines describing the differentiation of C. elegans vulval precursor cells can increase the speed of prediction by four orders of magnitude relative to previous approaches. Moreover, this increase in speed allows us to infer, or ‘retrodict’, compatible genomes from cell fate patterns. We exploit this technique to predict highly variable cell fate patterns resulting from dig-1 reduced-function mutations and let-23 mosaics. In addition to the new insights offered, we propose our technique as a platform for aiding the design and analysis of experimental data. PMID:24966232
Logic programming to predict cell fate patterns and retrodict genotypes in organogenesis.
Hall, Benjamin A; Jackson, Ethan; Hajnal, Alex; Fisher, Jasmin
2014-09-06
Caenorhabditis elegans vulval development is a paradigm system for understanding cell differentiation in the process of organogenesis. Through temporal and spatial controls, the fate pattern of six cells is determined by the competition of the LET-23 and the Notch signalling pathways. Modelling cell fate determination in vulval development using state-based models, coupled with formal analysis techniques, has been established as a powerful approach in predicting the outcome of combinations of mutations. However, computing the outcomes of complex and highly concurrent models can become prohibitive. Here, we show how logic programs derived from state machines describing the differentiation of C. elegans vulval precursor cells can increase the speed of prediction by four orders of magnitude relative to previous approaches. Moreover, this increase in speed allows us to infer, or 'retrodict', compatible genomes from cell fate patterns. We exploit this technique to predict highly variable cell fate patterns resulting from dig-1 reduced-function mutations and let-23 mosaics. In addition to the new insights offered, we propose our technique as a platform for aiding the design and analysis of experimental data.
Yu, Xue; Lian, Wenjing; Zhang, Jiannan; Liu, Hongyun
2016-06-15
Herein, poly(N-isopropylacrylamide-co-N,N'-dimethylaminoethylmethacrylate) copolymer films were polymerized on electrode surface with a simple one-step method, and the enzyme horseradish peroxidase (HRP) was embedded in the films simultaneously, which were designated as P(NiPAAm-co-DMEM)-HRP. The films exhibited a reversible structure change with the external stimuli, such as pH, CO2, temperature and SO4(2-), causing the cyclic voltammetric (CV) response of electroactive K3Fe(CN)6 at the film electrodes to display the corresponding multi-stimuli sensitive ON-OFF behavior. Based on the switchable CV property of the system and the electrochemical reduction of H2O2 catalyzed by HRP in the films and mediated by Fe(CN)6(3-) in solution, a 5-input/3-output logic gate was established. To further increase the complexity of the logic system, another enzyme glucose oxidase (GOD) was added into the films, designated as P(NiPAAm-co-DMEM)-HRP-GOD. In the presence of oxygen, the oxidation of glucose in the solution was catalyzed by GOD in the films, and the produced H2O2 in situ was recognized and electrocatalytically reduced by HRP and mediated by Fe(CN)6(3-). Based on the bienzyme films, a cascaded or concatenated 4-input/3-output logic gate system was proposed. The present work combined the multi-responsive interface with bioelectrocatalysis to construct cascaded logic circuits, which might open a new avenue to develop biocomputing elements with more sophisticated functions and design novel glucose biosensors.
Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan
2016-02-23
We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.
A reconfigurable NAND/NOR genetic logic gate
2012-01-01
Background Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. Results We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. Conclusions We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications. PMID:22989145
Simulated Laboratory in Digital Logic.
ERIC Educational Resources Information Center
Cleaver, Thomas G.
Design of computer circuits used to be a pencil and paper task followed by laboratory tests, but logic circuit design can now be done in half the time as the engineer accesses a program which simulates the behavior of real digital circuits, and does all the wiring and testing on his computer screen. A simulated laboratory in digital logic has been…
Spatiotemporal prediction applying fuzzy logic in a sequence of satellite images
NASA Astrophysics Data System (ADS)
Mezzadri-Centeno, Tania; Selleron, Gilles
2002-01-01
Spatial evolutions of anthropized ecosystems and the progressive transformation of spaces in the course of time emerge more and more as a special interest issue in researches about the environment. This evolution constitutes one of the major concerns in the domain of environmental space management. The landscape evolution of a region area and the perspectives for a future state rises an issue particularly important. What will be the state of the region in 15, 30 or 50 years? Time can produce transformations over a region area like emergence, disappearance or union of spatial entities... These transformations are called temporal phenomena. We propose to predict the forestry evolution in the forthcoming years on an experimental area, which reveals these spatial transformations. The proposed method is based on the analysis of terrain landscape given a sequence of n satellite images, which represent the state of a region area in different years. For these purposes, we have developed a specific spatio-temporal prediction approach, linking results of forestry evolution analysis and fuzzy logic. The method is supported by the analysis of the landscape dynamics of a test-site located in a tropical rain country: the oriental piedmont of Andes Mountain in Venezuela. This large area - at the scale of a spot satellite image - is typical of tropical deforestation in a pioneer front. The presented approach allows the geographer interested in environmental prospective problems to get type cartographical documents showing future conditions of a landscape. The experimental tests have showed promising results.
Chen, Junhua; Zhou, Shungui; Wen, Junlin
2015-01-07
Concatenated logic circuits operating as a biocomputing keypad-lock security system with an automatic reset function have been successfully constructed on the basis of toehold-mediated strand displacement and three-way-DNA-junction architecture. In comparison with previously reported keypad locks, the distinctive advantage of the proposed security system is that it can be reset and cycled spontaneously a large number of times without an external stimulus, thus making practical applications possible. By the use of a split-G-quadruplex DNAzyme as the signal reporter, the output of the keypad lock can be recognized readily by the naked eye. The "lock" is opened only when the inputs are introduced in an exact order. This requirement provides defense against illegal invasion to protect information at the molecular scale.
NASA Astrophysics Data System (ADS)
Loch-Dehbi, S.; Dehbi, Y.; Gröger, G.; Plümer, L.
2016-10-01
This paper introduces a novel method for the automatic derivation of building floorplans and indoor models. Our approach is based on a logical and stochastic reasoning using sparse observations such as building room areas. No further sensor observations like 3D point clouds are needed. Our method benefits from an extensive prior knowledge of functional dependencies and probability density functions of shape and location parameters of rooms depending on their functional use. The determination of posterior beliefs is performed using Bayesian Networks. Stochastic reasoning is complex since the problem is characterized by a mixture of discrete and continuous parameters that are in turn correlated by non-linear constraints. To cope with this kind of complexity, the proposed reasoner combines statistical methods with constraint propagation. It generates a limited number of hypotheses in a model-based top-down approach. It predicts floorplans based on a-priori localised windows. The use of Gaussian mixture models, constraint solvers and stochastic models helps to cope with the a-priori infinite space of the possible floorplan instantiations.
Coelho, Antonio Augusto Rodrigues
2016-01-01
This paper introduces the Fuzzy Logic Hypercube Interpolator (FLHI) and demonstrates applications in control of multiple-input single-output (MISO) and multiple-input multiple-output (MIMO) processes with Hammerstein nonlinearities. FLHI consists of a Takagi-Sugeno fuzzy inference system where membership functions act as kernel functions of an interpolator. Conjunction of membership functions in an unitary hypercube space enables multivariable interpolation of N-dimensions. Membership functions act as interpolation kernels, such that choice of membership functions determines interpolation characteristics, allowing FLHI to behave as a nearest-neighbor, linear, cubic, spline or Lanczos interpolator, to name a few. The proposed interpolator is presented as a solution to the modeling problem of static nonlinearities since it is capable of modeling both a function and its inverse function. Three study cases from literature are presented, a single-input single-output (SISO) system, a MISO and a MIMO system. Good results are obtained regarding performance metrics such as set-point tracking, control variation and robustness. Results demonstrate applicability of the proposed method in modeling Hammerstein nonlinearities and their inverse functions for implementation of an output compensator with Model Based Predictive Control (MBPC), in particular Dynamic Matrix Control (DMC). PMID:27657723
Plastic corollary discharge predicts sensory consequences of movements in a cerebellum-like circuit
Requarth, Tim; Sawtell, Nathaniel B.
2014-01-01
SUMMARY The capacity to predict the sensory consequences of movements is critical for sensory, motor, and cognitive function. Though it is hypothesized that internal signals related to motor commands, known as corollary discharge, serve to generate such predictions, this process remains poorly understood at the neural circuit level. Here we demonstrate that neurons in the electrosensory lobe (ELL) of weakly electric mormyrid fish generate negative images of the sensory consequences of the fish’s own movements based on ascending spinal corollary discharge signals. These results generalize previous findings describing mechanisms for generating negative images of the effects of the fish’s specialized electric organ discharge (EOD) and suggest that a cerebellum-like circuit endowed with associative synaptic plasticity acting on corollary discharge can solve the complex and ubiquitous problem of predicting sensory consequences of movements. PMID:24853945
Plastic corollary discharge predicts sensory consequences of movements in a cerebellum-like circuit.
Requarth, Tim; Sawtell, Nathaniel B
2014-05-21
The capacity to predict the sensory consequences of movements is critical for sensory, motor, and cognitive function. Though it is hypothesized that internal signals related to motor commands, known as corollary discharge, serve to generate such predictions, this process remains poorly understood at the neural circuit level. Here we demonstrate that neurons in the electrosensory lobe (ELL) of weakly electric mormyrid fish generate negative images of the sensory consequences of the fish's own movements based on ascending spinal corollary discharge signals. These results generalize previous findings describing mechanisms for generating negative images of the effects of the fish's specialized electric organ discharge (EOD) and suggest that a cerebellum-like circuit endowed with associative synaptic plasticity acting on corollary discharge can solve the complex and ubiquitous problem of predicting sensory consequences of movements.
Fundamentals of Digital Logic.
ERIC Educational Resources Information Center
Noell, Monica L.
This course is designed to prepare electronics personnel for further training in digital techniques, presenting need to know information that is basic to any maintenance course on digital equipment. It consists of seven study units: (1) binary arithmetic; (2) boolean algebra; (3) logic gates; (4) logic flip-flops; (5) nonlogic circuits; (6)…
A prediction technique for single-event effects on complex integrated circuits
NASA Astrophysics Data System (ADS)
Yuanfu, Zhao; Chunqing, Yu; Long, Fan; Suge, Yue; Maoxin, Chen; Shougang, Du; Hongchao, Zheng
2015-11-01
The sensitivity of complex integrated circuits to single-event effects is investigated. Sensitivity depends not only on the cross section of physical modules but also on the behavior of data patterns running on the system. A method dividing the main functional modules is proposed. The intrinsic cross section and the duty cycles of different sensitive modules are obtained during the execution of data patterns. A method for extracting the duty cycle is presented and a set of test patterns with different duty cycles are implemented experimentally. By combining the intrinsic cross section and the duty cycle of different sensitive modules, a universal method to predict SEE sensitivities of different test patterns is proposed, which is verified by experiments based on the target circuit of a microprocessor. Experimental results show that the deviation between prediction and experiment is less than 20%.
NASA Astrophysics Data System (ADS)
Aliouane, Leila; Ouadfeul, Sid-Ali; Boudella, Amar
2015-04-01
The main goal of the proposed idea is to use the artificial intelligence such as the neural network and fuzzy logic to predict the pore pressure in shale gas reservoirs. Pore pressure is a very important parameter that will be used or estimation of effective stress. This last is used to resolve well-bore stability problems, failure plan identification from Mohr-Coulomb circle and sweet spots identification. Many models have been proposed to estimate the pore pressure from well-logs data; we can cite for example the equivalent depth model, the horizontal model for undercompaction called the Eaton's model…etc. All these models require a continuous measurement of the slowness of the primary wave, some thing that is not easy during well-logs data acquisition in shale gas formtions. Here, we suggest the use the fuzzy logic and the multilayer perceptron neural network to predict the pore pressure in two horizontal wells drilled in the lower Barnett shale formation. The first horizontal well is used for the training of the fuzzy set and the multilayer perecptron, the input is the natural gamma ray, the neutron porosity, the slowness of the compression and shear wave, however the desired output is the estimated pore pressure using Eaton's model. Data of another horizontal well are used for generalization. Obtained results clearly show the power of the fuzzy logic system than the multilayer perceptron neural network machine to predict the pore pressure in shale gas reservoirs. Keywords: artificial intelligence, fuzzy logic, pore pressure, multilayer perecptron, Barnett shale.
Gallium Arsenide Domino Circuit
NASA Technical Reports Server (NTRS)
Yang, Long; Long, Stephen I.
1990-01-01
Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.
Emergence of complex behaviour from simple circuit structures.
Kaufman, Marcelle; Thomas, René
2003-02-01
The set of (feedback) circuits of a complex system is the machinery that allows the system to be aware of the levels of its crucial constituents. Circuits can be identified without ambiguity from the elements of the Jacobian matrix of the system. There are two types of circuits: positive if they comprise an even number of negative interactions, negative if this number is odd. The two types of circuits play deeply different roles: negative circuits are required for homeostasis, with or without oscillations, positive circuits are required for multistationarity, and hence, in biology, for differentiation and memory. In non-linear systems, a circuit can positive or negative (an 'ambiguous circuit', depending on the location in phase space. Full circuits are those circuits (or unions of disjoint circuits) that imply all the variables of the system. There is a tight relation between circuits and steady states. Each full circuit, if isolated, generates steady state(s) whose nature (eigenvalues) is determined by the structure of the circuit. Multistationarity requires the presence of at least two full circuits of opposite Eisenfeld signs, or else, an ambiguous circuit. We show how a significant part of the dynamical behaviour of a system can be predicted by a mere examination of its Jacobian matrix. We also show how extremely complex dynamics can be generated by such simple logical structures as a single (full and ambiguous) circuit.
Okamoto, Akimitsu; Tanaka, Kazuo; Saito, Isao
2004-08-04
A conceptually new logic gate based on DNA has been devised. Methoxybenzodeazaadenine ((MD)A), an artificial nucleobase which we recently developed for efficient hole transport through DNA, formed stable base pairs with T and C. However, a reasonable hole-transport efficiency was observed in the reaction for the duplex containing an (MD)A/T base pair, whereas the hole transport was strongly suppressed in the reaction using a duplex where the base opposite (MD)A was replaced by C. The influence of complementary pyrimidines on the efficiency of hole transport through (MD)A was quite contrary to the selectivity observed for hole transport through G. The orthogonality of the modulation of these hole-transport properties by complementary pyrimidine bases is promising for the design of a new molecular logic gate. The logic gate system was executed by hole transport through short DNA duplexes, which consisted of the "logic gate strand", containing hole-transporting nucleobases, and the "input strand", containing pyrimidines which modulate the hole-transport efficiency of logic bases. A logic gate strand containing multiple (MD)A bases in series provided the basis for a sharp AND logic action. On the other hand, for OR logic and combinational logic, conversion of Boolean expressions to standard sum-of-product (SOP) expressions was indispensable. Three logic gate strands were designed for OR logic according to each product term in the standard SOP expression of OR logic. The hole-transport efficiency observed for the mixed sample of logic gate strands exhibited an OR logic behavior. This approach is generally applicable to the design of other complicated combinational logic circuits such as the full-adder.
Wolpe, Noham; Ingram, James N; Tsvetanov, Kamen A; Geerligs, Linda; Kievit, Rogier A; Henson, Richard N; Wolpert, Daniel M; Rowe, James B
2016-10-03
The control of voluntary movement changes markedly with age. A critical component of motor control is the integration of sensory information with predictions of the consequences of action, arising from internal models of movement. This leads to sensorimotor attenuation-a reduction in the perceived intensity of sensations from self-generated compared with external actions. Here we show that sensorimotor attenuation occurs in 98% of adults in a population-based cohort (n=325; 18-88 years; the Cambridge Centre for Ageing and Neuroscience). Importantly, attenuation increases with age, in proportion to reduced sensory sensitivity. This effect is associated with differences in the structure and functional connectivity of the pre-supplementary motor area (pre-SMA), assessed with magnetic resonance imaging. The results suggest that ageing alters the balance between the sensorium and predictive models, mediated by the pre-SMA and its connectivity in frontostriatal circuits. This shift may contribute to the motor and cognitive changes observed with age.
Wang, Chen; Zhao, Wu; Wang, Jie; Chen, Ling; Luo, Chun-Jing
2016-06-01
The printed circuit boards basis of electronic equipment have seen a rapid growth in recent years and played a significant role in modern life. Nowadays, the fact that electronic devices upgrade quickly necessitates a proper management of waste printed circuit boards. Non-destructive desoldering of waste printed circuit boards becomes the first and the most crucial step towards recycling electronic components. Owing to the diversity of materials and components, the separation process is difficult, which results in complex and expensive recovery of precious materials and electronic components from waste printed circuit boards. To cope with this problem, we proposed an innovative approach integrating Theory of Inventive Problem Solving (TRIZ) evolution theory and technology maturity mapping system to forecast the evolution trends of desoldering technology of waste printed circuit boards. This approach can be applied to analyse the technology evolution, as well as desoldering technology evolution, then research and development strategy and evolution laws can be recommended. As an example, the maturity of desoldering technology is analysed with a technology maturity mapping system model. What is more, desoldering methods in different stages are analysed and compared. According to the analysis, the technological evolution trends are predicted to be 'the law of energy conductivity' and 'increasing the degree of idealisation'. And the potential technology and evolutionary state of waste printed circuit boards are predicted, offering reference for future waste printed circuit boards recycling.
2014-10-03
introduce distributed logics. Distributed logics lift the distribution structure of a distributed system directly into the logic, thereby parameterizing...the logic by the distribution structure itself. Each domain supports a “local modal logic.” The connections between domains are realized as...There are also multi- agent logic systems [12]. What distinguishes distributed logics from these are that the morphisms, i.e., the nbd maps, have
de Franciscis, Stefano; Fregola, Salvatore; Gallo, Alessandro; Argirò, Giuseppe; Barbetta, Andrea; Buffone, Gianluca; Caliò, Francesco G; De Caridi, Giovanni; Amato, Bruno; Serra, Raffaele
2016-12-01
Chronic leg ulcers (CLUs) are a common occurrence in the western population and are associated with a negative impact on the quality of life of patients. They also cause a substantial burden on the health budget. The pathogenesis of leg ulceration is quite heterogeneous, and chronic venous ulceration (CVU) is the most common manifestation representing the main complication of chronic venous disease (CVD). Prevention strategies and early identification of the risk represent the best form of management. Fuzzy logic is a flexible mathematical system that has proved to be a powerful tool for decision-making systems and pattern classification systems in medicine. In this study, we have elaborated a computerised prediction system for chronic leg ulcers (PredyCLU) based on fuzzy logic, which was retrospectively applied on a multicentre population of 77 patients with CVD. This evaluation system produced reliable risk score patterns and served effectively as a stratification risk tool in patients with CVD who were at the risk of developing CVUs.
A Model for Predicting Integrated Man-Machine System Reliability: Model Logic and Description
1974-11-01
A MODEL FOR PREDICTING INTEGRATED MAN-MACHINE SYSTEMS RELIABILITY prepared for Naval Si nand Deparrmem aw nr. Con :’III’lit UNCLASSIFIED...was substantially modified so as to allow its use for system reliability and system availability predictive purposes. The resultant new model is...from 4 to 20 members was substantially modified so as to allow its use for system reliability and system availability predictive purposes. The
Using LogicWorks to Teach Logic Design.
ERIC Educational Resources Information Center
Spoerri, Peter
1988-01-01
Discusses a computer simulation to teach logic design using a Macintosh computer which allows circuits to be built piece by piece. Describes features of the simulation and presents several schematics drawn by the software. (MVL)
Electronic logic for enhanced switch reliability
Cooper, J.A.
1984-01-20
A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and fail-safe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.
The Use of a Predictive Habitat Model and a Fuzzy Logic Approach for Marine Management and Planning
Hattab, Tarek; Ben Rais Lasram, Frida; Albouy, Camille; Sammari, Chérif; Romdhane, Mohamed Salah; Cury, Philippe; Leprieur, Fabien; Le Loc’h, François
2013-01-01
Bottom trawl survey data are commonly used as a sampling technique to assess the spatial distribution of commercial species. However, this sampling technique does not always correctly detect a species even when it is present, and this can create significant limitations when fitting species distribution models. In this study, we aim to test the relevance of a mixed methodological approach that combines presence-only and presence-absence distribution models. We illustrate this approach using bottom trawl survey data to model the spatial distributions of 27 commercially targeted marine species. We use an environmentally- and geographically-weighted method to simulate pseudo-absence data. The species distributions are modelled using regression kriging, a technique that explicitly incorporates spatial dependence into predictions. Model outputs are then used to identify areas that met the conservation targets for the deployment of artificial anti-trawling reefs. To achieve this, we propose the use of a fuzzy logic framework that accounts for the uncertainty associated with different model predictions. For each species, the predictive accuracy of the model is classified as ‘high’. A better result is observed when a large number of occurrences are used to develop the model. The map resulting from the fuzzy overlay shows that three main areas have a high level of agreement with the conservation criteria. These results align with expert opinion, confirming the relevance of the proposed methodology in this study. PMID:24146867
Wolpe, Noham; Ingram, James N.; Tsvetanov, Kamen A.; Geerligs, Linda; Kievit, Rogier A.; Henson, Richard N.; Wolpert, Daniel M.; Tyler, Lorraine K.; Brayne, Carol; Bullmore, Edward; Calder, Andrew; Cusack, Rhodri; Dalgleish, Tim; Duncan, John; Matthews, Fiona E.; Marslen-Wilson, William; Shafto, Meredith A.; Campbell, Karen; Cheung, Teresa; Davis, Simon; McCarrey, Anna; Mustafa, Abdur; Price, Darren; Samu, David; Taylor, Jason R.; Treder, Matthias; van Belle, Janna; Williams, Nitin; Bates, Lauren; Emery, Tina; Erzinçlioglu, Sharon; Gadie, Andrew; Gerbase, Sofia; Georgieva, Stanimira; Hanley, Claire; Parkin, Beth; Troy, David; Auer, Tibor; Correia, Marta; Gao, Lu; Green, Emma; Henriques, Rafael; Allen, Jodie; Amery, Gillian; Amunts, Liana; Barcroft, Anne; Castle, Amanda; Dias, Cheryl; Dowrick, Jonathan; Fair, Melissa; Fisher, Hayley; Goulding, Anna; Grewal, Adarsh; Hale, Geoff; Hilton, Andrew; Johnson, Frances; Johnston, Patricia; Kavanagh-Williamson, Thea; Kwasniewska, Magdalena; McMinn, Alison; Norman, Kim; Penrose, Jessica; Roby, Fiona; Rowland, Diane; Sargeant, John; Squire, Maggie; Stevens, Beth; Stoddart, Aldabra; Stone, Cheryl; Thompson, Tracy; Yazlik, Ozlem; Barnes, Dan; Dixon, Marie; Hillman, Jaya; Mitchell, Joanne; Villis, Laura; Rowe, James B.
2016-01-01
The control of voluntary movement changes markedly with age. A critical component of motor control is the integration of sensory information with predictions of the consequences of action, arising from internal models of movement. This leads to sensorimotor attenuation—a reduction in the perceived intensity of sensations from self-generated compared with external actions. Here we show that sensorimotor attenuation occurs in 98% of adults in a population-based cohort (n=325; 18–88 years; the Cambridge Centre for Ageing and Neuroscience). Importantly, attenuation increases with age, in proportion to reduced sensory sensitivity. This effect is associated with differences in the structure and functional connectivity of the pre-supplementary motor area (pre-SMA), assessed with magnetic resonance imaging. The results suggest that ageing alters the balance between the sensorium and predictive models, mediated by the pre-SMA and its connectivity in frontostriatal circuits. This shift may contribute to the motor and cognitive changes observed with age. PMID:27694879
Vianco, P.T.; Erickson, K.L.; Hopkins, P.L.
1997-12-31
A mathematical model was developed to quantitatively describe the intermetallic compound (IMC) layer growth that takes place between a Sn-based solder and a noble metal thick film conductor material used in hybrid microcircuit (HMC) assemblies. The model combined the reaction kinetics of the solder/substrate interaction, as determined from ancillary isothermal aging experiments, with a 2-D finite element mesh that took account of the porous morphology of the thick film coating. The effect of the porous morphology on the IMC layer growth when compared to the traditional 1-D computations was significant. The previous 1-D calculations under-predicted the nominal IMC layer thickness relative to the 2-D case. The 2-D model showed greater substrate consumption by IMC growth and lesser solder consumption that was determined with the 1-D computation. The new 2-D model allows the design engineer to better predict circuit aging and hence, the reliability of HMC hardware that is placed in the field.
Abrams, Daniel A.; Chen, Tianwen; Odriozola, Paola; Cheng, Katherine M.; Baker, Amanda E.; Padmanabhan, Aarthi; Ryali, Srikanth; Kochalka, John; Feinstein, Carl; Menon, Vinod
2016-01-01
The human voice is a critical social cue, and listeners are extremely sensitive to the voices in their environment. One of the most salient voices in a child’s life is mother's voice: Infants discriminate their mother’s voice from the first days of life, and this stimulus is associated with guiding emotional and social function during development. Little is known regarding the functional circuits that are selectively engaged in children by biologically salient voices such as mother’s voice or whether this brain activity is related to children’s social communication abilities. We used functional MRI to measure brain activity in 24 healthy children (mean age, 10.2 y) while they attended to brief (<1 s) nonsense words produced by their biological mother and two female control voices and explored relationships between speech-evoked neural activity and social function. Compared to female control voices, mother’s voice elicited greater activity in primary auditory regions in the midbrain and cortex; voice-selective superior temporal sulcus (STS); the amygdala, which is crucial for processing of affect; nucleus accumbens and orbitofrontal cortex of the reward circuit; anterior insula and cingulate of the salience network; and a subregion of fusiform gyrus associated with face perception. The strength of brain connectivity between voice-selective STS and reward, affective, salience, memory, and face-processing regions during mother’s voice perception predicted social communication skills. Our findings provide a novel neurobiological template for investigation of typical social development as well as clinical disorders, such as autism, in which perception of biologically and socially salient voices may be impaired. PMID:27185915
Abrams, Daniel A; Chen, Tianwen; Odriozola, Paola; Cheng, Katherine M; Baker, Amanda E; Padmanabhan, Aarthi; Ryali, Srikanth; Kochalka, John; Feinstein, Carl; Menon, Vinod
2016-05-31
The human voice is a critical social cue, and listeners are extremely sensitive to the voices in their environment. One of the most salient voices in a child's life is mother's voice: Infants discriminate their mother's voice from the first days of life, and this stimulus is associated with guiding emotional and social function during development. Little is known regarding the functional circuits that are selectively engaged in children by biologically salient voices such as mother's voice or whether this brain activity is related to children's social communication abilities. We used functional MRI to measure brain activity in 24 healthy children (mean age, 10.2 y) while they attended to brief (<1 s) nonsense words produced by their biological mother and two female control voices and explored relationships between speech-evoked neural activity and social function. Compared to female control voices, mother's voice elicited greater activity in primary auditory regions in the midbrain and cortex; voice-selective superior temporal sulcus (STS); the amygdala, which is crucial for processing of affect; nucleus accumbens and orbitofrontal cortex of the reward circuit; anterior insula and cingulate of the salience network; and a subregion of fusiform gyrus associated with face perception. The strength of brain connectivity between voice-selective STS and reward, affective, salience, memory, and face-processing regions during mother's voice perception predicted social communication skills. Our findings provide a novel neurobiological template for investigation of typical social development as well as clinical disorders, such as autism, in which perception of biologically and socially salient voices may be impaired.
Assessment and prediction of air quality using fuzzy logic and autoregressive models
NASA Astrophysics Data System (ADS)
Carbajal-Hernández, José Juan; Sánchez-Fernández, Luis P.; Carrasco-Ochoa, Jesús A.; Martínez-Trinidad, José Fco.
2012-12-01
In recent years, artificial intelligence methods have been used for the treatment of environmental problems. This work, presents two models for assessment and prediction of air quality. First, we develop a new computational model for air quality assessment in order to evaluate toxic compounds that can harm sensitive people in urban areas, affecting their normal activities. In this model we propose to use a Sigma operator to statistically asses air quality parameters using their historical data information and determining their negative impact in air quality based on toxicity limits, frequency average and deviations of toxicological tests. We also introduce a fuzzy inference system to perform parameter classification using a reasoning process and integrating them in an air quality index describing the pollution levels in five stages: excellent, good, regular, bad and danger, respectively. The second model proposed in this work predicts air quality concentrations using an autoregressive model, providing a predicted air quality index based on the fuzzy inference system previously developed. Using data from Mexico City Atmospheric Monitoring System, we perform a comparison among air quality indices developed for environmental agencies and similar models. Our results show that our models are an appropriate tool for assessing site pollution and for providing guidance to improve contingency actions in urban areas.
Exchange circuits for FASTBUS slaves
Bratskii, A.A.; Matseev, M.Y.; Rybakov, V.G.
1985-09-01
This paper describes general-purpose circuits for FASTBUS interfacing of the functional part of a slave device. The circuits contain buffered receivers and transmitters, addressrecognition and data-transfer logic, and the required control/status registers. The described circuits are implemented with series-K500 integrated circuits.
Superconducting flux flow digital circuits
Hietala, Vincent M.; Martens, Jon S.; Zipperian, Thomas E.
1995-01-01
A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs). Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics.
Superconducting flux flow digital circuits
Hietala, V.M.; Martens, J.S.; Zipperian, T.E.
1995-02-14
A NOR/inverter logic gate circuit and a flip flop circuit implemented with superconducting flux flow transistors (SFFTs) are disclosed. Both circuits comprise two SFFTs with feedback lines. They have extremely low power dissipation, very high switching speeds, and the ability to interface between Josephson junction superconductor circuits and conventional microelectronics. 8 figs.
Radiation tolerant combinational logic cell
NASA Technical Reports Server (NTRS)
Maki, Gary R. (Inventor); Gambles, Jody W. (Inventor); Whitaker, Sterling (Inventor)
2009-01-01
A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.
Corrosion of silicon integrated circuits and lifetime predictions in implantable electronic devices
NASA Astrophysics Data System (ADS)
Vanhoestenberghe, A.; Donaldson, N.
2013-06-01
Corrosion is a prime concern for active implantable devices. In this paper we review the principles underlying the concepts of hermetic packages and encapsulation, used to protect implanted electronics, some of which remain widely overlooked. We discuss how technological advances have created a need to update the way we evaluate the suitability of both protection methods. We demonstrate how lifetime predictability is lost for very small hermetic packages and introduce a single parameter to compare different packages, with an equation to calculate the minimum sensitivity required from a test method to guarantee a given lifetime. In the second part of this paper, we review the literature on the corrosion of encapsulated integrated circuits (ICs) and, following a new analysis of published data, we propose an equation for the pre-corrosion lifetime of implanted ICs, and discuss the influence of the temperature, relative humidity, encapsulation and field-strength. As any new protection will be tested under accelerated conditions, we demonstrate the sensitivity of acceleration factors to some inaccurately known parameters. These results are relevant for any application of electronics working in a moist environment. Our comparison of encapsulation and hermetic packages suggests that both concepts may be suitable for future implants.
A formalized design process for bacterial consortia that perform logic computing.
Ji, Weiyue; Shi, Handuo; Zhang, Haoqian; Sun, Rui; Xi, Jingyi; Wen, Dingqiao; Feng, Jingchen; Chen, Yiwei; Qin, Xiao; Ma, Yanrong; Luo, Wenhan; Deng, Linna; Lin, Hanchi; Yu, Ruofan; Ouyang, Qi
2013-01-01
The concept of microbial consortia is of great attractiveness in synthetic biology. Despite of all its benefits, however, there are still problems remaining for large-scaled multicellular gene circuits, for example, how to reliably design and distribute the circuits in microbial consortia with limited number of well-behaved genetic modules and wiring quorum-sensing molecules. To manage such problem, here we propose a formalized design process: (i) determine the basic logic units (AND, OR and NOT gates) based on mathematical and biological considerations; (ii) establish rules to search and distribute simplest logic design; (iii) assemble assigned basic logic units in each logic operating cell; and (iv) fine-tune the circuiting interface between logic operators. We in silico analyzed gene circuits with inputs ranging from two to four, comparing our method with the pre-existing ones. Results showed that this formalized design process is more feasible concerning numbers of cells required. Furthermore, as a proof of principle, an Escherichia coli consortium that performs XOR function, a typical complex computing operation, was designed. The construction and characterization of logic operators is independent of "wiring" and provides predictive information for fine-tuning. This formalized design process provides guidance for the design of microbial consortia that perform distributed biological computation.
Research in computer simulation of integrated circuits
NASA Astrophysics Data System (ADS)
Newton, A. R.; Pdederson, D. O.
1983-07-01
The performance of the new LSI simulator CLASSIE is evaluated on several circuits with a few hundred to over one thousand semiconductor devices. A more accurate run time prediction formula has been found to be appropriate for circuit simulators. The design decisions for optimal performance under the constraints of the hardware (CRAY-1) are presented. Vector computers have an increased potential for fast, accurate simulation at the transistor level of Large-Scale-Integrated Circuits. Design considerations for a new circuit simulator are developed based on the specifics of the vector computer architecture and of LSI circuits. The simulation of Large-Scale-Integrated (LSI) circuits requires very long run time on conventional circuit analysis programs such as SPICE2 and super-mini computers. A new simulator for LSI circuits, CLASSIE, which takes advantage of circuit hierarchy and repetitiveness, and array processors capable of high-speed floating-point computation are a promising combination. While a large number of powerful design verfication tools have been developed for IC design at the transistor and logic gate levels, there are very few silicon-oriented tools for architectural design and evaluation.
Electronics. Module 3: Digital Logic Application. Instructor's Guide.
ERIC Educational Resources Information Center
Carter, Ed; Murphy, Mark
This guide contains instructor's materials for a 10-unit secondary school course on digital logic application. The units are introduction to digital, logic gates, digital integrated circuits, combination logic, flip-flops, counters and shift registers, encoders and decoders, arithmetic circuits, memory, and analog/digital and digital/analog…
Solid state remote circuit selector switch
NASA Technical Reports Server (NTRS)
Peterson, V. S.
1970-01-01
Remote switching circuit utilizes voltage logic to switch on desired circuit. Circuit controls rotating multi-range pressure transducers in jet engine testing and can be used in coded remote circuit activator where sequence of switching has to occur in defined length of time to prevent false or undesired circuit activation.
The universal magnetic tunnel junction logic gates representing 16 binary Boolean logic operations
NASA Astrophysics Data System (ADS)
Lee, Junwoo; Suh, Dong Ik; Park, Wanjun
2015-05-01
The novel devices are expected to shift the paradigm of a logic operation by their own nature, replacing the conventional devices. In this study, the nature of our fabricated magnetic tunnel junction (MTJ) that responds to the two external inputs, magnetic field and voltage bias, demonstrated seven basic logic operations. The seven operations were obtained by the electric-field-assisted switching characteristics, where the surface magnetoelectric effect occurs due to a sufficiently thin free layer. The MTJ was transformed as a universal logic gate combined with three supplementary circuits: A multiplexer (MUX), a Wheatstone bridge, and a comparator. With these circuits, the universal logic gates demonstrated 16 binary Boolean logic operations in one logic stage. A possible further approach is parallel computations through a complimentary of MUX and comparator, capable of driving multiple logic gates. A reconfigurable property can also be realized when different logic operations are produced from different level of voltages applying to the same configuration of the logic gate.
LOGIC DEVICES, *OPTICAL CIRCUITS, *OPTICAL SWITCHING, HETEROJUNCTIONS, PHOTOTRANSISTORS, ELECTROOPTICS, LASER CAVITIES, OPTICAL PROCESSING, PARALLEL PROCESSING, BISTABLE DEVICES, GATES(CIRCUITS), VOLTAGE, BINARY ARITHMETIC .
Turkdogan-Aydinol, F Ilter; Yetilmezsoy, Kaan
2010-10-15
A MIMO (multiple inputs and multiple outputs) fuzzy-logic-based model was developed to predict biogas and methane production rates in a pilot-scale 90-L mesophilic up-flow anaerobic sludge blanket (UASB) reactor treating molasses wastewater. Five input variables such as volumetric organic loading rate (OLR), volumetric total chemical oxygen demand (TCOD) removal rate (R(V)), influent alkalinity, influent pH and effluent pH were fuzzified by the use of an artificial intelligence-based approach. Trapezoidal membership functions with eight levels were conducted for the fuzzy subsets, and a Mamdani-type fuzzy inference system was used to implement a total of 134 rules in the IF-THEN format. The product (prod) and the centre of gravity (COG, centroid) methods were employed as the inference operator and defuzzification methods, respectively. Fuzzy-logic predicted results were compared with the outputs of two exponential non-linear regression models derived in this study. The UASB reactor showed a remarkable performance on the treatment of molasses wastewater, with an average TCOD removal efficiency of 93 (+/-3)% and an average volumetric TCOD removal rate of 6.87 (+/-3.93) kg TCOD(removed)/m(3)-day, respectively. Findings of this study clearly indicated that, compared to non-linear regression models, the proposed MIMO fuzzy-logic-based model produced smaller deviations and exhibited a superior predictive performance on forecasting of both biogas and methane production rates with satisfactory determination coefficients over 0.98.
Flexible programmable logic module
Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.
2001-01-01
The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.
NASA Astrophysics Data System (ADS)
Zhang, Chao; Santhanagopalan, Shriram; Sprague, Michael A.; Pesaran, Ahmad A.
2015-09-01
In order to better understand the behavior of lithium-ion batteries under mechanical abuse, a coupled modeling methodology encompassing the mechanical, electrical and thermal response is presented for predicting short-circuit under external crush. The combined mechanical-electrical-thermal response is simulated in a commercial finite element software LS-DYNA® using a representative-sandwich finite-element model, where electrical-thermal modeling is conducted after an instantaneous mechanical crush. The model includes an explicit representation of each individual component such as the active material, current collector, separator, etc., and predicts their mechanical deformation under quasi-static indentation. Model predictions show good agreement with experiments: the fracture of the battery structure under an indentation test is accurately predicted. The electrical-thermal simulation predicts the current density and temperature distribution in a reasonable manner. Whereas previously reported models consider the mechanical response exclusively, we use the electrical contact between active materials following the failure of the separator as a criterion for short-circuit. These results are used to build a lumped representative sandwich model that is computationally efficient and captures behavior at the cell level without resolving the individual layers.
Magnetic Circuit Model of PM Motor-Generator to Predict Radial Forces
NASA Technical Reports Server (NTRS)
McLallin, Kerry (Technical Monitor); Kascak, Peter E.; Dever, Timothy P.; Jansen, Ralph H.
2004-01-01
A magnetic circuit model is developed for a PM motor for flywheel applications. A sample motor is designed and modeled. Motor configuration and selection of materials is discussed, and the choice of winding configuration is described. A magnetic circuit model is described, which includes the stator back iron, rotor yoke, permanent magnets, air gaps and the stator teeth. Iterative solution of this model yields flux linkages, back EMF, torque, power, and radial force at the rotor caused by eccentricity. Calculated radial forces are then used to determine motor negative stiffness.
Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch.
Gao, Shuang; Zeng, Fei; Wang, Minjuan; Wang, Guangyue; Song, Cheng; Pan, Feng
2015-10-21
The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods-in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits-are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage.
Xavier, MA; Trimboli, MS
2015-07-01
This paper introduces a novel application of model predictive control (MPC) to cell-level charging of a lithium-ion battery utilizing an equivalent circuit model of battery dynamics. The approach employs a modified form of the MPC algorithm that caters for direct feed-though signals in order to model near-instantaneous battery ohmic resistance. The implementation utilizes a 2nd-order equivalent circuit discrete-time state-space model based on actual cell parameters; the control methodology is used to compute a fast charging profile that respects input, output, and state constraints. Results show that MPC is well-suited to the dynamics of the battery control problem and further suggest significant performance improvements might be achieved by extending the result to electrochemical models. (C) 2015 Elsevier B.V. All rights reserved.
ERIC Educational Resources Information Center
Chung, Gregory K. W. K.; Dionne, Gary B.; Kaiser, William J.
2006-01-01
Our research question was whether we could develop a feasible technique, using Bayesian networks, to diagnose gaps in student knowledge. Thirty-four college-age participants completed tasks designed to measure conceptual knowledge, procedural knowledge, and problem-solving skills related to circuit analysis. A Bayesian network was used to model…
NASA Technical Reports Server (NTRS)
Le Balleur, J. C.
1988-01-01
The applicability of conventional mathematical analysis (based on the combination of two-valued logic and probability theory) to problems in which human judgment, perception, or emotions play significant roles is considered theoretically. It is shown that dispositional logic, a branch of fuzzy logic, has particular relevance to the common-sense reasoning typical of human decision-making. The concepts of dispositionality and usuality are defined analytically, and a dispositional conjunctive rule and dispositional modus ponens are derived.
Lusk, E.L.; Overbeek, R.A.
1989-01-01
This book contains the proceedings of the 1989 North American Conference on Logic Programming. Included are the following papers: Expanding query power in constrain logic programming languages, Investigating the linguistics of DNA with definite clause grammars, An intermediate language to support prolog's unification.
A bit serial sequential circuit
NASA Technical Reports Server (NTRS)
Hu, S.; Whitaker, S.
1990-01-01
Normally a sequential circuit with n state variables consists of n unique hardware realizations, one for each state variable. All variables are processed in parallel. This paper introduces a new sequential circuit architecture that allows the state variables to be realized in a serial manner using only one next state logic circuit. The action of processing the state variables in a serial manner has never been addressed before. This paper presents a general design procedure for circuit construction and initialization. Utilizing pass transistors to form the combinational next state forming logic in synchronous sequential machines, a bit serial state machine can be realized with a single NMOS pass transistor network connected to shift registers. The bit serial state machine occupies less area than other realizations which perform parallel operations. Moreover, the logical circuit of the bit serial state machine can be modified by simply changing the circuit input matrix to develop an adaptive state machine.
All-optical symmetric ternary logic gate
NASA Astrophysics Data System (ADS)
Chattopadhyay, Tanay
2010-09-01
Symmetric ternary number (radix=3) has three logical states (1¯, 0, 1). It is very much useful in carry free arithmetical operation. Beside this, the logical operation using this type of number system is also effective in high speed computation and communication in multi-valued logic. In this literature all-optical circuits for three basic symmetrical ternary logical operations (inversion, MIN and MAX) are proposed and described. Numerical simulation verifies the theoretical model. In this present scheme the different ternary logical states are represented by different polarized state of light. Terahertz optical asymmetric demultiplexer (TOAD) based interferometric switch has been used categorically in this manuscript.
MinlanYuan; Meng, Yajing; Zhang, Yan; Nie, Xiaojing; Ren, Zhengjia; Zhu, Hongru; Li, Yuchen; Lui, Su; Gong, Qiyong; Qiu, Changjian; Zhang, Wei
2017-02-02
Some intrinsic connectivity networks including the default mode network (DMN) and executive control network (ECN) may underlie social anxiety disorder (SAD). Although the cerebellum has been implicated in the pathophysiology of SAD and several networks relevant to higher-order cognition, it remains unknown whether cerebellar areas involved in DMN and ECN exhibit altered resting-state functional connectivity (rsFC) with cortical networks in SAD. Forty-six patients with SAD and 64 healthy controls (HC) were included and submitted to the baseline resting-state functional magnetic resonance imaging (fMRI). Seventeen SAD patients who completed post-treatment clinical assessments were included after group cognitive behavior therapy (CBT). RsFC of three cerebellar subregions in both groups was assessed respectively in a voxel-wise way, and these rsFC maps were compared by two-sample t tests between groups. Whole-brain voxel-wise regression was performed to examine whether cerebellar connectivity networks can predict response to CBT. Lower rsFC circuits of cerebellar subregions compared with HC at baseline (p < 0.05, corrected by false discovery rate) were revealed. The left Crus I rsFC with dorsal medial prefrontal cortex was negatively correlated with symptom severity. The clinical assessments in SAD patients were significantly decreased after CBT. Higher pretreatment cerebellar rsFC with angular gyrus and dorsal lateral frontal cortex corresponded with greater symptom improvement following CBT. Cerebellar rsFC circuits involving DMN and ECN are possible neuropathologic mechanisms of SAD. Stronger pretreatment cerebellar rsFC circuits involving ECN suggest potential neural markers to predict CBT response.
Nonvolatile ``AND,'' ``OR,'' and ``NOT'' Boolean logic gates based on phase-change memory
NASA Astrophysics Data System (ADS)
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.
2013-12-01
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.
NASA Astrophysics Data System (ADS)
Yang, Xiankun; Chen, Haoyuan; Cheng, Linan; Zheng, Xitao
2011-11-01
The circuit model was applied to predict the pin load distribution of composite multiple bolt-joint structure. The load, flexibility and deformation of the mechanics model were equivalent to the current, resistance and voltage of the circuit model, respectively. Based on the above assumption, it could be found that the Hooke's law and the deformation compatibility equation in the origin mechanics model transformed into the Ohm's law and the voltage balance equation in the new circuit model. This approach translated the complex model of composite multiple bolt-jointed into a simple circuit model which consisted of some series circuits and parallel circuits. The analysis of the new circuit model had formed n-1 independence voltage balance equations and a current balance equation, thus, the current and load of each bolt could be calculated. In the new model, power sources which were added as required in some branch circuits could also simulate the clearance or interference in the origin model. Compared with the result of the multiple bolt-joints composite laminate test, the new approach could make an excellent performance to estimate the load distribution.
NASA Astrophysics Data System (ADS)
Yang, Xiankun; Chen, Haoyuan; Cheng, Linan; Zheng, Xitao
2012-04-01
The circuit model was applied to predict the pin load distribution of composite multiple bolt-joint structure. The load, flexibility and deformation of the mechanics model were equivalent to the current, resistance and voltage of the circuit model, respectively. Based on the above assumption, it could be found that the Hooke's law and the deformation compatibility equation in the origin mechanics model transformed into the Ohm's law and the voltage balance equation in the new circuit model. This approach translated the complex model of composite multiple bolt-jointed into a simple circuit model which consisted of some series circuits and parallel circuits. The analysis of the new circuit model had formed n-1 independence voltage balance equations and a current balance equation, thus, the current and load of each bolt could be calculated. In the new model, power sources which were added as required in some branch circuits could also simulate the clearance or interference in the origin model. Compared with the result of the multiple bolt-joints composite laminate test, the new approach could make an excellent performance to estimate the load distribution.
Zhang, Jialu; Wang, Chuan; Fu, Yue; Che, Yuchi; Zhou, Chongwu
2011-04-26
Due to extraordinary electrical properties, preseparated, high purity semiconducting carbon nanotubes hold great potential for thin-film transistors (TFTs) and integrated circuit applications. One of the main challenges it still faces is the fabrication of air-stable n-type nanotube TFTs with industry-compatible techniques. Here in this paper, we report a novel and highly reliable method of converting the as-made p-type TFTs using preseparated semiconducting nanotubes into air-stable n-type transistors by adding a high-κ oxide passivation layer using atomic layer deposition (ALD). The n-type devices exhibit symmetric electrical performance compared with the p-type devices in terms of on-current, on/off ratio, and device mobility. Various factors affecting the conversion process, including ALD temperature, metal contact material, and channel length, have also been systematically studied by a series of designed experiments. A complementary metal-oxide-semiconductor (CMOS) inverter with rail-to-rail output, symmetric input/output behavior, and large noise margin has been further demonstrated. The excellent performance gives us the feasibility of cascading multiple stages of logic blocks and larger scale integration. Our approach can serve as the critical foundation for future nanotube-based thin-film macroelectronics.
Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch
Gao, Shuang; Zeng, Fei; Wang, Minjuan; Wang, Guangyue; Song, Cheng; Pan, Feng
2015-01-01
The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods—in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits—are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage. PMID:26486231
Implementation of Complete Boolean Logic Functions in Single Complementary Resistive Switch
NASA Astrophysics Data System (ADS)
Gao, Shuang; Zeng, Fei; Wang, Minjuan; Wang, Guangyue; Song, Cheng; Pan, Feng
2015-10-01
The unique complementary switching behaviour of complementary resistive switches (CRSs) makes them very attractive for logic applications. The implementation of complete Boolean logic functions in a single CRS cell is certainly an extremely important step towards the commercialisation of related logic circuits, but it has not been accomplished to date. Here, we report two methods for the implementation of complete Boolean logic functions in a single CRS cell. The first method is based on the intrinsic switchable diode of a peculiar CRS cell that is composed of two anti-serial bipolar resistive switches with a rectifying high resistance state, while the second method is based directly on the complementary switching behaviour itself of any single CRS cell. The feasibilities of both methods have been theoretically predicted and then experimentally demonstrated on the basis of a Ta/Ta2O5/Pt/Ta2O5/Ta CRS cell. Therefore, these two methods—in particular the complementary switching behaviour itself-based method, which has natural immunity to the sneak-path issue of crossbar logic circuits—are believed to be capable of significantly advancing both our understanding and commercialization of related logic circuits. Moreover, peculiar CRS cells have been demonstrated to be feasible for tri-level storage, which can serve as an alternative method of realising ultra-high-density data storage.
Nanowire NMOS Logic Inverter Characterization.
Hashim, Yasir
2016-06-01
This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.
Adaptive parallel logic networks
NASA Technical Reports Server (NTRS)
Martinez, Tony R.; Vidal, Jacques J.
1988-01-01
Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.
Digital logic testing and testability
NASA Astrophysics Data System (ADS)
Debany, Warren H., Jr.
1991-02-01
Electronic hardware is subject to defects that are introduced at the time of manufacture and failures that occur in the field. Because of the complexity of digital logic circuits, they are difficult to test. This report provides an overview of digital logic testing. It provides access to the literature and unifies terminology and concepts that have evolved in this field. It discusses the types and causes of failures in digital logic. This report presents the topics of logic and fault simulation, fault grading, test generation algorithms, and fault isolation. The discussion of testability measurement is useful for understanding testability requirements and analysis techniques. Design-for-testability and built in test techniques are presented.
HDL to verification logic translator
NASA Technical Reports Server (NTRS)
Gambles, J. W.; Windley, P. J.
1992-01-01
The increasingly higher number of transistors possible in VLSI circuits compounds the difficulty in insuring correct designs. As the number of possible test cases required to exhaustively simulate a circuit design explodes, a better method is required to confirm the absence of design faults. Formal verification methods provide a way to prove, using logic, that a circuit structure correctly implements its specification. Before verification is accepted by VLSI design engineers, the stand alone verification tools that are in use in the research community must be integrated with the CAD tools used by the designers. One problem facing the acceptance of formal verification into circuit design methodology is that the structural circuit descriptions used by the designers are not appropriate for verification work and those required for verification lack some of the features needed for design. We offer a solution to this dilemma: an automatic translation from the designers' HDL models into definitions for the higher-ordered logic (HOL) verification system. The translated definitions become the low level basis of circuit verification which in turn increases the designer's confidence in the correctness of higher level behavioral models.
Sequential circuit design for radiation hardened multiple voltage integrated circuits
Clark, Lawrence T.; McIver, III, John K.
2009-11-24
The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.
Starter circuit for an ion engine
NASA Technical Reports Server (NTRS)
Cardwell, Jr., Gilbert I. (Inventor); Phelps, Thomas K. (Inventor)
2002-01-01
A starter circuit particularly suitable for a plasma of an ion engine for a spacecraft includes a power supply having an output inductor with a tap. A switch is coupled to the tap. The switch has a control input. A pulse control logic circuit is coupled to said control input, said pulse control logic circuit controlling said switch to an off state to generate a high voltage discharge.
Starter circuit for an ion engine
NASA Technical Reports Server (NTRS)
Cardwell, Jr., Gilbert I. (Inventor); Phelps, Thomas K. (Inventor)
2001-01-01
A starter circuit particularly suitable for a plasma of an ion engine for a spacecraft includes a power supply having an output inductor with a tap. A switch is coupled to the tap. The switch has a control input. A pulse control logic circuit is coupled to said control input, said pulse control logic circuit controlling said switch to an off state to generate a high voltage discharge.
NASA Technical Reports Server (NTRS)
Zadeh, Lofti A.
1988-01-01
The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.
Gentili, Pier Luigi; Gotoda, Hiroshi; Dolnik, Milos; Epstein, Irving R.
2015-01-15
Forecasting of aperiodic time series is a compelling challenge for science. In this work, we analyze aperiodic spectrophotometric data, proportional to the concentrations of two forms of a thermoreversible photochromic spiro-oxazine, that are generated when a cuvette containing a solution of the spiro-oxazine undergoes photoreaction and convection due to localized ultraviolet illumination. We construct the phase space for the system using Takens' theorem and we calculate the Lyapunov exponents and the correlation dimensions to ascertain the chaotic character of the time series. Finally, we predict the time series using three distinct methods: a feed-forward neural network, fuzzy logic, and a local nonlinear predictor. We compare the performances of these three methods.
ERIC Educational Resources Information Center
Lin, Jing-Wen
2016-01-01
Holding scientific conceptions and having the ability to accurately predict students' preconceptions are a prerequisite for science teachers to design appropriate constructivist-oriented learning experiences. This study explored the types and sources of students' preconceptions of electric circuits. First, 438 grade 3 (9 years old) students were…
Logic Programming in Digital Circuit Design
1991-12-01
facts. Computers using AI software can be useful in discovering design mistakes before they become a problem [46]. AFIT currently supports research ...and the objectives of this research along with an overall view of assumptions and methodologies are stated. Chapter 2 presents a brief history of...chapter, Chapter 7, discusses the strengths and weaknesses of the algorithms presented and makes recommendations for the direction of future research
Optical design of programmable logic arrays
NASA Astrophysics Data System (ADS)
Murdocca, Miles J.; Huang, Alan; Jahns, Jurgen; Streibl, Norbert
1988-05-01
Regular free-space interconnects such as the perfect shuffle and banyan provided by beam splitters, lenses, and mirrors connect optical logic gates arranged in two-dimensional arrays. An algorithmic design technique transforms arbitrary logic equations into a near-optimal depth circuit. Analysis shows that an arbitrary interconnect makes little or no improvement in circuit depth and can even reduce throughput. Gate count is normally higher with a regular interconnect, and cost bounds are shown. It is concluded that regularly interconnected circuits will have a higher gate count compared with arbitrarily interconnected circuits using the design techniques presented here and that regular free-space interconnects are comparable with arbitrary interconnects in terms of circuit depth and are preferred to arbitrary interconnects for maximizing throughput.
GMAG Dissertation Award Talk: All Spin Logic -- Multimagnet Networks interacting via Spin currents
NASA Astrophysics Data System (ADS)
Srinivasan, Srikant
2012-02-01
Digital logic circuits have traditionally been based on storing information as charge on capacitors, and the stored information is transferred by controlling the flow of charge. However, electrons carry both charge and spin, the latter being responsible for magnetic phenomena. In the last few decades, there has been a significant improvement in our ability to control spins and their interaction with magnets. All Spin Logic (ASL) represents a new approach to information processing where spins and magnets now mirror the roles of charges and capacitors in conventional logic circuits. In this talk I first present a model [1] that couples non-collinear spin transport with magnet-dynamics to predict the switching behavior of the basic ASL device. This model is based on established physics and is benchmarked against available experimental data that demonstrate spin-torque switching in lateral structures. Next, the model is extended to simulate multi-magnet networks coupled with spin transport channels. The simulations suggest ASL devices have the essential characteristics for building logic circuits. In particular, (1) the example of an ASL ring oscillator [2, 3] is used to provide a clear signature of directed information transfer in cascaded ASL devices without the need for external control circuitry and (2) a simulated NAND [4] gate with fan-out of 2 suggests that ASL can implement universal logic and drive subsequent stages. Finally I will discuss how ASL based circuits could also have potential use in the design of neuromorphic circuits suitable for hybrid analog/digital information processing because of the natural mapping of ASL devices to neurons [4]. [4pt] [1] B. Behin-Aein, A. Sarkar, S. Srinivasan, and S. Datta, ``Switching Energy-Delay of All-Spin Logic devices,'' Appl. Phys. Lett., 98, 123510 (2011).[0pt] [2] S. Srinivasan, A. Sarkar, B. Behin-Aein, and S. Datta, ``All Spin Logic Device with Inbuilt Non-reciprocity,'' IEEE Trans. Magn., 47, 10 (2011).[0pt] [3
Development of ferrite logic devices for an arithmetic processor
NASA Technical Reports Server (NTRS)
Heckler, C. H., Jr.
1972-01-01
A number of fundamentally ultra-reliable, all-magnetic logic circuits are developed using as a basis a single element ferrite structure wired as a logic delay element. By making minor additions or changes to the basic wiring pattern of the delay element other logic functions such as OR, AND, NEGATION, MAJORITY, EXCLUSIVE-OR, and FAN-OUT are developed. These logic functions are then used in the design of a full-adder, a set/reset flip-flop, and an edge detector. As a demonstration of the utility of all the developed devices, an 8-bit, all-magnetic, logic arithmetic unit capable of controlled addition, subtraction, and multiplication is designed. A new basic ferrite logic element and associated complementary logic scheme with the potential of improved performance is also described. Finally, an improved batch process for fabricating joint-free power drive and logic interconnect conductors for this basic class of all-magnetic logic is presented.
Kaushik, Aman Chandra; Sahi, Shakti
2015-06-01
Systems biology addresses challenges in the analysis of genomics data, especially for complex genes and protein interactions using Meta data approach on various signaling pathways. In this paper, we report systems biology and biological circuits approach to construct pathway and identify early gene and protein interactions for predicting GPR142 responses in Type 2 diabetes. The information regarding genes, proteins and other molecules involved in Type 2 diabetes were retrieved from literature and kinetic simulation of GPR142 was carried out in order to determine the dynamic interactions. The major objective of this work was to design a GPR142 biochemical pathway using both systems biology as well as biological circuits synthetically. The term 'synthetically' refers to building biological circuits for cell signaling pathway especially for hormonal pathway disease. The focus of the paper is on logical components and logical circuits whereby using these applications users can create complex virtual circuits. Logic gates process represents only true or false and investigates whether biological regulatory circuits are active or inactive. The basic gates used are AND, NAND, OR, XOR and NOT gates and Integrated circuit composition of many such basic gates and some derived gates. Biological circuits may have a futuristic application in biomedical sciences which may involve placing a micro chip in human cells to modulate the down or up regulation of hormonal disease.
Small circuits for cryptography.
Torgerson, Mark Dolan; Draelos, Timothy John; Schroeppel, Richard Crabtree; Miller, Russell D.; Anderson, William Erik
2005-10-01
This report examines a number of hardware circuit design issues associated with implementing certain functions in FPGA and ASIC technologies. Here we show circuit designs for AES and SHA-1 that have an extremely small hardware footprint, yet show reasonably good performance characteristics as compared to the state of the art designs found in the literature. Our AES performance numbers are fueled by an optimized composite field S-box design for the Stratix chipset. Our SHA-1 designs use register packing and feedback functionalities of the Stratix LE, which reduce the logic element usage by as much as 72% as compared to other SHA-1 designs.
Bilayer avalanche spin-diode logic
Friedman, Joseph S. Querlioz, Damien; Fadel, Eric R.; Wessels, Bruce W.; Sahakian, Alan V.
2015-11-15
A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.
CMAT non-volatile spintronic computing: complementary MTJ logic
NASA Astrophysics Data System (ADS)
Friedman, Joseph S.
2016-10-01
Magnetic tunnel junctions (MTJs) have thoroughly demonstrated their utility as a non-volatile memory storage element, inspiring their application to a memory-in-logic computer that would overcome the von Neumann bottleneck. However, MTJ logic gates must be able to cause other MTJs to switch, thus ensuring the cascading capability fundamental to efficient computing. Complementary MTJ logic (CMAT) provides a simple circuit structure through which MTJs can be cascaded directly to perform logic operations. In this novel logic family, charge pulses resulting from MTJ switching create magnetic fields that switch other MTJs, providing impetus for further development of MTJs for computing applications.
NASA Astrophysics Data System (ADS)
Polasek, P.; Halamik, J.
1984-05-01
The term semicustom designed integrated circuits denotes integrated circuits of an all purpose character in which the production of chips is completed by using one to three custom design stencil type exposure masks. This involves in most cases interconnecting masks that are used to devise the circuit function desired by the customer. Silicon plates with an all purpose gate matrix are produced up to the interconnection level and can be kept at this phase in storage, after which a customer's specific demands can be met very expediently. All purpose logic fields containing 200 logic gates on a chip and an all purpose chip to be expanded to 1,000 logic gates are discussed. The technology facilitates the devising of fast gates with a delay of approximately 5 ns and power dissipation of 1 mW. In assembly it will be possible to make use of the entire assortment of the currently used casings with 16, 18, 20, 24, 28 and 40 outlets. In addition to the development of the mentioned technology, a general methodology for design of the mentioned gate fields is currently under way.
Simple digital pulse-programing circuit
NASA Technical Reports Server (NTRS)
Langston, J. L.
1979-01-01
Pulse-sequencing circuit uses only shift register and Exclusive-OR gates. Circuit also serves as date-transition edge detector (for rising or falling edges). It is used in sample-and-hold, analog-to-digital conversion sequence control, multiphase clock logic, precise delay control computer control logic, edge detectors, other timing applications, and provides simple means to generate timing and control signals for data transfer, addressing, or mode control in microprocessors and minicomputers.
Cooper, James A.
1986-01-01
A logic circuit is used to enhance redundant switch reliability. Two or more switches are monitored for logical high or low output. The output for the logic circuit produces a redundant and failsafe representation of the switch outputs. When both switch outputs are high, the output is high. Similarly, when both switch outputs are low, the logic circuit's output is low. When the output states of the two switches do not agree, the circuit resolves the conflict by memorizing the last output state which both switches were simultaneously in and produces the logical complement of this output state. Thus, the logic circuit of the present invention allows the redundant switches to be treated as if they were in parallel when the switches are open and as if they were in series when the switches are closed. A failsafe system having maximum reliability is thereby produced.
Sun, Shan C.; Chaprnka, Anthony G.
1977-01-11
An automatic gain control circuit functions to adjust the magnitude of an input signal supplied to a measuring circuit to a level within the dynamic range of the measuring circuit while a log-ratio circuit adjusts the magnitude of the output signal from the measuring circuit to the level of the input signal and optimizes the signal-to-noise ratio performance of the measuring circuit.
Development of automated test procedures and techniques for LSI circuits
NASA Technical Reports Server (NTRS)
Carroll, B. D.
1975-01-01
Testing of large scale integrated (LSI) logic circuits was considered from the point of view of automatic test pattern generation. A system for automatic test pattern generation is described. A test generation algorithm is presented that can be applied to both combinational and sequential logic circuits. Also included is a programmed implementation of the algorithm and sample results from the program.
Interface Circuits for Self-Checking Microprocessors
NASA Technical Reports Server (NTRS)
Rennels, D. A.; Chandramouli, R.
1986-01-01
Fault-tolerant-microcomputer concept based on enhancing "simple" computer with redundancy and self-checking logic circuits detect hardware faults. Interface and checking logic and redundant processors confer on 16-bit microcomputer ability to check itself for hardware faults. Checking circuitry also checks itself. Concept of self-checking complementary pairs (SCCP's) employed throughout ICL unit.
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.
2013-12-21
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.
NASA Astrophysics Data System (ADS)
Matrosova, A. Yu.; Kirienko, I. E.; Tomkov, V. V.; Miryutov, A. A.
2016-12-01
Reliability of physical systems is provided by reliability of their parts including logical ones. Insertion of malicious subcircuits that can destroy logical circuit or cause leakage of confidential information from a system necessitates the detection of such subcircuits followed by their masking if possible. We suggest a method of finding a set of sequential circuit nodes in which Trojan Circuits can be inserted. The method is based on random estimations of controllability and observability of combinational nodes calculated using a description of sequential circuit working area and an evidence of existence of a transfer sequence for the proper set of internal states without finding the sequence itself. The method allows cutting calculations using operations on Reduced Ordered Binary Decision Diagrams (ROBDDs) that can depend only on the state variables of the circuit. The approach, unlike traditional ones, does not require preliminary sequential circuit simulation but can use its results. It can be used when malicious circuits cannot be detected during sequential circuit verification.
Development of CMOS integrated circuits
NASA Technical Reports Server (NTRS)
Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.
1979-01-01
Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.
Man-machine interactive system simplifies computer-aided circuit design
NASA Technical Reports Server (NTRS)
Bavuso, S. J.
1970-01-01
Langley interactive computerized circuit analysis capability /LICCA/ enables designer to draw electronic circuit diagrams on cathode ray tube screen. This information is submitted as input to user-selected circuit analysis program. LICCA accommodates binary logic circuits and circuits with discrete components, and monitors operator's instructions to detect errors.
Noise-based logic: Binary, multi-valued, or fuzzy, with optional superposition of logic states
NASA Astrophysics Data System (ADS)
Kish, Laszlo B.
2009-03-01
A new type of deterministic (non-probabilistic) computer logic system inspired by the stochasticity of brain signals is shown. The distinct values are represented by independent stochastic processes: independent voltage (or current) noises. The orthogonality of these processes provides a natural way to construct binary or multi-valued logic circuitry with arbitrary number N of logic values by using analog circuitry. Moreover, the logic values on a single wire can be made a (weighted) superposition of the N distinct logic values. Fuzzy logic is also naturally represented by a two-component superposition within the binary case ( N=2). Error propagation and accumulation are suppressed. Other relevant advantages are reduced energy dissipation and leakage current problems, and robustness against circuit noise and background noises such as 1/f, Johnson, shot and crosstalk noise. Variability problems are also non-existent because the logic value is an AC signal. A similar logic system can be built with orthogonal sinusoidal signals (different frequency or orthogonal phase) however that has an extra 1/N type slowdown compared to the noise-based logic system with increasing number of N furthermore it is less robust against time delay effects than the noise-based counterpart.
Multi-input regulation and logic with T7 promoters in cells and cell free systems
Iyer, Sukanya; Karig, David K; Norred, Sarah E; Simpson, Michael L; Doktycz, Mitchel John
2014-01-01
Engineered gene circuits offer an opportunity to harness biological systems for biotechnological and biomedical applications. However, reliance on host E. coli promoters for the construction of circuit elements, such as logic gates, makes implementation of predictable, independently functioning circuits difficult. In contrast, T7 promoters offer a simple orthogonal expression system for use in a variety of cellular backgrounds and even in cell free systems. Here we develop a T7 promoter system that can be regulated by two different transcriptional repressors for the construction of a logic gate that functions in cells and in cell free systems. We first present LacI repressible T7lacO promoters that are regulated from a distal lac operator site for repression. We next explore the positioning of a tet operator site within the T7lacO framework to create T7 promoters that respond to tet and lac repressors and realize an IMPLIES gate. Finally, we demonstrate that these dual input sensitive promoters function in a commercially available E. coli cell-free protein expression system. Together, our results contribute to the first demonstration of multi-input regulation of T7 promoters and expand the utility of T7 promoters in cell based as well as cell-free gene circuits.
Implementing neural nets with programmable logic
NASA Technical Reports Server (NTRS)
Vidal, Jacques J.
1988-01-01
Networks of Boolean programmable logic modules are presented as one purely digital class of artificial neural nets. The approach contrasts with the continuous analog framework usually suggested. Programmable logic networks are capable of handling many neural-net applications. They avoid some of the limitations of threshold logic networks and present distinct opportunities. The network nodes are called dynamically programmable logic modules. They can be implemented with digitally controlled demultiplexers. Each node performs a Boolean function of its inputs which can be dynamically assigned. The overall network is therefore a combinational circuit and its outputs are Boolean global functions of the network's input variables. The approach offers definite advantages for VLSI implementation, namely, a regular architecture with limited connectivity, simplicity of the control machinery, natural modularity, and the support of a mature technology.
Introduction to lethal circuit transformations
NASA Astrophysics Data System (ADS)
Fišer, Petr; Schmidt, Jan
2015-12-01
Logic optimization is a process that takes a logic circuit description (Boolean network) as an input and tries to refine it, to reduce its size and/or depth. An ideal optimization process should be able to devise an optimum implementation of a network in a reasonable time, given any circuit structure at the input. However, there are cases where it completely fails to produce even near-optimum solutions. Such cases are typically induced by non-standard circuit structure modifications. Surprisingly enough, such deviated structures are frequently present in standard benchmark sets too. We may only wonder whether it is an intention of the benchmarks creators, or just an unlucky coincidence. Even though synthesis tools should be primarily well suited for practical circuits, there is no guarantee that, e.g., a higher-level synthesis process will not generate such unlucky structures. Here we present examples of circuit transformations that lead to failure of most of state-of-the-art logic synthesis and optimization processes, both academic and commercial, and suggest actions to mitigate the disturbing effects.
Integrated-Circuit Pseudorandom-Number Generator
NASA Technical Reports Server (NTRS)
Steelman, James E.; Beasley, Jeff; Aragon, Michael; Ramirez, Francisco; Summers, Kenneth L.; Knoebel, Arthur
1992-01-01
Integrated circuit produces 8-bit pseudorandom numbers from specified probability distribution, at rate of 10 MHz. Use of Boolean logic, circuit implements pseudorandom-number-generating algorithm. Circuit includes eight 12-bit pseudorandom-number generators, outputs are uniformly distributed. 8-bit pseudorandom numbers satisfying specified nonuniform probability distribution are generated by processing uniformly distributed outputs of eight 12-bit pseudorandom-number generators through "pipeline" of D flip-flops, comparators, and memories implementing conditional probabilities on zeros and ones.
Divide and control: split design of multi-input DNA logic gates†
Gerasimova, Yulia V.
2015-01-01
Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct. PMID:25513764
NASA Technical Reports Server (NTRS)
1973-01-01
Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be noted that the logic theory contained herein applies to all hardware. Discussed here are synchronous binary UP counters, synchronous DOWN and UP/DOWN counters, integrated circuit counters, shift registers, sequential techniques, and designing sequential counting machines.
Genetic Dissection of Neural Circuits
Luo, Liqun; Callaway, Edward M.; Svoboda, Karel
2009-01-01
Understanding the principles of information processing in neural circuits requires systematic characterization of the participating cell types and their connections, and the ability to measure and perturb their activity. Genetic approaches promise to bring experimental access to complex neural systems, including genetic stalwarts such as the fly and mouse, but also to nongenetic systems such as primates. Together with anatomical and physiological methods, cell-type-specific expression of protein markers and sensors and transducers will be critical to construct circuit diagrams and to measure the activity of genetically defined neurons. Inactivation and activation of genetically defined cell types will establish causal relationships between activity in specific groups of neurons, circuit function, and animal behavior. Genetic analysis thus promises to reveal the logic of the neural circuits in complex brains that guide behaviors. Here we review progress in the genetic analysis of neural circuits and discuss directions for future research and development. PMID:18341986
CMOS Interface Circuits for Spin Tunneling Junction Based Magnetic Random Access Memories
Saripalli, Ganesh
2002-01-01
Magneto resistive memories (MRAM) are non-volatile memories which use magnetic instead of electrical structures to store data. These memories, apart from being non-volatile, offer a possibility to achieve densities better than DRAMs and speeds faster than SRAMs. MRAMs could potentially replace all computer memory RAM technologies in use today, leading to future applications like instan-on computers and longer battery life for pervasive devices. Such rapid development was made possible due to the recent discovery of large magnetoresistance in Spin tunneling junction devices. Spin tunneling junctions (STJ) are composite structures consisting of a thin insulating layer sandwiched between two magnetic layers. This thesis research is targeted towards these spin tunneling junction based Magnetic memories. In any memory, some kind of an interface circuit is needed to read the logic states. In this thesis, four such circuits are proposed and designed for Magnetic memories (MRAM). These circuits interface to the Spin tunneling junctions and act as sense amplifiers to read their magnetic states. The physical structure and functional characteristics of these circuits are discussed in this thesis. Mismatch effects on the circuits and proper design techniques are also presented. To demonstrate the functionality of these interface structures, test circuits were designed and fabricated in TSMC 0.35μ CMOS process. Also circuits to characterize the process mismatches were fabricated and tested. These results were then used in Matlab programs to aid in design process and to predict interface circuit's yields.
NASA Astrophysics Data System (ADS)
Feng, Tianheng; Yang, Lin; Zhao, Xiaowei; Zhang, Huidong; Qiang, Jiaxi
2015-05-01
In battery management system (BMS), equivalent-circuit model (ECM) is commonly used to simulate battery dynamics. However, there always is a contradiction between model simplicity and accuracy. A simple model is usually unable to reflect all the dynamic effects of the battery, which may bring errors to parameter identification. A complex model, however, always has too many parameters to be identified and may have parameter divergence problem. This paper tries to solve this problem with a novel ECM by adding a moving average (MA) noise to the one resistor-capacity (RC) circuit model. It can accurately capture the battery dynamics and retain a simple topology. A recursive extended least squares (RELS) algorithm is applied to online identify the ECM parameters, which shows a high accuracy in the experiments. In addition, a battery state-of-power (SOP) prediction algorithm is derived based on the proposed ECM. It considers both the voltage and current limitations of the battery, and offers a two-level prediction of the battery peak power capabilities.
Pattern recognition using linguistic fuzzy logic predictors
NASA Astrophysics Data System (ADS)
Habiballa, Hashim
2016-06-01
The problem of pattern recognition has been solved with numerous methods in the Artificial Intelligence field. We present an unconventional method based on Lingustic Fuzzy Logic Forecaster which is primarily used for the task of time series analysis and prediction through logical deduction wtih linguistic variables. This method should be used not only to the time series prediction itself, but also for recognition of patterns in a signal with seasonal component.
Fuzzy logic controller optimization
Sepe, Jr., Raymond B; Miller, John Michael
2004-03-23
A method is provided for optimizing a rotating induction machine system fuzzy logic controller. The fuzzy logic controller has at least one input and at least one output. Each input accepts a machine system operating parameter. Each output produces at least one machine system control parameter. The fuzzy logic controller generates each output based on at least one input and on fuzzy logic decision parameters. Optimization begins by obtaining a set of data relating each control parameter to at least one operating parameter for each machine operating region. A model is constructed for each machine operating region based on the machine operating region data obtained. The fuzzy logic controller is simulated with at least one created model in a feedback loop from a fuzzy logic output to a fuzzy logic input. Fuzzy logic decision parameters are optimized based on the simulation.
Jacobsohn, D.H.; Merrill, L.C.
1959-01-20
An improved parallel addition unit is described which is especially adapted for use in electronic digital computers and characterized by propagation of the carry signal through each of a plurality of denominationally ordered stages within a minimum time interval. In its broadest aspects, the invention incorporates a fast multistage parallel digital adder including a plurality of adder circuits, carry-propagation circuit means in all but the most significant digit stage, means for conditioning each carry-propagation circuit during the time period in which information is placed into the adder circuits, and means coupling carry-generation portions of thc adder circuit to the carry propagating means.
Universal programmable logic gate and routing method
NASA Technical Reports Server (NTRS)
Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)
2009-01-01
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Chaos in Electronic Circuits: Nonlinear Time Series Analysis
Wheat, Jr., Robert M.
2003-07-01
Chaos in electronic circuits is a phenomenon that has been largely ignored by engineers, manufacturers, and researchers until the early 1990’s and the work of Chua, Matsumoto, and others. As the world becomes more dependent on electronic devices, the detrimental effects of non-normal operation of these devices becomes more significant. Developing a better understanding of the mechanisms involved in the chaotic behavior of electronic circuits is a logical step toward the prediction and prevention of any potentially catastrophic occurrence of this phenomenon. Also, a better understanding of chaotic behavior, in a general sense, could potentially lead to better accuracy in the prediction of natural events such as weather, volcanic activity, and earthquakes. As a first step in this improvement of understanding, and as part of the research being reported here, methods of computer modeling, identifying and analyzing, and producing chaotic behavior in simple electronic circuits have been developed. The computer models were developed using both the Alternative Transient Program (ATP) and Spice, the analysis techniques have been implemented using the C and C++ programming languages, and the chaotically behaving circuits developed using “off the shelf” electronic components.
A circuit design for multi-inputs stateful OR gate
NASA Astrophysics Data System (ADS)
Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-09-01
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
Design of a Ferroelectric Programmable Logic Gate Array
NASA Technical Reports Server (NTRS)
MacLeod, Todd C.; Ho, Fat Duen
2003-01-01
A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.
High-speed dynamic domino circuit implemented with gaas mesfets
NASA Technical Reports Server (NTRS)
Yang, Long (Inventor); Long, Stephen I. (Inventor)
1990-01-01
A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.
NASA Astrophysics Data System (ADS)
Foster, J. M.; Kirkpatrick, J.; Richardson, G.
2013-09-01
In this study, a drift-diffusion model is used to derive the current-voltage curves of an organic bilayer solar cell consisting of slabs of electron acceptor and electron donor materials sandwiched together between current collectors. A simplified version of the standard drift-diffusion equations is employed in which minority carrier densities are neglected. This is justified by the large disparities in electron affinity and ionisation potential between the two materials. The resulting equations are solved (via both asymptotic and numerical techniques) in conjunction with (i) Ohmic boundary conditions on the contacts and (ii) an internal boundary condition, imposed on the interface between the two materials, that accounts for charge pair generation (resulting from the dissociation of excitons) and charge pair recombination. Current-voltage curves are calculated from the solution to this model as a function of the strength of the solar charge generation. In the physically relevant power generating regime, it is shown that these current-voltage curves are well-approximated by a Shockley equivalent circuit model. Furthermore, since our drift-diffusion model is predictive, it can be used to directly calculate equivalent circuit parameters from the material parameters of the device.
Reversible logic for supercomputing.
DeBenedictis, Erik P.
2005-05-01
This paper is about making reversible logic a reality for supercomputing. Reversible logic offers a way to exceed certain basic limits on the performance of computers, yet a powerful case will have to be made to justify its substantial development expense. This paper explores the limits of current, irreversible logic for supercomputers, thus forming a threshold above which reversible logic is the only solution. Problems above this threshold are discussed, with the science and mitigation of global warming being discussed in detail. To further develop the idea of using reversible logic in supercomputing, a design for a 1 Zettaflops supercomputer as required for addressing global climate warming is presented. However, to create such a design requires deviations from the mainstream of both the software for climate simulation and research directions of reversible logic. These deviations provide direction on how to make reversible logic practical.
Scaling up digital circuit computation with DNA strand displacement cascades.
Qian, Lulu; Winfree, Erik
2011-06-03
To construct sophisticated biochemical circuits from scratch, one needs to understand how simple the building blocks can be and how robustly such circuits can scale up. Using a simple DNA reaction mechanism based on a reversible strand displacement process, we experimentally demonstrated several digital logic circuits, culminating in a four-bit square-root circuit that comprises 130 DNA strands. These multilayer circuits include thresholding and catalysis within every logical operation to perform digital signal restoration, which enables fast and reliable function in large circuits with roughly constant switching time and linear signal propagation delays. The design naturally incorporates other crucial elements for large-scale circuitry, such as general debugging tools, parallel circuit preparation, and an abstraction hierarchy supported by an automated circuit compiler.
A novel, efficient CNTFET Galois design as a basic ternary-valued logic field.
Keshavarzian, Peiman; Mirzaee, Mahla Mohammad
2012-01-01
This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs). Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued) logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption.
A novel, efficient CNTFET Galois design as a basic ternary-valued logic field
Keshavarzian, Peiman; Mirzaee, Mahla Mohammad
2012-01-01
This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs). Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued) logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption. PMID:24198492
Auto-programmable impulse neural circuits
NASA Technical Reports Server (NTRS)
Watula, D.; Meador, J.
1990-01-01
Impulse neural networks use pulse trains to communicate neuron activation levels. Impulse neural circuits emulate natural neurons at a more detailed level than that typically employed by contemporary neural network implementation methods. An impulse neural circuit which realizes short term memory dynamics is presented. The operation of that circuit is then characterized in terms of pulse frequency modulated signals. Both fixed and programmable synapse circuits for realizing long term memory are also described. The implementation of a simple and useful unsupervised learning law is then presented. The implementation of a differential Hebbian learning rule for a specific mean-frequency signal interpretation is shown to have a straightforward implementation using digital combinational logic with a variation of a previously developed programmable synapse circuit. This circuit is expected to be exploited for simple and straightforward implementation of future auto-adaptive neural circuits.
Digital circuits for computer applications: A compilation
NASA Technical Reports Server (NTRS)
1972-01-01
The innovations in this updated series of compilations dealing with electronic technology represent a carefully selected collection of digital circuits which have direct application in computer oriented systems. In general, the circuits have been selected as representative items of each section and have been included on their merits of having universal applications in digital computers and digital data processing systems. As such, they should have wide appeal to the professional engineer and scientist who encounter the fundamentals of digital techniques in their daily activities. The circuits are grouped as digital logic circuits, analog to digital converters, and counters and shift registers.
Logic gates based on ion transistors.
Tybrandt, Klas; Forchheimer, Robert; Berggren, Magnus
2012-05-29
Precise control over processing, transport and delivery of ionic and molecular signals is of great importance in numerous fields of life sciences. Integrated circuits based on ion transistors would be one approach to route and dispense complex chemical signal patterns to achieve such control. To date several types of ion transistors have been reported; however, only individual devices have so far been presented and most of them are not functional at physiological salt concentrations. Here we report integrated chemical logic gates based on ion bipolar junction transistors. Inverters and NAND gates of both npn type and complementary type are demonstrated. We find that complementary ion gates have higher gain and lower power consumption, as compared with the single transistor-type gates, which imitates the advantages of complementary logics found in conventional electronics. Ion inverters and NAND gates lay the groundwork for further development of solid-state chemical delivery circuits.
Solinas, Sergio; Nieus, Thierry; D'Angelo, Egidio
2010-01-01
The way the cerebellar granular layer transforms incoming mossy fiber signals into new spike patterns to be related to Purkinje cells is not yet clear. Here, a realistic computational model of the granular layer was developed and used to address four main functional hypotheses: center-surround organization, time-windowing, high-pass filtering in responses to spike bursts and coherent oscillations in response to diffuse random activity. The model network was activated using patterns inspired by those recorded in vivo. Burst stimulation of a small mossy fiber bundle resulted in granule cell bursts delimited in time (time windowing) and space (center-surround) by network inhibition. This burst-burst transmission showed marked frequency-dependence configuring a high-pass filter with cut-off frequency around 100 Hz. The contrast between center and surround properties was regulated by the excitatory-inhibitory balance. The stronger excitation made the center more responsive to 10-50 Hz input frequencies and enhanced the granule cell output (with spikes occurring earlier and with higher frequency and number) compared to the surround. Finally, over a certain level of mossy fiber background activity, the circuit generated coherent oscillations in the theta-frequency band. All these processes were fine-tuned by NMDA and GABA-A receptor activation and neurotransmitter vesicle cycling in the cerebellar glomeruli. This model shows that available knowledge on cellular mechanisms is sufficient to unify the main functional hypotheses on the cerebellum granular layer and suggests that this network can behave as an adaptable spatio-temporal filter coordinated by theta-frequency oscillations.
Logic Design Pathology and Space Flight Electronics
NASA Technical Reports Server (NTRS)
Katz, Richard; Barto, Rod L.; Erickson, K.
1997-01-01
Logic design errors have been observed in space flight missions and the final stages of ground test. The technologies used by designers and their design/analysis methodologies will be analyzed. This will give insight to the root causes of the failures. These technologies include discrete integrated circuit based systems, systems based on field and mask programmable logic, and the use computer aided engineering (CAE) systems. State-of-the-art (SOTA) design tools and methodologies will be analyzed with respect to high-reliability spacecraft design and potential pitfalls are discussed. Case studies of faults from large expensive programs to "smaller, faster, cheaper" missions will be used to explore the fundamental reasons for logic design problems.
Plastic Logic quits e-reader market
NASA Astrophysics Data System (ADS)
Perks, Simon
2012-07-01
A UK firm spun out from the University of Cambridge that sought to be a world leader in flexible organic electronic circuits and displays has pulled out of the competitive e-reader market as it struggles to find a commercial outlet for its technology. Plastic Logic announced in May that it is to close its development facility in Mountain View, California, with the loss of around 40 jobs.
"Glitch Logic" and Applications to Computing and Information Security
NASA Technical Reports Server (NTRS)
Stoica, Adrian; Katkoori, Srinivas
2009-01-01
This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.
Reliability concerns with logical constants in Xilinx FPGA designs
Quinn, Heather M; Graham, Paul; Morgan, Keith; Ostler, Patrick; Allen, Greg; Swift, Gary; Tseng, Chen W
2009-01-01
In Xilinx Field Programmable Gate Arrays logical constants, which ground unused inputs and provide constants for designs, are implemented in SEU-susceptible logic. In the past, these logical constants have been shown to cause the user circuit to output bad data and were not resetable through off-line rcconfiguration. In the more recent devices, logical constants are less problematic, though mitigation should still be considered for high reliability applications. In conclusion, we have presented a number of reliability concerns with logical constants in the Xilinx Virtex family. There are two main categories of logical constants: implicit and explicit logical constants. In all of the Virtex devices, the implicit logical constants are implemented using half latches, which in the most recent devices are several orders of magnitudes smaller than configuration bit cells. Explicit logical constants are implemented exclusively using constant LUTs in the Virtex-I and Virtex-II, and use a combination of constant LUTs and architectural posts to the ground plane in the Virtex-4. We have also presented mitigation methods and options for these devices. While SEUs in implicit and some types of explicit logical constants can cause data corrupt, the chance of failure from these components is now much smaller than it was in the Virtex-I device. Therefore, for many cases, mitigation might not be necessary, except under extremely high reliability situations.
Palladio: An Exploratory Environment for Circuit Design
1983-06-01
been Qpproved Spublic =.jo 3 0o’s; its ditni’buto i-.i•,• --’ 93-15882 THIS DOCUMENT IS BEST QUALITY AVAILABLE. THE COPY FURNISHED TO DTIC CONTAINED...behavior, functional performance, design quality (e.g., testability, understandability, robustness), and physical realizability. Circuit verification...format can accommodate behavior that transcends traditional logic modes for digital design. For example, the rule syntax permits Boolean logic control to
Automated ILA design for synchronous sequential circuits
NASA Technical Reports Server (NTRS)
Liu, M. N.; Liu, K. Z.; Maki, G. K.; Whitaker, S. R.
1991-01-01
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.
Resnik, Jennifer; Polley, Daniel B
2017-03-21
Cortical neurons remap their receptive fields and rescale sensitivity to spared peripheral inputs following sensory nerve damage. To address how these plasticity processes are coordinated over the course of functional recovery, we tracked receptive field reorganization, spontaneous activity, and response gain from individual principal neurons in the adult mouse auditory cortex over a 50-day period surrounding either moderate or massive auditory nerve damage. We related the day-by-day recovery of sound processing to dynamic changes in the strength of intracortical inhibition from parvalbumin-expressing (PV) inhibitory neurons. Whereas the status of brainstem-evoked potentials did not predict the recovery of sensory responses to surviving nerve fibers, homeostatic adjustments in PV-mediated inhibition during the first days following injury could predict the eventual recovery of cortical sound processing weeks later. These findings underscore the potential importance of self-regulated inhibitory dynamics for the restoration of sensory processing in excitatory neurons following peripheral nerve injuries.
High level modelling and design of asynchronous interface logic
NASA Astrophysics Data System (ADS)
Yakovlev, A. V.; Koelmans, A. M.; Lavagno, L.
1993-11-01
The authors propose a new methodology to design asynchronous circuits that is divided in two stages: abstract synthesis and logic synthesis. The first state is carried out by refining an abstract model, based on logic predicates describing the correct input-output behavior of the circuit, into a labelled Petri net and then into a formalization of timing diagrams (the Signal Transition Graph). This refinement involves hierarchical decomposition of the initial implementation until its size can be handled by automated logic synthesis tools, as well as replacing symbolic events occurring on the input-output ports of the labelled Petri net with up and down transitions occurring on the input-output wires of a circuit implementation.
Closed circuit TV system automatically guides welding arc
NASA Technical Reports Server (NTRS)
Stephans, D. L.; Wall, W. A., Jr.
1968-01-01
Closed circuit television /CCTV/ system automatically guides a welding torch to position the welding arc accurately along weld seams. Digital counting and logic techniques incorporated in the control circuitry, ensure performance reliability.
NASA Astrophysics Data System (ADS)
Saleh, F.; Flipo, N.; de Fouquet, C.
2012-04-01
The main objective of this study is to provide a realistic simulation of river stage in regional river networks in order to improve the quantification of stream-aquifer exchanges and better assess the associated aquifer responses that are often impacted by the magnitude and the frequency of the river stage fluctuations. The study focuses on the Oise basin (17 000 km2, part of the 65 000 km2 Seine basin in Northern France) where stream-aquifer exchanges cannot be assessed directly by experimental methods. Nowadays numerical methods are the most appropriate approaches for assessing stream-aquifer exchanges at this scale. A regional distributed process-based hydro(geo)logical model, Eau-Dyssée, is used, which aims at the integrated modeling of the hydrosystem to manage the various elements involved in the quantitative and qualitative aspects of water resources. Eau-Dyssée simulates pseudo 3D flow in aquifer systems solving the diffusivity equation with a finite difference numerical scheme. River flow is simulated with a Muskingum model. In addition to the in-stream discharge, a river stage estimate is needed to calculate the water exchange at the stream-aquifer interface using the Darcy law. Three methods for assessing in-stream river stages are explored to determine the most appropriate representation at regional scale over 25 years (1980-2005). The first method consists in defining rating curves for each cell of a 1D Saint-Venant hydraulic model. The second method consists in interpolating observed rating curves (at gauging stations) onto the river cells of the hydro(geo)logical model. The interpolation technique is based on geostatistics. The last method assesses river stage using Manning equation with a simplified rectangular cross-section (water depth equals the hydraulic radius). Compared to observations, the geostatistical and the Manning methodologies lead to slightly less accurate (but still acceptable) results offering a low computational cost opportunity
NASA Technical Reports Server (NTRS)
Du Fresne, E. R.; Dowler, W. L.
1985-01-01
Logic gates for light signals constructed from combinations of prisms, polarizing plates, and quarterwave plates. Optical logic gate performs elementary logic operation on light signals received along two optical fibers. Whether gate performs OR function or exclusive-OR function depends on orientation of analyzer. Nonbinary truth tables also obtained by rotating polarizer or analyzer to other positions or inserting other quarter-wave plates.
NASA Technical Reports Server (NTRS)
Preston, K., Jr.
1972-01-01
The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.
NASA Astrophysics Data System (ADS)
Zucca, R. R.; Kirkpatrick, C. G.; Asbeck, P. M.; Eisen, F. H.; Lee, C. P.
1984-01-01
This report summarizes the research carried out at North Carolina State University in support of the Rockwell International Program on LSI-VLSI Ion Implanted Planar GaAs IC Processing. The major thrust of the program at NCSU was to develop accurate computer models for analyzing the performance of short-channel GaAs MESFET devices as used in the Rockwell VLSI circuits. The modeling research is divided into three parts: (1) Two-dimensional finite difference simulation, (2) Two-dimensional Monte Carlo analysis, and (3) Analytical modeling. The intent was to use the two-dimensional analyses to give exact solutions to the device operation and to serve as a guide for developing a simpler, and less expensive, analytical model of sufficient accuracy to be valuable as a design aid and to study effects of parameter changes.
NASA Technical Reports Server (NTRS)
Howard, Ayanna
2005-01-01
The Fuzzy Logic Engine is a software package that enables users to embed fuzzy-logic modules into their application programs. Fuzzy logic is useful as a means of formulating human expert knowledge and translating it into software to solve problems. Fuzzy logic provides flexibility for modeling relationships between input and output information and is distinguished by its robustness with respect to noise and variations in system parameters. In addition, linguistic fuzzy sets and conditional statements allow systems to make decisions based on imprecise and incomplete information. The user of the Fuzzy Logic Engine need not be an expert in fuzzy logic: it suffices to have a basic understanding of how linguistic rules can be applied to the user's problem. The Fuzzy Logic Engine is divided into two modules: (1) a graphical-interface software tool for creating linguistic fuzzy sets and conditional statements and (2) a fuzzy-logic software library for embedding fuzzy processing capability into current application programs. The graphical- interface tool was developed using the Tcl/Tk programming language. The fuzzy-logic software library was written in the C programming language.
Resnik, Jennifer; Polley, Daniel B
2017-01-01
Cortical neurons remap their receptive fields and rescale sensitivity to spared peripheral inputs following sensory nerve damage. To address how these plasticity processes are coordinated over the course of functional recovery, we tracked receptive field reorganization, spontaneous activity, and response gain from individual principal neurons in the adult mouse auditory cortex over a 50-day period surrounding either moderate or massive auditory nerve damage. We related the day-by-day recovery of sound processing to dynamic changes in the strength of intracortical inhibition from parvalbumin-expressing (PV) inhibitory neurons. Whereas the status of brainstem-evoked potentials did not predict the recovery of sensory responses to surviving nerve fibers, homeostatic adjustments in PV-mediated inhibition during the first days following injury could predict the eventual recovery of cortical sound processing weeks later. These findings underscore the potential importance of self-regulated inhibitory dynamics for the restoration of sensory processing in excitatory neurons following peripheral nerve injuries. DOI: http://dx.doi.org/10.7554/eLife.21452.001 PMID:28323619
NASA Astrophysics Data System (ADS)
Nomura, Fumimasa; Hattori, Akihiro; Terazono, Hideyuki; Kim, Hyonchol; Odaka, Masao; Sugio, Yoshihiro; Yasuda, Kenji
2016-06-01
For the prediction of lethal arrhythmia occurrence caused by abnormality of cell-to-cell conduction, we have developed a next-generation in vitro cell-to-cell conduction assay, i.e., a quasi in vivo assay, in which the change in spatial cell-to-cell conduction is quantitatively evaluated from the change in waveforms of the convoluted electrophysiological signals from lined-up cardiomyocytes on a single closed loop of a microelectrode of 1 mm diameter and 20 µm width in a cultivation chip. To evaluate the importance of the closed-loop arrangement of cardiomyocytes for prediction, we compared the change in waveforms of convoluted signals of the responses in the closed-loop circuit arrangement with that of the response of cardiomyocyte clusters using a typical human ether a go-go related gene (hERG) ion channel blocker, E-4031. The results showed that (1) waveform prolongation and fluctuation both in the closed loops and clusters increased depending on the E-4031 concentration increase. However, (2) only the waveform signals in closed loops showed an apparent temporal change in waveforms from ventricular tachycardia (VT) to ventricular fibrillation (VF), which is similar to the most typical cell-to-cell conductance abnormality. The results indicated the usefulness of convoluted waveform signals of a closed-loop cell network for acquiring reproducible results acquisition and more detailed temporal information on cell-to-cell conduction.
Photonic encryption using all optical logic.
Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.; Robertson, Perry J.; Vawter, Gregory Allen; Tarman, Thomas David; Pierson, Lyndon George
2003-12-01
With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an
Integrated-Circuit Controller For Brushless dc Motor
NASA Technical Reports Server (NTRS)
Le, Dong Tuan
1994-01-01
Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.
Thomas, R.E.
1959-01-20
An electronic circuit is presented for automatically computing the product of two selected variables by multiplying the voltage pulses proportional to the variables. The multiplier circuit has a plurality of parallel resistors of predetermined values connected through separate gate circults between a first input and the output terminal. One voltage pulse is applied to thc flrst input while the second voltage pulse is applied to control circuitry for the respective gate circuits. Thc magnitude of the second voltage pulse selects the resistors upon which the first voltage pulse is imprcssed, whereby the resultant output voltage is proportional to the product of the input voltage pulses
Merrill, L.C.
1958-10-14
Control circuits for vacuum tubes are described, and a binary counter having an improved trigger circuit is reported. The salient feature of the binary counter is the application of the input signal to the cathode of each of two vacuum tubes through separate capacitors and the connection of each cathode to ground through separate diodes. The control of the binary counter is achieved in this manner without special pulse shaping of the input signal. A further advantage of the circuit is the simplicity and minimum nuruber of components required, making its use particularly desirable in computer machines.
Optical Circuit Switched Protocol
NASA Technical Reports Server (NTRS)
Monacos, Steve P. (Inventor)
2000-01-01
The present invention is a system and method embodied in an optical circuit switched protocol for the transmission of data through a network. The optical circuit switched protocol is an all-optical circuit switched network and includes novel optical switching nodes for transmitting optical data packets within a network. Each optical switching node comprises a detector for receiving the header, header detection logic for translating the header into routing information and eliminating the header, and a controller for receiving the routing information and configuring an all optical path within the node. The all optical path located within the node is solely an optical path without having electronic storage of the data and without having optical delay of the data. Since electronic storage of the header is not necessary and the initial header is eliminated by the first detector of the first switching node. multiple identical headers are sent throughout the network so that subsequent switching nodes can receive and read the header for setting up an optical data path.
Partition algebraic design of asynchronous sequential circuits
NASA Technical Reports Server (NTRS)
Maki, Gary K.; Chen, Kristen Q.; Gopalakrishnan, Suresh K.
1993-01-01
Tracey's Theorem has long been recognized as essential in generating state assignments for asynchronous sequential circuits. This paper shows that partitioning variables derived from Tracey's Theorem also has a significant impact in generating the design equations. Moreover, this theorem is important to the fundamental understanding of asynchronous sequential operation. The results of this work simplify asynchronous logic design. Moreover, detection of safe circuits is made easier.
Novel Quaternary Quantum Decoder, Multiplexer and Demultiplexer Circuits
NASA Astrophysics Data System (ADS)
Haghparast, Majid; Monfared, Asma Taheri
2017-02-01
Multiple valued logic is a promising approach to reduce the width of the reversible or quantum circuits, moreover, quaternary logic is considered as being a good choice for future quantum computing technology hence it is very suitable for the encoded realization of binary logic functions through its grouping of 2-bits together into quaternary values. The Quaternary decoder, multiplexer, and demultiplexer are essential units of quaternary digital systems. In this paper, we have initially designed a quantum realization of the quaternary decoder circuit using quaternary 1-qudit gates and quaternary Muthukrishnan-Stroud gates. Then we have presented quantum realization of quaternary multiplexer and demultiplexer circuits using the constructed quaternary decoder circuit and quaternary controlled Feynman gates. The suggested circuits in this paper have a lower quantum cost and hardware complexity than the existing designs that are currently used in quaternary digital systems. All the scales applied in this paper are based on Nanometric area.
Principles of Intelligence: On Evolutionary Logic of the Brain
Tsien, Joe Z.
2016-01-01
Humans and animals may encounter numerous events, objects, scenes, foods and countless social interactions in a lifetime. This means that the brain is constructed by evolution to deal with uncertainties and various possibilities. What is the architectural abstraction of intelligence that enables the brain to discover various possible patterns and knowledge about complex, evolving worlds? Here, I discuss the Theory of Connectivity–a “power-of-two” based, operational principle that can serve as a unified wiring and computational logic for organizing and constructing cell assemblies into the microcircuit-level building block, termed as functional connectivity motif (FCM). Defined by the power-of-two based equation, N = 2i−1, each FCM consists of the principal projection neuron cliques (N), ranging from those specific cliques receiving specific information inputs (i) to those general and sub-general cliques receiving various combinatorial convergent inputs. As the evolutionarily conserved logic, its validation requires experimental demonstrations of the following three major properties: (1) Anatomical prevalence—FCMs are prevalent across neural circuits, regardless of gross anatomical shapes; (2) Species conservancy—FCMs are conserved across different animal species; and (3) Cognitive universality—FCMs serve as a universal computational logic at the cell assembly level for processing a variety of cognitive experiences and flexible behaviors. More importantly, this Theory of Connectivity further predicts that the specific-to-general combinatorial connectivity pattern within FCMs should be preconfigured by evolution, and emerge innately from development as the brain’s computational primitives. This proposed design-principle can also explain the general purpose of the layered cortex and serves as its core computational algorithm. PMID:26869892
Principles of Intelligence: On Evolutionary Logic of the Brain.
Tsien, Joe Z
2015-01-01
Humans and animals may encounter numerous events, objects, scenes, foods and countless social interactions in a lifetime. This means that the brain is constructed by evolution to deal with uncertainties and various possibilities. What is the architectural abstraction of intelligence that enables the brain to discover various possible patterns and knowledge about complex, evolving worlds? Here, I discuss the Theory of Connectivity-a "power-of-two" based, operational principle that can serve as a unified wiring and computational logic for organizing and constructing cell assemblies into the microcircuit-level building block, termed as functional connectivity motif (FCM). Defined by the power-of-two based equation, N = 2 (i) -1, each FCM consists of the principal projection neuron cliques (N), ranging from those specific cliques receiving specific information inputs (i) to those general and sub-general cliques receiving various combinatorial convergent inputs. As the evolutionarily conserved logic, its validation requires experimental demonstrations of the following three major properties: (1) Anatomical prevalence-FCMs are prevalent across neural circuits, regardless of gross anatomical shapes; (2) Species conservancy-FCMs are conserved across different animal species; and (3) Cognitive universality-FCMs serve as a universal computational logic at the cell assembly level for processing a variety of cognitive experiences and flexible behaviors. More importantly, this Theory of Connectivity further predicts that the specific-to-general combinatorial connectivity pattern within FCMs should be preconfigured by evolution, and emerge innately from development as the brain's computational primitives. This proposed design-principle can also explain the general purpose of the layered cortex and serves as its core computational algorithm.
Programmable Logic Controllers.
ERIC Educational Resources Information Center
Insolia, Gerard; Anderson, Kathleen
This document contains a 40-hour course in programmable logic controllers (PLC), developed for a business-industry technology resource center for firms in eastern Pennsylvania by Northampton Community College. The 10 units of the course cover the following: (1) introduction to programmable logic controllers; (2) DOS primer; (3) prerequisite…
ERIC Educational Resources Information Center
Osborne, Alan R.
1973-01-01
This article reports one search for factors or conditions shaping the child's growth in logical ability. The search indicated the existence of a relationship between the quantity of teacher talk that contains the language of logic and the change exhibited by students. Implications for classroom practice are discussed. (JA)
Logic via Computer Programming.
ERIC Educational Resources Information Center
Wieschenberg, Agnes A.
This paper proposed the question "How do we teach logical thinking and sophisticated mathematics to unsophisticated college students?" One answer among many is through the writing of computer programs. The writing of computer algorithms is mathematical problem solving and logic in disguise and it may attract students who would otherwise stop…
ERIC Educational Resources Information Center
Lopez, Antonio M., Jr.
1989-01-01
Provides background material on logic programing and presents PROLOG as a high-level artificial intelligence programing language that borrows its basic constructs from logic. Suggests the language is one which will help the educator to achieve various goals, particularly the promotion of problem solving ability. (MVL)
Microelectromechanical reprogrammable logic device
NASA Astrophysics Data System (ADS)
Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.
2016-03-01
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.
Microelectromechanical reprogrammable logic device
Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.
2016-01-01
In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295
Three-Function Logic Gate Controlled by Analog Voltage
NASA Technical Reports Server (NTRS)
Zebulum, Ricardo; Stoica, Adrian
2006-01-01
The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If
Lees, G.W.; McCormick, E.D.
1962-05-22
A tripping circuit employing a magnetic amplifier for tripping a reactor in response to power level, period, or instrument failure is described. A reference winding and signal winding are wound in opposite directions on the core. Current from an ion chamber passes through both windings. If the current increases at too fast a rate, a shunt circuit bypasses one or the windings and the amplifier output reverses polarity. (AEC)
Regulatory Conformance Checking: Logic and Logical Form
ERIC Educational Resources Information Center
Dinesh, Nikhil
2010-01-01
We consider the problem of checking whether an organization conforms to a body of regulation. Conformance is studied in a runtime verification setting. The regulation is translated to a logic, from which we synthesize monitors. The monitors are evaluated as the state of an organization evolves over time, raising an alarm if a violation is…
Surface-confined assemblies and polymers for molecular logic.
de Ruiter, Graham; van der Boom, Milko E
2011-08-16
Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the
Logic-controlled solid state switchgear for 270 volts dc
NASA Technical Reports Server (NTRS)
Sundberg, G. R.; Waddington, D.; Buchanan, E. E., Jr.
1973-01-01
A feasibility study to design and demonstrate solid state switchgear in the form of circuit breakers and a power transfer switch is described. The switchgear operates on a nominal 270 V dc circuit and controls power to a load of up to 15 amperes. One circuit breaker may be interconnected to a second breaker to form a power transfer switch. On-off and transfer functions of the breakers or the transfer switch are remotely controlled. A number of reclosures with variable time delay between tripout and reclosure are programmed and controlled by integrated analog and COSMOS logic circuits. A unique commutation circuit, that generates only minimal transient disturbance to either source or load, was developed to interrupt current flow through the main SCR switching element. Laboratory tests demonstrated performance of the solid state circuit breakers over specified voltage and temperature ranges.
Computer circuit will fit on single silicon chip
NASA Technical Reports Server (NTRS)
Smith, C.
1964-01-01
A simplified computer logic circuit of two NAND/NOR gates and three additional inputs to accomplish the count and shift function is described. The circuit has capacity for parallel read-in, counting, serial shiftout, complement input and set and reset.
Simple circuit performs binary addition and subtraction
NASA Technical Reports Server (NTRS)
Cliff, R. A.; Schaefer, D. H.
1965-01-01
Ripple adder reduces the number of logic circuits required to preform binary addition and subtraction. The adder uses dual input and delayed output flip-flops in one register. The contents of this register are summed with those of a standard register through conventional AND/gates.
Biologically Self-Assembled Memristive Circuit Elements
2010-01-01
and sonication for 5 min ( Branson 1510). DNA Binding to TiO2 Nanoparticles DNA binding to TiO2 particles was determined by varying the...X. Li, D.A.A. Ohlberg, W. Wu, D.R. Stewart, and R.S. Williams . “A hybrid nanomemristor/transistor logic circuit capable of self-programming,” PNAS
Heat-Transfer Microstructures for Integrated Circuits
2007-11-02
fatigue failure curves for silicon mounted on molybdenum or copper (from Lang et a[ [75]). Microcapillary thermal interface concept. a) Tunnels...Coolant Figure of Merit Complementary Metal-Oxide-Semiconductor Emitter- Coupled Logic Integrated Circuit Metal-Oxide-Semiconductor Median Time to...nominally independent devices; for example, electromagnetic coupling (crosstalk) between adjacent long, parallel wires on an IC, especially when a ground
Processing of Image Data by Integrated Circuits
NASA Technical Reports Server (NTRS)
Armstrong, R. W.
1985-01-01
Sensors combined with logic and memory circuitry. Cross-correlation of two inputs accomplished by transversal filter. Position of image taken to point where image and template data yield maximum value correlation function. Circuit used for controlling robots, medical-image analysis, automatic vehicle guidance, and precise pointing of scientific cameras.
Rajasethupathy, Priyamvada; Ferenczi, Emily; Deisseroth, Karl
2017-01-01
Current optogenetic methodology enables precise inhibition or excitation of neural circuits, spanning timescales as needed from the acute (milliseconds) to the chronic (many days or more), for experimental modulation of network activity and animal behavior. Such broad temporal versatility, unique to optogenetic control, is particularly powerful when combined with brain activity measurements that span both acute and chronic timescales as well. This enables, for instance, the study of adaptive circuit dynamics across the intact brain, and tuning interventions to match activity patterns naturally observed during behavior in the same individual. Although the impact of this approach has been greater on basic research than on clinical translation, it is natural to ask if specific neural circuit activity patterns discovered to be involved in controlling adaptive or maladaptive behaviors could become targets for treatment of neuropsychiatric diseases. Here we consider the landscape of such ideas related to therapeutic targeting of circuit dynamics, taking note of developments not only in optical but also in ultrasonic, magnetic, and thermal methods. We note the recent emergence of first-in-kind optogenetically-guided clinical outcomes, as well as opportunities related to the integration of interventions and readouts spanning diverse circuit-physiology, molecular, and behavioral modalities. PMID:27104976
Perrot, Nathalie; Baudrit, Cédric; Brousset, Jean Marie; Abbal, Philippe; Guillemin, Hervé; Perret, Bruno; Goulet, Etienne; Guerin, Laurence; Barbeau, Gérard; Picque, Daniel
2015-01-01
Agri-food is one of the most important sectors of the industry and a major contributor to the global warming potential in Europe. Sustainability issues pose a huge challenge for this sector. In this context, a big issue is to be able to predict the multiscale dynamics of those systems using computing science. A robust predictive mathematical tool is implemented for this sector and applied to the wine industry being easily able to be generalized to other applications. Grape berry maturation relies on complex and coupled physicochemical and biochemical reactions which are climate dependent. Moreover one experiment represents one year and the climate variability could not be covered exclusively by the experiments. Consequently, harvest mostly relies on expert predictions. A big challenge for the wine industry is nevertheless to be able to anticipate the reactions for sustainability purposes. We propose to implement a decision support system so called FGRAPEDBN able to (1) capitalize the heterogeneous fragmented knowledge available including data and expertise and (2) predict the sugar (resp. the acidity) concentrations with a relevant RMSE of 7 g/l (resp. 0.44 g/l and 0.11 g/kg). FGRAPEDBN is based on a coupling between a probabilistic graphical approach and a fuzzy expert system.
Brousset, Jean Marie; Abbal, Philippe; Guillemin, Hervé; Perret, Bruno; Goulet, Etienne; Guerin, Laurence; Barbeau, Gérard; Picque, Daniel
2015-01-01
Agri-food is one of the most important sectors of the industry and a major contributor to the global warming potential in Europe. Sustainability issues pose a huge challenge for this sector. In this context, a big issue is to be able to predict the multiscale dynamics of those systems using computing science. A robust predictive mathematical tool is implemented for this sector and applied to the wine industry being easily able to be generalized to other applications. Grape berry maturation relies on complex and coupled physicochemical and biochemical reactions which are climate dependent. Moreover one experiment represents one year and the climate variability could not be covered exclusively by the experiments. Consequently, harvest mostly relies on expert predictions. A big challenge for the wine industry is nevertheless to be able to anticipate the reactions for sustainability purposes. We propose to implement a decision support system so called FGRAPEDBN able to (1) capitalize the heterogeneous fragmented knowledge available including data and expertise and (2) predict the sugar (resp. the acidity) concentrations with a relevant RMSE of 7 g/l (resp. 0.44 g/l and 0.11 g/kg). FGRAPEDBN is based on a coupling between a probabilistic graphical approach and a fuzzy expert system. PMID:26230334
A single nano cantilever as a reprogrammable universal logic gate
NASA Astrophysics Data System (ADS)
Chappanda, K. N.; Ilyas, S.; Kazmi, S. N. R.; Holguin-Lerma, J.; Batra, N. M.; Costa, P. M. F. J.; Younis, M. I.
2017-04-01
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.
N channel JFET based digital logic gate structure
NASA Technical Reports Server (NTRS)
Krasowski, Michael J. (Inventor)
2010-01-01
A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.
A wire of Nitinol can be stretched up to a given amount and will remain in this stretched state until heated to a critical temperature. When heated...circuit of this invention provides a current pulse for the required time period to heat the Nitinol wire to its critical temperature to thereby restore the...wire to its original length. The circuit includes a high power transistor which is gated on for a controlled time to provide the required power to heat the Nitinol wire to its critical temperature. (Author)
Chase, R.L.
1963-05-01
An electronic fast multiplier circuit utilizing a transistor controlled voltage divider network is presented. The multiplier includes a stepped potentiometer in which solid state or transistor switches are substituted for mechanical wipers in order to obtain electronic switching that is extremely fast as compared to the usual servo-driven mechanical wipers. While this multiplier circuit operates as an approximation and in steps to obtain a voltage that is the product of two input voltages, any desired degree of accuracy can be obtained with the proper number of increments and adjustment of parameters. (AEC)
Gallium arsenide processing for gate array logic
NASA Technical Reports Server (NTRS)
Cole, Eric D.
1989-01-01
The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.
Gallium arsenide processing for gate array logic
NASA Astrophysics Data System (ADS)
Cole, Eric D.
1989-09-01
The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.
1981-01-01
79/7, Imperial College, University of London. [Colmerauer 1973] Colmerauer, A., Un Systeme de Communication Homme - machine Kanoui, H., en Francais...any of the LOGIC interface functions (,-, THE, ALL, ANY, etc.) can be obtained by invoking the command (DOC fn), where "fn" is the name of the function...well as for output) illustrates one more way in which the LOGLISP programmer can fruitfully exploit the interface between LOGIC and LISP. GIVE is just a
2008-07-14
as a basis for Phase II research. 2 Background 2.1 Event logic 2.1.1 Event structures Intuitively, an event structure is an abstract algebraic ...Theoretical Computer Science, 149:257–298, 1995. [2] Uri Abraham. Models for Concurrency, volume 11 of Algebra , Logic and Applications Series. Gordon...the ordering of events in a distributed system. Comms. ACM, 21(7):558–65, 1978. [28] Leslie Lamport. Hybrid systems in TLA+. In Grossman , Nerode, Ravn
Design Techniques for Power-Aware Combinational Logic SER Mitigation
NASA Astrophysics Data System (ADS)
Mahatme, Nihaar N.
The history of modern semiconductor devices and circuits suggests that technologists have been able to maintain scaling at the rate predicted by Moore's Law [Moor-65]. With improved performance, speed and lower area, technology scaling has also exacerbated reliability issues such as soft errors. Soft errors are transient errors that occur in microelectronic circuits due to ionizing radiation particle strikes on reverse biased semiconductor junctions. These radiation induced errors at the terrestrial-level are caused due to radiation particle strikes by (1) alpha particles emitted as decay products of packing material (2) cosmic rays that produce energetic protons and neutrons, and (3) thermal neutrons [Dodd-03], [Srou-88] and more recently muons and electrons [Ma-79] [Nara-08] [Siew-10] [King-10]. In the space environment radiation induced errors are a much bigger threat and are mainly caused by cosmic heavy-ions, protons etc. The effects of radiation exposure on circuits and measures to protect against them have been studied extensively for the past 40 years, especially for parts operating in space. Radiation particle strikes can affect memory as well as combinational logic. Typically when these particles strike semiconductor junctions of transistors that are part of feedback structures such as SRAM memory cells or flip-flops, it can lead to an inversion of the cell content. Such a failure is formally called a bit-flip or single-event upset (SEU). When such particles strike sensitive junctions part of combinational logic gates they produce transient voltage spikes or glitches called single-event transients (SETs) that could be latched by receiving flip-flops. As the circuits are clocked faster, there are more number of clocking edges which increases the likelihood of latching these transients. In older technology generations the probability of errors in flip-flops due to SETs being latched was much lower compared to direct strikes on flip-flops or SRAMs leading to
Automatic logic synthesis for parallel alternating latches clocking schemes
NASA Astrophysics Data System (ADS)
Guerrero, D.; Bellido, M.; Juan, J.; Millan, A.; Ruiz, P.; Ostua, E.; Viejo, J.
2007-05-01
This paper proposes a VHDL coding technique that allows for the automatic synthesis of digital circuits using the so called Parallel Alternating Latches Clocking Schemes (PALACS). The proposed method greatly improves the applicability of PALACS and its benefits. This technique is verified through design examples in three different CMOS processes and using logic level simulation, with successful results in all the cases.
The Development of a Digital Logic Concept Inventory
ERIC Educational Resources Information Center
Herman, Geoffrey Lindsay
2011-01-01
Instructors in electrical and computer engineering and in computer science have developed innovative methods to teach digital logic circuits. These methods attempt to increase student learning, satisfaction, and retention. Although there are readily accessible and accepted means for measuring satisfaction and retention, there are no widely…
Optical logic array processor using shadowgrams
NASA Astrophysics Data System (ADS)
Tanida, J.; Ichioka, Y.
1983-06-01
On the basis of a lensless shadow-casting technique, a new, simple method of optically implementing digital logic gates has been developed. These gates are capable of performimg a complete set of logical operations on a large array of binary variables in parallel, i.e., the pattern logics. A light-emitting diode (LED) array is used as an incoherent light source in the lensless shadow-casting system. Sixteen possible functions of two binary variables are simply realizable with these gates in parallel by controlling the switching modes of the LEDs. Experimental results demonstrate the feasibility of various gate arrays, such as AND, OR, NOR, XOR, and NAND. As an example of application of the proposed method, an optical logic array processor is constructed that can implement parallel operations of addition or subtraction for two binary variables without considering the carry mechanisms. Use of the light-modulated LED array means that the proposed method can be applied to combinational circuits.
Circuit for high resolution decoding of multi-anode microchannel array detectors
NASA Technical Reports Server (NTRS)
Kasle, David B. (Inventor)
1995-01-01
A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.
Multi-input regulation and logic with T7 promoters in cells and cell-free systems.
Iyer, Sukanya; Karig, David K; Norred, S Elizabeth; Simpson, Michael L; Doktycz, Mitchel J
2013-01-01
Engineered gene circuits offer an opportunity to harness biological systems for biotechnological and biomedical applications. However, reliance on native host promoters for the construction of circuit elements, such as logic gates, can make the implementation of predictable, independently functioning circuits difficult. In contrast, T7 promoters offer a simple orthogonal expression system for use in a variety of cellular backgrounds and even in cell-free systems. Here we develop a T7 promoter system that can be regulated by two different transcriptional repressors for the construction of a logic gate that functions in cells and in cell-free systems. We first present LacI repressible T7lacO promoters that are regulated from a distal lac operator site for repression. We next explore the positioning of a tet operator site within the T7lacO framework to create T7 promoters that respond to tet and lac repressors and realize an IMPLIES gate. Finally, we demonstrate that these dual input sensitive promoters function in an E. coli cell-free protein expression system. Our results expand the utility of T7 promoters in cell based as well as cell-free synthetic biology applications.
Multi-Input Regulation and Logic with T7 Promoters in Cells and Cell-Free Systems
Norred, S. Elizabeth; Simpson, Michael L.; Doktycz, Mitchel J.
2013-01-01
Engineered gene circuits offer an opportunity to harness biological systems for biotechnological and biomedical applications. However, reliance on native host promoters for the construction of circuit elements, such as logic gates, can make the implementation of predictable, independently functioning circuits difficult. In contrast, T7 promoters offer a simple orthogonal expression system for use in a variety of cellular backgrounds and even in cell-free systems. Here we develop a T7 promoter system that can be regulated by two different transcriptional repressors for the construction of a logic gate that functions in cells and in cell-free systems. We first present LacI repressible T7lacO promoters that are regulated from a distal lac operator site for repression. We next explore the positioning of a tet operator site within the T7lacO framework to create T7 promoters that respond to tet and lac repressors and realize an IMPLIES gate. Finally, we demonstrate that these dual input sensitive promoters function in an E. coli cell-free protein expression system. Our results expand the utility of T7 promoters in cell based as well as cell-free synthetic biology applications. PMID:24194933
Noise-free logical stochastic resonance.
Gupta, Animesh; Sohane, Aman; Kohar, Vivek; Murali, K; Sinha, Sudeshna
2011-11-01
The phenomena of logical stochastic resonance (LSR) was demonstrated recently [Phys. Rev. Lett. 102, 104101 (2009)]: namely, when a bistable system is driven by two inputs it consistently yields a response mirroring a logic function of the two inputs in an optimal window of moderate noise. Here we examine the intriguing possibility of obtaining dynamical behavior equivalent to LSR in a noise-free bistable system, subjected only to periodic forcing, such as sinusoidal driving or rectangular pulse trains. We find that such a system, despite having no stochastic influence, also yields phenomena analogous to LSR, in an appropriate window of frequency and amplitude of the periodic forcing. The results are corroborated by circuit experiments.
Towards bioelectronic logic (Conference Presentation)
NASA Astrophysics Data System (ADS)
Meredith, Paul; Mostert, Bernard; Sheliakina, Margarita; Carrad, Damon J.; Micolich, Adam P.
2016-09-01
One of the critical tasks in realising a bioelectronic interface is the transduction of ion and electron signals at high fidelity, and with appropriate speed, bandwidth and signal-to-noise ratio [1]. This is a challenging task considering ions and electrons (or holes) have drastically different physics. For example, even the lightest ions (protons) have mobilities much smaller than electrons in the best semiconductors, effective masses are quite different, and at the most basic level, ions are `classical' entities and electrons `quantum mechanical'. These considerations dictate materials and device strategies for bioelectronic interfaces alongside practical aspects such as integration and biocompatibility [2]. In my talk I will detail these `differences in physics' that are pertinent to the ion-electron transduction challenge. From this analysis, I will summarise the basic categories of device architecture that are possibilities for transducing elements and give recent examples of their realisation. Ultimately, transducing elements need to be combined to create `bioelectronic logic' capable of signal processing at the interface level. In this regard, I will extend the discussion past the single element concept, and discuss our recent progress in delivering all-solids-state logic circuits based upon transducing interfaces. [1] "Ion bipolar junction transistors", K. Tybrandt, K.C. Larsson, A. Richter-Dahlfors and M. Berggren, Proc. Natl Acad. Sci., 107, 9929 (2010). [2] "Electronic and optoelectronic materials and devices inspired by nature", P Meredith, C.J. Bettinger, M. Irimia-Vladu, A.B. Mostert and P.E. Schwenn, Reports on Progress in Physics, 76, 034501 (2013).
Teleology as Logical Phenomenology: Some Therapeutic Implications.
ERIC Educational Resources Information Center
Rychlak, Joseph F.
Phenomenology is an important force in the development of psychological theory, rather than a variant type of counseling method. A distinction must be drawn between the sensory phenomenology in which gestaltists focus on sensory receptors, and logical pheomenology in which the grounding of belief or self-identity is viewed as a prediction or…
Subnanowatt carbon nanotube complementary logic enabled by threshold voltage control.
Geier, Michael L; Prabhumirashi, Pradyumna L; McMorrow, Julian J; Xu, Weichao; Seo, Jung-Woo T; Everaerts, Ken; Kim, Chris H; Marks, Tobin J; Hersam, Mark C
2013-10-09
In this Letter, we demonstrate thin-film single-walled carbon nanotube (SWCNT) complementary metal-oxide-semiconductor (CMOS) logic devices with subnanowatt static power consumption and full rail-to-rail voltage transfer characteristics as is required for logic gate cascading. These results are enabled by a local metal gate structure that achieves enhancement-mode p-type and n-type SWCNT thin-film transistors (TFTs) with widely separated and symmetric threshold voltages. These complementary SWCNT TFTs are integrated to demonstrate CMOS inverter, NAND, and NOR logic gates at supply voltages as low as 0.8 V with ideal rail-to-rail operation, subnanowatt static power consumption, high gain, and excellent noise immunity. This work provides a direct pathway for solution processable, large area, power efficient SWCNT advanced logic circuits and systems.
Stacked resistive switches for AND/OR logic gates
NASA Astrophysics Data System (ADS)
Kim, Myung Ju; Son, Kyung Rock; Park, Ju Hyun; Kim, Tae Geun
2017-06-01
This paper reports the use of stacked resistive switches as logic gates for implementing the ;AND; and ;OR; operations. These stacked resistive switches consist of two resistive switches that share a middle electrode, and they operate based on the difference in resistance between the low and high resistance states indicating the logical states of ;0; and ;1;, respectively. The stacked resistive switches can perform either AND or OR operation, using two read schemes in one device. To perform the AND (or OR) operation, two resistive switches are arranged in a serial (or parallel) connection. AND and OR operations have been successfully demonstrated using the stacked resistive switches. The use of stacked resistive switches as logic gates that utilize the advantages of memristive devices shows the possibility of stateful logic circuits.
NASA Astrophysics Data System (ADS)
Kreutz, M.; Richalet, J.; Mocha, K.; Haber, R.
2014-12-01
HVAC systems of industrial buildings consume a lot of energy. Therefore it is important to know the performance of these systems and strategies to optimize the hardware and the control. Tackling the temperature control of the HVAC system promises quick savings by tuning the control within specified tolerance limits, which mostly can be done by low investment. This paper mainly deals with the implementation strategy of a new controller in a PLC using the predictive functional control for temperature control. The different stages of the implementation from the simulation over the SCL code till to the real-time operation are presented. A bumpless switch between the PI(D) and the PFC control was realized, as well.
Diagnosable structured logic array
NASA Technical Reports Server (NTRS)
Whitaker, Sterling (Inventor); Miles, Lowell (Inventor); Gambles, Jody (Inventor); Maki, Gary K. (Inventor)
2009-01-01
A diagnosable structured logic array and associated process is provided. A base cell structure is provided comprising a logic unit comprising a plurality of input nodes, a plurality of selection nodes, and an output node, a plurality of switches coupled to the selection nodes, where the switches comprises a plurality of input lines, a selection line and an output line, a memory cell coupled to the output node, and a test address bus and a program control bus coupled to the plurality of input lines and the selection line of the plurality of switches. A state on each of the plurality of input nodes is verifiably loaded and read from the memory cell. A trusted memory block is provided. The associated process is provided for testing and verifying a plurality of truth table inputs of the logic unit.
A Simple Memristor Model for Circuit Simulations
NASA Astrophysics Data System (ADS)
Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team
This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.
Thermionic integrated circuits
MacRoberts, M.; Brown, D.R.; Dooley, R.; Lemons, R.; Lynn, D.; McCormick, B.; Mombourquette, C.; Sinah, D.
1986-01-01
Thermionic integrated circuits combine vacuum-tube technology with integrated-circuit techniques to form integrated vacuum circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments.
Design and implementation of a delay-optimized universal programmable routing circuit for FPGAs
NASA Astrophysics Data System (ADS)
Fang, Wu; Huowen, Zhang; Jinmei, Lai; Yuan, Wang; Liguang, Chen; Lei, Duan; Jiarong, Tong
2009-06-01
This paper presents a universal field programmable gate array (FPGA) programmable routing circuit, focusing primarily on a delay optimization. Under the precondition of the routing resource's flexibility and routability, the number of programmable interconnect points (PIP) is reduced, and a multiplexer (MUX) plus a BUFFER structure is adopted as the programmable switch. Also, the method of offset lines and the method of complementary hanged end-lines are applied to the TILE routing circuit and the I/O routing circuit, respectively. All of the above features ensure that the whole FPGA chip is highly repeatable, and the signal delay is uniform and predictable over the total chip. Meanwhile, the BUFFER driver is optimized to decrease the signal delay by up to 5%. The proposed routing circuit is applied to the Fudan programmable device (FDP) FPGA, which has been taped out with an SMIC 0.18-μm logic 1P6M process. The test result shows that the programmable routing resource works correctly, and the signal delay over the chip is highly uniform and predictable.
Modeling and simulation of single-event effect in CMOS circuit
NASA Astrophysics Data System (ADS)
Suge, Yue; Xiaolin, Zhang; Yuanfu, Zhao; Lin, Liu; Hanning, Wang
2015-11-01
This paper reviews the status of research in modeling and simulation of single-event effects (SEE) in digital devices and integrated circuits. After introducing a brief historical overview of SEE simulation, different level simulation approaches of SEE are detailed, including material-level physical simulation where two primary methods by which ionizing radiation releases charge in a semiconductor device (direct ionization and indirect ionization) are introduced, device-level simulation where the main emerging physical phenomena affecting nanometer devices (bipolar transistor effect, charge sharing effect) and the methods envisaged for taking them into account are focused on, and circuit-level simulation where the methods for predicting single-event response about the production and propagation of single-event transients (SETs) in sequential and combinatorial logic are detailed, as well as the soft error rate trends with scaling are particularly addressed.
Equivalent circuit for birdcage resonators.
Harpen, M D
1993-02-01
We present an equivalent circuit analysis for both low pass and high pass birdcage resonators loaded with lossy samples. In a generalization of the method of Hoult and Lauterbur (J. Magn. Reson. 34, 425 (1979)), we also derive circuit component values by application of the laws of electrodynamics. Measured resonance spectra, quality factors, and feed point impedances in a test resonator are shown to be in agreement with those predicted by the proposed model.
Fuzzy logic and neural network technologies
NASA Technical Reports Server (NTRS)
Villarreal, James A.; Lea, Robert N.; Savely, Robert T.
1992-01-01
Applications of fuzzy logic technologies in NASA projects are reviewed to examine their advantages in the development of neural networks for aerospace and commercial expert systems and control. Examples of fuzzy-logic applications include a 6-DOF spacecraft controller, collision-avoidance systems, and reinforcement-learning techniques. The commercial applications examined include a fuzzy autofocusing system, an air conditioning system, and an automobile transmission application. The practical use of fuzzy logic is set in the theoretical context of artificial neural systems (ANSs) to give the background for an overview of ANS research programs at NASA. The research and application programs include the Network Execution and Training Simulator and faster training algorithms such as the Difference Optimized Training Scheme. The networks are well suited for pattern-recognition applications such as predicting sunspots, controlling posture maintenance, and conducting adaptive diagnoses.
Energy-Efficient Wide Datapath Integer Arithmetic Logic Units Using Superconductor Logic
NASA Astrophysics Data System (ADS)
Ayala, Christopher Lawrence
Complementary Metal-Oxide-Semiconductor (CMOS) technology is currently the most widely used integrated circuit technology today. As CMOS approaches the physical limitations of scaling, it is unclear whether or not it can provide long-term support for niche areas such as high-performance computing and telecommunication infrastructure, particularly with the emergence of cloud computing. Alternatively, superconductor technologies based on Josephson junction (JJ) switching elements such as Rapid Single Flux Quantum (RSFQ) logic and especially its new variant, Energy-Efficient Rapid Single Flux Quantum (ERSFQ) logic have the capability to provide an ultra-high-speed, low power platform for digital systems. The objective of this research is to design and evaluate energy-efficient, high-speed 32-bit integer Arithmetic Logic Units (ALUs) implemented using RSFQ and ERSFQ logic as the first steps towards achieving practical Very-Large-Scale-Integration (VLSI) complexity in digital superconductor electronics. First, a tunable VHDL superconductor cell library is created to provide a mechanism to conduct design exploration and evaluation of superconductor digital circuits from the perspectives of functionality, complexity, performance, and energy-efficiency. Second, hybrid wave-pipelining techniques developed earlier for wide datapath RSFQ designs have been used for efficient arithmetic and logic circuit implementations. To develop the core foundation of the ALU, the ripple-carry adder and the Kogge-Stone parallel prefix carry look-ahead adder are studied as representative candidates on opposite ends of the design spectrum. By combining the high-performance features of the Kogge-Stone structure and the low complexity of the ripple-carry adder, a 32-bit asynchronous wave-pipelined hybrid sparse-tree ALU has been designed and evaluated using the VHDL cell library tuned to HYPRES' gate-level characteristics. The designs and techniques from this research have been implemented using
NASA Astrophysics Data System (ADS)
Kapit, Eliot
Superconducting qubits are among the most promising platforms for building a quantum computer. However, individual qubit coherence times are not far past the scalability threshold for quantum error correction, meaning that millions of physical devices would be required to construct a useful quantum computer. Consequently, further increases in coherence time are very desirable. In this letter, we blueprint a simple circuit consisting of two transmon qubits and two additional lossy qubits or resonators, which is passively protected against all single qubit quantum error channels through a combination of continuous driving and engineered dissipation. Photon losses are rapidly corrected through two-photon drive fields implemented with driven SQUID couplings, and dephasing from random potential fluctuations is heavily suppressed by the drive fields used to implement the multi-qubit Hamiltonian. Comparing our theoretical model to published noise estimates from recent experiments on flux and transmon qubits, we find that logical state coherence could be improved by a factor of forty or more compared to the individual qubit T1 and T2 using this technique.
ERIC Educational Resources Information Center
Welty, Gordon A.
The logic of the evaluation of educational and other action programs is discussed from a methodological viewpoint. However, no attempt is made to develop methods of evaluating programs. In Part I, the structure of an educational program is viewed as a system with three components--inputs, transformation of inputs into outputs, and outputs. Part II…
Metacomputation and logic programming
Abramov, S.M.
1992-03-01
This paper presents an approach to logic programming based on implementing reverse semantics of programming languages. The interpreter that implements reverse semantics is called a Universal Resolving Algorithm (URA). Implementation and methods for application of a URA are based on methods of metacomputation. 12 refs., 2 figs.
Temporal logics meet telerobotics
NASA Technical Reports Server (NTRS)
Rutten, Eric; Marce, Lionel
1989-01-01
The specificity of telerobotics being the presence of a human operator, decision assistance tools are necessary for the operator, especially in hostile environments. In order to reduce execution hazards due to a degraded ability for quick and efficient recovery of unexpected dangerous situations, it is of importance to have the opportunity, amongst others, to simulate the possible consequences of a plan before its actual execution, in order to detect these problematic situations. Hence the idea of providing the operator with a simulator enabling him to verify the temporal and logical coherence of his plans. Therefore, the power of logical formalisms is used for representation and deduction purposes. Starting from the class of situations that are represented, a STRIPS (the STanford Research Institute Problem Solver)-like formalism and its underlying logic are adapted to the simulation of plans of actions in time. The choice of a temporal logic enables to build a world representation, on which the effects of plans, grouping actions into control structures, will be transcribed by the simulation, resulting in a verdict and information about the plan's coherence.
Quantum probabilistic logic programming
NASA Astrophysics Data System (ADS)
Balu, Radhakrishnan
2015-05-01
We describe a quantum mechanics based logic programming language that supports Horn clauses, random variables, and covariance matrices to express and solve problems in probabilistic logic. The Horn clauses of the language wrap random variables, including infinite valued, to express probability distributions and statistical correlations, a powerful feature to capture relationship between distributions that are not independent. The expressive power of the language is based on a mechanism to implement statistical ensembles and to solve the underlying SAT instances using quantum mechanical machinery. We exploit the fact that classical random variables have quantum decompositions to build the Horn clauses. We establish the semantics of the language in a rigorous fashion by considering an existing probabilistic logic language called PRISM with classical probability measures defined on the Herbrand base and extending it to the quantum context. In the classical case H-interpretations form the sample space and probability measures defined on them lead to consistent definition of probabilities for well formed formulae. In the quantum counterpart, we define probability amplitudes on Hinterpretations facilitating the model generations and verifications via quantum mechanical superpositions and entanglements. We cast the well formed formulae of the language as quantum mechanical observables thus providing an elegant interpretation for their probabilities. We discuss several examples to combine statistical ensembles and predicates of first order logic to reason with situations involving uncertainty.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
2000-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard; Day, John H. (Technical Monitor)
2001-01-01
This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.
Development of beam leaded low power logic circuits
NASA Technical Reports Server (NTRS)
Smith, B. W.; Malone, F.
1972-01-01
The technologies of low power TTL and beam lead processing were merged into a single product family. This family offers the power and thermal advantages of low power(54L), while providing the additional reliability advantages of beam leads. The reduction in the power and heat levels also allows the system designer to take advantage, through beam lead, multichip assemblies, of increased package density to reduce system size and weight.
SOA-Based Optical Logic Circuit Development and Demonstration
2008-09-30
ridge using an AZ-5214 image-reversal resist photolithography to liftoff e-beam evaporated Ti/Pt (20/20 nm). A 450 nm SiO 2 hardmask was deposited... hardmask defined the adiabatic tapers, active ridge and trench, overlapping the Ti/Pt metal to form a dual mask, with the Ti/Pt intended as part of an ohmic...oxide hardmask remaining from the first etch, another 450 nm PECVD SiO, layer was deposited over the whole wafer, which conformally-coated the exposed
OptCircuit: An optimization based method for computational design of genetic circuits
Dasika, Madhukar S; Maranas, Costas D
2008-01-01
Background Recent years has witnessed an increasing number of studies on constructing simple synthetic genetic circuits that exhibit desired properties such as oscillatory behavior, inducer specific activation/repression, etc. It has been widely acknowledged that that task of building circuits to meet multiple inducer-specific requirements is a challenging one. This is because of the incomplete description of component interactions compounded by the fact that the number of ways in which one can chose and interconnect components, increases exponentially with the number of components. Results In this paper we introduce OptCircuit, an optimization based framework that automatically identifies the circuit components from a list and connectivity that brings about the desired functionality. Multiple literature sources are used to compile a comprehensive compilation of kinetic descriptions of promoter-protein pairs. The dynamics that govern the interactions between the elements of the genetic circuit are currently modeled using deterministic ordinary differential equations but the framework is general enough to accommodate stochastic simulations. The desired circuit response is abstracted as the maximization/minimization of an appropriately constructed objective function. Computational results for a toggle switch example demonstrate the ability of the framework to generate the complete list of circuit designs of varying complexity that exhibit the desired response. Designs identified for a genetic decoder highlight the ability of OptCircuit to suggest circuit configurations that go beyond the ones compatible with digital logic-based design principles. Finally, the results obtained from the concentration band detector example demonstrate the ability of OptCircuit to design circuits whose responses are contingent on the level of external inducer as well as pinpoint parameters for modification to rectify an existing (non-functional) biological circuit and restore
Addressing biological uncertainties in engineering gene circuits.
Zhang, Carolyn; Tsoi, Ryan; You, Lingchong
2016-04-18
Synthetic biology has grown tremendously over the past fifteen years. It represents a new strategy to develop biological understanding and holds great promise for diverse practical applications. Engineering of a gene circuit typically involves computational design of the circuit, selection of circuit components, and test and optimization of circuit functions. A fundamental challenge in this process is the predictable control of circuit function due to multiple layers of biological uncertainties. These uncertainties can arise from different sources. We categorize these uncertainties into incomplete quantification of parts, interactions between heterologous components and the host, or stochastic dynamics of chemical reactions and outline potential design strategies to minimize or exploit them.
Sandia ATM SONET Interface Logic
Kitta, Joseph P.
1994-07-21
SASIL is used to program the EPLD's (Erasable Programmable Logic Devices) and PAL's (Programmable Array Logic) that make up a large percentage of the Sandia ATM SONET Interface (OC3 version) for the INTEL Paragon.
Photonic encryption : modeling and functional analysis of all optical logic.
Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.
2004-10-01
With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in the photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay
Automatic ranging circuit for a digital panel meter
Mueller, Theodore R.; Ross, Harley H.
1976-01-01
This invention relates to a range changing circuit that operates in conjunction with a digital panel meter of fixed sensitivity. The circuit decodes the output of the panel meter and uses that information to change the gain of an input amplifier to the panel meter in order to insure that the maximum number of significant figures is always displayed in the meter. The circuit monitors five conditions in the meter and responds to any of four combinations of these conditions by means of logic elements to carry out the function of the circuit.
Conceptual Modeling via Logic Programming
1990-01-01
31 2.7 Approaches Other Than Logic Programming ............................. 33 2.7.1 L isp...Development Environment Needs ................................ 84 5.1.4 Alternative Logic Programming Implementation Approaches ......... 85 5.1.5 User... APPROACH and logic programming techniques. Section 2 The CMLP project consisted of three describes the task outputs. interrelated investi ations: 3
Conditional Logic and Primary Children.
ERIC Educational Resources Information Center
Ennis, Robert H.
Conditional logic, as interpreted in this paper, means deductive logic characterized by "if-then" statements. This study sought to investigate the knowledge of conditional logic possessed by primary children and to test their readiness to learn such concepts. Ninety students were designated the experimental group and participated in a…
1980-09-01
Equivalent GaAs MESFET Circuit Model 37 11 Hower’s Equivalent GaAs MESFET Circuit Model 38 12 Modified DC Equivalent Circuit Model of...I Truth Table for the GaAs MESFET Logic Gate of Figure 1 29 II Equivalent - Circuit Parameters of a GaAs MESFET with a 1 micron x 500 micron Gate 39...using Schottky diodes in the output buffer circuit . The number of diodes required is determined by the pinchoff voltage of the
Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell
NASA Astrophysics Data System (ADS)
Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng
2016-06-01
Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis
Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo
2015-03-25
A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain.
Pascal, Robert; Pross, Addy
2016-11-01
In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the 'regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both 'regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.
NASA Astrophysics Data System (ADS)
Pascal, Robert; Pross, Addy
2016-11-01
In this paper we propose a logical connection between the physical and biological worlds, one resting on a broader understanding of the stability concept. We propose that stability manifests two facets - time and energy, and that stability's time facet, expressed as persistence, is more general than its energy facet. That insight leads to the logical formulation of the Persistence Principle, which describes the general direction of material change in the universe, and which can be stated most simply as: nature seeks persistent forms. Significantly, the principle is found to express itself in two mathematically distinct ways: in the replicative world through Malthusian exponential growth, and in the `regular' physical/chemical world through Boltzmann's probabilistic considerations. By encompassing both `regular' and replicative worlds, the principle appears to be able to help reconcile two of the major scientific theories of the 19th century - the Second Law of Thermodynamics and Darwin's theory of evolution - within a single conceptual framework.
Nanomagnet Logic: Architectures, design, and benchmarking
NASA Astrophysics Data System (ADS)
Kurtz, Steven J.
Nanomagnet Logic (NML) is an emerging technology being studied as a possible replacement or supplementary device for Complimentary Metal-Oxide-Semiconductor (CMOS) Field-Effect Transistors (FET) by the year 2020. NML devices offer numerous potential advantages including: low energy operation, steady state non-volatility, radiation hardness and a clear path to fabrication and integration with CMOS. However, maintaining both low-energy operation and non-volatility while scaling from the device to the architectural level is non-trivial as (i) nearest neighbor interactions within NML circuits complicate the modeling of ensemble nanomagnet behavior and (ii) the energy intensive clock structures required for re-evaluation and NML's relatively high latency challenge its ability to offer system-level performance wins against other emerging nanotechnologies. Thus, further research efforts are required to model more complex circuits while also identifying circuit design techniques that balance low-energy operation with steady state non-volatility. In addition, further work is needed to design and model low-power on-chip clocks while simultaneously identifying application spaces where NML systems (including clock overhead) offer sufficient energy savings to merit their inclusion in future processors. This dissertation presents research advancing the understanding and modeling of NML at all levels including devices, circuits, and line clock structures while also benchmarking NML against both scaled CMOS and tunneling FETs (TFET) devices. This is accomplished through the development of design tools and methodologies for (i) quantifying both energy and stability in NML circuits and (ii) evaluating line-clocked NML system performance. The application of these newly developed tools improves the understanding of ideal design criteria (i.e., magnet size, clock wire geometry, etc.) for NML architectures. Finally, the system-level performance evaluation tool offers the ability to
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
1998-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
1998-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, heavy ion test results, and some total dose results.
Multi/infinite dimensional neural networks, multi/infinite dimensional logic theory.
Murthy, Garimella Rama
2005-06-01
A mathematical model of an arbitrary multi-dimensional neural network is developed and a convergence theorem for an arbitrary multi-dimensional neural network represented by a fully symmetric tensor is stated and proved. The input and output signal states of a multi-dimensional neural network/logic gate are related through an energy function, defined over the fully symmetric tensor (representing the connection structure of a multi-dimensional neural network). The inputs and outputs are related such that the minimum/maximum energy states correspond to the output states of the logic gate/neural network realizing a logic function. Similarly, a logic circuit consisting of the interconnection of logic gates, represented by a block symmetric tensor, is associated with a quadratic/higher degree energy function. Infinite dimensional logic theory is discussed through the utilization of infinite dimension/order tensors.
RSFQ logic devices; non-linear properties and experimental investigations
NASA Astrophysics Data System (ADS)
Mygind, Jesper
1998-05-01
Rapid Single Flux Quantum (RSFQ) logic has a great potential as fast digital and high frequency analog electronics. Several Logic/Memory base elements and integrated sub-systems in the RSFQ family have been devised and tested since the pioneering work in the mid 1980s by K. K. Likharev's group at Moscow State University [1,2]. It is argumented why the RSFQ digital circuits are superior to the voltage state family circuits, which were utilised in the first development of Josephson logic. Also the parameter space for operation of the 1-D RSFQ transmission line is discussed. Presently most RSFQ circuits are made with low-Tc superconductors using the now mature whole-wafer NbAlOxNb technology, which allows for large and densely packed integrated circuits. Recently, a few operational high-Tc RSFQ circuits have been reported. An important development within the last two years is the advent of general-purpose on-chip bit-by-bit verification test systems. Timing of RSFQ circuits and a few recent RSFQ "highlights" are briefly mentioned. Basically the RSFQ technology appears "ready" for widespread industrial use. One of the key components is the RSFQ transmission line, which can both generate and transmit SFQ pulses. In order to demonstrate the importance of the fluxon dynamics we discuss a new phenomenon observed in a parallel array of identical junctions. Steps with extremely low differential resistance in the I-V characteristic are found to be due to the self-induced magnetic field produced by the edge current fed to the array. The underlying mechanism is that the nonuniform field divides the moving fluxon into "domains" covering several (unit) cells. The experimental/numerical results illustrate practical and may be more fundamental limits to RSFQ electronics.
Commutation circuit for an HVDC circuit breaker
Premerlani, William J.
1981-01-01
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.
Commutation circuit for an HVDC circuit breaker
Premerlani, W.J.
1981-11-10
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components. 13 figs.
Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model
NASA Technical Reports Server (NTRS)
MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.
2005-01-01
A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.
Fuzzy forecasting based on fuzzy-trend logical relationship groups.
Chen, Shyi-Ming; Wang, Nai-Yi
2010-10-01
In this paper, we present a new method to predict the Taiwan Stock Exchange Capitalization Weighted Stock Index (TAIEX) based on fuzzy-trend logical relationship groups (FTLRGs). The proposed method divides fuzzy logical relationships into FTLRGs based on the trend of adjacent fuzzy sets appearing in the antecedents of fuzzy logical relationships. First, we apply an automatic clustering algorithm to cluster the historical data into intervals of different lengths. Then, we define fuzzy sets based on these intervals of different lengths. Then, the historical data are fuzzified into fuzzy sets to derive fuzzy logical relationships. Then, we divide the fuzzy logical relationships into FTLRGs for forecasting the TAIEX. Moreover, we also apply the proposed method to forecast the enrollments and the inventory demand, respectively. The experimental results show that the proposed method gets higher average forecasting accuracy rates than the existing methods.
Logic as Marr's Computational Level: Four Case Studies.
Baggio, Giosuè; van Lambalgen, Michiel; Hagoort, Peter
2015-04-01
We sketch four applications of Marr's levels-of-analysis methodology to the relations between logic and experimental data in the cognitive neuroscience of language and reasoning. The first part of the paper illustrates the explanatory power of computational level theories based on logic. We show that a Bayesian treatment of the suppression task in reasoning with conditionals is ruled out by EEG data, supporting instead an analysis based on defeasible logic. Further, we describe how results from an EEG study on temporal prepositions can be reanalyzed using formal semantics, addressing a potential confound. The second part of the article demonstrates the predictive power of logical theories drawing on EEG data on processing progressive constructions and on behavioral data on conditional reasoning in people with autism. Logical theories can constrain processing hypotheses all the way down to neurophysiology, and conversely neuroscience data can guide the selection of alternative computational level models of cognition.
The development of an interim generalized gate logic software simulator
NASA Technical Reports Server (NTRS)
Mcgough, J. G.; Nemeroff, S.
1985-01-01
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
A programming language for composable DNA circuits.
Phillips, Andrew; Cardelli, Luca
2009-08-06
Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.
A programmable heater control circuit for spacecraft
NASA Technical Reports Server (NTRS)
Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.
1994-01-01
Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.
Probabilistic Analysis of Localized DNA Hybridization Circuits.
Dalchau, Neil; Chandran, Harish; Gopalkrishnan, Nikhil; Phillips, Andrew; Reif, John
2015-08-21
Molecular devices made of nucleic acids can perform complex information processing tasks at the nanoscale, with potential applications in biofabrication and smart therapeutics. However, limitations in the speed and scalability of such devices in a well-mixed setting can significantly affect their performance. In this article, we propose designs for localized circuits involving DNA molecules that are arranged on addressable substrates and interact via hybridization reactions. We propose designs for localized elementary logic circuits, which we compose to produce more complex devices, including a circuit for computing the square root of a four bit number. We develop an efficient method for probabilistic model checking of localized circuits, which we implement within the Visual DSD design tool. We use this method to prove the correctness of our circuits with respect to their functional specifications and to analyze their performance over a broad range of local rate parameters. Specifically, we analyze the extent to which our localized designs can overcome the limitations of well-mixed circuits, with respect to speed and scalability. To provide an estimate of local rate parameters, we propose a biophysical model of localized hybridization. Finally, we use our analysis to identify constraints in the rate parameters that enable localized circuits to retain their advantages in the presence of unintended interferences between strands.
A reliable ground bounce noise reduction technique for nanoscale CMOS circuits
NASA Astrophysics Data System (ADS)
Sharma, Vijay Kumar; Pattanaik, Manisha
2015-11-01
Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.
Use of Fuzzy Logic Systems for Assessment of Primary Faults
NASA Astrophysics Data System (ADS)
Petrović, Ivica; Jozsa, Lajos; Baus, Zoran
2015-09-01
In electric power systems, grid elements are often subjected to very complex and demanding disturbances or dangerous operating conditions. Determining initial fault or cause of those states is a difficult task. When fault occurs, often it is an imperative to disconnect affected grid element from the grid. This paper contains an overview of possibilities for using fuzzy logic in an assessment of primary faults in the transmission grid. The tool for this task is SCADA system, which is based on information of currents, voltages, events of protection devices and status of circuit breakers in the grid. The function model described with the membership function and fuzzy logic systems will be presented in the paper. For input data, diagnostics system uses information of protection devices tripping, states of circuit breakers and measurements of currents and voltages before and after faults.
The formation of sense organs in Drosophila: a logical approach.
Ghysen, Alain; Thomas, René
2003-08-01
The genetic analysis of development has revealed the importance of small sets of interacting genes in most morphogenetic processes. The results of gene interactions have so far been examined intuitively. This approach is largely sufficient when one deals with simple interactions, a feedback circuit for example. As more components become involved, however, it is difficult to make sure that the intuitive approach gives a comprehensive view of the behaviour of the system. In this paper, we illustrate the use of a logical approach to describe the genetic circuit that underlies the singling out of sense organ precursor cells in Drosophila. We show how to apply logical modelling to a realistic problem, and how this approach allows an easy assessment of the dynamic properties of the system, i.e., of its possible evolutions and of its reactions to fluctuations and perturbations.
Bit-systolic arithmetic arrays using dynamic differential gallium arsenide circuits
NASA Technical Reports Server (NTRS)
Beagles, Grant; Winters, Kel; Eldin, A. G.
1992-01-01
A new family of gallium arsenide circuits for fine grained bit-systolic arithmetic arrays is introduced. This scheme combines features of two recent techniques of dynamic gallium arsenide FET logic and differential dynamic single-clock CMOS logic. The resulting circuits are fast and compact, with tightly constrained series FET propagation paths, low fanout, no dc power dissipation, and depletion FET implementation without level shifting diodes.
Circuit monitors powerline interruptions
NASA Technical Reports Server (NTRS)
Simmons, N. E.; Stricklen, J. O.
1977-01-01
Simple circuit when combined with pulse detector detects momentary interruptions of 400-cycle ac signal. Circuit has been used during shock and vibration testing of electronic hardware to determine if tests caused interruptions of normal circuit operation.
NASA Technical Reports Server (NTRS)
Dimeff, J.
1972-01-01
Electric circuit to measure frequency of repetitive sinusoidal or rectangular wave is presented. Components of electric circuit and method of operation are explained. Application of circuit as tachometer for automobile is discussed.
Surface confined assemblies and polymers for sensing and molecular logic
NASA Astrophysics Data System (ADS)
de Ruiter, Graham; Altman, Marc; Motiei, Leila; Lahav, Michal; van der Boom, Milko E.
2013-05-01
Since the development of molecule-based sensors and the introduction of molecules mimicking the behavior of the AND gate in solution by de Silva in 1993, molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. The molecular approach toward Boolean logic resulted in intriguing proofs of concepts in solution including logic gates, half-adders, multiplexers, and flip-flop logic circuits. Molecular assemblies can perform diverse logic tasks by reconfiguring their inputs. Our recent research activities focus on MBLC with electrochromic polymers and immobilized polypyridyl complexes on solid support. We have designed a series of coordination-based thin films that are formed linearly by stepwise wet-chemical deposition or by self-propagating molecular assembly. The electrochromic properties of these films can be used for (i) detecting various analytes in solution and in the air, (ii) MBLC, (iii) electron-transfer studies, and (iv) interlayers for efficient inverted bulk-heterojunction solar cells. Our concept toward MBLC with functionalized surfaces is applicable to electrochemical and chemical inputs coupled with optical readout. Using this approach, we demonstrated various logic architectures with redox-active functionalized surfaces. Electrochemically operated sequential logic systems (e.g., flip-flops), multi-valued logic, and multi-state memory have been designed, which can improve computational power without increasing spatial requirements. Applying multi-valued digits in data storage and information processing could exponentially increase memory capacity. Our approach is applicable to highly diverse electrochromic thin films that operate at practical voltages (< 1.5 V).
Black, Dolores Archuleta; Robinson, William H.; Wilcox, Ian Zachary; Limbrick, Daniel B.; Black, Jeffrey D.
2015-08-07
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. Likewise, an accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventional model based on one double-exponential source can be incomplete. Furthermore, a small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. As a result, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.
Black, Dolores Archuleta; Robinson, William H.; Wilcox, Ian Zachary; ...
2015-08-07
Single event effects (SEE) are a reliability concern for modern microelectronics. Bit corruptions can be caused by single event upsets (SEUs) in the storage cells or by sampling single event transients (SETs) from a logic path. Likewise, an accurate prediction of soft error susceptibility from SETs requires good models to convert collected charge into compact descriptions of the current injection process. This paper describes a simple, yet effective, method to model the current waveform resulting from a charge collection event for SET circuit simulations. The model uses two double-exponential current sources in parallel, and the results illustrate why a conventionalmore » model based on one double-exponential source can be incomplete. Furthermore, a small set of logic cells with varying input conditions, drive strength, and output loading are simulated to extract the parameters for the dual double-exponential current sources. As a result, the parameters are based upon both the node capacitance and the restoring current (i.e., drive strength) of the logic cell.« less
Feasibility study for a generalized gate logic software simulator
NASA Technical Reports Server (NTRS)
Mcgough, J. G.
1983-01-01
Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.
Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs
NASA Astrophysics Data System (ADS)
Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.
2015-03-01
This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.
Substructural Logical Specifications
2012-11-14
a more natural correspondence with our physical intuitions about consumable resources. Linear conjunction A ⊗ B (“A tensor B”) represents the...sketch a radically different, vaguely Feynman - diagram-inspired, way of presenting traces in Figure 4.14. Resources are the edges in the DAG and steps or...70th Birthday, volume 17 of Studies in Logic. College Publications, 2008. 3.3.3, 4.1.2, 4.7.3 [Pfe12a] Frank Pfenning. Lecture notes on backtracking
Programmable Logic Application Notes
NASA Technical Reports Server (NTRS)
Katz, Richard
1999-01-01
This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter the focus is on some experimental data on low voltage drop out regulators to support mixed 5 and 3.3 volt systems. A discussion of the Small Explorer WIRE spacecraft will also be given. Lastly, we show take a first look at robust state machines in Hardware Description Languages (VHDL) and their use in critical systems. If you have information that you would like to submit or an area you would like discussed or researched, please give me a call or e-mail.
Programming a Pavlovian-like conditioning circuit in Escherichia coli
NASA Astrophysics Data System (ADS)
Zhang, Haoqian; Lin, Min; Shi, Handuo; Ji, Weiyue; Huang, Longwen; Zhang, Xiaomeng; Shen, Shan; Gao, Rencheng; Wu, Shuke; Tian, Chengzhe; Yang, Zhenglin; Zhang, Guosheng; He, Siheng; Wang, Hao; Saw, Tiffany; Chen, Yiwei; Ouyang, Qi
2014-01-01
Synthetic genetic circuits are programmed in living cells to perform predetermined cellular functions. However, designing higher-order genetic circuits for sophisticated cellular activities remains a substantial challenge. Here we program a genetic circuit that executes Pavlovian-like conditioning, an archetypical sequential-logic function, in Escherichia coli. The circuit design is first specified by the subfunctions that are necessary for the single simultaneous conditioning, and is further genetically implemented using four function modules. During this process, quantitative analysis is applied to the optimization of the modules and fine-tuning of the interconnections. Analogous to classical Pavlovian conditioning, the resultant circuit enables the cells to respond to a certain stimulus only after a conditioning process. We show that, although the conditioning is digital in single cells, a dynamically progressive conditioning process emerges at the population level. This circuit, together with its rational design strategy, is a key step towards the implementation of more sophisticated cellular computing.
Design infrastructure for Rapid Single Flux Quantum circuits
NASA Astrophysics Data System (ADS)
Toepfer, Hannes; Ortlepp, Thomas
2009-11-01
Cryoelectronic integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology are promising candidates for realizing systems exhibiting very high performance in combination with very low-power consumption. Like other superconductive logic circuits, they are characterized by a high switching speed. Their unique feature consists in the particular representation of binary information by means of short transient voltage pulses. The development of RSFQ circuits and systems requires a comprehensive design approach, supported by appropriate tools. Within the recent years, a dedicated design infrastructure has been developed in Europe in close association with a foundry for digital RSFQ integrated circuits. As a result, RSFQ technology has matured to such a level that engineering efforts enable the development of integrated circuits. In the contribution, the basic features of the RSFQ circuit design are addressed within the context of technical and infrastructural issues of implementation from a European perspective.
FPGA-based gating and logic for multichannel single photon counting
Pooser, Raphael C; Earl, Dennis Duncan; Evans, Philip G; Williams, Brian P; Schaake, Jason; Humble, Travis S
2012-01-01
We present results characterizing multichannel InGaAs single photon detectors utilizing gated passive quenching circuits (GPQC), self-differencing techniques, and field programmable gate array (FPGA)-based logic for both diode gating and coincidence counting. Utilizing FPGAs for the diode gating frontend and the logic counting backend has the advantage of low cost compared to custom built logic circuits and current off-the-shelf detector technology. Further, FPGA logic counters have been shown to work well in quantum key distribution (QKD) test beds. Our setup combines multiple independent detector channels in a reconfigurable manner via an FPGA backend and post processing in order to perform coincidence measurements between any two or more detector channels simultaneously. Using this method, states from a multi-photon polarization entangled source are detected and characterized via coincidence counting on the FPGA. Photons detection events are also processed by the quantum information toolkit for application testing (QITKAT)
Fine-Grained Power Gating Based on the Controlling Value of Logic Elements
NASA Astrophysics Data System (ADS)
Chen, Lei; Horiyama, Takashi; Nakamura, Yuichi; Kimura, Shinji
Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
pH-programmable DNA logic arrays powered by modular DNAzyme libraries.
Elbaz, Johann; Wang, Fuan; Remacle, Francoise; Willner, Itamar
2012-12-12
Nature performs complex information processing circuits, such the programmed transformations of versatile stem cells into targeted functional cells. Man-made molecular circuits are, however, unable to mimic such sophisticated biomachineries. To reach these goals, it is essential to construct programmable modular components that can be triggered by environmental stimuli to perform different logic circuits. We report on the unprecedented design of artificial pH-programmable DNA logic arrays, constructed by modular libraries of Mg(2+)- and UO(2)(2+)-dependent DNAzyme subunits and their substrates. By the appropriate modular design of the DNA computation units, pH-programmable logic arrays of various complexities are realized, and the arrays can be erased, reused, and/or reprogrammed. Such systems may be implemented in the near future for nanomedical applications by pH-controlled regulation of cellular functions or may be used to control biotransformations stimulated by bacteria.
Realization of a quantum Hamiltonian Boolean logic gate on the Si(001):H surface.
Kolmer, Marek; Zuzak, Rafal; Dridi, Ghassen; Godlewski, Szymon; Joachim, Christian; Szymonski, Marek
2015-08-07
The design and construction of the first prototypical QHC (Quantum Hamiltonian Computing) atomic scale Boolean logic gate is reported using scanning tunnelling microscope (STM) tip-induced atom manipulation on an Si(001):H surface. The NOR/OR gate truth table was confirmed by dI/dU STS (Scanning Tunnelling Spectroscopy) tracking how the surface states of the QHC quantum circuit on the Si(001):H surface are shifted according to the input logical status.
NASA Technical Reports Server (NTRS)
Canaris, J.
1991-01-01
A new logic family, which is immune to single event upsets, is described. Members of the logic family are capable of recovery, regardless of the shape of the upsetting event. Glitch propagation from an upset node is also blocked. Logic diagrams for an Inverter, Nor, Nand, and Complex Gates are provided. The logic family can be implemented in a standard, commercial CMOS process with no additional masks. DC, transient, static power, upset recovery and layout characteristics of the new family, based on a commercial 1 micron CMOS N-Well process, are described.
New elements of the RSFQ logic family
Mukhanov, O.A. ); Polonsky, S.V.; Semenov, V.K. )
1991-03-01
Elements of the RSFQ logic/memory family have already reached operation frequency as large as 100 GHz and have a good chance to enter a sub-terahertz clock frequency range. Their parameter margins are as wide as {plus minus}25 + 30%, even one bit gates posses flip-flop features, and can be naturally self-times. This paper reports on RSFQ elements (OR-AND, NOR-AND), half adder, mutiplexer, demultiplexer, and shift registers are presented. Operation of these gates have been studied with the help of the Personal Superconductor Circuit Analyzer (PSCAN) within the standard RSJ model of Josephson junctions. Parameter margins and other performance limits of the new elements are thoroughly investigated.
Logic elements for reactor period meter
McDowell, William P.; Bobis, James P.
1976-01-01
Logic elements are provided for a reactor period meter trip circuit. For one element, first and second inputs are applied to first and second chopper comparators, respectively. The output of each comparator is O if the input applied to it is greater than or equal to a trip level associated with each input and each output is a square wave of frequency f if the input applied to it is less than the associated trip level. The outputs of the comparators are algebraically summed and applied to a bandpass filter tuned to f. For another element, the output of each comparator is applied to a bandpass filter which is tuned to f to give a sine wave of frequency f. The outputs of the filters are multiplied by an analog multiplier whose output is 0 if either input is 0 and a sine wave of frequency 2f if both inputs are a frequency f.
Parallel algorithm strategies for circuit simulation.
Thornquist, Heidi K.; Schiek, Richard Louis; Keiter, Eric Richard
2010-01-01
Circuit simulation tools (e.g., SPICE) have become invaluable in the development and design of electronic circuits. However, they have been pushed to their performance limits in addressing circuit design challenges that come from the technology drivers of smaller feature scales and higher integration. Improving the performance of circuit simulation tools through exploiting new opportunities in widely-available multi-processor architectures is a logical next step. Unfortunately, not all traditional simulation applications are inherently parallel, and quickly adapting mature application codes (even codes designed to parallel applications) to new parallel paradigms can be prohibitively difficult. In general, performance is influenced by many choices: hardware platform, runtime environment, languages and compilers used, algorithm choice and implementation, and more. In this complicated environment, the use of mini-applications small self-contained proxies for real applications is an excellent approach for rapidly exploring the parameter space of all these choices. In this report we present a multi-core performance study of Xyce, a transistor-level circuit simulation tool, and describe the future development of a mini-application for circuit simulation.
Fuzzy logic and coarse coding using programmable logic devices
NASA Astrophysics Data System (ADS)
Brooks, Geoffrey
2009-05-01
Naturally-occurring sensory signal processing algorithms, such as those that inspired fuzzy-logic control, can be integrated into non-naturally-occurring high-performance technology, such as programmable logic devices, to realize novel bio-inspired designs. Research is underway concerning an investigation into using field programmable logic devices (FPLD's) to implement fuzzy logic sensory processing. A discussion is provided concerning the commonality between bio-inspired fuzzy logic algorithms and coarse coding that is prevalent in naturally-occurring sensory systems. Undergraduate design projects using fuzzy logic for an obstacle-avoidance robot has been accomplished at our institution and other places; numerous other successful fuzzy logic applications can be found as well. The long-term goal is to leverage such biomimetic algorithms for future applications. This paper outlines a design approach for implementing fuzzy-logic algorithms into reconfigurable computing devices. This paper is presented in an effort to connect with others who may be interested in collaboration as well as to establish a starting point for future research.
Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell.
Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng
2016-07-07
Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.
Parsing with logical variables (logic-based programming systems)
Finin, T.W.; Stone Palmer, M.
1983-01-01
Logic based programming systems have enjoyed an increasing popularity in applied AI work in the last few years. One of the contributions to computational linguistics made by the logic programming paradigm has been the definite clause grammar. In comparing DCGS with previous parsing mechanisms such as ATNS, certain clear advantages are seen. The authors feel that the most important of these advantages are due to the use of logical variables with unification as the fundamental operation on them. To illustrate the power of the logical variable, they have implemented an experimental atn system which treats atn registers as logical variables and provides a unification operation over them. They aim to simultaneously encourage the use of the powerful mechanisms available in DCGS and demonstrate that some of these techniques can be captured without reference to a resolution theorem prover. 14 references.
NASA Technical Reports Server (NTRS)
2005-01-01
A new all-electronic Particle Image Velocimetry technique that can efficiently map high speed gas flows has been developed in-house at the NASA Lewis Research Center. Particle Image Velocimetry is an optical technique for measuring the instantaneous two component velocity field across a planar region of a seeded flow field. A pulsed laser light sheet is used to illuminate the seed particles entrained in the flow field at two instances in time. One or more charged coupled device (CCD) cameras can be used to record the instantaneous positions of particles. Using the time between light sheet pulses and determining either the individual particle displacements or the average displacement of particles over a small subregion of the recorded image enables the calculation of the fluid velocity. Fuzzy logic minimizes the required operator intervention in identifying particles and computing velocity. Using two cameras that have the same view of the illumination plane yields two single exposure image frames. Two competing techniques that yield unambiguous velocity vector direction information have been widely used for reducing the single-exposure, multiple image frame data: (1) cross-correlation and (2) particle tracking. Correlation techniques yield averaged velocity estimates over subregions of the flow, whereas particle tracking techniques give individual particle velocity estimates. For the correlation technique, the correlation peak corresponding to the average displacement of particles across the subregion must be identified. Noise on the images and particle dropout result in misidentification of the true correlation peak. The subsequent velocity vector maps contain spurious vectors where the displacement peaks have been improperly identified. Typically these spurious vectors are replaced by a weighted average of the neighboring vectors, thereby decreasing the independence of the measurements. In this work, fuzzy logic techniques are used to determine the true
Simple Autonomous Chaotic Circuits
NASA Astrophysics Data System (ADS)
Piper, Jessica; Sprott, J.
2010-03-01
Over the last several decades, numerous electronic circuits exhibiting chaos have been proposed. Non-autonomous circuits with as few as two components have been developed. However, the operation of such circuits relies on the non-ideal behavior of the devices used, and therefore the circuit equations can be quite complex. In this paper, we present two simple autonomous chaotic circuits using only opamps and linear passive components. The circuits each use one opamp as a comparator, to provide a signum nonlinearity. The chaotic behavior is robust, and independent of nonlinearities in the passive components. Moreover, the circuit equations are among the algebraically simplest chaotic systems yet constructed.
Rapidly Reconfigurable All-Optical Universal Logic Gates
Goddard, L L; Kallman, J S; Bond, T C
2006-06-21
We present designs and simulations for a highly cascadable, rapidly reconfigurable, all-optical, universal logic gate. We will discuss the gate's expected performance, e.g. speed, fanout, and contrast ratio, as a function of the device layout and biasing conditions. The gate is a three terminal on-chip device that consists of: (1) the input optical port, (2) the gate selection port, and (3) the output optical port. The device can be built monolithically using a standard multiple quantum well graded index separate confinement heterostructure laser configuration. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog electrical or optical signal at the gate selection port. Specifically, the same gate can be selected to execute one of the 2 basic unary operations (NOT or COPY), or one of the 6 binary operations (OR, XOR, AND, NOR, XNOR, or NAND), or one of the many logic operations involving more than two inputs. The speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal modulation speed of a laser, which can be on the order of tens of GHz. The reprogrammable nature of the universal gate offers maximum flexibility and interchangeability for the end user since the entire application of a photonic integrated circuit built from cascaded universal logic gates can be changed simply by adjusting the gate selection port signals.
NASA Technical Reports Server (NTRS)
Cleaveland, Rance; Luettgen, Gerald; Bushnell, Dennis M. (Technical Monitor)
2002-01-01
This paper presents the Logical Process Calculus (LPC), a formalism that supports heterogeneous system specifications containing both operational and declarative subspecifications. Syntactically, LPC extends Milner's Calculus of Communicating Systems with operators from the alternation-free linear-time mu-calculus (LT(mu)). Semantically, LPC is equipped with a behavioral preorder that generalizes Hennessy's and DeNicola's must-testing preorder as well as LT(mu's) satisfaction relation, while being compositional for all LPC operators. From a technical point of view, the new calculus is distinguished by the inclusion of: (1) both minimal and maximal fixed-point operators and (2) an unimple-mentability predicate on process terms, which tags inconsistent specifications. The utility of LPC is demonstrated by means of an example highlighting the benefits of heterogeneous system specification.
Borresen, Jon; Lynch, Stephen
2012-01-01
In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034
NASA Technical Reports Server (NTRS)
Simon, R. A.
1986-01-01
Electrical properties of solenoids imitated for tests of control circuits. Simulation circuit imitates voltage and current responses of two engine-controlling solenoids. Used in tests of programs of digital engine-control circuits, also provides electronic interface with circuits imitating electrical properties of pressure sensors and linear variable-differential transformers. Produces voltages, currents, delays, and discrete turnon and turnoff signals representing operation of solenoid in engine-control relay. Many such circuits used simulating overall engine circuitry.
Ultra-low-power carbon nanotube FET-based quaternary logic gates
NASA Astrophysics Data System (ADS)
Sharifi, Fazel; Moaiyeri, Mohammad Hossein; Navi, Keivan; Bagherzadeh, Nader
2016-09-01
This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.
Quantum circuits for OR and AND of ORs
NASA Astrophysics Data System (ADS)
Barnum, Howard; Bernstein, Herbert J.; Spector, Lee
2000-11-01
We give the first quantum circuit for computing f(0) OR f(1) more reliably than is classically possible with a single evaluation of the function. OR therefore joins XOR (i.e. parity, f(0)⊕f(1)) to give the full set of logical connectives (up to relabelling of inputs and outputs) for which there is quantum speedup.
Evaluation performance of digital integrated circuits while exposed to radiation
NASA Astrophysics Data System (ADS)
Barbashov, V. M.; Trushkin, N. S.
2016-10-01
The methods of functional-logical simulation of digital integrated circuits (ICs) exposed to radiation are observed. It is shown that in a number of cases functional and electrical deterioration of ICs performances have both deterministic and non-deterministic nature. Methods for simulating IC failure exposed to radiation based on the model of fuzzy digital machine and Brauer probabilistic reliability machine are proposed.
Kronberg, James W.
1992-01-01
A sequential power-up circuit for starting several electrical load elements in series to avoid excessive current surge, comprising a voltage ramp generator and a set of voltage comparators, each comparator having a different reference voltage and interfacing with a switch that is capable of turning on one of the load elements. As the voltage rises, it passes the reference voltages one at a time and causes the switch corresponding to that voltage to turn on its load element. The ramp is turned on and off by a single switch or by a logic-level electrical signal. The ramp rate for turning on the load element is relatively slow and the rate for turning the elements off is relatively fast. Optionally, the duration of each interval of time between the turning on of the load elements is programmable.
Logic, reasoning, and verbal behavior
Terrell, Dudley J.; Johnston, J. M.
1989-01-01
This paper analyzes the traditional concepts of logic and reasoning from the perspective of radical behaviorism and in the terms of Skinner's treatment of verbal behavior. The topics covered in this analysis include the proposition, premises and conclusions, logicality and rules, and deductive and inductive reasoning. PMID:22478015
Zapatrin, R.R.
1992-02-01
Given a finite ortholattice L, the *-semigroup is explicitly built whose annihilator ortholattice is isomorphic to L. Thus, it is shown that any finite quantum logic is the additive part of a binary logic. Some areas of possible applications are outlined. 7 refs.
Programmable Logic Controllers. Teacher Edition.
ERIC Educational Resources Information Center
Rauh, Bob; Kaltwasser, Stan
These materials were developed for a seven-unit secondary or postsecondary education course on programmable logic controllers (PLCs) that treats most of the skills needed to work effectively with PLCs as programming skills. The seven units of the course cover the following topics: fundamentals of programmable logic controllers; contracts, timers,…
Logic and the National Curriculum.
ERIC Educational Resources Information Center
Nelson, David
2000-01-01
Reviews the historic relationship between logic and the mathematics curriculum. Proposes a list of logical elements for modern school mathematics. Checks the current national curriculum against this list and finds it to be deficient, especially in relation to the development of ideas of proof. Presents arguments for reform. (Contains 29…
Biosensors with Built-In Biomolecular Logic Gates for Practical Applications
Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh
2014-01-01
Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423
Reconfigurable magnetic logic combined with non-volatile memory in silicon
NASA Astrophysics Data System (ADS)
Luo, Zhaochu; Zhang, Xiaozhong
Silicon-based complementary metal-oxide-semiconductor (CMOS) transistors have achieved great success and become the mainstream of integrated logic circuits. However, the traditional pathway to enhance computational performance and decrease cost by continuous miniaturization is approaching its fundamental limits. The recent emergence of magnetic logic devices, especially magnetic-field-based semiconductor logic devices, shows promise for surpassing the development limits of CMOS logic and arouses profound attentions. Based on our Si based magnetoresistance (MR) device, we proposed a Si based reconfigurable magnetic logic device by coupling nonlinear transport effect and Hall effect in Si, which could do all four basic Boolean logic operations including AND, OR, NOR and NAND combined with non-volatile memory. Further, we developed a Si based current-mode magnetic logic device, which allowed direct communication between different logic devices by current-induced magnetization switch effect without external intermediate magnetic-electric converters. This may result in a memory-logic integrated system leading to a non von Neumann computer.
Weighted Automata and Weighted Logics
NASA Astrophysics Data System (ADS)
Droste, Manfred; Gastin, Paul
In automata theory, a fundamental result of Büchi and Elgot states that the recognizable languages are precisely the ones definable by sentences of monadic second order logic. We will present a generalization of this result to the context of weighted automata. We develop syntax and semantics of a quantitative logic; like the behaviors of weighted automata, the semantics of sentences of our logic are formal power series describing ‘how often’ the sentence is true for a given word. Our main result shows that if the weights are taken in an arbitrary semiring, then the behaviors of weighted automata are precisely the series definable by sentences of our quantitative logic. We achieve a similar characterization for weighted Büchi automata acting on infinite words, if the underlying semiring satisfies suitable completeness assumptions. Moreover, if the semiring is additively locally finite or locally finite, then natural extensions of our weighted logic still have the same expressive power as weighted automata.
Power optimization in logic isomers
NASA Technical Reports Server (NTRS)
Panwar, Ramesh; Rennels, David; Alkalaj, Leon
1993-01-01
Logic isomers are labeled, 2-isomorphic graphs that implement the same logic function. Logic isomers may have significantly different power requirements even though they have the same number of transistors in the implementation. The power requirements of the isomers depend on the transition activity of the input signals. The power requirements of isomorphic graph isomers of n-input NAND and NOR gates are shown. Choosing the less power-consuming isomer instead of the others can yield significant power savings. Experimental results on a ripple-carry adder are presented to show that the implementation using the least power-consuming isomers requires approximately 10 percent less power than the implementation using the most power-consuming isomers. Simulations of other random logic designs also confirm that designs using less power-consuming isomers can reduce the logic power demand by approximately 10 percent as compared to designs using more power-consuming isomers.
Spintronic logic design methodology based on spin Hall effect-driven magnetic tunnel junctions
NASA Astrophysics Data System (ADS)
Kang, Wang; Wang, Zhaohao; Zhang, Youguang; Klein, Jacques-Olivier; Lv, Weifeng; Zhao, Weisheng
2016-02-01
Conventional complementary metal-oxide-semiconductor (CMOS) technology is now approaching its physical scaling limits to enable Moore’s law to continue. Spintronic devices, as one of the potential alternatives, show great promise to replace CMOS technology for next-generation low-power integrated circuits in nanoscale technology nodes. Until now, spintronic memory has been successfully commercialized. However spintronic logic still faces many critical challenges (e.g. direct cascading capability and small operation gain) before it can be practically applied. In this paper, we propose a standard complimentary spintronic logic (CSL) design methodology to form a CMOS-like logic design paradigm. Using the spin Hall effect (SHE)-driven magnetic tunnel junction (MTJ) device as an example, we demonstrate CSL implementation, functionality and performance. This logic family provides a unified design methodology for spintronic logic circuits and partly solves the challenges of direct cascading capability and small operation gain in the previously proposed spintronic logic designs. By solving a modified Landau-Lifshitz-Gilbert equation, the magnetization dynamics in the free layer of the MTJ is theoretically described and a compact electrical model is developed. With this electrical model, numerical simulations have been performed to evaluate the functionality and performance of the proposed CSL design. Simulation results demonstrate that the proposed CSL design paradigm is rather promising for low-power logic computing.
Effects of smoke on functional circuits
Tanaka, T.J.
1997-10-01
Nuclear power plants are converting to digital instrumentation and control systems; however, the effects of abnormal environments such as fire and smoke on such systems are not known. There are no standard tests for smoke, but previous smoke exposure tests at Sandia National Laboratories have shown that digital communications can be temporarily interrupted during a smoke exposure. Another concern is the long-term corrosion of metals exposed to the acidic gases produced by a cable fire. This report documents measurements of basic functional circuits during and up to 1 day after exposure to smoke created by burning cable insulation. Printed wiring boards were exposed to the smoke in an enclosed chamber for 1 hour. For high-resistance circuits, the smoke lowered the resistance of the surface of the board and caused the circuits to short during the exposure. These circuits recovered after the smoke was vented. For low-resistance circuits, the smoke caused their resistance to increase slightly. A polyurethane conformal coating substantially reduced the effects of smoke. A high-speed digital circuit was unaffected. A second experiment on different logic chip technologies showed that the critical shunt resistance that would cause failure was dependent on the chip technology and that the components used in the smoke exposures were some of the most smoke tolerant. The smoke densities in these tests were high enough to cause changes in high impedance (resistance) circuits during exposure, but did not affect most of the other circuits. Conformal coatings and the characteristics of chip technologies should be considered when designing circuitry for nuclear power plant safety systems, which must be highly reliable under a variety of operating and accident conditions. 10 refs., 34 figs., 18 tabs.
G4-FETs as Universal and Programmable Logic Gates
NASA Technical Reports Server (NTRS)
Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin
2007-01-01
An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.
Generalized Majority Logic Criterion to Analyze the Statistical Strength of S-Boxes
NASA Astrophysics Data System (ADS)
Hussain, Iqtadar; Shah, Tariq; Gondal, Muhammad Asif; Mahmood, Hasan
2012-05-01
The majority logic criterion is applicable in the evaluation process of substitution boxes used in the advanced encryption standard (AES). The performance of modified or advanced substitution boxes is predicted by processing the results of statistical analysis by the majority logic criteria. In this paper, we use the majority logic criteria to analyze some popular and prevailing substitution boxes used in encryption processes. In particular, the majority logic criterion is applied to AES, affine power affine (APA), Gray, Lui J, residue prime, S8 AES, Skipjack, and Xyi substitution boxes. The majority logic criterion is further extended into a generalized majority logic criterion which has a broader spectrum of analyzing the effectiveness of substitution boxes in image encryption applications. The integral components of the statistical analyses used for the generalized majority logic criterion are derived from results of entropy analysis, contrast analysis, correlation analysis, homogeneity analysis, energy analysis, and mean of absolute deviation (MAD) analysis.
NASA Technical Reports Server (NTRS)
Johnson, Steven D.; Byers, Jerry W.; Martin, James A.
2012-01-01
A method has been developed for continuous cell voltage balancing for rechargeable batteries (e.g. lithium ion batteries). A resistor divider chain is provided that generates a set of voltages representing the ideal cell voltage (the voltage of each cell should be as if the cells were perfectly balanced). An operational amplifier circuit with an added current buffer stage generates the ideal voltage with a very high degree of accuracy, using the concept of negative feedback. The ideal voltages are each connected to the corresponding cell through a current- limiting resistance. Over time, having the cell connected to the ideal voltage provides a balancing current that moves the cell voltage very close to that ideal level. In effect, it adjusts the current of each cell during charging, discharging, and standby periods to force the cell voltages to be equal to the ideal voltages generated by the resistor divider. The device also includes solid-state switches that disconnect the circuit from the battery so that it will not discharge the battery during storage. This solution requires relatively few parts and is, therefore, of lower cost and of increased reliability due to the fewer failure modes. Additionally, this design uses very little power. A preliminary model predicts a power usage of 0.18 W for an 8-cell battery. This approach is applicable to a wide range of battery capacities and voltages.
Hidden circuits and argumentation
NASA Astrophysics Data System (ADS)
Leinonen, Risto; Kesonen, Mikko H. P.; Hirvonen, Pekka E.
2016-11-01
Despite the relevance of DC circuits in everyday life and schools, they have been shown to cause numerous learning difficulties at various school levels. In the course of this article, we present a flexible method for teaching DC circuits at lower secondary level. The method is labelled as hidden circuits, and the essential idea underlying hidden circuits is in hiding the actual wiring of DC circuits, but to make their behaviour evident for pupils. Pupils are expected to find out the wiring of the circuit which should enhance their learning of DC circuits. We present two possible ways to utilise hidden circuits in a classroom. First, they can be used to test and enhance pupils’ conceptual understanding when pupils are expected to find out which one of the offered circuit diagram options corresponds to the actual circuit shown. This method aims to get pupils to evaluate the circuits holistically rather than locally, and as a part of that aim this method highlights any learning difficulties of pupils. Second, hidden circuits can be used to enhance pupils’ argumentation skills with the aid of argumentation sheet that illustrates the main elements of an argument. Based on the findings from our co-operating teachers and our own experiences, hidden circuits offer a flexible and motivating way to supplement teaching of DC circuits.
NASA Astrophysics Data System (ADS)
Naggary, Schabnam; Shihab, Mohammed; Atteln, Frank; Megahed, Mustafa; Brinkmann, Ralf Peter
2013-09-01
Capacitively coupled radio frequency discharges are widely used in the semiconductor processing industry for thin film deposition and etching. Thus the evaluation of the ion energy distribution function (IEDF) is of paramount importance for industrial applications. Spatially and temporally resolved CCP models are generally computationally expensive leading to reduced applicability of these models for industrial optimization. In order to reduce the simulation time, as an alternative method, we use equivalent circuits based on a global model to characterize the plasma bulk and provide the needed input parameters for a hybrid sheath model [ 1 , 2 , 3 ] . The overall computational time to obtain time averaged IEDFs lies within seconds, hence the concept is very attractive for industrial scanning and optimization. In order to assess the applicability of this novel approach the results are compared with those of commercial multi-physics software CFD-ACE+ in 2 and 3 dimensions. Our investigation demonstrates the feasibility of the compromise between short simulation times and accurate calculation of spatially resolved IEDF. The authors acknowledge support by the ESI Group, DFG via SFB-TR87, and the Ruhr-University Research School.
NASA Astrophysics Data System (ADS)
Naused, Barbara A.; Samson, Mark L.; Schwab, Daniel J.; Gilbert, Barry K.
Various GaAs transistor and gate technologies that have been developed since 1980 are analyzed. The characteristics of GaAs logic gates and ICs and the buffered FET logic, Shottky diode FET logic, direct coupled FET logic, and heterojunction integrated injection logic used to implement GaAs gate arrays of LSI complexity are described. The use of digital GaAs in a complex target signal processor, the Advanced Onboard Signal Processor (AOSP), is studied. Data from the testing of GaAs components for the AOSP at the wafer probe, package, and assembled circuit board levels are examined.
LSI/VLSI Ion Implanted GaAs IC (Integrated Circuits) Processing
1981-02-01
circuits employing depletion mode MESFETs . The highlight of the first quarter is the successful operation of the 8 x 8 bit parallel multiplier (1008...fully operational circuits was also high, 15%. An interesting observation is that the dislocation density of the LEC substrate determined by etch pit...at 5:1. Figure 5.2-6 shows an * improved version of the 2 level diode logic gate which would allow an - implementation of complex circuits without
Synthesis of energy-efficient counters implemented in PLD circuits
NASA Astrophysics Data System (ADS)
Kulisz, Józef; Nawrot, Radosław; Kania, Dariusz
2016-12-01
The paper presents a comparison of four methods of implementing sequential circuits in Programmable Logic Devices in respect of dissipated power. Objective of the research was to investigate influence of different methods of "disabling" the clock signal on the dynamic power consumed by the circuit. The comparison is carried out using simple counter circuits, i. e. circuits the algorithm of which is described by linear graphs. However, the presented considerations are general, and can be applied to any sequential circuit. Results of simulation tests show that the method based on clock gating is the most efficient one, and it leads to significant reduction of the dissipated dynamic power. The authors also propose a simple modification of global clock network structures, to facilitate clock gating.
Single Circuit Parallel Computing with Phonons through Magneto-acoustics
NASA Astrophysics Data System (ADS)
Sklan, Sophia; Grossman, Jeffrey
2013-03-01
Phononic computing - the use of (typically thermal) vibrations for information processing - is a nascent technology; its capabilities are still being discovered. We analyze an alternative form of phononic computing inspired by optical, rather than electronic, computing. Using the acoustic Faraday effect, we design a phonon gyrator and thereby a means of performing computation through the manipulation of polarization in transverse phonon currents. Moreover, we establish that our gyrators act as generalized transistors and can construct digital logic gates. Exploiting the wave nature of phonons and the similarity of our logic gates, we demonstrate parallel computation within a single circuit, an effect presently unique to phonons. Finally, a generic method of designing these parallel circuits is introduced and used to analyze the feasibility of magneto-acoustic materials in realizing these circuits. This material is based upon work supported by the National Science Foundation Graduate Research Fellowship under Grant No. 1122374.
NASA Astrophysics Data System (ADS)
Hayashi, Kenta; Gotoda, Hiroshi; Gentili, Pier Luigi
2016-05-01
The convective motions within a solution of a photochromic spiro-oxazine being irradiated by UV only on the bottom part of its volume, give rise to aperiodic spectrophotometric dynamics. In this paper, we study three nonlinear properties of the aperiodic time series: permutation entropy, short-term predictability and long-term unpredictability, and degree distribution of the visibility graph networks. After ascertaining the extracted chaotic features, we show how the aperiodic time series can be exploited to implement all the fundamental two-inputs binary logic functions (AND, OR, NAND, NOR, XOR, and XNOR) and some basic arithmetic operations (half-adder, full-adder, half-subtractor). This is possible due to the wide range of states a nonlinear system accesses in the course of its evolution. Therefore, the solution of the convective photochemical oscillator results in hardware for chaos-computing alternative to conventional complementary metal-oxide semiconductor-based integrated circuits.
Kral, M J
1994-01-01
Although suicide is not viewed as a mental disorder per se, it is viewed by many if not most clinicians, researchers, and lay people as a real or natural symptom of depression. It is at least most typically seen as the unfortunate, severe, yet logical end result of a chain of negative self-appraisals, negative events, and hopelessness. Extending an approach articulated by the early French sociologist Gabriel Tarde, in this paper I argue that suicide is merely an idea, albeit a very bad one, having more in common with societal beliefs and norms regarding such things as divorce, abortion, sex, politics, consumer behavior, and fashion. I make a sharp contrast between perturbation and lethality, concepts central to Edwin S. Shneidman's theory of suicide. Evidence supportive of suicide as an idea is discussed based on what we are learning from the study of history and culture, and about contagion/cluster phenomena, media/communication, and choice of method. It is suggested that certain individuals are more vulnerable to incorporate the idea and act of suicide into their concepts of self, based on the same principles by which ideas are spread throughout society. Just as suicide impacts on society, so does society impact on suicide.
NASA Technical Reports Server (NTRS)
Smith, David E.; Jonsson, Ari K.; Clancy, Daniel (Technical Monitor)
2001-01-01
In recent years, Graphplan style reachability analysis and mutual exclusion reasoning have been used in many high performance planning systems. While numerous refinements and extensions have been developed, the basic plan graph structure and reasoning mechanisms used in these systems are tied to the very simple STRIPS model of action. In 1999, Smith and Weld generalized the Graphplan methods for reachability and mutex reasoning to allow actions to have differing durations. However, the representation of actions still has some severe limitations that prevent the use of these techniques for many real-world planning systems. In this paper, we 1) separate the logic of reachability from the particular representation and inference methods used in Graphplan, and 2) extend the notions of reachability and mutual exclusion to more general notions of time and action. As it turns out, the general rules for mutual exclusion reasoning take on a remarkably clean and simple form. However, practical instantiations of them turn out to be messy, and require that we make representation and reasoning choices.
Formalized Epistemology, Logic, and Grammar
NASA Astrophysics Data System (ADS)
Bitbol, Michel
The task of a formal epistemology is defined. It appears that a formal epistemology must be a generalization of "logic" in the sense of Wittgenstein's Tractatus. The generalization is required because, whereas logic presupposes a strict relation between activity and language, this relation may be broken in some domains of experimental enquiry (e.g., in microscopic physics). However, a formal epistemology should also retain a major feature of Wittgenstein's "logic": It must not be a discourse about scientific knowledge, but rather a way of making manifest the structures usually implicit in knowledge-gaining activity. This strategy is applied to the formalism of quantum mechanics.
Electrical Circuits and Water Analogies
ERIC Educational Resources Information Center
Smith, Frederick A.; Wilson, Jerry D.
1974-01-01
Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)
NASA Astrophysics Data System (ADS)
Young, T.
This book is intended to be used as a textbook in a one-semester course at a variety of levels. Because of self-study features incorporated, it may also be used by practicing electronic engineers as a formal and thorough introduction to the subject. The distinction between linear and digital integrated circuits is discussed, taking into account digital and linear signal characteristics, linear and digital integrated circuit characteristics, the definitions for linear and digital circuits, applications of digital and linear integrated circuits, aspects of fabrication, packaging, and classification and numbering. Operational amplifiers are considered along with linear integrated circuit (LIC) power requirements and power supplies, voltage and current regulators, linear amplifiers, linear integrated circuit oscillators, wave-shaping circuits, active filters, DA and AD converters, demodulators, comparators, instrument amplifiers, current difference amplifiers, analog circuits and devices, and aspects of troubleshooting.
Computer Fiction: ``A Logic Named Joe''
NASA Astrophysics Data System (ADS)
Ferro, David; Swedin, Eric
The bulk of Science Fiction (SF) has not predicted the most influential computer technologies of the late 20th century. This paper begins with an exception entitled “A Logic Named Joe” and its accurate description of the contemporary environment of PCs and the World Wide Web. It then proposes the possible historical and cultural value of SF in techno-scientific development - more specifically computer development - in both the U.S. and Finland, and argues that social science approaches to understanding technoscience should take SF into account when describing those communities of practice.
NASA Technical Reports Server (NTRS)
Bohning, Oliver D. (Inventor)
1976-01-01
A unique, two-node sense circuit is disclosed. The circuit includes a bridge comprised of resistance elements and a differential amplifier. The two-node circuit is suitably adapted to be arranged in an array comprised of a plurality of discrete bridge-amplifiers which can be selectively energized. The circuit is arranged so as to form a configuration with minimum power utilization and a reduced number of components and interconnections therebetween.
2014-09-26
microns %H*SIC dimensions. Part 2: Various Programmable Logic Array (PLA) implementations with clocked CMOS technology are explored inthis project...Previous research at MSU has dealt with clocked CMOS circuit styles with some application to gate array and microprocessor applications. Work under this...in this report deals with structured logic schemes based on Programmable Logic Arrays (PLAs). Three different PLA design methods are reported with a
Periodic binary sequence generators: VLSI circuits considerations
NASA Technical Reports Server (NTRS)
Perlman, M.
1984-01-01
Feedback shift registers are efficient periodic binary sequence generators. Polynomials of degree r over a Galois field characteristic 2(GF(2)) characterize the behavior of shift registers with linear logic feedback. The algorithmic determination of the trinomial of lowest degree, when it exists, that contains a given irreducible polynomial over GF(2) as a factor is presented. This corresponds to embedding the behavior of an r-stage shift register with linear logic feedback into that of an n-stage shift register with a single two-input modulo 2 summer (i.e., Exclusive-OR gate) in its feedback. This leads to Very Large Scale Integrated (VLSI) circuit architecture of maximal regularity (i.e., identical cells) with intercell communications serialized to a maximal degree.
Knowledge representation in fuzzy logic
NASA Technical Reports Server (NTRS)
Zadeh, Lotfi A.
1989-01-01
The author presents a summary of the basic concepts and techniques underlying the application of fuzzy logic to knowledge representation. He then describes a number of examples relating to its use as a computational system for dealing with uncertainty and imprecision in the context of knowledge, meaning, and inference. It is noted that one of the basic aims of fuzzy logic is to provide a computational framework for knowledge representation and inference in an environment of uncertainty and imprecision. In such environments, fuzzy logic is effective when the solutions need not be precise and/or it is acceptable for a conclusion to have a dispositional rather than categorical validity. The importance of fuzzy logic derives from the fact that there are many real-world applications which fit these conditions, especially in the realm of knowledge-based systems for decision-making and control.
Emerging Standards for Medical Logic
Clayton, Paul D.; Hripcsak, George; Pryor, T. Allan
1990-01-01
Sharing medical logic has traditionally occurred in the form of lectures, conversations, books and journals. As knowledge based computer systems have demonstrated their utility in the health care arena, individuals have pondered the best way to transfer knowledge in a computer based representation (1). A simple representation which allows the knowledge to be shared can be constructed when the knowledge base is modular. Within this representation, units have been named Medical Logic Modules (MLM's) and a syntax has emerged which would allow multiple users to create, criticize, and share those types of medical logic which can be represented in this format. In this paper we talk about why standards exist and why they emerge in some areas and not in others. The appropriateness of using the proposed standards for medical logic modules is then examined against this broader context.
Treu, C.A. Jr.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.
Treu, Jr., Charles A.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes.
NASA Astrophysics Data System (ADS)
Kennedy, Peter
2013-01-01
Since its invention in 1983, Chua's circuit has become a reference circuit for studying bifurcations and chaos. This chapter plots the evolution of the circuit from the original simulations and experimental realization of a five-element topology with a three-segment nonlinear resistor to the latest three-element design comprising a capacitor, an inductor, and a memristor.
Integrated Circuit Computer Analysis.
information on this topic. The most important findings were the method used to identify combinational circuits ( Quine - McCluskey algorithm) and a clearly...defined set of limits on the problem of identifying sequential circuits. Since the Quine - McCluskey algorithm works only for combinational circuits, an
Electrical Circuit Simulation Code
Wix, Steven D.; Waters, Arlon J.; Shirley, David
2001-08-09
Massively-Parallel Electrical Circuit Simulation Code. CHILESPICE is a massively-arallel distributed-memory electrical circuit simulation tool that contains many enhanced radiation, time-based, and thermal features and models. Large scale electronic circuit simulation. Shared memory, parallel processing, enhance convergence. Sandia specific device models.
Yu, Lili; El-Damak, Dina; Radhakrishna, Ujwal; Ling, Xi; Zubair, Ahmad; Lin, Yuxuan; Zhang, Yuhao; Chuang, Meng-Hsi; Lee, Yi-Hsien; Antoniadis, Dimitri; Kong, Jing; Chandrakasan, Anantha; Palacios, Tomas
2016-10-12
Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.
Logic, Probability, and Human Reasoning
2015-01-01
logics developed in artificial intelligence, which allow conclusions to be withdrawn [38–42]. Second, conditional assertions (e.g., ‘If she insulted him...N. (2014) Probabilistic single function dual process theory and logic programming as approaches to non- monotonicity in human vs artificial reasoning...How can we solve this crisis? Leibniz dreamed of a calculus that settles any argument. Can cognitive scientists devise such a system? Feature
Heat exchanger expert system logic
NASA Technical Reports Server (NTRS)
Cormier, R.
1988-01-01
The reduction is described of the operation and fault diagnostics of a Deep Space Network heat exchanger to a rule base by the application of propositional calculus to a set of logic statements. The value of this approach lies in the ease of converting the logic and subsequently implementing it on a computer as an expert system. The rule base was written in Process Intelligent Control software.
Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata.
Bahar, Ali Newaz; Rahman, Mohammad Maksudur; Nahid, Nur Mohammad; Hassan, Md Kamrul
2017-02-01
This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T=2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.
Neural Circuit Inference from Function to Structure.
Real, Esteban; Asari, Hiroki; Gollisch, Tim; Meister, Markus
2017-01-23
Advances in technology are opening new windows on the structural connectivity and functional dynamics of brain circuits. Quantitative frameworks are needed that integrate these data from anatomy and physiology. Here, we present a modeling approach that creates such a link. The goal is to infer the structure of a neural circuit from sparse neural recordings, using partial knowledge of its anatomy as a regularizing constraint. We recorded visual responses from the output neurons of the retina, the ganglion cells. We then generated a systematic sequence of circuit models that represents retinal neurons and connections and fitted them to the experimental data. The optimal models faithfully recapitulated the ganglion cell outputs. More importantly, they made predictions about dynamics and connectivity among unobserved neurons internal to the circuit, and these were subsequently confirmed by experiment. This circuit inference framework promises to facilitate the integration and understanding of big data in neuroscience.
Smart Detector Cell: A Scalable All-Spin Circuit for Low Power Non-Boolean Pattern Recognition
NASA Astrophysics Data System (ADS)
Aghasi, Hamidreza; Iraei, Rouhollah Mousavi; Naeemi, Azad; Afshari, Ehsan
2016-05-01
We present a new circuit for non-Boolean recognition of binary images. Employing all-spin logic (ASL) devices, we design logic comparators and non-Boolean decision blocks for compact and efficient computation. By manipulation of fan-in number in different stages of the circuit, the structure can be extended for larger training sets or larger images. Operating based on the mainly similarity idea, the system is capable of constructing a mean image and compare it with a separate input image within a short decision time. Taking advantage of the non-volatility of ASL devices, the proposed circuit is capable of hybrid memory/logic operation. Compared with existing CMOS pattern recognition circuits, this work achieves a smaller footprint, lower power consumption, faster decision time and a lower operational voltage. To the best of our knowledge, this is the first fully spin-based complete pattern recognition circuit demonstrated using spintronic devices.
Logic implementations using a single nanoparticle-protein hybrid
NASA Astrophysics Data System (ADS)
Medalsy, Izhar; Klein, Michael; Heyman, Arnon; Shoseyov, Oded; Remacle, F.; Levine, R. D.; Porath, Danny
2010-06-01
A Set-Reset machine is the simplest logic circuit with a built-in memory. Its output is a (nonlinear) function of the input and of the state stored in the machine's memory. Here, we report a nanoscale Set-Reset machine operating at room temperature that is based on a 5-nm silicon nanoparticle attached to the inner pore of a stable circular protein. The nanoparticle-protein hybrid can also function as a balanced ternary multiplier. Conductive atomic force microscopy is used to implement the logic input and output operations, and the processing of the logic Set and Reset operations relies on the finite capacitance of the nanoparticle provided by the good electrical isolation given by the protein, thus enabling stability of the logic device states. We show that the machine can be cycled, such that in every successive cycle, the previous state in the memory is retained as the present state. The energy cost of one cycle of computation is minimized to the cost of charging this state.
NASA Astrophysics Data System (ADS)
Wang, Tiansi; Pei, Lei; Wang, Tingting; Lu, Rengui; Zhu, Chunbo
2016-01-01
Effective capacity-loss diagnosis and life-time prediction are the foundations of battery second-use technology and will play an important role in the development of the new energy industry. Of the two, the capacity-loss diagnostic, as a precondition of the life-time prediction, needs to be studied first. Performing a capacity-loss diagnosis for an aging cell consists of finding the decisive degradation mechanisms for the cell's capacity degradation. Because a cell's capacity just equals the span of the open-circuit voltage (OCV), when suspect degradation mechanisms affect a cell's capacity, they will leave corresponding and particular clues in the OCV curve. Taking a cell's OCV as the diagnostic indicator, a multi-mechanistic and non-destructive diagnostic method is developed in this paper. To establish an unambiguous relationship between OCV changes and the combinations of the decisive mechanisms, all the possible OCV changes under various aging situations are systematically analyzed based on a novel simultaneous coordinate system, in which the effects of each suspect capacity-loss mechanism on the OCV curve can be clearly represented. As a summary of the analysis results, a straightforward diagnostic flowchart is presented. By following the flowchart, an aging cell can be diagnosed within three steps by observation of the OCV changes.
Nicholls, David G
2010-01-01
Proton circuits across the inner mitochondrial membrane link the primary energy generators, namely the complexes of the electron transport chain, to multiple energy utilizing processes, including the ATP synthase, inherent proton leak pathways, metabolite transport and linked circuits of sodium and calcium. These mitochondrial circuits can be monitored in both isolated preparations and intact cells and, for the primary proton circuit techniques, exist to follow both the proton current and proton electrochemical potential components of the circuit in parallel experiments, providing a quantitative means of assessing mitochondrial function and, equally importantly, dysfunction.
CIRCUITS FOR CURRENT MEASUREMENTS
Cox, R.J.
1958-11-01
Circuits are presented for measurement of a logarithmic scale of current flowing in a high impedance. In one form of the invention the disclosed circuit is in combination with an ionization chamber to measure lonization current. The particular circuit arrangement lncludes a vacuum tube having at least one grid, an ionization chamber connected in series with a high voltage source and the grid of the vacuum tube, and a d-c amplifier feedback circuit. As the ionization chamber current passes between the grid and cathode of the tube, the feedback circuit acts to stabilize the anode current, and the feedback voltage is a measure of the logaritbm of the ionization current.
Novel latch for adiabatic quantum-flux-parametron logic
Takeuchi, Naoki Yamanashi, Yuki; Yoshikawa, Nobuyuki; Ortlepp, Thomas
2014-03-14
We herein propose the quantum-flux-latch (QFL) as a novel latch for adiabatic quantum-flux-parametron (AQFP) logic. A QFL is very compact and compatible with AQFP logic gates and can be read out in one clock cycle. Simulation results revealed that the QFL operates at 5 GHz with wide parameter margins of more than ±22%. The calculated energy dissipation was only ∼0.1 aJ/bit, which yields a small energy delay product of 20 aJ·ps. We also designed shift registers using QFLs to demonstrate more complex circuits with QFLs. Finally, we experimentally demonstrated correct operations of the QFL and a 1-bit shift register (a D flip-flop)
ERIC Educational Resources Information Center
Lawton, Joseph T.
1977-01-01
Tests Ausubel's (1960) subsumption theory of learning in the context of children's use of causal and logical connectives. Predicts that the acquisition of prior cognitive structure organizers would facilitate the learning and retention of subsequently presented concepts and logical operations and lead to a decrease of syncretic reasoning and…
Design structure for in-system redundant array repair in integrated circuits
Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.
2008-11-25
A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.
TRIAC/SCR proportional control circuit
Hughes, Wallace J.
1999-01-01
A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.
TRIAC/SCR proportional control circuit
Hughes, W.J.
1999-04-06
A power controller device is disclosed which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the ``reset`` input of a R-S flip flop, while an ``0`` crossing detector controls the ``set`` input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the ``reset`` and ``set`` inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations. 9 figs.
Memristive Sisyphus circuit for clock signal generation
NASA Astrophysics Data System (ADS)
Pershin, Yuriy V.; Shevchenko, Sergey N.; Nori, Franco
2016-05-01
Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as “dripping ants” or drops from leaky faucets.
Memristive Sisyphus circuit for clock signal generation
Pershin, Yuriy V.; Shevchenko, Sergey N.; Nori, Franco
2016-01-01
Frequency generators are widely used in electronics. Here, we report the design and experimental realization of a memristive frequency generator employing a unique combination of only digital logic gates, a single-supply voltage and a realistic thresholdtype memristive device. In our circuit, the oscillator frequency and duty cycle are defined by the switching characteristics of the memristive device and external resistors. We demonstrate the circuit operation both experimentally, using a memristor emulator, and theoretically, using a model memristive device with threshold. Importantly, nanoscale realizations of memristive devices offer small-size alternatives to conventional quartz-based oscillators. In addition, the suggested approach can be used for mimicking some cyclic (Sisyphus) processes in nature, such as “dripping ants” or drops from leaky faucets. PMID:27199243
Equivalent Circuit Modeling of Hysteresis Motors
Nitao, J J; Scharlemann, E T; Kirkendall, B A
2009-08-31
We performed a literature review and found that many equivalent circuit models of hysteresis motors in use today are incorrect. The model by Miyairi and Kataoka (1965) is the correct one. We extended the model by transforming it to quadrature coordinates, amenable to circuit or digital simulation. 'Hunting' is an oscillatory phenomenon often observed in hysteresis motors. While several works have attempted to model the phenomenon with some partial success, we present a new complete model that predicts hunting from first principles.
Chain Of Test Contacts For Integrated Circuits
NASA Technical Reports Server (NTRS)
Lieneweg, Udo
1989-01-01
Test structure forms chain of "cross" contacts fabricated together with large-scale integrated circuits. If necessary, number of such chains incorporated at suitable locations in integrated-circuit wafer for determination of fabrication yield of contacts. In new structure, resistances of individual contacts determined: In addition to making it possible to identify local defects, enables generation of statistical distributions of contact resistances for prediction of "parametric" contact yield of fabrication process.
Heuristics and criteria for constructing logical patterns in data
NASA Astrophysics Data System (ADS)
Antamoshkin, A. N.; Masich, I. S.; Kuzmich, R. I.
2015-10-01
The article considers various optimization models for constructing patterns in the method of logical analysis of data. Application techniques of the proposed models are specified and comparison of their classification against the accuracy on the task of predicting complications of myocardial infarction is provided
Fang, Fang; Lin, Yi-Han; Pierce, B Daniel; Lynn, David G
2015-10-12
The molecular logic gates that regulate gene circuits are necessarily intricate and highly regulated, particularly in the critical commitments necessary for pathogenesis. We now report simple AND and OR logic gates to be accessible within a single protein receptor. Pathogenesis by the bacterium Rhizobium radiobacter is mediated by a single histidine kinase, VirA, which processes multiple small molecule host signals (phenol and sugar). Mutagenesis analyses converged on a single signal integration node, and finer functional analyses revealed that a single residue could switch VirA from a functional AND logic gate to an OR gate where each of two signals activate independently. Host range preferences among natural strains of R. radiobacter correlate with these gate logic strategies. Although the precise mechanism for the signal integration node requires further analyses, long-range signal transmission through this histidine kinase can now be exploited for synthetic signaling circuits.
Logic-controlled solid-state switchgear for 270 volt dc.
NASA Technical Reports Server (NTRS)
Waddington, D.; Buchanan, E., Jr.; Sundberg, G.
1973-01-01
A feasibility study to design and demonstrate solid-state switchgear composed of circuit breakers and a power transfer switch is described. The switchgear operates on a nominal 270 Vdc circuit and controls power to a load up to 15 A. One circuit breaker may be interconnected to a second to form a power transfer switch. Breaker or switch on-off and transfer functions can be remotely controlled. Automatic overload trip-out is provided through an ultimate current trip and an I squared t trip for transient overcurrents lower than the ultimate current trip level. A number of reclosures with variable time delay between trip-out and reclosure are programmed and controlled by integrated analog and COSMOS logic circuits. A commutation circuit that creates minimal transient disturbances to either source or load was developed to interrupt current flow through the main SCR switching element.-
NASA Astrophysics Data System (ADS)
Proskuryakov, K. N.; Fedorov, A. I.; Zaporozhets, M. V.
2015-08-01
The accident at the Japanese Fukushima Daiichi nuclear power plant (NPP) caused by an earthquake showed the need of taking further efforts aimed at improving the design and engineering solutions for ensuring seismic resistance of NPPs with due regard to mutual influence of the dynamic processes occurring in the NPP building structures and process systems. Resonance interaction between the vibrations of NPP equipment and coolant pressure pulsations leads to an abnormal growth of dynamic stresses in structural materials, accelerated exhaustion of equipment service life, and increased number of sudden equipment failures. The article presents the results from a combined calculation-theoretical and experimental substantiation of mutual amplification of two kinds of external periodic loads caused by rotation of the reactor coolant pump (RCP) rotor and an earthquake. The data of vibration measurements at an NPP are presented, which confirm the predicted multiple amplification of vibrations in the steam generator and RCP at a certain combination of coolant thermal-hydraulic parameters. It is shown that the vibration frequencies of the main equipment may fall in the frequency band corresponding to the maximal values in the envelope response spectra constructed on the basis of floor accelerograms. The article presents the results from prediction of conditions under which vibroacoustic resonances with external periodic loads take place, which confirm the occurrence of additional earthquake-induced multiple growth of pressure pulsation intensity in the steam generator at the 8.3 Hz frequency and additional multiple growth of vibrations of the RCP and the steam generator cold header at the 16.6 Hz frequency. It is shown that at the elastic wave frequency equal to 8.3 Hz in the coolant, resonance occurs with the frequency of forced vibrations caused by the rotation of the RCP rotor. A conclusion is drawn about the possibility of exceeding the design level of equipment vibrations
Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan
2013-05-21
A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.
Medium scale integration of molecular logic gates in an automaton.
Macdonald, Joanne; Li, Yang; Sutovic, Marko; Lederman, Harvey; Pendri, Kiran; Lu, Wanhong; Andrews, Benjamin L; Stefanovic, Darko; Stojanovic, Milan N
2006-11-01
The assembly of molecular automata that perform increasingly complex tasks, such as game playing, presents an unbiased test of molecular computation. We now report a second-generation deoxyribozyme-based automaton, MAYA-II, which plays a complete game of tic-tac-toe according to a perfect strategy. In silicon terminology, MAYA-II represents the first "medium-scale integrated molecular circuit", integrating 128 deoxyribozyme-based logic gates, 32 input DNA molecules, and 8 two-channel fluorescent outputs across 8 wells.
Construction of a fuzzy and Boolean logic gates based on DNA.
Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen
2015-04-17
Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics.
Parallelizing quantum circuit synthesis
NASA Astrophysics Data System (ADS)
Di Matteo, Olivia; Mosca, Michele
2016-03-01
Quantum circuit synthesis is the process in which an arbitrary unitary operation is decomposed into a sequence of gates from a universal set, typically one which a quantum computer can implement both efficiently and fault-tolerantly. As physical implementations of quantum computers improve, the need is growing for tools that can effectively synthesize components of the circuits and algorithms they will run. Existing algorithms for exact, multi-qubit circuit synthesis scale exponentially in the number of qubits and circuit depth, leaving synthesis intractable for circuits on more than a handful of qubits. Even modest improvements in circuit synthesis procedures may lead to significant advances, pushing forward the boundaries of not only the size of solvable circuit synthesis problems, but also in what can be realized physically as a result of having more efficient circuits. We present a method for quantum circuit synthesis using deterministic walks. Also termed pseudorandom walks, these are walks in which once a starting point is chosen, its path is completely determined. We apply our method to construct a parallel framework for circuit synthesis, and implement one such version performing optimal T-count synthesis over the Clifford+T gate set. We use our software to present examples where parallelization offers a significant speedup on the runtime, as well as directly confirm that the 4-qubit 1-bit full adder has optimal T-count 7 and T-depth 3.
Multiple logic functions from extended blockade region in a silicon quantum-dot transistor
Lee, Youngmin; Lee, Sejoon Im, Hyunsik; Hiramoto, Toshiro
2015-02-14
We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.
Block QCA Fault-Tolerant Logic Gates
NASA Technical Reports Server (NTRS)
Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon
2003-01-01
Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA
Automated Design of Synthetic Cell Classifier Circuits Using a Two-Step Optimization Strategy.
Mohammadi, Pejman; Beerenwinkel, Niko; Benenson, Yaakov
2017-02-22
Cell classifiers are genetic logic circuits that transduce endogenous molecular inputs into cell-type-specific responses. Designing classifiers that achieve optimal differential response between specific cell types is a hard computational problem because it involves selection of endogenous inputs and optimization of both biochemical parameters and a logic function. To address this problem, we first derive an optimal set of biochemical parameters with the largest expected differential response over a diverse set of logic circuits, and second, we use these parameters in an evolutionary algorithm to select circuit inputs and optimize the logic function. Using this approach, we design experimentally feasible microRNA-based circuits capable of perfect discrimination for several real-world cell-classification tasks. We also find that under realistic cell-to-cell variation, circuit performance is comparable to standard cross-validation performance estimates. Our approach facilitates the generation of candidate circuits for experimental testing in therapeutic settings that require precise cell targeting, such as cancer therapy.
Multi-input distributed classifiers for synthetic genetic circuits.
Kanakov, Oleg; Kotelnikov, Roman; Alsaedi, Ahmed; Tsimring, Lev; Huerta, Ramón; Zaikin, Alexey; Ivanchenko, Mikhail
2015-01-01
For practical construction of complex synthetic genetic networks able to perform elaborate functions it is important to have a pool of relatively simple modules with different functionality which can be compounded together. To complement engineering of very different existing synthetic genetic devices such as switches, oscillators or logical gates, we propose and develop here a design of synthetic multi-input classifier based on a recently introduced distributed classifier concept. A heterogeneous population of cells acts as a single classifier, whose output is obtained by summarizing the outputs of individual cells. The learning ability is achieved by pruning the population, instead of tuning parameters of an individual cell. The present paper is focused on evaluating two possible schemes of multi-input gene classifier circuits. We demonstrate their suitability for implementing a multi-input distributed classifier capable of separating data which are inseparable for single-input classifiers, and characterize performance of the classifiers by analytical and numerical results. The simpler scheme implements a linear classifier in a single cell and is targeted at separable classification problems with simple class borders. A hard learning strategy is used to train a distributed classifier by removing from the population any cell answering incorrectly to at least one training example. The other scheme implements a circuit with a bell-shaped response in a single cell to allow potentially arbitrary shape of the classification border in the input space of a distributed classifier. Inseparable classification problems are addressed using soft learning strategy, characterized by probabilistic decision to keep or discard a cell at each training iteration. We expect that our classifier design contributes to the development of robust and predictable synthetic biosensors, which have the potential to affect applications in a lot of fields, including that of medicine and industry.
Robust design of biological circuits: evolutionary systems biology approach.
Chen, Bor-Sen; Hsu, Chih-Yuan; Liou, Jing-Jia
2011-01-01
Artificial gene circuits have been proposed to be embedded into microbial cells that function as switches, timers, oscillators, and the Boolean logic gates. Building more complex systems from these basic gene circuit components is one key advance for biologic circuit design and synthetic biology. However, the behavior of bioengineered gene circuits remains unstable and uncertain. In this study, a nonlinear stochastic system is proposed to model the biological systems with intrinsic parameter fluctuations and environmental molecular noise from the cellular context in the host cell. Based on evolutionary systems biology algorithm, the design parameters of target gene circuits can evolve to specific values in order to robustly track a desired biologic function in spite of intrinsic and environmental noise. The fitness function is selected to be inversely proportional to the tracking error so that the evolutionary biological circuit can achieve the optimal tracking mimicking the evolutionary process of a gene circuit. Finally, several design examples are given in silico with the Monte Carlo simulation to illustrate the design procedure and to confirm the robust performance of the proposed design method. The result shows that the designed gene circuits can robustly track desired behaviors with minimal errors even with nontrivial intrinsic and external noise.
Enabling complex genetic circuits to respond to extrinsic environmental signals.
Hoynes-O'Connor, Allison; Shopera, Tatenda; Hinman, Kristina; Creamer, John Philip; Moon, Tae Seok
2017-03-06
Genetic circuits have the potential to improve a broad range of metabolic engineering processes and address a variety of medical and environmental challenges. However, in order to engineer genetic circuits that can meet the needs of these real-world applications, genetic sensors that respond to relevant extrinsic and intrinsic signals must be implemented in complex genetic circuits. In this work, we construct the first AND and NAND gates that respond to temperature and pH, two signals that have relevance in a variety of real-world applications. A previously identified pH-responsive promoter and a temperature-responsive promoter were extracted from the E. coli genome, characterized, and modified to suit the needs of the genetic circuits. These promoters were combined with components of the type III secretion system in Salmonella typhimurium and used to construct a set of AND gates with up to 23-fold change. Next, an antisense RNA was integrated into the circuit architecture to invert the logic of the AND gate and generate a set of NAND gates with up to 1168-fold change. These circuits provide the first demonstration of complex pH- and temperature-responsive genetic circuits, and lay the groundwork for the use of similar circuits in real-world applications. Biotechnol. Bioeng. 2017;9999: 1-6. © 2017 Wiley Periodicals, Inc.
NASA Astrophysics Data System (ADS)
Eriguchi, Koji
2014-10-01
An increasing demand for high performance field-effect transistors (FETs) leads to the aggressive critical dimension shrinkage and the currently-emerging three dimensional (3D) geometry. Plasma processing is widely used also in the scaled- and 3D-FET (e.g. FinFET) manufacturing, where precise control of the reaction on the (sidewall) surfaces is a prime issue. In this study, damage creation mechanism during plasma etching--plasma-induced physical damage (PPD)--was investigated in such structures on the basis of the PPD range theory, atomistic simulations, and experiments. Compared to PPD in planar FETs (e.g. Si recess [2,3]), a stochastic modeling and atomistic simulations predicted that, during etching of ``fins'' in a 3D-FET, the following two mechanisms are responsible for damage creation in addition to an ion impact on the sidewall at an oblique incident angle: 1) incoming ions penetrate into the Si substrate and undergo scattering by Si atoms in the lateral direction even if the incident angle is normal to the surface and 2) some of Si atoms and ions sputtered at the surface being etched impact on the sidewall with energies sufficient to break Si-Si bonds. These straggling and sputtering processes are stochastic and fundamental, thus, result in 3D structure damage (``fin-damage''). The ``fin-damage'' induced by straggling was modeled by the PPD range theory. Molecular dynamics simulations clarified the mechanisms under the various plasma conditions. Quantum mechanical calculations showed that created defect structures play the role of a carrier trap site, which was experimentally verified by an electrical measurement. Since they are intrinsic natures of etching, both straggling and sputtering noted here should be implemented to design a low-damage etching process. This work was supported in part by Grant-in-Aid for Scientific Research (B) 23360321 from JSPS and STARC project.
Applying analog integrated circuits for HERO protection
NASA Technical Reports Server (NTRS)
Willis, Kenneth E.; Blachowski, Thomas J.
1994-01-01
One of the most efficient methods for protecting electro-explosive devices (EED's) from HERO and ESD is to shield the EED in a conducting shell (Faraday cage). Electrical energy is transferred to the bridge by means of a magnetic coupling which passes through a portion of the conducting shell that is made from a magnetically permeable but electrically conducting material. This technique was perfected by ML Aviation, a U.K. company, in the early 80's, and was called a Radio Frequency Attenuation Connector (RFAC). It is now in wide use in the U.K. Previously, the disadvantage of RFAC over more conventional methods was its relatively high cost, largely driven by a thick film hybrid circuit used to switch the primary of the transformer. Recently, through a licensing agreement, this technology has been transferred to the U.S. and significant cost reductions and performance improvements have been achieved by the introduction of analog integrated circuits. An integrated circuit performs the following functions: (1) Chops the DC input to a signal suitable for driving the primary of the transformer; (2) Verifies the input voltage is above a threshold; (3) Verifies the input voltage is valid for a pre set time before enabling the device; (4) Provides thermal protection of the circuit; and (5) Provides an external input for independent logic level enabling of the power transfer mechanism. This paper describes the new RFAC product and its applications.
A four-colour optical detector circuit
NASA Astrophysics Data System (ADS)
Yohannes, Israel; Assaad, Maher
2013-02-01
In this article, a new architecture for a four-colour optical detector circuit is presented. The proposed detector uses a photodiode as its basic light transducing element and a mixed signal readout circuit for signal processing and decision making. The readout circuit requires only two comparators, two multiplexers and a few logic gates to produce a digital 4 bit output that represents the right colour detected. The proposed detector is advantageous because the number of required components is fixed even if the number of detected colours is increased. The feature of having a fixed number of elements while increasing the number of detected colours is important especially in component count (i.e. low cost) and low power consumption. The proposed detector can be used as an autonomous and portable real-time pH monitoring applications. The objective of this article is to present a validation of a novel four colour sensor architecture using simulation and experiment as a proof of concept for a future implementation as a CMOS integrated circuit using the Austria Microsystems 350 nm technology.
Logic, probability, and human reasoning.
Johnson-Laird, P N; Khemlani, Sangeet S; Goodwin, Geoffrey P
2015-04-01
This review addresses the long-standing puzzle of how logic and probability fit together in human reasoning. Many cognitive scientists argue that conventional logic cannot underlie deductions, because it never requires valid conclusions to be withdrawn - not even if they are false; it treats conditional assertions implausibly; and it yields many vapid, although valid, conclusions. A new paradigm of probability logic allows conclusions to be withdrawn and treats conditionals more plausibly, although it does not address the problem of vapidity. The theory of mental models solves all of these problems. It explains how people reason about probabilities and postulates that the machinery for reasoning is itself probabilistic. Recent investigations accordingly suggest a way to integrate probability and deduction.
Fuzzy logic particle tracking velocimetry
NASA Technical Reports Server (NTRS)
Wernet, Mark P.
1993-01-01
Fuzzy logic has proven to be a simple and robust method for process control. Instead of requiring a complex model of the system, a user defined rule base is used to control the process. In this paper the principles of fuzzy logic control are applied to Particle Tracking Velocimetry (PTV). Two frames of digitally recorded, single exposure particle imagery are used as input. The fuzzy processor uses the local particle displacement information to determine the correct particle tracks. Fuzzy PTV is an improvement over traditional PTV techniques which typically require a sequence (greater than 2) of image frames for accurately tracking particles. The fuzzy processor executes in software on a PC without the use of specialized array or fuzzy logic processors. A pair of sample input images with roughly 300 particle images each, results in more than 200 velocity vectors in under 8 seconds of processing time.
Inverter Circuits using Pentacene and ZnO Transistors
NASA Astrophysics Data System (ADS)
Iechi, Hiroyuki; Watanabe, Yasuyuki; Kudo, Kazuhiro
2007-04-01
We report two types of integrated circuits based on a pentacene static-induction transistor (SIT), a pentacene thin-film transistor (TFT) and a zinc oxide (ZnO) TFT. The operating characteristics of a p-p inverter using pentacene SITs and a complementary inverter using a p-channel pentacene TFT and an n-channel ZnO TFT are described. The basic operation of logic circuits at a low voltage was achieved for the first time using the pentacene SIT inverter and complementary circuits with hybrid inorganic and organic materials. Furthermore, we describe the electrical properties of the ZnO films depending on sputtering conditions, and the complementary circuits using ZnO and pentacene TFTs.
Improved Classical Simulation of Quantum Circuits Dominated by Clifford Gates.
Bravyi, Sergey; Gosset, David
2016-06-24
We present a new algorithm for classical simulation of quantum circuits over the Clifford+T gate set. The runtime of the algorithm is polynomial in the number of qubits and the number of Clifford gates in the circuit but exponential in the number of T gates. The exponential scaling is sufficiently mild that the algorithm can be used in practice to simulate medium-sized quantum circuits dominated by Clifford gates. The first demonstrations of fault-tolerant quantum circuits based on 2D topological codes are likely to be dominated by Clifford gates due to a high implementation cost associated with logical T gates. Thus our algorithm may serve as a verification tool for near-term quantum computers which cannot in practice be simulated by other means. To demonstrate the power of the new method, we performed a classical simulation of a hidden shift quantum algorithm with 40 qubits, a few hundred Clifford gates, and nearly 50 T gates.
Macromodeling and optimization of digital MOS VLSI circuits
NASA Astrophysics Data System (ADS)
Matson, M. D.; Glasser, L. A.
1986-03-01
Power consumption and signal delay are crucial to the design of high-performance VLSI circuits. This paper presents CAD tools for modeling and optimizing digital MOS designs. The tools determine the transistor sizes that minimize circuit power consumption subject to constraints on signal path delays. Computational efficiency is obtained through macromodeling techniques and a specialized optimization algorithm. The macromodels are based on device equations, and encapsulate logic gate behavior in a set of simple yet accurate formulas. The optimization algorithm exploits properties of the digital MOS domain to convert the primal optimization problem into a dual form which is much easier to solve. The result is a pair of CAD tools that can optimize a circuit in roughly the amount of time needed to perform a transistor level simulation of the circuit.
Gritzo, Russell E.
1987-01-01
A remote reset circuit acts as a stand-alone monitor and controller by clocking in each character sent by a terminal to a computer and comparing it to a given reference character. When a match occurs, the remote reset circuit activates the system's hardware reset line. The remote reset circuit is hardware based centered around monostable multivibrators and is unaffected by system crashes, partial serial transmissions, or power supply transients.
Regenerative feedback resonant circuit
Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.
2014-09-02
A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.
Advances in the modeling of single electron transistors for the design of integrated circuit.
Chi, Yaqing; Sui, Bingcai; Yi, Xun; Fang, Liang; Zhou, Hailiang
2010-09-01
Single electron transistor (SET) has become a promising candidate for the key device of logic circuit in the near future. The advances of recent 5 years in the modeling of SETs are reviewed for the simulation of SET/hybrid CMOS-SET integrated circuit. Three dominating SET models, Monte Carlo model, master equation model and macro model, are analyzed, tested and compared on their principles, characteristics, applicability and development trend. The Monte Carlo model is suitable for SET structure research and simulation of small scale SET circuit, while the analytical model based on combination with master equation and macro model is suitable to simulate the SET circuit at balanceable efficiency and accuracy.
NASA Technical Reports Server (NTRS)
Ruspini, Enrique H.
1991-01-01
Summarized here are the results of recent research on the conceptual foundations of fuzzy logic. The focus is primarily on the principle characteristics of a model that quantifies resemblance between possible worlds by means of a similarity function that assigns a number between 0 and 1 to every pair of possible worlds. Introduction of such a function permits one to interpret the major constructs and methods of fuzzy logic: conditional and unconditional possibility and necessity distributions and the generalized modus ponens of Zadeh on the basis of related metric relationships between subsets of possible worlds.
Logic programming and metadata specifications
NASA Technical Reports Server (NTRS)
Lopez, Antonio M., Jr.; Saacks, Marguerite E.
1992-01-01
Artificial intelligence (AI) ideas and techniques are critical to the development of intelligent information systems that will be used to collect, manipulate, and retrieve the vast amounts of space data produced by 'Missions to Planet Earth.' Natural language processing, inference, and expert systems are at the core of this space application of AI. This paper presents logic programming as an AI tool that can support inference (the ability to draw conclusions from a set of complicated and interrelated facts). It reports on the use of logic programming in the study of metadata specifications for a small problem domain of airborne sensors, and the dataset characteristics and pointers that are needed for data access.
Superconducting gates with fluxon logics
NASA Astrophysics Data System (ADS)
Nacak, H.; Kusmartsev, F. V.
2010-10-01
We have developed several logic gates (OR, XOR, AND and NAND) made of superconducting Josephson junctions. The gates based of the flux cloning phenomenon and high speed of fluxons moving in Josephson junctions of different shapes. In a contrast with previous design the gates operates extremely fast since fluxons are moving with the speed close to the speed of light. We have demonstrated their operations and indicated several ways to made a more complicated logic elements which have at the same time a compact form.
Dynamic Logic Assigned to Automata
NASA Astrophysics Data System (ADS)
Chajda, Ivan; Paseka, Jan
2017-02-01
A dynamic logic B can be assigned to every automaton [InlineMediaObject not available: see fulltext.] without regard if [InlineMediaObject not available: see fulltext.] is deterministic or nondeterministic. This logic enables us to formulate observations on [InlineMediaObject not available: see fulltext.] in the form of composed propositions and, due to a transition functor T, it captures the dynamic behaviour of [InlineMediaObject not available: see fulltext.]. There are formulated conditions under which the automaton [InlineMediaObject not available: see fulltext.] can be recovered by means of B and T.
A Logical Approach to Entanglement
NASA Astrophysics Data System (ADS)
Das, Abhishek
2016-10-01
In this paper we innovate a logical approach to develop an intuition regarding the phenomenon of quantum entanglement. In the vein of the logic introduced we substantiate that particles that were entangled in the past will be entangled in perpetuity and thereby abide a rule that restricts them to act otherwise. We also introduce a game and by virtue of the concept of Nash equilibrium we have been able to show that entangled particles will mutually correspond to an experiment that is performed on any one of the particle.
MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic
Jaiswal, Akhilesh; Roy, Kaushik
2017-01-01
In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates. PMID:28045074
MESL: Proposal for a Non-volatile Cascadable Magneto-Electric Spin Logic
NASA Astrophysics Data System (ADS)
Jaiswal, Akhilesh; Roy, Kaushik
2017-01-01
In the quest for novel, scalable and energy-efficient computing technologies, many non-charge based logic devices are being explored. Recent advances in multi-ferroic materials have paved the way for electric field induced low energy and fast switching of nano-magnets using the magneto-electric (ME) effect. In this paper, we propose a voltage driven logic-device based on the ME induced switching of nano-magnets. We further demonstrate that the proposed logic-device, which exhibits decoupled read and write paths, can be used to construct a complete logic family including XNOR, NAND and NOR gates. The proposed logic family shows good scalability with a quadratic dependence of switching energy with respect to the switching voltage. Further, the proposed logic-device has better robustness against the effect of thermal noise as compared to the conventional current driven switching of nano-magnets. A device-to-circuit level coupled simulation framework, including magnetization dynamics and electron transport model, has been developed for analyzing the present proposal. Using our simulation framework, we present energy and delay results for the proposed Magneto-Electric Spin Logic (MESL) gates.
caspo: a toolbox for automated reasoning on the response of logical signaling networks families
Videla, Santiago; Saez-Rodriguez, Julio; Guziolowski, Carito
2017-01-01
Abstract Summary: We introduce the caspo toolbox, a python package implementing a workflow for reasoning on logical networks families. Our software allows researchers to (i) learn a family of logical networks derived from a given topology and explaining the experimental response to various perturbations; (ii) classify all logical networks in a given family by their input-output behaviors; (iii) predict the response of the system to every possible perturbation based on the ensemble of predictions; (iv) design new experimental perturbations to discriminate among a family of logical networks; and (v) control a family of logical networks by finding all interventions strategies forcing a set of targets into a desired steady state. Availability and Implementation: caspo is open-source software distributed under the GPLv3 license. Source code is publicly hosted at http://github.com/bioasp/caspo. Contact: anne.siegel@irisa.fr PMID:28065903
Chabi, Amir Mokhtar; Sayedsalehi, Samira; Angizi, Shaahin; Navi, Keivan
2014-01-01
Quantum-dot cellular automata (QCA) are a transistorless computation approach which encodes binary information via configuration of charges among quantum dots. The fundamental QCA logic primitives are majority and inverter gates which can be utilized to design various QCA circuits. This study presents a novel approach to designing efficient QCA-based circuits based on Boolean expressions achieved from reconfiguration of five-input and three-input majority gates. Whereas the multiplexer and Exclusive-or are the most important fundamental logical circuits in digital systems, designing efficient and single layer structures without coplanar cross-over wiring is advantageous in QCA technology. In order to demonstrate the efficiency and usefulness of the proposed approach, simple and dense multiplexer and Exclusive-or structures are implemented. The proposed designs have significant improvement in terms of area, complexity, latency, and gate count in comparison to previous designs. The correct logical functionalities of presented structures have been authenticated using QCA designer tool.
Designing Experiments to Discriminate Families of Logic Models
Videla, Santiago; Konokotina, Irina; Alexopoulos, Leonidas G.; Saez-Rodriguez, Julio; Schaub, Torsten; Siegel, Anne; Guziolowski, Carito
2015-01-01
Logic models of signaling pathways are a promising way of building effective in silico functional models of a cell, in particular of signaling pathways. The automated learning of Boolean logic models describing signaling pathways can be achieved by training to phosphoproteomics data, which is particularly useful if it is measured upon different combinations of perturbations in a high-throughput fashion. However, in practice, the number and type of allowed perturbations are not exhaustive. Moreover, experimental data are unavoidably subjected to noise. As a result, the learning process results in a family of feasible logical networks rather than in a single model. This family is composed of logic models implementing different internal wirings for the system and therefore the predictions of experiments from this family may present a significant level of variability, and hence uncertainty. In this paper, we introduce a method based on Answer Set Programming to propose an optimal experimental design that aims to narrow down the variability (in terms of input–output behaviors) within families of logical models learned from experimental data. We study how the fitness with respect to the data can be improved after an optimal selection of signaling perturbations and how we learn optimal logic models with minimal number of experiments. The methods are applied on signaling pathways in human liver cells and phosphoproteomics experimental data. Using 25% of the experiments, we obtained logical models with fitness scores (mean square error) 15% close to the ones obtained using all experiments, illustrating the impact that our approach can have on the design of experiments for efficient model calibration. PMID:26389116
NASA Astrophysics Data System (ADS)
Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui
2016-07-01
Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.