Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices

NASA Astrophysics Data System (ADS)

Breuer, Thomas; Nielen, Lutz; Roesgen, Bernd; Waser, Rainer; Rana, Vikas; Linn, Eike

2016-04-01

Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 106 cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Construction of a fuzzy and Boolean logic gates based on DNA.

PubMed

Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

2015-04-17

Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Toward spin-based Magneto Logic Gate in Graphene

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland

Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.

Experimental demonstration of programmable multi-functional spin logic cell based on spin Hall effect

NASA Astrophysics Data System (ADS)

Zhang, X.; Wan, C. H.; Yuan, Z. H.; Fang, C.; Kong, W. J.; Wu, H.; Zhang, Q. T.; Tao, B. S.; Han, X. F.

2017-04-01

Confronting with the gigantic volume of data produced every day, raising integration density by reducing the size of devices becomes harder and harder to meet the ever-increasing demand for high-performance computers. One feasible path is to actualize more logic functions in one cell. In this respect, we experimentally demonstrate a prototype spin-orbit torque based spin logic cell integrated with five frequently used logic functions (AND, OR, NOT, NAND and NOR). The cell can be easily programmed and reprogrammed to perform desired function. Furthermore, the information stored in cells is symmetry-protected, making it possible to expand into logic gate array where the cell can be manipulated one by one without changing the information of other undesired cells. This work provides a prospective example of multi-functional spin logic cell with reprogrammability and nonvolatility, which will advance the application of spin logic devices.

A type of all-optical logic gate based on graphene surface plasmon polaritons

NASA Astrophysics Data System (ADS)

Wu, Xiaoting; Tian, Jinping; Yang, Rongcao

2017-11-01

In this paper, a novel type of all-optical logic device based on graphene surface plasmon polaritons (GSP) is proposed. By utilizing linear interference between the GSP waves propagating in the different channels, this new structure can realize six different basic logic gates including OR, XOR, NOT, AND, NOR, and NAND. The state of ;ON/OFF; of each input channel can be well controlled by tuning the optical conductivity of graphene sheets, which can be further controlled by changing the external gate voltage. This type of logic gate is compact in geometrical sizes and is a potential block in the integration of nanophotonic devices.

Versatile logic devices based on programmable DNA-regulated silver-nanocluster signal transducers.

PubMed

Huang, Zhenzhen; Tao, Yu; Pu, Fang; Ren, Jinsong; Qu, Xiaogang

2012-05-21

A DNA-encoding strategy is reported for the programmable regulation of the fluorescence properties of silver nanoclusters (AgNCs). By taking advantage of the DNA-encoding strategy, aqueous AgNCs were used as signal transducers to convert DNA inputs into fluorescence outputs for the construction of various DNA-based logic gates (AND, OR, INHIBIT, XOR, NOR, XNOR, NAND, and a sequential logic gate). Moreover, a biomolecular keypad that was capable of constructing crossword puzzles was also fabricated. These AgNC-based logic systems showed several advantages, including a simple transducer-introduction strategy, universal design, and biocompatible operation. In addition, this proof of concept opens the door to a new generation of signal transducer materials and provides a general route to versatile biomolecular logic devices for practical applications. Copyright © 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Compact modeling of CRS devices based on ECM cells for memory, logic and neuromorphic applications.

PubMed

Linn, E; Menzel, S; Ferch, S; Waser, R

2013-09-27

Dynamic physics-based models of resistive switching devices are of great interest for the realization of complex circuits required for memory, logic and neuromorphic applications. Here, we apply such a model of an electrochemical metallization (ECM) cell to complementary resistive switches (CRSs), which are favorable devices to realize ultra-dense passive crossbar arrays. Since a CRS consists of two resistive switching devices, it is straightforward to apply the dynamic ECM model for CRS simulation with MATLAB and SPICE, enabling study of the device behavior in terms of sweep rate and series resistance variations. Furthermore, typical memory access operations as well as basic implication logic operations can be analyzed, revealing requirements for proper spike and level read operations. This basic understanding facilitates applications of massively parallel computing paradigms required for neuromorphic applications.

An Energy Saving Green Plug Device for Nonlinear Loads

NASA Astrophysics Data System (ADS)

Bloul, Albe; Sharaf, Adel; El-Hawary, Mohamed

2018-03-01

The paper presents a low cost a FACTS Based flexible fuzzy logic based modulated/switched tuned arm filter and Green Plug compensation (SFC-GP) scheme for single-phase nonlinear loads ensuring both voltage stabilization and efficient energy utilization. The new Green Plug-Switched filter compensator SFC modulated LC-Filter PWM Switched Capacitive Compensation Devices is controlled using a fuzzy logic regulator to enhance power quality, improve power factor at the source and reduce switching transients and inrush current conditions as well harmonic contents in source current. The FACTS based SFC-GP Device is a member of family of Green Plug/Filters/Compensation Schemes used for efficient energy utilization, power quality enhancement and voltage/inrush current/soft starting control using a dynamic error driven fuzzy logic controller (FLC). The device with fuzzy logic controller is validated using the Matlab / Simulink Software Environment for enhanced power quality (PQ), improved power factor and reduced inrush currents. This is achieved using modulated PWM Switching of the Filter-Capacitive compensation scheme to cope with dynamic type nonlinear and inrush cyclical loads..

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Magnetic tunnel junction based spintronic logic devices

NASA Astrophysics Data System (ADS)

Lyle, Andrew Paul

The International Technology Roadmap for Semiconductors (ITRS) predicts that complimentary metal oxide semiconductor (CMOS) based technologies will hit their last generation on or near the 16 nm node, which we expect to reach by the year 2025. Thus future advances in computational power will not be realized from ever-shrinking device sizes, but rather by 'outside the box' designs and new physics, including molecular or DNA based computation, organics, magnonics, or spintronic. This dissertation investigates magnetic logic devices for post-CMOS computation. Three different architectures were studied, each relying on a different magnetic mechanism to compute logic functions. Each design has it benefits and challenges that must be overcome. This dissertation focuses on pushing each design from the drawing board to a realistic logic technology. The first logic architecture is based on electrically connected magnetic tunnel junctions (MTJs) that allow direct communication between elements without intermediate sensing amplifiers. Two and three input logic gates, which consist of two and three MTJs connected in parallel, respectively were fabricated and are compared. The direct communication is realized by electrically connecting the output in series with the input and applying voltage across the series connections. The logic gates rely on the fact that a change in resistance at the input modulates the voltage that is needed to supply the critical current for spin transfer torque switching the output. The change in resistance at the input resulted in a voltage margin of 50--200 mV and 250--300 mV for the closest input states for the three and two input designs, respectively. The two input logic gate realizes the AND, NAND, NOR, and OR logic functions. The three input logic function realizes the Majority, AND, NAND, NOR, and OR logic operations. The second logic architecture utilizes magnetostatically coupled nanomagnets to compute logic functions, which is the basis of Magnetic Quantum Cellular Automata (MQCA). MQCA has the potential to be thousands of times more energy efficient than CMOS technology. While interesting, these systems are academic unless they can be interfaced into current technologies. This dissertation pushed past a major hurdle by experimentally demonstrating a spintronic input/output (I/O) interface for the magnetostatically coupled nanomagnets by incorporating MTJs. This spintronic interface allows individual nanomagnets to be programmed using spin transfer torque and read using magneto resistance structure. Additionally the spintronic interface allows statistical data on the reliability of the magnetic coupling utilized for data propagation to be easily measured. The integration of spintronics and MQCA for an electrical interface to achieve a magnetic logic device with low power creates a competitive post-CMOS logic device. The final logic architecture that was studied used MTJs to compute logic functions and magnetic domain walls to communicate between gates. Simulations were used to optimize the design of this architecture. Spin transfer torque was used to compute logic function at each MTJ gate and was used to drive the domain walls. The design demonstrated that multiple nanochannels could be connected to each MTJ to realize fan-out from the logic gates. As a result this logic scheme eliminates the need for intermediate reads and conversions to pass information from one logic gate to another.

Microelectromechanical reprogrammable logic device.

PubMed

Hafiz, M A A; Kosuru, L; Younis, M I

2016-03-29

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme.

Microelectromechanical reprogrammable logic device

PubMed Central

Hafiz, M. A. A.; Kosuru, L.; Younis, M. I.

2016-01-01

In modern computing, the Boolean logic operations are set by interconnect schemes between the transistors. As the miniaturization in the component level to enhance the computational power is rapidly approaching physical limits, alternative computing methods are vigorously pursued. One of the desired aspects in the future computing approaches is the provision for hardware reconfigurability at run time to allow enhanced functionality. Here we demonstrate a reprogrammable logic device based on the electrothermal frequency modulation scheme of a single microelectromechanical resonator, capable of performing all the fundamental 2-bit logic functions as well as n-bit logic operations. Logic functions are performed by actively tuning the linear resonance frequency of the resonator operated at room temperature and under modest vacuum conditions, reprogrammable by the a.c.-driving frequency. The device is fabricated using complementary metal oxide semiconductor compatible mass fabrication process, suitable for on-chip integration, and promises an alternative electromechanical computing scheme. PMID:27021295

Integrated all-optical logic discriminators based on plasmonic bandgap engineering

PubMed Central

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2013-01-01

Optical computing uses photons as information carriers, opening up the possibility for ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic devices are indispensible core components of optical computing systems. However, up to now, little experimental progress has been made in nanoscale all-optical logic discriminators, which have the function of discriminating and encoding incident light signals according to wavelength. Here, we report a strategy to realize a nanoscale all-optical logic discriminator based on plasmonic bandgap engineering in a planar plasmonic microstructure. Light signals falling within different operating wavelength ranges are differentiated and endowed with different logic state encodings. Compared with values previously reported, the operating bandwidth is enlarged by one order of magnitude. Also the SPP light source is integrated with the logic device while retaining its ultracompact size. This opens up a way to construct on-chip all-optical information processors and artificial intelligence systems. PMID:24071647

Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lashin, A. V., E-mail: LashinAV@lhp.ru; Kozyrev, A. V.

One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits.

Application of SEU imaging for analysis of device architecture using a 25 MeV/u 86Kr ion microbeam at HIRFL

NASA Astrophysics Data System (ADS)

Liu, Tianqi; Yang, Zhenlei; Guo, Jinlong; Du, Guanghua; Tong, Teng; Wang, Xiaohui; Su, Hong; Liu, Wenjing; Liu, Jiande; Wang, Bin; Ye, Bing; Liu, Jie

2017-08-01

The heavy-ion imaging of single event upset (SEU) in a flash-based field programmable gate array (FPGA) device was carried out for the first time at Heavy Ion Research Facility in Lanzhou (HIRFL). The three shift register chains with separated input and output configurations in device under test (DUT) were used to identify the corresponding logical area rapidly once an upset occurred. The logic units in DUT were partly configured in order to distinguish the registers in SEU images. Based on the above settings, the partial architecture of shift register chains in DUT was imaged by employing the microbeam of 86Kr ion with energy of 25 MeV/u in air. The results showed that the physical distribution of registers in DUT had a high consistency with its logical arrangement by comparing SEU image with logic configuration in scanned area.

CMOS-compatible spintronic devices: a review

NASA Astrophysics Data System (ADS)

Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

2016-11-01

For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

Multiferroic nanomagnetic logic: Hybrid spintronics-straintronic paradigm for ultra-low energy computing

NASA Astrophysics Data System (ADS)

Salehi Fashami, Mohammad

Excessive energy dissipation in CMOS devices during switching is the primary threat to continued downscaling of computing devices in accordance with Moore's law. In the quest for alternatives to traditional transistor based electronics, nanomagnet-based computing [1, 2] is emerging as an attractive alternative since: (i) nanomagnets are intrinsically more energy-efficient than transistors due to the correlated switching of spins [3], and (ii) unlike transistors, magnets have no leakage and hence have no standby power dissipation. However, large energy dissipation in the clocking circuit appears to be a barrier to the realization of ultra low power logic devices with such nanomagnets. To alleviate this issue, we propose the use of a hybrid spintronics-straintronics or straintronic nanomagnetic logic (SML) paradigm. This uses a piezoelectric layer elastically coupled to an elliptically shaped magnetostrictive nanomagnetic layer for both logic [4-6] and memory [7-8] and other information processing [9-10] applications that could potentially be 2-3 orders of magnitude more energy efficient than current CMOS based devices. This dissertation focuses on studying the feasibility, performance and reliability of such nanomagnetic logic circuits by simulating the nanoscale magnetization dynamics of dipole coupled nanomagnets clocked by stress. Specifically, the topics addressed are: 1. Theoretical study of multiferroic nanomagnetic arrays laid out in specific geometric patterns to implement a "logic wire" for unidirectional information propagation and a universal logic gate [4-6]. 2. Monte Carlo simulations of the magnetization trajectories in a simple system of dipole coupled nanomagnets and NAND gate described by the Landau-Lifshitz-Gilbert (LLG) equations simulated in the presence of random thermal noise to understand the dynamics switching error [11, 12] in such devices. 3. Arriving at a lower bound for energy dissipation as a function of switching error [13] for a practical nanomagnetic logic scheme. 4. Clocking of nanomagnetic logic with surface acoustic waves (SAW) to drastically decrease the lithographic burden needed to contact each multiferroic nanomagnet while maintaining pipelined information processing. 5. Nanomagnets with four (or higher states) implemented with shape engineering. Two types of magnet that encode four states: (i) diamond, and (ii) concave nanomagnets are studied for coherence of the switching process.

Spin wave nonreciprocity for logic device applications

NASA Astrophysics Data System (ADS)

Jamali, Mahdi; Kwon, Jae Hyun; Seo, Soo-Man; Lee, Kyung-Jin; Yang, Hyunsoo

2013-11-01

The utilization of spin waves as eigenmodes of the magnetization dynamics for information processing and communication has been widely explored recently due to its high operational speed with low power consumption and possible applications for quantum computations. Previous proposals of spin wave Mach-Zehnder devices were based on the spin wave phase, a delicate entity which can be easily disrupted. Here, we propose a complete logic system based on the spin wave amplitude utilizing the nonreciprocal spin wave behavior excited by microstrip antennas. The experimental data reveal that the nonreciprocity of magnetostatic surface spin wave can be tuned by the bias magnetic field. Furthermore, engineering of the device structure could result in a high nonreciprocity factor for spin wave logic applications.

Spin wave nonreciprocity for logic device applications

PubMed Central

Jamali, Mahdi; Kwon, Jae Hyun; Seo, Soo-Man; Lee, Kyung-Jin; Yang, Hyunsoo

2013-01-01

The utilization of spin waves as eigenmodes of the magnetization dynamics for information processing and communication has been widely explored recently due to its high operational speed with low power consumption and possible applications for quantum computations. Previous proposals of spin wave Mach-Zehnder devices were based on the spin wave phase, a delicate entity which can be easily disrupted. Here, we propose a complete logic system based on the spin wave amplitude utilizing the nonreciprocal spin wave behavior excited by microstrip antennas. The experimental data reveal that the nonreciprocity of magnetostatic surface spin wave can be tuned by the bias magnetic field. Furthermore, engineering of the device structure could result in a high nonreciprocity factor for spin wave logic applications. PMID:24196318

Trinary flip-flops using Savart plate and spatial light modulator for optical computation in multivalued logic

NASA Astrophysics Data System (ADS)

Ghosh, Amal K.; Basuray, Amitabha

2008-11-01

The memory devices in multi-valued logic are of most significance in modern research. This paper deals with the implementation of basic memory devices in multi-valued logic using Savart plate and spatial light modulator (SLM) based optoelectronic circuits. Photons are used here as the carrier to speed up the operations. Optical tree architecture (OTA) has been also utilized in the optical interconnection network. We have exploited the advantages of Savart plates, SLMs and OTA and proposed the SLM based high speed JK, D-type and T-type flip-flops in a trinary system.

Biophotonic logic devices based on quantum dots and temporally-staggered Förster energy transfer relays

NASA Astrophysics Data System (ADS)

Claussen, Jonathan C.; Algar, W. Russ; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G.; Medintz, Igor L.

2013-11-01

Integrating photonic inputs/outputs into unimolecular logic devices can provide significantly increased functional complexity and the ability to expand the repertoire of available operations. Here, we build upon a system previously utilized for biosensing to assemble and prototype several increasingly sophisticated biophotonic logic devices that function based upon multistep Förster resonance energy transfer (FRET) relays. The core system combines a central semiconductor quantum dot (QD) nanoplatform with a long-lifetime Tb complex FRET donor and a near-IR organic fluorophore acceptor; the latter acts as two unique inputs for the QD-based device. The Tb complex allows for a form of temporal memory by providing unique access to a time-delayed modality as an alternate output which significantly increases the inherent computing options. Altering the device by controlling the configuration parameters with biologically based self-assembly provides input control while monitoring changes in emission output of all participants, in both a spectral and temporal-dependent manner, gives rise to two input, single output Boolean Logic operations including OR, AND, INHIBIT, XOR, NOR, NAND, along with the possibility of gate transitions. Incorporation of an enzymatic cleavage step provides for a set-reset function that can be implemented repeatedly with the same building blocks and is demonstrated with single input, single output YES and NOT gates. Potential applications for these devices are discussed in the context of their constituent parts and the richness of available signal.

Biophotonic logic devices based on quantum dots and temporally-staggered Förster energy transfer relays.

PubMed

Claussen, Jonathan C; Algar, W Russ; Hildebrandt, Niko; Susumu, Kimihiro; Ancona, Mario G; Medintz, Igor L

2013-12-21

Integrating photonic inputs/outputs into unimolecular logic devices can provide significantly increased functional complexity and the ability to expand the repertoire of available operations. Here, we build upon a system previously utilized for biosensing to assemble and prototype several increasingly sophisticated biophotonic logic devices that function based upon multistep Förster resonance energy transfer (FRET) relays. The core system combines a central semiconductor quantum dot (QD) nanoplatform with a long-lifetime Tb complex FRET donor and a near-IR organic fluorophore acceptor; the latter acts as two unique inputs for the QD-based device. The Tb complex allows for a form of temporal memory by providing unique access to a time-delayed modality as an alternate output which significantly increases the inherent computing options. Altering the device by controlling the configuration parameters with biologically based self-assembly provides input control while monitoring changes in emission output of all participants, in both a spectral and temporal-dependent manner, gives rise to two input, single output Boolean Logic operations including OR, AND, INHIBIT, XOR, NOR, NAND, along with the possibility of gate transitions. Incorporation of an enzymatic cleavage step provides for a set-reset function that can be implemented repeatedly with the same building blocks and is demonstrated with single input, single output YES and NOT gates. Potential applications for these devices are discussed in the context of their constituent parts and the richness of available signal.

Multi-input and binary reproducible, high bandwidth floating point adder in a collective network

DOEpatents

Chen, Dong; Eisley, Noel A.; Heidelberger, Philip; Steinmacher-Burow, Burkhard

2016-11-15

To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to the collective logic device and receive outputs only once from the collective logic device.

Spintronic logic: from switching devices to computing systems

NASA Astrophysics Data System (ADS)

Friedman, Joseph S.

2017-09-01

Though numerous spintronic switching devices have been proposed or demonstrated, there has been significant difficulty in translating these advances into practical computing systems. The challenge of cascading has impeded the integration of multiple devices into a logic family, and several proposed solutions potentially overcome these challenges. Here, the cascading techniques by which the output of each spintronic device can drive the input of another device are described for several logic families, including spin-diode logic (in particular, all-carbon spin logic), complementary magnetic tunnel junction logic (CMAT), and emitter-coupled spin-transistor logic (ECSTL).

Multiple logic functions from extended blockade region in a silicon quantum-dot transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Youngmin; Lee, Sejoon, E-mail: sejoon@dongguk.edu; Im, Hyunsik

2015-02-14

We demonstrate multiple logic-functions at room temperature on a unit device of the Si single electron transistor (SET). Owing to the formation of the multi-dot system, the device exhibits the enhanced Coulomb blockade characteristics (e.g., large peak-to-valley current ratio ∼200) that can improve the reliability of the SET-based logic circuits. The SET displays a unique feature useful for the logic applications; namely, the Coulomb oscillation peaks are systematically shifted by changing either of only the gate or the drain voltage. This enables the SET to act as a multi-functional one-transistor logic gate with AND, OR, NAND, and XOR functions.

Non-volatile logic gates based on planar Hall effect in magnetic films with two in-plane easy axes.

PubMed

Lee, Sangyeop; Bac, Seul-Ki; Choi, Seonghoon; Lee, Hakjoon; Yoo, Taehee; Lee, Sanghoon; Liu, Xinyu; Dobrowolska, M; Furdyna, Jacek K

2017-04-25

We discuss the use of planar Hall effect (PHE) in a ferromagnetic GaMnAs film with two in-plane easy axes as a means for achieving novel logic functionalities. We show that the switching of magnetization between the easy axes in a GaMnAs film depends strongly on the magnitude of the current flowing through the film due to thermal effects that modify its magnetic anisotropy. Planar Hall resistance in a GaMnAs film with two in-plane easy axes shows well-defined maxima and minima that can serve as two binary logic states. By choosing appropriate magnitudes of the input current for the GaMnAs Hall device, magnetic logic functions can then be achieved. Specifically, non-volatile logic functionalities such as AND, OR, NAND, and NOR gates can be obtained in such a device by selecting appropriate initial conditions. These results, involving a simple PHE device, hold promise for realizing programmable logic elements in magnetic electronics.

N channel JFET based digital logic gate structure

NASA Technical Reports Server (NTRS)

Krasowski, Michael J. (Inventor)

2010-01-01

A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.

Excitonic AND Logic Gates on DNA Brick Nanobreadboards.

PubMed

Cannon, Brittany L; Kellis, Donald L; Davis, Paul H; Lee, Jeunghoon; Kuang, Wan; Hughes, William L; Graugnard, Elton; Yurke, Bernard; Knowlton, William B

2015-03-18

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems.

Excitonic AND Logic Gates on DNA Brick Nanobreadboards

PubMed Central

2015-01-01

A promising application of DNA self-assembly is the fabrication of chromophore-based excitonic devices. DNA brick assembly is a compelling method for creating programmable nanobreadboards on which chromophores may be rapidly and easily repositioned to prototype new excitonic devices, optimize device operation, and induce reversible switching. Using DNA nanobreadboards, we have demonstrated each of these functions through the construction and operation of two different excitonic AND logic gates. The modularity and high chromophore density achievable via this brick-based approach provide a viable path toward developing information processing and storage systems. PMID:25839049

Multi-input and binary reproducible, high bandwidth floating point adder in a collective network

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Dong; Eisley, Noel A; Heidelberger, Philip

To add floating point numbers in a parallel computing system, a collective logic device receives the floating point numbers from computing nodes. The collective logic devices converts the floating point numbers to integer numbers. The collective logic device adds the integer numbers and generating a summation of the integer numbers. The collective logic device converts the summation to a floating point number. The collective logic device performs the receiving, the converting the floating point numbers, the adding, the generating and the converting the summation in one pass. One pass indicates that the computing nodes send inputs only once to themore » collective logic device and receive outputs only once from the collective logic device.« less

Local rollback for fault-tolerance in parallel computing systems

DOEpatents

Blumrich, Matthias A [Yorktown Heights, NY; Chen, Dong [Yorktown Heights, NY; Gara, Alan [Yorktown Heights, NY; Giampapa, Mark E [Yorktown Heights, NY; Heidelberger, Philip [Yorktown Heights, NY; Ohmacht, Martin [Yorktown Heights, NY; Steinmacher-Burow, Burkhard [Boeblingen, DE; Sugavanam, Krishnan [Yorktown Heights, NY

2012-01-24

A control logic device performs a local rollback in a parallel super computing system. The super computing system includes at least one cache memory device. The control logic device determines a local rollback interval. The control logic device runs at least one instruction in the local rollback interval. The control logic device evaluates whether an unrecoverable condition occurs while running the at least one instruction during the local rollback interval. The control logic device checks whether an error occurs during the local rollback. The control logic device restarts the local rollback interval if the error occurs and the unrecoverable condition does not occur during the local rollback interval.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

A DNA Logic Gate Automaton for Detection of Rabies and Other Lyssaviruses.

PubMed

Vijayakumar, Pavithra; Macdonald, Joanne

2017-07-05

Immediate activation of biosensors is not always desirable, particularly if activation is due to non-specific interactions. Here we demonstrate the use of deoxyribozyme-based logic gate networks arranged into visual displays to precisely control activation of biosensors, and demonstrate a prototype molecular automaton able to discriminate between seven different genotypes of Lyssaviruses, including Rabies virus. The device uses novel mixed-base logic gates to enable detection of the large diversity of Lyssavirus sequence populations, while an ANDNOT logic gate prevents non-specific activation across genotypes. The resultant device provides a user-friendly digital-like, but molecule-powered, dot-matrix text output for unequivocal results read-out that is highly relevant for point of care applications. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.

PubMed

Dathbun, Ajjiporn; Kim, Youngchan; Kim, Seongchan; Yoo, Youngjae; Kang, Moon Sung; Lee, Changgu; Cho, Jeong Ho

2017-05-10

We demonstrated the fabrication of large-area ReS 2 transistors and logic gates composed of a chemical vapor deposition (CVD)-grown multilayer ReS 2 semiconductor channel and graphene electrodes. Single-layer graphene was used as the source/drain and coplanar gate electrodes. An ion gel with an ultrahigh capacitance effectively gated the ReS 2 channel at a low voltage, below 2 V, through a coplanar gate. The contact resistance of the ion gel-gated ReS 2 transistors with graphene electrodes decreased dramatically compared with the SiO 2 -devices prepared with Cr electrodes. The resulting transistors exhibited good device performances, including a maximum electron mobility of 0.9 cm 2 /(V s) and an on/off current ratio exceeding 10 4 . NMOS logic devices, such as NOT, NAND, and NOR gates, were assembled using the resulting transistors as a proof of concept demonstration of the applicability of the devices to complex logic circuits. The large-area synthesis of ReS 2 semiconductors and graphene electrodes and their applications in logic devices open up new opportunities for realizing future flexible electronics based on 2D nanomaterials.

Upper-Bound Estimates Of SEU in CMOS

NASA Technical Reports Server (NTRS)

Edmonds, Larry D.

1990-01-01

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

77 FR 35107 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-12

... devices. CSX requests relief from 49 CFR 236.109 as it applies to variable timers within the program logic... program logic of the operating software. However, CSX notes that some microprocessor-based equipment have.../check sum/universal control number of the existing location specific application logic to the previously...

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Reversible logic elements as a new field of application of optical solitons

NASA Astrophysics Data System (ADS)

Maimistov, Andrei I.

1995-10-01

An analysis is made of the fundamental concepts of conservative logic. It is shown that the existing optical soliton switches can be converted into logic gates which act as conservative logic elements. A logic device of this type, based on a nonlinear fibre-optic directional coupler, is considered. Polarised solitons are used in this coupler. This use of solitons leads in a natural way to the desirability of developing conservative triple-valued logic.

Digital microfluidics: Droplet based logic gates

NASA Astrophysics Data System (ADS)

Cheow, Lih Feng; Yobas, Levent; Kwong, Dim-Lee

2007-01-01

The authors present microfluidic logic gates based on two-phase flows at low Reynold's number. The presence and the absence of a dispersed phase liquid (slug) in a continuous phase liquid represent 1 and 0, respectively. The working principle of these devices is based on the change in hydrodynamic resistance for a channel containing droplets. Logical operations including AND, OR, and NOT are demonstrated, and may pave the way for microfludic system automation and computation.

Enzyme-Based Logic Gates and Networks with Output Signals Analyzed by Various Methods.

PubMed

Katz, Evgeny

2017-07-05

The paper overviews various methods that are used for the analysis of output signals generated by enzyme-based logic systems. The considered methods include optical techniques (optical absorbance, fluorescence spectroscopy, surface plasmon resonance), electrochemical techniques (cyclic voltammetry, potentiometry, impedance spectroscopy, conductivity measurements, use of field effect transistor devices, pH measurements), and various mechanoelectronic methods (using atomic force microscope, quartz crystal microbalance). Although each of the methods is well known for various bioanalytical applications, their use in combination with the biomolecular logic systems is rather new and sometimes not trivial. Many of the discussed methods have been combined with the use of signal-responsive materials to transduce and amplify biomolecular signals generated by the logic operations. Interfacing of biocomputing logic systems with electronics and "smart" signal-responsive materials allows logic operations be extended to actuation functions; for example, stimulating molecular release and switchable features of bioelectronic devices, such as biofuel cells. The purpose of this review article is to emphasize the broad variability of the bioanalytical systems applied for signal transduction in biocomputing processes. All bioanalytical systems discussed in the article are exemplified with specific logic gates and multi-gate networks realized with enzyme-based biocatalytic cascades. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ultralow-voltage design of graphene PN junction quantum reflective switch transistor

NASA Astrophysics Data System (ADS)

Sohier, Thibault; Yu, Bin

2011-05-01

We propose the concept of a graphene-based quantum reflective switch (QRS) for low-power logic application. With the unique electronic properties of graphene, a tilted PN junction is used to implement logic switch function with 103 ON/OFF ratio. Carriers are reflected on an electrostatically induced potential step with strong incidence-angle-dependency due to the widening of classically forbidden energies. Optimized design of the device for ultralow-voltage operating has been conducted. The device is constantly ON with a turning-off gate voltage around 180 mV using thin HfO2 as the gate dielectric. The results suggest a class of logic switch devices operating with micropower dissipation.

The cognitive bases for the design of a new class of fuzzy logic controllers: The clearness transformation fuzzy logic controller

NASA Technical Reports Server (NTRS)

Sultan, Labib; Janabi, Talib

1992-01-01

This paper analyses the internal operation of fuzzy logic controllers as referenced to the human cognitive tasks of control and decision making. Two goals are targeted. The first goal focuses on the cognitive interpretation of the mechanisms employed in the current design of fuzzy logic controllers. This analysis helps to create a ground to explore the potential of enhancing the functional intelligence of fuzzy controllers. The second goal is to outline the features of a new class of fuzzy controllers, the Clearness Transformation Fuzzy Logic Controller (CT-FLC), whereby some new concepts are advanced to qualify fuzzy controllers as 'cognitive devices' rather than 'expert system devices'. The operation of the CT-FLC, as a fuzzy pattern processing controller, is explored, simulated, and evaluated.

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell

NASA Astrophysics Data System (ADS)

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-06-01

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr03169b

High-speed all-optical logic inverter based on stimulated Raman scattering in silicon nanocrystal.

PubMed

Sen, Mrinal; Das, Mukul K

2015-11-01

In this paper, we propose a new device architecture for an all-optical logic inverter (NOT gate), which is cascadable with a similar device. The inverter is based on stimulated Raman scattering in silicon nanocrystal waveguides, which are embedded in a silicon photonic crystal structure. The Raman response function of silicon nanocrystal is evaluated to explore the transfer characteristic of the inverter. A maximum product criterion for the noise margin is taken to analyze the cascadability of the inverter. The time domain response of the inverter, which explores successful inversion operation at 100 Gb/s, is analyzed. Propagation delay of the inverter is on the order of 5 ps, which is less than the delay in most of the electronic logic families as of today. Overall dimension of the device is around 755  μm ×15  μm, which ensures integration compatibility with the matured silicon industry.

Easy design of colorimetric logic gates based on nonnatural base pairing and controlled assembly of gold nanoparticles.

PubMed

Zhang, Li; Wang, Zhong-Xia; Liang, Ru-Ping; Qiu, Jian-Ding

2013-07-16

Utilizing the principles of metal-ion-mediated base pairs (C-Ag-C and T-Hg-T), the pH-sensitive conformational transition of C-rich DNA strand, and the ligand-exchange process triggered by DL-dithiothreitol (DTT), a system of colorimetric logic gates (YES, AND, INHIBIT, and XOR) can be rationally constructed based on the aggregation of the DNA-modified Au NPs. The proposed logic operation system is simple, which consists of only T-/C-rich DNA-modified Au NPs, and it is unnecessary to exquisitely design and alter the DNA sequence for different multiple molecular logic operations. The nonnatural base pairing combined with unique optical properties of Au NPs promises great potential in multiplexed ion sensing, molecular-scale computers, and other computational logic devices.

Memory hierarchy using row-based compression

DOEpatents

Loh, Gabriel H.; O'Connor, James M.

2016-10-25

A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.

Pressure driven digital logic in PDMS based microfluidic devices fabricated by multilayer soft lithography.

PubMed

Devaraju, Naga Sai Gopi K; Unger, Marc A

2012-11-21

Advances in microfluidics now allow an unprecedented level of parallelization and integration of biochemical reactions. However, one challenge still faced by the field has been the complexity and cost of the control hardware: one external pressure signal has been required for each independently actuated set of valves on chip. Using a simple post-modification to the multilayer soft lithography fabrication process, we present a new implementation of digital fluidic logic fully analogous to electronic logic with significant performance advances over the previous implementations. We demonstrate a novel normally closed static gain valve capable of modulating pressure signals in a fashion analogous to an electronic transistor. We utilize these valves to build complex fluidic logic circuits capable of arbitrary control of flows by processing binary input signals (pressure (1) and atmosphere (0)). We demonstrate logic gates and devices including NOT, NAND and NOR gates, bi-stable flip-flops, gated flip-flops (latches), oscillators, self-driven peristaltic pumps, delay flip-flops, and a 12-bit shift register built using static gain valves. This fluidic logic shows cascade-ability, feedback, programmability, bi-stability, and autonomous control capability. This implementation of fluidic logic yields significantly smaller devices, higher clock rates, simple designs, easy fabrication, and integration into MSL microfluidics.

A Memory-Based Programmable Logic Device Using Look-Up Table Cascade with Synchronous Static Random Access Memories

NASA Astrophysics Data System (ADS)

Nakamura, Kazuyuki; Sasao, Tsutomu; Matsuura, Munehiro; Tanaka, Katsumasa; Yoshizumi, Kenichi; Nakahara, Hiroki; Iguchi, Yukihiro

2006-04-01

A large-scale memory-technology-based programmable logic device (PLD) using a look-up table (LUT) cascade is developed in the 0.35-μm standard complementary metal oxide semiconductor (CMOS) logic process. Eight 64 K-bit synchronous SRAMs are connected to form an LUT cascade with a few additional circuits. The features of the LUT cascade include: 1) a flexible cascade connection structure, 2) multi phase pseudo asynchronous operations with synchronous static random access memory (SRAM) cores, and 3) LUT-bypass redundancy. This chip operates at 33 MHz in 8-LUT cascades at 122 mW. Benchmark results show that it achieves a comparable performance to field programmable gate array (FPGAs).

Reversible logic gates based on enzyme-biocatalyzed reactions and realized in flow cells: a modular approach.

PubMed

Fratto, Brian E; Katz, Evgeny

2015-05-18

Reversible logic gates, such as the double Feynman gate, Toffoli gate and Peres gate, with 3-input/3-output channels are realized using reactions biocatalyzed with enzymes and performed in flow systems. The flow devices are constructed using a modular approach, where each flow cell is modified with one enzyme that biocatalyzes one chemical reaction. The multi-step processes mimicking the reversible logic gates are organized by combining the biocatalytic cells in different networks. This work emphasizes logical but not physical reversibility of the constructed systems. Their advantages and disadvantages are discussed and potential use in biosensing systems, rather than in computing devices, is suggested. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A survey of advancements in nucleic acid-based logic gates and computing for applications in biotechnology and biomedicine.

PubMed

Wu, Cuichen; Wan, Shuo; Hou, Weijia; Zhang, Liqin; Xu, Jiehua; Cui, Cheng; Wang, Yanyue; Hu, Jun; Tan, Weihong

2015-03-04

Nucleic acid-based logic devices were first introduced in 1994. Since then, science has seen the emergence of new logic systems for mimicking mathematical functions, diagnosing disease and even imitating biological systems. The unique features of nucleic acids, such as facile and high-throughput synthesis, Watson-Crick complementary base pairing, and predictable structures, together with the aid of programming design, have led to the widespread applications of nucleic acids (NA) for logic gate and computing in biotechnology and biomedicine. In this feature article, the development of in vitro NA logic systems will be discussed, as well as the expansion of such systems using various input molecules for potential cellular, or even in vivo, applications.

A Survey of Advancements in Nucleic Acid-based Logic Gates and Computing for Applications in Biotechnology and biomedicine

PubMed Central

Wu, Cuichen; Wan, Shuo; Hou, Weijia; Zhang, Liqin; Xu, Jiehua; Cui, Cheng; Wang, Yanyue; Hu, Jun

2015-01-01

Nucleic acid-based logic devices were first introduced in 1994. Since then, science has seen the emergence of new logic systems for mimicking mathematical functions, diagnosing disease and even imitating biological systems. The unique features of nucleic acids, such as facile and high-throughput synthesis, Watson-Crick complementary base pairing, and predictable structures, together with the aid of programming design, have led to the widespread applications of nucleic acids (NA) for logic gating and computing in biotechnology and biomedicine. In this feature article, the development of in vitro NA logic systems will be discussed, as well as the expansion of such systems using various input molecules for potential cellular, or even in vivo, applications. PMID:25597946

Enzyme-based logic gates and circuits-analytical applications and interfacing with electronics.

PubMed

Katz, Evgeny; Poghossian, Arshak; Schöning, Michael J

2017-01-01

The paper is an overview of enzyme-based logic gates and their short circuits, with specific examples of Boolean AND and OR gates, and concatenated logic gates composed of multi-step enzyme-biocatalyzed reactions. Noise formation in the biocatalytic reactions and its decrease by adding a "filter" system, converting convex to sigmoid response function, are discussed. Despite the fact that the enzyme-based logic gates are primarily considered as components of future biomolecular computing systems, their biosensing applications are promising for immediate practical use. Analytical use of the enzyme logic systems in biomedical and forensic applications is discussed and exemplified with the logic analysis of biomarkers of various injuries, e.g., liver injury, and with analysis of biomarkers characteristic of different ethnicity found in blood samples on a crime scene. Interfacing of enzyme logic systems with modified electrodes and semiconductor devices is discussed, giving particular attention to the interfaces functionalized with signal-responsive materials. Future perspectives in the design of the biomolecular logic systems and their applications are discussed in the conclusion. Graphical Abstract Various applications and signal-transduction methods are reviewed for enzyme-based logic systems.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

PubMed Central

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-01-01

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

PubMed

Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

2016-04-13

The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

Assurance of Complex Electronics. What Path Do We Take?

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array.

PubMed

Zhou, Ya-Xiong; Li, Yi; Su, Yu-Ting; Wang, Zhuo-Rui; Shih, Ling-Yi; Chang, Ting-Chang; Chang, Kuan-Chang; Long, Shi-Bing; Sze, Simon M; Miao, Xiang-Shui

2017-05-25

Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO 2 -based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.

Universal programmable logic gate and routing method

NASA Technical Reports Server (NTRS)

Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Mojarradi, Mohammad M. (Inventor); Fijany, Amir (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Toomarian, Nikzad (Inventor)

2009-01-01

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Engineering modular and orthogonal genetic logic gates for robust digital-like synthetic biology.

PubMed

Wang, Baojun; Kitney, Richard I; Joly, Nicolas; Buck, Martin

2011-10-18

Modular and orthogonal genetic logic gates are essential for building robust biologically based digital devices to customize cell signalling in synthetic biology. Here we constructed an orthogonal AND gate in Escherichia coli using a novel hetero-regulation module from Pseudomonas syringae. The device comprises two co-activating genes hrpR and hrpS controlled by separate promoter inputs, and a σ(54)-dependent hrpL promoter driving the output. The hrpL promoter is activated only when both genes are expressed, generating digital-like AND integration behaviour. The AND gate is demonstrated to be modular by applying new regulated promoters to the inputs, and connecting the output to a NOT gate module to produce a combinatorial NAND gate. The circuits were assembled using a parts-based engineering approach of quantitative characterization, modelling, followed by construction and testing. The results show that new genetic logic devices can be engineered predictably from novel native orthogonal biological control elements using quantitatively in-context characterized parts. © 2011 Macmillan Publishers Limited. All rights reserved.

Digital Device Architecture and the Safe Use of Flash Devices in Munitions

NASA Technical Reports Server (NTRS)

Katz, Richard B.; Flowers, David; Bergevin, Keith

2017-01-01

Flash technology is being utilized in fuzed munition applications and, based on the development of digital logic devices in the commercial world, usage of flash technology will increase. Digital devices of interest to designers include flash-based microcontrollers and field programmable gate arrays (FPGAs). Almost a decade ago, a study was undertaken to determine if flash-based microcontrollers could be safely used in fuzes and, if so, how should such devices be applied. The results were documented in the Technical Manual for the Use of Logic Devices in Safety Features. This paper will first review the Technical Manual and discuss the rationale behind the suggested architectures for microcontrollers and a brief review of the concern about data retention in flash cells. An architectural feature in the microcontroller under study will be discussed and its use will show how to screen for weak or failed cells during manufacture, storage, or immediately prior to use. As was done for microcontrollers a decade ago, architectures for a flash-based FPGA will be discussed, showing how it can be safely used in fuzes. Additionally, architectures for using non-volatile (including flash-based) storage will be discussed for SRAM-based FPGAs.

Poly-4-vinylphenol (PVP) and Poly(melamine-co-formaldehyde) (PMF)-Based Atomic Switching Device and Its Application to Logic Gate Circuits with Low Operating Voltage.

PubMed

Kang, Dong-Ho; Choi, Woo-Young; Woo, Hyunsuk; Jang, Sungkyu; Park, Hyung-Youl; Shim, Jaewoo; Choi, Jae-Woong; Kim, Sungho; Jeon, Sanghun; Lee, Sungjoo; Park, Jin-Hong

2017-08-16

In this study, we demonstrate a high-performance solid polymer electrolyte (SPE) atomic switching device with low SET/RESET voltages (0.25 and -0.5 V, respectively), high on/off-current ratio (10 5 ), excellent cyclic endurance (>10 3 ), and long retention time (>10 4 s), where poly-4-vinylphenol (PVP)/poly(melamine-co-formaldehyde) (PMF) is used as an SPE layer. To accomplish these excellent device performance parameters, we reduce the off-current level of the PVP/PMF atomic switching device by improving the electrical insulating property of the PVP/PMF electrolyte through adjustment of the number of cross-linked chains. We then apply a titanium buffer layer to the PVP/PMF switching device for further improvement of bipolar switching behavior and device stability. In addition, we first implement SPE atomic switch-based logic AND and OR circuits with low operating voltages below 2 V by integrating 5 × 5 arrays of PVP/PMF switching devices on the flexible substrate. In particular, this low operating voltage of our logic circuits was much lower than that (>5 V) of the circuits configured by polymer resistive random access memory. This research successfully presents the feasibility of PVP/PMF atomic switches for flexible integrated circuits for next-generation electronic applications.

Logic and memory concepts for all-magnetic computing based on transverse domain walls

NASA Astrophysics Data System (ADS)

Vandermeulen, J.; Van de Wiele, B.; Dupré, L.; Van Waeyenberge, B.

2015-06-01

We introduce a non-volatile digital logic and memory concept in which the binary data is stored in the transverse magnetic domain walls present in in-plane magnetized nanowires with sufficiently small cross sectional dimensions. We assign the digital bit to the two possible orientations of the transverse domain wall. Numerical proofs-of-concept are presented for a NOT-, AND- and OR-gate, a FAN-out as well as a reading and writing device. Contrary to the chirality based vortex domain wall logic gates introduced in Omari and Hayward (2014 Phys. Rev. Appl. 2 044001), the presented concepts remain applicable when miniaturized and are driven by electrical currents, making the technology compatible with the in-plane racetrack memory concept. The individual devices can be easily combined to logic networks working with clock speeds that scale linearly with decreasing design dimensions. This opens opportunities to an all-magnetic computing technology where the digital data is stored and processed under the same magnetic representation.

Logic circuit prototypes for three-terminal magnetic tunnel junctions with mobile domain walls

PubMed Central

Currivan-Incorvia, J. A.; Siddiqui, S.; Dutta, S.; Evarts, E. R.; Zhang, J.; Bono, D.; Ross, C. A.; Baldo, M. A.

2016-01-01

Spintronic computing promises superior energy efficiency and nonvolatility compared to conventional field-effect transistor logic. But, it has proven difficult to realize spintronic circuits with a versatile, scalable device design that is adaptable to emerging material physics. Here we present prototypes of a logic device that encode information in the position of a magnetic domain wall in a ferromagnetic wire. We show that a single three-terminal device can perform inverter and buffer operations. We demonstrate one device can drive two subsequent gates and logic propagation in a circuit of three inverters. This prototype demonstration shows that magnetic domain wall logic devices have the necessary characteristics for future computing, including nonlinearity, gain, cascadability, and room temperature operation. PMID:26754412

Realisation of all 16 Boolean logic functions in a single magnetoresistance memory cell.

PubMed

Gao, Shuang; Yang, Guang; Cui, Bin; Wang, Shouguo; Zeng, Fei; Song, Cheng; Pan, Feng

2016-07-07

Stateful logic circuits based on next-generation nonvolatile memories, such as magnetoresistance random access memory (MRAM), promise to break the long-standing von Neumann bottleneck in state-of-the-art data processing devices. For the successful commercialisation of stateful logic circuits, a critical step is realizing the best use of a single memory cell to perform logic functions. In this work, we propose a method for implementing all 16 Boolean logic functions in a single MRAM cell, namely a magnetoresistance (MR) unit. Based on our experimental results, we conclude that this method is applicable to any MR unit with a double-hump-like hysteresis loop, especially pseudo-spin-valve magnetic tunnel junctions with a high MR ratio. Moreover, after simply reversing the correspondence between voltage signals and output logic values, this method could also be applicable to any MR unit with a double-pit-like hysteresis loop. These results may provide a helpful solution for the final commercialisation of MRAM-based stateful logic circuits in the near future.

Principle and experimental investigation of current-driven negative-inductance superconducting quantum interference device

NASA Astrophysics Data System (ADS)

Li, Hao; Liu, Jianshe; Zhang, Yingshan; Cai, Han; Li, Gang; Liu, Qichun; Han, Siyuan; Chen, Wei

2017-03-01

A negative-inductance superconducting quantum interference device (nSQUID) is an adiabatic superconducting logic device with high energy efficiency, and therefore a promising building block for large-scale low-power superconducting computing. However, the principle of the nSQUID is not that straightforward and an nSQUID driven by voltage is vulnerable to common mode noise. We investigate a single nSQUID driven by current instead of voltage, and clarify the principle of the adiabatic transition of the current-driven nSQUID between different states. The basic logic operations of the current-driven nSQUID with proper parameters are simulated by WRspice. The corresponding circuit is fabricated with a 100 A cm-2 Nb-based lift-off process, and the experimental results at low temperature confirm the basic logic operations as a gated buffer.

Electrically reconfigurable logic array

NASA Technical Reports Server (NTRS)

Agarwal, R. K.

1982-01-01

To compose the complicated systems using algorithmically specialized logic circuits or processors, one solution is to perform relational computations such as union, division and intersection directly on hardware. These relations can be pipelined efficiently on a network of processors having an array configuration. These processors can be designed and implemented with a few simple cells. In order to determine the state-of-the-art in Electrically Reconfigurable Logic Array (ERLA), a survey of the available programmable logic array (PLA) and the logic circuit elements used in such arrays was conducted. Based on this survey some recommendations are made for ERLA devices.

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

PubMed Central

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-01

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

PubMed

Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-27

Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

Analysis of the logic and framing of a tobacco industry campaign opposing standardised packaging legislation in New Zealand.

PubMed

Waa, Andrew Morehu; Hoek, Janet; Edwards, Richard; Maclaurin, James

2017-11-01

The tobacco industry routinely opposes tobacco control policies, often using a standard repertoire of arguments. Following proposals to introduce standardised packaging in New Zealand (NZ), British American Tobacco New Zealand (BATNZ) launched the 'Agree-Disagree' mass media campaign, which coincided with the NZ government's standardised packaging consultations. This study examined the logic of the arguments presented and rhetorical strategies employed in the campaign. We analysed each advertisement to identify key messages, arguments and rhetorical devices, then examined the arguments' structure and assessed their logical soundness and validity. All advertisements attempted to frame BATNZ as reasonable, and each contained flawed arguments that were either unsound or based on logical fallacies. Flawed arguments included misrepresenting the intent of the proposed legislation (straw man), claiming standardised packaging would harm all NZ brands (false dilemma), warning NZ not to adopt standardised packaging because of its Australian origins (an unsound argument) or using vague premises as a basis for claiming negative outcomes (equivocation). BATNZ's Agree-Disagree campaign relied on unsound arguments, logical fallacies and rhetorical devices. Given the industry's frequent recourse to these tactics, we propose strategies based on our study findings that can be used to assist the tobacco control community to counter industry opposition to standardised packaging. Greater recognition of logical fallacies and rhetorical devices employed by the tobacco industry will help maintain focus on the health benefits proposed policies will deliver. Published by the BMJ Publishing Group Limited. For permission to use (where not already granted under a licence) please go to http://www.bmj.com/company/products-services/rights-and-licensing/.

Linear and passive silicon diodes, isolators, and logic gates

NASA Astrophysics Data System (ADS)

Li, Zhi-Yuan

2013-12-01

Silicon photonic integrated devices and circuits have offered a promising means to revolutionalize information processing and computing technologies. One important reason is that these devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processing technology that overwhelms current microelectronics industry. Yet, the dream to build optical computers has yet to come without the breakthrough of several key elements including optical diodes, isolators, and logic gates with low power, high signal contrast, and large bandwidth. Photonic crystal has a great power to mold the flow of light in micrometer/nanometer scale and is a promising platform for optical integration. In this paper we present our recent efforts of design, fabrication, and characterization of ultracompact, linear, passive on-chip optical diodes, isolators and logic gates based on silicon two-dimensional photonic crystal slabs. Both simulation and experiment results show high performance of these novel designed devices. These linear and passive silicon devices have the unique properties of small fingerprint, low power request, large bandwidth, fast response speed, easy for fabrication, and being compatible with COMS technology. Further improving their performance would open up a road towards photonic logics and optical computing and help to construct nanophotonic on-chip processor architectures for future optical computers.

Error-Transparent Quantum Gates for Small Logical Qubit Architectures

NASA Astrophysics Data System (ADS)

Kapit, Eliot

2018-02-01

One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016), 10.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.

Quantum logic gates based on ballistic transport in graphene

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dragoman, Daniela; Academy of Romanian Scientists, Splaiul Independentei 54, 050094 Bucharest; Dragoman, Mircea, E-mail: mircea.dragoman@imt.ro

2016-03-07

The paper presents various configurations for the implementation of graphene-based Hadamard, C-phase, controlled-NOT, and Toffoli gates working at room temperature. These logic gates, essential for any quantum computing algorithm, involve ballistic graphene devices for qubit generation and processing and can be fabricated using existing nanolithographical techniques. All quantum gate configurations are based on the very large mean-free-paths of carriers in graphene at room temperature.

All-optical XNOR/NOT logic gates and LATCH based on a reflective vertical cavity semiconductor saturable absorber.

PubMed

Pradhan, Rajib

2014-06-10

This work proposes a scheme of all-optical XNOR/NOT logic gates based on a reflective vertical cavity semiconductor (quantum wells, QWs) saturable absorber (VCSSA). In a semiconductor Fabry-Perot cavity operated with a low-intensity resonance wavelength, both intensity-dependent saturating phase-shift and thermal phase-shift occur, which are considered in the proposed logic operations. The VCSSA-based logics are possible using the saturable behavior of reflectivity under the typical operating conditions. The low-intensity saturable reflectivity is reported for all-optical logic operations where all possible nonlinear phase-shifts are ignored. Here, saturable absorption (SA) and the nonlinear phase-shift-based all-optical XNOR/NOT gates and one-bit memory or LATCH are proposed under new operating conditions. All operations are demonstrated for a VCSSA based on InGaAs/InP QWs. These types of SA-based logic devices can be comfortably used for a signal bit rate of about 10 GHz corresponding to the carrier recovery time of the semiconductor material.

Current-limiting challenges for all-spin logic devices

PubMed Central

Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

2015-01-01

All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

Filling the Assurance Gap on Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Software Process Assurance for Complex Electronics

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2008-01-01

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

General purpose programmable accelerator board

DOEpatents

Robertson, Perry J.; Witzke, Edward L.

2001-01-01

A general purpose accelerator board and acceleration method comprising use of: one or more programmable logic devices; a plurality of memory blocks; bus interface for communicating data between the memory blocks and devices external to the board; and dynamic programming capabilities for providing logic to the programmable logic device to be executed on data in the memory blocks.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, Dinesh; Thapliyal, Himanshu; Mohammad, Azhar

Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs.more » Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPAresistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for lowpower portable electronic devices and Internet-of-Things (IoT) based electronic devices.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.

With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in themore » photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an encrypting/scrambling algorithm based on a study of candidate encryption algorithms. Demonstration circuits show how these logic elements can be used to form NAND, NOR, and XOR functions. This paper also presents functional analysis of a serial, low gate count demonstration algorithm suitable for scrambling/encryption using S-SEED devices.« less

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulle; Robinson, Daryl C.; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel translators and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. Furthermore, the ability to form devices on flexible substrates expands the range of applications where electronic circuitry can be introduced. For NASA, nonotechndogy offers opportunities for increased onboard data processing and thus autonomous decision-making ability, ad novel sensors that detect and respond to external stimuli with few oversight requirements. The goat of this work is to demonstrate transistor behavior in polyaniline/ polyethylene oxide nanofibers, thus creating a foundation for future logic devices.

Integrated all-optical programmable logic array based on semiconductor optical amplifiers.

PubMed

Dong, Wenchan; Huang, Zhuyang; Hou, Jie; Santos, Rui; Zhang, Xinliang

2018-05-01

The all-optical programmable logic array (PLA) is one of the most important optical complex logic devices that can implement combinational logic functions. In this Letter, we propose and experimentally demonstrate an integrated all-optical PLA at the operation speed of 40 Gb/s. The PLA mainly consists of a delay interferometer (DI) and semiconductor optical amplifiers (SOAs) of different lengths. The DI is used to pre-code the input signals and improve the reconfigurability of the scheme. The longer SOAs are nonlinear media for generating canonical logic units (CLUs) using four-wave mixing. The shorter SOAs are used to select the appropriate CLUs by changing the working states; then reconfigurable logic functions can be output directly. The results show that all the CLUs are realized successfully, and the optical signal-to-noise ratios are above 22 dB. The exclusive NOR gate and exclusive OR gate are experimentally demonstrated based on output CLUs.

Multi-valued logic gates based on ballistic transport in quantum point contacts.

PubMed

Seo, M; Hong, C; Lee, S-Y; Choi, H K; Kim, N; Chung, Y; Umansky, V; Mahalu, D

2014-01-22

Multi-valued logic gates, which can handle quaternary numbers as inputs, are developed by exploiting the ballistic transport properties of quantum point contacts in series. The principle of a logic gate that finds the minimum of two quaternary number inputs is demonstrated. The device is scalable to allow multiple inputs, which makes it possible to find the minimum of multiple inputs in a single gate operation. Also, the principle of a half-adder for quaternary number inputs is demonstrated. First, an adder that adds up two quaternary numbers and outputs the sum of inputs is demonstrated. Second, a device to express the sum of the adder into two quaternary digits [Carry (first digit) and Sum (second digit)] is demonstrated. All the logic gates presented in this paper can in principle be extended to allow decimal number inputs with high quality QPCs.

Rule-based interface generation on mobile devices for structured documentation.

PubMed

Kock, Ann-Kristin; Andersen, Björn; Handels, Heinz; Ingenerf, Josef

2014-01-01

In many software systems to date, interactive graphical user interfaces (GUIs) are represented implicitly in the source code, together with the application logic. Hence, the re-use, development, and modification of these interfaces is often very laborious. Flexible adjustments of GUIs for various platforms and devices as well as individual user preferences are furthermore difficult to realize. These problems motivate a software-based separation of content and GUI models on the one hand, and application logic on the other. In this project, a software solution for structured reporting on mobile devices is developed. Clinical content archetypes developed in a previous project serve as the content model while the Android SDK provides the GUI model. The necessary bindings between the models are specified using the Jess Rule Language.

Light-Triggered Ternary Device and Inverter Based on Heterojunction of van der Waals Materials.

PubMed

Shim, Jaewoo; Jo, Seo-Hyeon; Kim, Minwoo; Song, Young Jae; Kim, Jeehwan; Park, Jin-Hong

2017-06-27

Multivalued logic (MVL) devices/circuits have received considerable attention because the binary logic used in current Si complementary metal-oxide-semiconductor (CMOS) technology cannot handle the predicted information throughputs and energy demands of the future. To realize MVL, the conventional transistor platform needs to be redesigned to have two or more distinctive threshold voltages (V TH s). Here, we report a finding: the photoinduced drain current in graphene/WSe 2 heterojunction transistors unusually decreases with increasing gate voltage under illumination, which we refer to as the light-induced negative differential transconductance (L-NDT) phenomenon. We also prove that such L-NDT phenomenon in specific bias ranges originates from a variable potential barrier at a graphene/WSe 2 junction due to a gate-controllable graphene electrode. This finding allows us to conceive graphene/WSe 2 -based MVL logic circuits by using the I D -V G characteristics with two distinctive V TH s. Based on this finding, we further demonstrate a light-triggered ternary inverter circuit with three stable logical states (ΔV out of each state <0.05 V). Our study offers the pathway to substantialize MVL systems.

High-performance all-printed amorphous oxide FETs and logics with electronically compatible electrode/ channel interface.

PubMed

Sharma, Bhupendra Kumar; Stoesser, Anna; Mondal, Sandeep Kumar; Garlapati, Suresh K; Fawey, Mohammed H; Chakravadhanula, Venkata Sai Kiran; Kruk, Robert; Hahn, Horst; Dasgupta, Subho

2018-06-12

Oxide semiconductors typically show superior device performance compared to amorphous silicon or organic counterparts, especially, when they are physical vapor deposited. However, it is not easy to reproduce identical device characteristics when the oxide field-effect transistors (FETs) are solution-processed/ printed; the level of complexity further intensifies with the need to print the passive elements as well. Here, we developed a protocol for designing the most electronically compatible electrode/ channel interface based on the judicious material selection. Exploiting this newly developed fabrication schemes, we are now able to demonstrate high-performance all-printed FETs and logic circuits using amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor, indium tin oxide (ITO) as electrodes and composite solid polymer electrolyte as the gate insulator. Interestingly, all-printed FETs demonstrate an optimal electrical performance in terms of threshold voltages and device mobility and may very well be compared with devices fabricated using sputtered ITO electrodes. This observation originates from the selection of electrode/ channel materials from the same transparent semiconductor oxide family, resulting in the formation of In-Sn-Zn-O (ITZO) based diffused a-IGZO/ ITO interface that controls doping density while ensuring high electrical performance. Compressive spectroscopic studies reveal that Sn doping mediated excellent band alignment of IGZO with ITO electrodes is responsible for the excellent device performance observed. All-printed n-MOS based logic circuits have also been demonstrated towards new-generation portable electronics.

Fuzzy logic modeling of high performance rechargeable batteries

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, P.; Fennie, C. Jr.; Reisner, D.E.

1998-07-01

Accurate battery state-of-charge (SOC) measurements are critical in many portable electronic device applications. Yet conventional techniques for battery SOC estimation are limited in their accuracy, reliability, and flexibility. In this paper the authors present a powerful new approach to estimate battery SOC using a fuzzy logic-based methodology. This approach provides a universally applicable, accurate method for battery SOC estimation either integrated within, or as an external monitor to, an electronic device. The methodology is demonstrated in modeling impedance measurements on Ni-MH cells and discharge voltage curves of Li-ion cells.

Challenges and opportunities with spin-based logic

NASA Astrophysics Data System (ADS)

Perricone, Robert; Niemier, Michael; Hu, X. Sharon

2017-09-01

In this paper, we provide a short overview of efforts to process information with spin as a state variable. We highlight initial efforts in spintronics where devices concepts such as spinwaves, field coupled nanomagnets, etc. were are considered as vehicles for processing information. We also highlight more recent work where spintronic logic and memory devices are considered in the context of information processing hardware for the internet of things (IoT), and where the ability to constantly "checkpoint" processor state can support computing in environments with unreliable power supplies.

A binary-decision-diagram-based two-bit arithmetic logic unit on a GaAs-based regular nanowire network with hexagonal topology.

PubMed

Zhao, Hong-Quan; Kasai, Seiya; Shiratori, Yuta; Hashizume, Tamotsu

2009-06-17

A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.

Design of a Ferroelectric Programmable Logic Gate Array

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

2003-01-01

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

Complex cellular logic computation using ribocomputing devices.

PubMed

Green, Alexander A; Kim, Jongmin; Ma, Duo; Silver, Pamela A; Collins, James J; Yin, Peng

2017-08-03

Synthetic biology aims to develop engineering-driven approaches to the programming of cellular functions that could yield transformative technologies. Synthetic gene circuits that combine DNA, protein, and RNA components have demonstrated a range of functions such as bistability, oscillation, feedback, and logic capabilities. However, it remains challenging to scale up these circuits owing to the limited number of designable, orthogonal, high-performance parts, the empirical and often tedious composition rules, and the requirements for substantial resources for encoding and operation. Here, we report a strategy for constructing RNA-only nanodevices to evaluate complex logic in living cells. Our 'ribocomputing' systems are composed of de-novo-designed parts and operate through predictable and designable base-pairing rules, allowing the effective in silico design of computing devices with prescribed configurations and functions in complex cellular environments. These devices operate at the post-transcriptional level and use an extended RNA transcript to co-localize all circuit sensing, computation, signal transduction, and output elements in the same self-assembled molecular complex, which reduces diffusion-mediated signal losses, lowers metabolic cost, and improves circuit reliability. We demonstrate that ribocomputing devices in Escherichia coli can evaluate two-input logic with a dynamic range up to 900-fold and scale them to four-input AND, six-input OR, and a complex 12-input expression (A1 AND A2 AND NOT A1*) OR (B1 AND B2 AND NOT B2*) OR (C1 AND C2) OR (D1 AND D2) OR (E1 AND E2). Successful operation of ribocomputing devices based on programmable RNA interactions suggests that systems employing the same design principles could be implemented in other host organisms or in extracellular settings.

Catalytic molecular logic devices by DNAzyme displacement.

PubMed

Brown, Carl W; Lakin, Matthew R; Stefanovic, Darko; Graves, Steven W

2014-05-05

Chemical reactions catalyzed by DNAzymes offer a route to programmable modification of biomolecules for therapeutic purposes. To this end, we have developed a new type of catalytic DNA-based logic gates in which DNAzyme catalysis is controlled via toehold-mediated strand displacement reactions. We refer to these as DNAzyme displacement gates. The use of toeholds to guide input binding provides a favorable pathway for input recognition, and the innate catalytic activity of DNAzymes allows amplification of nanomolar input concentrations. We demonstrate detection of arbitrary input sequences by rational introduction of mismatched bases into inhibitor strands. Furthermore, we illustrate the applicability of DNAzyme displacement to compute logic functions involving multiple logic gates. This work will enable sophisticated logical control of a range of biochemical modifications, with applications in pathogen detection and autonomous theranostics. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

High speed all optical logic gates based on quantum dot semiconductor optical amplifiers.

PubMed

Ma, Shaozhen; Chen, Zhe; Sun, Hongzhi; Dutta, Niloy K

2010-03-29

A scheme to realize all-optical Boolean logic functions AND, XOR and NOT using semiconductor optical amplifiers with quantum-dot active layers is studied. nonlinear dynamics including carrier heating and spectral hole-burning are taken into account together with the rate equations scheme. Results show with QD excited state and wetting layer serving as dual-reservoir of carriers, as well as the ultra fast carrier relaxation of the QD device, this scheme is suitable for high speed Boolean logic operations. Logic operation can be carried out up to speed of 250 Gb/s.

Proposal for nanoscale cascaded plasmonic majority gates for non-Boolean computation.

PubMed

Dutta, Sourav; Zografos, Odysseas; Gurunarayanan, Surya; Radu, Iuliana; Soree, Bart; Catthoor, Francky; Naeemi, Azad

2017-12-19

Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm 2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.

An iLab for Teaching Advanced Logic Concepts with Hardware Descriptive Languages

ERIC Educational Resources Information Center

Ayodele, Kayode P.; Inyang, Isaac A.; Kehinde, Lawrence O.

2015-01-01

One of the more interesting approaches to teaching advanced logic concepts is the use of online laboratory frameworks to provide student access to remote field-programmable devices. There is as yet, however, no conclusive evidence of the effectiveness of such an approach. This paper presents the Advanced Digital Lab, a remote laboratory based on…

Software Process Assurance for Complex Electronics (SPACE)

NASA Technical Reports Server (NTRS)

Plastow, Richard A.

2007-01-01

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

A Reversible DNA Logic Gate Platform Operated by One- and Two-Photon Excitations.

PubMed

Tam, Dick Yan; Dai, Ziwen; Chan, Miu Shan; Liu, Ling Sum; Cheung, Man Ching; Bolze, Frederic; Tin, Chung; Lo, Pik Kwan

2016-01-04

We demonstrate the use of two different wavelength ranges of excitation light as inputs to remotely trigger the responses of the self-assembled DNA devices (D-OR). As an important feature of this device, the dependence of the readout fluorescent signals on the two external inputs, UV excitation for 1 min and/or near infrared irradiation (NIR) at 800 nm fs laser pulses, can mimic function of signal communication in OR logic gates. Their operations could be reset easily to its initial state. Furthermore, these DNA devices exhibit efficient cellular uptake, low cytotoxicity, and high bio-stability in different cell lines. They are considered as the first example of a photo-responsive DNA logic gate system, as well as a biocompatible, multi-wavelength excited system in response to UV and NIR. This is an important step to explore the concept of photo-responsive DNA-based systems as versatile tools in DNA computing, display devices, optical communication, and biology. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Novel all-optical logic gate using an add/drop filter and intensity switch.

PubMed

Threepak, T; Mitatha, S; Yupapin, P P

2011-12-01

A novel design of all-optical logic device is proposed. An all-optical logic device system composes of an optical intensity switch and add/drop filter. The intensity switch is formed to switch signal by using the relationship between refraction angle and signal intensity. In operation, two input signals are coupled into one with some coupling loss and attenuation, in which the combination of add/drop with intensity switch produces the optical logic gate. The advantage is that the proposed device can operate the high speed logic function. Moreover, it uses low power consumption. Furthermore, by using the extremely small component, this design can be put into a single chip. Finally, we have successfully produced the all-optical logic gate that can generate the accurate AND and NOT operation results.

New trends in logic synthesis for both digital designing and data processing

NASA Astrophysics Data System (ADS)

Borowik, Grzegorz; Łuba, Tadeusz; Poźniak, Krzysztof

2016-09-01

FPGA devices are equipped with memory-based structures. These memories act as very large logic cells where the number of inputs equals the number of address lines. At the same time, there is a huge demand in the market of Internet of Things for devices implementing virtual routers, intrusion detection systems, etc.; where such memories are crucial for realizing pattern matching circuits, IP address tables, and other. Unfortunately, existing CAD tools are not well suited to utilize capabilities that such large memory blocks offer due to the lack of appropriate synthesis procedures. This paper presents methods which are useful for memory-based implementations: minimization of the number of input variables and functional decomposition.

Optoelectronic date acquisition system based on FPGA

NASA Astrophysics Data System (ADS)

Li, Xin; Liu, Chunyang; Song, De; Tong, Zhiguo; Liu, Xiangqing

2015-11-01

An optoelectronic date acquisition system is designed based on FPGA. FPGA chip that is EP1C3T144C8 of Cyclone devices from Altera corporation is used as the centre of logic control, XTP2046 chip is used as A/D converter, host computer that communicates with the date acquisition system through RS-232 serial communication interface are used as display device and photo resistance is used as photo sensor. We use Verilog HDL to write logic control code about FPGA. It is proved that timing sequence is correct through the simulation of ModelSim. Test results indicate that this system meets the design requirement, has fast response and stable operation by actual hardware circuit test.

Development of an optical parallel logic device and a half-adder circuit for digital optical processing

NASA Technical Reports Server (NTRS)

Athale, R. A.; Lee, S. H.

1978-01-01

The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

TAXONOMY OF MEDICAL DEVICES IN THE LOGIC OF HEALTH TECHNOLOGY ASSESSMENT.

PubMed

Henschke, Cornelia; Panteli, Dimitra; Perleth, Matthias; Busse, Reinhard

2015-01-01

The suitability of general HTA methodology for medical devices is gaining interest as a topic of scientific discourse. Given the broad range of medical devices, there might be differences between groups of devices that impact both the necessity and the methods of their assessment. Our aim is to develop a taxonomy that provides researchers and policy makers with an orientation tool on how to approach the assessment of different types of medical devices. Several classifications for medical devices based on varying rationales for different regulatory and reporting purposes were analyzed in detail to develop a comprehensive taxonomic model. The taxonomy is based on relevant aspects of existing classification schemes incorporating elements of risk and functionality. Its 9 × 6 matrix distinguishes between the diagnostic or therapeutic nature of devices and considers whether the medical device is directly used by patients, constitutes part of a specific procedure, or can be used for a variety of procedures. We considered the relevance of different device categories in regard to HTA to be considerably variable, ranging from high to low. Existing medical device classifications cannot be used for HTA as they are based on different underlying logics. The developed taxonomy combines different device classification schemes used for different purposes. It aims at providing decision makers with a tool enabling them to consider device characteristics in detail across more than one dimension. The placement of device groups in the matrix can provide decision support on the necessity of conducting a full HTA.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Code conversion from signed-digit to complement representation based on look-ahead optical logic operations

NASA Astrophysics Data System (ADS)

Li, Guoqiang; Qian, Feng

2001-11-01

We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to complement representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed- digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quarternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

21 CFR 866.5400 - Alpha-globulin immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5400 Alpha-globulin immuno-logical test system. (a) Identification. An alpha-globulin immunological... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Alpha-globulin immuno-logical test system. 866...

21 CFR 866.5380 - Free secretory component immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5380 Free secretory component immuno-logical test system. (a) Identification. A free... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Free secretory component immuno-logical test...

21 CFR 866.5350 - Fibrinopeptide A immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5350 Fibrinopeptide A immuno-logical test system. (a) Identification. A fibrinopeptide A immunological... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Fibrinopeptide A immuno-logical test system. 866...

The performativity of "media logic" in the mass mediation of science.

PubMed

Plesner, Ursula

2012-08-01

Studies of the use of research-based expertise in the mass media often demonstrate how experts are used to confirm journalists' angles on particular stories or how research-based knowledge claims are twisted. Both among practitioners and science communication scholars, such practices are often explained with reference to a pervasive "media logic." "Media logic" is constructed as governing choices and interactions of researchers and journalists. This article critically examines the extensive use of the term "media logic" to explain choices, changes or content in media production, and presents Actor-Network-Theory as an approach that invites us to ask what takes place in practice without resorting to such generalizing explanatory devices. The article argues that a quick jump to "media logic" as an explanation may imply that we forget its contingency and ignore what actually takes place in journalists' and researchers' negotiations about texts and facts in the mass mediation of science.

The effect of output-input isolation on the scaling and energy consumption of all-spin logic devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hu, Jiaxi; Haratipour, Nazila; Koester, Steven J., E-mail: skoester@umn.edu

All-spin logic (ASL) is a novel approach for digital logic applications wherein spin is used as the state variable instead of charge. One of the challenges in realizing a practical ASL system is the need to ensure non-reciprocity, meaning the information flows from input to output, not vice versa. One approach described previously, is to introduce an asymmetric ground contact, and while this approach was shown to be effective, it remains unclear as to the optimal approach for achieving non-reciprocity in ASL. In this study, we quantitatively analyze techniques to achieve non-reciprocity in ASL devices, and we specifically compare themore » effect of using asymmetric ground position and dipole-coupled output/input isolation. For this analysis, we simulate the switching dynamics of multiple-stage logic devices with FePt and FePd perpendicular magnetic anisotropy materials using a combination of a matrix-based spin circuit model coupled to the Landau–Lifshitz–Gilbert equation. The dipole field is included in this model and can act as both a desirable means of coupling magnets and a source of noise. The dynamic energy consumption has been calculated for these schemes, as a function of input/output magnet separation, and the results show that using a scheme that electrically isolates logic stages produces superior non-reciprocity, thus allowing both improved scaling and reduced energy consumption.« less

A mechanized process algebra for verification of device synchronization protocols

NASA Technical Reports Server (NTRS)

Schubert, E. Thomas

1992-01-01

We describe the formalization of a process algebra based on CCS within the Higher Order Logic (HOL) theorem-proving system. The representation of four types of device interactions and a correctness proof of the communication between a microprocessor and MMU is presented.

A novel architecture of non-volatile magnetic arithmetic logic unit using magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Guo, Wei; Prenat, Guillaume; Dieny, Bernard

2014-04-01

Complementary metal-oxide-semiconductor (CMOS) technology is facing increasingly difficult obstacles such as power consumption and interconnection delay. Novel hybrid technologies and architectures are being investigated with the aim to circumvent some of these limits. In particular, hybrid CMOS/magnetic technology based on magnetic tunnel junctions (MTJs) is considered as a very promising approach thanks to the full compatibility of MTJs with CMOS technology. By tightly merging the conventional electronics with magnetism, both logic and memory functions can be implemented in the same device. As a result, non-volatility is directly brought into logic circuits, yielding significant improvement of device performances and new functionalities as well. We have conceived an innovative methodology to construct non-volatile magnetic arithmetic logic units (MALUs) combining spin-transfer torque MTJs with MOS transistors. The present 4-bit MALU utilizes 4 MTJ pairs to store its operation code (opcode). Its operations and performances have been confirmed and evaluated through electrical simulations.

21 CFR 866.5270 - C-reactive protein immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5270 C-reactive protein immuno-logical test system. (a) Identification. A C-reactive protein... 21 Food and Drugs 8 2010-04-01 2010-04-01 false C-reactive protein immuno-logical test system. 866...

21 CFR 866.5360 - Cohn fraction IV immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5360 Cohn fraction IV immuno-logical test system. (a) Identification. A Cohn fraction IV immunological... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Cohn fraction IV immuno-logical test system. 866...

21 CFR 866.5580 - Alpha-1-lipoprotein immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5580 Alpha-1-lipoprotein immuno-logical test system. (a) Identification. An alpha-1-lipoprotein... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Alpha-1-lipoprotein immuno-logical test system...

Computing with volatile memristors: an application of non-pinched hysteresis

NASA Astrophysics Data System (ADS)

Pershin, Y. V.; Shevchenko, S. N.

2017-02-01

The possibility of in-memory computing with volatile memristive devices, namely, memristors requiring a power source to sustain their memory, is demonstrated theoretically. We have adopted a hysteretic graphene-based field emission structure as a prototype of a volatile memristor, which is characterized by a non-pinched hysteresis loop. A memristive model of the structure is developed and used to simulate a polymorphic circuit implementing stateful logic gates, such as the material implication. Specific regions of parameter space realizing useful logic functions are identified. Our results are applicable to other realizations of volatile memory devices, such as certain NEMS switches.

Interconnected magnetic tunnel junctions for spin-logic applications

NASA Astrophysics Data System (ADS)

Manfrini, Mauricio; Vaysset, Adrien; Wan, Danny; Raymenants, Eline; Swerts, Johan; Rao, Siddharth; Zografos, Odysseas; Souriau, Laurent; Gavan, Khashayar Babaei; Rassoul, Nouredine; Radisic, Dunja; Cupak, Miroslav; Dehan, Morin; Sayan, Safak; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Mocuta, Dan; Radu, Iuliana P.

2018-05-01

With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free layer and its propagation towards the output pillar sensed by tunneling magneto-resistance. Domain pinning conditions are studied quasi-statically showing a strong dependence on pillar size, ferromagnetic free layer width and inter-pillar distance. Addressing pinning conditions are detrimental for cascading and fan-out of domain walls across nodes, enabling the realization of domain-wall-based logic technology.

Optical NOR logic gate design on square lattice photonic crystal platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

D’souza, Nirmala Maria, E-mail: nirmala@cukerala.ac.in; Mathew, Vincent, E-mail: vincent@cukerala.ac.in

We numerically demonstrate a new configuration of all-optical NOR logic gate with square lattice photonic crystal (PhC) waveguide using finite difference time domain (FDTD) method. The logic operations are based on interference effect of optical waves. We have determined the operating frequency range by calculating the band structure for a perfectly periodic PhC using plane wave expansion (PWE) method. Response time of this logic gate is 1.98 ps and it can be operated with speed about 513 GB/s. The proposed device consists of four linear waveguides and a square ring resonator waveguides on PhC platform.

Field-Free Programmable Spin Logics via Chirality-Reversible Spin-Orbit Torque Switching.

PubMed

Wang, Xiao; Wan, Caihua; Kong, Wenjie; Zhang, Xuan; Xing, Yaowen; Fang, Chi; Tao, Bingshan; Yang, Wenlong; Huang, Li; Wu, Hao; Irfan, Muhammad; Han, Xiufeng

2018-06-21

Spin-orbit torque (SOT)-induced magnetization switching exhibits chirality (clockwise or counterclockwise), which offers the prospect of programmable spin-logic devices integrating nonvolatile spintronic memory cells with logic functions. Chirality is usually fixed by an applied or effective magnetic field in reported studies. Herein, utilizing an in-plane magnetic layer that is also switchable by SOT, the chirality of a perpendicular magnetic layer that is exchange-coupled with the in-plane layer can be reversed in a purely electrical way. In a single Hall bar device designed from this multilayer structure, three logic gates including AND, NAND, and NOT are reconfigured, which opens a gateway toward practical programmable spin-logic devices. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A data-driven modeling approach to stochastic computation for low-energy biomedical devices.

PubMed

Lee, Kyong Ho; Jang, Kuk Jin; Shoeb, Ali; Verma, Naveen

2011-01-01

Low-power devices that can detect clinically relevant correlations in physiologically-complex patient signals can enable systems capable of closed-loop response (e.g., controlled actuation of therapeutic stimulators, continuous recording of disease states, etc.). In ultra-low-power platforms, however, hardware error sources are becoming increasingly limiting. In this paper, we present how data-driven methods, which allow us to accurately model physiological signals, also allow us to effectively model and overcome prominent hardware error sources with nearly no additional overhead. Two applications, EEG-based seizure detection and ECG-based arrhythmia-beat classification, are synthesized to a logic-gate implementation, and two prominent error sources are introduced: (1) SRAM bit-cell errors and (2) logic-gate switching errors ('stuck-at' faults). Using patient data from the CHB-MIT and MIT-BIH databases, performance similar to error-free hardware is achieved even for very high fault rates (up to 0.5 for SRAMs and 7 × 10(-2) for logic) that cause computational bit error rates as high as 50%.

Towards constructing multi-bit binary adder based on Belousov-Zhabotinsky reaction

NASA Astrophysics Data System (ADS)

Zhang, Guo-Mao; Wong, Ieong; Chou, Meng-Ta; Zhao, Xin

2012-04-01

It has been proposed that the spatial excitable media can perform a wide range of computational operations, from image processing, to path planning, to logical and arithmetic computations. The realizations in the field of chemical logical and arithmetic computations are mainly concerned with single simple logical functions in experiments. In this study, based on Belousov-Zhabotinsky reaction, we performed simulations toward the realization of a more complex operation, the binary adder. Combining with some of the existing functional structures that have been verified experimentally, we designed a planar geometrical binary adder chemical device. Through numerical simulations, we first demonstrated that the device can implement the function of a single-bit full binary adder. Then we show that the binary adder units can be further extended in plane, and coupled together to realize a two-bit, or even multi-bit binary adder. The realization of chemical adders can guide the constructions of other sophisticated arithmetic functions, ultimately leading to the implementation of chemical computer and other intelligent systems.

Josephson Thermal Memory

NASA Astrophysics Data System (ADS)

Guarcello, Claudio; Solinas, Paolo; Braggio, Alessandro; Di Ventra, Massimiliano; Giazotto, Francesco

2018-01-01

We propose a superconducting thermal memory device that exploits the thermal hysteresis in a flux-controlled temperature-biased superconducting quantum-interference device (SQUID). This system reveals a flux-controllable temperature bistability, which can be used to define two well-distinguishable thermal logic states. We discuss a suitable writing-reading procedure for these memory states. The time of the memory writing operation is expected to be on the order of approximately 0.2 ns for a Nb-based SQUID in thermal contact with a phonon bath at 4.2 K. We suggest a noninvasive readout scheme for the memory states based on the measurement of the effective resonance frequency of a tank circuit inductively coupled to the SQUID. The proposed device paves the way for a practical implementation of thermal logic and computation. The advantage of this proposal is that it represents also an example of harvesting thermal energy in superconducting circuits.

Energy consumption analysis of graphene based all spin logic device with voltage controlled magnetic anisotropy

NASA Astrophysics Data System (ADS)

Zhang, Zhizhong; Zhang, Yue; Zheng, Zhenyi; Wang, Guanda; Su, Li; Zhang, Youguang; Zhao, Weisheng

2017-05-01

All spin logic device (ASLD) is a promising option to realize the ultra-low power computing systems. However, the low spin transport efficiency and the non-local switching of the detector have become two key challenges of the ASLD. In this paper, we analyze the energy consumption of a graphene based ASLD with the ferromagnetic layer switching assistance by voltage control magnetic anisotropy (VCMA) effect. This structure has significant potential towards ultra-low power consumption: the applied voltage can not only shorten switching time of the ferromagnetic layer, but also decreases the critical injection current; the graphene channel enhances greatly the spin transport efficiency. By applying the approximate circuit model, the impact of material configurations, interfaces and geometry can be synthetically studied. An accurate physic model was also developed, based on which, we carry out the micro-magnetic simulations to analyze the magnetization dynamics. Combining these electrical and magnetic investigations, the energy consumption of the proposed ASLD can be estimated. With the optimizing parameters, the energy consumption can be reduced to 2.5 pJ for a logic operation.

Energy efficient hybrid computing systems using spin devices

NASA Astrophysics Data System (ADS)

Sharad, Mrigank

Emerging spin-devices like magnetic tunnel junctions (MTJ's), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ˜20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode' processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ˜100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters.

Design and implementation of projects with Xilinx Zynq FPGA: a practical case

NASA Astrophysics Data System (ADS)

Travaglini, R.; D'Antone, I.; Meneghini, S.; Rignanese, L.; Zuffa, M.

The main advantage when using FPGAs with embedded processors is the availability of additional several high-performance resources in the same physical device. Moreover, the FPGA programmability allows for connect custom peripherals. Xilinx have designed a programmable device named Zynq-7000 (simply called Zynq in the following), which integrates programmable logic (identical to the other Xilinx "serie 7" devices) with a System on Chip (SOC) based on two embedded ARM processors. Since both parts are deeply connected, the designers benefit from performance of hardware SOC and flexibility of programmability as well. In this paper a design developed by the Electronic Design Department at the Bologna Division of INFN will be presented as a practical case of project based on Zynq device. It is developed by using a commercial board called ZedBoard hosting a FMC mezzanine with a 12-bit 500 MS/s ADC. The Zynq FPGA on the ZedBoard receives digital outputs from the ADC and send them to the acquisition PC, after proper formatting, through a Gigabit Ethernet link. The major focus of the paper will be about the methodology to develop a Zynq-based design with the Xilinx Vivado software, enlightening how to configure the SOC and connect it with the programmable logic. Firmware design techniques will be presented: in particular both VHDL and IP core based strategies will be discussed. Further, the procedure to develop software for the embedded processor will be presented. Finally, some debugging tools, like the embedded Logic Analyzer, will be shown. Advantages and disadvantages with respect to adopting FPGA without embedded processors will be discussed.

Generating and executing programs for a floating point single instruction multiple data instruction set architecture

DOEpatents

Gschwind, Michael K

2013-04-16

Mechanisms for generating and executing programs for a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA) are provided. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon is provided. The computer readable program, when executed on a computing device, causes the computing device to receive one or more instructions and execute the one or more instructions using logic in an execution unit of the computing device. The logic implements a floating point (FP) only single instruction multiple data (SIMD) instruction set architecture (ISA), based on data stored in a vector register file of the computing device. The vector register file is configured to store both scalar and floating point values as vectors having a plurality of vector elements.

Radio Frequency Based Programmable Logic Controller Anomaly Detection

DTIC Science & Technology

2013-09-01

include wireless radios, IEEE 802.15 Blue- tooth devices, cellular phones, and IEEE 802.11 WiFi networking devices. While wireless communication...MacKenzie, H. Shamoon Malware and SCADA Security What are the Im- pacts? . Technical Report, Tofino Security, Sep 2012. 61. Mateti,P. Hacking Techniques

Programmable and multiparameter DNA-based logic platform for cancer recognition and targeted therapy.

PubMed

You, Mingxu; Zhu, Guizhi; Chen, Tao; Donovan, Michael J; Tan, Weihong

2015-01-21

The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.

With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in themore » photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an encrypting/scrambling algorithm based on a study of candidate encryption algorithms. We found that a low gate count, cascadable encryption algorithm is most feasible given device and processing constraints. The modeling and simulation of optical designs using these components is proceeding in parallel with efforts to perfect the physical devices and their interconnect. We have applied these techniques to the development of a 'toy' algorithm that may pave the way for more robust optical algorithms. These design/modeling/simulation techniques are now ready to be applied to larger optical designs in advance of our ability to implement such systems in hardware.« less

Programmable hardware for reconfigurable computing systems

NASA Astrophysics Data System (ADS)

Smith, Stephen

1996-10-01

In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

Use of Fuzzy Logic Systems for Assessment of Primary Faults

NASA Astrophysics Data System (ADS)

Petrović, Ivica; Jozsa, Lajos; Baus, Zoran

2015-09-01

In electric power systems, grid elements are often subjected to very complex and demanding disturbances or dangerous operating conditions. Determining initial fault or cause of those states is a difficult task. When fault occurs, often it is an imperative to disconnect affected grid element from the grid. This paper contains an overview of possibilities for using fuzzy logic in an assessment of primary faults in the transmission grid. The tool for this task is SCADA system, which is based on information of currents, voltages, events of protection devices and status of circuit breakers in the grid. The function model described with the membership function and fuzzy logic systems will be presented in the paper. For input data, diagnostics system uses information of protection devices tripping, states of circuit breakers and measurements of currents and voltages before and after faults.

Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity

PubMed Central

Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

2015-01-01

Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity). PMID:25976626

Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity.

PubMed

Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

2015-05-15

Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity).

Notes on stochastic (bio)-logic gates: computing with allosteric cooperativity

NASA Astrophysics Data System (ADS)

Agliari, Elena; Altavilla, Matteo; Barra, Adriano; Dello Schiavo, Lorenzo; Katz, Evgeny

2015-05-01

Recent experimental breakthroughs have finally allowed to implement in-vitro reaction kinetics (the so called enzyme based logic) which code for two-inputs logic gates and mimic the stochastic AND (and NAND) as well as the stochastic OR (and NOR). This accomplishment, together with the already-known single-input gates (performing as YES and NOT), provides a logic base and paves the way to the development of powerful biotechnological devices. However, as biochemical systems are always affected by the presence of noise (e.g. thermal), standard logic is not the correct theoretical reference framework, rather we show that statistical mechanics can work for this scope: here we formulate a complete statistical mechanical description of the Monod-Wyman-Changeaux allosteric model for both single and double ligand systems, with the purpose of exploring their practical capabilities to express noisy logical operators and/or perform stochastic logical operations. Mixing statistical mechanics with logics, and testing quantitatively the resulting findings on the available biochemical data, we successfully revise the concept of cooperativity (and anti-cooperativity) for allosteric systems, with particular emphasis on its computational capabilities, the related ranges and scaling of the involved parameters and its differences with classical cooperativity (and anti-cooperativity).

21 CFR 866.5330 - Factor XIII, A, S, immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866.5330 Factor XIII, A, S, immuno-logical test system. (a) Identification. A factor XIII, A, S... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Factor XIII, A, S, immuno-logical test system. 866...

Optimized 4-bit Quantum Reversible Arithmetic Logic Unit

NASA Astrophysics Data System (ADS)

Ayyoub, Slimani; Achour, Benslama

2017-08-01

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This paper presents a complete design of a new reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented ALU can produce the largest number (28) of arithmetic and logic functions and have the smallest number of quantum cost and delay compared with existing designs.

Biomaterial-based Memory Device Development by Conducting Metallic DNA

DTIC Science & Technology

2013-05-28

time. Therefore, we have created a multiple-states memory system . This is the first multi-states resistance memory device by using bio-nanowire of the...world. Based on this achievement, logic device and application will be developed in the near future, too. Moreover, by using Ni-DNA detection system ...ions in DNA can change the resistance of Ni-DNA by applying different polar bias and time. Therefore, we have created a multiple-states memory system

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

Electromechanical Devices and Controllers. Electronics Module 10. Instructor's Guide.

ERIC Educational Resources Information Center

Carter, Ed

This module is the tenth of 10 modules in the competency-based electronics series. Introductory materials include a listing of competencies addressed in the module, a parts/equipment list, and a cross-reference table of instructional materials. Six instructional units cover: electromechanical control devices; programmable logic controllers (PLC);…

Control of electrochemical signals from quantum dots conjugated to organic materials by using DNA structure in an analog logic gate.

PubMed

Chen, Qi; Yoo, Si-Youl; Chung, Yong-Ho; Lee, Ji-Young; Min, Junhong; Choi, Jeong-Woo

2016-10-01

Various bio-logic gates have been studied intensively to overcome the rigidity of single-function silicon-based logic devices arising from combinations of various gates. Here, a simple control tool using electrochemical signals from quantum dots (QDs) was constructed using DNA and organic materials for multiple logic functions. The electrochemical redox current generated from QDs was controlled by the DNA structure. DNA structure, in turn, was dependent on the components (organic materials) and the input signal (pH). Independent electrochemical signals from two different logic units containing QDs were merged into a single analog-type logic gate, which was controlled by two inputs. We applied this electrochemical biodevice to a simple logic system and achieved various logic functions from the controlled pH input sets. This could be further improved by choosing QDs, ionic conditions, or DNA sequences. This research provides a feasible method for fabricating an artificial intelligence system. Copyright © 2016 Elsevier B.V. All rights reserved.

All-optical XOR logic gate using intersubband transition in III-V quantum well materials.

PubMed

Feng, Jijun; Akimoto, Ryoichi; Gozu, Shin-ichiro; Mozume, Teruo

2014-06-02

A monolithically integrated all-optical exclusive-OR (XOR) logic gate is experimentally demonstrated based on a Michelson interferometer (MI) gating device in InGaAs/AlAsSb coupled double quantum wells (CDQWs). The MI arms can convert the pump data with return-to-zero ON-OFF keying (RZ OOK) to binary phase-shift keying (BPSK) format, then two BPSK signals can interfere with each other for realizing a desired logical operation. All-optical format conversion from the RZ OOK to BPSK is based on the cross-phase modulation to the transverse electric (TE) probe wave, which is caused by the intersubband transition excited by the transverse magnetic (TM) pump light. Bit error rate measurements show that error free operation for both BPSK format conversion and XOR logical operation can be achieved.

Enhancing Learning Effectiveness in Digital Design Courses through the Use of Programmable Logic Boards

ERIC Educational Resources Information Center

Zhu, Yi; Weng, T.; Cheng, Chung-Kuan

2009-01-01

Incorporating programmable logic devices (PLD) in digital design courses has become increasingly popular. The advantages of using PLDs, such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGA), have been discussed before. However, previous studies have focused on the experiences from the point of view of the…

Enabling optical metrology on small 5×5μm2 in-cell targets to support flexible sampling and higher order overlay and CD control for advanced logic devices nodes

NASA Astrophysics Data System (ADS)

Salerno, Antonio; de la Fuente, Isabel; Hsu, Zack; Tai, Alan; Chang, Hammer; McNamara, Elliott; Cramer, Hugo; Li, Daoping

2018-03-01

In next generation Logic devices, overlay control requirements shrink to sub 2.5nm level on-product overlay. Historically on-product overlay has been defined by the overlay capability of after-develop in-scribe targets. However, due to design and dimension, the after development metrology targets are not completely representative for the final overlay of the device. In addition, they are confined to the scribe-lane area, which limits the sampling possibilities. To address these two issues, metrology on structures matching the device structure and which can be sampled with high density across the device is required. Conventional after-etch CDSEM techniques on logic devices present difficulties in discerning the layers of interest, potential destructive charging effects and finally, they are limited by the long measurement times[1] [2] [3] . All together, limit the sampling densities and making CDSEM less attractive for control applications. Optical metrology can overcome most of these limitations. Such measurement, however, does require repetitive structures. This requirement is not fulfilled by logic devices, as the features vary in pitch and CD over the exposure field. The solution is to use small targets, with a maximum pad size of 5x5um2 , which can easily be placed in the logic cell area. These targets share the process and architecture of the device features of interest, but with a modified design that replicates as close as possible the device layout, allowing for in-device metrology for both CD and Overlay. This solution enables measuring closer to the actual product feature location and, not being limited to scribe-lanes, it opens the possibility of higher-density sampling schemes across the field. In summary, these targets become the facilitator of in-device metrology (IDM), that is, enabling the measurements both in-device Overlay and the CD parameters of interest and can deliver accurate, high-throughput, dense and after-etch measurements for Logic. Overlay improvements derived from a high-densely sampled Overlay map measured with 5x5 um2 In Device Metrology (IDM) targets were investigated on a customer Logic application. In this work we present both the main design aspects of the 5x5 um2 IDM targets, as well as the results on the improved Overlay performance.

Bioelectrochemical interface engineering: toward the fabrication of electrochemical biosensors, biofuel cells, and self-powered logic biosensors.

PubMed

Zhou, Ming; Dong, Shaojun

2011-11-15

Over the past decade, researchers have devoted considerable attention to the integration of living organisms with electronic elements to yield bioelectronic devices. Not only is the integration of DNA, enzymes, or whole cells with electronics of scientific interest, but it has many versatile potential applications. Researchers are using these ideas to fabricate biosensors for analytical applications and to assemble biofuel cells (BFCs) and biomolecule-based devices. Other research efforts include the development of biocomputing systems for information processing. In this Account, we focus on our recent progress in engineering at the bioelectrochemical interface (BECI) for the rational design and construction of important bioelectronic devices, ranging from electrochemical (EC-) biosensors to BFCs, and self-powered logic biosensors. Hydrogels and sol-gels provide attractive materials for the immobilization of enzymes because they make EC-enzyme biosensors stable and even functional in extreme environments. We use a layer-by-layer (LBL) self-assembly technique to fabricate multicomponent thin films on the BECI at the nanometer scale. Additionally, we demonstrate how carbon nanomaterials have paved the way for new and improved EC-enzyme biosensors. In addition to the widely reported BECI-based electrochemical impedance spectroscopy (EIS)-type aptasensors, we integrate the LBL technique with our previously developed "solid-state probe" technique for redox probes immobilization on electrode surfaces to design and fabricate BECI-based differential pulse voltammetry (DPV)-type aptasensors. BFCs can directly harvest energy from ambient biofuels as green energy sources, which could lead to their application as simple, flexible, and portable power sources. Porous materials provide favorable microenvironments for enzyme immobilization, which can enhance BFC power output. Furthermore, by introducing aptamer-based logic systems to BFCs, such systems could be applied as self-powered and intelligent aptasensors for the logic detection. We have developed biocomputing keypad lock security systems which can be also used for intelligent medical diagnostics. BECI engineering provides a simple but effective approach toward the design and fabrication of EC-biosensors, BFCs, and self-powered logic biosensors, which will make essential contributions in the development of creative and practical bioelectronic devices. The exploration of novel interface engineering applications and the creation of new fabrication concepts or methods merit further attention.

THRESHOLD LOGIC IN ARTIFICIAL INTELLIGENCE

DTIC Science & Technology

COMPUTER LOGIC, ARTIFICIAL INTELLIGENCE , BIONICS, GEOMETRY, INPUT OUTPUT DEVICES, LINEAR PROGRAMMING, MATHEMATICAL LOGIC, MATHEMATICAL PREDICTION, NETWORKS, PATTERN RECOGNITION, PROBABILITY, SWITCHING CIRCUITS, SYNTHESIS

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

PubMed Central

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-01-01

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits. PMID:27491391

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal

NASA Astrophysics Data System (ADS)

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-08-01

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature ‘prototype’ PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

All-optical transistor- and diode-action and logic gates based on anisotropic nonlinear responsive liquid crystal.

PubMed

Wang, Cheng-Yu; Chen, Chun-Wei; Jau, Hung-Chang; Li, Cheng-Chang; Cheng, Chiao-Yu; Wang, Chun-Ta; Leng, Shi-Ee; Khoo, Iam-Choon; Lin, Tsung-Hsien

2016-08-05

In this paper, we show that anisotropic photosensitive nematic liquid crystals (PNLC) made by incorporating anisotropic absorbing dyes are promising candidates for constructing all-optical elements by virtue of the extraordinarily large optical nonlinearity of the nematic host. In particular, we have demonstrated several room-temperature 'prototype' PNLC-based all-optical devices such as optical diode, optical transistor and all primary logic gate operations (OR, AND, NOT) based on such optical transistor. Owing to the anisotropic absorption property and the optical activity of the twist alignment nematic cell, spatially non-reciprocal transmission response can be obtained within a sizeable optical isolation region of ~210 mW. Exploiting the same mechanisms, a tri-terminal configuration as an all-optical analogue of a bipolar junction transistor is fabricated. Its ability to be switched by an optical field enables us to realize an all-optical transistor and demonstrate cascadability, signal fan-out, logic restoration, and various logical gate operations such as OR, AND and NOT. Due to the possibility of synthesizing anisotropic dyes and wide ranging choice of liquid crystals nonlinear optical mechanisms, these all-optical operations can be optimized to have much lower thresholds and faster response speeds. The demonstrated capabilities of these devices have shown great potential in all-optical control system and photonic integrated circuits.

Noise-margin limitations on gallium-arsenide VLSI

NASA Technical Reports Server (NTRS)

Long, Stephen I.; Sundaram, Mani

1988-01-01

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Variability and reliability analysis in self-assembled multichannel carbon nanotube field-effect transistors

NASA Astrophysics Data System (ADS)

Hu, Zhaoying; Tulevski, George S.; Hannon, James B.; Afzali, Ali; Liehr, Michael; Park, Hongsik

2015-06-01

Carbon nanotubes (CNTs) have been widely studied as a channel material of scaled transistors for high-speed and low-power logic applications. In order to have sufficient drive current, it is widely assumed that CNT-based logic devices will have multiple CNTs in each channel. Understanding the effects of the number of CNTs on device performance can aid in the design of CNT field-effect transistors (CNTFETs). We have fabricated multi-CNT-channel CNTFETs with an 80-nm channel length using precise self-assembly methods. We describe compact statistical models and Monte Carlo simulations to analyze failure probability and the variability of the on-state current and threshold voltage. The results show that multichannel CNTFETs are more resilient to process variation and random environmental fluctuations than single-CNT devices.

Biosensors with Built-In Biomolecular Logic Gates for Practical Applications

PubMed Central

Lai, Yu-Hsuan; Sun, Sin-Cih; Chuang, Min-Chieh

2014-01-01

Molecular logic gates, designs constructed with biological and chemical molecules, have emerged as an alternative computing approach to silicon-based logic operations. These molecular computers are capable of receiving and integrating multiple stimuli of biochemical significance to generate a definitive output, opening a new research avenue to advanced diagnostics and therapeutics which demand handling of complex factors and precise control. In molecularly gated devices, Boolean logic computations can be activated by specific inputs and accurately processed via bio-recognition, bio-catalysis, and selective chemical reactions. In this review, we survey recent advances of the molecular logic approaches to practical applications of biosensors, including designs constructed with proteins, enzymes, nucleic acids, nanomaterials, and organic compounds, as well as the research avenues for future development of digitally operating “sense and act” schemes that logically process biochemical signals through networked circuits to implement intelligent control systems. PMID:25587423

Minimum energy dissipation required for a logically irreversible operation

NASA Astrophysics Data System (ADS)

Takeuchi, Naoki; Yoshikawa, Nobuyuki

2018-01-01

According to Landauer's principle, the minimum heat emission required for computing is linked to logical entropy, or logical reversibility. The validity of Landauer's principle has been investigated for several decades and was finally demonstrated in recent experiments by showing that the minimum heat emission is associated with the reduction in logical entropy during a logically irreversible operation. Although the relationship between minimum heat emission and logical reversibility is being revealed, it is not clear how much free energy is required to be dissipated for a logically irreversible operation. In the present study, in order to reveal the connection between logical reversibility and free energy dissipation, we numerically demonstrated logically irreversible protocols using adiabatic superconductor logic. The calculation results of work during the protocol showed that, while the minimum heat emission conforms to Landauer's principle, the free energy dissipation can be arbitrarily reduced by performing the protocol quasistatically. The above results show that logical reversibility is not associated with thermodynamic reversibility, and that heat is not only emitted from logic devices but also absorbed by logic devices. We also formulated the heat emission from adiabatic superconductor logic during a logically irreversible operation at a finite operation speed.

All optical programmable logic array (PLA)

NASA Astrophysics Data System (ADS)

Hiluf, Dawit

2018-03-01

A programmable logic array (PLA) is an integrated circuit (IC) logic device that can be reconfigured to implement various kinds of combinational logic circuits. The device has a number of AND and OR gates which are linked together to give output or further combined with more gates or logic circuits. This work presents the realization of PLAs via the physics of a three level system interacting with light. A programmable logic array is designed such that a number of different logical functions can be combined as a sum-of-product or product-of-sum form. We present an all optical PLAs with the aid of laser light and observables of quantum systems, where encoded information can be considered as memory chip. The dynamics of the physical system is investigated using Lie algebra approach.

Non-classical logic inverter coupling a ZnO nanowire-based Schottky barrier transistor and adjacent Schottky diode.

PubMed

Hosseini Shokouh, Seyed Hossein; Raza, Syed Raza Ali; Lee, Hee Sung; Im, Seongil

2014-08-21

On a single ZnO nanowire (NW), we fabricated an inverter-type device comprising a Schottky diode (SD) and field-effect transistor (FET), aiming at 1-dimensional (1D) electronic circuits with low power consumption. The SD and adjacent FET worked respectively as the load and driver, so that voltage signals could be easily extracted as the output. In addition, NW FET with a transparent conducting oxide as top gate turned out to be very photosensitive, although ZnO NW SD was blind to visible light. Based on this, we could achieve an array of photo-inverter cells on one NW. Our non-classical inverter is regarded as quite practical for both logic and photo-sensing due to its performance as well as simple device configuration.

Current-controlled unidirectional edge-meron motion

NASA Astrophysics Data System (ADS)

Xing, Xiangjun; Pong, Philip W. T.; Zhou, Yan

2016-11-01

In order to address many of the challenges and bottlenecks currently experienced by traditional charge-based technologies, various alternatives are being actively explored to provide potential solutions of device miniaturization and scaling in the post-Moore's-law era. Amongst these alternatives, spintronic physics and devices have recently attracted rapidly increasing interest by exploiting the additional degree of electrons-spin. For example, magnetic domain-wall racetrack-memory and logic devices have been realized via manipulating domain-wall motion. As compared to domain-wall-based devices, magnetic skyrmions have the advantages of ultrasmall size (typically 5-100 nm in diameter), facile current-driven motion, topological stability, and peculiar emergent electrodynamics, promising for next-generation electronics applications in the post-Moore's-law regime. Here, a magnetic meron device, which behaves similarly to a PN-junction diode, is demonstrated for the first time, by tailoring the current-controlled unidirectional motion of edge-merons (i.e., fractional skyrmions) in a nanotrack with interfacial Dzyaloshinskii-Moriya interaction. The working principles of the meron device, theoretically predicted from the Thiele equation for topological magnetic objects, are further verified using micromagnetic simulations. The present study has revealed the topology-independent transport property of different magnetic objects and is expected to open the vista toward integrated composite circuitry (with unified data storage and processing) based on a single magnetic chip, as the meron device can be used, either as a building block to develop complex logic components or as a signal controller to interconnect skyrmion, domain-wall, and even spin-wave devices.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

PubMed Central

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-01-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced. PMID:27834352

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

PubMed

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-11

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic

NASA Astrophysics Data System (ADS)

Kim, Wonjoo; Chattopadhyay, Anupam; Siemon, Anne; Linn, Eike; Waser, Rainer; Rana, Vikas

2016-11-01

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Multiple advanced logic gates made of DNA-Ag nanocluster and the application for intelligent detection of pathogenic bacterial genes.

PubMed

Lin, Xiaodong; Liu, Yaqing; Deng, Jiankang; Lyu, Yanlong; Qian, Pengcheng; Li, Yunfei; Wang, Shuo

2018-02-21

The integration of multiple DNA logic gates on a universal platform to implement advance logic functions is a critical challenge for DNA computing. Herein, a straightforward and powerful strategy in which a guanine-rich DNA sequence lighting up a silver nanocluster and fluorophore was developed to construct a library of logic gates on a simple DNA-templated silver nanoclusters (DNA-AgNCs) platform. This library included basic logic gates, YES, AND, OR, INHIBIT, and XOR, which were further integrated into complex logic circuits to implement diverse advanced arithmetic/non-arithmetic functions including half-adder, half-subtractor, multiplexer, and demultiplexer. Under UV irradiation, all the logic functions could be instantly visualized, confirming an excellent repeatability. The logic operations were entirely based on DNA hybridization in an enzyme-free and label-free condition, avoiding waste accumulation and reducing cost consumption. Interestingly, a DNA-AgNCs-based multiplexer was, for the first time, used as an intelligent biosensor to identify pathogenic genes, E. coli and S. aureus genes, with a high sensitivity. The investigation provides a prototype for the wireless integration of multiple devices on even the simplest single-strand DNA platform to perform diverse complex functions in a straightforward and cost-effective way.

Programmable and Multiparameter DNA-Based Logic Platform For Cancer Recognition and Targeted Therapy

PubMed Central

2014-01-01

The specific inventory of molecules on diseased cell surfaces (e.g., cancer cells) provides clinicians an opportunity for accurate diagnosis and intervention. With the discovery of panels of cancer markers, carrying out analyses of multiple cell-surface markers is conceivable. As a trial to accomplish this, we have recently designed a DNA-based device that is capable of performing autonomous logic-based analysis of two or three cancer cell-surface markers. Combining the specific target-recognition properties of DNA aptamers with toehold-mediated strand displacement reactions, multicellular marker-based cancer analysis can be realized based on modular AND, OR, and NOT Boolean logic gates. Specifically, we report here a general approach for assembling these modular logic gates to execute programmable and higher-order profiling of multiple coexisting cell-surface markers, including several found on cancer cells, with the capacity to report a diagnostic signal and/or deliver targeted photodynamic therapy. The success of this strategy demonstrates the potential of DNA nanotechnology in facilitating targeted disease diagnosis and effective therapy. PMID:25361164

Efficient G(sup 4)FET-Based Logic Circuits

NASA Technical Reports Server (NTRS)

Vatan, Farrokh

2008-01-01

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Overcoming thermal noise in non-volatile spin wave logic.

PubMed

Dutta, Sourav; Nikonov, Dmitri E; Manipatruni, Sasikanth; Young, Ian A; Naeemi, Azad

2017-05-15

Spin waves are propagating disturbances in magnetically ordered materials, analogous to lattice waves in solid systems and are often described from a quasiparticle point of view as magnons. The attractive advantages of Joule-heat-free transmission of information, utilization of the phase of the wave as an additional degree of freedom and lower footprint area compared to conventional charge-based devices have made spin waves or magnon spintronics a promising candidate for beyond-CMOS wave-based computation. However, any practical realization of an all-magnon based computing system must undergo the essential steps of a careful selection of materials and demonstrate robustness with respect to thermal noise or variability. Here, we aim at identifying suitable materials and theoretically demonstrate the possibility of achieving error-free clocked non-volatile spin wave logic device, even in the presence of thermal noise and clock jitter or clock skew.

Zone routing in a torus network

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Dong; Heidelberger, Philip; Kumar, Sameer

A system for routing data in a network comprising a network logic device at a sending node for determining a path between the sending node and a receiving node, wherein the network logic device sets one or more selection bits and one or more hint bits within the data packet, a control register for storing one or more masks, wherein the network logic device uses the one or more selection bits to select a mask from the control register and the network logic device applies the selected mask to the hint bits to restrict routing of the data packet tomore » one or more routing directions for the data packet within the network and selects one of the restricted routing directions from the one or more routing directions and sends the data packet along a link in the selected routing direction toward the receiving node.« less

The Design of Fault Tolerant Quantum Dot Cellular Automata Based Logic

NASA Technical Reports Server (NTRS)

Armstrong, C. Duane; Humphreys, William M.; Fijany, Amir

2002-01-01

As transistor geometries are reduced, quantum effects begin to dominate device performance. At some point, transistors cease to have the properties that make them useful computational components. New computing elements must be developed in order to keep pace with Moore s Law. Quantum dot cellular automata (QCA) represent an alternative paradigm to transistor-based logic. QCA architectures that are robust to manufacturing tolerances and defects must be developed. We are developing software that allows the exploration of fault tolerant QCA gate architectures by automating the specification, simulation, analysis and documentation processes.

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than two orders of lower energy consumption compared to state of the art CMOS implementation. Finally, we show the dynamics of injection locked Spin Hall Effect Spin-Torque Oscillator (SHE-STO) cluster can be exploited as a robust multi-dimensional distance metric for associative computing, image/ video analysis, etc. Our simulation results show that the proposed system architecture with injection locked SHE-STOs and the associated CMOS interface circuits can be suitable for robust and energy efficient associative computing and pattern matching.

Current Radiation Issues for Programmable Elements and Devices

NASA Technical Reports Server (NTRS)

Katz, R.; Wang, J. J.; Koga, R.; LaBel, A.; McCollum, J.; Brown, R.; Reed, R. A.; Cronquist, B.; Crain, S.; Scott, T.;

Graphene-Based Flexible and Stretchable Electronics.

PubMed

Jang, Houk; Park, Yong Ju; Chen, Xiang; Das, Tanmoy; Kim, Min-Seok; Ahn, Jong-Hyun

2016-06-01

Graphene provides outstanding properties that can be integrated into various flexible and stretchable electronic devices in a conventional, scalable fashion. The mechanical, electrical, and optical properties of graphene make it an attractive candidate for applications in electronics, energy-harvesting devices, sensors, and other systems. Recent research progress on graphene-based flexible and stretchable electronics is reviewed here. The production and fabrication methods used for target device applications are first briefly discussed. Then, the various types of flexible and stretchable electronic devices that are enabled by graphene are discussed, including logic devices, energy-harvesting devices, sensors, and bioinspired devices. The results represent important steps in the development of graphene-based electronics that could find applications in the area of flexible and stretchable electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Detection and response to unauthorized access to a communication device

DOEpatents

Smith, Rhett; Gordon, Colin

2015-09-08

A communication gateway consistent with the present disclosure may detect unauthorized physical or electronic access and implement security actions in response thereto. A communication gateway may provide a communication path to an intelligent electronic device (IED) using an IED communications port configured to communicate with the IED. The communication gateway may include a physical intrusion detection port and a network port. The communication gateway may further include control logic configured to evaluate physical intrusion detection signal. The control logic may be configured to determine that the physical intrusion detection signal is indicative of an attempt to obtain unauthorized access to one of the communication gateway, the IED, and a device in communication with the gateway; and take a security action based upon the determination that the indication is indicative of the attempt to gain unauthorized access.

Valleytronics in merging Dirac cones: All-electric-controlled valley filter, valve, and universal reversible logic gate

NASA Astrophysics Data System (ADS)

Ang, Yee Sin; Yang, Shengyuan A.; Zhang, C.; Ma, Zhongshui; Ang, L. K.

2017-12-01

Despite much anticipation of valleytronics as a candidate to replace the aging complementary metal-oxide-semiconductor (CMOS) based information processing, its progress is severely hindered by the lack of practical ways to manipulate valley polarization all electrically in an electrostatic setting. Here, we propose a class of all-electric-controlled valley filter, valve, and logic gate based on the valley-contrasting transport in a merging Dirac cones system. The central mechanism of these devices lies on the pseudospin-assisted quantum tunneling which effectively quenches the transport of one valley when its pseudospin configuration mismatches that of a gate-controlled scattering region. The valley polarization can be abruptly switched into different states and remains stable over semi-infinite gate-voltage windows. Colossal tunneling valley-pseudomagnetoresistance ratio of over 10 000 % can be achieved in a valley-valve setup. We further propose a valleytronic-based logic gate capable of covering all 16 types of two-input Boolean logics. Remarkably, the valley degree of freedom can be harnessed to resurrect logical reversibility in two-input universal Boolean gate. The (2 +1 ) polarization states (two distinct valleys plus a null polarization) reestablish one-to-one input-to-output mapping, a crucial requirement for logical reversibility, and significantly reduce the complexity of reversible circuits. Our results suggest that the synergy of valleytronics and digital logics may provide new paradigms for valleytronic-based information processing and reversible computing.

Radiation tolerant combinational logic cell

NASA Technical Reports Server (NTRS)

Maki, Gary R. (Inventor); Whitaker, Sterling (Inventor); Gambles, Jody W. (Inventor)

2009-01-01

A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q'. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

Programmable Regulation of DNA Conjugation to Gold Nanoparticles via Strand Displacement.

PubMed

Zhang, Cheng; Wu, Ranfeng; Li, Yifan; Zhang, Qiang; Yang, Jing

2017-10-31

Methods for conjugating DNA to gold nanoparticles (AuNPs) have recently attracted considerable attention. The ability to control such conjugation in a programmable way is of great interest. Here, we have developed a logic-based method for manipulating the conjugation of thiolated DNA species to AuNPs via cascading DNA strand displacement. Using this method, several logic-based operation systems are established and up to three kinds of DNA signals are introduced at the same time. In addition, a more sensitive catalytic logic-based operation is also achieved based on an entropy-driven process. In the experiment, all of the DNA/AuNPs conjugation results are verified by agrose gel. This strategy promises great potential for automatically conjugating DNA stands onto label-free gold nanoparticles and can be extended to constructing DNA/nanoparticle devices for applications in diagnostics, biosensing, and molecular robotics.

Integrated circuits and logic operations based on single-layer MoS2.

PubMed

Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

2011-12-27

Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

pH-controlled silicon nanowires fluorescence switch

NASA Astrophysics Data System (ADS)

Mu, Lixuan; Shi, Wensheng; Zhang, Taiping; Zhang, Hongyan; She, Guangwei

2010-08-01

Covalently immobilizing photoinduced electronic transfer (PET) fluorophore 3-[N, N-bis(9-anthrylmethyl)amino]-propyltriethoxysilane (DiAN) on the surface of silicon nanowires (SiNWs) resulted a SiNWs-based fluorescence switch. This fluorescence switch is operated by adjustment of the acidity of the environment and exhibits sensitive response to pH at the range from 8 to 10. Such response is attributed to the effect of pH on the PET process. The successful combination of logic switch and SiNWs provides a rational approach to assemble different logic molecules on SiNWs for realization of miniaturization and modularization of switches and logic devices.

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Bilayer avalanche spin-diode logic

DOE Office of Scientific and Technical Information (OSTI.GOV)

Friedman, Joseph S., E-mail: joseph.friedman@u-psud.fr; Querlioz, Damien; Fadel, Eric R.

2015-11-15

A novel spintronic computing paradigm is proposed and analyzed in which InSb p-n bilayer avalanche spin-diodes are cascaded to efficiently perform complex logic operations. This spin-diode logic family uses control wires to generate magnetic fields that modulate the resistance of the spin-diodes, and currents through these devices control the resistance of cascaded devices. Electromagnetic simulations are performed to demonstrate the cascading mechanism, and guidelines are provided for the development of this innovative computing technology. This cascading scheme permits compact logic circuits with switching speeds determined by electromagnetic wave propagation rather than electron motion, enabling high-performance spintronic computing.

Software Safety Assurance of Programmable Logic

NASA Technical Reports Server (NTRS)

Berens, Kalynnda

2002-01-01

Programmable Logic (PLC, FPGA, ASIC) devices are hybrids - hardware devices that are designed and programmed like software. As such, they fall in an assurance gray area. Programmable Logic is usually tested and verified as hardware, and the software aspects are ignored, potentially leading to safety or mission success concerns. The objective of this proposal is to first determine where and how Programmable Logic (PL) is used within NASA and document the current methods of assurance. Once that is known, raise awareness of the PL software aspects within the NASA engineering community and provide guidance for the use and assurance of PL form a software perspective.

Fuzzy logic controller to improve powerline communication

NASA Astrophysics Data System (ADS)

Tirrito, Salvatore

2015-12-01

The Power Line Communications (PLC) technology allows the use of the power grid in order to ensure the exchange of data information among devices. This work proposes an approach, based on Fuzzy Logic, that dynamically manages the amplitude of the signal, with which each node transmits, by processing the master-slave link quality measured and the master-slave distance. The main objective of this is to reduce both the impact of communication interferences induced and power consumption.

Effects of Asymmetric Local Joule Heating on Silicon Nanowire-Based Devices Formed by Dielectrophoresis Alignment Across Pt Electrodes

NASA Astrophysics Data System (ADS)

Ho, Hsiang-Hsi; Lin, Chun-Lung; Tsai, Wei-Che; Hong, Liang-Zheng; Lyu, Cheng-Han; Hsu, Hsun-Feng

2018-01-01

We demonstrate the fabrication and characterization of silicon nanowire-based devices in metal-nanowire-metal configuration using direct current dielectrophoresis. The current-voltage characteristics of the devices were found rectifying, and their direction of rectification could be determined by voltage sweep direction due to the asymmetric Joule heating effect that occurred in the electrical measurement process. The photosensing properties of the rectifying devices were investigated. It reveals that when the rectifying device was in reverse-biased mode, the excellent photoresponse was achieved due to the strong built-in electric field at the junction interface. It is expected that rectifying silicon nanowire-based devices through this novel and facile method can be potentially applied to other applications such as logic gates and sensors.

Parallel database search and prime factorization with magnonic holographic memory devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Khitun, Alexander

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploitmore » wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.« less

Parallel database search and prime factorization with magnonic holographic memory devices

NASA Astrophysics Data System (ADS)

Khitun, Alexander

2015-12-01

In this work, we describe the capabilities of Magnonic Holographic Memory (MHM) for parallel database search and prime factorization. MHM is a type of holographic device, which utilizes spin waves for data transfer and processing. Its operation is based on the correlation between the phases and the amplitudes of the input spin waves and the output inductive voltage. The input of MHM is provided by the phased array of spin wave generating elements allowing the producing of phase patterns of an arbitrary form. The latter makes it possible to code logic states into the phases of propagating waves and exploit wave superposition for parallel data processing. We present the results of numerical modeling illustrating parallel database search and prime factorization. The results of numerical simulations on the database search are in agreement with the available experimental data. The use of classical wave interference may results in a significant speedup over the conventional digital logic circuits in special task data processing (e.g., √n in database search). Potentially, magnonic holographic devices can be implemented as complementary logic units to digital processors. Physical limitations and technological constrains of the spin wave approach are also discussed.

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, X.; Mamaluy, D.; Cyr, E. C.

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE PAGES

Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

2016-05-10

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

Research on NC motion controller based on SOPC technology

NASA Astrophysics Data System (ADS)

Jiang, Tingbiao; Meng, Biao

2006-11-01

With the rapid development of the digitization and informationization, the application of numerical control technology in the manufacturing industry becomes more and more important. However, the conventional numerical control system usually has some shortcomings such as the poor in system openness, character of real-time, cutability and reconfiguration. In order to solve these problems, this paper investigates the development prospect and advantage of the application in numerical control area with system-on-a-Programmable-Chip (SOPC) technology, and puts forward to a research program approach to the NC controller based on SOPC technology. Utilizing the characteristic of SOPC technology, we integrate high density logic device FPGA, memory SRAM, and embedded processor ARM into a single programmable logic device. We also combine the 32-bit RISC processor with high computing capability of the complicated algorithm with the FPGA device with strong motivable reconfiguration logic control ability. With these steps, we can greatly resolve the defect described in above existing numerical control systems. For the concrete implementation method, we use FPGA chip embedded with ARM hard nuclear processor to construct the control core of the motion controller. We also design the peripheral circuit of the controller according to the requirements of actual control functions, transplant real-time operating system into ARM, design the driver of the peripheral assisted chip, develop the application program to control and configuration of FPGA, design IP core of logic algorithm for various NC motion control to configured it into FPGA. The whole control system uses the concept of modular and structured design to develop hardware and software system. Thus the NC motion controller with the advantage of easily tailoring, highly opening, reconfigurable, and expandable can be implemented.

Multiple advanced logic gates made of DNA-Ag nanocluster and the application for intelligent detection of pathogenic bacterial genes† †Electronic supplementary information (ESI) available: Chemicals, materials and DNA sequences used in the investigation, the construction of YES, AND, OR, XOR and INH logic gates, CD and PAGE experimental results. See DOI: 10.1039/c7sc05246d

PubMed Central

Lin, Xiaodong; Deng, Jiankang; Lyu, Yanlong; Qian, Pengcheng; Li, Yunfei

2018-01-01

The integration of multiple DNA logic gates on a universal platform to implement advance logic functions is a critical challenge for DNA computing. Herein, a straightforward and powerful strategy in which a guanine-rich DNA sequence lighting up a silver nanocluster and fluorophore was developed to construct a library of logic gates on a simple DNA-templated silver nanoclusters (DNA-AgNCs) platform. This library included basic logic gates, YES, AND, OR, INHIBIT, and XOR, which were further integrated into complex logic circuits to implement diverse advanced arithmetic/non-arithmetic functions including half-adder, half-subtractor, multiplexer, and demultiplexer. Under UV irradiation, all the logic functions could be instantly visualized, confirming an excellent repeatability. The logic operations were entirely based on DNA hybridization in an enzyme-free and label-free condition, avoiding waste accumulation and reducing cost consumption. Interestingly, a DNA-AgNCs-based multiplexer was, for the first time, used as an intelligent biosensor to identify pathogenic genes, E. coli and S. aureus genes, with a high sensitivity. The investigation provides a prototype for the wireless integration of multiple devices on even the simplest single-strand DNA platform to perform diverse complex functions in a straightforward and cost-effective way. PMID:29675221

Programmable logic construction kits for hyper-real-time neuronal modeling.

PubMed

Guerrero-Rivera, Ruben; Morrison, Abigail; Diesmann, Markus; Pearce, Tim C

2006-11-01

Programmable logic designs are presented that achieve exact integration of leaky integrate-and-fire soma and dynamical synapse neuronal models and incorporate spike-time dependent plasticity and axonal delays. Highly accurate numerical performance has been achieved by modifying simpler forward-Euler-based circuitry requiring minimal circuit allocation, which, as we show, behaves equivalently to exact integration. These designs have been implemented and simulated at the behavioral and physical device levels, demonstrating close agreement with both numerical and analytical results. By exploiting finely grained parallelism and single clock cycle numerical iteration, these designs achieve simulation speeds at least five orders of magnitude faster than the nervous system, termed here hyper-real-time operation, when deployed on commercially available field-programmable gate array (FPGA) devices. Taken together, our designs form a programmable logic construction kit of commonly used neuronal model elements that supports the building of large and complex architectures of spiking neuron networks for real-time neuromorphic implementation, neurophysiological interfacing, or efficient parameter space investigations.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

Powerful timing generator using mono-chip timers: An application to pulsed nuclear magnetic resonance

NASA Astrophysics Data System (ADS)

Saint-Jalmes, Hervé; Barjhoux, Yves

1982-01-01

We present a 10 line-7 MHz timing generator built on a single board around two LSI timer chips interfaced to a 16-bit microcomputer. Once programmed from the host computer, this device is able to generate elaborate logic sequences on its 10 output lines without further interventions from the CPU. Powerful architecture introduces new possibilities over conventional memory-based timing simulators and word generators. Loop control on a given sequence of events, loop nesting, and various logic combinations can easily be implemented through a software interface, using a symbolic command language. Typical applications of such a device range from development, emulation, and test of integrated circuits, circuit boards, and communication systems to pulse-controlled instrumentation (radar, ultrasonic systems). A particular application to a pulsed Nuclear Magnetic Resonance (NMR) spectrometer is presented, along with customization of the device for generating four-channel radio-frequency pulses and the necessary sequence for subsequent data acquisition.

In-situ, In-Memory Stateful Vector Logic Operations based on Voltage Controlled Magnetic Anisotropy.

PubMed

Jaiswal, Akhilesh; Agrawal, Amogh; Roy, Kaushik

2018-04-10

Recently, the exponential increase in compute requirements demanded by emerging applications like artificial intelligence, Internet of things, etc. have rendered the state-of-art von-Neumann machines inefficient in terms of energy and throughput owing to the well-known von-Neumann bottleneck. A promising approach to mitigate the bottleneck is to do computations as close to the memory units as possible. One extreme possibility is to do in-situ Boolean logic computations by using stateful devices. Stateful devices are those that can act both as a compute engine and storage device, simultaneously. We propose such stateful, vector, in-memory operations using voltage controlled magnetic anisotropy (VCMA) effect in magnetic tunnel junctions (MTJ). Our proposal is based on the well known manufacturable 1-transistor - 1-MTJ bit-cell and does not require any modifications in the bit-cell circuit or the magnetic device. Instead, we leverage the very physics of the VCMA effect to enable stateful computations. Specifically, we exploit the voltage asymmetry of the VCMA effect to construct stateful IMP (implication) gate and use the precessional switching dynamics of the VCMA devices to propose a massively parallel NOT operation. Further, we show that other gates like AND, OR, NAND, NOR, NIMP (complement of implication) can be implemented using multi-cycle operations.

Near-Field Thermal Radiation for Solar Thermophotovoltaics and High Temperature Thermal Logic and Memory Applications

NASA Astrophysics Data System (ADS)

Elzouka, Mahmoud

This dissertation investigates Near-Field Thermal Radiation (NFTR) applied to MEMS-based concentrated solar thermophotovoltaics (STPV) energy conversion and thermal memory and logics. NFTR is the exchange of thermal radiation energy at nano/microscale; when separation between the hot and cold objects is less than dominant radiation wavelength (˜1 mum). NFTR is particularly of interest to the above applications due to its high rate of energy transfer, exceeding the blackbody limit by orders of magnitude, and its strong dependence on separation gap size, surface nano/microstructure and material properties. Concentrated STPV system converts solar radiation to electricity using heat as an intermediary through a thermally coupled absorber/emitter, which causes STPV to have one of the highest solar-to-electricity conversion efficiency limits (85.4%). Modeling of a near-field concentrated STPV microsystem is carried out to investigate the use of STPV based solid-state energy conversion as high power density MEMS power generator. Numerical results for In 0.18Ga0.82Sb PV cell illuminated with tungsten emitter showed significant enhancement in energy transfer, resulting in output power densities as high as 60 W/cm2; 30 times higher than the equivalent far-field power density. On thermal computing, this dissertation demonstrates near-field heat transfer enabled high temperature NanoThermoMechanical memory and logics. Unlike electronics, NanoThermoMechanical memory and logic devices use heat instead of electricity to record and process data; hence they can operate in harsh environments where electronics typically fail. NanoThermoMechanical devices achieve memory and thermal rectification functions through the coupling of near-field thermal radiation and thermal expansion in microstructures, resulting in nonlinear heat transfer between two temperature terminals. Numerical modeling of a conceptual NanoThermoMechanical is carried out; results include the dynamic response under write/read cycles for a practical silicon-based device. NanoThermoMechanical rectification is achieved experimentally--for the first time--with measurements at a high temperature of 600 K, demonstrating the feasibility of NanoThermoMechanical to operate in harsh environments. The proof-of-concept device has shown a maximum rectification of 10.9%. This dissertation proposes using meshed photonic crystal structures to enhance NFTR between surfaces. Numerical results show thermal rectification as high as 2500%. Incorporating these structures in thermal memory and rectification devices will significantly enhance their functionality and performance.

Programmable single-cell mammalian biocomputers.

PubMed

Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

2012-07-05

Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

A novel productivity-driven logic element for field-programmable devices

NASA Astrophysics Data System (ADS)

Marconi, Thomas; Bertels, Koen; Gaydadjiev, Georgi

2014-06-01

Although various techniques have been proposed for power reduction in field-programmable devices (FPDs), they are still all based on conventional logic elements (LEs). In the conventional LE, the output of the combinational logic (e.g. the look-up table (LUT) in many field-programmable gate arrays (FPGAs)) is connected to the input of the storage element; while the D flip-flop (DFF) is always clocked even when not necessary. Such unnecessary transitions waste power. To address this problem, we propose a novel productivity-driven LE with reduced number of transitions. The differences between our LE and the conventional LE are in the FFs-type used and the internal LE organisation. In our LEs, DFFs have been replaced by T flip-flops with the T input permanently connected to logic value 1. Instead of connecting the output of the combinational logic to the FF input, we use it as the FF clock. The proposed LE has been validated via Simulation Program with Integrated Circuit Emphasis (SPICE) simulations for a 45-nm Complementary Metal-Oxide-Semiconductor (CMOS) technology as well as via a real Computer-Aided Design (CAD) tools on a real FPGA using the standard Microelectronic Center of North Carolina (MCNC) benchmark circuits. The experimental results show that FPDs using our proposal not only have 48% lower total power but also run 17% faster than conventional FPDs on average.

The role of Snell's law for a magnonic majority gate.

PubMed

Kanazawa, Naoki; Goto, Taichi; Sekiguchi, Koji; Granovsky, Alexander B; Ross, Caroline A; Takagi, Hiroyuki; Nakamura, Yuichi; Uchida, Hironaga; Inoue, Mitsuteru

2017-08-11

In the fifty years since the postulation of Moore's Law, the increasing energy consumption in silicon electronics has motivated research into emerging devices. An attractive research direction is processing information via the phase of spin waves within magnonic-logic circuits, which function without charge transport and the accompanying heat generation. The functional completeness of magnonic logic circuits based on the majority function was recently proved. However, the performance of such logic circuits was rather poor due to the difficulty of controlling spin waves in the input junction of the waveguides. Here, we show how Snell's law describes the propagation of spin waves in the junction of a Ψ-shaped magnonic majority gate composed of yttrium iron garnet with a partially metallized surface. Based on the analysis, we propose a magnonic counterpart of a core-cladding waveguide to control the wave propagation in the junction. This study has therefore experimentally demonstrated a fundamental building block of a magnonic logic circuit.

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

PubMed

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

A graphene barristor using nitrogen profile controlled ZnO Schottky contacts.

PubMed

Hwang, Hyeon Jun; Chang, Kyoung Eun; Yoo, Won Beom; Shim, Chang Hoo; Lee, Sang Kyung; Yang, Jin Ho; Kim, So-Young; Lee, Yongsu; Cho, Chunhum; Lee, Byoung Hun

2017-02-16

We have successfully demonstrated a graphene-ZnO:N Schottky barristor. The barrier height between graphene and ZnO:N could be modulated by a buried gate electrode in the range of 0.5-0.73 eV, and an on-off ratio of up to 10 7 was achieved. By using a nitrogen-doped ZnO film as a Schottky contact material, the stability problem of previously reported graphene barristors could be greatly alleviated and a facile route to build a top-down processed graphene barristor was realized with a very low heat cycle. This device will be instrumental when implementing logic functions in systems requiring high-performance logic devices fabricated with a low temperature fabrication process such as back-end integrated logic devices or flexible devices on soft substrates.

21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

Code of Federal Regulations, 2014 CFR

2014-04-01

... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2014-04-01 2014-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866...

21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

Code of Federal Regulations, 2013 CFR

2013-04-01

... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2013-04-01 2013-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866...

21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

Code of Federal Regulations, 2011 CFR

2011-04-01

... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2011-04-01 2011-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866...

21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

Code of Federal Regulations, 2012 CFR

2012-04-01

... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2012-04-01 2012-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866...

21 CFR 866.5860 - Total spinal fluid immuno-logical test system.

Code of Federal Regulations, 2010 CFR

2010-04-01

... diagnosis of multiple sclerosis and other diseases of the nervous system. (b) Classification. Class I... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Total spinal fluid immuno-logical test system. 866... SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test Systems § 866...

Irradiation of MOS-FET devices to provide desired logic functions

NASA Technical Reports Server (NTRS)

Danchenko, V.; Schaefer, D. H.

1972-01-01

Gamma, X-ray, electron, or other radiation is used to shift threshold potentials of MOS devices on logic circuits. Before irradiation MOS gates to be shifted are biased positive and other gates are grounded to substrate. Threshold lasts 10 years. Thermal annealing brings circuit back to original configuration.

A Bluetooth-Based Device Management Platform for Smart Sensor Environment

NASA Astrophysics Data System (ADS)

Lim, Ivan Boon-Kiat; Yow, Kin Choong

In this paper, we propose the use of Bluetooth as the device management platform for the various embedded sensors and actuators in an ambient intelligent environment. We demonstrate the ease of adding Bluetooth capability to common sensor circuits (e.g. motion sensor circuit based on a pyroelectric infrared (PIR) sensor). A central logic application is proposed which controls the operation of controller devices, based on values returned by sensors via Bluetooth. The operation of devices depends on rules that are learnt from user behavior using an Elman recurrent neural network. Overall, Bluetooth has shown its potential in being used as a device management platform in an ambient intelligent environment, which allows sensors and controllers to be deployed even in locations where power sources are not readily available, by using battery power.

A Double-Stimuli-Responsive Fluorescent Center for Monitoring of Food Spoilage based on Dye Covalently Modified EuMOFs: From Sensory Hydrogels to Logic Devices.

PubMed

Xu, Xiao-Yu; Lian, Xiao; Hao, Ji-Na; Zhang, Chi; Yan, Bing

2017-10-01

Unsafe food is a huge threat to human health and the economy, and detecting food spoilage early is an ongoing and imperative need. Herein, a simple and effective strategy combining a fluorescence sensor and one-to-two logic operation is designed for monitoring biogenic amines, indicators of food spoilage. Sensors (methyl red@lanthanide metal-organic frameworks (MR@EuMOFs)) are created by covalently modifying MR into NH 2 -rich EuMOFs, which have a high quantum yield (48%). A double-stimuli-responsive fluorescence center is produced via energy transfer from the ligands to Eu 3+ and MR. Portable sensory hydrogels are obtained by dispersing and solidifying MR@EuMOFs in water-phase sodium salt of carboxy methyl cellulose (CMC-Na). The hydrogels exhibit a color transition upon "smelling" histamine (HI) vapor. This transition and shift in the MR-based emission peak are closely related to the HI concentration. Using the HI concentration as the input signal and the two fluorescence emissions as output signals, an advanced analytical device based on a one-to-two logic gate is constructed. The four output combinations, NOT (0, 1), YES (1, 0), PASS 1 (1, 1), and PASS 0 (0, 0), allow the direct analysis of HI levels, which can be used for real-time food-freshness evaluation. The novel strategy suggested here may be a new application for a molecular logic system in the sensing field. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ambipolar Barristors for Reconfigurable Logic Circuits.

PubMed

Liu, Yuan; Zhang, Guo; Zhou, Hailong; Li, Zheng; Cheng, Rui; Xu, Yang; Gambin, Vincent; Huang, Yu; Duan, Xiangfeng

2017-03-08

Vertical heterostructures based on graphene have emerged as a unique architecture for novel electronic devices with unusual characteristics. Here we report a new design of vertical ambipolar barristors based on metal-graphene-silicon-graphene sandwich structure, using the bottom graphene as a gate-tunable "active contact", the top graphene as an adaptable Ohmic contact, and the low doping thin silicon layer as the switchable channel. Importantly, with finite density of states and weak screening effect of graphene, we demonstrate, for the first time, that both the carrier concentration and majority carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar barristors with an ON-OFF ratio exceeding 10 3 . Significantly, these ambipolar barristors can be flexibly configured into either p-type or n-type transistors and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable characteristics can open up exciting opportunities in future electronics based on graphene or two-dimensional van der Waals heterostructures.

FAST TRACK COMMUNICATION: Eight-logic memory cell based on multiferroic junctions

NASA Astrophysics Data System (ADS)

Yang, Feng; Zhou, Y. C.; Tang, M. H.; Liu, Fen; Ma, Ying; Zheng, X. J.; Zhao, W. F.; Xu, H. Y.; Sun, Z. H.

2009-04-01

A model is proposed for a device combining a multiferroic tunnel junction with a magnetoelectric (ME) film in which the magnetic configuration is controlled by the electric field. Calculations embodying the Green's function approach show that the magnetic polarization can be switched on and off by an electric field in the ME film due to the effect of elastic coupling interaction. Using a model including the spin-filter effect and screening of polarization charges, we have produced eight logic states of tunnelling resistance in the tunnel junction and have obtained corresponding laws that control them. The results provide some insights into the realization of an eight-logic memory cell.

Voltage-controlled low-energy switching of nanomagnets through Ruderman-Kittel-Kasuya-Yosida interactions for magnetoelectric device applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ghosh, Bahniman, E-mail: bghosh@utexas.edu; Dey, Rik; Register, Leonard F.

2016-07-21

In this article, we consider through simulation low-energy switching of nanomagnets via electrostatically gated inter-magnet Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions on the surface of three-dimensional topological insulators, for possible memory and nonvolatile logic applications. We model the possibility and dynamics of RKKY-based switching of one nanomagnet by coupling to one or more nanomagnets of set orientation. Potential applications to both memory and nonvolatile logic are illustrated. Sub-attojoule switching energies, far below conventional spin transfer torque (STT)-based memories and even below CMOS logic appear possible. Switching times on the order of a few nanoseconds, comparable to times for STT switching, are estimated formore » ferromagnetic nanomagnets, but the approach also appears compatible with the use of antiferromagnets which may allow for faster switching.« less

Energy efficient circuit design using nanoelectromechanical relays

NASA Astrophysics Data System (ADS)

Venkatasubramanian, Ramakrishnan

Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS. This dissertation demonstrates NEM relay based charge pump and NEM-CMOS heterogeneous discontinuous conduction mode (DCM) buck regulator and the results are compared against a standard commercial 0.35μm CMOS implementation. It is shown that NEM-CMOS heterogeneous DC-DC converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of 94.3% at 100mA. NEM relays offers unprecedented 10X-30X energy efficiency improvement in logic design for low frequency operation and has the potential to break the CMOS efficiency barrier in power electronic circuits as well. The practical aspects of NEM Relay integration are evaluated and algorithms for synthesis and development of large NEM relay based logic circuits are explored.

Nanopore Logic Operation with DNA to RNA Transcription in a Droplet System.

PubMed

Ohara, Masayuki; Takinoue, Masahiro; Kawano, Ryuji

2017-07-21

This paper describes an AND logic operation with amplification and transcription from DNA to RNA, using T7 RNA polymerase. All four operations, (0 0) to (1 1), with an enzyme reaction can be performed simultaneously, using four-droplet devices that are directly connected to a patch-clamp amplifier. The output RNA molecule is detected using a biological nanopore with single-molecule translocation. Channel current recordings can be obtained using the enzyme solution. The integration of DNA logic gates into electrochemical devices is necessary to obtain output information in a human-recognizable form. Our method will be useful for rapid and confined DNA computing applications, including the development of programmable diagnostic devices.

Proposal of ultra-compact NAND/NOR/XNOR all-optical logic gates based on a nonlinear 3x1 multimode interference

NASA Astrophysics Data System (ADS)

Tajaldini, Mehdi; Mat Jafri, M. Z.

2014-05-01

We present a highly miniaturized multimode interference (MMI) coupler based on nonlinear modal propagation analysis (NMPA) method as a novel design method and potential application for optical NAND, NOR and XNOR logic gates for Boolean logic signal processing devices. Crystalline polydiacetylene is used to allow the appearances of nonlinear effects in low input intensities and ultra- short length to control the MMI coupler as an active device to access light switching due to its high nonlinear susceptibility. We consider a 10x33 μm2 MMI structure with three inputs and one output. Notably, the access facets are single-mode waveguides with sub-micron width. The center input contributes to control the induced light propagation in MMI by intensity variation whereas others could be launched by particular intensity when they are ON and 0 in OFF. Output intensity is analyzed in various sets of inputs to show the capability of Boolean logic gates, the contrast between ON and OFF is calculated on mentioned gates to present the efficiency. Good operation in low intensity and highly miniaturized MMI coupler is observed. Furthermore, nonlinear effects could be realized through the modal interferences. The issue of high insertion loss is addressed with a 3×3 upgraded coupler. Furthermore, the main significant aspect of this paper is simulating an MMI coupler that is launched by three nonlinear inputs, simultaneously, whereas last presents have never studied more than one input in nonlinear regimes.

DNA "nano-claw": logic-based autonomous cancer targeting and therapy.

PubMed

You, Mingxu; Peng, Lu; Shao, Na; Zhang, Liqin; Qiu, Liping; Cui, Cheng; Tan, Weihong

2014-01-29

Cell types, both healthy and diseased, can be classified by inventories of their cell-surface markers. Programmable analysis of multiple markers would enable clinicians to develop a comprehensive disease profile, leading to more accurate diagnosis and intervention. As a first step to accomplish this, we have designed a DNA-based device, called "Nano-Claw". Combining the special structure-switching properties of DNA aptamers with toehold-mediated strand displacement reactions, this claw is capable of performing autonomous logic-based analysis of multiple cancer cell-surface markers and, in response, producing a diagnostic signal and/or targeted photodynamic therapy. We anticipate that this design can be widely applied in facilitating basic biomedical research, accurate disease diagnosis, and effective therapy.

Systems and methods to control multiple peripherals with a single-peripheral application code

DOEpatents

Ransom, Ray M.

2013-06-11

Methods and apparatus are provided for enhancing the BIOS of a hardware peripheral device to manage multiple peripheral devices simultaneously without modifying the application software of the peripheral device. The apparatus comprises a logic control unit and a memory in communication with the logic control unit. The memory is partitioned into a plurality of ranges, each range comprising one or more blocks of memory, one range being associated with each instance of the peripheral application and one range being reserved for storage of a data pointer related to each peripheral application of the plurality. The logic control unit is configured to operate multiple instances of the control application by duplicating one instance of the peripheral application for each peripheral device of the plurality and partitioning a memory device into partitions comprising one or more blocks of memory, one partition being associated with each instance of the peripheral application. The method then reserves a range of memory addresses for storage of a data pointer related to each peripheral device of the plurality, and initializes each of the plurality of peripheral devices.

Field-programmable logic devices with optical input-output.

PubMed

Szymanski, T H; Saint-Laurent, M; Tyan, V; Au, A; Supmonchai, B

2000-02-10

A field-programmable logic device (FPLD) with optical I/O is described. FPLD's with optical I/O can have their functionality specified in the field by means of downloading a control-bit stream and can be used in a wide range of applications, such as optical signal processing, optical image processing, and optical interconnects. Our device implements six state-of-the-art dynamically programmable logic arrays (PLA's) on a 2 mm x 2 mm die. The devices were fabricated through the Lucent Technologies-Advanced Research Projects Agency-Consortium for Optical and Optoelectronic Technologies in Computing (Lucent/ARPA/COOP) workshop by use of 0.5-microm complementary metal-oxide semiconductor-self-electro-optic device technology and were delivered in 1998. All devices are fully functional: The electronic data paths have been verified at 200 MHz, and optical tests are pending. The device has been programmed to implement a two-stage optical switching network with six 4 x 4 crossbar switches, which can realize more than 190 x 10(6) unique programmable input-output permutations. The same device scaled to a 2 cm x 2 cm substrate could support as many as 4000 optical I/O and 1 Tbit/s of optical I/O bandwidth and offer fully programmable digital functionality with approximately 110,000 programmable logic gates. The proposed optoelectronic FPLD is also ideally suited to realizing dense, statically reconfigurable crossbar switches. We describe an attractive application area for such devices: a rearrangeable three-stage optical switch for a wide-area-network backbone, switching 1000 traffic streams at the OC-48 data rate and supporting several terabits of traffic.

Reversible Conversion of Dominant Polarity in Ambipolar Polymer/Graphene Oxide Hybrids

PubMed Central

Zhou, Ye; Han, Su-Ting; Sonar, Prashant; Ma, Xinlei; Chen, Jihua; Zheng, Zijian; Roy, V. A. L.

2015-01-01

The possibility to selectively modulate the charge carrier transport in semiconducting materials is extremely challenging for the development of high performance and low-power consuming logic circuits. Systematical control over the polarity (electrons and holes) in transistor based on solution processed layer by layer polymer/graphene oxide hybrid system has been demonstrated. The conversion degree of the polarity is well controlled and reversible by trapping the opposite carriers. Basically, an electron device is switched to be a hole only device or vice versa. Finally, a hybrid layer ambipolar inverter is demonstrated in which almost no leakage of opposite carrier is found. This hybrid material has wide range of applications in planar p-n junctions and logic circuits for high-throughput manufacturing of printed electronic circuits. PMID:25801827

Three-Dimensional Flexible Complementary Metal-Oxide-Semiconductor Logic Circuits Based On Two-Layer Stacks of Single-Walled Carbon Nanotube Networks.

PubMed

Zhao, Yudan; Li, Qunqing; Xiao, Xiaoyang; Li, Guanhong; Jin, Yuanhao; Jiang, Kaili; Wang, Jiaping; Fan, Shoushan

2016-02-23

We have proposed and fabricated stable and repeatable, flexible, single-walled carbon nanotube (SWCNT) thin film transistor (TFT) complementary metal-oxide-semiconductor (CMOS) integrated circuits based on a three-dimensional (3D) structure. Two layers of SWCNT-TFT devices were stacked, where one layer served as n-type devices and the other one served as p-type devices. On the basis of this method, it is able to save at least half of the area required to construct an inverter and make large-scale and high-density integrated CMOS circuits easier to design and manufacture. The 3D flexible CMOS inverter gain can be as high as 40, and the total noise margin is more than 95%. Moreover, the input and output voltage of the inverter are exactly matched for cascading. 3D flexible CMOS NOR, NAND logic gates, and 15-stage ring oscillators were fabricated on PI substrates with high performance as well. Stable electrical properties of these circuits can be obtained with bending radii as small as 3.16 mm, which shows that such a 3D structure is a reliable architecture and suitable for carbon nanotube electrical applications in complex flexible and wearable electronic devices.

Molecular implementation of simple logic programs.

PubMed

Ran, Tom; Kaplan, Shai; Shapiro, Ehud

2009-10-01

Autonomous programmable computing devices made of biomolecules could interact with a biological environment and be used in future biological and medical applications. Biomolecular implementations of finite automata and logic gates have already been developed. Here, we report an autonomous programmable molecular system based on the manipulation of DNA strands that is capable of performing simple logical deductions. Using molecular representations of facts such as Man(Socrates) and rules such as Mortal(X) <-- Man(X) (Every Man is Mortal), the system can answer molecular queries such as Mortal(Socrates)? (Is Socrates Mortal?) and Mortal(X)? (Who is Mortal?). This biomolecular computing system compares favourably with previous approaches in terms of expressive power, performance and precision. A compiler translates facts, rules and queries into their molecular representations and subsequently operates a robotic system that assembles the logical deductions and delivers the result. This prototype is the first simple programming language with a molecular-scale implementation.

Reconfigurable all-optical NOT, XOR, and NOR logic gates based on two dimensional photonic crystals

NASA Astrophysics Data System (ADS)

Parandin, Fariborz; Malmir, M. Reza; Naseri, Mosayeb; Zahedi, Abdulhamid

2018-01-01

Photonic crystals can be considered as one of the most important basis for designing optical devices. In this research, using two-dimensional photonic crystals with triangular lattices, ultra-compact logic gates are designed and simulated. The intended structure has the capability to be used as three logical gates (NOT, XOR, and NOR). The designed structures not only have characteristics of small dimensions which make them suitable for integrated optical circuits, but also exhibit very low power transfer delay which makes it possible to design high speed gates. On comparison with the previous works, our simulations show that at a wavelength of 1.55 μm , the gates indicate a time delay of about 0.1 ps and the contrast ratio for the XOR gate is about 30 dB, i.e., the proposed structures are more applicable in designing low error optical logic gates.

Temperature Dependence Of Single-Event Effects

NASA Technical Reports Server (NTRS)

Coss, James R.; Nichols, Donald K.; Smith, Lawrence S.; Huebner, Mark A.; Soli, George A.

1990-01-01

Report describes experimental study of effects of temperature on vulnerability of integrated-circuit memories and other electronic logic devices to single-event effects - spurious bit flips or latch-up in logic state caused by impacts of energetic ions. Involved analysis of data on 14 different device types. In most cases examined, vulnerability to these effects increased or remain constant with temperature.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing: Digital Timing Analysis Tools and Techniques. Articles in this issue include: SX and SX-A Series Devices Power Sequencing; JTAG and SXISX-AISX-S Series Devices; Analysis Techniques (i.e., notes on digital timing analysis tools and techniques); Status of the Radiation Hard reconfigurable Field Programmable Gate Array Program, Input Transition Times; Apollo Guidance Computer Logic Study; RT54SX32S Prototype Data Sets; A54SX32A - 0.22 micron/UMC Test Results; Ramtron FM1608 FRAM; and Analysis of VHDL Code and Synthesizer Output.

Digital Holographic Logic

NASA Technical Reports Server (NTRS)

Preston, K., Jr.

1972-01-01

The characteristics of the holographic logic computer are discussed. The holographic operation is reviewed from the Fourier transform viewpoint, and the formation of holograms for use in performing digital logic are described. The operation of the computer with an experiment in which the binary identity function is calculated is discussed along with devices for achieving real-time performance. An application in pattern recognition using neighborhood logic is presented.

Realization of optimized quantum controlled-logic gate based on the orbital angular momentum of light.

PubMed

Zeng, Qiang; Li, Tao; Song, Xinbing; Zhang, Xiangdong

2016-04-18

We propose and experimentally demonstrate an optimized setup to implement quantum controlled-NOT operation using polarization and orbital angular momentum qubits. This device is more adaptive to inputs with various polarizations, and can work both in classical and quantum single-photon regime. The logic operations performed by such a setup not only possess high stability and polarization-free character, they can also be easily extended to deal with multi-qubit input states. As an example, the experimental implementation of generalized three-qubit Toffoli gate has been presented.

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

High-speed low-power photonic transistor devices based on optically-controlled gain or absorption to affect optical interference.

PubMed

Huang, Yingyan; Ho, Seng-Tiong

2008-10-13

We show that a photonic transistor device can be realized via the manipulation of optical interference by optically controlled gain or absorption in novel ways, resulting in efficient transistor signal gain and switching action. Exemplary devices illustrate two complementary device types with high operating speed, microm size, microW switching power, and switching gain. They can act in tandem to provide a wide variety of operations including wavelength conversion, pulse regeneration, and logical operations. These devices could have a Transistor Figure-of-Merits >10(5) times higher than current chi((3)) approaches and are highly attractive.

Development of Algorithms for Control of Humidity in Plant Growth Chambers

NASA Technical Reports Server (NTRS)

Costello, Thomas A.

2003-01-01

Algorithms were developed to control humidity in plant growth chambers used for research on bioregenerative life support at Kennedy Space Center. The algorithms used the computed water vapor pressure (based on measured air temperature and relative humidity) as the process variable, with time-proportioned outputs to operate the humidifier and de-humidifier. Algorithms were based upon proportional-integral-differential (PID) and Fuzzy Logic schemes and were implemented using I/O Control software (OPTO-22) to define and download the control logic to an autonomous programmable logic controller (PLC, ultimate ethernet brain and assorted input-output modules, OPTO-22), which performed the monitoring and control logic processing, as well the physical control of the devices that effected the targeted environment in the chamber. During limited testing, the PLC's successfully implemented the intended control schemes and attained a control resolution for humidity of less than 1%. The algorithms have potential to be used not only with autonomous PLC's but could also be implemented within network-based supervisory control programs. This report documents unique control features that were implemented within the OPTO-22 framework and makes recommendations regarding future uses of the hardware and software for biological research by NASA.

Tunable nano-scale graphene-based devices in mid-infrared wavelengths composed of cylindrical resonators

NASA Astrophysics Data System (ADS)

Asgari, Somayyeh; Ghattan Kashani, Zahra; Granpayeh, Nosrat

2018-04-01

The performances of three optical devices including a refractive index sensor, a power splitter, and a 4-channel multi/demultiplexer based on graphene cylindrical resonators are proposed, analyzed, and simulated numerically by using the finite-difference time-domain method. The proposed sensor operates on the principle of the shift in resonance wavelength with a change in the refractive index of dielectric materials. The sensor sensitivity has been numerically derived. In addition, the performances of the power splitter and the multi/demultiplexer based on the variation of the resonance wavelengths of cylindrical resonator have been thoroughly investigated. The simulation results are in good agreement with the theoretical ones. Our studies demonstrate that the graphene based ultra-compact, nano-scale devices can be improved to be used as photonic integrated devices, optical switching, and logic gates.

A Survey of Memristive Threshold Logic Circuits.

PubMed

Maan, Akshay Kumar; Jayadevi, Deepthi Anirudhan; James, Alex Pappachen

2017-08-01

In this paper, we review different memristive threshold logic (MTL) circuits that are inspired from the synaptic action of the flow of neurotransmitters in the biological brain. The brainlike generalization ability and the area minimization of these threshold logic circuits aim toward crossing Moore's law boundaries at device, circuits, and systems levels. Fast switching memory, signal processing, control systems, programmable logic, image processing, reconfigurable computing, and pattern recognition are identified as some of the potential applications of MTL systems. The physical realization of nanoscale devices with memristive behavior from materials, such as TiO 2 , ferroelectrics, silicon, and polymers, has accelerated research effort in these application areas, inspiring the scientific community to pursue the design of high-speed, low-cost, low-power, and high-density neuromorphic architectures.

SEE Sensitivity Analysis of 180 nm NAND CMOS Logic Cell for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focus on Single Event Effects caused by energetic particle strike on sensitive locations in CMOS NAND logic cell designed in 180nm technology node to be operated in space radiation environment. The generation of SE transients as well as upsets as function of LET of incident particle has been determined for logic devices onboard LEO and GEO satellites. The minimum magnitude pulse and pulse-width for threshold LET was determined to estimate the vulnerability /susceptibility of device for heavy ion strike. The impact of temperature, strike location and logic state of NAND circuit on total SEU/SET rate was estimated with physical mechanism simulations using Visual TCAD, Genius, runSEU program and Crad computer codes.

A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices

NASA Technical Reports Server (NTRS)

Kulkarni, Shriram; Mazumder, Pinaki; Haddad, George I.

1995-01-01

An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations.

An Automated Design Framework for Multicellular Recombinase Logic.

PubMed

Guiziou, Sarah; Ulliana, Federico; Moreau, Violaine; Leclere, Michel; Bonnet, Jerome

2018-05-18

Tools to systematically reprogram cellular behavior are crucial to address pressing challenges in manufacturing, environment, or healthcare. Recombinases can very efficiently encode Boolean and history-dependent logic in many species, yet current designs are performed on a case-by-case basis, limiting their scalability and requiring time-consuming optimization. Here we present an automated workflow for designing recombinase logic devices executing Boolean functions. Our theoretical framework uses a reduced library of computational devices distributed into different cellular subpopulations, which are then composed in various manners to implement all desired logic functions at the multicellular level. Our design platform called CALIN (Composable Asynchronous Logic using Integrase Networks) is broadly accessible via a web server, taking truth tables as inputs and providing corresponding DNA designs and sequences as outputs (available at http://synbio.cbs.cnrs.fr/calin ). We anticipate that this automated design workflow will streamline the implementation of Boolean functions in many organisms and for various applications.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

FAST TRACK COMMUNICATION: Reversible arithmetic logic unit for quantum arithmetic

NASA Astrophysics Data System (ADS)

Kirkedal Thomsen, Michael; Glück, Robert; Axelsen, Holger Bock

2010-09-01

This communication presents the complete design of a reversible arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The presented ALU is garbage free and uses reversible updates to combine the standard reversible arithmetic and logical operations in one unit. Combined with a suitable control unit, the ALU permits the construction of an r-Turing complete computing device. The garbage-free ALU developed in this communication requires only 6n elementary reversible gates for five basic arithmetic-logical operations on two n-bit operands and does not use ancillae. This remarkable low resource consumption was achieved by generalizing the V-shape design first introduced for quantum ripple-carry adders and nesting multiple V-shapes in a novel integrated design. This communication shows that the realization of an efficient reversible ALU for a programmable computing device is possible and that the V-shape design is a very versatile approach to the design of quantum networks.

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fuzzy logic based on-line fault detection and classification in transmission line.

PubMed

Adhikari, Shuma; Sinha, Nidul; Dorendrajit, Thingam

2016-01-01

This study presents fuzzy logic based online fault detection and classification of transmission line using Programmable Automation and Control technology based National Instrument Compact Reconfigurable i/o (CRIO) devices. The LabVIEW software combined with CRIO can perform real time data acquisition of transmission line. When fault occurs in the system current waveforms are distorted due to transients and their pattern changes according to the type of fault in the system. The three phase alternating current, zero sequence and positive sequence current data generated by LabVIEW through CRIO-9067 are processed directly for relaying. The result shows that proposed technique is capable of right tripping action and classification of type of fault at high speed therefore can be employed in practical application.

A Simple Memristor Model for Circuit Simulations

NASA Astrophysics Data System (ADS)

Fullerton, Farrah-Amoy; Joe, Aaleyah; Gergel-Hackett, Nadine; Department of Chemistry; Physics Team

This work describes the development of a model for the memristor, a novel nanoelectronic technology. The model was designed to replicate the real-world electrical characteristics of previously fabricated memristor devices, but was constructed with basic circuit elements using a free widely available circuit simulator, LT Spice. The modeled memrsistors were then used to construct a circuit that performs material implication. Material implication is a digital logic that can be used to perform all of the same basic functions as traditional CMOS gates, but with fewer nanoelectronic devices. This memristor-based digital logic could enable memristors' use in new paradigms of computer architecture with advantages in size, speed, and power over traditional computing circuits. Additionally, the ability to model the real-world electrical characteristics of memristors in a free circuit simulator using its standard library of elements could enable not only the development of memristor material implication, but also the development of a virtually unlimited array of other memristor-based circuits.

Control and manipulation of antiferromagnetic skyrmions in racetrack

NASA Astrophysics Data System (ADS)

Xia, Haiyan; Jin, Chendong; Song, Chengkun; Wang, Jinshuai; Wang, Jianbo; Liu, Qingfang

2017-12-01

Controllable manipulations of magnetic skyrmions are essential for next-generation spintronic devices. Here, the duplication and merging of skyrmions, as well as logical AND and OR functions, are designed in antiferromagnetic (AFM) materials with a cusp or smooth Y-junction structures. The operational time are in the dozens of picoseconds, enabling ultrafast information processing. A key factor for the successful operation is the relatively complex Y-junction structures, where domain walls propagate through in a controlled manner, without significant risks of pinning, vanishing or unwanted depinning of existing domain walls, as well as the nucleation of new domain walls. The motions of a multi-bit, namely the motion of an AFM skyrmion-chain in racetrack, are also investigated. Those micromagnetic simulations may contribute to future AFM skyrmion-based spintronic devices, such as nanotrack memory, logic gates and other information processes.

Nano- and micro-electromechanical switch dynamics

NASA Astrophysics Data System (ADS)

Pulskamp, Jeffrey S.; Proie, Robert M.; Polcawich, Ronald G.

2013-01-01

This paper reports theoretical analysis and experimental results on the dynamics of piezoelectric MEMS mechanical logic relays. The multiple degree of freedom analytical model, based on modal decomposition, utilizes modal parameters obtained from finite element analysis and an analytical model of piezoelectric actuation. The model accounts for exact device geometry, damping, drive waveform variables, and high electric field piezoelectric nonlinearity. The piezoelectrically excited modal force is calculated directly and provides insight into design optimization for switching speed. The model accurately predicts the propagation delay dependence on actuation voltage of mechanically distinct relay designs. The model explains the observed discrepancies in switching speed of these devices relative to single degree of freedom switching speed models and suggests the strong potential for improved switching speed performance in relays designed for mechanical logic and RF circuits through the exploitation of higher order vibrational modes.

Field Effect Transistor Behavior in Electrospun Polyaniline/Polyethylene Oxide Nanofibers

NASA Technical Reports Server (NTRS)

Miranda, Felix A.; Theofylaktos, Noulie; Mueller, Carl H.; Pinto, Nicholas J.

2004-01-01

Novel transistors and logic devices based on nanotechnology concepts are under intense development. The potential for ultra-low-power circuitry makes nanotechnology attractive for applications such as digital electronics and sensors. For NASA applications, nanotechnology offers tremendous opportunities for increased onboard data processing, and thus autonomous decision-making ability, and novel sensors that detect and respond to environmental stimuli with little oversight requirements. Polyaniline (PANi) is an intriguing material because its electrical conductivity can be changed from insulating to metallic by varying the doping levels and conformations of the polymer chain, and when combined with polyethylene oxide (PEO), can be formed into nanofibers with diameters ranging from approximately 50 to 500 nm (depending on the deposition conditions). The initial goal of this work was to demonstrate transistor behavior in these nanofibers, thus creating a foundation for future logic devices.

Reversible conversion of dominant polarity in ambipolar polymer/graphene oxide hybrids

DOE PAGES

Zhou, Ye; Han, Su -Ting; Sonar, Prashant; ...

2015-03-24

The possibility to selectively modulate the charge carrier transport in semiconducting materials is extremely challenging for the development of high performance and low-power consuming logic circuits. Systematical control over the polarity (electrons and holes) in transistor based on solution processed layer by layer polymer/graphene oxide hybrid system has been demonstrated. The conversion degree of the polarity is well controlled and reversible by trapping the opposite carriers. Basically, an electron device is switched to be a hole only device or vice versa. Finally, a hybrid layer ambipolar inverter is demonstrated in which almost no leakage of opposite carrier is found. Wemore » conclude that this hybrid material has wide range of applications in planar p-n junctions and logic circuits for high-throughput manufacturing of printed electronic circuits.« less

Ultra Low Power Datalogger

NASA Astrophysics Data System (ADS)

Holik, Michael

2010-01-01

The article describes a design and the test of the datalogger unit. Main demands on the datalogger were to achieve the power consumption as low as possible and the ability to capture short-time events. The datalogger is based on a programmable logic device FPGA. VHDL language is used to design the architecture fitted into the FPGA. The results of the test confirmed low power consumption feature of the device as well as proper functionality of the unit.

Semiconductor/High-Tc-Superconductor Hybrid ICs

NASA Technical Reports Server (NTRS)

Burns, Michael J.

1995-01-01

Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

Fault tolerance issues in nanoelectronics

NASA Astrophysics Data System (ADS)

Spagocci, S. M.

The astonishing success story of microelectronics cannot go on indefinitely. In fact, once devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected to impair their behaviour. Fault tolerant techniques will then be required. The aim of this thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient error rates for a selection of nanoelectronic gates, based upon quantum cellular automata and single electron devices, in which the electrostatic interaction between electrons is used to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional techniques are found to be unsuitable. A new technique, in which the voting approach of triple modular redundancy (TMR) is extended by cascading TMR units composed of nanogate clusters, is proposed and generalised to other voting approaches. For memory chips, an error correcting code approach is found to be suitable. Various codes are considered and a lookup table approach is proposed for encoding and decoding. We are then able to give estimations for the redundancy level to be provided on nanochips, so as to make their mean time between failures acceptable. It is found that, for logic chips, space redundancies up to a few tens are required, if mean times between failures have to be of the order of a few years. Space redundancy can also be traded for time redundancy. As for memory chips, mean times between failures of the order of a few years are found to imply both space and time redundancies of the order of ten.

Clocked Magnetostriction-Assisted Spintronic Device Design and Simulation

NASA Astrophysics Data System (ADS)

Mousavi Iraei, Rouhollah; Kani, Nickvash; Dutta, Sourav; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Heron, John T.; Naeemi, Azad

2018-05-01

We propose a heterostructure device comprised of magnets and piezoelectrics that significantly improves the delay and the energy dissipation of an all-spin logic (ASL) device. This paper studies and models the physics of the device, illustrates its operation, and benchmarks its performance using SPICE simulations. We show that the proposed device maintains low voltage operation, non-reciprocity, non-volatility, cascadability, and thermal reliability of the original ASL device. Moreover, by utilizing the deterministic switching of a magnet from the saddle point of the energy profile, the device is more efficient in terms of energy and delay and is robust to thermal fluctuations. The results of simulations show that compared to ASL devices, the proposed device achieves 21x shorter delay and 27x lower energy dissipation per bit for a 32-bit arithmetic-logic unit (ALU).

Design and Construction of a Microcontroller-Based Ventilator Synchronized with Pulse Oximeter.

PubMed

Gölcük, Adem; Işık, Hakan; Güler, İnan

2016-07-01

This study aims to introduce a novel device with which mechanical ventilator and pulse oximeter work in synchronization. Serial communication technique was used to enable communication between the pulse oximeter and the ventilator. The SpO2 value and the pulse rate read on the pulse oximeter were transmitted to the mechanical ventilator through transmitter (Tx) and receiver (Rx) lines. The fuzzy-logic-based software developed for the mechanical ventilator interprets these values and calculates the percentage of oxygen (FiO2) and Positive End-Expiratory Pressure (PEEP) to be delivered to the patient. The fuzzy-logic-based software was developed to check the changing medical states of patients and to produce new results (FiO2 ve PEEP) according to each new state. FiO2 and PEEP values delivered from the ventilator to the patient can be calculated in this way without requiring any arterial blood gas analysis. Our experiments and the feedbacks from physicians show that this device makes it possible to obtain more successful results when compared to the current practices.

Smart molecules at work--mimicking advanced logic operations.

PubMed

Andréasson, Joakim; Pischel, Uwe

2010-01-01

Molecular logic is an interdisciplinary research field, which has captured worldwide interest. This tutorial review gives a brief introduction into molecular logic and Boolean algebra. This serves as the basis for a discussion of the state-of-the-art and future challenges in the field. Representative examples from the most recent literature including adders/subtractors, multiplexers/demultiplexers, encoders/decoders, and sequential logic devices (keypad locks) are highlighted. Other horizons, such as the utility of molecular logic in bio-related applications, are discussed as well.

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

A label-free and enzyme-free system for operating various logic devices using poly(thymine)-templated CuNPs and SYBR Green I as signal transducers

NASA Astrophysics Data System (ADS)

Wu, Changtong; Zhou, Chunyang; Wang, Erkang; Dong, Shaojun

2016-07-01

For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations.For the first time by integrating fluorescent polyT-templated CuNPs and SYBR Green I, a basic INHIBIT gate and four advanced logic circuits (2-to-1 encoder, 4-to-2 encoder, 1-to-2 decoder and 1-to-2 demultiplexer) have been conceptually realized under label-free and enzyme-free conditions. Taking advantage of the selective formation of CuNPs on ss-DNA, the implementation of these advanced logic devices were achieved without any usage of dye quenching groups or other nanomaterials like graphene oxide or AuNPs since polyA strands not only worked as an input but also acted as effective inhibitors towards polyT templates, meeting the aim of developing bio-computing with cost-effective and operationally simple methods. In short, polyT-templated CuNPs, as promising fluorescent signal reporters, are successfully applied to fabricate advanced logic devices, which may present a potential path for future development of molecular computations. Electronic supplementary information (ESI) available. See DOI: 10.1039/c6nr04069a

Boolean Logic Tree of Label-Free Dual-Signal Electrochemical Aptasensor System for Biosensing, Three-State Logic Computation, and Keypad Lock Security Operation.

PubMed

Lu, Jiao Yang; Zhang, Xin Xing; Huang, Wei Tao; Zhu, Qiu Yan; Ding, Xue Zhi; Xia, Li Qiu; Luo, Hong Qun; Li, Nian Bing

2017-09-19

The most serious and yet unsolved problems of molecular logic computing consist in how to connect molecular events in complex systems into a usable device with specific functions and how to selectively control branchy logic processes from the cascading logic systems. This report demonstrates that a Boolean logic tree is utilized to organize and connect "plug and play" chemical events DNA, nanomaterials, organic dye, biomolecule, and denaturant for developing the dual-signal electrochemical evolution aptasensor system with good resettability for amplification detection of thrombin, controllable and selectable three-state logic computation, and keypad lock security operation. The aptasensor system combines the merits of DNA-functionalized nanoamplification architecture and simple dual-signal electroactive dye brilliant cresyl blue for sensitive and selective detection of thrombin with a wide linear response range of 0.02-100 nM and a detection limit of 1.92 pM. By using these aforementioned chemical events as inputs and the differential pulse voltammetry current changes at different voltages as dual outputs, a resettable three-input biomolecular keypad lock based on sequential logic is established. Moreover, the first example of controllable and selectable three-state molecular logic computation with active-high and active-low logic functions can be implemented and allows the output ports to assume a high impediment or nothing (Z) state in addition to the 0 and 1 logic levels, effectively controlling subsequent branchy logic computation processes. Our approach is helpful in developing the advanced controllable and selectable logic computing and sensing system in large-scale integration circuits for application in biomedical engineering, intelligent sensing, and control.

Introduction of Interfacial Charges to Black Phosphorus for a Family of Planar Devices

NASA Astrophysics Data System (ADS)

Bao, Lihong; Wang, Guocai; Du, Shixuan; Pantelides, Sokrates; Gao, Hong-Jun

As a young member in the family of two dimensional materials, black phosphorus (BP) has attracted great attention since its discovery due to its high hole mobility and a sizable and tunable bandgap, which meets the basic requirements for logic circuits applications. Naturally, for realization of complementary logic operation, the challenge lies in how to control the conduction type in BP FETs, i.e., the dominant carrier types, holes (p-type) or electrons (n-type). However, the absence of reliable substitutional doping techniques makes this task a great challenge. Introducing interfacial charges into 2D materials has been proven to be a successfulway to control conduction. In this work, we, for the first time, demonstrate that capping a thin BP layer with a layer of cross-linked PMMA can modify the conductivity type of the BP by a surface charge transfer process, converting a BP layer dominated by hole conduction in the absence of an external electric field (p-type) to one dominated by electron conduction (n-type). Combining BP films capped by cross-linked PMMA with standard BP, a familyof planar devices can be created, including BP gated diodes and bidirectional recitifiers (rectification ratio >102) and BP logic inverter (gain¡«0.75) which are capable of performing current rectification, switching, and signal inversion operations. The device performance demonstrated here suggests a promising route for developing 2D-based electronics.

Dynamic partial reconfiguration of logic controllers implemented in FPGAs

NASA Astrophysics Data System (ADS)

Bazydło, Grzegorz; Wiśniewski, Remigiusz

2016-09-01

Technological progress in recent years benefits in digital circuits containing millions of logic gates with the capability for reprogramming and reconfiguring. On the one hand it provides the unprecedented computational power, but on the other hand the modelled systems are becoming increasingly complex, hierarchical and concurrent. Therefore, abstract modelling supported by the Computer Aided Design tools becomes a very important task. Even the higher consumption of the basic electronic components seems to be acceptable because chip manufacturing costs tend to fall over the time. The paper presents a modelling approach for logic controllers with the use of Unified Modelling Language (UML). Thanks to the Model Driven Development approach, starting with a UML state machine model, through the construction of an intermediate Hierarchical Concurrent Finite State Machine model, a collection of Verilog files is created. The system description generated in hardware description language can be synthesized and implemented in reconfigurable devices, such as FPGAs. Modular specification of the prototyped controller permits for further dynamic partial reconfiguration of the prototyped system. The idea bases on the exchanging of the functionality of the already implemented controller without stopping of the FPGA device. It means, that a part (for example a single module) of the logic controller is replaced by other version (called context), while the rest of the system is still running. The method is illustrated by a practical example by an exemplary Home Area Network system.

Teaching Discrete and Programmable Logic Design Techniques Using a Single Laboratory Board

ERIC Educational Resources Information Center

Debiec, P.; Byczuk, M.

2011-01-01

Programmable logic devices (PLDs) are used at many universities in introductory digital logic laboratories, where kits containing a single high-capacity PLD replace "standard" sets containing breadboards, wires, and small- or medium-scale integration (SSI/MSI) chips. From the pedagogical point of view, two problems arise in these…

Efficiency of optical-electronic systems: methods application for the analysis of structural changes in the process of eye grounds diagnosis

NASA Astrophysics Data System (ADS)

Saldan, Yosyp R.; Pavlov, Sergii V.; Vovkotrub, Dina V.; Saldan, Yulia Y.; Vassilenko, Valentina B.; Mazur, Nadia I.; Nikolaichuk, Daria V.; Wójcik, Waldemar; Romaniuk, Ryszard; Suleimenov, Batyrbek; Bainazarov, Ulan

2017-08-01

Process of eye tomogram obtaining by means of optical coherent tomography is studied. Stages of idiopathic macula holes formation in the process of eye grounds diagnostics are considered. Main stages of retina pathology progression are determined: Fuzzy logic units for obtaining reliable conclusions regarding the result of diagnosis are developed. By the results of theoretical and practical research system and technique of retinal macular region of the eye state analysis is developed ; application of the system, based on fuzzy logic device, improves the efficiency of eye retina complex.

Design and Implementation of an MC68020-Based Educational Computer Board

DTIC Science & Technology

1989-12-01

device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to initialize...MHz. It includes four * Static Random Access Memory (SRAM) chips which provide a storage of 32K bytes. Two Programmable Array Logic (PAL) chips...device and the other for a Macintosh personal computer. A stored program can be installed in 8K bytes Programmable Read Only Memory (PROM) to

Single InAs/GaSb nanowire low-power CMOS inverter.

PubMed

Dey, Anil W; Svensson, Johannes; Borg, B Mattias; Ek, Martin; Wernersson, Lars-Erik

2012-11-14

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Design and fuzzy logic control of an active wrist orthosis.

PubMed

Kilic, Ergin; Dogan, Erdi

2017-08-01

People who perform excessive wrist movements throughout the day because of their professions have a higher risk of developing lateral and medial epicondylitis. If proper precautions are not taken against these diseases, serious consequences such as job loss and early retirement can occur. In this study, the design and control of an active wrist orthosis that is mobile, powerful and lightweight is presented as a means to avoid the occurrence and/or for the treatment of repetitive strain injuries in an effective manner. The device has an electromyography-based control strategy so that the user's intention always comes first. In fact, the device-user interaction is mainly activated by the electromyography signals measured from the forearm muscles that are responsible for the extension and flexion wrist movements. Contractions of the muscles are detected using surface electromyography sensors, and the desired quantity of the velocity value of the wrist is extracted from a fuzzy logic controller. Then, the actuator system of the device comes into play by conveying the necessary motion support to the wrist. Experimental studies show that the presented device actually reduces the demand on the muscles involved in repetitive strain injuries while performing challenging daily life activities including extension and flexion wrist motions.

Performance evaluation of electro-optic effect based graphene transistors

NASA Astrophysics Data System (ADS)

Gupta, Gaurav; Abdul Jalil, Mansoor Bin; Yu, Bin; Liang, Gengchiau

2012-09-01

Despite the advantages afforded by the unique electronic properties of graphene, the absence of a bandgap has limited its applicability in logic devices. This has led to a study on electro-optic behavior in graphene for novel device operations, beyond the conventional field effect, to meet the requirements of ultra-low power and high-speed logic transistors. Recently, two potential designs have been proposed to leverage on this effect and open a virtual bandgap for ballistic transport in the graphene channel. The first one implements a barrier in the centre of the channel, whereas the second incorporates a tilted gate junction. In this paper, we computationally evaluate the relative device performance of these two designs, in terms of subthreshold slope (SS) and ION/IOFF ratio under different temperature and voltage bias, for a defect-free graphene channel. Our calculations employ pure optical modeling for low field electron transport under the constraints of device anatomy. The calculated results show that the two designs are functionally similar and are able to provide SS smaller than 60 mV per decade. Both designs show similar device performance but marginally top one another under different operating constraints. Our results could serve as a guide to circuit designers in selecting an appropriate design as per their system specifications and requirements.

Performance evaluation of electro-optic effect based graphene transistors.

PubMed

Gupta, Gaurav; Jalil, Mansoor Bin Abdul; Yu, Bin; Liang, Gengchiau

2012-10-21

Despite the advantages afforded by the unique electronic properties of graphene, the absence of a bandgap has limited its applicability in logic devices. This has led to a study on electro-optic behavior in graphene for novel device operations, beyond the conventional field effect, to meet the requirements of ultra-low power and high-speed logic transistors. Recently, two potential designs have been proposed to leverage on this effect and open a virtual bandgap for ballistic transport in the graphene channel. The first one implements a barrier in the centre of the channel, whereas the second incorporates a tilted gate junction. In this paper, we computationally evaluate the relative device performance of these two designs, in terms of subthreshold slope (SS) and I(ON)/I(OFF) ratio under different temperature and voltage bias, for a defect-free graphene channel. Our calculations employ pure optical modeling for low field electron transport under the constraints of device anatomy. The calculated results show that the two designs are functionally similar and are able to provide SS smaller than 60 mV per decade. Both designs show similar device performance but marginally top one another under different operating constraints. Our results could serve as a guide to circuit designers in selecting an appropriate design as per their system specifications and requirements.

Eight-Channel Digital Signal Processor and Universal Trigger Module

NASA Astrophysics Data System (ADS)

Skulski, Wojtek; Wolfs, Frank

2003-04-01

A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

Material Targets for Scaling All-Spin Logic

NASA Astrophysics Data System (ADS)

Manipatruni, Sasikanth; Nikonov, Dmitri E.; Young, Ian A.

2016-01-01

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy (Hk ) and saturation magnetization (Ms ), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet-spin-channel interface (Gmix ). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

Performance characteristics of a nanoscale double-gate reconfigurable array

NASA Astrophysics Data System (ADS)

Beckett, Paul

2008-12-01

The double gate transistor is a promising device applicable to deep sub-micron design due to its inherent resistance to short-channel effects and superior subthreshold performance. Using both TCAD and SPICE circuit simulation, it is shown that the characteristics of fully depleted dual-gate thin-body Schottky barrier silicon transistors will not only uncouple the conflicting requirements of high performance and low standby power in digital logic, but will also allow the development of a locally-connected reconfigurable computing mesh. The magnitude of the threshold shift effect will scale with device dimensions and will remain compatible with oxide reliability constraints. A field-programmable architecture based on the double gate transistor is described in which the operating point of the circuit is biased via one gate while the other gate is used to form the logic array, such that complex heterogeneous computing functions may be developed from this homogeneous, mesh-connected organization.

Fully chip-embedded automation of a multi-step lab-on-a-chip process using a modularized timer circuit.

PubMed

Kang, Junsu; Lee, Donghyeon; Heo, Young Jin; Chung, Wan Kyun

2017-11-07

For highly-integrated microfluidic systems, an actuation system is necessary to control the flow; however, the bulk of actuation devices including pumps or valves has impeded the broad application of integrated microfluidic systems. Here, we suggest a microfluidic process control method based on built-in microfluidic circuits. The circuit is composed of a fluidic timer circuit and a pneumatic logic circuit. The fluidic timer circuit is a serial connection of modularized timer units, which sequentially pass high pressure to the pneumatic logic circuit. The pneumatic logic circuit is a NOR gate array designed to control the liquid-controlling process. By using the timer circuit as a built-in signal generator, multi-step processes could be done totally inside the microchip without any external controller. The timer circuit uses only two valves per unit, and the number of process steps can be extended without limitation by adding timer units. As a demonstration, an automation chip has been designed for a six-step droplet treatment, which entails 1) loading, 2) separation, 3) reagent injection, 4) incubation, 5) clearing and 6) unloading. Each process was successfully performed for a pre-defined step-time without any external control device.

Programmable logic devices

NASA Astrophysics Data System (ADS)

Jacobs, J. L.

1993-04-01

Erasable programmable logic devices (EPLD's) were investigated to determine their advantages and/or disadvantages in Test Equipment Engineering applications. It was found that EPLD's performed as well as or better than identical circuits using standard transistor transistor logic (TTL). The chip count in these circuits was reduced, saving printed circuit board space and shortening fabrication and prove-in time. Troubleshooting circuits of EPLD's was also easier with 10 to 100 times fewer wires needed. The reduced number of integrated circuits (IC's) contributed to faster system speeds and an overall lower power consumption. In some cases changes to the circuit became software changes using EPLD's instead of hardware changes for standard logic. Using EPLD's was fairly easy; however, as with any new technology, a learning curve must be overcome before EPLD's can be used efficiently. The many benefits of EPLD's outweighed this initial inconvenience.

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Design of optical seven-segment decoder using Pockel's effect inside lithium niobate-based waveguide

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep

2017-01-01

Seven-segment decoder is a device that allows placing digital information from many inputs to many outputs optically, having 11 Mach-Zehnder interferometers (MZIs) for their implementation. The layout of the circuit is implemented to fit the electrical method on an optical logic circuit based on the beam propagation method (BPM). Seven-segment decoder is proposed using electro-optic effect inside lithium niobate-based MZIs. MZI structures are able to switch an optical signal to a desired output port. It consists of a mathematical explanation about the proposed device. The BPM is also used to analyze the study.

Access control mechanism of wireless gateway based on open flow

NASA Astrophysics Data System (ADS)

Peng, Rong; Ding, Lei

2017-08-01

In order to realize the access control of wireless gateway and improve the access control of wireless gateway devices, an access control mechanism of SDN architecture which is based on Open vSwitch is proposed. The mechanism utilizes the features of the controller--centralized control and programmable. Controller send access control flow table based on the business logic. Open vSwitch helps achieve a specific access control strategy based on the flow table.

Design of 4 to 2 line encoder using lithium niobate based Mach Zehnder Interferometers for high speed communication

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep; Raghuwanshi, Sanjeev K.

2016-04-01

Encoder is a device that allows placing digital information from many inputs to many outputs. Any application of combinational logic circuit can be implemented by using encoder and external gates. In this paper, 4 to 2 line encoder is proposed using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers (MZIs). The MZI structures have powerful capability to switching an optical input signal to a desired output port. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

A Novel Hybrid Intelligent Indoor Location Method for Mobile Devices by Zones Using Wi-Fi Signals

PubMed Central

Castañón–Puga, Manuel; Salazar, Abby Stephanie; Aguilar, Leocundo; Gaxiola-Pacheco, Carelia; Licea, Guillermo

2015-01-01

The increasing use of mobile devices in indoor spaces brings challenges to location methods. This work presents a hybrid intelligent method based on data mining and Type-2 fuzzy logic to locate mobile devices in an indoor space by zones using Wi-Fi signals from selected access points (APs). This approach takes advantage of wireless local area networks (WLANs) over other types of architectures and implements the complete method in a mobile application using the developed tools. Besides, the proposed approach is validated by experimental data obtained from case studies and the cross-validation technique. For the purpose of generating the fuzzy rules that conform to the Takagi–Sugeno fuzzy system structure, a semi-supervised data mining technique called subtractive clustering is used. This algorithm finds centers of clusters from the radius map given by the collected signals from APs. Measurements of Wi-Fi signals can be noisy due to several factors mentioned in this work, so this method proposed the use of Type-2 fuzzy logic for modeling and dealing with such uncertain information. PMID:26633417

A Novel Hybrid Intelligent Indoor Location Method for Mobile Devices by Zones Using Wi-Fi Signals.

PubMed

Castañón-Puga, Manuel; Salazar, Abby Stephanie; Aguilar, Leocundo; Gaxiola-Pacheco, Carelia; Licea, Guillermo

2015-12-02

The increasing use of mobile devices in indoor spaces brings challenges to location methods. This work presents a hybrid intelligent method based on data mining and Type-2 fuzzy logic to locate mobile devices in an indoor space by zones using Wi-Fi signals from selected access points (APs). This approach takes advantage of wireless local area networks (WLANs) over other types of architectures and implements the complete method in a mobile application using the developed tools. Besides, the proposed approach is validated by experimental data obtained from case studies and the cross-validation technique. For the purpose of generating the fuzzy rules that conform to the Takagi-Sugeno fuzzy system structure, a semi-supervised data mining technique called subtractive clustering is used. This algorithm finds centers of clusters from the radius map given by the collected signals from APs. Measurements of Wi-Fi signals can be noisy due to several factors mentioned in this work, so this method proposed the use of Type-2 fuzzy logic for modeling and dealing with such uncertain information.

Polymer-electrolyte-gated nanowire synaptic transistors for neuromorphic applications

NASA Astrophysics Data System (ADS)

Zou, Can; Sun, Jia; Gou, Guangyang; Kong, Ling-An; Qian, Chuan; Dai, Guozhang; Yang, Junliang; Guo, Guang-hua

2017-09-01

Polymer-electrolytes are formed by dissolving a salt in polymer instead of water, the conducting mechanism involves the segmental motion-assisted diffusion of ion in the polymer matrix. Here, we report on the fabrication of tin oxide (SnO2) nanowire synaptic transistors using polymer-electrolyte gating. A thin layer of poly(ethylene oxide) and lithium perchlorate (PEO/LiClO4) was deposited on top of the devices, which was used to boost device performances. A voltage spike applied on the in-plane gate attracts ions toward the polymer-electrolyte/SnO2 nanowire interface and the ions are gradually returned after the pulse is removed, which can induce a dynamic excitatory postsynaptic current in the nanowire channel. The SnO2 synaptic transistors exhibit the behavior of short-term plasticity like the paired-pulse facilitation and self-adaptation, which is related to the electric double-effect regulation. In addition, the synaptic logic functions and the logical function transformation are also discussed. Such single SnO2 nanowire-based synaptic transistors are of great importance for future neuromorphic devices.

FPGA-Based Multiprocessor System for Injection Molding Control

PubMed Central

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

2012-01-01

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

Patterning control strategies for minimum edge placement error in logic devices

NASA Astrophysics Data System (ADS)

Mulkens, Jan; Hanna, Michael; Slachter, Bram; Tel, Wim; Kubis, Michael; Maslow, Mark; Spence, Chris; Timoshkov, Vadim

2017-03-01

In this paper we discuss the edge placement error (EPE) for multi-patterning semiconductor manufacturing. In a multi-patterning scheme the creation of the final pattern is the result of a sequence of lithography and etching steps, and consequently the contour of the final pattern contains error sources of the different process steps. We describe the fidelity of the final pattern in terms of EPE, which is defined as the relative displacement of the edges of two features from their intended target position. We discuss our holistic patterning optimization approach to understand and minimize the EPE of the final pattern. As an experimental test vehicle we use the 7-nm logic device patterning process flow as developed by IMEC. This patterning process is based on Self-Aligned-Quadruple-Patterning (SAQP) using ArF lithography, combined with line cut exposures using EUV lithography. The computational metrology method to determine EPE is explained. It will be shown that ArF to EUV overlay, CDU from the individual process steps, and local CD and placement of the individual pattern features, are the important contributors. Based on the error budget, we developed an optimization strategy for each individual step and for the final pattern. Solutions include overlay and CD metrology based on angle resolved scatterometry, scanner actuator control to enable high order overlay corrections and computational lithography optimization to minimize imaging induced pattern placement errors of devices and metrology targets.

Proposal for a graphene-based all-spin logic gate

NASA Astrophysics Data System (ADS)

Su, Li; Zhao, Weisheng; Zhang, Yue; Querlioz, Damien; Zhang, Youguang; Klein, Jacques-Olivier; Dollfus, Philippe; Bournel, Arnaud

2015-02-01

In this work, we present a graphene-based all-spin logic gate (G-ASLG) that integrates the functionalities of perpendicular anisotropy magnetic tunnel junctions (p-MTJs) with spin transport in graphene-channel. It provides an ideal integration of logic and memory. The input and output states are defined as the relative magnetization between free layer and fixed layer of p-MTJs. They can be probed by the tunnel magnetoresistance and controlled by spin transfer torque effect. Using lateral non-local spin valve, the spin information is transmitted by the spin-current interaction through graphene channels. By using a physics-based spin current compact model, the operation of G-ASLG is demonstrated and its performance is analyzed. It allows us to evaluate the influence of parameters, such as spin injection efficiency, spin diffusion length, contact area, the device length, and their interdependence, and to optimize the energy and dynamic performance. Compared to other beyond-CMOS solutions, longer spin information transport length (˜μm), higher data throughput, faster computing speed (˜ns), and lower power consumption (˜μA) can be expected from the G-ASLG.

Selectivity Enhancement by Using Double-Layer MOX-Based Gas Sensors Prepared by Flame Spray Pyrolysis (FSP).

PubMed

Rebholz, Julia; Grossmann, Katharina; Pham, David; Pokhrel, Suman; Mädler, Lutz; Weimar, Udo; Barsan, Nicolae

2016-09-06

Here we present a novel concept for the selective recognition of different target gases with a multilayer semiconducting metal oxide (SMOX)-based sensor device. Direct current (DC) electrical resistance measurements were performed during exposure to CO and ethanol as single gases and mixtures of highly porous metal oxide double- and single-layer sensors obtained by flame spray pyrolysis. The results show that the calculated resistance ratios of the single- and double-layer sensors are a good indicator for the presence of specific gases in the atmosphere, and can constitute some building blocks for the development of chemical logic devices. Due to the inherent lack of selectivity of SMOX-based gas sensors, such devices could be especially relevant for domestic applications.

Selectivity Enhancement by Using Double-Layer MOX-Based Gas Sensors Prepared by Flame Spray Pyrolysis (FSP)

PubMed Central

Rebholz, Julia; Grossmann, Katharina; Pham, David; Pokhrel, Suman; Mädler, Lutz; Weimar, Udo; Barsan, Nicolae

2016-01-01

Here we present a novel concept for the selective recognition of different target gases with a multilayer semiconducting metal oxide (SMOX)-based sensor device. Direct current (DC) electrical resistance measurements were performed during exposure to CO and ethanol as single gases and mixtures of highly porous metal oxide double- and single-layer sensors obtained by flame spray pyrolysis. The results show that the calculated resistance ratios of the single- and double-layer sensors are a good indicator for the presence of specific gases in the atmosphere, and can constitute some building blocks for the development of chemical logic devices. Due to the inherent lack of selectivity of SMOX-based gas sensors, such devices could be especially relevant for domestic applications. PMID:27608028

Multilevel Resistance Programming in Conductive Bridge Resistive Memory

NASA Astrophysics Data System (ADS)

Mahalanabis, Debayan

This work focuses on the existence of multiple resistance states in a type of emerging non-volatile resistive memory device known commonly as Programmable Metallization Cell (PMC) or Conductive Bridge Random Access Memory (CBRAM), which can be important for applications such as multi-bit memory as well as non-volatile logic and neuromorphic computing. First, experimental data from small signal, quasi-static and pulsed mode electrical characterization of such devices are presented which clearly demonstrate the inherent multi-level resistance programmability property in CBRAM devices. A physics based analytical CBRAM compact model is then presented which simulates the ion-transport dynamics and filamentary growth mechanism that causes resistance change in such devices. Simulation results from the model are fitted to experimental dynamic resistance switching characteristics. The model designed using Verilog-a language is computation-efficient and can be integrated with industry standard circuit simulation tools for design and analysis of hybrid circuits involving both CMOS and CBRAM devices. Three main circuit applications for CBRAM devices are explored in this work. Firstly, the susceptibility of CBRAM memory arrays to single event induced upsets is analyzed via compact model simulation and experimental heavy ion testing data that show possibility of both high resistance to low resistance and low resistance to high resistance transitions due to ion strikes. Next, a non-volatile sense amplifier based flip-flop architecture is proposed which can help make leakage power consumption negligible by allowing complete shutdown of power supply while retaining its output data in CBRAM devices. Reliability and energy consumption of the flip-flop circuit for different CBRAM low resistance levels and supply voltage values are analyzed and compared to CMOS designs. Possible extension of this architecture for threshold logic function computation using the CBRAM devices as re-configurable resistive weights is also discussed. Lastly, Spike timing dependent plasticity (STDP) based gradual resistance change behavior in CBRAM device fabricated in back-end-of-line on a CMOS die containing integrate and fire CMOS neuron circuits is demonstrated for the first time which indicates the feasibility of using CBRAM devices as electronic synapses in spiking neural network hardware implementations for non-Boolean neuromorphic computing.

High performance Si nanowire field-effect-transistors based on a CMOS inverter with tunable threshold voltage.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Sohn, Jung Inn; Cha, Seung Nam; Whang, Dongmok; Kim, Jong Min; Kang, Dae Joon

2014-05-21

We successfully fabricated nanowire-based complementary metal-oxide semiconductor (NWCMOS) inverter devices by utilizing n- and p-type Si nanowire field-effect-transistors (NWFETs) via a low-temperature fabrication processing technique. We demonstrate that NWCMOS inverter devices can be operated at less than 1 V, a significantly lower voltage than that of typical thin-film based complementary metal-oxide semiconductor (CMOS) inverter devices. This low-voltage operation was accomplished by controlling the threshold voltage of the n-type Si NWFETs through effective management of the nanowire (NW) doping concentration, while realizing high voltage gain (>10) and ultra-low static power dissipation (≤3 pW) for high-performance digital inverter devices. This result offers a viable means of fabricating high-performance, low-operation voltage, and high-density digital logic circuits using a low-temperature fabrication processing technique suitable for next-generation flexible electronics.

Energy Management of An Extended Hybrid Renewable Energy System For Isolated Sites Using A Fuzzy Logic Controller

NASA Astrophysics Data System (ADS)

Faquir, Sanaa; Yahyaouy, Ali; Tairi, Hamid; Sabor, Jalal

2018-05-01

This paper presents the implementation of a fuzzy logic controller to manage the flow of energy in an extended hybrid renewable energy system employed to satisfy the load for a wide isolated site at the city of Essaouira in Morocco. To achieve Efficient energy management, the system is combining two important renewable energies: solar and wind. Lithium Ion batteries were also used as storage devices to store the excess of energy provided by the renewable sources or to supply the system with the required energy when the energy delivered by the input sources is not enough to satisfy the load demand. To manage the energy in the system, a controller based on fuzzy logic was implemented. Real data taken from previous research and meteorological sites was used to test the controller.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

1998-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter's column will include some announcements and some recent radiation test results and evaluations of interest. Specifically, the following topics will be covered: the Military and Aerospace Applications of Programmable Devices and Technologies Conference to be held at GSFC in September, 1998, proton test results, and some total dose results.

A specification of 3D manipulation in virtual environments

NASA Technical Reports Server (NTRS)

Su, S. Augustine; Furuta, Richard

1994-01-01

In this paper we discuss the modeling of three basic kinds of 3-D manipulations in the context of a logical hand device and our virtual panel architecture. The logical hand device is a useful software abstraction representing hands in virtual environments. The virtual panel architecture is the 3-D component of the 2-D window systems. Both of the abstractions are intended to form the foundation for adaptable 3-D manipulation.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Knowledge system and method for simulating chemical controlled release device performance

DOEpatents

Cowan, Christina E.; Van Voris, Peter; Streile, Gary P.; Cataldo, Dominic A.; Burton, Frederick G.

1991-01-01

A knowledge system for simulating the performance of a controlled release device is provided. The system includes an input device through which the user selectively inputs one or more data parameters. The data parameters comprise first parameters including device parameters, media parameters, active chemical parameters and device release rate; and second parameters including the minimum effective inhibition zone of the device and the effective lifetime of the device. The system also includes a judgemental knowledge base which includes logic for 1) determining at least one of the second parameters from the release rate and the first parameters and 2) determining at least one of the first parameters from the other of the first parameters and the second parameters. The system further includes a device for displaying the results of the determinations to the user.

Two-dimensional radiant energy array computers and computing devices

NASA Technical Reports Server (NTRS)

Schaefer, D. H.; Strong, J. P., III (Inventor)

1976-01-01

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

Construction and Operation of Three-Dimensional Memory and Logic Molecular Devices and Circuits

DTIC Science & Technology

2013-07-01

higher currents and less leakage. We also constructed a ferrocene -based self-assembling monolayer attached to gold nanoparticles, exhibiting a...charging transistor utilizing Ferrocene -based SAM attached to gold nano-particle. Our experiments are, to our knowledge, the first to exhibit an...The molecular layer includes a ferrocene SAM attached to Au Distribution A: Approved for public release; distribution is unlimited

Reconfigurable logic in nanosecond Cu/GeTe/TiN filamentary memristors for energy-efficient in-memory computing.

PubMed

Jin, Miaomiao; Cheng, Long; Li, Yi; Hu, Siyu; Lu, Ke; Chen, Jia; Duan, Nian; Wang, Zhuorui; Zhou, Yaxiong; Chang, Ting-Chang; Miao, Xiangshui

2018-06-27

Owing to the capability of integrating the information storage and computing in the same physical location, in-memory computing with memristors has become a research hotspot as a promising route for non von Neumann architecture. However, it is still a challenge to develop high performance devices as well as optimized logic methodologies to realize energy-efficient computing. Herein, filamentary Cu/GeTe/TiN memristor is reported to show satisfactory properties with nanosecond switching speed (< 60 ns), low voltage operation (< 2 V), high endurance (>104 cycles) and good retention (>104 s @85℃). It is revealed that the charge carrier conduction mechanisms in high resistance and low resistance states are Schottky emission and hopping transport between the adjacent Cu clusters, respectively, based on the analysis of current-voltage behaviors and resistance-temperature characteristics. An intuitive picture is given to describe the dynamic processes of resistive switching. Moreover, based on the basic material implication (IMP) logic circuit, we proposed a reconfigurable logic method and experimentally implemented IMP, NOT, OR, and COPY logic functions. Design of a one-bit full adder with reduction in computational sequences and its validation in simulation further demonstrate the potential practical application. The results provide important progress towards understanding of resistive switching mechanism and realization of energy-efficient in-memory computing architecture. © 2018 IOP Publishing Ltd.

Giant spin Hall angle from topological insulator BixSe(1 - x) thin films

NASA Astrophysics Data System (ADS)

Dc, Mahendra; Jamali, Mahdi; Chen, Junyang; Hickey, Danielle; Zhang, Delin; Zhao, Zhengyang; Li, Hongshi; Quarterman, Patrick; Lv, Yang; Mkhyon, Andre; Wang, Jian-Ping

Investigation on the spin-orbit torque (SOT) from large spin-orbit coupling materials has been attracting interest because of its low power switching of the magnetization and ultra-fast driving of the domain wall motion that can be used in future spin based memory and logic devices. We investigated SOT from topological insulator BixSe(1 - x) thin film in BixSe(1 - x) /CoFeB heterostructure by using the dc planar Hall method, where BixSe(1 - x) thin films were prepared by a unique industry-compatible deposition process. The angle dependent Hall resistance was measured in the presence of a rotating external in-plane magnetic field at bipolar currents. The spin Hall angle (SHA) from this BixSe(1 - x) thin film was found to be as large as 22.41, which is the largest ever reported at room temperature (RT). The giant SHA and large spin Hall conductivity (SHC) make this BixSe(1 - x) thin film a very strong candidate as an SOT generator in SOT based memory and logic devices.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

DOEpatents

Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

2013-05-21

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Single event upset sensitivity of low power Schottky devices

NASA Technical Reports Server (NTRS)

Price, W. E.; Nichols, D. K.; Measel, P. R.; Wahlin, K. L.

1982-01-01

Data taken from tests involving heavy ions in the Berkeley 88 in. cyclotron being directed at low power Schottky barrier devices are reported. The tests also included trials in the Harvard cyclotron with 130 MeV protons, and at the U.C. Davis cyclotron using 56 MeV protons. The experiments were performed to study the single event upsets in MSI logic devices containing flip-flops. Results are presented of single-event upsets (SEU) causing functional degradation observed in post-exposure tests of six different devices. The effectiveness of the particles in producing SEUs in logic device functioning was found to be directly proportional to the proton energy. Shielding was determined to offer negligible protection from the particle bombardment. The results are considered significant for the design and fabrication of LS devices for space applications.

Towards bioelectronic logic (Conference Presentation)

NASA Astrophysics Data System (ADS)

Meredith, Paul; Mostert, Bernard; Sheliakina, Margarita; Carrad, Damon J.; Micolich, Adam P.

2016-09-01

One of the critical tasks in realising a bioelectronic interface is the transduction of ion and electron signals at high fidelity, and with appropriate speed, bandwidth and signal-to-noise ratio [1]. This is a challenging task considering ions and electrons (or holes) have drastically different physics. For example, even the lightest ions (protons) have mobilities much smaller than electrons in the best semiconductors, effective masses are quite different, and at the most basic level, ions are `classical' entities and electrons `quantum mechanical'. These considerations dictate materials and device strategies for bioelectronic interfaces alongside practical aspects such as integration and biocompatibility [2]. In my talk I will detail these `differences in physics' that are pertinent to the ion-electron transduction challenge. From this analysis, I will summarise the basic categories of device architecture that are possibilities for transducing elements and give recent examples of their realisation. Ultimately, transducing elements need to be combined to create `bioelectronic logic' capable of signal processing at the interface level. In this regard, I will extend the discussion past the single element concept, and discuss our recent progress in delivering all-solids-state logic circuits based upon transducing interfaces. [1] "Ion bipolar junction transistors", K. Tybrandt, K.C. Larsson, A. Richter-Dahlfors and M. Berggren, Proc. Natl Acad. Sci., 107, 9929 (2010). [2] "Electronic and optoelectronic materials and devices inspired by nature", P Meredith, C.J. Bettinger, M. Irimia-Vladu, A.B. Mostert and P.E. Schwenn, Reports on Progress in Physics, 76, 034501 (2013).

All-optical universal logic gates on nonlinear multimode interference coupler using tunable input intensity

NASA Astrophysics Data System (ADS)

Tajaldini, Mehdi; Jafri, Mohd Zubir Mat

2015-04-01

The theory of Nonlinear Modal Propagation Analysis Method (NMPA) have shown significant features of nonlinear multimode interference (MMI) coupler with compact dimension and when launched near the threshold of nonlinearity. Moreover, NMPA have the potential to allow studying the nonlinear MMI based the modal interference to explorer the phenomenon that what happen due to the natural of multimode region. Proposal of all-optical switch based NMPA has approved its capability to achieving the all-optical gates. All-optical gates have attracted increasing attention due to their practical utility in all-optical signal processing networks and systems. Nonlinear multimode interference devices could apply as universal all-optical gates due to significant features that NMPA introduce them. In this Paper, we present a novel Ultra-compact MMI coupler based on NMPA method in low intensity compared to last reports either as a novel design method and potential application for optical NAND, NOR as universal gates on single structure for Boolean logic signal processing devices and optimize their application via studding the contrast ratio between ON and OFF as a function of output width. We have applied NMPA for several applications so that the miniaturization in low nonlinear intensities is their main purpose.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Montenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Intelligent control of a multi-degree-of freedom reaction compensating platform system using fuzzy logic

NASA Technical Reports Server (NTRS)

Choi, Benjamin B.; Lawrence, Charles; Lin, Yueh-Jaw

1994-01-01

This paper presents the development of a general-purpose fuzzy logic (FL) control methodology for isolating the external vibratory disturbances of space-based devices. According to the desired performance specifications, a full investigation regarding the development of an FL controller was done using different scenarios, such as variances of passive reaction-compensating components and external disturbance load. It was shown that the proposed FL controller is robust in that the FL-controlled system closely follows the prespecified ideal reference model. The comparative study also reveals that the FL-controlled system achieves significant improvement in reducing vibrations over passive systems.

Defect Dynamics in Artificial Colloidal Ice: Real-Time Observation, Manipulation, and Logic Gate.

PubMed

Loehr, Johannes; Ortiz-Ambriz, Antonio; Tierno, Pietro

2016-10-14

We study the defect dynamics in a colloidal spin ice system realized by filling a square lattice of topographic double well islands with repulsively interacting magnetic colloids. We focus on the contraction of defects in the ground state, and contraction or expansion in a metastable biased state. Combining real-time experiments with simulations, we prove that these defects behave like emergent topological monopoles obeying a Coulomb law with an additional line tension. We further show how to realize a completely resettable "nor" gate, which provides guidelines for fabrication of nanoscale logic devices based on the motion of topological magnetic monopoles.

Memristor-based programmable logic array (PLA) and analysis as Memristive networks.

PubMed

Lee, Kwan-Hee; Lee, Sang-Jin; Kim, Seok-Man; Cho, Kyoungrok

2013-05-01

A Memristor theorized by Chua in 1971 has the potential to dramatically influence the way electronic circuits are designed. It is a two terminal device whose resistance state is based on the history of charge flow brought about as the result of the voltage being applied across its terminals and hence can be thought of as a special case of a reconfigurable resistor. Nanoscale devices using dense and regular fabrics such as Memristor cross-bar is promising new architecture for System-on-Chip (SoC) implementations in terms of not only the integration density that the technology can offer but also both improved performance and reduced power dissipation. Memristor has the capacity to switch between high and low resistance states in a cross-bar circuit configuration. The cross-bars are formed from an array of vertical conductive nano-wires cross a second array of horizontal conductive wires. Memristors are realized at the intersection of the two wires in the array through appropriate processing technology such that any particular wire in the vertical array can be connected to a wire in the horizontal array by switching the resistance of a particular intersection to a low state while other cross-points remain in a high resistance state. However the approach introduces a number of challenges. The lack of voltage gain prevents logic being cascaded and voltage level degradation affects robustness of the operation. Moreover the cross-bars introduce sneak current paths when two or more cross points are connected through the switched Memristor. In this paper, we propose Memristor-based programmable logic array (PLA) architecture and develop an analytical model to analyze the logic level on the memristive networks. The proposed PLA architecture has 12 inputs maximum and can be cascaded for more input variables with R(off)/R(on) ratio in the range from 55 to 160 of Memristors.

Energy Efficient Digital Logic Using Nanoscale Magnetic Devices

NASA Astrophysics Data System (ADS)

Lambson, Brian James

Increasing demand for information processing in the last 50 years has been largely satisfied by the steadily declining price and improving performance of microelectronic devices. Much of this progress has been made by aggressively scaling the size of semiconductor transistors and metal interconnects that microprocessors are built from. As devices shrink to the size regime in which quantum effects pose significant challenges, new physics may be required in order to continue historical scaling trends. A variety of new devices and physics are currently under investigation throughout the scientific and engineering community to meet these challenges. One of the more drastic proposals on the table is to replace the electronic components of information processors with magnetic components. Magnetic components are already commonplace in computers for their information storage capability. Unlike most electronic devices, magnetic materials can store data in the absence of a power supply. Today's magnetic hard disk drives can routinely hold billions of bits of information and are in widespread commercial use. Their ability to function without a constant power source hints at an intrinsic energy efficiency. The question we investigate in this dissertation is whether or not this advantage can be extended from information storage to the notoriously energy intensive task of information processing. Several proof-of-concept magnetic logic devices were proposed and tested in the past decade. In this dissertation, we build on the prior work by answering fundamental questions about how magnetic devices achieve such high energy efficiency and how they can best function in digital logic applications. The results of this analysis are used to suggest and test improvements to nanomagnetic computing devices. Two of our results are seen as especially important to the field of nanomagnetic computing: (1) we show that it is possible to operate nanomagnetic computers at the fundamental thermodyanimic limits of computation and (2) we develop a nanomagnet with a unique shape that is engineered to significantly improve the reliability of nanomagnetic logic.

Processing device with self-scrubbing logic

DOEpatents

Wojahn, Christopher K.

2016-03-01

An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configuration memory in response to a data feed signal outputted by the self-scrubber logic.

Practical applications of digital integrated circuits. Part 2: Minimization techniques, code conversion, flip-flops, and asynchronous circuits

NASA Technical Reports Server (NTRS)

1972-01-01

Here, the 7400 line of transistor to transistor logic (TTL) devices is emphasized almost exclusively where hardware is concerned. However, it should be pointed out that the logic theory contained herein applies to all hardware. Binary numbers, simplification of logic circuits, code conversion circuits, basic flip-flop theory, details about series 54/7400, and asynchronous circuits are discussed.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Using a Commercial Ethernet PHY Device in a Radiation Environment

NASA Technical Reports Server (NTRS)

Parks, Jeremy; Arani, Michael; Arroyo, Roberto

2014-01-01

This work involved placing a commercial Ethernet PHY on its own power boundary, with limited current supply, and providing detection methods to determine when the device is not operating and when it needs either a reset or power-cycle. The device must be radiation-tested and free of destructive latchup errors. The commercial Ethernet PHY's own power boundary must be supplied by a current-limited power regulator that must have an enable (for power cycling), and its maximum power output must not exceed the PHY's input requirements, thus preventing damage to the device. A regulator with configurable output limits and short-circuit protection (such as the RHFL4913, rad hard positive voltage regulator family) is ideal. This will prevent a catastrophic failure due to radiation (such as a short between the commercial device's power and ground) from taking down the board's main power. Logic provided on the board will detect errors in the PHY. An FPGA (field-programmable gate array) with embedded Ethernet MAC (Media Access Control) will work well. The error detection includes monitoring the PHY's interrupt line, and the status of the Ethernet's switched power. When the PHY is determined to be non-functional, the logic device resets the PHY, which will often clear radiation induced errors. If this doesn't work, the logic device power-cycles the FPGA by toggling the regulator's enable input. This should clear almost all radiation induced errors provided the device is not latched up.

Coupling carbon nanomaterials with photochromic molecules for the generation of optically responsive materials

PubMed Central

Zhang, Xiaoyan; Hou, Lili; Samorì, Paolo

2016-01-01

Multifunctional carbon-based nanomaterials offer routes towards the realization of smart and high-performing (opto)electronic (nano)devices, sensors and logic gates. Meanwhile photochromic molecules exhibit reversible transformation between two forms, induced by the absorption of electromagnetic radiation. By combining carbon-based nanomaterials with photochromic molecules, one can achieve reversible changes in geometrical structure, electronic properties and nanoscale mechanics triggering by light. This thus enables a reversible modulation of numerous physical and chemical properties of the carbon-based nanomaterials towards the fabrication of cognitive devices. This review examines the state of the art with respect to these responsive materials, and seeks to identify future directions for investigation. PMID:27067387

Logic-centered architecture for ubiquitous health monitoring.

PubMed

Lewandowski, Jacek; Arochena, Hisbel E; Naguib, Raouf N G; Chao, Kuo-Ming; Garcia-Perez, Alexeis

2014-09-01

One of the key points to maintain and boost research and development in the area of smart wearable systems (SWS) is the development of integrated architectures for intelligent services, as well as wearable systems and devices for health and wellness management. This paper presents such a generic architecture for multiparametric, intelligent and ubiquitous wireless sensing platforms. It is a transparent, smartphone-based sensing framework with customizable wireless interfaces and plug'n'play capability to easily interconnect third party sensor devices. It caters to wireless body, personal, and near-me area networks. A pivotal part of the platform is the integrated inference engine/runtime environment that allows the mobile device to serve as a user-adaptable personal health assistant. The novelty of this system lays in a rapid visual development and remote deployment model. The complementary visual Inference Engine Editor that comes with the package enables artificial intelligence specialists, alongside with medical experts, to build data processing models by assembling different components and instantly deploying them (remotely) on patient mobile devices. In this paper, the new logic-centered software architecture for ubiquitous health monitoring applications is described, followed by a discussion as to how it helps to shift focus from software and hardware development, to medical and health process-centered design of new SWS applications.

International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

NASA Astrophysics Data System (ADS)

Ostrowsky, D. B.; Sriram, S.

Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

Transient fault behavior in a microprocessor: A case study

NASA Technical Reports Server (NTRS)

Duba, Patrick

1989-01-01

An experimental analysis is described which studies the susceptibility of a microprocessor based jet engine controller to upsets caused by current and voltage transients. A design automation environment which allows the run time injection of transients and the tracing from their impact device to the pin level is described. The resulting error data are categorized by the charge levels of the injected transients by location and by their potential to cause logic upsets, latched errors, and pin errors. The results show a 3 picoCouloumb threshold, below which the transients have little impact. An Arithmetic and Logic Unit transient is most likely to result in logic upsets and pin errors (i.e., impact the external environment). The transients in the countdown unit are potentially serious since they can result in latched errors, thus causing latent faults. Suggestions to protect the processor against these errors, by incorporating internal error detection and transient suppression techniques, are also made.

QCAPUF: QCA-based physically unclonable function as a hardware security primitive

NASA Astrophysics Data System (ADS)

Abutaleb, M. M.

2018-04-01

Physically unclonable functions (PUFs) are increasingly used as innovative security primitives to provide the hardware authentication and identification as well as the secret key generation based on unique and random variations in identically fabricated devices. Security and low power have appeared to become two crucial necessities to modern designs. As an emerging nanoelectronic technology, a quantum-dot cellular automata (QCA) can achieve ultra-low power consumption as well as an extremely small area for implementing digital designs. However, there are various classes of permanent defects that can happen during the manufacture of QCA devices. The recent extensive research has been focused on how to eliminate errors in QCA structures resulting from fabrication variances. By a completely different vision, to turn this disadvantage into an advantage, this paper presents a novel QCA-based PUF (QCAPUF) architecture to exploit the unique physical characteristics of fabricated QCA cells in order to produce different hardware fingerprint instances. This architecture is composed of proposed logic and interconnect blocks that have critical vulnerabilities and perform unexpected logical operations. The behaviour of QCAPUF is thoroughly analysed through physical relations and simulations. Results confirm that the proposed QCAPUF has state of the art PUF characteristics in the QCA technology. This paper will serve as a basis for further research into QCA-based hardware security primitives and applications.

A Proposal for IoT Dynamic Routes Selection Based on Contextual Information.

PubMed

Araújo, Harilton da Silva; Filho, Raimir Holanda; Rodrigues, Joel J P C; Rabelo, Ricardo de A L; Sousa, Natanael de C; Filho, José C C L S; Sobral, José V V

2018-01-26

The Internet of Things (IoT) is based on interconnection of intelligent and addressable devices, allowing their autonomy and proactive behavior with Internet connectivity. Data dissemination in IoT usually depends on the application and requires context-aware routing protocols that must include auto-configuration features (which adapt the behavior of the network at runtime, based on context information). This paper proposes an approach for IoT route selection using fuzzy logic in order to attain the requirements of specific applications. In this case, fuzzy logic is used to translate in math terms the imprecise information expressed by a set of linguistic rules. For this purpose, four Objective Functions (OFs) are proposed for the Routing Protocol for Low Power and Loss Networks (RPL); such OFs are dynamically selected based on context information. The aforementioned OFs are generated from the fusion of the following metrics: Expected Transmission Count (ETX), Number of Hops (NH) and Energy Consumed (EC). The experiments performed through simulation, associated with the statistical data analysis, conclude that this proposal provides high reliability by successfully delivering nearly 100% of data packets, low delay for data delivery and increase in QoS. In addition, an 30% improvement is attained in the network life time when using one of proposed objective function, keeping the devices alive for longer duration.

Experimental Demonstration of xor Operation in Graphene Magnetologic Gates at Room Temperature

NASA Astrophysics Data System (ADS)

Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Žutić, Igor; Krivorotov, Ilya; Sham, L. J.; Kawakami, Roland K.

2016-04-01

We report the experimental demonstration of a magnetologic gate built on graphene at room temperature. This magnetologic gate consists of three ferromagnetic electrodes contacting a single-layer graphene spin channel and relies on spin injection and spin transport in the graphene. We utilize electrical bias tuning of spin injection to balance the inputs and achieve "exclusive or" (xor) logic operation. Furthermore, a simulation of the device performance shows that substantial improvement towards spintronic applications can be achieved by optimizing the device parameters such as the device dimensions. This advance holds promise as a basic building block for spin-based information processing.

Advanced Electronic Structure Calculations For Nanoelectronics Using Finite Element Bases and Effective Mass Theory.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gamble, John King; Nielsen, Erik; Baczewski, Andrew David

This paper describes our work over the past few years to use tools from quantum chemistry to describe electronic structure of nanoelectronic devices. These devices, dubbed "artificial atoms", comprise a few electrons, con ned by semiconductor heterostructures, impurities, and patterned electrodes, and are of intense interest due to potential applications in quantum information processing, quantum sensing, and extreme-scale classical logic. We detail two approaches we have employed: nite-element and Gaussian basis sets, exploring the interesting complications that arise when techniques that were intended to apply to atomic systems are instead used for artificial, solid-state devices.

Low-voltage organic electronics based on a gate-tunable injection barrier in vertical graphene-organic semiconductor heterostructures.

PubMed

Hlaing, Htay; Kim, Chang-Hyun; Carta, Fabio; Nam, Chang-Yong; Barton, Rob A; Petrone, Nicholas; Hone, James; Kymissis, Ioannis

2015-01-14

The vertical integration of graphene with inorganic semiconductors, oxide semiconductors, and newly emerging layered materials has recently been demonstrated as a promising route toward novel electronic and optoelectronic devices. Here, we report organic thin film transistors based on vertical heterojunctions of graphene and organic semiconductors. In these thin heterostructure devices, current modulation is accomplished by tuning of the injection barriers at the semiconductor/graphene interface with the application of a gate voltage. N-channel devices fabricated with a thin layer of C60 show a room temperature on/off ratio >10(4) and current density of up to 44 mAcm(-2). Because of the ultrashort channel intrinsic to the vertical structure, the device is fully operational at a driving voltage of 200 mV. A complementary p-channel device is also investigated, and a logic inverter based on two complementary transistors is demonstrated. The vertical integration of graphene with organic semiconductors via simple, scalable, and low-temperature fabrication processes opens up new opportunities to realize flexible, transparent organic electronic, and optoelectronic devices.

Three-terminal resistive switching memory in a transparent vertical-configuration device

NASA Astrophysics Data System (ADS)

Ungureanu, Mariana; Llopis, Roger; Casanova, Fèlix; Hueso, Luis E.

2014-01-01

The resistive switching phenomenon has attracted much attention recently for memory applications. It describes the reversible change in the resistance of a dielectric between two non-volatile states by the application of electrical pulses. Typical resistive switching memories are two-terminal devices formed by an oxide layer placed between two metal electrodes. Here, we report on the fabrication and operation of a three-terminal resistive switching memory that works as a reconfigurable logic component and offers an increased logic density on chip. The three-terminal memory device we present is transparent and could be further incorporated in transparent computing electronic technologies.

Optical 1's and 2's complement devices using lithium-niobate-based waveguide

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep

2016-12-01

Optical 1's and 2's complement devices are proposed with the help of lithium-niobate-based Mach-Zehnder interferometers. It has a powerful capability of switching an optical signal from one port to the other port with the help of an electrical control signal. The paper includes the optical conversion scheme using sets of optical switches. 2's complement is common in computer systems and is used in binary subtraction and logical manipulation. The operation of the circuits is studied theoretically and analyzed through numerical simulations. The truth table of these complement methods is verified with the beam propagation method and MATLAB® simulation results.

Starting Circuit For Erasable Programmable Logic Device

NASA Technical Reports Server (NTRS)

Cole, Steven W.

1990-01-01

Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.

Glutathione-facilitated design and fabrication of gold nanoparticle-based logic gates and keypad lock.

PubMed

Huang, Zhenzhen; Wang, Haonan; Yang, Wensheng

2014-07-21

In this paper, we describe how we developed a simple design and fabrication method for logic gates and a device by using a commercially available tripeptide, namely glutathione (GSH), together with metal ions and disodium ethylenediaminetetraacetate (EDTA) to control the dispersion and aggregation of gold nanoparticles (NPs). With the fast adsorption of GSH on gold NPs and the strong coordination of GSH with metal ions, the addition of GSH and Pb(2+) ions immediately resulted in the aggregation of gold NPs, giving rise to an AND function. Either Pb(2+) or Ba(2+) ions induced the aggregation of gold NPs in the presence of GSH, supporting an OR gate. Based on the fact that EDTA has a strong capacity to bind metal ions, thus preventing the aggregation of gold NPs, an INHIBIT gate was also fabricated. More interestingly, we found that the addition sequence of GSH and Hg(2+) ions influenced the aggregation of gold NPs in a controlled manner, which was used to design a sequential logic gate and a three-input keypad lock for potential use in information security. The GSH strategy addresses concerns of low cost, simple fabrication, versatile design and easy operation, and offers a promising platform for the development of functional logic systems.

Learning with touchscreen devices: game strategies to improve geometric thinking

NASA Astrophysics Data System (ADS)

Soldano, Carlotta; Arzarello, Ferdinando

2016-03-01

The aim of this paper is to reflect on the importance of the students' game-strategic thinking during the development of mathematical activities. In particular, we hypothesise that this type of thinking helps students in the construction of logical links between concepts during the "argumentation phase" of the proving process. The theoretical background of our study lies in the works of J. Hintikka, a Finnish logician, who developed a new type of logic, based on game theory, called the logic of inquiry. In order to experiment with this new approach to the teaching and learning of mathematics, we have prepared five game-activities based on geometric theorems in which two players play against each other in a multi-touch dynamic geometric environment (DGE). In this paper, we present the design of the first game-activity and the relationship between it and the logic of inquiry. Then, adopting the theoretical framework of the instrumental genesis by Vérillon and Rabardel (EJPE 10: 77-101, 1995), we will present and analyse significant actions and dialogues developed by students while they are solving the game. We focus on the presence of a particular way of playing the game introduced by the students, the "reflected game", and highlight its functions for the development of the task.

Review of multi-layered magnetoelectric composite materials and devices applications

NASA Astrophysics Data System (ADS)

Chu, Zhaoqiang; PourhosseiniAsl, MohammadJavad; Dong, Shuxiang

2018-06-01

Multiferroic materials with the coexistence of at least two ferroic orders, such as ferroelectricity, ferromagnetism, or ferroelasticity, have recently attracted ever-increasing attention due to their potential for multifunctional device applications, including magnetic and current sensors, energy harvesters, magnetoelectric (ME) random access memory and logic devices, tunable microwave devices, and ME antenna. In this article, we provide a review of the recent and ongoing research efforts in the field of multi-layered ME composites. After a brief introduction to ME composites and ME coupling mechanisms, we review recent advances in multi-layered ME composites as well as their device applications based on the direct ME effect, magnetic sensors in particular. Finally, some remaining challenges and future perspective of ME composites and their engineering applications will be discussed.

Coupling Photonics and Coherent Spintronics for Low-Loss Flexible Optical Logic

DTIC Science & Technology

2015-12-02

AFRL-AFOSR-VA-TR-2016-0055 Coupling photonics and coherent spintronics for low-loss flexible optical logic Jesse Berezovsky CASE WESTERN RESERVE UNIV...2012 - 14/06/2015 4. TITLE AND SUBTITLE Coupling photonics and coherent spintronics for low-loss flexible optical logic 5a. CONTRACT NUMBER 5b...into devices, ranging from macroscopic optical cavities, to arrays of microlens cavities, to quantum dot-impregnated integrated polymer waveguides

Processing device with self-scrubbing logic

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wojahn, Christopher K.

An apparatus includes a processing unit including a configuration memory and self-scrubber logic coupled to read the configuration memory to detect compromised data stored in the configuration memory. The apparatus also includes a watchdog unit external to the processing unit and coupled to the self-scrubber logic to detect a failure in the self-scrubber logic. The watchdog unit is coupled to the processing unit to selectively reset the processing unit in response to detecting the failure in the self-scrubber logic. The apparatus also includes an external memory external to the processing unit and coupled to send configuration data to the configurationmore » memory in response to a data feed signal outputted by the self-scrubber logic.« less

Amplifying genetic logic gates.

PubMed

Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

2013-05-03

Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

Generalized look-ahead number conversion from signed digit to complement representation with optical logic operations

NASA Astrophysics Data System (ADS)

Qian, Feng; Li, Guoqiang

2001-12-01

In this paper a generalized look-ahead logic algorithm for number conversion from signed-digit to its complement representation is developed. By properly encoding the signed digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's complement, trinary signed-digit (TSD) to 3's complement, and quaternary signed-digit (QSD) to 4's complement. For optical implementation, a parallel logical array module using electron-trapping device is employed, which is suitable for realizing complex logic functions in the form of sum-of-product. The proposed algorithm and architecture are compatible with a general-purpose optoelectronic computing system.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard

2000-01-01

This column will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will start a series of notes concentrating on analysis techniques with this issues section discussing worst-case analysis requirements.

Topological Material-Based Spin Devices

NASA Astrophysics Data System (ADS)

Zhang, Minhao; Wang, Xuefeng

Three-dimensional topological insulators have insulating bulk and gapless helical surface states. One of the most fascinating properties of the metallic surface states is the spin-momentum helical locking. The giant current-driven torques on the magnetic layer have been discovered in TI/ferromagnet bilayers originating from the spin-momentum helical locking, enabling the efficient magnetization switching with a low current density. We demonstrated the current-direction dependent on-off state in TIs-based spin valve devices for memory and logic applications. Further, we demonstrated the Bi2Se3 system will go from a topologically nontrivial state to a topologically trivial state when Bi atoms are replaced by lighter In atoms. Here, topologically trivial metal (BixIny)2 Se3 with high mobility also facilitates the realization of its application in multifunctional spintronic devices.

A new approach to telemetry data processing. Ph.D. Thesis - Maryland Univ.

NASA Technical Reports Server (NTRS)

Broglio, C. J.

1973-01-01

An approach for a preprocessing system for telemetry data processing was developed. The philosophy of the approach is the development of a preprocessing system to interface with the main processor and relieve it of the burden of stripping information from a telemetry data stream. To accomplish this task, a telemetry preprocessing language was developed. Also, a hardware device for implementing the operation of this language was designed using a cellular logic module concept. In the development of the hardware device and the cellular logic module, a distributed form of control was implemented. This is accomplished by a technique of one-to-one intermodule communications and a set of privileged communication operations. By transferring this control state from module to module, the control function is dispersed through the system. A compiler for translating the preprocessing language statements into an operations table for the hardware device was also developed. Finally, to complete the system design and verify it, a simulator for the collular logic module was written using the APL/360 system.

Magnon detection using a ferroic collinear multilayer spin valve.

PubMed

Cramer, Joel; Fuhrmann, Felix; Ritzmann, Ulrike; Gall, Vanessa; Niizeki, Tomohiko; Ramos, Rafael; Qiu, Zhiyong; Hou, Dazhi; Kikkawa, Takashi; Sinova, Jairo; Nowak, Ulrich; Saitoh, Eiji; Kläui, Mathias

2018-03-14

Information transport and processing by pure magnonic spin currents in insulators is a promising alternative to conventional charge-current-driven spintronic devices. The absence of Joule heating and reduced spin wave damping in insulating ferromagnets have been suggested for implementing efficient logic devices. After the successful demonstration of a majority gate based on the superposition of spin waves, further components are required to perform complex logic operations. Here, we report on magnetization orientation-dependent spin current detection signals in collinear magnetic multilayers inspired by the functionality of a conventional spin valve. In Y 3 Fe 5 O 12 |CoO|Co, we find that the detection amplitude of spin currents emitted by ferromagnetic resonance spin pumping depends on the relative alignment of the Y 3 Fe 5 O 12 and Co magnetization. This yields a spin valve-like behavior with an amplitude change of 120% in our systems. We demonstrate the reliability of the effect and identify its origin by both temperature-dependent and power-dependent measurements.

Artificial neuron synapse transistor based on silicon nanomembrane on plastic substrate

NASA Astrophysics Data System (ADS)

Liu, Minjie; Huang, Gaoshan; Feng, Ping; Guo, Qinglei; Shao, Feng; Tian, Ziao; Li, Gongjin; Wan, Qing; Mei, Yongfeng

2017-06-01

Silicon nanomembrane (SiNM) transistors gated by chitosan membrane were fabricated on plastic substrate to mimic synapse behaviors. The device has both a bottom proton gate (BG) and multiple side gates (SG). Electrical transfer properties of BG show hysteresis curves different from those of typical SiO2 gate dielectric. Synaptic behaviors and functions by linear accumulation and release of protons have been mimicked on this device: excitatory post-synaptic current (EPSC) and paired pulse facilitation behavior of biological synapses were mimicked and the paired-pulse facilitation index could be effectively tuned by the spike interval applied on the BG. Synaptic behaviors and functions, including short-term memory and long-term memory, were also experimentally demonstrated in BG mode. Meanwhile, spiking logic operation and logic modulation were realized in SG mode. Project supported by the National Natural Science Foundation of China (No. 51322201), the Specialized Research Fund for the Doctoral Program of Higher Education (No. 20120071110025), and Science and Technology Commission of Shanghai Municipality (No. 14JC1400200).

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Reconfigurable nanoscale spin-wave directional coupler

PubMed Central

Wang, Qi; Pirro, Philipp; Verba, Roman; Slavin, Andrei; Hillebrands, Burkard; Chumak, Andrii V.

2018-01-01

Spin waves, and their quanta magnons, are prospective data carriers in future signal processing systems because Gilbert damping associated with the spin-wave propagation can be made substantially lower than the Joule heat losses in electronic devices. Although individual spin-wave signal processing devices have been successfully developed, the challenging contemporary problem is the formation of two-dimensional planar integrated spin-wave circuits. Using both micromagnetic modeling and analytical theory, we present an effective solution of this problem based on the dipolar interaction between two laterally adjacent nanoscale spin-wave waveguides. The developed device based on this principle can work as a multifunctional and dynamically reconfigurable signal directional coupler performing the functions of a waveguide crossing element, tunable power splitter, frequency separator, or multiplexer. The proposed design of a spin-wave directional coupler can be used both in digital logic circuits intended for spin-wave computing and in analog microwave signal processing devices. PMID:29376117

Reconfigurable nanoscale spin-wave directional coupler.

PubMed

Wang, Qi; Pirro, Philipp; Verba, Roman; Slavin, Andrei; Hillebrands, Burkard; Chumak, Andrii V

2018-01-01

Spin waves, and their quanta magnons, are prospective data carriers in future signal processing systems because Gilbert damping associated with the spin-wave propagation can be made substantially lower than the Joule heat losses in electronic devices. Although individual spin-wave signal processing devices have been successfully developed, the challenging contemporary problem is the formation of two-dimensional planar integrated spin-wave circuits. Using both micromagnetic modeling and analytical theory, we present an effective solution of this problem based on the dipolar interaction between two laterally adjacent nanoscale spin-wave waveguides. The developed device based on this principle can work as a multifunctional and dynamically reconfigurable signal directional coupler performing the functions of a waveguide crossing element, tunable power splitter, frequency separator, or multiplexer. The proposed design of a spin-wave directional coupler can be used both in digital logic circuits intended for spin-wave computing and in analog microwave signal processing devices.

The Temperature Fuzzy Control System of Barleythe Malt Drying Based on Microcontroller

NASA Astrophysics Data System (ADS)

Gao, Xiaoyang; Bi, Yang; Zhang, Lili; Chen, Jingjing; Yun, Jianmin

The control strategy of temperature and humidity in the beer barley malt drying chamber based on fuzzy logic control was implemented.Expounded in this paper was the selection of parameters for the structure of the regulatory device, as well as the essential design from control rules based on the existing experience. A temperature fuzzy controller was thus constructed using relevantfuzzy logic, and humidity control was achieved by relay, ensured the situation of the humidity to control the temperature. The temperature's fuzzy control and the humidity real-time control were all processed by single chip microcomputer with assembly program. The experimental results showed that the temperature control performance of this fuzzy regulatory system,especially in the ways of working stability and responding speed and so on,was better than normal used PID control. The cost of real-time system was inquite competitive position. It was demonstrated that the system have a promising prospect of extensive application.

Trapped-Ion Quantum Logic with Global Radiation Fields.

PubMed

Weidt, S; Randall, J; Webster, S C; Lake, K; Webb, A E; Cohen, I; Navickas, T; Lekitsch, B; Retzker, A; Hensinger, W K

2016-11-25

Trapped ions are a promising tool for building a large-scale quantum computer. However, the number of required radiation fields for the realization of quantum gates in any proposed ion-based architecture scales with the number of ions within the quantum computer, posing a major obstacle when imagining a device with millions of ions. Here, we present a fundamentally different approach for trapped-ion quantum computing where this detrimental scaling vanishes. The method is based on individually controlled voltages applied to each logic gate location to facilitate the actual gate operation analogous to a traditional transistor architecture within a classical computer processor. To demonstrate the key principle of this approach we implement a versatile quantum gate method based on long-wavelength radiation and use this method to generate a maximally entangled state of two quantum engineered clock qubits with fidelity 0.985(12). This quantum gate also constitutes a simple-to-implement tool for quantum metrology, sensing, and simulation.

Molecular processors: from qubits to fuzzy logic.

PubMed

Gentili, Pier Luigi

2011-03-14

Single molecules or their assemblies are information processing devices. Herein it is demonstrated how it is possible to process different types of logic through molecules. As long as decoherent effects are maintained far away from a pure quantum mechanical system, quantum logic can be processed. If the collapse of superimposed or entangled wavefunctions is unavoidable, molecules can still be used to process either crisp (binary or multi-valued) or fuzzy logic. The way for implementing fuzzy inference engines is declared and it is supported by the examples of molecular fuzzy logic systems devised so far. Fuzzy logic is drawing attention in the field of artificial intelligence, because it models human reasoning quite well. This ability may be due to some structural analogies between a fuzzy logic system and the human nervous system. Copyright © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC upgrades

NASA Astrophysics Data System (ADS)

Madorsky, A.

2017-07-01

To accommodate high-luminosity LHC operation at a 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide robust track reconstruction, the trigger system must now import all available trigger primitives generated by the Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources. To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The μ TCA architecture (adopted by CMS) was used for this design. The talk presents the details of the hardware and firmware design of the production system based on Xilinx Virtex-7 FPGA family. The next round of LHC and CMS upgrades starts in 2019, followed by a major High-Luminosity (HL) LHC upgrade starting in 2024. In the course of these upgrades, new Gas Electron Multiplier (GEM) detectors and more RPC chambers will be added to the Endcap Muon system. In order to keep up with all these changes, a new Advanced Processor unit is being designed. This device will be based on Xilinx UltraScale+ FPGAs. It will be able to accommodate up to 100 serial links with bit rates of up to 25 Gb/s, and provide up to 2.5 times more logic resources than the device used currently. The amount of PTLUT memory will be significantly increased to provide more flexibility for the Pt assignment algorithm. The talk presents preliminary details of the hardware design program.

Partial spin absorption induced magnetization switching and its voltage-assisted improvement in an asymmetrical all spin logic device at the mesoscopic scale

NASA Astrophysics Data System (ADS)

Zhang, Yue; Zhang, Zhizhong; Wang, Lezhi; Nan, Jiang; Zheng, Zhenyi; Li, Xiang; Wong, Kin; Wang, Yu; Klein, Jacques-Olivier; Khalili Amiri, Pedram; Zhang, Youguang; Wang, Kang L.; Zhao, Weisheng

2017-07-01

Beyond memory and storage, future logic applications put forward higher requirements for electronic devices. All spin logic devices (ASLDs) have drawn exceptional interest as they utilize pure spin current instead of charge current, which could promise ultra-low power consumption. However, relatively low efficiencies of spin injection, transport, and detection actually impede high-speed magnetization switching and challenge perspectives of ASLD. In this work, we study partial spin absorption induced magnetization switching in asymmetrical ASLD at the mesoscopic scale, in which the injector and detector have the nano-fabrication compatible device size (>100 nm) and their contact areas are different. The enlarged contact area of the detector is conducive to the spin current absorption, and the contact resistance difference between the injector and the detector can decrease the spin current backflow. Rigorous spin circuit modeling and micromagnetic simulations have been carried out to analyze the electrical and magnetic features. The results show that, at the fabrication-oriented technology scale, the ferromagnetic layer can hardly be switched by geometrically partial spin current absorption. The voltage-controlled magnetic anisotropy (VCMA) effect has been applied on the detector to accelerate the magnetization switching by modulating magnetic anisotropy of the ferromagnetic layer. With a relatively high VCMA coefficient measured experimentally, a voltage of 1.68 V can assist the whole magnetization switching within 2.8 ns. This analysis and improving approach will be of significance for future low-power, high-speed logic applications.

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

NASA Technical Reports Server (NTRS)

Gwaltney, David A.; King, Kenneth D.; Smith, Keary J.; Monenegro, Justino (Technical Monitor)

2002-01-01

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Control of Ambipolar Transport in SnO Thin-Film Transistors by Back-Channel Surface Passivation for High Performance Complementary-like Inverters.

PubMed

Luo, Hao; Liang, Lingyan; Cao, Hongtao; Dai, Mingzhi; Lu, Yicheng; Wang, Mei

2015-08-12

For ultrathin semiconductor channels, the surface and interface nature are vital and often dominate the bulk properties to govern the field-effect behaviors. High-performance thin-film transistors (TFTs) rely on the well-defined interface between the channel and gate dielectric, featuring negligible charge trap states and high-speed carrier transport with minimum carrier scattering characters. The passivation process on the back-channel surface of the bottom-gate TFTs is indispensable for suppressing the surface states and blocking the interactions between the semiconductor channel and the surrounding atmosphere. We report a dielectric layer for passivation of the back-channel surface of 20 nm thick tin monoxide (SnO) TFTs to achieve ambipolar operation and complementary metal oxide semiconductor (CMOS) like logic devices. This chemical passivation reduces the subgap states of the ultrathin channel, which offers an opportunity to facilitate the Fermi level shifting upward upon changing the polarity of the gate voltage. With the advent of n-type inversion along with the pristine p-type conduction, it is now possible to realize ambipolar operation using only one channel layer. The CMOS-like logic inverters based on ambipolar SnO TFTs were also demonstrated. Large inverter voltage gains (>100) in combination with wide noise margins are achieved due to high and balanced electron and hole mobilities. The passivation also improves the long-term stability of the devices. The ability to simultaneously achieve field-effect inversion, electrical stability, and logic function in those devices can open up possibilities for the conventional back-channel surface passivation in the CMOS-like electronics.

Spin torque oscillator neuroanalog of von Neumann's microwave computer.

PubMed

Hoppensteadt, Frank

2015-10-01

Frequency and phase of neural activity play important roles in the behaving brain. The emerging understanding of these roles has been informed by the design of analog devices that have been important to neuroscience, among them the neuroanalog computer developed by O. Schmitt and A. Hodgkin in the 1930s. Later J. von Neumann, in a search for high performance computing using microwaves, invented a logic machine based on crystal diodes that can perform logic functions including binary arithmetic. Described here is an embodiment of his machine using nano-magnetics. Electrical currents through point contacts on a ferromagnetic thin film can create oscillations in the magnetization of the film. Under natural conditions these properties of a ferromagnetic thin film may be described by a nonlinear Schrödinger equation for the film's magnetization. Radiating solutions of this system are referred to as spin waves, and communication within the film may be by spin waves or by directed graphs of electrical connections. It is shown here how to formulate a STO logic machine, and by computer simulation how this machine can perform several computations simultaneously using multiplexing of inputs, that this system can evaluate iterated logic functions, and that spin waves may communicate frequency, phase and binary information. Neural tissue and the Schmitt-Hodgkin, von Neumann and STO devices share a common bifurcation structure, although these systems operate on vastly different space and time scales; namely, all may exhibit Andronov-Hopf bifurcations. This suggests that neural circuits may be capable of the computational functionality as described by von Neumann. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

21 CFR 866.5380 - Free secretory component immuno-logical test system.

Code of Federal Regulations, 2013 CFR

2013-04-01

... body fluids. Measurement of free secretory component (protein molecules) aids in the diagnosis or... HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test...

21 CFR 866.5380 - Free secretory component immuno-logical test system.

Code of Federal Regulations, 2014 CFR

2014-04-01

... body fluids. Measurement of free secretory component (protein molecules) aids in the diagnosis or... HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test...

21 CFR 866.5380 - Free secretory component immuno-logical test system.

Code of Federal Regulations, 2012 CFR

2012-04-01

... body fluids. Measurement of free secretory component (protein molecules) aids in the diagnosis or... HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test...

21 CFR 866.5380 - Free secretory component immuno-logical test system.

Code of Federal Regulations, 2011 CFR

2011-04-01

... body fluids. Measurement of free secretory component (protein molecules) aids in the diagnosis or... HUMAN SERVICES (CONTINUED) MEDICAL DEVICES IMMUNOLOGY AND MICROBIOLOGY DEVICES Immunological Test...

LOGIC OF CONTROLLED THRESHOLD DEVICES.

DTIC Science & Technology

The synthesis of threshold logic circuits from several points of view is presented. The first approach is applicable to resistor-transistor networks...in which the outputs are tied to a common collector resistor. In general, fewer threshold logic gates than NOR gates connected to a common collector...network to realize a specified function such that the failure of any but the output gate can be compensated for by a change in the threshold level (and

Summary of Proton Test on the Quick Logic QL3025 at Indiana University

NASA Technical Reports Server (NTRS)

Katz, Richard

1998-01-01

This issue of the Programmable Logic Application Notes is a compilation of topics: (1) Proton irradiation tests were performed on the Quick Logic QL3025 at the Indian University Cyclotron facility. The devices, tests, and results are discussed; (2) The functional failure of EEPROM's in heavy ion environment is presented; (3) the Act 1 architecture is summarized; (4) Antifuse hardness and hardness testing is updated; the single even upset (SEU) response of hardwired flip-flops is also presented; (4) Total dose results of the ACT 2 and ACT 3 circuits is presented in a chart; (5) Recent sub-micron devices testing of total dose is presented in a chart along with brief discussion; and (6) a reference to the WWW site for more articles of interest.

Accessing memory

DOEpatents

Yoon, Doe Hyun; Muralimanohar, Naveen; Chang, Jichuan; Ranganthan, Parthasarathy

2017-09-26

A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.

Reliability analysis of magnetic logic interconnect wire subjected to magnet edge imperfections

NASA Astrophysics Data System (ADS)

Zhang, Bin; Yang, Xiaokuo; Liu, Jiahao; Li, Weiwei; Xu, Jie

2018-02-01

Nanomagnet logic (NML) devices have been proposed as one of the best candidates for the next generation of integrated circuits thanks to its substantial advantages of nonvolatility, radiation hardening and potentially low power. In this article, errors of nanomagnetic interconnect wire subjected to magnet edge imperfections have been evaluated for the purpose of reliable logic propagation. The missing corner defects of nanomagnet in the wire are modeled with a triangle, and the interconnect fabricated with various magnetic materials is thoroughly investigated by micromagnetic simulations under different corner defect amplitudes and device spacings. The results show that as the defect amplitude increases, the success rate of logic propagation in the interconnect decreases. More results show that from the interconnect wire fabricated with materials, iron demonstrates the best defect tolerance ability among three representative and frequently used NML materials, also logic transmission errors can be mitigated by adjusting spacing between nanomagnets. These findings can provide key technical guides for designing reliable interconnects. Project supported by the National Natural Science Foundation of China (No. 61302022) and the Scientific Research Foundation for Postdoctor of Air Force Engineering University (Nos. 2015BSKYQD03, 2016KYMZ06).

Voltage-Controlled Reconfigurable Spin-Wave Nanochannels and Logic Devices

NASA Astrophysics Data System (ADS)

Rana, Bivas; Otani, YoshiChika

2018-01-01

Propagating spin waves (SWs) promise to be a potential information carrier in future spintronics devices with lower power consumption. Here, we propose reconfigurable nanochannels (NCs) generated by voltage-controlled magnetic anisotropy (VCMA) in an ultrathin ferromagnetic waveguide for SW propagation. Numerical micromagnetic simulations are performed to demonstrate the confinement of magnetostatic forward volumelike spin waves in NCs by VCMA. We demonstrate that the NCs, with a width down to a few tens of a nanometer, can be configured either into a straight or curved structure on an extended SW waveguide. The key advantage is that either a single NC or any combination of a number of NCs can be easily configured by VCMA for simultaneous propagation of SWs either with the same or different wave vectors according to our needs. Furthermore, we demonstrate the logic operation of a voltage-controlled magnonic xnor and universal nand gate and propose a voltage-controlled reconfigurable SW switch for the development of a multiplexer and demultiplexer. We find that the NCs and logic devices can even be functioning in the absence of the external-bias magnetic field. These results are a step towards the development of all-voltage-controlled magnonic devices with an ultralow power consumption.

Electro-optical graphene plasmonic logic gates.

PubMed

Ooi, Kelvin J A; Chu, Hong Son; Bai, Ping; Ang, Lay Kee

2014-03-15

The versatile control of graphene's plasmonic modes via an external gate-voltage inspires us to design efficient electro-optical graphene plasmonic logic gates at the midinfrared wavelengths. We show that these devices are superior to the conventional optical logic gates because the former possess cut-off states and interferometric effects. Moreover, the designed six basic logic gates (i.e., NOR/AND, NAND/OR, XNOR/XOR) achieved not only ultracompact size lengths of less than λ/28 with respect to the operating wavelength of 10 μm, but also a minimum extinction ratio as high as 15 dB. These graphene plasmonic logic gates are potential building blocks for future nanoscale midinfrared photonic integrated circuits.

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

NASA Technical Reports Server (NTRS)

Pinto, N. J.; Perez, R.; Mueller, C. H.; Theofylaktos, N.; Miranda, F. A.

2006-01-01

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Exploring Carbon Nanotubes for Nanoscale Devices

NASA Technical Reports Server (NTRS)

Han, Jie; Dai; Anantram; Jaffe; Saini, Subhash (Technical Monitor)

1998-01-01

Carbon nanotubes (CNTs) are shown to promise great opportunities in nanoelectronic devices and nanoelectromechanical systems (NEMS) because of their inherent nanoscale sizes, intrinsic electric conductivities, and seamless hexagonal network architectures. I present our collaborative work with Stanford on exploring CNTs for nanodevices in this talk. The electrical property measurements suggest that metallic tubes are quantum wires. Furthermore, two and three terminal CNT junctions have been observed experimentally. We have proposed and studied CNT-based molecular switches and logic devices for future digital electronics. We also have studied CNTs based NEMS inclusing gears, cantilevers, and scanning probe microscopy tips. We investigate both chemistry and physics based aspects of the CNT NEMS. Our results suggest that CNT have ideal stiffness, vibrational frequencies, Q-factors, geometry-dependent electric conductivities, and the highest chemical and mechanical stabilities for the NEMS. The use of CNT SPM tips for nanolithography is presented for demonstration of the advantages of the CNT NEMS.

Spectromicroscopic insights for rational design of redox-based memristive devices

PubMed Central

Baeumer, Christoph; Schmitz, Christoph; Ramadan, Amr H. H.; Du, Hongchu; Skaja, Katharina; Feyer, Vitaliy; Müller, Philipp; Arndt, Benedikt; Jia, Chun-Lin; Mayer, Joachim; De Souza, Roger A.; Michael Schneider, Claus; Waser, Rainer; Dittmann, Regina

2015-01-01

The demand for highly scalable, low-power devices for data storage and logic operations is strongly stimulating research into resistive switching as a novel concept for future non-volatile memory devices. To meet technological requirements, it is imperative to have a set of material design rules based on fundamental material physics, but deriving such rules is proving challenging. Here, we elucidate both switching mechanism and failure mechanism in the valence-change model material SrTiO3, and on this basis we derive a design rule for failure-resistant devices. Spectromicroscopy reveals that the resistance change during device operation and failure is indeed caused by nanoscale oxygen migration resulting in localized valence changes between Ti4+ and Ti3+. While fast reoxidation typically results in retention failure in SrTiO3, local phase separation within the switching filament stabilizes the retention. Mimicking this phase separation by intentionally introducing retention-stabilization layers with slow oxygen transport improves retention times considerably. PMID:26477940

Flip-flop logic circuit based on fully solution-processed organic thin film transistor devices with reduced variations in electrical performance

NASA Astrophysics Data System (ADS)

Takeda, Yasunori; Yoshimura, Yudai; Adib, Faiz Adi Ezarudin Bin; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2015-04-01

Organic reset-set (RS) flip-flop logic circuits based on pseudo-CMOS inverters have been fabricated using full solution processing at a relatively low process temperatures of 150 °C or less. The work function for printed silver electrodes was increased from 4.7 to 5.4 eV through surface modification with a self-assembled monolayer (SAM) material. A bottom-gate, bottom-contact organic thin-film transistor (OTFT) device using a solution-processable small-molecular semiconductor material exhibited field-effect mobility of 0.40 cm2 V-1 s-1 in the saturation region and a threshold voltage (VTH) of -2.4 V in ambient air operation conditions. In order to reduce the variations in mobility and VTH, we designed a circuit with six transistors arranged in parallel, in order to average out their electrical characteristics. As a result, we have succeeded in reducing these variations without changing the absolute values of the mobility and VTH. The fabricated RS flip-flop circuits were functioned well and exhibited short delay times of 3.5 ms at a supply voltage of 20 V.

Room temperature operation of electro-optical bistability in the edge-emitting tunneling-collector transistor laser

NASA Astrophysics Data System (ADS)

Feng, M.; Holonyak, N.; Wang, C. Y.

2017-09-01

Optical bistable devices are fundamental to digital photonics as building blocks of switches, logic gates, and memories in future computer systems. Here, we demonstrate both optical and electrical bistability and capability for switching in a single transistor operated at room temperature. The electro-optical hysteresis is explained by the interaction of electron-hole (e-h) generation and recombination dynamics with the cavity photon modulation in different switching paths. The switch-UP and switch-DOWN threshold voltages are determined by the rate difference of photon generation at the base quantum-well and the photon absorption via intra-cavity photon-assisted tunneling controlled by the collector voltage. Thus, the transistor laser electro-optical bistable switching is programmable with base current and collector voltage, and the basis for high speed optical logic processors.

Bi-directional magnetic domain wall shift register

NASA Astrophysics Data System (ADS)

Read, D. E.; O'Brien, L.; Zeng, H. T.; Lewis, E. R.; Petit, D.; Cowburn, R. P.

2010-03-01

Data storage devices based on magnetic domain walls (DWs) propagating through ferromagnetic nanowires have attracted a great deal of attention in recent years [1,2]. Here we experimentally demonstrate a shift register based on an open-ended chain of ferromagnetic NOT gates. When used in combination with a globally applied magnetic field such devices can support bi-directional data flow [3]. We have demonstrated data writing, propagation, and readout in individually addressable NiFe nanowires 90 nm wide and 10 nm thick. Up to eight data bits are electrically input to the device, stored for extended periods without power supplied to the device, and then output using either a first in first out or a last in first out mode of operation. Compared to traditional electronic transistor-based circuits, the inherent bi-directionality afforded by these DW logic gates offers a range of devices that are reversible and not limited to only one mode of operation. [1] S. S. Parkin, US Patent 6,834,005 (2004) [2] D. A. Allwod, et al., Science 309 (5741), 1688 (2005) [3] L. O'Brien, et al. accepted for publication in APL (2009)

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory.

PubMed

Ng, Tse Nga; Schwartz, David E; Lavery, Leah L; Whiting, Gregory L; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic.

Techniques for detumbling a disabled space base

NASA Technical Reports Server (NTRS)

Kaplan, M. H.

1973-01-01

Techniques and conceptual devices for carrying out detumbling operations are examined, and progress in the development of these concepts is discussed. Devices which reduce tumble to simple spin through active linear motion of a small mass are described, together with a Module for Automatic Dock and Detumble (MADD) that could perform an orbital transfer from the shuttle in order to track and dock at a preselected point on the distressed craft. Once docked, MADD could apply torques by firing thrustors to detumble the passive vehicle. Optimum combinations of mass-motion and external devices for various situation should be developed. The need for completely formulating the automatic control logic of MADD is also emphasized.

Complete all-optical processing polarization-based binary logic gates and optical processors.

PubMed

Zaghloul, Y A; Zaghloul, A R M

2006-10-16

We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible logic, and threshold logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper.

The Art of Electronics

NASA Astrophysics Data System (ADS)

Horowitz, Paul; Hill, Winfield

2015-04-01

1. Foundations; 2. Bipolar transistors; 3. Field effect transistors; 4. Operational amplifiers; 5. Precision circuits; 6. Filters; 7. Oscillators and timers; 8. Low noise techniques and transimpedance; 9. Power regulation; 10. Digital electronics; 11. Programmable logic devices; 12. Logical interfacing; 13. Digital meets analog; 14. Computers, controllers, and data links; 15. Microcontrollers.

Programmable Logic Application Notes

NASA Technical Reports Server (NTRS)

Katz, Richard; Day, John H. (Technical Monitor)

2001-01-01

This report will be provided each quarter as a source for reliability, radiation results, NASA capabilities, and other information on programmable logic devices and related applications. This quarter will continue a series of notes concentrating on analysis techniques with this issue's section discussing the use of Root-Sum-Square calculations for digital delays.

Crystal growth of device quality GaAs in space

NASA Technical Reports Server (NTRS)

Gatos, Harry C.; Lagowski, Jacek

1989-01-01

The program on Crystal Growth of Device Quality GaAs in Space was initiated in 1977. The initial stage covering 1977 to 1984 was devoted strictly to ground-based research. By 1985 the program had evolved into its next logical stage aimed at space growth experiments; however, since the Challenger disaster, the program has been maintained as a ground-based program awaiting activation of experimentation in space. The overall prgram has produced some 80 original scientific publications on GaAs crystal growth, crystal characterization, and new approaches to space processing. Publication completed in the last three years are listed. Their key results are outlined and discussed in the twelve publications included as part of the report.

Ambipolar transport based on CVD-synthesized ReSe2

NASA Astrophysics Data System (ADS)

Kang, Byunggil; Kim, Youngchan; Cho, Jeong Ho; Lee, Changgu

2017-06-01

Control of the carrier type in two dimensional (2D) materials is a serious issue for the realization of logic devices. The carrier type control of 2D semiconducting materials such as MoTe2, WSe2 and black phosphorus have been studied for this purpose. However, the systematic study on the polarity control of transistors based on ReSe2, a new member of 2D materials, has remained unexplored despite the intriguing anisotropic optical and electrical properties deriving from the exotic crystal structure. Here, we report the electrical characterization of field effect transistors (FETs) of single crystalline ReSe2 grown by a chemical vapor deposition. In contrast to a previous report of unipolar p-type exfoliated crystals, synthesized ReSe2 FETs on SiO2 with Au contact exhibit highly symmetric ambipolar behaviors with the current on/off ratios of ~104 for both of hole and electron injection. The carrier type could be controlled via the metal contact. With Al contacts, ReSe2 FETs display perfect transition to pure n-type unipolar behavior. It is found that carrier type of ReSe2 via thickness variation was hardly modulated because the ReSe2 bandgap has little dependence on its thickness. We successfully achieved the fabrication of a logic inverter by using only ambipolar ReSe2 FETs on SiO2/Si without electrostatic doping or chemical treatments. These results demonstrate that ReSe2 is a promising candidate for future low power logic devices and functional nano electronic applications.

Family of new operations equivalency of neuro-fuzzy logic: optoelectronic realization and applications

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Yatskovsky, Victor I.; Ogorodnik, K. V.; Lischenko, Sergey

2002-07-01

The perspective of neural networks equivalental models (EM) base on vector-matrix procedure with basic operations of continuous and neuro-fuzzy logic (equivalence, absolute difference) are shown. Capacity on base EMs exceeded the amount of neurons in 2.5 times. This is larger than others neural networks paradigms. Amount neurons of this neural networks on base EMs may be 10 - 20 thousands. The base operations in EMs are normalized equivalency operations. The family of new operations equivalency and non-equivalency of neuro-fuzzy logic's, which we have elaborated on the based of such generalized operations of fuzzy-logic's as fuzzy negation, t-norm and s-norm are shown. Generalized rules of construction of new functions (operations) equivalency which uses relations of t-norm and s-norm to fuzzy negation are proposed. Among these elements the following should be underlined: (1) the element which fulfills the operation of limited difference; (2) the element which algebraic product (intensifier with controlled coefficient of transmission or multiplier of analog signals); (3) the element which fulfills a sample summarizing (uniting) of signals (including the one during normalizing). Synthesized structures which realize on the basic of these elements the whole spectrum of required operations: t-norm, s-norm and new operations equivalency are shown. These realization on the basic of new multifunctional optoelectronical BISPIN- devices (MOEBD) represent the circuit with constant and pulse optical input signals. They are modeling the operation of limited difference. These circuits realize frequency- dynamic neuron models and neural networks. Experimental results of these MOEBD and equivalency circuits, which fulfill the limited difference operation are discussed. For effective realization of neural networks on the basic of EMs as it is shown in report, picture elements are required as main nodes to implement element operations equivalence ('non-equivalence') of neuro-fuzzy logic's.

Design and simulation of programmable relational optoelectronic time-pulse coded processors as base elements for sorting neural networks

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

2010-05-01

In the paper we show that the biologically motivated conception of time-pulse encoding usage gives a set of advantages (single methodological basis, universality, tuning simplicity, learning and programming et al) at creation and design of sensor systems with parallel input-output and processing for 2D structures hybrid and next generations neuro-fuzzy neurocomputers. We show design principles of programmable relational optoelectronic time-pulse encoded processors on the base of continuous logic, order logic and temporal waves processes. We consider a structure that execute analog signal extraction, analog and time-pulse coded variables sorting. We offer optoelectronic realization of such base relational order logic element, that consists of time-pulse coded photoconverters (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutation blocks. We make technical parameters estimations of devices and processors on such base elements by simulation and experimental research: optical input signals power 0.2 - 20 uW, processing time 1 - 10 us, supply voltage 1 - 3 V, consumption power 10 - 100 uW, extended functional possibilities, learning possibilities. We discuss some aspects of possible rules and principles of learning and programmable tuning on required function, relational operation and realization of hardware blocks for modifications of such processors. We show that it is possible to create sorting machines, neural networks and hybrid data-processing systems with untraditional numerical systems and pictures operands on the basis of such quasiuniversal hardware simple blocks with flexible programmable tuning.

A Proposal for IoT Dynamic Routes Selection Based on Contextual Information

PubMed Central

Filho, Raimir Holanda; Rabelo, Ricardo de A. L.; Sousa, Natanael de C.; Filho, José C. C. L. S.

2018-01-01

The Internet of Things (IoT) is based on interconnection of intelligent and addressable devices, allowing their autonomy and proactive behavior with Internet connectivity. Data dissemination in IoT usually depends on the application and requires context-aware routing protocols that must include auto-configuration features (which adapt the behavior of the network at runtime, based on context information). This paper proposes an approach for IoT route selection using fuzzy logic in order to attain the requirements of specific applications. In this case, fuzzy logic is used to translate in math terms the imprecise information expressed by a set of linguistic rules. For this purpose, four Objective Functions (OFs) are proposed for the Routing Protocol for Low Power and Loss Networks (RPL); such OFs are dynamically selected based on context information. The aforementioned OFs are generated from the fusion of the following metrics: Expected Transmission Count (ETX), Number of Hops (NH) and Energy Consumed (EC). The experiments performed through simulation, associated with the statistical data analysis, conclude that this proposal provides high reliability by successfully delivering nearly 100% of data packets, low delay for data delivery and increase in QoS. In addition, an 30% improvement is attained in the network life time when using one of proposed objective function, keeping the devices alive for longer duration. PMID:29373499

Fluidic-thermochromic display device

NASA Technical Reports Server (NTRS)

Grafstein, D.; Hilborn, E. H.

1968-01-01

Fluidic decoder and display device has low-power requirements for temperature control of thermochromic materials. An electro-to-fluid converter translates incoming electrical signals into pneumatics signal of sufficient power to operate the fluidic logic elements.

Multi-factor authentication

DOEpatents

Hamlet, Jason R; Pierson, Lyndon G

2014-10-21

Detection and deterrence of spoofing of user authentication may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a user of the hardware device. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a PUF value. Combining logic is coupled to receive the PUF value, combines the PUF value with one or more other authentication factors to generate a multi-factor authentication value. A key generator is coupled to generate a private key and a public key based on the multi-factor authentication value while a decryptor is coupled to receive an authentication challenge posed to the hardware device and encrypted with the public key and coupled to output a response to the authentication challenge decrypted with the private key.

Novel optoelectronic devices; Proceedings of the Meeting, The Hague, Netherlands, Mar. 31-Apr. 2, 1987

NASA Technical Reports Server (NTRS)

Adams, Michael J. (Editor)

1987-01-01

The present conference on novel optoelectronics discusses topics in the state-of-the-art in this field in the Netherlands, quantum wells, integrated optics, nonlinear optical devices and fiber-optic-based devices, ultrafast optics, and nonlinear optics and optical bistability. Attention is given to the production of fiber-optics for telecommunications by means of PCVD, lifetime broadening in quantum wells, nonlinear multiple quantum well waveguide devices, tunable single-wavelength lasers, an Si integrated waveguiding polarimeter, and an electrooptic light modulator using long-range surface plasmons. Also discussed are backward-wave couplers and reflectors, a wavelength-selective all-fiber switching matrix, the impact of ultrafast optics in high-speed electronics, the physics of low energy optical switching, and all-optical logical elements for optical processing.

Studies in optical parallel processing. [All optical and electro-optic approaches

NASA Technical Reports Server (NTRS)

Lee, S. H.

1978-01-01

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Experimental realization of a CMOS-compatible optical directed priority encoder using cascaded micro-ring resonators

NASA Astrophysics Data System (ADS)

Xiao, Huifu; Li, Dezhao; Liu, Zilong; Han, Xu; Chen, Wenping; Zhao, Ting; Tian, Yonghui; Yang, Jianhong

2018-03-01

In this paper, we propose and experimentally demonstrate an integrated optical device that can implement the logical function of priority encoding from a 4-bit electrical signal to a 2-bit optical signal. For the proof of concept, the thermo-optic modulation scheme is adopted to tune each micro-ring resonator (MRR). A monochromatic light with the working wavelength is coupled into the input port of the device through a lensed fiber, and the four input electrical logic signals regarded as pending encode signals are applied to the micro-heaters above four MRRs to control the working states of the optical switches. The encoding results are directed to the output ports in the form of light. At last, the logical function of priority encoding with an operation speed of 10 Kbps is demonstrated successfully.

PLATO--AN AUTOMATED TEACHING DEVICE.

ERIC Educational Resources Information Center

BITZER, D.; AND OTHERS

PLATO (PROGRAMED LOGIC FOR AUTOMATIC TEACHING OPERATION) IS A DEVICE FOR TEACHING A NUMBER OF STUDENTS INDIVIDUALLY BY MEANS OF A SINGLE, CENTRAL PURPOSE, DIGITAL COMPUTER. THE GENERAL ORGANIZATION OF EQUIPMENT CONSISTS OF A KEYSET FOR STUDENT RESPONSES, THE COMPUTER, STORAGE DEVICE (ELECTRIC BLACKBOARD), SLIDE SELECTOR (ELECTRICAL BOOK), AND TV…

High-performance hybrid complementary logic inverter through monolithic integration of a MEMS switch and an oxide TFT.

PubMed

Song, Yong-Ha; Ahn, Sang-Joon Kenny; Kim, Min-Wu; Lee, Jeong-Oen; Hwang, Chi-Sun; Pi, Jae-Eun; Ko, Seung-Deok; Choi, Kwang-Wook; Park, Sang-Hee Ko; Yoon, Jun-Bo

2015-03-25

A hybrid complementary logic inverter consisting of a microelectromechanical system switch as a promising alternative for the p-type oxide thin film transistor (TFT) and an n-type oxide TFT is presented for ultralow power integrated circuits. These heterogeneous microdevices are monolithically integrated. The resulting logic device shows a distinctive voltage transfer characteristic curve, very low static leakage, zero-short circuit current, and exceedingly high voltage gain. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Complementary spin transistor using a quantum well channel.

PubMed

Park, Youn Ho; Choi, Jun Woo; Kim, Hyung-Jun; Chang, Joonyeon; Han, Suk Hee; Choi, Heon-Jin; Koo, Hyun Cheol

2017-04-20

In order to utilize the spin field effect transistor in logic applications, the development of two types of complementary transistors, which play roles of the n- and p-type conventional charge transistors, is an essential prerequisite. In this research, we demonstrate complementary spin transistors consisting of two types of devices, namely parallel and antiparallel spin transistors using InAs based quantum well channels and exchange-biased ferromagnetic electrodes. In these spin transistors, the magnetization directions of the source and drain electrodes are parallel or antiparallel, respectively, depending on the exchange bias field direction. Using this scheme, we also realize a complementary logic operation purely with spin transistors controlled by the gate voltage, without any additional n- or p-channel transistor.

A comparative TCAD assessment of III-V channel materials for future high speed and low power logic applications

NASA Astrophysics Data System (ADS)

Gomes, U. P.; Takhar, K.; Ranjan, K.; Rathi, S.; Biswas, D.

2015-02-01

In this work, by means physics based drift-diffusion simulations, three different narrow band gap semiconductors; InAs, InSb and In0.53Ga0.47As, and their associated heterostructures have been studied for future high speed and low power logic applications. It is observed that In0.53Ga0.47As has higher immunity towards short channel effects with low DIBL and sub-threshold slope than InSb and InAs. Also it is observed that for the same device geometry InSb has the highest drive current and lower intrinsic delay but its ION/IOFF figure of merit is deteriorated due to excess leakage current.

Redundant single event upset supression system

DOEpatents

Hoff, James R.

2006-04-04

CMOS transistors are configured to operate as either a redundant, SEU-tolerant, positive-logic, cross-coupled Nor Gate SR-flip flop or a redundant, SEU-tolerant, negative-logic, cross-coupled Nand Gate SR-flip flop. The register can operate as a memory, and further as a memory that can overcome the effects of radiation. As an SR-flip flop, the invention can be altered into any known type of latch or flip-flop by the application of external logic, thereby extending radiation tolerance to devices previously incapable of radiation tolerance. Numerous registers can be logically connected and replicated thereby being electronically configured to operate as a redundant circuit.

Sign-And-Magnitude Up/Down Counter

NASA Technical Reports Server (NTRS)

Cole, Steven W.

1991-01-01

Magnitude-and-sign counter includes conventional up/down counter for magnitude part and special additional circuitry for sign part. Negative numbers indicated more directly. Counter implemented by programming erasable programmable logic device (EPLD) or programmable logic array (PLA). Used in place of conventional up/down counter to provide sign and magnitude values directly to other circuits.

Multi-variants synthesis of Petri nets for FPGA devices

NASA Astrophysics Data System (ADS)

Bukowiec, Arkadiusz; Doligalski, Michał

2015-09-01

There is presented new method of synthesis of application specific logic controllers for FPGA devices. The specification of control algorithm is made with use of control interpreted Petri net (PT type). It allows specifying parallel processes in easy way. The Petri net is decomposed into state-machine type subnets. In this case, each subnet represents one parallel process. For this purpose there are applied algorithms of coloring of Petri nets. There are presented two approaches of such decomposition: with doublers of macroplaces or with one global wait place. Next, subnets are implemented into two-level logic circuit of the controller. The levels of logic circuit are obtained as a result of its architectural decomposition. The first level combinational circuit is responsible for generation of next places and second level decoder is responsible for generation output symbols. There are worked out two variants of such circuits: with one shared operational memory or with many flexible distributed memories as a decoder. Variants of Petri net decomposition and structures of logic circuits can be combined together without any restrictions. It leads to existence of four variants of multi-variants synthesis.

Spin pumping driven auto-oscillator for phase-encoded logic—device design and material requirements

NASA Astrophysics Data System (ADS)

Rakheja, S.; Kani, N.

2017-05-01

In this work, we propose a spin nano-oscillator (SNO) device where information is encoded in the phase (time-shift) of the output oscillations. The spin current required to set up the oscillations in the device is generated through spin pumping from an input nanomagnet that is precessing at RF frequencies. We discuss the operation of the SNO device, in which either the in-plane (IP) or out-of-plane (OOP) magnetization oscillations are utilized toward implementing ultra-low-power circuits. Using physical models of the nanomagnet dynamics and the spin transport through non-magnetic channels, we quantify the reliability of the SNO device using a "scaling ratio". Material requirements for the nanomagnet and the channel to ensure correct logic functionality are identified using the scaling ratio metric. SNO devices consume (2-5)× lower energy compared to CMOS devices and other spin-based devices with similar device sizes and material parameters. The analytical models presented in this work can be used to optimize the performance and scaling of SNO devices in comparison to CMOS devices at ultra-scaled technology nodes.

Scalable printed electronics: an organic decoder addressing ferroelectric non-volatile memory

PubMed Central

Ng, Tse Nga; Schwartz, David E.; Lavery, Leah L.; Whiting, Gregory L.; Russo, Beverly; Krusor, Brent; Veres, Janos; Bröms, Per; Herlogsson, Lars; Alam, Naveed; Hagel, Olle; Nilsson, Jakob; Karlsson, Christer

2012-01-01

Scalable circuits of organic logic and memory are realized using all-additive printing processes. A 3-bit organic complementary decoder is fabricated and used to read and write non-volatile, rewritable ferroelectric memory. The decoder-memory array is patterned by inkjet and gravure printing on flexible plastics. Simulation models for the organic transistors are developed, enabling circuit designs tolerant of the variations in printed devices. We explain the key design rules in fabrication of complex printed circuits and elucidate the performance requirements of materials and devices for reliable organic digital logic. PMID:22900143

High Temperature Near-Field NanoThermoMechanical Rectification

PubMed Central

Elzouka, Mahmoud; Ndao, Sidy

2017-01-01

Limited performance and reliability of electronic devices at extreme temperatures, intensive electromagnetic fields, and radiation found in space exploration missions (i.e., Venus & Jupiter planetary exploration, and heliophysics missions) and earth-based applications requires the development of alternative computing technologies. In the pursuit of alternative technologies, research efforts have looked into developing thermal memory and logic devices that use heat instead of electricity to perform computations. However, most of the proposed technologies operate at room or cryogenic temperatures, due to their dependence on material’s temperature-dependent properties. Here in this research, we show experimentally—for the first time—the use of near-field thermal radiation (NFTR) to achieve thermal rectification at high temperatures, which can be used to build high-temperature thermal diodes for performing logic operations in harsh environments. We achieved rectification through the coupling between NFTR and the size of a micro/nano gap separating two terminals, engineered to be a function of heat flow direction. We fabricated and tested a proof-of-concept NanoThermoMechanical device that has shown a maximum rectification of 10.9% at terminals’ temperatures of 375 and 530 K. Experimentally, we operated the microdevice in temperatures as high as about 600 K, demonstrating this technology’s suitability to operate at high temperatures. PMID:28322324

High Temperature Near-Field NanoThermoMechanical Rectification

NASA Astrophysics Data System (ADS)

Elzouka, Mahmoud; Ndao, Sidy

2017-03-01

Limited performance and reliability of electronic devices at extreme temperatures, intensive electromagnetic fields, and radiation found in space exploration missions (i.e., Venus & Jupiter planetary exploration, and heliophysics missions) and earth-based applications requires the development of alternative computing technologies. In the pursuit of alternative technologies, research efforts have looked into developing thermal memory and logic devices that use heat instead of electricity to perform computations. However, most of the proposed technologies operate at room or cryogenic temperatures, due to their dependence on material’s temperature-dependent properties. Here in this research, we show experimentally—for the first time—the use of near-field thermal radiation (NFTR) to achieve thermal rectification at high temperatures, which can be used to build high-temperature thermal diodes for performing logic operations in harsh environments. We achieved rectification through the coupling between NFTR and the size of a micro/nano gap separating two terminals, engineered to be a function of heat flow direction. We fabricated and tested a proof-of-concept NanoThermoMechanical device that has shown a maximum rectification of 10.9% at terminals’ temperatures of 375 and 530 K. Experimentally, we operated the microdevice in temperatures as high as about 600 K, demonstrating this technology’s suitability to operate at high temperatures.

Advanced development of double-injection, deep-impurity semiconductor switches

NASA Technical Reports Server (NTRS)

Hanes, M. H.

1987-01-01

Deep-impurity, double-injection devices, commonly refered to as (DI) squared devices, represent a class of semiconductor switches possessing a very high degree of tolerance to electron and neutron irradiation and to elevated temperature operation. These properties have caused them to be considered as attractive candidates for space power applications. The design, fabrication, and testing of several varieties of (DI) squared devices intended for power switching are described. All of these designs were based upon gold-doped silicon material. Test results, along with results of computer simulations of device operation, other calculations based upon the assumed mode of operation of (DI) squared devices, and empirical information regarding power semiconductor device operation and limitations, have led to the conculsion that these devices are not well suited to high-power applications. When operated in power circuitry configurations, they exhibit high-power losses in both the off-state and on-state modes. These losses are caused by phenomena inherent to the physics and material of the devices and cannot be much reduced by device design optimizations. The (DI) squared technology may, however, find application in low-power functions such as sensing, logic, and memory, when tolerance to radiation and temperature are desirable (especially is device performance is improved by incorporation of deep-level impurities other than gold.

Optically programmable encoder based on light propagation in two-dimensional regular nanoplates.

PubMed

Li, Ya; Zhao, Fangyin; Guo, Shuai; Zhang, Yongyou; Niu, Chunhui; Zeng, Ruosheng; Zou, Bingsuo; Zhang, Wensheng; Ding, Kang; Bukhtiar, Arfan; Liu, Ruibin

2017-04-07

We design an efficient optically controlled microdevice based on CdSe nanoplates. Two-dimensional CdSe nanoplates exhibit lighting patterns around the edges and can be realized as a new type of optically controlled programmable encoder. The light source is used to excite the nanoplates and control the logical position under vertical pumping mode by the objective lens. At each excitation point in the nanoplates, the preferred light-propagation routes are along the normal direction and perpendicular to the edges, which then emit out from the edges to form a localized lighting section. The intensity distribution around the edges of different nanoplates demonstrates that the lighting part with a small scale is much stronger, defined as '1', than the dark section, defined as '0', along the edge. These '0' and '1' are the basic logic elements needed to compose logically functional devices. The observed propagation rules are consistent with theoretical simulations, meaning that the guided-light route in two-dimensional semiconductor nanoplates is regular and predictable. The same situation was also observed in regular CdS nanoplates. Basic theoretical analysis and experiments prove that the guided light and exit position follow rules mainly originating from the shape rather than material itself.

Target-responsive DNA-capped nanocontainer used for fabricating universal detector and performing logic operations

PubMed Central

Wu, Li; Ren, Jinsong; Qu, Xiaogang

2014-01-01

Nucleic acids have become a powerful tool in nanotechnology because of their controllable diverse conformational transitions and adaptable higher-order nanostructure. Using single-stranded DNA probes as the pore-caps for various target recognition, here we present an ultrasensitive universal electrochemical detection system based on graphene and mesoporous silica, and achieve sensitivity with all of the major classes of analytes and simultaneously realize DNA logic gate operations. The concept is based on the locking of the pores and preventing the signal-reporter molecules from escape by target-induced the conformational change of the tailored DNA caps. The coupling of ‘waking up’ gatekeeper with highly specific biochemical recognition is an innovative strategy for the detection of various targets, able to compete with classical methods which need expensive instrumentation and sophisticated experimental operations. The present study has introduced a new electrochemical signal amplification concept and also adds a new dimension to the function of graphene-mesoporous materials hybrids as multifunctional nanoscale logic devices. More importantly, the development of this approach would spur further advances in important areas, such as point-of-care diagnostics or detection of specific biological contaminations, and hold promise for use in field analysis. PMID:25249622

Observation of conducting filament growth in nanoscale resistive memories

NASA Astrophysics Data System (ADS)

Yang, Yuchao; Gao, Peng; Gaba, Siddharth; Chang, Ting; Pan, Xiaoqing; Lu, Wei

2012-03-01

Nanoscale resistive switching devices, sometimes termed memristors, have recently generated significant interest for memory, logic and neuromorphic applications. Resistive switching effects in dielectric-based devices are normally assumed to be caused by conducting filament formation across the electrodes, but the nature of the filaments and their growth dynamics remain controversial. Here we report direct transmission electron microscopy imaging, and structural and compositional analysis of the nanoscale conducting filaments. Through systematic ex-situ and in-situ transmission electron microscopy studies on devices under different programming conditions, we found that the filament growth can be dominated by cation transport in the dielectric film. Unexpectedly, two different growth modes were observed for the first time in materials with different microstructures. Regardless of the growth direction, the narrowest region of the filament was found to be near the dielectric/inert-electrode interface in these devices, suggesting that this region deserves particular attention for continued device optimization.

Fundamentals of Digital Engineering: Designing for Reliability

NASA Technical Reports Server (NTRS)

Katz, R.; Day, John H. (Technical Monitor)

2001-01-01

The concept of designing for reliability will be introduced along with a brief overview of reliability, redundancy and traditional methods of fault tolerance is presented, as applied to current logic devices. The fundamentals of advanced circuit design and analysis techniques will be the primary focus. The introduction will cover the definitions of key device parameters and how analysis is used to prove circuit correctness. Basic design techniques such as synchronous vs asynchronous design, metastable state resolution time/arbiter design, and finite state machine structure/implementation will be reviewed. Advanced topics will be explored such as skew-tolerant circuit design, the use of triple-modular redundancy and circuit hazards, device transients and preventative circuit design, lock-up states in finite state machines generated by logic synthesizers, device transient characteristics, radiation mitigation techniques. worst-case analysis, the use of timing analyzer and simulators, and others. Case studies and lessons learned from spaceflight designs will be given as examples

Boron nitride as two dimensional dielectric: Reliability and dielectric breakdown

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ji, Yanfeng; Pan, Chengbin; Hui, Fei

2016-01-04

Boron Nitride (BN) is a two dimensional insulator with excellent chemical, thermal, mechanical, and optical properties, which make it especially attractive for logic device applications. Nevertheless, its insulating properties and reliability as a dielectric material have never been analyzed in-depth. Here, we present the first thorough characterization of BN as dielectric film using nanoscale and device level experiments complementing with theoretical study. Our results reveal that BN is extremely stable against voltage stress, and it does not show the reliability problems related to conventional dielectrics like HfO{sub 2}, such as charge trapping and detrapping, stress induced leakage current, and untimelymore » dielectric breakdown. Moreover, we observe a unique layer-by-layer dielectric breakdown, both at the nanoscale and device level. These findings may be of interest for many materials scientists and could open a new pathway towards two dimensional logic device applications.« less

Terahertz electrical writing speed in an antiferromagnetic memory

PubMed Central

Kašpar, Zdeněk; Campion, Richard P.; Baumgartner, Manuel; Sinova, Jairo; Kužel, Petr; Müller, Melanie; Kampfrath, Tobias

2018-01-01

The speed of writing of state-of-the-art ferromagnetic memories is physically limited by an intrinsic gigahertz threshold. Recently, realization of memory devices based on antiferromagnets, in which spin directions periodically alternate from one atomic lattice site to the next has moved research in an alternative direction. We experimentally demonstrate at room temperature that the speed of reversible electrical writing in a memory device can be scaled up to terahertz using an antiferromagnet. A current-induced spin-torque mechanism is responsible for the switching in our memory devices throughout the 12-order-of-magnitude range of writing speeds from hertz to terahertz. Our work opens the path toward the development of memory-logic technology reaching the elusive terahertz band. PMID:29740601

Designable DNA-binding domains enable construction of logic circuits in mammalian cells.

PubMed

Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman

2014-03-01

Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.

Design and simulation of a 800 Mbit/s data link for magnetic resonance imaging wearables.

PubMed

Vogt, Christian; Buthe, Lars; Petti, Luisa; Cantarella, Giuseppe; Munzenrieder, Niko; Daus, Alwin; Troster, Gerhard

2015-08-01

This paper presents the optimization of electronic circuitry for operation in the harsh electro magnetic (EM) environment during a magnetic resonance imaging (MRI) scan. As demonstrator, a device small enough to be worn during the scan is optimized. Based on finite element method (FEM) simulations, the induced current densities due to magnetic field changes of 200 T s(-1) were reduced from 1 × 10(10) A m(-2) by one order of magnitude, predicting error-free operation of the 1.8V logic employed. The simulations were validated using a bit error rate test, which showed no bit errors during a MRI scan sequence. Therefore, neither the logic, nor the utilized 800 Mbit s(-1) low voltage differential swing (LVDS) data link of the optimized wearable device were significantly influenced by the EM interference. Next, the influence of ferro-magnetic components on the static magnetic field and consequently the image quality was simulated showing a MRI image loss with approximately 2 cm radius around a commercial integrated circuit of 1×1 cm(2). This was successively validated by a conventional MRI scan.

Mechanically Controlled Electron Transfer in a Single-Polypeptide Transistor

NASA Astrophysics Data System (ADS)

Sheu, Sheh-Yi; Yang, Dah-Yen

2017-01-01

Proteins are of interest in nano-bio electronic devices due to their versatile structures, exquisite functionality and specificity. However, quantum transport measurements produce conflicting results due to technical limitations whereby it is difficult to precisely determine molecular orientation, the nature of the moieties, the presence of the surroundings and the temperature; in such circumstances a better understanding of the protein electron transfer (ET) pathway and the mechanism remains a considerable challenge. Here, we report an approach to mechanically drive polypeptide flip-flop motion to achieve a logic gate with ON and OFF states during protein ET. We have calculated the transmission spectra of the peptide-based molecular junctions and observed the hallmarks of electrical current and conductance. The results indicate that peptide ET follows an NC asymmetric process and depends on the amino acid chirality and α-helical handedness. Electron transmission decreases as the number of water molecules increases, and the ET efficiency and its pathway depend on the type of water-bridged H-bonds. Our results provide a rational mechanism for peptide ET and new perspectives on polypeptides as potential candidates in logic nano devices.

46 CFR 62.25-25 - Programmable systems and devices.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 46 Shipping 2 2014-10-01 2014-10-01 false Programmable systems and devices. 62.25-25 Section 62.25... AUTOMATION General Requirements for All Automated Vital Systems § 62.25-25 Programmable systems and devices. (a) Programmable control or alarm system logic must not be altered after Design Verification testing...

Bistable metamaterial for switching and cascading elastic vibrations

PubMed Central

Foehr, André; Daraio, Chiara

2017-01-01

The realization of acoustic devices analogous to electronic systems, like diodes, transistors, and logic elements, suggests the potential use of elastic vibrations (i.e., phonons) in information processing, for example, in advanced computational systems, smart actuators, and programmable materials. Previous experimental realizations of acoustic diodes and mechanical switches have used nonlinearities to break transmission symmetry. However, existing solutions require operation at different frequencies or involve signal conversion in the electronic or optical domains. Here, we show an experimental realization of a phononic transistor-like device using geometric nonlinearities to switch and amplify elastic vibrations, via magnetic coupling, operating at a single frequency. By cascading this device in a tunable mechanical circuit board, we realize the complete set of mechanical logic elements and interconnect selected ones to execute simple calculations. PMID:28416663

Fault-Tolerant Sequencer Using FPGA-Based Logic Designs for Space Applications

DTIC Science & Technology

2013-12-01

Prototype Board SBU single bit upset SDK software development kit SDRAM synchronous dynamic random-access memory SEB single-event burnout ...current VHDL VHSIC hardware description language VHSIC very-high-speed integrated circuits VLSI very-large- scale integration VQFP very...transient pulse, called a single-event transient (SET), or even cause permanent damage to the device in the form of a burnout or gate rupture. The SEE

Slime mould foraging behaviour as optically coupled logical operations

NASA Astrophysics Data System (ADS)

Mayne, R.; Adamatzky, A.

2015-04-01

Physarum polycephalum is a macroscopic plasmodial slime mould whose apparently 'intelligent' behaviour patterns may be interpreted as computation. We employ plasmodial phototactic responses to construct laboratory prototypes of NOT and NAND logical gates with electrical inputs/outputs and optical coupling in which the slime mould plays dual roles of computing device and electrical conductor. Slime mould logical gates are fault tolerant and resettable. The results presented here demonstrate the malleability and resilience of biological systems and highlight how the innate behaviour patterns of living substrates may be used to implement useful computation.

Water-based and biocompatible 2D crystal inks for all-inkjet-printed heterostructures

NASA Astrophysics Data System (ADS)

McManus, Daryl; Vranic, Sandra; Withers, Freddie; Sanchez-Romaguera, Veronica; Macucci, Massimo; Yang, Huafeng; Sorrentino, Roberto; Parvez, Khaled; Son, Seok-Kyun; Iannaccone, Giuseppe; Kostarelos, Kostas; Fiori, Gianluca; Casiraghi, Cinzia

2017-05-01

Exploiting the properties of two-dimensional crystals requires a mass production method able to produce heterostructures of arbitrary complexity on any substrate. Solution processing of graphene allows simple and low-cost techniques such as inkjet printing to be used for device fabrication. However, the available printable formulations are still far from ideal as they are either based on toxic solvents, have low concentration, or require time-consuming and expensive processing. In addition, none is suitable for thin-film heterostructure fabrication due to the re-mixing of different two-dimensional crystals leading to uncontrolled interfaces and poor device performance. Here, we show a general approach to achieve inkjet-printable, water-based, two-dimensional crystal formulations, which also provide optimal film formation for multi-stack fabrication. We show examples of all-inkjet-printed heterostructures, such as large-area arrays of photosensors on plastic and paper and programmable logic memory devices. Finally, in vitro dose-escalation cytotoxicity assays confirm the biocompatibility of the inks, extending their possible use to biomedical applications.

Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates

PubMed Central

Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda

2012-01-01

One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039

Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

PubMed

Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

2016-12-21

One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

Japanese project aims at supercomputer that executes 10 gflops

DOE Office of Scientific and Technical Information (OSTI.GOV)

Burskey, D.

1984-05-03

Dubbed supercom by its multicompany design team, the decade-long project's goal is an engineering supercomputer that can execute 10 billion floating-point operations/s-about 20 times faster than today's supercomputers. The project, guided by Japan's Ministry of International Trade and Industry (MITI) and the Agency of Industrial Science and Technology encompasses three parallel research programs, all aimed at some angle of the superconductor. One program should lead to superfast logic and memory circuits, another to a system architecture that will afford the best performance, and the last to the software that will ultimately control the computer. The work on logic and memorymore » chips is based on: GAAS circuit; Josephson junction devices; and high electron mobility transistor structures. The architecture will involve parallel processing.« less

Oscillatory threshold logic.

PubMed

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory.

Synthesis of energy-efficient FSMs implemented in PLD circuits

NASA Astrophysics Data System (ADS)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Sensor sentinel computing device

DOEpatents

Damico, Joseph P.

2016-08-02

Technologies pertaining to authenticating data output by sensors in an industrial environment are described herein. A sensor sentinel computing device receives time-series data from a sensor by way of a wireline connection. The sensor sentinel computing device generates a validation signal that is a function of the time-series signal. The sensor sentinel computing device then transmits the validation signal to a programmable logic controller in the industrial environment.

New reaction tester accurate within 56 microseconds

NASA Technical Reports Server (NTRS)

Brown, H.

1972-01-01

Testing device measures simple and disjunctive reaction time of human subject to light stimuli. Tester consists of reaction key, logic card, panel mounted neon indicators, and interconnecting wiring. Device is used for determining reaction times of patients undergoing postoperative neurological therapy.

Fuzzy logic control of an AGV

NASA Astrophysics Data System (ADS)

Kelkar, Nikhal; Samu, Tayib; Hall, Ernest L.

1997-09-01

Automated guided vehicles (AGVs) have many potential applications in manufacturing, medicine, space and defense. The purpose of this paper is to describe exploratory research on the design of a modular autonomous mobile robot controller. The controller incorporates a fuzzy logic approach for steering and speed control, a neuro-fuzzy approach for ultrasound sensing (not discussed in this paper) and an overall expert system. The advantages of a modular system are related to portability and transportability, i.e. any vehicle can become autonomous with minimal modifications. A mobile robot test-bed has been constructed using a golf cart base. This cart has full speed control with guidance provided by a vision system and obstacle avoidance using ultrasonic sensors. The speed and steering fuzzy logic controller is supervised by a 486 computer through a multi-axis motion controller. The obstacle avoidance system is based on a micro-controller interfaced with six ultrasonic transducers. This micro- controller independently handles all timing and distance calculations and sends a steering angle correction back to the computer via the serial line. This design yields a portable independent system in which high speed computer communication is not necessary. Vision guidance is accomplished with a CCD camera with a zoom lens. The data is collected by a vision tracking device that transmits the X, Y coordinates of the lane marker to the control computer. Simulation and testing of these systems yielded promising results. This design, in its modularity, creates a portable autonomous fuzzy logic controller applicable to any mobile vehicle with only minor adaptations.

Fuzzy logic and optical correlation-based face recognition method for patient monitoring application in home video surveillance

NASA Astrophysics Data System (ADS)

Elbouz, Marwa; Alfalou, Ayman; Brosseau, Christian

2011-06-01

Home automation is being implemented into more and more domiciles of the elderly and disabled in order to maintain their independence and safety. For that purpose, we propose and validate a surveillance video system, which detects various posture-based events. One of the novel points of this system is to use adapted Vander-Lugt correlator (VLC) and joint-transfer correlator (JTC) techniques to make decisions on the identity of a patient and his three-dimensional (3-D) positions in order to overcome the problem of crowd environment. We propose a fuzzy logic technique to get decisions on the subject's behavior. Our system is focused on the goals of accuracy, convenience, and cost, which in addition does not require any devices attached to the subject. The system permits one to study and model subject responses to behavioral change intervention because several levels of alarm can be incorporated according different situations considered. Our algorithm performs a fast 3-D recovery of the subject's head position by locating eyes within the face image and involves a model-based prediction and optical correlation techniques to guide the tracking procedure. The object detection is based on (hue, saturation, value) color space. The system also involves an adapted fuzzy logic control algorithm to make a decision based on information given to the system. Furthermore, the principles described here are applicable to a very wide range of situations and robust enough to be implementable in ongoing experiments.

Reproducible Operating Margins on a 72800-Device Digital Superconducting Chip (Open Access)

DTIC Science & Technology

2015-10-28

superconductor digital logic. Keywords: flux trapping, yield, digital Superconductor digital technology offers fundamental advantages over conventional...trapping in the superconductor films can degrade or preclude correct circuit operation. Scaling superconductor technology is now possible due to recent...advances in circuit design embodied in reciprocal quantum logic (RQL) [2, 3] and recent advances in superconductor integrated circuit fabrication, which

Photon-triggered nanowire transistors

NASA Astrophysics Data System (ADS)

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J.; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 106. A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Photon-triggered nanowire transistors.

PubMed

Kim, Jungkil; Lee, Hoo-Cheol; Kim, Kyoung-Ho; Hwang, Min-Soo; Park, Jin-Sung; Lee, Jung Min; So, Jae-Pil; Choi, Jae-Hyuck; Kwon, Soon-Hong; Barrelet, Carl J; Park, Hong-Gyu

2017-10-01

Photon-triggered electronic circuits have been a long-standing goal of photonics. Recent demonstrations include either all-optical transistors in which photons control other photons or phototransistors with the gate response tuned or enhanced by photons. However, only a few studies report on devices in which electronic currents are optically switched and amplified without an electrical gate. Here we show photon-triggered nanowire (NW) transistors, photon-triggered NW logic gates and a single NW photodetection system. NWs are synthesized with long crystalline silicon (CSi) segments connected by short porous silicon (PSi) segments. In a fabricated device, the electrical contacts on both ends of the NW are connected to a single PSi segment in the middle. Exposing the PSi segment to light triggers a current in the NW with a high on/off ratio of >8 × 10 6 . A device that contains two PSi segments along the NW can be triggered using two independent optical input signals. Using localized pump lasers, we demonstrate photon-triggered logic gates including AND, OR and NAND gates. A photon-triggered NW transistor of diameter 25 nm with a single 100 nm PSi segment requires less than 300 pW of power. Furthermore, we take advantage of the high photosensitivity and fabricate a submicrometre-resolution photodetection system. Photon-triggered transistors offer a new venue towards multifunctional device applications such as programmable logic elements and ultrasensitive photodetectors.

Electromechanical Componentry. High-Technology Training Module.

ERIC Educational Resources Information Center

Lindemann, Don

This training module on electromechanical components contains 10 units for a two-year vocational program packaging system equipment control course at Wisconsin Indianhead Technical College. This module describes the functions of electromechanical devices essential for understanding input/output devices for Programmable Logic Control (PLC)…

Conformation-based signal transfer and processing at the single-molecule level

NASA Astrophysics Data System (ADS)

Li, Chao; Wang, Zhongping; Lu, Yan; Liu, Xiaoqing; Wang, Li

2017-11-01

Building electronic components made of individual molecules is a promising strategy for the miniaturization and integration of electronic devices. However, the practical realization of molecular devices and circuits for signal transmission and processing at room temperature has proven challenging. Here, we present room-temperature intermolecular signal transfer and processing using SnCl2Pc molecules on a Cu(100) surface. The in-plane orientations of the molecules are effectively coupled via intermolecular interaction and serve as the information carrier. In the coupled molecular arrays, the signal can be transferred from one molecule to another in the in-plane direction along predesigned routes and processed to realize logical operations. These phenomena enable the use of molecules displaying intrinsic bistable states as complex molecular devices and circuits with novel functions.

Academic Achievement from Using the Learning Medium Via a Tablet Device Based on Multiple Intelligences in Grade 1 Elementary Student.

PubMed

Nuallaong, Winitra; Nuallaong, Thanya; Preechadirek, Nongluck

2015-04-01

To measure academic achievement of the multiple intelligence-based learning medium via a tablet device. This is a quasi-experimental research study (non-randomized control group pretest-posttest design) in 62 grade 1 elementary students (33 males and 29 females). Thirty-one students were included in an experimental group using purposive sampling by choosing a student who had highest multiple intelligence test scores in logical-mathematic. Then, this group learned by the new learning medium via a tablet which the application matched to logical-mathematic multiple intelligence. Another 31 students were included in a control group using simple random sampling and then learning by recitation. Both groups did pre-test and post-test vocabulary. Thirty students in the experimental group and 24 students in the control group increased post-test scores (odds ratio = 8.75). Both groups made significant increasing in post-test scores. The experimental group increased 9.07 marks (95% CI 8.20-9.93) significantly higher than the control group which increased 4.39 marks (95% CI 3.06-5.72) (t = -6.032, df = 51.481, p < 0.001). Although learning from either multiple intelligence-based learning medium via a tablet or recitation can contribute academic achievement, learningfrom the new medium contributed more achievement than recitation. The new learning medium group had higher post-test scores 8.75 times than the recitation group. Therefore, the new learning medium is more effective than the traditional recitation in terms of academic achievement. This study has limitations because samples came from the same school. However, the previous study in Thailand did notfind a logical-mathematical multiple intelligence difference among schools. In the future, long-term research to find how the new learning medium affects knowledge retention will support the advantage for life-long learning.

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Controlled Quantum Operations of a Semiconductor Three-Qubit System

NASA Astrophysics Data System (ADS)

Li, Hai-Ou; Cao, Gang; Yu, Guo-Dong; Xiao, Ming; Guo, Guang-Can; Jiang, Hong-Wen; Guo, Guo-Ping

2018-02-01

In a specially designed semiconductor device consisting of three capacitively coupled double quantum dots, we achieve strong and tunable coupling between a target qubit and two control qubits. We demonstrate how to completely switch on and off the target qubit's coherent rotations by presetting two control qubits' states. A Toffoli gate is, therefore, possible based on these control effects. This research paves a way for realizing full quantum-logic operations in semiconductor multiqubit systems.

Assembly of Ultra-Dense Nanowire-Based Computing Systems

DTIC Science & Technology

2006-06-30

34* characterized basic device element properties and statistics "* demonstrated product of sums (POS) validating assembled 2-bit adder structures " Demonstrated...linear region (Vds= 10 mV) from the peak g = 3 jiS at IVg -VTI= 0.13 V using the charge control model, representsmore than a factor of 10 improvement over...disrupted by ionizing particles or thermal fluctuation. Further, when working with such small charges, it is statistically possible that logic

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Feasibility study for future implantable neural-silicon interface devices.

PubMed

Al-Armaghany, Allann; Yu, Bo; Mak, Terrence; Tong, Kin-Fai; Sun, Yihe

2011-01-01

The emerging neural-silicon interface devices bridge nerve systems with artificial systems and play a key role in neuro-prostheses and neuro-rehabilitation applications. Integrating neural signal collection, processing and transmission on a single device will make clinical applications more practical and feasible. This paper focuses on the wireless antenna part and real-time neural signal analysis part of implantable brain-machine interface (BMI) devices. We propose to use millimeter-wave for wireless connections between different areas of a brain. Various antenna, including microstrip patch, monopole antenna and substrate integrated waveguide antenna are considered for the intra-cortical proximity communication. A Hebbian eigenfilter based method is proposed for multi-channel neuronal spike sorting. Folding and parallel design techniques are employed to explore various structures and make a trade-off between area and power consumption. Field programmable logic arrays (FPGAs) are used to evaluate various structures.

Biomolecular logic systems: applications to biosensors and bioactuators

NASA Astrophysics Data System (ADS)

Katz, Evgeny

2014-05-01

The paper presents an overview of recent advances in biosensors and bioactuators based on the biocomputing concept. Novel biosensors digitally process multiple biochemical signals through Boolean logic networks of coupled biomolecular reactions and produce output in the form of YES/NO response. Compared to traditional single-analyte sensing devices, biocomputing approach enables a high-fidelity multi-analyte biosensing, particularly beneficial for biomedical applications. Multi-signal digital biosensors thus promise advances in rapid diagnosis and treatment of diseases by processing complex patterns of physiological biomarkers. Specifically, they can provide timely detection and alert to medical emergencies, along with an immediate therapeutic intervention. Application of the biocomputing concept has been successfully demonstrated for systems performing logic analysis of biomarkers corresponding to different injuries, particularly exemplified for liver injury. Wide-ranging applications of multi-analyte digital biosensors in medicine, environmental monitoring and homeland security are anticipated. "Smart" bioactuators, for example for signal-triggered drug release, were designed by interfacing switchable electrodes and biocomputing systems. Integration of novel biosensing and bioactuating systems with the biomolecular information processing systems keeps promise for further scientific advances and numerous practical applications.

Role of biomolecular logic systems in biosensors and bioactuators

NASA Astrophysics Data System (ADS)

Mailloux, Shay; Katz, Evgeny

2014-09-01

An overview of recent advances in biosensors and bioactuators based on biocomputing systems is presented. Biosensors digitally process multiple biochemical signals through Boolean logic networks of coupled biomolecular reactions and produce an output in the form of a YES/NO response. Compared to traditional single-analyte sensing devices, the biocomputing approach enables high-fidelity multianalyte biosensing, which is particularly beneficial for biomedical applications. Multisignal digital biosensors thus promise advances in rapid diagnosis and treatment of diseases by processing complex patterns of physiological biomarkers. Specifically, they can provide timely detection and alert medical personnel of medical emergencies together with immediate therapeutic intervention. Application of the biocomputing concept has been successfully demonstrated for systems performing logic analysis of biomarkers corresponding to different injuries, particularly as exemplified for liver injury. Wide-ranging applications of multianalyte digital biosensors in medicine, environmental monitoring, and homeland security are anticipated. "Smart" bioactuators, for signal-triggered drug release, for example, were designed by interfacing switchable electrodes with biocomputing systems. Integration of biosensing and bioactuating systems with biomolecular information processing systems advances the potential for further scientific innovations and various practical applications.

The structure, logic of operation and distinctive features of the system of triggers and counting signals formation for gamma-telescope GAMMA-400

NASA Astrophysics Data System (ADS)

Topchiev, N. P.; Galper, A. M.; Arkhangelskiy, A. I.; Arkhangelskaja, I. V.; Kheymits, M. D.; Suchkov, S. I.; Yurkin, Y. T.

2017-01-01

Scientific project GAMMA-400 (Gamma Astronomical Multifunctional Modular Apparatus) relates to the new generation of space observatories intended to perform an indirect search for signatures of dark matter in the cosmic-ray fluxes, measurements of characteristics of diffuse gamma-ray emission and gamma-rays from the Sun during periods of solar activity, gamma-ray bursts, extended and point gamma-ray sources, electron/positron and cosmic-ray nuclei fluxes up to TeV energy region by means of the GAMMA-400 gamma-ray telescope represents the core of the scientific complex. The system of triggers and counting signals formation of the GAMMA-400 gamma-ray telescope constitutes the pipelined processor structure which collects data from the gamma-ray telescope subsystems and produces summary information used in forming the trigger decision for each event. The system design is based on the use of state-of-the-art reconfigurable logic devices and fast data links. The basic structure, logic of operation and distinctive features of the system are presented.

Fluorescence Resonance Energy Transfer-Based Photonic Circuits Using Single-Stranded Tile Self-Assembly and DNA Strand Displacement.

PubMed

Zhang, Xuncai; Ying, Niu; Shen, Chaonan; Cui, Guangzhao

2017-02-01

Structural DNA nanotechnology has great potential in the fabrication of complicated nanostructures and devices capable of bio-sensing and logic function. A variety of nanostructures with desired shapes have been created in the past few decades. But the application of nanostructures remains to be fully studied. Here, we present a novel biological information processing system constructed on a self-assembled, spatially addressable single-stranded tile (SST) nanostructure as DNA nano-manipulation platform that created by SST self-assembly technology. Utilizing DNA strand displacement technology, the fluorescent dye that is pre-assembled in the nano-manipulation platform is transferred from the original position to the destination, which can achieve photonic logic circuits by FRET signal cascades, including logic AND, OR, and NOT gates. And this transfer process is successfully validated by visual DSD software. The transfer process proposed in this study may provide a novel method to design complicated biological information processing system constructed on a SST nanostructure, and can be further used to develop intelligent delivery of drug molecules in vivo.

Realization of spin wave switch for data processing

NASA Astrophysics Data System (ADS)

Balinskiy, M.; Chiang, H.; Khitun, A.

2018-05-01

In this work, experimental data on a spin wave switch based on spin wave interference is reported. The switch is a three terminal device where spin wave propagation between the source and the drain is modulated by the control spin wave signal. The prototype is a micrometer scale device based on Y3Fe2(FeO4)3 film. The output characteristics show the oscillation of the output spin wave signal as a function of the phase difference between the source and the drain spin wave signals. The On/Off ratio of the prototype exceeds 20 dB at room temperature. The utilization of phase in addition to amplitude for information encoding offers an innovative route towards multi-state logic circuits. The advantages and shortcomings of spin wave switches are also discussed.

The Use of Stepper Motor-Controlled Proportional Valve for Fio2 Calculation in the Ventilator and its Control with Fuzzy Logic.

PubMed

Gölcük, Adem; Güler, İnan

2017-01-01

This article proposes the employment of a proportional valve that can calculate the amount of oxygen in the air to be given to patient in accordance with the amount of FiO 2 which is set from the control menu of the ventilation device. To actualize this, a stepper motor-controlled proportional valve was used. Two counts of valves were employed in order to control the gases with 2 bar pressure that came from both the oxygen and medical air tanks. Oxygen and medical air manometers alongside the pressure regulators were utilized to perform this task. It is a fuzzy-logic-based controller which calculates at what rate the proportional valves will be opened and closed for FiO 2 calculation. Fluidity and pressure of air given by the ventilation device were tested with a FlowMeter while the oxygen level was tested using the electronic lung model. The obtained results from the study revealed that stepper motor controlled proportional valve could be safely used in ventilation devices. In this article, it was indicated that fluidity and pressure control could be carried out with just two counts of proportional valve, which could be done with many solenoid valves, so this reduces the cost of ventilator, electrical power consumed by the ventilator, and the dimension of ventilator.

Graphene field effect transistor without an energy gap.

PubMed

Jang, Min Seok; Kim, Hyungjun; Son, Young-Woo; Atwater, Harry A; Goddard, William A

2013-05-28

Graphene is a room temperature ballistic electron conductor and also a very good thermal conductor. Thus, it has been regarded as an ideal material for postsilicon electronic applications. A major complication is that the relativistic massless electrons in pristine graphene exhibit unimpeded Klein tunneling penetration through gate potential barriers. Thus, previous efforts to realize a field effect transistor for logic applications have assumed that introduction of a band gap in graphene is a prerequisite. Unfortunately, extrinsic treatments designed to open a band gap seriously degrade device quality, yielding very low mobility and uncontrolled on/off current ratios. To solve this dilemma, we propose a gating mechanism that leads to a hundredfold enhancement in on/off transmittance ratio for normally incident electrons without any band gap engineering. Thus, our saw-shaped geometry gate potential (in place of the conventional bar-shaped geometry) leads to switching to an off state while retaining the ultrahigh electron mobility in the on state. In particular, we report that an on/off transmittance ratio of 130 is achievable for a sawtooth gate with a gate length of 80 nm. Our switching mechanism demonstrates that intrinsic graphene can be used in designing logic devices without serious alteration of the conventional field effect transistor architecture. This suggests a new variable for the optimization of the graphene-based device--geometry of the gate electrode.

A nanocryotron comparator can connect single-flux-quantum circuits to conventional electronics

NASA Astrophysics Data System (ADS)

Zhao, Qing-Yuan; McCaughan, Adam N.; Dane, Andrew E.; Berggren, Karl K.; Ortlepp, Thomas

2017-04-01

Integration with conventional electronics offers a straightforward and economical approach to upgrading existing superconducting technologies, such as scaling up superconducting detectors into large arrays and combining single flux quantum (SFQ) digital circuits with semiconductor logic gates and memories. However, direct output signals from superconducting devices (e.g., Josephson junctions) are usually not compatible with the input requirements of conventional devices (e.g., transistors). Here, we demonstrate the use of a single three-terminal superconducting-nanowire device, called the nanocryotron (nTron), as a digital comparator to combine SFQ circuits with mature semiconductor circuits such as complementary metal oxide semiconductor (CMOS) circuits. Since SFQ circuits can digitize output signals from general superconducting devices and CMOS circuits can interface existing CMOS-compatible electronics, our results demonstrate the feasibility of a general architecture that uses an nTron as an interface to realize a ‘super-hybrid’ system consisting of superconducting detectors, superconducting quantum electronics, CMOS logic gates and memories, and other conventional electronics.

Valve system incorporating single failure protection logic

DOEpatents

Ryan, Rodger; Timmerman, Walter J. H.

1980-01-01

A valve system incorporating single failure protective logic. The system consists of a valve combination or composite valve which allows actuation or de-actuation of a device such as a hydraulic cylinder or other mechanism, integral with or separate from the valve assembly, by means of three independent input signals combined in a function commonly known as two-out-of-three logic. Using the input signals as independent and redundant actuation/de-actuation signals, a single signal failure, or failure of the corresponding valve or valve set, will neither prevent the desired action, nor cause the undesired action of the mechanism.

Programmed optoelectronic time-pulse coded relational processor as base element for sorting neural networks

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Bardachenko, Vitaliy F.; Nikolsky, Alexander I.; Lazarev, Alexander A.

2007-04-01

In the paper we show that the biologically motivated conception of the use of time-pulse encoding gives the row of advantages (single methodological basis, universality, simplicity of tuning, training and programming et al) at creation and designing of sensor systems with parallel input-output and processing, 2D-structures of hybrid and neuro-fuzzy neurocomputers of next generations. We show principles of construction of programmable relational optoelectronic time-pulse coded processors, continuous logic, order logic and temporal waves processes, that lie in basis of the creation. We consider structure that executes extraction of analog signal of the set grade (order), sorting of analog and time-pulse coded variables. We offer optoelectronic realization of such base relational elements of order logic, which consists of time-pulse coded phototransformers (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutations blocks. We make estimations of basic technical parameters of such base devices and processors on their basis by simulation and experimental research: power of optical input signals - 0.200-20 μW, processing time - microseconds, supply voltage - 1.5-10 V, consumption power - hundreds of microwatts per element, extended functional possibilities, training possibilities. We discuss some aspects of possible rules and principles of training and programmable tuning on the required function, relational operation and realization of hardware blocks for modifications of such processors. We show as on the basis of such quasiuniversal hardware simple block and flexible programmable tuning it is possible to create sorting machines, neural networks and hybrid data-processing systems with the untraditional numerical systems and pictures operands.

Interface For Dual-Channel MIL-STD-1553 Data Bus

NASA Technical Reports Server (NTRS)

Davies, Bryan L.; Heaps, Timothy L.

1992-01-01

Digital electronic subsystem made of commercially available programmable logic arrays and discrete logic devices serves as interface between microprocessor and dual-channel MIL-STD-1553 data bus. Subsystem consumes only 800 mW of power. Provides flexibility in that it is controllable via firmware. Includes only two reading-and-writing ports: one for status and control signals, other for transmission and reception of data.

Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch

PubMed Central

Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

2010-01-01

Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and ‘memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch. PMID:20212522

Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch.

PubMed

Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

2010-01-01

Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch.

Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

PubMed Central

Dutta, Sourav; Chang, Sou-Chi; Kani, Nickvash; Nikonov, Dmitri E.; Manipatruni, Sasikanth; Young, Ian A.; Naeemi, Azad

2015-01-01

The possibility of using spin waves for information transmission and processing has been an area of active research due to the unique ability to manipulate the amplitude and phase of the spin waves for building complex logic circuits with less physical resources and low power consumption. Previous proposals on spin wave logic circuits have suggested the idea of utilizing the magneto-electric effect for spin wave amplification and amplitude- or phase-dependent switching of magneto-electric cells. Here, we propose a comprehensive scheme for building a clocked non-volatile spin wave device by introducing a charge-to-spin converter that translates information from electrical domain to spin domain, magneto-electric spin wave repeaters that operate in three different regimes - spin wave transmitter, non-volatile memory and spin wave detector, and a novel clocking scheme that ensures sequential transmission of information and non-reciprocity. The proposed device satisfies the five essential requirements for logic application: nonlinearity, amplification, concatenability, feedback prevention, and complete set of Boolean operations. PMID:25955353

3VSR: Three Valued Secure Routing for Vehicular Ad Hoc Networks using Sensing Logic in Adversarial Environment

PubMed Central

Wang, Liangmin

2018-01-01

Today IoT integrate thousands of inter networks and sensing devices e.g., vehicular networks, which are considered to be challenging due to its high speed and network dynamics. The goal of future vehicular networks is to improve road safety, promote commercial or infotainment products and to reduce the traffic accidents. All these applications are based on the information exchange among nodes, so not only reliable data delivery but also the authenticity and credibility of the data itself are prerequisite. To cope with the aforementioned problem, trust management come up as promising candidate to conduct node’s transaction and interaction management, which requires distributed mobile nodes cooperation for achieving design goals. In this paper, we propose a trust-based routing protocol i.e., 3VSR (Three Valued Secure Routing), which extends the widely used AODV (Ad hoc On-demand Distance Vector) routing protocol and employs the idea of Sensing Logic-based trust model to enhance the security solution of VANET (Vehicular Ad-Hoc Network). The existing routing protocol are mostly based on key or signature-based schemes, which off course increases computation overhead. In our proposed 3VSR, trust among entities is updated frequently by means of opinion derived from sensing logic due to vehicles random topologies. In 3VSR the theoretical capabilities are based on Dirichlet distribution by considering prior and posterior uncertainty of the said event. Also by using trust recommendation message exchange, nodes are able to reduce computation and routing overhead. The simulated results shows that the proposed scheme is secure and practical. PMID:29538314

3VSR: Three Valued Secure Routing for Vehicular Ad Hoc Networks using Sensing Logic in Adversarial Environment.

PubMed

Sohail, Muhammad; Wang, Liangmin

2018-03-14

Today IoT integrate thousands of inter networks and sensing devices e.g., vehicular networks, which are considered to be challenging due to its high speed and network dynamics. The goal of future vehicular networks is to improve road safety, promote commercial or infotainment products and to reduce the traffic accidents. All these applications are based on the information exchange among nodes, so not only reliable data delivery but also the authenticity and credibility of the data itself are prerequisite. To cope with the aforementioned problem, trust management come up as promising candidate to conduct node's transaction and interaction management, which requires distributed mobile nodes cooperation for achieving design goals. In this paper, we propose a trust-based routing protocol i.e., 3VSR (Three Valued Secure Routing), which extends the widely used AODV (Ad hoc On-demand Distance Vector) routing protocol and employs the idea of Sensing Logic-based trust model to enhance the security solution of VANET (Vehicular Ad-Hoc Network). The existing routing protocol are mostly based on key or signature-based schemes, which off course increases computation overhead. In our proposed 3VSR, trust among entities is updated frequently by means of opinion derived from sensing logic due to vehicles random topologies. In 3VSR the theoretical capabilities are based on Dirichlet distribution by considering prior and posterior uncertainty of the said event. Also by using trust recommendation message exchange, nodes are able to reduce computation and routing overhead. The simulated results shows that the proposed scheme is secure and practical.

Nanoscale memory elements based on the superconductor-ferromagnet proximity effect and spin-transfer torque magnetization switching

NASA Astrophysics Data System (ADS)

Baek, Burm

Superconducting-ferromagnetic hybrid devices have potential for a practical memory technology compatible with superconducting logic circuits and may help realize energy-efficient, high-performance superconducting computers. We have developed Josephson junction devices with pseudo-spin-valve barriers. We observed changes in Josephson critical current depending on the magnetization state of the barrier (parallel or anti-parallel) through the superconductor-ferromagnet proximity effect. This effect persists to nanoscale devices in contrast to the remanent field effect. In nanopillar devices, the magnetization states of the pseudo-spin-valve barriers could also be switched with applied bias currents at 4 K, which is consistent with the spin-transfer torque effect in analogous room-temperature spin valve devices. These results demonstrate devices that combine major superconducting and spintronic effects for scalable read and write of memory states, respectively. Further challenges and proposals towards practical devices will also be discussed.In collaboration with: William Rippard, NIST - Boulder, Matthew Pufall, NIST - Boulder, Stephen Russek, NIST-Boulder, Michael Schneider, NIST - Boulder, Samuel Benz, NIST - Boulder, Horst Rogalla, NIST-Boulder, Paul Dresselhaus, NIST - Boulder

The design of radiation-hardened ICs for space - A compendium of approaches

NASA Technical Reports Server (NTRS)

Kerns, Sherra E.; Shafer, B. D; Rockett, L. R., Jr.; Pridmore, J. S.; Berndt, D. F.

1988-01-01

Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ISs.

Design on the x-ray oral digital image display card

NASA Astrophysics Data System (ADS)

Wang, Liping; Gu, Guohua; Chen, Qian

2009-10-01

According to the main characteristics of X-ray imaging, the X-ray display card is successfully designed and debugged using the basic principle of correlated double sampling (CDS) and combined with embedded computer technology. CCD sensor drive circuit and the corresponding procedures have been designed. Filtering and sampling hold circuit have been designed. The data exchange with PC104 bus has been implemented. Using complex programmable logic device as a device to provide gating and timing logic, the functions which counting, reading CPU control instructions, corresponding exposure and controlling sample-and-hold have been completed. According to the image effect and noise analysis, the circuit components have been adjusted. And high-quality images have been obtained.

Oscillatory Threshold Logic

PubMed Central

Borresen, Jon; Lynch, Stephen

2012-01-01

In the 1940s, the first generation of modern computers used vacuum tube oscillators as their principle components, however, with the development of the transistor, such oscillator based computers quickly became obsolete. As the demand for faster and lower power computers continues, transistors are themselves approaching their theoretical limit and emerging technologies must eventually supersede them. With the development of optical oscillators and Josephson junction technology, we are again presented with the possibility of using oscillators as the basic components of computers, and it is possible that the next generation of computers will be composed almost entirely of oscillatory devices. Here, we demonstrate how coupled threshold oscillators may be used to perform binary logic in a manner entirely consistent with modern computer architectures. We describe a variety of computational circuitry and demonstrate working oscillator models of both computation and memory. PMID:23173034

Centralized and distributed control architectures under Foundation Fieldbus network.

PubMed

Persechini, Maria Auxiliadora Muanis; Jota, Fábio Gonçalves

2013-01-01

This paper aims at discussing possible automation and control system architectures based on fieldbus networks in which the controllers can be implemented either in a centralized or in a distributed form. An experimental setup is used to demonstrate some of the addressed issues. The control and automation architecture is composed of a supervisory system, a programmable logic controller and various other devices connected to a Foundation Fieldbus H1 network. The procedures used in the network configuration, in the process modelling and in the design and implementation of controllers are described. The specificities of each one of the considered logical organizations are also discussed. Finally, experimental results are analysed using an algorithm for the assessment of control loops to compare the performances between the centralized and the distributed implementations. Copyright © 2012 ISA. Published by Elsevier Ltd. All rights reserved.

21 CFR 866.5360 - Cohn fraction IV immuno-logical test system.

Code of Federal Regulations, 2012 CFR

2012-04-01

...-lipoprotein), malnutrition, iron deficiency anemia, red blood cell disorders, and kidney disease. (b) Classification. Class I (general controls). The device is exempt from the premarket notification procedures in... test system is a device that consists of or measures that fraction of plasma proteins, predominantly...

21 CFR 866.5360 - Cohn fraction IV immuno-logical test system.

Code of Federal Regulations, 2011 CFR

2011-04-01

...-lipoprotein), malnutrition, iron deficiency anemia, red blood cell disorders, and kidney disease. (b) Classification. Class I (general controls). The device is exempt from the premarket notification procedures in... test system is a device that consists of or measures that fraction of plasma proteins, predominantly...

21 CFR 866.5360 - Cohn fraction IV immuno-logical test system.

Code of Federal Regulations, 2014 CFR

2014-04-01

...-lipoprotein), malnutrition, iron deficiency anemia, red blood cell disorders, and kidney disease. (b) Classification. Class I (general controls). The device is exempt from the premarket notification procedures in... test system is a device that consists of or measures that fraction of plasma proteins, predominantly...

21 CFR 866.5360 - Cohn fraction IV immuno-logical test system.

Code of Federal Regulations, 2013 CFR

2013-04-01

...-lipoprotein), malnutrition, iron deficiency anemia, red blood cell disorders, and kidney disease. (b) Classification. Class I (general controls). The device is exempt from the premarket notification procedures in... test system is a device that consists of or measures that fraction of plasma proteins, predominantly...

Solid State pH Sensor Based on Light Emitting Diodes (LED) As Detector Platform

PubMed Central

Lau, King Tong; Shepherd, R.; Diamond, Danny; Diamond, Dermot

2006-01-01

A low-power, high sensitivity, very low-cost light emitting diode (LED)-based device developed for low-cost sensor networks was modified with bromocresol green membrane to work as a solid-state pH sensor. In this approach, a reverse-biased LED functioning as a photodiode is coupled with a second LED configured in conventional emission mode. A simple timer circuit measures how long (in microsecond) it takes for the photocurrent generated on the detector LED to discharge its capacitance from logic 1 (+5 V) to logic 0 (+1.7 V). The entire instrument provides an inherently digital output of light intensity measurements for a few cents. A light dependent resistor (LDR) modified with similar sensor membrane was also used as a comparison method. Both the LED sensor and the LDR sensor responded to various pH buffer solutions in a similar way to obtain sigmoidal curves expected of the dye. The pKa value obtained for the sensors was found to agree with the literature value.

Energy management strategy based on fuzzy logic for a fuel cell hybrid bus

NASA Astrophysics Data System (ADS)

Gao, Dawei; Jin, Zhenhua; Lu, Qingchun

Fuel cell vehicles, as a substitute for internal-combustion-engine vehicles, have become a research hotspot for most automobile manufacturers all over the world. Fuel cell systems have disadvantages, such as high cost, slow response and no regenerative energy recovery during braking; hybridization can be a solution to these drawbacks. This paper presents a fuel cell hybrid bus which is equipped with a fuel cell system and two energy storage devices, i.e., a battery and an ultracapacitor. An energy management strategy based on fuzzy logic, which is employed to control the power flow of the vehicular power train, is described. This strategy is capable of determining the desired output power of the fuel cell system, battery and ultracapacitor according to the propulsion power and recuperated braking power. Some tests to verify the strategy were developed, and the results of the tests show the effectiveness of the proposed energy management strategy and the good performance of the fuel cell hybrid bus.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

Magnetization dynamics of single-domain nanodots and minimum energy dissipation during either irreversible or reversible switching

NASA Astrophysics Data System (ADS)

Madami, Marco; Gubbiotti, Gianluca; Tacchi, Silvia; Carlotti, Giovanni

2017-11-01

Single- or multi-layered planar magnetic dots, with lateral dimensions ranging from tens to hundreds of nanometers, are used as elemental switches in current and forthcoming devices for information and communication technology (ICT), including magnetic memories, spin-torque oscillators and nano-magnetic logic gates. In this review article, we will first discuss energy dissipation during irreversible switching protocols of dots of different dimensions, ranging from a few tens of nanometers to the micrometric range. Then we will focus on the fundamental energy limits of adiabatic (slow) erasure and reversal of a magnetic nanodot, showing that dissipationless operation is achievable, provided that both dynamic reversibility (arbitrarily slow application of external fields) and entropic reversibility (no free entropy increase) are insured. However, recent theoretical and experimental tests of magnetic-dot erasure reveal that intrinsic defects related to materials imperfections such as roughness or polycrystallinity, may cause an excess of dissipation if compared to the minimum theoretical limit. We will conclude providing an outlook on the most promising strategies to achieve a new generation of power-saving nanomagnetic logic devices based on clusters of interacting dots and on straintronics.

A learnable parallel processing architecture towards unity of memory and computing

NASA Astrophysics Data System (ADS)

Li, H.; Gao, B.; Chen, Z.; Zhao, Y.; Huang, P.; Ye, H.; Liu, L.; Liu, X.; Kang, J.

2015-08-01

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Computer-aided biochemical programming of synthetic microreactors as diagnostic devices.

PubMed

Courbet, Alexis; Amar, Patrick; Fages, François; Renard, Eric; Molina, Franck

2018-04-26

Biological systems have evolved efficient sensing and decision-making mechanisms to maximize fitness in changing molecular environments. Synthetic biologists have exploited these capabilities to engineer control on information and energy processing in living cells. While engineered organisms pose important technological and ethical challenges, de novo assembly of non-living biomolecular devices could offer promising avenues toward various real-world applications. However, assembling biochemical parts into functional information processing systems has remained challenging due to extensive multidimensional parameter spaces that must be sampled comprehensively in order to identify robust, specification compliant molecular implementations. We introduce a systematic methodology based on automated computational design and microfluidics enabling the programming of synthetic cell-like microreactors embedding biochemical logic circuits, or protosensors , to perform accurate biosensing and biocomputing operations in vitro according to temporal logic specifications. We show that proof-of-concept protosensors integrating diagnostic algorithms detect specific patterns of biomarkers in human clinical samples. Protosensors may enable novel approaches to medicine and represent a step toward autonomous micromachines capable of precise interfacing of human physiology or other complex biological environments, ecosystems, or industrial bioprocesses. © 2018 The Authors. Published under the terms of the CC BY 4.0 license.

A learnable parallel processing architecture towards unity of memory and computing.

PubMed

Li, H; Gao, B; Chen, Z; Zhao, Y; Huang, P; Ye, H; Liu, L; Liu, X; Kang, J

2015-08-14

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named "iMemComp", where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped "iMemComp" with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on "iMemComp" can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS2

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Kim, In Soo; Chen, Kan-Sheng; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2015-05-01

Continued progress in high-speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two-terminal device with internal resistance that depends on the history of the external bias voltage. State-of-the-art memristors, based on metal-insulator-metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to ˜103 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.

Organic-Inorganic Hybrid Halide Perovskites for Memories, Transistors, and Artificial Synapses.

PubMed

Choi, Jaeho; Han, Ji Su; Hong, Kootak; Kim, Soo Young; Jang, Ho Won

2018-05-30

Fascinating characteristics of halide perovskites (HPs), which cannot be seen in conventional semiconductors and metal oxides, have boosted the application of HPs in electronic devices beyond optoelectronics such as solar cells, photodetectors, and light-emitting diodes. Here, recent advances in HP-based memory and logic devices such as resistive-switching memories (i.e., resistive random access memory (RRAM) or memristors), transistors, and artificial synapses are reviewed, focusing on inherently exotic properties of HPs: i) tunable bandgap, ii) facile majority carrier control, iii) fast ion migration, and iv) superflexibility. Various fabrication techniques of HP thin films from solution-based methods to vacuum processes are introduced. Up-to-date work in the field, emphasizing the compositional flexibility of HPs, suggest that HPs are promising candidates for next-generation electronic devices. Taking advantages of their unique electrical properties, low-cost and low-temperature synthesis, and compositional and mechanical flexibility, HPs have enormous potential to provide a new platform for future electronic devices and explosively intensive studies will pave the way in finding new HP materials beyond conventional silicon-based semiconductors to keep up with "More-than-Moore" times. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

The first radical-based spintronic memristors: Towards resistive RAMs made of organic magnets

NASA Astrophysics Data System (ADS)

Goss, Karin; Krist, Florian; Seyfferle, Simon; Hoefel, Udo; Paretzki, Alexa; Dressel, Martin; Bogani, Lapo; Institut Fuer Anorganische Chemie, University of Stuttgart Collaboration; 1. Physikalisches Institut, University of Stuttgart Team

2014-03-01

Using molecules as building blocks for electronic devices offers ample possibilities for new device functionalities due to a chemical tunability much higher than that of standard inorganic materials, and at the same time offers a decrease in the size of the electronic component down to the single-molecule level. Purely organic molecules containing no metallic centers such as organic radicals can serve as an electronic component with magnetic properties due to the unpaired electron in the radical state. Here we present memristive logic units based on organic radicals of the nitronyl-nitroxide kind. Integrating these purely molecular units as a spin coated layer into crossbar arrays, electrically induced unipolar resistive switching is observed with a change in resistance of up to 100%. We introduce a model based on filamentary reorganization of molecules of different oxidation state revealing the importance of the molecular nature for the switching properties. The major role of the oxidation state of these paramagnetic molecules introduces a magnetic field dependence to the device functionality, which goes along with magnetoresistive charactistics observed for the material. These are the first steps towards a spintronic implementation of organic radicals in electronic devices.

Programmable nanowire circuits for nanoprocessors.

PubMed

Yan, Hao; Choe, Hwan Sung; Nam, SungWoo; Hu, Yongjie; Das, Shamik; Klemic, James F; Ellenbogen, James C; Lieber, Charles M

2011-02-10

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Implementation of Complex Biological Logic Circuits Using Spatially Distributed Multicellular Consortia

PubMed Central

Urrios, Arturo; de Nadal, Eulàlia; Solé, Ricard; Posas, Francesc

2016-01-01

Engineered synthetic biological devices have been designed to perform a variety of functions from sensing molecules and bioremediation to energy production and biomedicine. Notwithstanding, a major limitation of in vivo circuit implementation is the constraint associated to the use of standard methodologies for circuit design. Thus, future success of these devices depends on obtaining circuits with scalable complexity and reusable parts. Here we show how to build complex computational devices using multicellular consortia and space as key computational elements. This spatial modular design grants scalability since its general architecture is independent of the circuit’s complexity, minimizes wiring requirements and allows component reusability with minimal genetic engineering. The potential use of this approach is demonstrated by implementation of complex logical functions with up to six inputs, thus demonstrating the scalability and flexibility of this method. The potential implications of our results are outlined. PMID:26829588

High-Bandwidth Tactical-Network Data Analysis in a High-Performance-Computing (HPC) Environment: Transport Protocol (Transmission Control Protocol/User Datagram Protocol [TCP/UDP]) Analysis

DTIC Science & Technology

2015-09-01

the network Mac8 Medium Access Control ( Mac ) (Ethernet) address observed as destination for outgoing packets subsessionid8 Zero-based index of...15. SUBJECT TERMS tactical networks, data reduction, high-performance computing, data analysis, big data 16. SECURITY CLASSIFICATION OF: 17...Integer index of row cts_deid Device (instrument) Identifier where observation took place cts_collpt Collection point or logical observation point on

The use of programmable logic controllers (PLC) for rocket engine component testing

NASA Technical Reports Server (NTRS)

Nail, William; Scheuermann, Patrick; Witcher, Kern

1991-01-01

Application of PLCs to the rocket engine component testing at a new Stennis Space Center Component Test Facility is suggested as an alternative to dedicated specialized computers. The PLC systems are characterized by rugged design, intuitive software, fault tolerance, flexibility, multiple end device options, networking capability, and built-in diagnostics. A distributed PLC-based system is projected to be used for testing LH2/LOx turbopumps required for the ALS/NLS rocket engines.

Strain-controlled skyrmion creation and propagation in ferroelectric/ferromagnetic hybrid wires

NASA Astrophysics Data System (ADS)

Li, Zhi; Zhang, Youguang; Huang, Yangqi; Wang, Chengxiang; Zhang, Xichao; Liu, Yan; Zhou, Yan; Kang, Wang; Koli, Shradha Chandrashekhar; Lei, Na

2018-06-01

The control of magnetic skyrmion creation and pinning through strain is studied by micromagnetic simulations. A single stable skyrmion can be created by a vertical strain pulse on Pd/Fe/Ir hybrid structure on Pb(Zr1-xTix)O3 nanowire with -1.8 V pulse voltage from 1.2 ns to 2.0 ns. Then the skyrmion is pinned by the vertical strain independent of the polarity during its propagation in the wire driven by the current. The proposed device integrates strain-controlled skyrmion creation and pinning in a single nanowire structure, which would open a new route for skyrmion-based memory and logic devices with ultra-low power consumption.

Binary to Octal and Octal to Binary Code Converter Using Mach-Zehnder Interferometer for High Speed Communication

NASA Astrophysics Data System (ADS)

Pal, Amrindra; Kumar, Santosh; Sharma, Sandeep

2017-05-01

Binary to octal and octal to binary code converter is a device that allows placing digital information from many inputs to many outputs. Any application of combinational logic circuit can be implemented by using external gates. In this paper, binary to octal and octal to binary code converter is proposed using electro-optic effect inside lithium-niobate based Mach-Zehnder interferometers (MZIs). The MZI structures have powerful capability to switching an optical input signal to a desired output port. The paper constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

NASA Astrophysics Data System (ADS)

Jara Casas, L. M.; Ceresa, D.; Kulis, S.; Miryala, S.; Christiansen, J.; Francisco, R.; Gnani, D.

2017-02-01

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.

Energy efficient wireless sensor networks by using a fuzzy-based solution

NASA Astrophysics Data System (ADS)

Tirrito, Salvatore; Nicolosi, Giuseppina

2016-12-01

Wireless Sensor Networks are characterized by a distributed architecture realized by a set of autonomous electronic devices able to sense data from the surrounding environment and to communicate among them. These devices are battery powered since they may be used even to monitor hazardous events in inaccessible areas. As a consequence, it is preferable to assure the adoption of energy management solutions in order to extend the WSN lifetime, as far as possible. Moreover, it is crucial to guarantee that the nodes receive the transmitted data correctly. It is clear that trading off power optimization and quality of service has become one the most important concerns when dealing with modern systems based on WSNs. This paper introduces a solution based on a Fuzzy Logic Controller (FLC) focusing on the minimization of energy consumption of wireless sensor nodes. This is made possible because the sleeping time of these nodes is dynamically regulated by a FLC.

TMS for Instantiating a Knowledge Base With Incomplete Data

NASA Technical Reports Server (NTRS)

James, Mark

2007-01-01

A computer program that belongs to the class known among software experts as output truth-maintenance-systems (output TMSs) has been devised as one of a number of software tools for reducing the size of the knowledge base that must be searched during execution of artificial- intelligence software of the rule-based inference-engine type in a case in which data are missing. This program determines whether the consequences of activation of two or more rules can be combined without causing a logical inconsistency. For example, in a case involving hypothetical scenarios that could lead to turning a given device on or off, the program determines whether a scenario involving a given combination of rules could lead to turning the device both on and off at the same time, in which case that combination of rules would not be included in the scenario.

Performance analysis of resistive switching devices based on BaTiO3 thin films

NASA Astrophysics Data System (ADS)

Samardzic, Natasa; Kojic, Tijana; Vukmirovic, Jelena; Tripkovic, Djordjije; Bajac, Branimir; Srdic, Vladimir; Stojanovic, Goran

2016-03-01

Resitive switching devices, memristors, have recenty attracted much attention due to promising performances and potential applications in the field of logic and memory devices. Here, we present thin film BaTiO3 based memristor fabricated using ink-jet printing technique. Active material is a single layer barium titanate film with thickness of ̴100 nm, sandwitched between metal electodes. Printing parameters were optimized aiming to achieve stable drop flow and uniform printed layer. Current-voltage characteristics show typical memristive behavior with pinched hysteresis loop crossed at the origin, with marked differences between High Resistive State (HRS) and Low Resistive State (LRS). Obtained resistive states are stable during numerous switching processes. The device also shows unipolar switching effect for negative voltage impulses. Variable voltage impulse amplitudes leads to the shifting of the energy levels of electode contacts resulting in changing of the overall current through the device. Structural charcterization have been performed using XRD analysis and SEM micrography. High-temperature current-voltage measurements combined with transport parameter analysis using Hall efect measurement system (HMS 3000) and Impedance Analyzer AC measurements allows deeper insigth into conduction mechanism of ferroelectric memristors.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

DNA biosensors that reason.

PubMed

Sainz de Murieta, Iñaki; Rodríguez-Patón, Alfonso

2012-08-01

Despite the many designs of devices operating with the DNA strand displacement, surprisingly none is explicitly devoted to the implementation of logical deductions. The present article introduces a new model of biosensor device that uses nucleic acid strands to encode simple rules such as "IF DNA_strand(1) is present THEN disease(A)" or "IF DNA_strand(1) AND DNA_strand(2) are present THEN disease(B)". Taking advantage of the strand displacement operation, our model makes these simple rules interact with input signals (either DNA or any type of RNA) to generate an output signal (in the form of nucleotide strands). This output signal represents a diagnosis, which either can be measured using FRET techniques, cascaded as the input of another logical deduction with different rules, or even be a drug that is administered in response to a set of symptoms. The encoding introduces an implicit error cancellation mechanism, which increases the system scalability enabling longer inference cascades with a bounded and controllable signal-noise relation. It also allows the same rule to be used in forward inference or backward inference, providing the option of validly outputting negated propositions (e.g. "diagnosis A excluded"). The models presented in this paper can be used to implement smart logical DNA devices that perform genetic diagnosis in vitro. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

Logic computation in phase change materials by threshold and memory switching.

PubMed

Cassinerio, M; Ciocchini, N; Ielmini, D

2013-11-06

Memristors, namely hysteretic devices capable of changing their resistance in response to applied electrical stimuli, may provide new opportunities for future memory and computation, thanks to their scalable size, low switching energy and nonvolatile nature. We have developed a functionally complete set of logic functions including NOR, NAND and NOT gates, each utilizing a single phase-change memristor (PCM) where resistance switching is due to the phase transformation of an active chalcogenide material. The logic operations are enabled by the high functionality of nanoscale phase change, featuring voltage comparison, additive crystallization and pulse-induced amorphization. The nonvolatile nature of memristive states provides the basis for developing reconfigurable hybrid logic/memory circuits featuring low-power and high-speed switching. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A suggested approach to the selection of chemical and biological protective clothing--meeting industry and emergency response needs for protection against a variety of hazards.

PubMed

Stull, Jeffrey O

2004-01-01

The paper describes the development of a comprehensive decision logic for selection and use of biological and chemical protective clothing (BCPC). The decision logic recognizes the separate areas of BCPC use among emergency, biological, and chemical hazards. The proposed decision logic provides a system for type classifying BCPC in terms of its compliance with existing standards (for emergency applications), the overall clothing integrity, and the material barrier performance. Type classification is offered for garments, gloves, footwear, and eye/face protection devices. On the basis of multiple, but simply designed flowcharts, the type of BCPC appropriate for specific biological and chemical hazards can be selected. The decision logic also provides supplemental considerations for choosing appropriate BCPC features.

Metal oxide resistive random access memory based synaptic devices for brain-inspired computing

NASA Astrophysics Data System (ADS)

Gao, Bin; Kang, Jinfeng; Zhou, Zheng; Chen, Zhe; Huang, Peng; Liu, Lifeng; Liu, Xiaoyan

2016-04-01

The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

Noble Logic for Preventing Scratch on Roll-to-Roll Printed Layers in Noncontacting Transportation

NASA Astrophysics Data System (ADS)

Lee, Changwoo; Kang, Hyunkyoo; Kim, Hojoon; Shin, Keehyun

2010-05-01

The use of roll-to-roll (R2R) printed electronics is a relatively new method of mass producing flexible electronic devices while keeping production costs down. The geometrical qualities of a printed pattern, such as surface roughness and uniformity, could deteriorate. Moreover, the geometric qualities of a printed layer affect the functional qualities of a printed electronic device directly. Therefore, the functional qualities (conductivity and mobility) of a multilayer electronic device could deteriorate in the presence of a scratch defect on the printed layer. In general, a scratch on a printed pattern on a flexible substrate is induced by contact between the rolls and printed pattern in R2R printing systems. To prevent such contact, one of the best solutions is to use an air flotation unit. However, a scratch defect could be induced even though an air flotation process is used to minimize contact, because the flotation height of a moving web is affected by web tension. In this paper, we discuss an analytical model of an air-floated moving substrate. For the noncontacting transfer of a moving web without a scratch defect, a mathematical tension model has been developed by considering an induced strain due to aerodynamic forces and verified by numerical and experimental studies. Additionally, the correlation between the flotation height of an air-floated moving web and speed compensation used to control the tension are investigated. The analysis shows that tension fluctuations can cause the substrate to touch the air-flotation subsystem, which is installed to prevent contact, resulting in defects such as scratches on the printed layer. On the basis of the proposed model, a logic is developed to minimize scratch defects on R2R printed layers in noncontacting transportation. Through a guideline based on this logic, the scratched area density on R2R printed layers can be reduced by approximately 70%.

Multiscale modeling of nanostructured ZnO based devices for optoelectronic applications: Dynamically-coupled structural fields, charge, and thermal transport processes

NASA Astrophysics Data System (ADS)

Abdullah, Abdulmuin; Alqahtani, Saad; Nishat, Md Rezaul Karim; Ahmed, Shaikh; SIU Nanoelectronics Research Group Team

Recently, hybrid ZnO nanostructures (such as ZnO deposited on ZnO-alloys, Si, GaN, polymer, conducting oxides, and organic compounds) have attracted much attention for their possible applications in optoelectronic devices (such as solar cells, light emitting and laser diodes), as well as in spintronics (such as spin-based memory, and logic). However, efficiency and performance of these hybrid ZnO devices strongly depend on an intricate interplay of complex, nonlinear, highly stochastic and dynamically-coupled structural fields, charge, and thermal transport processes at different length and time scales, which have not yet been fully assessed experimentally. In this work, we study the effects of these coupled processes on the electronic and optical emission properties in nanostructured ZnO devices. The multiscale computational framework employs the atomistic valence force-field molecular mechanics, models for linear and non-linear polarization, the 8-band sp3s* tight-binding models, and coupling to a TCAD toolkit to determine the terminal properties of the device. A series of numerical experiments are performed (by varying different nanoscale parameters such as size, geometry, crystal cut, composition, and electrostatics) that mainly aim to improve the efficiency of these devices. Supported by the U.S. National Science Foundation Grant No. 1102192.

Digital optical signal processing with polarization-bistable semiconductor lasers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jai-Ming Liu,; Ying-Chin Chen,

1985-04-01

The operations of a complete set of optical AND, NAND, OR, and NOR gates and clocked optical S-R, D, J-K, and T flip-flops are demonstrated, based on direct polarization switching and polarization bistability, which we have recently observed in InGaAsP/InP semiconductor lasers. By operating the laser in the direct-polarizationswitchable mode, the output of the laser can be directly switched between the TM00 and TE00 modes with high extinction ratios by changing the injection-current level, and optical logic gates are constructed with two optoelectronic switches or photodetectors. In the polarization-bistable mode, the laser exhibits controllable hysteresis loops in the polarization-resolved powermore » versus current characteristics. When the laser is biased in the middle of the hysteresis loop, the light output can be switched between the two polarization states by injection of short electrical or optical pulses, and clocked optical flip-flops are constructed with a few optoelectronic switches and/or photodetectors. The 1 and 0 states of these devices are defined through polarization changes of the laser and direct complement functions are obtainable from the TE and TM output signals from the same laser. Switching of the polarization-bistable lasers with fast-rising current pulses has an instrument-limited mode-switching time on the order of 1 ns. With fast optoelectronic switches and/or fast photodetectors, the overall switching speed of the logic gates and flip-flops is limited by the polarizationbistable laser to <1 ns. We have demonstrated the operations of these devices using optical signals generated by semiconductor lasers. The proposed schemes of our devices are compatible with monolithic integration based on current fabrication technology and are applicable to other types of bistable semiconductor lasers.« less

A graphene solution to conductivity mismatch: spin injection from ferromagnetic metal/graphene tunnel contacts into silicon

NASA Astrophysics Data System (ADS)

van't Erve, Olaf

2014-03-01

New paradigms for spin-based devices, such as spin-FETs and reconfigurable logic, have been proposed and modeled. These devices rely on electron spin being injected, transported, manipulated and detected in a semiconductor channel. This work is the first demonstration on how a single layer of graphene can be used as a low resistance tunnel barrier solution for electrical spin injection into Silicon at room temperature. We will show that a FM metal / monolayer graphene contact serves as a spin-polarized tunnel barrier which successfully circumvents the classic metal / semiconductor conductivity mismatch issue for electrical spin injection. We demonstrate electrical injection and detection of spin accumulation in Si above room temperature, and show that the corresponding spin lifetimes correlate with the Si carrier concentration, confirming that the spin accumulation measured occurs in the Si and not in interface trap states. An ideal tunnel barrier should exhibit several key material characteristics: a uniform and planar habit with well-controlled thickness, minimal defect / trapped charge density, a low resistance-area product for minimal power consumption, and compatibility with both the FM metal and semiconductor, insuring minimal diffusion to/from the surrounding materials at temperatures required for device processing. Graphene, offers all of the above, while preserving spin injection properties, making it a compelling solution to the conductivity mismatch for spin injection into Si. Although Graphene is very conductive in plane, it exhibits poor conductivity perpendicular to the plane. Its sp2 bonding results in a highly uniform, defect free layer, which is chemically inert, thermally robust, and essentially impervious to diffusion. The use of a single monolayer of graphene at the Si interface provides a much lower RA product than any film of an oxide thick enough to prevent pinholes (1 nm). Our results identify a new route to low resistance-area product spin-polarized contacts, a crucial requirement enabling future semiconductor spintronic devices, which rely upon two-terminal magnetoresistance, including spin-based transistors, logic and memory.

GaAs integrated circuits and heterojunction devices

NASA Astrophysics Data System (ADS)

Fowlis, Colin

1986-06-01

The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

An efficient and ultrasensitive rhodamine B-based reversible colorimetric chemosensor for naked-eye recognition of molybdenum and citrate ions in aqueous solution: Sensing behavior and logic operation

NASA Astrophysics Data System (ADS)

Tavallali, Hossein; Deilamy-Rad, Gohar; Parhami, Abolfath; Hasanli, Nahid

2015-03-01

In this paper we manifest a novel rhodamine B (RhB) based colorimetric chemosensor for molybdenum and citrate ions (Cit3-) in an absolutely aqueous media. It has been identified as highly sensitive probe for Mo6+ which responds at 4.0 nmol L-1 concentration levels. RhB while combined with Mo6+ in aqueous solution displays a color changing from pink to purple which could be quickly dissociated by the addition of citrate in this system so that reversible color changes from purple to pink can be achieved. The comparison of this method with some other methods for citrate indicates that this is the only method which can detect citrate in aqueous solution by color changes. This chemosensor can be applied for quantification of citrate with a linear range covering from 1.67 × 10-7 to 1.22 × 10-5 M and a detection limit of 2.0 × 10-8 M. Moreover, the response of the chemosensor toward Mo6+ and citrate is fast. In addition, based on above sensing mechanism, an IMPLICATION logic operation can be achieved using Mo6+ ion and Cit3- as the inputs, making RhB a promising candidate for further applications in molecular logic devices and also indicates that RhB is suitable for the detection of Mo6+ and Cit3- ions in real samples.

An efficient and ultrasensitive rhodamine B-based reversible colorimetric chemosensor for naked-eye recognition of molybdenum and citrate ions in aqueous solution: sensing behavior and logic operation.

PubMed

Tavallali, Hossein; Deilamy-Rad, Gohar; Parhami, Abolfath; Hasanli, Nahid

2015-03-15

In this paper we manifest a novel rhodamine B (RhB) based colorimetric chemosensor for molybdenum and citrate ions (Cit(3-)) in an absolutely aqueous media. It has been identified as highly sensitive probe for Mo(6+) which responds at 4.0 nmol L(-1) concentration levels. RhB while combined with Mo(6+) in aqueous solution displays a color changing from pink to purple which could be quickly dissociated by the addition of citrate in this system so that reversible color changes from purple to pink can be achieved. The comparison of this method with some other methods for citrate indicates that this is the only method which can detect citrate in aqueous solution by color changes. This chemosensor can be applied for quantification of citrate with a linear range covering from 1.67×10(-7) to 1.22×10(-5) M and a detection limit of 2.0×10(-8) M. Moreover, the response of the chemosensor toward Mo(6+) and citrate is fast. In addition, based on above sensing mechanism, an IMPLICATION logic operation can be achieved using Mo(6+) ion and Cit(3-) as the inputs, making RhB a promising candidate for further applications in molecular logic devices and also indicates that RhB is suitable for the detection of Mo(6+) and Cit(3-) ions in real samples. Copyright © 2014 Elsevier B.V. All rights reserved.

Nanomagnetic Logic

NASA Astrophysics Data System (ADS)

Carlton, David Bryan

The exponential improvements in speed, energy efficiency, and cost that the computer industry has relied on for growth during the last 50 years are in danger of ending within the decade. These improvements all have relied on scaling the size of the silicon-based transistor that is at the heart of every modern CPU down to smaller and smaller length scales. However, as the size of the transistor reaches scales that are measured in the number of atoms that make it up, it is clear that this scaling cannot continue forever. As a result of this, there has been a great deal of research effort directed at the search for the next device that will continue to power the growth of the computer industry. However, due to the billions of dollars of investment that conventional silicon transistors have received over the years, it is unlikely that a technology will emerge that will be able to beat it outright in every performance category. More likely, different devices will possess advantages over conventional transistors for certain applications and uses. One of these emerging computing platforms is nanomagnetic logic (NML). NML-based circuits process information by manipulating the magnetization states of single-domain nanomagnets coupled to their nearest neighbors through magnetic dipole interactions. The state variable is magnetization direction and computations can take place without passing an electric current. This makes them extremely attractive as a replacement for conventional transistor-based computing architectures for certain ultra-low power applications. In most work to date, nanomagnetic logic circuits have used an external magnetic clocking field to reset the system between computations. The clocking field is then subsequently removed very slowly relative to the magnetization dynamics, guiding the nanomagnetic logic circuit adiabatically into its magnetic ground state. In this dissertation, I will discuss the dynamics behind this process and show that it is greatly influenced by thermal fluctuations. The magnetic ground state containing the answer to the computation is reached by a stochastic process very similar to the thermal annealing of crystalline materials. We will discuss how these dynamics affect the expected reliability, speed, and energy dissipation of NML systems operating under these conditions. Next I will show how a slight change in the properties of the nanomagnets that make up a NML circuit can completely alter the dynamics by which computations take place. The addition of biaxial anisotropy to the magnetic energy landscape creates a metastable state along the hard axis of the nanomagnet. This metastability can be used to remove the stochastic nature of the computation and has large implications for reliability, speed, and energy dissipation which will all be discussed. The changes to NML operation by the addition of biaxial anisotropy introduce new challenges to realizing a commercially viable logic architecture. In the final chapter, I will discuss these challenges and talk about the architectural changes that are necessary to make a working NML circuit based on nanomagnets with biaxial anisotropy.

Memristive switching of MgO based magnetic tunnel junctions

NASA Astrophysics Data System (ADS)

Krzysteczko, Patryk; Reiss, Günter; Thomas, Andy

2009-09-01

Here we demonstrate that both, tunnel magnetoresistance (TMR) and resistive switching (RS), can be observed simultaneously in nanoscale magnetic tunnel junctions. The devices show bipolar RS of 6% and TMR ratios of about 100%. For each magnetic state, multiple resistive states are created depending on the bias history, which provides a method for multibit data storage and logic. The electronic transport measurements are discussed in the framework of a memristive system. Differently prepared MgO barriers are compared to gain insight into the switching mechanism.

III-V Semiconductor Optical Micro-Ring Resonators

NASA Astrophysics Data System (ADS)

Grover, Rohit; Absil, Philippe P.; Ibrahim, Tarek A.; Ho, Ping-Tong

2004-05-01

We describe the theory of optical ring resonators, and our work on GaAs-AlGaAs and GaInAsP-InP optical micro-ring resonators. These devices are promising building blocks for future all-optical signal processing and photonic logic circuits. Their versatility allows the fabrication of ultra-compact multiplexers/demultiplexers, optical channel dropping filters, lasers, amplifiers, and logic gates (to name a few), which will enable large-scale monolithic integration for optics.

Testability Design Rating System: Testability Handbook. Volume 1

DTIC Science & Technology

1992-02-01

4-10 4.7.5 Summary of False BIT Alarms (FBA) ............................. 4-10 4.7.6 Smart BIT Technique...Circuit Board PGA Pin Grid Array PLA Programmable Logic Array PLD Programmable Logic Device PN Pseudo-Random Number PREDICT Probabilistic Estimation of...11 4.7.6 Smart BIT ( reference: RADC-TR-85-198). " Smart " BIT is a term given to BIT circuitry in a system LRU which includes dedicated processor/memory

Inorganic proton conducting electrolyte coupled oxide-based dendritic transistors for synaptic electronics.

PubMed

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2014-05-07

Ionic/electronic hybrid devices with synaptic functions are considered to be the essential building blocks for neuromorphic systems and brain-inspired computing. Here, artificial synapses based on indium-zinc-oxide (IZO) transistors gated by nanogranular SiO2 proton-conducting electrolyte films are fabricated on glass substrates. Spike-timing dependent plasticity and paired-pulse facilitation are successfully mimicked in an individual bottom-gate transistor. Most importantly, dynamic logic and dendritic integration established by spatiotemporally correlated spikes are also mimicked in dendritic transistors with two in-plane gates as the presynaptic input terminals.

Epilepsy Forewarning Using A Hand-Held Device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hively, LM

2005-02-21

Over the last decade, ORNL has developed and patented a novel approach for forewarning of a large variety of machine and biomedical events. The present implementation uses desktop computers to analyze archival data. This report describes the next logical step in this effort, namely use of a hand-held device for the analysis.

Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

NASA Astrophysics Data System (ADS)

Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernandez-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph

2015-11-01

Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 μm × 10 μm using 6 NEM switches. Each NEM switch device has a footprint of 5 μm × 3 μm, an air gap of 60 μm and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

NASA Astrophysics Data System (ADS)

Li, Huiyun; Du, Guanghua; Shao, Cuiping; Dai, Liang; Xu, Guoqing; Guo, Jinlong

2015-06-01

Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations.

Investigation of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors for logic application

NASA Astrophysics Data System (ADS)

Tsai, Jung-Hui

2014-01-01

DC performance of InP/InGaAs metamorphic co-integrated complementary doping-channel field-effect transistors (DCFETs) grown on a low-cost GaAs substrate is first demonstrated. In the complementary DCFETs, the n-channel device was fabricated on the InxGa1-xP metamorphic linearly graded buffer layer and the p-channel field-effect transistor was stacked on the top of the n-channel device. Particularly, the saturation voltage of the n-channel device is substantially reduced to decrease the VOL and VIH values attributed that two-dimensional electron gas is formed and could be modulated in the n-InGaAs channel. Experimentally, a maximum extrinsic transconductance of 215 (17) mS/mm and a maximum saturation current density of 43 (-27) mA/mm are obtained in the n-channel (p-channel) device. Furthermore, the noise margins NMH and NML are up to 0.842 and 0.330 V at a supply voltage of 1.5 V in the complementary logic inverter application.

Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

NASA Astrophysics Data System (ADS)

Geier, Michael

Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and symmetric threshold voltages. Additionally, a novel n-type doping procedure for SWCNT TFTs was also developed utilizing a solution-processed organometallic small molecule to demonstrate the first network top-gated n-type SWCNT TFTs. Lastly, new doping and encapsulation layers were incorporated to stabilize both p-type and n-type SWCNT TFT electronic properties, which enabled the fabrication of large-scale memory circuits. Employing these materials and processing advances has addressed many application specific barriers to commercialization. For instance, the first thin-film SWCNT complementary metal-oxide-semi-conductor (CMOS) logic devices are demonstrated with sub-nanowatt static power consumption and full rail-to-rail voltage transfer characteristics. With the introduction of a new n-type Rh-based molecular dopant, the first SWCNT TFTs are fabricated in top-gate geometries over large areas with high yield. Then by utilizing robust encapsulation methods, stable and uniform electronic performance of both p-type and n-type SWCNT TFTs has been achieved. Based on these complementary SWCNT TFTs, it is possible to simulate, design, and fabricate arrays of low-power static random access memory (SRAM) circuits, achieving large-scale integration for the first time based on solution-processed semiconductors. Together, this work provides a direct pathway for solution processable, large scale, power-efficient advanced integrated logic circuits and systems.

Resonant cavity enhanced photonic devices

NASA Astrophysics Data System (ADS)

Ünlü, M. Selim; Strite, Samuel

1995-07-01

We review the family of optoelectronic devices whose performance is enhanced by placing the active device structure inside a Fabry-Perot resonant microcavity. Such resonant cavity enhanced (RCE) devices benefit from the wavelength selectivity and the large increase of the resonant optical field introduced by the cavity. The increased optical field allows RCE photodetector structures to be thinner and therefore faster, while simultaneously increasing the quantum efficiency at the resonant wavelengths. Off-resonance wavelengths are rejected by the cavity making RCE photodetectors promising for low crosstalk wavelength division multiplexing (WDM) applications. RCE optical modulators require fewer quantum wells so are capable of reduced voltage operation. The spontaneous emission spectrum of RCE light emitting diodes (LED) is drastically altered, improving the spectral purity and directivity. RCE devices are also highly suitable for integrated detectors and emitters with applications as in optical logic and in communication networks. This review attempts an encyclopedic overview of RCE photonic devices and systems. Considerable attention is devoted to the theoretical formulation and calculation of important RCE device parameters. Materials criteria are outlined and the suitability of common heteroepitaxial systems for RCE devices is examined. Arguments for the improved bandwidth in RCE detectors are presented intuitively, and results from advanced numerical simulations confirming the simple model are provided. An overview of experimental results on discrete RCE photodiodes, phototransistors, modulators, and LEDs is given. Work aimed at integrated RCE devices, optical logic and WDM systems is also covered. We conclude by speculating what remains to be accomplished to implement a practical RCE WDM system.

Interlocked DNA nanostructures controlled by a reversible logic circuit.

PubMed

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-09-17

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems.

Interlocked DNA nanostructures controlled by a reversible logic circuit

PubMed Central

Li, Tao; Lohmann, Finn; Famulok, Michael

2014-01-01

DNA nanostructures constitute attractive devices for logic computing and nanomechanics. An emerging interest is to integrate these two fields and devise intelligent DNA nanorobots. Here we report a reversible logic circuit built on the programmable assembly of a double-stranded (ds) DNA [3]pseudocatenane that serves as a rigid scaffold to position two separate branched-out head-motifs, a bimolecular i-motif and a G-quadruplex. The G-quadruplex only forms when preceded by the assembly of the i-motif. The formation of the latter, in turn, requires acidic pH and unhindered mobility of the head-motif containing dsDNA nanorings with respect to the central ring to which they are interlocked, triggered by release oligodeoxynucleotides. We employ these features to convert the structural changes into Boolean operations with fluorescence labelling. The nanostructure behaves as a reversible logic circuit consisting of tandem YES and AND gates. Such reversible logic circuits integrated into functional nanodevices may guide future intelligent DNA nanorobots to manipulate cascade reactions in biological systems. PMID:25229207

Origins of Chaos in Autonomous Boolean Networks

NASA Astrophysics Data System (ADS)

Socolar, Joshua; Cavalcante, Hugo; Gauthier, Daniel; Zhang, Rui

2010-03-01

Networks with nodes consisting of ideal Boolean logic gates are known to display either steady states, periodic behavior, or an ultraviolet catastrophe where the number of logic-transition events circulating in the network per unit time grows as a power-law. In an experiment, non-ideal behavior of the logic gates prevents the ultraviolet catastrophe and may lead to deterministic chaos. We identify certain non-ideal features of real logic gates that enable chaos in experimental networks. We find that short-pulse rejection and the asymmetry between the logic states tends to engender periodic behavior. On the other hand, a memory effect termed ``degradation'' can generate chaos. Our results strongly suggest that deterministic chaos can be expected in a large class of experimental Boolean-like networks. Such devices may find application in a variety of technologies requiring fast complex waveforms or flat power spectra. The non-ideal effects identified here also have implications for the statistics of attractors in large complex networks.