The New ISD: Applying Cognitive Strategies to Instructional Design.

ERIC Educational Resources Information Center

Clark, Ruth Colvin

2002-01-01

Discusses cognitive models of instruction that can help develop new models of Instructional Systems Design (ISD) that include cognitive task analysis to identify mental models; constructive assumptions of learning; working memory and long-term memory; retrieval of new knowledge and skills from long-term memory; and support of metacognitive skills.…

Electronic shift register memory based on molecular electron-transfer reactions

NASA Technical Reports Server (NTRS)

Hopfield, J. J.; Onuchic, Jose Nelson; Beratan, David N.

1989-01-01

The design of a shift register memory at the molecular level is described in detail. The memory elements are based on a chain of electron-transfer molecules incorporated on a very large scale integrated (VLSI) substrate, and the information is shifted by photoinduced electron-transfer reactions. The design requirements for such a system are discussed, and several realistic strategies for synthesizing these systems are presented. The immediate advantage of such a hybrid molecular/VLSI device would arise from the possible information storage density. The prospect of considerable savings of energy per bit processed also exists. This molecular shift register memory element design solves the conceptual problems associated with integrating molecular size components with larger (micron) size features on a chip.

Memory Overview - Technologies and Needs

NASA Technical Reports Server (NTRS)

LaBel, Kenneth A.

2010-01-01

As NASA has evolved it's usage of spaceflight computing, memory applications have followed as well. In this talk, we will discuss the history of NASA's memories from magnetic core and tape recorders to current semiconductor approaches. We will briefly describe current functional memory usage in NASA space systems followed by a description of potential radiation-induced failure modes along with considerations for reliable system design.

Architectural design and simulation of a virtual memory

NASA Technical Reports Server (NTRS)

Kwok, G.; Chu, Y.

1971-01-01

Virtual memory is an imaginary main memory with a very large capacity which the programmer has at his disposal. It greatly contributes to the solution of the dynamic storage allocation problem. The architectural design of a virtual memory is presented which implements by hardware the idea of queuing and scheduling the page requests to a paging drum in such a way that the access of the paging drum is increased many times. With the design, an increase of up to 16 times in page transfer rate is achievable when the virtual memory is heavily loaded. This in turn makes feasible a great increase in the system throughput.

Fabrication and characterization of shape memory polymers at small-scales

NASA Astrophysics Data System (ADS)

Wornyo, Edem

The objective of this research is to thoroughly investigate the shape memory effect in polymers, characterize, and optimize these polymers for applications in information storage systems. Previous research effort in this field concentrated on shape memory metals for biomedical applications such as stents. Minimal work has been done on shape memory polymers; and the available work on shape memory polymers has not characterized the behaviors of this category of polymers fully. Copolymer shape memory materials based on diethylene glycol dimethacrylate (DEGDMA) crosslinker, and tert butyl acrylate (tBA) monomer are designed. The design encompasses a careful control of the backbone chemistry of the materials. Characterization methods such as dynamic mechanical analysis (DMA), differential scanning calorimetry (DSC); and novel nanoscale techniques such as atomic force microscopy (AFM), and nanoindentation are applied to this system of materials. Designed experiments are conducted on the materials to optimize spin coating conditions for thin films. Furthermore, the recovery, a key for the use of these polymeric materials for information storage, is examined in detail with respect to temperature. In sum, the overarching objectives of the proposed research are to: (i) Design shape memory polymers based on polyethylene glycol dimethacrylate (PEGDMA) and diethylene glycol dimethacrylate (DEGDMA) crosslinkers, 2-hydroxyethyl methacrylate (HEMA) and tert-butyl acrylate monomer (tBA). (ii) Utilize dynamic mechanical analysis (DMA) to comprehend the thermomechanical properties of shape memory polymers based on DEGDMA and tBA. (iii) Utilize nanoindentation and atomic force microscopy (AFM) to understand the nanoscale behavior of these SMPs, and explore the strain storage and recovery of the polymers from a deformed state. (iv) Study spin coating conditions on thin film quality with designed experiments. (iv) Apply neural networks and genetic algorithms to optimize these systems.

A class Hierarchical, object-oriented approach to virtual memory management

NASA Technical Reports Server (NTRS)

Russo, Vincent F.; Campbell, Roy H.; Johnston, Gary M.

1989-01-01

The Choices family of operating systems exploits class hierarchies and object-oriented programming to facilitate the construction of customized operating systems for shared memory and networked multiprocessors. The software is being used in the Tapestry laboratory to study the performance of algorithms, mechanisms, and policies for parallel systems. Described here are the architectural design and class hierarchy of the Choices virtual memory management system. The software and hardware mechanisms and policies of a virtual memory system implement a memory hierarchy that exploits the trade-off between response times and storage capacities. In Choices, the notion of a memory hierarchy is captured by abstract classes. Concrete subclasses of those abstractions implement a virtual address space, segmentation, paging, physical memory management, secondary storage, and remote (that is, networked) storage. Captured in the notion of a memory hierarchy are classes that represent memory objects. These classes provide a storage mechanism that contains encapsulated data and have methods to read or write the memory object. Each of these classes provides specializations to represent the memory hierarchy.

BLACKCOMB2: Hardware-software co-design for non-volatile memory in exascale systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mudge, Trevor

This work was part of a larger project, Blackcomb2, centered at Oak Ridge National Labs (Jeff Vetter PI) to investigate the opportunities for replacing or supplementing DRAM main memory with nonvolatile memory (NVmemory) in Exascale memory systems. The goal was to reduce the energy consumed by in future supercomputer memory systems and to improve their resiliency. Building on the accomplishments of the original Blackcomb Project, funded in 2010, the goal for Blackcomb2 was to identify, evaluate, and optimize the most promising emerging memory technologies, architecture hardware and software technologies, which are essential to provide the necessary memory capacity, performance, resilience,more » and energy efficiency in Exascale systems. Capacity and energy are the key drivers.« less

Research on memory management in embedded systems

NASA Astrophysics Data System (ADS)

Huang, Xian-ying; Yang, Wu

2005-12-01

Memory is a scarce resource in embedded system due to cost and size. Thus, applications in embedded systems cannot use memory randomly, such as in desktop applications. However, data and code must be stored into memory for running. The purpose of this paper is to save memory in developing embedded applications and guarantee running under limited memory conditions. Embedded systems often have small memory and are required to run a long time. Thus, a purpose of this study is to construct an allocator that can allocate memory effectively and bear a long-time running situation, reduce memory fragmentation and memory exhaustion. Memory fragmentation and exhaustion are related to the algorithm memory allocated. Static memory allocation cannot produce fragmentation. In this paper it is attempted to find an effective allocation algorithm dynamically, which can reduce memory fragmentation. Data is the critical part that ensures an application can run regularly, which takes up a large amount of memory. The amount of data that can be stored in the same size of memory is relevant with the selected data structure. Skills for designing application data in mobile phone are explained and discussed also.

Single-pass memory system evaluation for multiprogramming workloads

NASA Technical Reports Server (NTRS)

Conte, Thomas M.; Hwu, Wen-Mei W.

1990-01-01

Modern memory systems are composed of levels of cache memories, a virtual memory system, and a backing store. Varying more than a few design parameters and measuring the performance of such systems has traditionally be constrained by the high cost of simulation. Models of cache performance recently introduced reduce the cost simulation but at the expense of accuracy of performance prediction. Stack-based methods predict performance accurately using one pass over the trace for all cache sizes, but these techniques have been limited to fully-associative organizations. This paper presents a stack-based method of evaluating the performance of cache memories using a recurrence/conflict model for the miss ratio. Unlike previous work, the performance of realistic cache designs, such as direct-mapped caches, are predicted by the method. The method also includes a new approach to the problem of the effects of multiprogramming. This new technique separates the characteristics of the individual program from that of the workload. The recurrence/conflict method is shown to be practical, general, and powerful by comparing its performance to that of a popular traditional cache simulator. The authors expect that the availability of such a tool will have a large impact on future architectural studies of memory systems.

Modeling of a bubble-memory organization with self-checking translators to achieve high reliability.

NASA Technical Reports Server (NTRS)

Bouricius, W. G.; Carter, W. C.; Hsieh, E. P.; Wadia, A. B.; Jessep, D. C., Jr.

1973-01-01

Study of the design and modeling of a highly reliable bubble-memory system that has the capabilities of: (1) correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and (2) detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The results of the study justify the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability.

Simplified Interface to Complex Memory Hierarchies 1.x

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lang, Michael; Ionkov, Latchesar; Williams, Sean

2017-02-21

Memory systems are expected to get evermore complicated in the coming years, and it isn't clear exactly what form that complexity will take. On the software side, a simple, flexible way of identifying and working with memory pools is needed. Additionally, most developers seek code portability and do not want to learn the intricacies of complex memory. Hence, we believe that a library for interacting with complex memory systems should expose two kinds of abstraction: First, a low-level, mechanism-based interface designed for the runtime or advanced user that wants complete control, with its focus on simplified representation but with allmore » decisions left to the caller. Second, a high-level, policy-based interface designed for ease of use for the application developer, in which we aim for best-practice decisions based on application intent. We have developed such a library, called SICM: Simplified Interface to Complex Memory.« less

A room-temperature non-volatile CNT-based molecular memory cell

NASA Astrophysics Data System (ADS)

Ye, Senbin; Jing, Qingshen; Han, Ray P. S.

2013-04-01

Recent experiments with a carbon nanotube (CNT) system confirmed that the innertube can oscillate back-and-forth even under a room-temperature excitation. This demonstration of relative motion suggests that it is now feasible to build a CNT-based molecular memory cell (MC), and the key to bring the concept to reality is the precision control of the moving tube for sustained and reliable read/write (RW) operations. Here, we show that by using a 2-section outertube design, we are able to suitably recalibrate the system energetics and obtain the designed performance characteristics of a MC. Further, the resulting energy modification enables the MC to operate as a non-volatile memory element at room temperatures. Our paper explores a fundamental understanding of a MC and its response at the molecular level to roadmap a novel approach in memory technologies that can be harnessed to overcome the miniaturization limit and memory volatility in memory technologies.

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 2: Feasibility evaluation model

NASA Technical Reports Server (NTRS)

Horst, R. L.; Nordstrom, M. J.

1972-01-01

The partially populated oligatomic mass memory feasibility model is described and evaluated. A system was desired to verify the feasibility of the oligatomic (mirror) memory approach as applicable to large scale solid state mass memories.

Design and Implementation of a Basic Cross-Compiler and Virtual Memory Management System for the TI-59 Programmable Calculator.

DTIC Science & Technology

1983-06-01

previously stated requirements to construct the framework for a software soluticn. It is during this phase of design that lany cf the most critical...the linker would have to be deferred until the compiler was formalized and ir the implementation phase of design. The second problem involved...memory liait was encountered. At this point a segmentation occurred. The memory limits were reset and the combining process continued until another

A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S; Li, Dong

Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the architectural approaches proposed for designing memory systems and, specifically, caches with these emerging memory technologies. To highlight theirmore » similarities and differences, we present a classification of these technologies and architectural approaches based on their key characteristics. We also briefly summarize the challenges in using these technologies for architecting caches. We believe that this survey will help the readers gain insights into the emerging memory device technologies, and their potential use in designing future computing systems.« less

Optical read/write memory system components

NASA Technical Reports Server (NTRS)

Kozma, A.

1972-01-01

The optical components of a breadboard holographic read/write memory system have been fabricated and the parameters specified of the major system components: (1) a laser system; (2) an x-y beam deflector; (3) a block data composer; (4) the read/write memory material; (5) an output detector array; and (6) the electronics to drive, synchronize, and control all system components. The objectives of the investigation were divided into three concurrent phases: (1) to supply and fabricate the major components according to the previously established specifications; (2) to prepare computer programs to simulate the entire holographic memory system so that a designer can balance the requirements on the various components; and (3) to conduct a development program to optimize the combined recording and reconstruction process of the high density holographic memory system.

Living Design Memory: Framework, Implementation, Lessons Learned.

ERIC Educational Resources Information Center

Terveen, Loren G.; And Others

1995-01-01

Discusses large-scale software development and describes the development of the Designer Assistant to improve software development effectiveness. Highlights include the knowledge management problem; related work, including artificial intelligence and expert systems, software process modeling research, and other approaches to organizational memory;…

A 1-Gigabit Memory System on a multi-Chip Module for Space Applications

NASA Technical Reports Server (NTRS)

Louie, Marianne E.; Topliffe, Douglas A.; Alkalai, Leon

1996-01-01

Current spaceborne applications desire compact, low weight, and high capacity data storage systems along with the additional requirement of radiation tolerance. This paper discusses a memory system on a multi-chip module (MCM) that is designed for space applications.

Weather prediction using a genetic memory

NASA Technical Reports Server (NTRS)

Rogers, David

1990-01-01

Kanaerva's sparse distributed memory (SDM) is an associative memory model based on the mathematical properties of high dimensional binary address spaces. Holland's genetic algorithms are a search technique for high dimensional spaces inspired by evolutional processes of DNA. Genetic Memory is a hybrid of the above two systems, in which the memory uses a genetic algorithm to dynamically reconfigure its physical storage locations to reflect correlations between the stored addresses and data. This architecture is designed to maximize the ability of the system to scale-up to handle real world problems.

Analysis of memory use for improved design and compile-time allocation of local memory

NASA Technical Reports Server (NTRS)

Mcniven, Geoffrey D.; Davidson, Edward S.

1986-01-01

Trace analysis techniques are used to study memory referencing behavior for the purpose of designing local memories and determining how to allocate them for data and instructions. In an attempt to assess the inherent behavior of the source code, the trace analysis system described here reduced the effects of the compiler and host architecture on the trace by using a technical called flattening. The variables in the trace, their associated single-assignment values, and references are histogrammed on the basis of various parameters describing memory referencing behavior. Bounds are developed specifying the amount of memory space required to store all live values in a particular histogram class. The reduction achieved in main memory traffic by allocating local memory is specified for each class.

Updated optical read/write memory system components

NASA Technical Reports Server (NTRS)

1973-01-01

The fabrication of an updated block data composer and holographic storage array for a breadboard holographic read/write memory system is described. System considerations such as transform optics and controlled aberration lens design are described along with the block data composer, photoplastic recording materials, and material development.

PDA: A coupling of knowledge and memory for case-based reasoning

NASA Technical Reports Server (NTRS)

Bharwani, S.; Walls, J.; Blevins, E.

1988-01-01

Problem solving in most domains requires reference to past knowledge and experience whether such knowledge is represented as rules, decision trees, networks or any variant of attributed graphs. Regardless of the representational form employed, designers of expert systems rarely make a distinction between the static and dynamic aspects of the system's knowledge base. The current paper clearly distinguishes between knowledge-based and memory-based reasoning where the former in its most pure sense is characterized by a static knowledge based resulting in a relatively brittle expert system while the latter is dynamic and analogous to the functions of human memory which learns from experience. The paper discusses the design of an advisory system which combines a knowledge base consisting of domain vocabulary and default dependencies between concepts with a dynamic conceptual memory which stores experimental knowledge in the form of cases. The case memory organizes past experience in the form of MOPs (memory organization packets) and sub-MOPs. Each MOP consists of a context frame and a set of indices. The context frame contains information about the features (norms) common to all the events and sub-MOPs indexed under it.

Collective input/output under memory constraints

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Yin; Chen, Yong; Zhuang, Yu

2014-12-18

Compared with current high-performance computing (HPC) systems, exascale systems are expected to have much less memory per node, which can significantly reduce necessary collective input/output (I/O) performance. In this study, we introduce a memory-conscious collective I/O strategy that takes into account memory capacity and bandwidth constraints. The new strategy restricts aggregation data traffic within disjointed subgroups, coordinates I/O accesses in intranode and internode layers, and determines I/O aggregators at run time considering memory consumption among processes. We have prototyped the design and evaluated it with commonly used benchmarks to verify its potential. The evaluation results demonstrate that this strategy holdsmore » promise in mitigating the memory pressure, alleviating the contention for memory bandwidth, and improving the I/O performance for projected extreme-scale systems. Given the importance of supporting increasingly data-intensive workloads and projected memory constraints on increasingly larger scale HPC systems, this new memory-conscious collective I/O can have a significant positive impact on scientific discovery productivity.« less

Design structure for in-system redundant array repair in integrated circuits

DOEpatents

Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

2008-11-25

A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Experimental evaluation of shape memory alloy actuation technique in adaptive antenna design concepts

NASA Astrophysics Data System (ADS)

Kefauver, W. Neill; Carpenter, Bernie F.

1994-09-01

Creation of an antenna system that could autonomously adapt contours of reflecting surfaces to compensate for structural loads induced by a variable environment would maximize performance of space-based communication systems. Design of such a system requires the comprehensive development and integration of advanced actuator, sensor, and control technologies. As an initial step in this process, a test has been performed to assess the use of a shape memory alloy as a potential actuation technique. For this test, an existing, offset, cassegrain antenna system was retrofit with a subreflector equipped with shape memory alloy actuators for surface contour control. The impacts that the actuators had on both the subreflector contour and the antenna system patterns were measured. The results of this study indicate the potential for using shape memory alloy actuation techniques to adaptively control antenna performance; both variations in gain and beam steering capabilities were demonstrated. Future development effort is required to evolve this potential into a useful technology for satellite applications.

Experimental evaluation of shape memory alloy actuation technique in adaptive antenna design concepts

NASA Technical Reports Server (NTRS)

Kefauver, W. Neill; Carpenter, Bernie F.

1994-01-01

Creation of an antenna system that could autonomously adapt contours of reflecting surfaces to compensate for structural loads induced by a variable environment would maximize performance of space-based communication systems. Design of such a system requires the comprehensive development and integration of advanced actuator, sensor, and control technologies. As an initial step in this process, a test has been performed to assess the use of a shape memory alloy as a potential actuation technique. For this test, an existing, offset, cassegrain antenna system was retrofit with a subreflector equipped with shape memory alloy actuators for surface contour control. The impacts that the actuators had on both the subreflector contour and the antenna system patterns were measured. The results of this study indicate the potential for using shape memory alloy actuation techniques to adaptively control antenna performance; both variations in gain and beam steering capabilities were demonstrated. Future development effort is required to evolve this potential into a useful technology for satellite applications.

Plated wire memory subsystem

NASA Technical Reports Server (NTRS)

Carpenter, K. H.

1974-01-01

The design, construction, and test history of a 4096 word by 18 bit random access NDRO Plated Wire Memory for use in conjunction with a spacecraft input/output and central processing unit is reported. A technical and functional description is given along with diagrams illustrating layout and systems operation. Test data is shown on the procedures and results of system level and memory stack testing, and hybrid circuit screening. A comparison of the most significant physical and performance characteristics of the memory unit versus the specified requirements is also included.

Computer memory management system

DOEpatents

Kirk, III, Whitson John

2002-01-01

A computer memory management system utilizing a memory structure system of "intelligent" pointers in which information related to the use status of the memory structure is designed into the pointer. Through this pointer system, The present invention provides essentially automatic memory management (often referred to as garbage collection) by allowing relationships between objects to have definite memory management behavior by use of coding protocol which describes when relationships should be maintained and when the relationships should be broken. In one aspect, the present invention system allows automatic breaking of strong links to facilitate object garbage collection, coupled with relationship adjectives which define deletion of associated objects. In another aspect, The present invention includes simple-to-use infinite undo/redo functionality in that it has the capability, through a simple function call, to undo all of the changes made to a data model since the previous `valid state` was noted.

Design and construction of a double inversion recombination switch for heritable sequential genetic memory.

PubMed

Ham, Timothy S; Lee, Sung K; Keasling, Jay D; Arkin, Adam P

2008-07-30

Inversion recombination elements present unique opportunities for computing and information encoding in biological systems. They provide distinct binary states that are encoded into the DNA sequence itself, allowing us to overcome limitations posed by other biological memory or logic gate systems. Further, it is in theory possible to create complex sequential logics by careful positioning of recombinase recognition sites in the sequence. In this work, we describe the design and synthesis of an inversion switch using the fim and hin inversion recombination systems to create a heritable sequential memory switch. We have integrated the two inversion systems in an overlapping manner, creating a switch that can have multiple states. The switch is capable of transitioning from state to state in a manner analogous to a finite state machine, while encoding the state information into DNA. This switch does not require protein expression to maintain its state, and "remembers" its state even upon cell death. We were able to demonstrate transition into three out of the five possible states showing the feasibility of such a switch. We demonstrate that a heritable memory system that encodes its state into DNA is possible, and that inversion recombination system could be a starting point for more complex memory circuits. Although the circuit did not fully behave as expected, we showed that a multi-state, temporal memory is achievable.

Design and Construction of a Double Inversion Recombination Switch for Heritable Sequential Genetic Memory

PubMed Central

Ham, Timothy S.; Lee, Sung K.; Keasling, Jay D.; Arkin, Adam P.

2008-01-01

Background Inversion recombination elements present unique opportunities for computing and information encoding in biological systems. They provide distinct binary states that are encoded into the DNA sequence itself, allowing us to overcome limitations posed by other biological memory or logic gate systems. Further, it is in theory possible to create complex sequential logics by careful positioning of recombinase recognition sites in the sequence. Methodology/Principal Findings In this work, we describe the design and synthesis of an inversion switch using the fim and hin inversion recombination systems to create a heritable sequential memory switch. We have integrated the two inversion systems in an overlapping manner, creating a switch that can have multiple states. The switch is capable of transitioning from state to state in a manner analogous to a finite state machine, while encoding the state information into DNA. This switch does not require protein expression to maintain its state, and “remembers” its state even upon cell death. We were able to demonstrate transition into three out of the five possible states showing the feasibility of such a switch. Conclusions/Significance We demonstrate that a heritable memory system that encodes its state into DNA is possible, and that inversion recombination system could be a starting point for more complex memory circuits. Although the circuit did not fully behave as expected, we showed that a multi-state, temporal memory is achievable. PMID:18665232

Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor

NASA Astrophysics Data System (ADS)

González, Diego; Botella, Guillermo; García, Carlos; Prieto, Manuel; Tirado, Francisco

2013-12-01

This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor.

Low-density parity-check codes for volume holographic memory systems.

PubMed

Pishro-Nik, Hossein; Rahnavard, Nazanin; Ha, Jeongseok; Fekri, Faramarz; Adibi, Ali

2003-02-10

We investigate the application of low-density parity-check (LDPC) codes in volume holographic memory (VHM) systems. We show that a carefully designed irregular LDPC code has a very good performance in VHM systems. We optimize high-rate LDPC codes for the nonuniform error pattern in holographic memories to reduce the bit error rate extensively. The prior knowledge of noise distribution is used for designing as well as decoding the LDPC codes. We show that these codes have a superior performance to that of Reed-Solomon (RS) codes and regular LDPC counterparts. Our simulation shows that we can increase the maximum storage capacity of holographic memories by more than 50 percent if we use irregular LDPC codes with soft-decision decoding instead of conventionally employed RS codes with hard-decision decoding. The performance of these LDPC codes is close to the information theoretic capacity.

C-MOS array design techniques: SUMC multiprocessor system study

NASA Technical Reports Server (NTRS)

Clapp, W. A.; Helbig, W. A.; Merriam, A. S.

1972-01-01

The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.

Music and Video Gaming during Breaks: Influence on Habitual versus Goal-Directed Decision Making.

PubMed

Liu, Shuyan; Schad, Daniel J; Kuschpel, Maxim S; Rapp, Michael A; Heinz, Andreas

2016-01-01

Different systems for habitual versus goal-directed control are thought to underlie human decision-making. Working memory is known to shape these decision-making systems and their interplay, and is known to support goal-directed decision making even under stress. Here, we investigated if and how decision systems are differentially influenced by breaks filled with diverse everyday life activities known to modulate working memory performance. We used a within-subject design where young adults listened to music and played a video game during breaks interleaved with trials of a sequential two-step Markov decision task, designed to assess habitual as well as goal-directed decision making. Based on a neurocomputational model of task performance, we observed that for individuals with a rather limited working memory capacity video gaming as compared to music reduced reliance on the goal-directed decision-making system, while a rather large working memory capacity prevented such a decline. Our findings suggest differential effects of everyday activities on key decision-making processes.

Music and Video Gaming during Breaks: Influence on Habitual versus Goal-Directed Decision Making

PubMed Central

Kuschpel, Maxim S.; Rapp, Michael A.; Heinz, Andreas

2016-01-01

Different systems for habitual versus goal-directed control are thought to underlie human decision-making. Working memory is known to shape these decision-making systems and their interplay, and is known to support goal-directed decision making even under stress. Here, we investigated if and how decision systems are differentially influenced by breaks filled with diverse everyday life activities known to modulate working memory performance. We used a within-subject design where young adults listened to music and played a video game during breaks interleaved with trials of a sequential two-step Markov decision task, designed to assess habitual as well as goal-directed decision making. Based on a neurocomputational model of task performance, we observed that for individuals with a rather limited working memory capacity video gaming as compared to music reduced reliance on the goal-directed decision-making system, while a rather large working memory capacity prevented such a decline. Our findings suggest differential effects of everyday activities on key decision-making processes. PMID:26982326

A design study of a signal detection system. [for search of extraterrestrial radio sources

NASA Technical Reports Server (NTRS)

Healy, T. J.

1980-01-01

A system is described which can aid in the search for radio signals from extraterrestrial sources, or in other applications characterized by low signal-to-noise ratios and very high data rates. The system follows a multichannel (16 million bin) spectrum analyzer, and has critical processing, system control, and memory fuctions. The design includes a moderately rich set of algorithms to be used in parallel to detect signals of unknown form. A multi-threshold approach is used to obtain high and low signal sensitivities. Relatively compact and transportable memory systems are specified.

Processing-in-Memory Enabled Graphics Processors for 3D Rendering

DOE Office of Scientific and Technical Information (OSTI.GOV)

Xie, Chenhao; Song, Shuaiwen; Wang, Jing

2017-02-06

The performance of 3D rendering of Graphics Processing Unit that convents 3D vector stream into 2D frame with 3D image effects significantly impact users’ gaming experience on modern computer systems. Due to the high texture throughput in 3D rendering, main memory bandwidth becomes a critical obstacle for improving the overall rendering performance. 3D stacked memory systems such as Hybrid Memory Cube (HMC) provide opportunities to significantly overcome the memory wall by directly connecting logic controllers to DRAM dies. Based on the observation that texel fetches significantly impact off-chip memory traffic, we propose two architectural designs to enable Processing-In-Memory based GPUmore » for efficient 3D rendering.« less

Tracking the Time-Dependent Role of the Hippocampus in Memory Recall Using DREADDs.

PubMed

Varela, Carmen; Weiss, Sarah; Meyer, Retsina; Halassa, Michael; Biedenkapp, Joseph; Wilson, Matthew A; Goosens, Ki Ann; Bendor, Daniel

2016-01-01

The hippocampus is critical for the storage of new autobiographical experiences as memories. Following an initial encoding stage in the hippocampus, memories undergo a process of systems-level consolidation, which leads to greater stability through time and an increased reliance on neocortical areas for retrieval. The extent to which the retrieval of these consolidated memories still requires the hippocampus is unclear, as both spared and severely degraded remote memory recall have been reported following post-training hippocampal lesions. One difficulty in definitively addressing the role of the hippocampus in remote memory retrieval is the precision with which the entire volume of the hippocampal region can be inactivated. To address this issue, we used Designer Receptors Exclusively Activated by Designer Drugs (DREADDs), a chemical-genetic tool capable of highly specific neuronal manipulation over large volumes of brain tissue. We find that remote (>7 weeks after acquisition), but not recent (1-2 days after acquisition) contextual fear memories can be recalled after injection of the DREADD agonist (CNO) in animals expressing the inhibitory DREADD in the entire hippocampus. Our data demonstrate a time-dependent role of the hippocampus in memory retrieval, supporting the standard model of systems consolidation.

Tracking the Time-Dependent Role of the Hippocampus in Memory Recall Using DREADDs

PubMed Central

Varela, Carmen; Weiss, Sarah; Meyer, Retsina; Halassa, Michael; Biedenkapp, Joseph; Wilson, Matthew A.; Goosens, Ki Ann

2016-01-01

The hippocampus is critical for the storage of new autobiographical experiences as memories. Following an initial encoding stage in the hippocampus, memories undergo a process of systems-level consolidation, which leads to greater stability through time and an increased reliance on neocortical areas for retrieval. The extent to which the retrieval of these consolidated memories still requires the hippocampus is unclear, as both spared and severely degraded remote memory recall have been reported following post-training hippocampal lesions. One difficulty in definitively addressing the role of the hippocampus in remote memory retrieval is the precision with which the entire volume of the hippocampal region can be inactivated. To address this issue, we used Designer Receptors Exclusively Activated by Designer Drugs (DREADDs), a chemical-genetic tool capable of highly specific neuronal manipulation over large volumes of brain tissue. We find that remote (>7 weeks after acquisition), but not recent (1–2 days after acquisition) contextual fear memories can be recalled after injection of the DREADD agonist (CNO) in animals expressing the inhibitory DREADD in the entire hippocampus. Our data demonstrate a time-dependent role of the hippocampus in memory retrieval, supporting the standard model of systems consolidation. PMID:27145133

Developmental amnesia: Fractionation of developing memory systems.

PubMed

Temple, Christine M; Richardson, Paul

2006-07-01

Study of the developmental amnesias utilizing a cognitive neuropsychological methodology has highlighted the dissociations that may occur between the development of components of memory. M.M., a new case of developmental amnesia, was identified after screening from the normal population on cognitive and memory measures. Retrospective investigation found that he was of low birthweight. M.M. had impaired semantic memory for knowledge of facts and words. There was impaired episodic memory for words and stories but intact episodic memory for visual designs and features. This forms a double dissociation with Dr S. (Temple, 1992), who had intact verbal but impaired visual episodic memory. M.M. also had impaired autobiographical episodic memory. Nevertheless, learning over repeated trials occurred, consistent with previous theorizing that learning is not simply the effect of recurrent episodic memory. Nor is it the same as establishing semantic memory, since for M.M. semantic memory is also impaired. Within reading, there was an impaired lexico-semantic system, elevated levels of homophone confusion, but intact phonological reading, consistent with surface dyslexia and raising issues about the interrelationship of the semantic system and literacy development. The results are compatible with discrete semi-independent components within memory development, whereby deficits are associated with residual normality, but there may also be an explicit relationship between the semantic memory system and both vocabulary and reading acquisition.

A behavioral rehabilitation intervention for amnestic Mild Cognitive Impairment

PubMed Central

Greenaway, Melanie C.; Hanna, Sherrie M.; Lepore, Susan W.; Smith, Glenn E.

2010-01-01

Individuals with amnestic Mild Cognitive Impairment (MCI) currently have few treatment options for combating their memory loss. The Memory Support System (MSS) is a calendar and organization system with accompanying 6-week curriculum designed for individuals with progressive memory impairment. Ability to learn the MSS and its utility were assessed in 20 participants. Participants were significantly more likely to successfully use the calendar system after training. Ninety-five percent were compliant with the MSS at training completion, and 89% continued to be compliant at follow-up. Outcome measures revealed a medium effect size for improvement in functional ability. Subjects further reported improved independence, self-confidence, and mood. This initial examination of the MSS suggests that with appropriate training, individuals with amnestic MCI can and will use a memory notebook system to help compensate for memory loss. These results are encouraging that the MSS may help with the symptoms of memory decline in MCI. PMID:18955724

Expert Systems on Multiprocessor Architectures. Volume 2. Technical Reports

DTIC Science & Technology

1991-06-01

Report RC 12936 (#58037). IBM T. J. Wartson Reiearch Center. July 1987. � Alan Jay Smith. Cache memories. Coniputing Sitrry., 1.1(3): I.3-5:30...basic-shared is an instrument for ashared memory design. The components panels are processor- qload-scrolling-bar-panel, memory-qload-scrolling-bar-panel

Automatic multi-banking of memory for microprocessors

NASA Technical Reports Server (NTRS)

Wiker, G. A. (Inventor)

1984-01-01

A microprocessor system is provided with added memories to expand its address spaces beyond its address word length capacity by using indirect addressing instructions of a type having a detectable operations code and dedicating designated address spaces of memory to each of the added memories, one space to a memory. By decoding each operations code of instructions read from main memory into a decoder to identify indirect addressing instructions of the specified type, and then decoding the address that follows in a decoder to determine which added memory is associated therewith, the associated added memory is selectively enabled through a unit while the main memory is disabled to permit the instruction to be executed on the location to which the effective address of the indirect address instruction points, either before the indirect address is read from main memory or afterwards, depending on how the system is arranged by a switch.

Application of source biasing technique for energy efficient DECODER circuit design: memory array application

NASA Astrophysics Data System (ADS)

Gupta, Neha; Parihar, Priyanka; Neema, Vaibhav

2018-04-01

Researchers have proposed many circuit techniques to reduce leakage power dissipation in memory cells. If we want to reduce the overall power in the memory system, we have to work on the input circuitry of memory architecture i.e. row and column decoder. In this research work, low leakage power with a high speed row and column decoder for memory array application is designed and four new techniques are proposed. In this work, the comparison of cluster DECODER, body bias DECODER, source bias DECODER, and source coupling DECODER are designed and analyzed for memory array application. Simulation is performed for the comparative analysis of different DECODER design parameters at 180 nm GPDK technology file using the CADENCE tool. Simulation results show that the proposed source bias DECODER circuit technique decreases the leakage current by 99.92% and static energy by 99.92% at a supply voltage of 1.2 V. The proposed circuit also improves dynamic power dissipation by 5.69%, dynamic PDP/EDP 65.03% and delay 57.25% at 1.2 V supply voltage.

Hybrid associative memory using an incoherent correlation system

NASA Astrophysics Data System (ADS)

Taniguchi, Masaki; Ichioka, Yoshiki; Matsuoka, Katsunori

1990-10-01

A hybrid heteroassociative memory is presented that uses an incoherent system in which two correlators and a nonlinear element form a nonlinear feedback system. This system can recall any pattern from an input pattern without cross-talk or ghosts by properly designing a pair of filters installed in the correlators. Experiments on a simple hybrid system were performed to ensure the operation of the system and to demonstrate the usefulness of this proposed system.

Unorganized Cognitive Structures of Illiterate as the Key Factor in Rural E-Learning Design

ERIC Educational Resources Information Center

Katre, Dinesh S.

2006-01-01

Cognitive Structures and Linguistic Sequential Memory or Memory of Serial Order are not very well developed among illiterate people contrary to educated people. It affects the comprehension of abstract ideas and the usability of the system. Therefore the cognitive limitations of illiterate must be considered for instructional design and user…

Multiple-User, Multitasking, Virtual-Memory Computer System

NASA Technical Reports Server (NTRS)

Generazio, Edward R.; Roth, Don J.; Stang, David B.

1993-01-01

Computer system designed and programmed to serve multiple users in research laboratory. Provides for computer control and monitoring of laboratory instruments, acquisition and anlaysis of data from those instruments, and interaction with users via remote terminals. System provides fast access to shared central processing units and associated large (from megabytes to gigabytes) memories. Underlying concept of system also applicable to monitoring and control of industrial processes.

Co-design of application software and NAND flash memory in solid-state drive for relational database storage system

NASA Astrophysics Data System (ADS)

Miyaji, Kousuke; Sun, Chao; Soga, Ayumi; Takeuchi, Ken

2014-01-01

A relational database management system (RDBMS) is designed based on NAND flash solid-state drive (SSD) for storage. By vertically integrating the storage engine (SE) and the flash translation layer (FTL), system performance is maximized and the internal SSD overhead is minimized. The proposed RDBMS SE utilizes physical information about the NAND flash memory which is supplied from the FTL. The query operation is also optimized for SSD. By these treatments, page-copy-less garbage collection is achieved and data fragmentation in the NAND flash memory is suppressed. As a result, RDBMS performance increases by 3.8 times, power consumption of SSD decreases by 46% and SSD life time is increased by 61%. The effectiveness of the proposed scheme increases with larger erase block sizes, which matches the future scaling trend of three-dimensional (3D-) NAND flash memories. The preferable row data size of the proposed scheme is below 500 byte for 16 kbyte page size.

The relationships between memory systems and sleep stages.

PubMed

Rauchs, Géraldine; Desgranges, Béatrice; Foret, Jean; Eustache, Francis

2005-06-01

Sleep function remains elusive despite our rapidly increasing comprehension of the processes generating and maintaining the different sleep stages. Several lines of evidence support the hypothesis that sleep is involved in the off-line reprocessing of recently-acquired memories. In this review, we summarize the main results obtained in the field of sleep and memory consolidation in both animals and humans, and try to connect sleep stages with the different memory systems. To this end, we have collated data obtained using several methodological approaches, including electrophysiological recordings of neuronal ensembles, post-training modifications of sleep architecture, sleep deprivation and functional neuroimaging studies. Broadly speaking, all the various studies emphasize the fact that the four long-term memory systems (procedural memory, perceptual representation system, semantic and episodic memory, according to Tulving's SPI model; Tulving, 1995) benefit either from non-rapid eye movement (NREM) (not just SWS) or rapid eye movement (REM) sleep, or from both sleep stages. Tulving's classification of memory systems appears more pertinent than the declarative/non-declarative dichotomy when it comes to understanding the role of sleep in memory. Indeed, this model allows us to resolve several contradictions, notably the fact that episodic and semantic memory (the two memory systems encompassed in declarative memory) appear to rely on different sleep stages. Likewise, this model provides an explanation for why the acquisition of various types of skills (perceptual-motor, sensory-perceptual and cognitive skills) and priming effects, subserved by different brain structures but all designated by the generic term of implicit or non-declarative memory, may not benefit from the same sleep stages.

Spacecraft optical disk recorder memory buffer control

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1993-01-01

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

Apollo guidance, navigation and control: Guidance system operations plans for manned LM earth orbital and lunar missions using Program COLOSSUS 3. Section 7: Erasable memory programs

NASA Technical Reports Server (NTRS)

Hamilton, M. H.

1972-01-01

Erasable-memory programs (EMPs) designed for the guidance computers used in the command (CMC) and lunar modules (LGC) are described. CMC programs are designated COLOSSUS 3, and the associated EMPs are identified by a three-digit number beginning with 5. LGC programs are designated LUMINARY 1E, and the associated EMPs are identified, with one exception, by a three-digit number beginning with 1. The exception is EMP 99. The EMPs vary in complexity from a simple flagbit setting to a long and intricate logical structure. They all, however, cause the computer to behave in a way not intended in the original design of the programs; they accomplish this off-nominal behavior by some alteration of erasable memory to interface with existing fixed-memory programs to effect a desired result.

Scripting for Construction of a Transactive Memory System in Multidisciplinary CSCL Environments

ERIC Educational Resources Information Center

Noroozi, Omid; Biemans, Harm J. A.; Weinberger, Armin; Mulder, Martin; Chizari, Mohammad

2013-01-01

Establishing a Transactive Memory System (TMS) is essential for groups of learners, when they are multidisciplinary and collaborate online. Environments for Computer-Supported Collaborative Learning (CSCL) could be designed to facilitate the TMS. This study investigates how various aspects of a TMS (i.e., specialization, coordination, and trust)…

Two Unipolar Terminal-Attractor-Based Associative Memories

NASA Technical Reports Server (NTRS)

Liu, Hua-Kuang; Wu, Chwan-Hwa

1995-01-01

Two unipolar mathematical models of electronic neural network functioning as terminal-attractor-based associative memory (TABAM) developed. Models comprise sets of equations describing interactions between time-varying inputs and outputs of neural-network memory, regarded as dynamical system. Simplifies design and operation of optoelectronic processor to implement TABAM performing associative recall of images. TABAM concept described in "Optoelectronic Terminal-Attractor-Based Associative Memory" (NPO-18790). Experimental optoelectronic apparatus that performed associative recall of binary images described in "Optoelectronic Inner-Product Neural Associative Memory" (NPO-18491).

Research about Memory Detection Based on the Embedded Platform

NASA Astrophysics Data System (ADS)

Sun, Hao; Chu, Jian

As is known to us all, the resources of memory detection of the embedded systems are very limited. Taking the Linux-based embedded arm as platform, this article puts forward two efficient memory detection technologies according to the characteristics of the embedded software. Especially for the programs which need specific libraries, the article puts forwards portable memory detection methods to help program designers to reduce human errors,improve programming quality and therefore make better use of the valuable embedded memory resource.

Rambrain - a library for virtually extending physical memory

NASA Astrophysics Data System (ADS)

Imgrund, Maximilian; Arth, Alexander

2017-08-01

We introduce Rambrain, a user space library that manages memory consumption of your code. Using Rambrain you can overcommit memory over the size of physical memory present in the system. Rambrain takes care of temporarily swapping out data to disk and can handle multiples of the physical memory size present. Rambrain is thread-safe, OpenMP and MPI compatible and supports Asynchronous IO. The library was designed to require minimal changes to existing programs and to be easy to use.

A FPGA-based Measurement System for Nonvolatile Semiconductor Memory Characterization

NASA Astrophysics Data System (ADS)

Bu, Jiankang; White, Marvin

2002-03-01

Low voltage, long retention, high density SONOS nonvolatile semiconductor memory (NVSM) devices are ideally suited for PCMCIA, FLASH and 'smart' cards. The SONOS memory transistor requires characterization with an accurate, rapid measurement system with minimum disturbance to the device. The FPGA-based measurement system includes three parts: 1) a pattern generator implemented with XILINX FPGAs and corresponding software, 2) a high-speed, constant-current, threshold voltage detection circuit, 3) and a data evaluation program, implemented with a LABVIEW program. Fig. 1 shows the general block diagram of the FPGA-based measurement system. The function generator is designed and simulated with XILINX Foundation Software. Under the control of the specific erase/write/read pulses, the analog detect circuit applies operational modes to the SONOS device under test (DUT) and determines the change of the memory-state of the SONOS nonvolatile memory transistor. The TEK460 digitizes the analog threshold voltage output and sends to the PC computer. The data is filtered and averaged with a LABVIEWTM program running on the PC computer and displayed on the monitor in real time. We have implemented the pattern generator with XILINX FPGAs. Fig. 2 shows the block diagram of the pattern generator. We realized the logic control by a method of state machine design. Fig. 3 shows a small part of the state machine. The flexibility of the FPGAs enhances the capabilities of this system and allows measurement variations without hardware changes. The characterization of the nonvolatile memory transistor device under test (DUT), as function of programming voltage and time, is achieved by a high-speed, constant-current threshold voltage detection circuit. The analog detection circuit incorporating fast analog switches controlled digitally with the FPGAs. The schematic circuit diagram is shown in Fig. 4. The various operational modes for the DUT are realized with control signals applied to the analog switches (SW) as shown in Fig. 5. A LABVIEWTM program, on a PC platform, collects and processes the data. The data is displayed on the monitor in real time. This time-domain filtering reduces the digitizing error. Fig. 6 shows the data processing. SONOS nonvolatile semiconductor memories are characterized by erase/write, retention and endurance measurements. Fig. 7 shows the erase/write characteristics of an n-Channel, 5V prog-rammable SONOS memory transistor. Fig.8 shows the retention characteristic of the same SONOS transistor. We have used this system to characterize SONOS nonvolatile semiconductor memory transistors. The attractive features of the test system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast read-out of memory state, low power, high precision determination of the device threshold voltage, and perhaps most importantly, minimum disturbance, which is indispensable for nonvolatile memory characterization.

Virtual data

NASA Astrophysics Data System (ADS)

Bjorklund, E.

1994-12-01

In the 1970s, when computers were memory limited, operating system designers created the concept of "virtual memory", which gave users the ability to address more memory than physically existed. In the 1990s, many large control systems have the potential of becoming data limited. We propose that many of the principles behind virtual memory systems (working sets, locality, caching and clustering) can also be applied to data-limited systems, creating, in effect, "virtual data systems". At the Los Alamos National Laboratory's Clinton P. Anderson Meson Physics Facility (LAMPF), we have applied these principles to a moderately sized (10 000 data points) data acquisition and control system. To test the principles, we measured the system's performance during tune-up, production, and maintenance periods. In this paper, we present a general discussion of the principles of a virtual data system along with some discussion of our own implementation and the results of our performance measurements.

Dynamism in Electronic Performance Support Systems.

ERIC Educational Resources Information Center

Laffey, James

1995-01-01

Describes a model for dynamic electronic performance support systems based on NNAble, a system developed by the training group at Apple Computer. Principles for designing dynamic performance support are discussed, including a systems approach, performer-centered design, awareness of situated cognition, organizational memory, and technology use.…

An ASIC memory buffer controller for a high speed disk system

NASA Technical Reports Server (NTRS)

Hodson, Robert F.; Campbell, Steve

1993-01-01

The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

ICE System: Interruptible control expert system. M.S. Thesis

NASA Technical Reports Server (NTRS)

Vezina, James M.

1990-01-01

The Interruptible Control Expert (ICE) System is based on an architecture designed to provide a strong foundation for real-time production rule expert systems. Three principles are adopted to guide the development of ICE. A practical delivery platform must be provided, no specialized hardware can be used to solve deficiencies in the software design. Knowledge of the environment and the rule-base is exploited to improve the performance of a delivered system. The third principle of ICE is to respond to the most critical event, at the expense of the more trivial tasks. Minimal time is spent on classifying the potential importance of environmental events with the majority of the time used for finding the responses. A feature of the system, derived from all three principles, is the lack of working memory. By using a priori information, a fixed amount of memory can be specified for the hardware platform. The absence of working memory removes the dangers of garbage collection during the continuous operation of the controller.

Data Movement Dominates: Final Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jacob, Bruce L.

Over the past three years in this project, what we have observed is that the primary reason for data movement in large-scale systems is that the per-node capacity is not large enough—i.e., one of the solutions to the data-movement problem (certainly not the only solution that is required, but a significant one nonetheless) is to increase per-node capacity so that inter-node traffic is reduced. This unfortunately is not as simple as it sounds. Today’s main memory systems for datacenters, enterprise computing systems, and supercomputers, fail to provide high per-socket capacity [Dirik & Jacob 2009; Cooper-Balis et al. 2012], except atmore » extremely high price points (factors of 10–100x the cost/bit of consumer main-memory systems) [Stokes 2008]. The reason is that our choice of technology for today’s main memory systems—i.e., DRAM, which we have used as a main-memory technology since the 1970s [Jacob et al. 2007]—can no longer keep up with our needs for density and price per bit. Main memory systems have always been built from the cheapest, densest, lowest-power memory technology available, and DRAM is no longer the cheapest, the densest, nor the lowest-power storage technology out there. It is now time for DRAM to go the way that SRAM went: move out of the way for a cheaper, slower, denser storage technology, and become a cache instead. This inflection point has happened before, in the context of SRAM yielding to DRAM. There was once a time that SRAM was the storage technology of choice for all main memories [Tomasulo 1967; Thornton 1970; Kidder 1981]. However, once DRAM hit volume production in the 1970s and 80s, it supplanted SRAM as a main memory technology because it was cheaper, and it was denser. It also happened to be lower power, but that was not the primary consideration of the day. At the time, it was recognized that DRAM was much slower than SRAM, but it was only at the supercomputer level (For instance the Cray X-MP in the 1980s and its follow-on, the Cray Y-MP, in the 1990s) that could one afford to build ever- larger main memories out of SRAM—the reasoning for moving to DRAM was that an appropriately designed memory hierarchy, built of DRAM as main memory and SRAM as a cache, would approach the performance of SRAM, at the price-per-bit of DRAM [Mashey 1999]. Today it is quite clear that, were one to build an entire multi-gigabyte main memory out of SRAM instead of DRAM, one could improve the performance of almost any computer system by up to an order of magnitude—but this option is not even considered, because to build that system would be prohibitively expensive. It is now time to revisit the same design choice in the context of modern technologies and modern systems. For reasons both technical and economic, we can no longer afford to build ever-larger main memory systems out of DRAM. Flash memory, on the other hand, is significantly cheaper and denser than DRAM and therefore should take its place. While it is true that flash is significantly slower than DRAM, one can afford to build much larger main memories out of flash than out of DRAM, and we show that an appropriately designed memory hierarchy, built of flash as main memory and DRAM as a cache, will approach the performance of DRAM, at the price-per-bit of flash. In our studies as part of this project, we have investigated Non-Volatile Main Memory (NVMM), a new main-memory architecture for large-scale computing systems, one that is specifically designed to address the weaknesses described previously. In particular, it provides the following features: non-volatility: The bulk of the storage is comprised of NAND flash, and in this organization DRAM is used only as a cache, not as main memory. Furthermore, the flash is journaled, which means that operations such as checkpoint/restore are already built into the system. 1+ terabytes of storage per socket: SSDs and DRAM DIMMs have roughly the same form factor (several square inches of PCB surface area), and terabyte SSDs are now commonplace. performance approaching that of DRAM: DRAM is used as a cache to the flash system. price-per-bit approaching that of NAND: Flash is currently well under $0.50 per gigabyte; DDR3 SDRAM is currently just over $10 per gigabyte [Newegg 2014]. Even today, one can build an easily affordable main memory system with a terabyte or more of NAND storage per CPU socket (which would be extremely expensive were one to use DRAM), and our cycle- accurate, full-system experiments show that this can be done at a performance point that lies within a factor of two of DRAM.« less

Design of diaphragm actuator based on ferromagnetic shape memory alloy composite

NASA Astrophysics Data System (ADS)

Liang, Yuanchang; Taya, Minoru; Kuga, Yasuo

2003-08-01

A new diaphragm actuator based on the ferromagnetic shape memory alloy (FSMA) composite is designed where the FSMA composite is composed of ferromagnetic soft iron and superelastic grade of NiTi shape memory alloy (SMA). The actuation mechanism for the FSMA composite plate of the actuator is the hybrid mechanism that we proposed previously. This diaphragm actuator is the first design toward designing a new synthetic jet actuator that will be used for active flow control technology on airplane wings. The design of the FSMA composite diaphragm actuator was established first by using both mechanical and ferromagnetic finite element analyses with an aim of optimization of the actuator components. Based on the FEM results, the first generation diaphragm actuator system was assembled and its static and dynamic performance was experimentally evaluated.

Design of a modular digital computer system DRL 4 and 5. [design of airborne/spaceborne computer system

NASA Technical Reports Server (NTRS)

1973-01-01

Design and development efforts for a spaceborne modular computer system are reported. An initial baseline description is followed by an interface design that includes definition of the overall system response to all classes of failure. Final versions for the register level designs for all module types were completed. Packaging, support and control executive software, including memory utilization estimates and design verification plan, were formalized to insure a soundly integrated design of the digital computer system.

Shape Memory Alloy Actuator Design: CASMART Collaborative Best Practices

NASA Technical Reports Server (NTRS)

Benafan, Othmane; Brown, Jeff; Calkins, F. Tad; Kumar, Parikshith; Stebner, Aaron; Turner, Travis; Vaidyanathan, Raj; Webster, John; Young, Marcus L.

2011-01-01

Upon examination of shape memory alloy (SMA) actuation designs, there are many considerations and methodologies that are common to them all. A goal of CASMART's design working group is to compile the collective experiences of CASMART's member organizations into a single medium that engineers can then use to make the best decisions regarding SMA system design. In this paper, a review of recent work toward this goal is presented, spanning a wide range of design aspects including evaluation, properties, testing, modeling, alloy selection, fabrication, actuator processing, design optimization, controls, and system integration. We have documented each aspect, based on our collective experiences, so that the design engineer may access the tools and information needed to successfully design and develop SMA systems. Through comparison of several case studies, it is shown that there is not an obvious single, linear route a designer can adopt to navigate the path of concept to product. SMA engineering aspects will have different priorities and emphasis for different applications.

Development of a shape memory alloy actuator for a robotic eye prosthesis

NASA Astrophysics Data System (ADS)

Bunton, T. B. Wolfe; Faulkner, M. G.; Wolfaardt, J.

2005-08-01

The quality of life of patients who wear an orbital prosthesis would be vastly improved if their prostheses were also able to execute vertical and horizontal motion. This requires appropriate actuation and control systems to create an intelligent prosthesis. A method of actuation that meets the demanding design criteria is currently not available. The present work considers an activation system that follows a design philosophy of biomimicry, simplicity and space optimization. While several methods of actuation were considered, shape memory alloys were chosen for their high power density, high actuation forces and high displacements. The behaviour of specific shape memory alloys as an actuator was investigated to determine the force obtained, the transformation temperatures and details of the material processing. In addition, a large-scale prototype was constructed to validate the response of the proposed system.

A Fully Automated Drosophila Olfactory Classical Conditioning and Testing System for Behavioral Learning and Memory Assessment

PubMed Central

Jiang, Hui; Hanna, Eriny; Gatto, Cheryl L.; Page, Terry L.; Bhuva, Bharat; Broadie, Kendal

2016-01-01

Background Aversive olfactory classical conditioning has been the standard method to assess Drosophila learning and memory behavior for decades, yet training and testing are conducted manually under exceedingly labor-intensive conditions. To overcome this severe limitation, a fully automated, inexpensive system has been developed, which allows accurate and efficient Pavlovian associative learning/memory analyses for high-throughput pharmacological and genetic studies. New Method The automated system employs a linear actuator coupled to an odorant T-maze with airflow-mediated transfer of animals between training and testing stages. Odorant, airflow and electrical shock delivery are automatically administered and monitored during training trials. Control software allows operator-input variables to define parameters of Drosophila learning, short-term memory and long-term memory assays. Results The approach allows accurate learning/memory determinations with operational fail-safes. Automated learning indices (immediately post-training) and memory indices (after 24 hours) are comparable to traditional manual experiments, while minimizing experimenter involvement. Comparison with Existing Methods The automated system provides vast improvements over labor-intensive manual approaches with no experimenter involvement required during either training or testing phases. It provides quality control tracking of airflow rates, odorant delivery and electrical shock treatments, and an expanded platform for high-throughput studies of combinational drug tests and genetic screens. The design uses inexpensive hardware and software for a total cost of ~$500US, making it affordable to a wide range of investigators. Conclusions This study demonstrates the design, construction and testing of a fully automated Drosophila olfactory classical association apparatus to provide low-labor, high-fidelity, quality-monitored, high-throughput and inexpensive learning and memory behavioral assays. PMID:26703418

A fully automated Drosophila olfactory classical conditioning and testing system for behavioral learning and memory assessment.

PubMed

Jiang, Hui; Hanna, Eriny; Gatto, Cheryl L; Page, Terry L; Bhuva, Bharat; Broadie, Kendal

2016-03-01

Aversive olfactory classical conditioning has been the standard method to assess Drosophila learning and memory behavior for decades, yet training and testing are conducted manually under exceedingly labor-intensive conditions. To overcome this severe limitation, a fully automated, inexpensive system has been developed, which allows accurate and efficient Pavlovian associative learning/memory analyses for high-throughput pharmacological and genetic studies. The automated system employs a linear actuator coupled to an odorant T-maze with airflow-mediated transfer of animals between training and testing stages. Odorant, airflow and electrical shock delivery are automatically administered and monitored during training trials. Control software allows operator-input variables to define parameters of Drosophila learning, short-term memory and long-term memory assays. The approach allows accurate learning/memory determinations with operational fail-safes. Automated learning indices (immediately post-training) and memory indices (after 24h) are comparable to traditional manual experiments, while minimizing experimenter involvement. The automated system provides vast improvements over labor-intensive manual approaches with no experimenter involvement required during either training or testing phases. It provides quality control tracking of airflow rates, odorant delivery and electrical shock treatments, and an expanded platform for high-throughput studies of combinational drug tests and genetic screens. The design uses inexpensive hardware and software for a total cost of ∼$500US, making it affordable to a wide range of investigators. This study demonstrates the design, construction and testing of a fully automated Drosophila olfactory classical association apparatus to provide low-labor, high-fidelity, quality-monitored, high-throughput and inexpensive learning and memory behavioral assays. Copyright © 2015 Elsevier B.V. All rights reserved.

Solar heating and hot water system installed at Charlotte Memorial Hospital, Charlotte, North Carolina

NASA Technical Reports Server (NTRS)

1981-01-01

Detailed information regarding the design and installation of a heating and hot water system in a commercial application is given. This information includes descriptions of system and building, design philosophy, control logic operation modes, design and installation drawing and a brief description of problems encountered and their solutions.

Biological Signal Processing with a Genetic Toggle Switch

PubMed Central

Hillenbrand, Patrick; Fritz, Georg; Gerland, Ulrich

2013-01-01

Complex gene regulation requires responses that depend not only on the current levels of input signals but also on signals received in the past. In digital electronics, logic circuits with this property are referred to as sequential logic, in contrast to the simpler combinatorial logic without such internal memory. In molecular biology, memory is implemented in various forms such as biochemical modification of proteins or multistable gene circuits, but the design of the regulatory interface, which processes the input signals and the memory content, is often not well understood. Here, we explore design constraints for such regulatory interfaces using coarse-grained nonlinear models and stochastic simulations of detailed biochemical reaction networks. We test different designs for biological analogs of the most versatile memory element in digital electronics, the JK-latch. Our analysis shows that simple protein-protein interactions and protein-DNA binding are sufficient, in principle, to implement genetic circuits with the capabilities of a JK-latch. However, it also exposes fundamental limitations to its reliability, due to the fact that biological signal processing is asynchronous, in contrast to most digital electronics systems that feature a central clock to orchestrate the timing of all operations. We describe a seemingly natural way to improve the reliability by invoking the master-slave concept from digital electronics design. This concept could be useful to interpret the design of natural regulatory circuits, and for the design of synthetic biological systems. PMID:23874595

DESIGN PRINCIPLES FOR AN ON-LINE INFORMATION RETRIEVAL SYSTEM. TECHNICAL REPORT.

ERIC Educational Resources Information Center

LOWE, THOMAS C.

AREAS INVESTIGATED INCLUDE SLOW MEMORY DATA STORAGE, THE PROBLEM OF DECODING FROM AN INDEX TO A SLOW MEMORY ADDRESS, THE STRUCTURE OF DATA LISTS AND DATA LIST OPERATORS, COMMUNICATIONS BETWEEN THE HUMAN USER AND THE SYSTEM, PROCESSING OF RETRIEVAL REQUESTS, AND THE USER'S CONTROL OVER THE RETURN OF INFORMATION RETRIEVED. LINEAR, LINKED AND…

Shared Values as Anchors of a Learning Community: A Case Study in Information Systems Design

ERIC Educational Resources Information Center

Giordano, Daniela

2004-01-01

This paper examines the role in both individual and organizational learning of the system of values sustained by a community undertaking a design task. The discussion is based on the results of a longitudinal study of a community of novice information system designers supported by a Web-based shared design memory which allows reuse of design…

Command and Control Software Development Memory Management

NASA Technical Reports Server (NTRS)

Joseph, Austin Pope

2017-01-01

This internship was initially meant to cover the implementation of unit test automation for a NASA ground control project. As is often the case with large development projects, the scope and breadth of the internship changed. Instead, the internship focused on finding and correcting memory leaks and errors as reported by a COTS software product meant to track such issues. Memory leaks come in many different flavors and some of them are more benign than others. On the extreme end a program might be dynamically allocating memory and not correctly deallocating it when it is no longer in use. This is called a direct memory leak and in the worst case can use all the available memory and crash the program. If the leaks are small they may simply slow the program down which, in a safety critical system (a system for which a failure or design error can cause a risk to human life), is still unacceptable. The ground control system is managed in smaller sub-teams, referred to as CSCIs. The CSCI that this internship focused on is responsible for monitoring the health and status of the system. This team's software had several methods/modules that were leaking significant amounts of memory. Since most of the code in this system is safety-critical, correcting memory leaks is a necessity.

Content addressable memory project

NASA Technical Reports Server (NTRS)

Hall, Josh; Levy, Saul; Smith, D.; Wei, S.; Miyake, K.; Murdocca, M.

1991-01-01

The progress on the Rutgers CAM (Content Addressable Memory) Project is described. The overall design of the system is completed at the architectural level and described. The machine is composed of two kinds of cells: (1) the CAM cells which include both memory and processor, and support local processing within each cell; and (2) the tree cells, which have smaller instruction set, and provide global processing over the CAM cells. A parameterized design of the basic CAM cell is completed. Progress was made on the final specification of the CPS. The machine architecture was driven by the design of algorithms whose requirements are reflected in the resulted instruction set(s). A few of these algorithms are described.

Development of a fault-tolerant microprocessor based computer system for space flight

NASA Technical Reports Server (NTRS)

Montgomery, V. T.

1981-01-01

A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.

Memory Network For Distributed Data Processors

NASA Technical Reports Server (NTRS)

Bolen, David; Jensen, Dean; Millard, ED; Robinson, Dave; Scanlon, George

1992-01-01

Universal Memory Network (UMN) is modular, digital data-communication system enabling computers with differing bus architectures to share 32-bit-wide data between locations up to 3 km apart with less than one millisecond of latency. Makes it possible to design sophisticated real-time and near-real-time data-processing systems without data-transfer "bottlenecks". This enterprise network permits transmission of volume of data equivalent to an encyclopedia each second. Facilities benefiting from Universal Memory Network include telemetry stations, simulation facilities, power-plants, and large laboratories or any facility sharing very large volumes of data. Main hub of UMN is reflection center including smaller hubs called Shared Memory Interfaces.

Guidance system operations plan for manned CSM earth orbital and lunar missions using program COLOSSUS 3. Section 7: Erasable memory programs

NASA Technical Reports Server (NTRS)

Hamilton, M. H.

1972-01-01

Erasable-memory programs designed for guidance computers used in command and lunar modules are presented. The purpose, functional description, assumptions, restrictions, and imitations are given for each program.

Gateway Arch Circulator Conceptual Feasibility Study : Jefferson National Expansion Memorial

DOT National Transportation Integrated Search

2015-03-01

The Jefferson National Expansion Memorial (JEFF) is undergoing major design changes as part of the City Arch River 2015 project (CAR) that will impact access for park visitors. The park and stakeholders are considering a circulator system to facilita...

Nonvolatile memory chips: critical technology for high-performance recce systems

NASA Astrophysics Data System (ADS)

Kaufman, Bruce

2000-11-01

Airborne recce systems universally require nonvolatile storage of recorded data. Both present and next generation designs make use of flash memory chips. Flash memory devices are in high volume use for a variety of commercial products ranging form cellular phones to digital cameras. Fortunately, commercial applications call for increasing capacities and fast write times. These parameters are important to the designer of recce recorders. Of economic necessity COTS devices are used in recorders that must perform in military avionics environments. Concurrently, recording rates are moving to $GTR10Gb/S. Thus to capture imagery for even a few minutes of record time, tactically meaningful solid state recorders will require storage capacities in the 100s of Gbytes. Even with memory chip densities at present day 512Mb, such capacities require thousands of chips. The demands on packaging technology are daunting. This paper will consider the differing flash chip architectures, both available and projected and discuss the impact on recorder architecture and performance. Emerging nonvolatile memory technologies, FeRAM AND MIRAM will be reviewed with regard to their potential use in recce recorders.

The misnomer of attention-deficit hyperactivity disorder.

PubMed

Wasserman, Theodore; Wasserman, Lori Drucker

2015-01-01

We propose that attention-deficit disorder represents an inefficiency of an integrated system designed to allocate working memory to designated tasks rather than the absence or dysfunction of a particular form of attention. A significant portion of this inefficiency in the allocation of working memory represents poor engagement of the reward circuit with distinct circuits of learning and performance that control instrumental conditioning (learning). Efficient attention requires the interaction of these circuits. For a significant percentage of individuals who present with attention-deficit disorder, their problems represent the engagement, or lack thereof, of the motivational and reward circuit as opposed to problems, or disorders of attention traditionally defined as problems with orienting, focusing, and sustaining. We demonstrate that there is an integrated system of working-memory allocation that responds by recruiting relevant aspects of both cortex and subcortex to the demands of the task being encountered. In this model, attention is viewed as a gating function determined by novelty, flight-or-fight response, and reward history/valence affecting motivation. We view the traditional models of attention, rather than describe specific types of attention per se, as representing the description of the behavioral output of this integrated orienting and engagement system designed to allocate working memory to task-specific stimuli.

Applications considerations in the system design of highly concurrent multiprocessors

NASA Technical Reports Server (NTRS)

Lundstrom, Stephen F.

1987-01-01

A flow model processor approach to parallel processing is described, using very-high-performance individual processors, high-speed circuit switched interconnection networks, and a high-speed synchronization capability to minimize the effect of the inherently serial portions of applications on performance. Design studies related to the determination of the number of processors, the memory organization, and the structure of the networks used to interconnect the processor and memory resources are discussed. Simulations indicate that applications centered on the large shared data memory should be able to sustain over 500 million floating point operations per second.

Optoelectronic-cache memory system architecture.

PubMed

Chiarulli, D M; Levitan, S P

1996-05-10

We present an investigation of the architecture of an optoelectronic cache that can integrate terabit optical memories with the electronic caches associated with high-performance uniprocessors and multiprocessors. The use of optoelectronic-cache memories enables these terabit technologies to provide transparently low-latency secondary memory with frame sizes comparable with disk pages but with latencies that approach those of electronic secondary-cache memories. This enables the implementation of terabit memories with effective access times comparable with the cycle times of current microprocessors. The cache design is based on the use of a smart-pixel array and combines parallel free-space optical input-output to-and-from optical memory with conventional electronic communication to the processor caches. This cache and the optical memory system to which it will interface provide a large random-access memory space that has a lower overall latency than that of magnetic disks and disk arrays. In addition, as a consequence of the high-bandwidth parallel input-output capabilities of optical memories, fault service times for the optoelectronic cache are substantially less than those currently achievable with any rotational media.

High-throughput state-machine replication using software transactional memory.

PubMed

Zhao, Wenbing; Yang, William; Zhang, Honglei; Yang, Jack; Luo, Xiong; Zhu, Yueqin; Yang, Mary; Luo, Chaomin

2016-11-01

State-machine replication is a common way of constructing general purpose fault tolerance systems. To ensure replica consistency, requests must be executed sequentially according to some total order at all non-faulty replicas. Unfortunately, this could severely limit the system throughput. This issue has been partially addressed by identifying non-conflicting requests based on application semantics and executing these requests concurrently. However, identifying and tracking non-conflicting requests require intimate knowledge of application design and implementation, and a custom fault tolerance solution developed for one application cannot be easily adopted by other applications. Software transactional memory offers a new way of constructing concurrent programs. In this article, we present the mechanisms needed to retrofit existing concurrency control algorithms designed for software transactional memory for state-machine replication. The main benefit for using software transactional memory in state-machine replication is that general purpose concurrency control mechanisms can be designed without deep knowledge of application semantics. As such, new fault tolerance systems based on state-machine replications with excellent throughput can be easily designed and maintained. In this article, we introduce three different concurrency control mechanisms for state-machine replication using software transactional memory, namely, ordered strong strict two-phase locking, conventional timestamp-based multiversion concurrency control, and speculative timestamp-based multiversion concurrency control. Our experiments show that speculative timestamp-based multiversion concurrency control mechanism has the best performance in all types of workload, the conventional timestamp-based multiversion concurrency control offers the worst performance due to high abort rate in the presence of even moderate contention between transactions. The ordered strong strict two-phase locking mechanism offers the simplest solution with excellent performance in low contention workload, and fairly good performance in high contention workload.

High-throughput state-machine replication using software transactional memory

PubMed Central

Yang, William; Zhang, Honglei; Yang, Jack; Luo, Xiong; Zhu, Yueqin; Yang, Mary; Luo, Chaomin

2017-01-01

State-machine replication is a common way of constructing general purpose fault tolerance systems. To ensure replica consistency, requests must be executed sequentially according to some total order at all non-faulty replicas. Unfortunately, this could severely limit the system throughput. This issue has been partially addressed by identifying non-conflicting requests based on application semantics and executing these requests concurrently. However, identifying and tracking non-conflicting requests require intimate knowledge of application design and implementation, and a custom fault tolerance solution developed for one application cannot be easily adopted by other applications. Software transactional memory offers a new way of constructing concurrent programs. In this article, we present the mechanisms needed to retrofit existing concurrency control algorithms designed for software transactional memory for state-machine replication. The main benefit for using software transactional memory in state-machine replication is that general purpose concurrency control mechanisms can be designed without deep knowledge of application semantics. As such, new fault tolerance systems based on state-machine replications with excellent throughput can be easily designed and maintained. In this article, we introduce three different concurrency control mechanisms for state-machine replication using software transactional memory, namely, ordered strong strict two-phase locking, conventional timestamp-based multiversion concurrency control, and speculative timestamp-based multiversion concurrency control. Our experiments show that speculative timestamp-based multiversion concurrency control mechanism has the best performance in all types of workload, the conventional timestamp-based multiversion concurrency control offers the worst performance due to high abort rate in the presence of even moderate contention between transactions. The ordered strong strict two-phase locking mechanism offers the simplest solution with excellent performance in low contention workload, and fairly good performance in high contention workload. PMID:29075049

Work stealing for GPU-accelerated parallel programs in a global address space framework: WORK STEALING ON GPU-ACCELERATED SYSTEMS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arafat, Humayun; Dinan, James; Krishnamoorthy, Sriram

Task parallelism is an attractive approach to automatically load balance the computation in a parallel system and adapt to dynamism exhibited by parallel systems. Exploiting task parallelism through work stealing has been extensively studied in shared and distributed-memory contexts. In this paper, we study the design of a system that uses work stealing for dynamic load balancing of task-parallel programs executed on hybrid distributed-memory CPU-graphics processing unit (GPU) systems in a global-address space framework. We take into account the unique nature of the accelerator model employed by GPUs, the significant performance difference between GPU and CPU execution as a functionmore » of problem size, and the distinct CPU and GPU memory domains. We consider various alternatives in designing a distributed work stealing algorithm for CPU-GPU systems, while taking into account the impact of task distribution and data movement overheads. These strategies are evaluated using microbenchmarks that capture various execution configurations as well as the state-of-the-art CCSD(T) application module from the computational chemistry domain.« less

Seeing the Wood for the Trees: Applying the dual-memory system model to investigate expert teachers' observational skills in natural ecological learning environments

NASA Astrophysics Data System (ADS)

Stolpe, Karin; Björklund, Lars

2012-01-01

This study aims to investigate two expert ecology teachers' ability to attend to essential details in a complex environment during a field excursion, as well as how they teach this ability to their students. In applying a cognitive dual-memory system model for learning, we also suggest a rationale for their behaviour. The model implies two separate memory systems: the implicit, non-conscious, non-declarative system and the explicit, conscious, declarative system. This model provided the starting point for the research design. However, it was revised from the empirical findings supported by new theoretical insights. The teachers were video and audio recorded during their excursion and interviewed in a stimulated recall setting afterwards. The data were qualitatively analysed using the dual-memory system model. The results show that the teachers used holistic pattern recognition in their own identification of natural objects. However, teachers' main strategy to teach this ability is to give the students explicit rules or specific characteristics. According to the dual-memory system model the holistic pattern recognition is processed in the implicit memory system as a non-conscious match with earlier experienced situations. We suggest that this implicit pattern matching serves as an explanation for teachers' ecological and teaching observational skills. Another function of the implicit memory system is its ability to control automatic behaviour and non-conscious decision-making. The teachers offer the students firsthand sensory experiences which provide a prerequisite for the formation of implicit memories that provides a foundation for expertise.

Multiprocessor shared-memory information exchange

DOE Office of Scientific and Technical Information (OSTI.GOV)

Santoline, L.L.; Bowers, M.D.; Crew, A.W.

1989-02-01

In distributed microprocessor-based instrumentation and control systems, the inter-and intra-subsystem communication requirements ultimately form the basis for the overall system architecture. This paper describes a software protocol which addresses the intra-subsystem communications problem. Specifically the protocol allows for multiple processors to exchange information via a shared-memory interface. The authors primary goal is to provide a reliable means for information to be exchanged between central application processor boards (masters) and dedicated function processor boards (slaves) in a single computer chassis. The resultant Multiprocessor Shared-Memory Information Exchange (MSMIE) protocol, a standard master-slave shared-memory interface suitable for use in nuclear safety systems, ismore » designed to pass unidirectional buffers of information between the processors while providing a minimum, deterministic cycle time for this data exchange.« less

The Sleep Elaboration-Awake Pruning (SEAP) theory of memory: long term memories grow in complexity during sleep and undergo selection while awake. Clinical, psychopharmacological and creative implications.

PubMed

Charlton, Bruce G; Andras, Peter

2009-07-01

Long term memory (LTM) systems need to be adaptive such that they enhance an organism's reproductive fitness and self-reproducing in order to maintain their complexity of communications over time in the face of entropic loss of information. Traditional 'representation-consolidation' accounts conceptualize memory adaptiveness as due to memories being 'representations' of the environment, and the longevity of memories as due to 'consolidation' processes. The assumption is that memory representations are formed while an animal is awake and interacting with the environment, and these memories are consolidated mainly while the animal is asleep. So the traditional view of memory is 'instructionist' and assumes that information is transferred from the environment into the brain. By contrast, we see memories as arising endogenously within the brain's LTM system mainly during sleep, to create complex but probably maladaptive memories which are then simplified ('pruned') and selected during the awake period. When awake the LTM system is brought into a more intense interaction with past and present experience. Ours is therefore a 'selectionist' account of memory, and could be termed the Sleep Elaboration-Awake Pruning (or SEAP) theory. The SEAP theory explains the longevity of memories in the face of entropy by the tendency for memories to grow in complexity during sleep; and explains the adaptiveness of memory by selection for consistency with perceptions and previous memories during the awake state. Sleep is therefore that behavioural state during which most of the internal processing of the system of LTM occurs; and the reason sleep remains poorly understood is that its primary activity is the expansion of long term memories. By re-conceptualizing the relationship between memory, sleep and the environment; SEAP provides a radically new framework for memory research, with implications for the measurement of memory and the design of empirical investigations in clinical, psychopharmacological and creative domains. For example, it would be predicted that states of insufficient alertness such as delirium would produce errors of commission (memory distortion and false memories, as with psychotic delusions), while sleep deprivation would produce errors of memory omission (memory loss). Ultimately, the main argument in favour of SEAP is that long term memory must be a complex adaptive system, and complex systems arise, are selected and sustained according to the principles of systems theory; and therefore LTM cannot be functioning in the way assumed by 'representation-consolidation' theories.

Design, fabrication, testing and delivery of a feasibility model laminated ferrite memory

NASA Technical Reports Server (NTRS)

Heckler, H. C.

1973-01-01

The effect of using multiword addressing with laminated ferrite arrays was made. Both a reduction in the number of components, and a reduction in power consumption was obtained for memory capacities between one million bits and one million words. An investigation into the effect of variations in the processing steps resulted in a number of process modifications that improved the quality of the arrays. A feasibility model laminated ferrite memory system was constructed by modifying a commercial plated wire memory system to operate with laminated ferrite arrays. To provide flexibility for the testing of the laminated ferrite memory, an exerciser has been constructed to automatically control the loading and recirculation of arbitrary size checkerboard patterns of one's and zero's and to display the patterns of stored information on a CRT screen.

Design of Unstructured Adaptive (UA) NAS Parallel Benchmark Featuring Irregular, Dynamic Memory Accesses

NASA Technical Reports Server (NTRS)

Feng, Hui-Yu; VanderWijngaart, Rob; Biswas, Rupak; Biegel, Bryan (Technical Monitor)

2001-01-01

We describe the design of a new method for the measurement of the performance of modern computer systems when solving scientific problems featuring irregular, dynamic memory accesses. The method involves the solution of a stylized heat transfer problem on an unstructured, adaptive grid. A Spectral Element Method (SEM) with an adaptive, nonconforming mesh is selected to discretize the transport equation. The relatively high order of the SEM lowers the fraction of wall clock time spent on inter-processor communication, which eases the load balancing task and allows us to concentrate on the memory accesses. The benchmark is designed to be three-dimensional. Parallelization and load balance issues of a reference implementation will be described in detail in future reports.

Photonic content-addressable memory system that uses a parallel-readout optical disk

NASA Astrophysics Data System (ADS)

Krishnamoorthy, Ashok V.; Marchand, Philippe J.; Yayla, Gökçe; Esener, Sadik C.

1995-11-01

We describe a high-performance associative-memory system that can be implemented by means of an optical disk modified for parallel readout and a custom-designed silicon integrated circuit with parallel optical input. The system can achieve associative recall on 128 \\times 128 bit images and also on variable-size subimages. The system's behavior and performance are evaluated on the basis of experimental results on a motionless-head parallel-readout optical-disk system, logic simulations of the very-large-scale integrated chip, and a software emulation of the overall system.

Advanced Control Systems for Aircraft Powerplants

DTIC Science & Technology

1980-02-01

production of high- integrity software. 1.0 INTRODUCTION Work on full-authority digital control for gas turbines was started at Rolls- Royce Limited... INTRODUCTION In order to fully understand the operation of the Secondary Power System Control Unit - abbreviated SPSCU - we must first take a close look at...Only Memory EPROM -- Erasable Read Only Memory PLA -- Power Lever Angle LVDT -- Linear Variable Differential Transformer INTRODUCTION Preliminary design

On the impact of communication complexity in the design of parallel numerical algorithms

NASA Technical Reports Server (NTRS)

Gannon, D.; Vanrosendale, J.

1984-01-01

This paper describes two models of the cost of data movement in parallel numerical algorithms. One model is a generalization of an approach due to Hockney, and is suitable for shared memory multiprocessors where each processor has vector capabilities. The other model is applicable to highly parallel nonshared memory MIMD systems. In the second model, algorithm performance is characterized in terms of the communication network design. Techniques used in VLSI complexity theory are also brought in, and algorithm independent upper bounds on system performance are derived for several problems that are important to scientific computation.

On the impact of communication complexity on the design of parallel numerical algorithms

NASA Technical Reports Server (NTRS)

Gannon, D. B.; Van Rosendale, J.

1984-01-01

This paper describes two models of the cost of data movement in parallel numerical alorithms. One model is a generalization of an approach due to Hockney, and is suitable for shared memory multiprocessors where each processor has vector capabilities. The other model is applicable to highly parallel nonshared memory MIMD systems. In this second model, algorithm performance is characterized in terms of the communication network design. Techniques used in VLSI complexity theory are also brought in, and algorithm-independent upper bounds on system performance are derived for several problems that are important to scientific computation.

Divergent short- and long-term effects of acute stress in object recognition memory are mediated by endogenous opioid system activation.

PubMed

Nava-Mesa, Mauricio O; Lamprea, Marisol R; Múnera, Alejandro

2013-11-01

Acute stress induces short-term object recognition memory impairment and elicits endogenous opioid system activation. The aim of this study was thus to evaluate whether opiate system activation mediates the acute stress-induced object recognition memory changes. Adult male Wistar rats were trained in an object recognition task designed to test both short- and long-term memory. Subjects were randomly assigned to receive an intraperitoneal injection of saline, 1 mg/kg naltrexone or 3 mg/kg naltrexone, four and a half hours before the sample trial. Five minutes after the injection, half the subjects were submitted to movement restraint during four hours while the other half remained in their home cages. Non-stressed subjects receiving saline (control) performed adequately during the short-term memory test, while stressed subjects receiving saline displayed impaired performance. Naltrexone prevented such deleterious effect, in spite of the fact that it had no intrinsic effect on short-term object recognition memory. Stressed subjects receiving saline and non-stressed subjects receiving naltrexone performed adequately during the long-term memory test; however, control subjects as well as stressed subjects receiving a high dose of naltrexone performed poorly. Control subjects' dissociated performance during both memory tests suggests that the short-term memory test induced a retroactive interference effect mediated through light opioid system activation; such effect was prevented either by low dose naltrexone administration or by strongly activating the opioid system through acute stress. Both short-term memory retrieval impairment and long-term memory improvement observed in stressed subjects may have been mediated through strong opioid system activation, since they were prevented by high dose naltrexone administration. Therefore, the activation of the opioid system plays a dual modulating role in object recognition memory. Copyright © 2013 Elsevier Inc. All rights reserved.

A Common DPU Platform for ESA JUICE Mission Instruments

NASA Astrophysics Data System (ADS)

Aberg, Martin; Hellstrom, Daniel; Samuelsson, Arne; Torelli, Felice

2016-08-01

This paper describes the resulting hardware and software platform based on GR712RC [1] LEON3-FT that Cobham Gaisler developed in accordance with the common system requirements of the ten scientific instruments on-board the ESA JUICE spacecraft destined the Jupiter system [8].The radiation hardened DPU platform features EDAC protected boot, application memory and working memory of configurable sizes and SpaceWire, FPGA I/O-32/16/8, GPIO, UART and SPI I/O interfaces. The design has undergone PSA, Risk, WCA, Radiation analyses etc. to justify component and design choices resulting in a robust design that can be used in spacecrafts requiring a total dose up to 100krad(Si). The prototype board manufactured uses engineering models of the flight components to ensure that development is representative.Validated boot, standby and driver software accommodates the various DPU platform configurations. The boot performs low-level DPU initialization, standby handles OBC SpaceWire communication and finally the loading and executing of application images typically stored in the non-volatile application memory.

A New Partial Reconfiguration-Based Fault-Injection System to Evaluate SEU Effects in SRAM-Based FPGAs

NASA Astrophysics Data System (ADS)

Sterpone, L.; Violante, M.

2007-08-01

Modern SRAM-based field programmable gate array (FPGA) devices offer high capability in implementing complex system. Unfortunately, SRAM-based FPGAs are extremely sensitive to single event upsets (SEUs) induced by radiation particles. In order to successfully deploy safety- or mission-critical applications, designer need to validate the correctness of the obtained designs. In this paper we describe a system based on partial-reconfiguration for running fault-injection experiments within the configuration memory of SRAM-based FPGAs. The proposed fault-injection system uses the internal configuration capabilities that modern FPGAs offer in order to inject SEU within the configuration memory. Detailed experimental results show that the technique is orders of magnitude faster than previously proposed ones.

Improved memory loading techniques for the TSRV display system

NASA Technical Reports Server (NTRS)

Easley, W. C.; Lynn, W. A.; Mcluer, D. G.

1986-01-01

A recent upgrade of the TSRV research flight system at NASA Langley Research Center retained the original monochrome display system. However, the display memory loading equipment was replaced requiring design and development of new methods of performing this task. This paper describes the new techniques developed to load memory in the display system. An outdated paper tape method for loading the BOOTSTRAP control program was replaced by EPROM storage of the characters contained on the tape. Rather than move a tape past an optical reader, a counter was implemented which steps sequentially through EPROM addresses and presents the same data to the loader circuitry. A cumbersome cassette tape method for loading the applications software was replaced with a floppy disk method using a microprocessor terminal installed as part of the upgrade. The cassette memory image was transferred to disk and a specific software loader was written for the terminal which duplicates the function of the cassette loader.

Work stealing for GPU-accelerated parallel programs in a global address space framework

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arafat, Humayun; Dinan, James; Krishnamoorthy, Sriram

Task parallelism is an attractive approach to automatically load balance the computation in a parallel system and adapt to dynamism exhibited by parallel systems. Exploiting task parallelism through work stealing has been extensively studied in shared and distributed-memory contexts. In this paper, we study the design of a system that uses work stealing for dynamic load balancing of task-parallel programs executed on hybrid distributed-memory CPU-graphics processing unit (GPU) systems in a global-address space framework. We take into account the unique nature of the accelerator model employed by GPUs, the significant performance difference between GPU and CPU execution as a functionmore » of problem size, and the distinct CPU and GPU memory domains. We consider various alternatives in designing a distributed work stealing algorithm for CPU-GPU systems, while taking into account the impact of task distribution and data movement overheads. These strategies are evaluated using microbenchmarks that capture various execution configurations as well as the state-of-the-art CCSD(T) application module from the computational chemistry domain« less

High-strain slide-ring shape-memory polycaprolactone-based polyurethane.

PubMed

Wu, Ruiqing; Lai, Jingjuan; Pan, Yi; Zheng, Zhaohui; Ding, Xiaobin

2018-06-06

To enable shape-memory polymer networks to achieve recoverable high deformability with a simultaneous high shape-fixity ratio and shape-recovery ratio, novel semi-crystalline slide-ring shape-memory polycaprolactone-based polyurethane (SR-SMPCLU) with movable net-points constructed by a topologically interlocked slide-ring structure was designed and fabricated. The SR-SMPCLU not only exhibited good shape fixity, almost complete shape recovery, and a fast shape-recovery speed, it also showed an outstanding recoverable high-strain capacity with 95.83% Rr under a deformation strain of 1410% due to the pulley effect of the topological slide-ring structure. Furthermore, the SR-SMPCLU system maintained excellent shape-memory performance with increasing the training cycle numbers at 45% and even 280% deformation strain. The effects of the slide-ring cross-linker content, deformation strain, and successive shape-memory cycles on the shape-memory performance were investigated. A possible mechanism for the shape-memory effect of the SR-SMPCLU system is proposed.

Implementation of an experimental fault-tolerant memory system

NASA Technical Reports Server (NTRS)

Carter, W. C.; Mccarthy, C. E.

1976-01-01

The experimental fault-tolerant memory system described in this paper has been designed to enable the modular addition of spares, to validate the theoretical fault-secure and self-testing properties of the translator/corrector, to provide a basis for experiments using the new testing and correction processes for recovery, and to determine the practicality of such systems. The hardware design and implementation are described, together with methods of fault insertion. The hardware/software interface, including a restricted single error correction/double error detection (SEC/DED) code, is specified. Procedures are carefully described which, (1) test for specified physical faults, (2) ensure that single error corrections are not miscorrections due to triple faults, and (3) enable recovery from double errors.

Data Movement Dominates: Advanced Memory Technology to Address the Real Exascale Power Problem

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bergman, Keren

Energy is the fundamental barrier to Exascale supercomputing and is dominated by the cost of moving data from one point to another, not computation. Similarly, performance is dominated by data movement, not computation. The solution to this problem requires three critical technologies: 3D integration, optical chip-to-chip communication, and a new communication model. The central goal of the Sandia led "Data Movement Dominates" project aimed to develop memory systems and new architectures based on these technologies that have the potential to lower the cost of local memory accesses by orders of magnitude and provide substantially more bandwidth. Only through these transformationalmore » advances can future systems reach the goals of Exascale computing with a manageable power budgets. The Sandia led team included co-PIs from Columbia University, Lawrence Berkeley Lab, and the University of Maryland. The Columbia effort of Data Movement Dominates focused on developing a physically accurate simulation environment and experimental verification for optically-connected memory (OCM) systems that can enable continued performance scaling through high-bandwidth capacity, energy-efficient bit-rate transparency, and time-of-flight latency. With OCM, memory device parallelism and total capacity can scale to match future high-performance computing requirements without sacrificing data-movement efficiency. When we consider systems with integrated photonics, links to memory can be seamlessly integrated with the interconnection network-in a sense, memory becomes a primary aspect of the interconnection network. At the core of the Columbia effort, toward expanding our understanding of OCM enabled computing we have created an integrated modeling and simulation environment that uniquely integrates the physical behavior of the optical layer. The PhoenxSim suite of design and software tools developed under this effort has enabled the co-design of and performance evaluation photonics-enabled OCM architectures on Exascale computing systems.« less

Defining the "D" in ISD. Part 1: Task-General Instructional Methods.

ERIC Educational Resources Information Center

Clark, Ruth Colvin

1986-01-01

The first of two articles designed to provide guidelines for the instructional development phase of instructional systems development focuses on general instructional methods supporting all instructional tasks. Teaching methods that support selective attention, processing in working memory, and connecting in long-term memory are described and…

Anxiety, cognition, and habit: a multiple memory systems perspective.

PubMed

Packard, Mark G

2009-10-13

Consistent with a multiple systems approach to memory organization in the mammalian brain, numerous studies have differentiated the roles of the hippocampus and dorsal striatum in "cognitive" and "habit" learning and memory, respectively. Additional research indicates that activation of efferent projections of the basolateral amygdala (BLA), a brain region implicated in mammalian emotion, modulates memory processes occurring in other brain structures. The present brief review describes research designed to link these general concepts by examining the manner in which emotional state may influence the relative use of multiple memory systems. In a dual-solution plus-maze task that can be acquired using either hippocampus-dependent or dorsal striatal-dependent learning, acute pre-training or pre-retrieval emotional arousal (restraint stress/inescapable foot shock, exposure to the predator odor TMT, or peripheral injection of anixogenic drugs) biases rats towards the use of habit memory. Moreover, intra-BLA injection of anxiogenic drugs is sufficient to bias rats towards the use of dorsal striatal-dependent habit memory. In single-solution plus-maze tasks that require the use of either cognitive or habit learning, intra-BLA infusions of anxiogenic drugs result in a behavioral profile indicating an impairing effect on hippocampus-dependent memory that effectively produces enhanced habit learning by eliminating competitive interference between cognitive and habit memory systems. It is speculated that the predominant use of habit memory that can be produced by anxious and/or stressful emotional states may have implications for understanding the role of learning and memory processes in various human psychopathologies, including for example post-traumatic stress disorder and drug addiction.

Dissecting the human immunologic memory for pathogens.

PubMed

Zielinski, Christina E; Corti, Davide; Mele, Federico; Pinto, Dora; Lanzavecchia, Antonio; Sallusto, Federica

2011-03-01

Studies on immunologic memory in animal models and especially in the human system are instrumental to identify mechanisms and correlates of protection necessary for vaccine development. In this article, we provide an overview of the cellular basis of immunologic memory. We also describe experimental approaches based on high throughput cell cultures, which we have developed to interrogate human memory T cells, B cells, and plasma cells. We discuss how these approaches can provide new tools and information for vaccine design, in a process that we define as 'analytic vaccinology'. © 2011 John Wiley & Sons A/S.

Detailed Design and Implementation of a Multiprogramming Operating System for Sixteen-Bit Microprocessors.

DTIC Science & Technology

1983-12-01

4 Multiuser Support ...... .......... 11-5 User Interface . .. .. ................ .. 11- 7 Inter -user Communications ................ 11- 7 Memory...user will greatly help facilitate the learning process. Inter -User Communication The inter -user communications of the operating system can be done using... inter -user communications would be met by using one or both of them. AMemory and File Management Memory and file management is concerned with four basic

Energy-aware Thread and Data Management in Heterogeneous Multi-core, Multi-memory Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Su, Chun-Yi

By 2004, microprocessor design focused on multicore scaling—increasing the number of cores per die in each generation—as the primary strategy for improving performance. These multicore processors typically equip multiple memory subsystems to improve data throughput. In addition, these systems employ heterogeneous processors such as GPUs and heterogeneous memories like non-volatile memory to improve performance, capacity, and energy efficiency. With the increasing volume of hardware resources and system complexity caused by heterogeneity, future systems will require intelligent ways to manage hardware resources. Early research to improve performance and energy efficiency on heterogeneous, multi-core, multi-memory systems focused on tuning a single primitivemore » or at best a few primitives in the systems. The key limitation of past efforts is their lack of a holistic approach to resource management that balances the tradeoff between performance and energy consumption. In addition, the shift from simple, homogeneous systems to these heterogeneous, multicore, multi-memory systems requires in-depth understanding of efficient resource management for scalable execution, including new models that capture the interchange between performance and energy, smarter resource management strategies, and novel low-level performance/energy tuning primitives and runtime systems. Tuning an application to control available resources efficiently has become a daunting challenge; managing resources in automation is still a dark art since the tradeoffs among programming, energy, and performance remain insufficiently understood. In this dissertation, I have developed theories, models, and resource management techniques to enable energy-efficient execution of parallel applications through thread and data management in these heterogeneous multi-core, multi-memory systems. I study the effect of dynamic concurrent throttling on the performance and energy of multi-core, non-uniform memory access (NUMA) systems. I use critical path analysis to quantify memory contention in the NUMA memory system and determine thread mappings. In addition, I implement a runtime system that combines concurrent throttling and a novel thread mapping algorithm to manage thread resources and improve energy efficient execution in multi-core, NUMA systems.« less

Robust relationship between reading span and speech recognition in noise

PubMed Central

Souza, Pamela; Arehart, Kathryn

2015-01-01

Objective Working memory refers to a cognitive system that manages information processing and temporary storage. Recent work has demonstrated that individual differences in working memory capacity measured using a reading span task are related to ability to recognize speech in noise. In this project, we investigated whether the specific implementation of the reading span task influenced the strength of the relationship between working memory capacity and speech recognition. Design The relationship between speech recognition and working memory capacity was examined for two different working memory tests that varied in approach, using a within-subject design. Data consisted of audiometric results along with the two different working memory tests; one speech-in-noise test; and a reading comprehension test. Study sample The test group included 94 older adults with varying hearing loss and 30 younger adults with normal hearing. Results Listeners with poorer working memory capacity had more difficulty understanding speech in noise after accounting for age and degree of hearing loss. That relationship did not differ significantly between the two different implementations of reading span. Conclusions Our findings suggest that different implementations of a verbal reading span task do not affect the strength of the relationship between working memory capacity and speech recognition. PMID:25975360

Control of an innovative super-capacitor-powered shape-memory-alloy actuated accumulator for blowout preventer

NASA Astrophysics Data System (ADS)

Chen, Jian; Li, Peng; Song, Gangbing; Ren, Zhang

2017-01-01

The design of a super-capacitor-powered shape-memory-alloy (SMA) actuated accumulator for blowout preventer (BOP) presented in this paper featured several advantages over conventional hydraulic accumulators including instant large current drive, quick system response and elimination of need for the pressure conduits. However, the mechanical design introduced two challenges, the nonlinear nature of SMA actuators and the varying voltage provided by a super capacitor, for control system design. A cerebellar model articulation controller (CMAC) feedforward plus PID controller was developed with the aim of compensation for these adverse effects. Experiments were conducted on a scaled down model and experimental results show that precision control can be achieved with the proposed configurations and algorithms.

Conceptual design and feasibility evaluation model of a 10 to the 8th power bit oligatomic mass memory. Volume 1: Conceptual design

NASA Technical Reports Server (NTRS)

Recksiedler, A. L.; Lutes, C. L.

1972-01-01

The oligatomic (mirror) thin film memory technology is a suitable candidate for general purpose spaceborne applications in the post-1975 time frame. Capacities of around 10 to the 8th power bits can be reliably implemented with systems designed around a 335 million bit module. The recommended mode was determined following an investigation of implementation sizes ranging from an 8,000,000 to 100,000,000 bits per module. Cost, power, weight, volume, reliability, maintainability and speed were investigated. The memory includes random access, NDRO, SEC-DED, nonvolatility, and dual interface characteristics. The applications most suitable for the technology are those involving a large capacity with high speed (no latency), nonvolatility, and random accessing.

Hearing loss is negatively related to episodic and semantic long-term memory but not to short-term memory.

PubMed

Rönnberg, Jerker; Danielsson, Henrik; Rudner, Mary; Arlinger, Stig; Sternäng, Ola; Wahlin, Ake; Nilsson, Lars-Göran

2011-04-01

To test the relationship between degree of hearing loss and different memory systems in hearing aid users. Structural equation modeling (SEM) was used to study the relationship between auditory and visual acuity and different cognitive and memory functions in an age-hetereogenous subsample of 160 hearing aid users without dementia, drawn from the Swedish prospective cohort aging study known as Betula (L.-G. Nilsson et al., 1997). Hearing loss was selectively and negatively related to episodic and semantic long-term memory (LTM) but not short-term memory (STM) performance. This held true for both ears, even when age was accounted for. Visual acuity alone, or in combination with auditory acuity, did not contribute to any acceptable SEM solution. The overall relationships between hearing loss and memory systems were predicted by the ease of language understanding model (J. Rönnberg, 2003), but the exact mechanisms of episodic memory decline in hearing aid users (i.e., mismatch/disuse, attentional resources, or information degradation) remain open for further experiments. The hearing aid industry should strive to design signal processing algorithms that are cognition friendly.

Cognitive memory.

PubMed

Widrow, Bernard; Aragon, Juan Carlos

2013-05-01

Regarding the workings of the human mind, memory and pattern recognition seem to be intertwined. You generally do not have one without the other. Taking inspiration from life experience, a new form of computer memory has been devised. Certain conjectures about human memory are keys to the central idea. The design of a practical and useful "cognitive" memory system is contemplated, a memory system that may also serve as a model for many aspects of human memory. The new memory does not function like a computer memory where specific data is stored in specific numbered registers and retrieval is done by reading the contents of the specified memory register, or done by matching key words as with a document search. Incoming sensory data would be stored at the next available empty memory location, and indeed could be stored redundantly at several empty locations. The stored sensory data would neither have key words nor would it be located in known or specified memory locations. Sensory inputs concerning a single object or subject are stored together as patterns in a single "file folder" or "memory folder". When the contents of the folder are retrieved, sights, sounds, tactile feel, smell, etc., are obtained all at the same time. Retrieval would be initiated by a query or a prompt signal from a current set of sensory inputs or patterns. A search through the memory would be made to locate stored data that correlates with or relates to the prompt input. The search would be done by a retrieval system whose first stage makes use of autoassociative artificial neural networks and whose second stage relies on exhaustive search. Applications of cognitive memory systems have been made to visual aircraft identification, aircraft navigation, and human facial recognition. Concerning human memory, reasons are given why it is unlikely that long-term memory is stored in the synapses of the brain's neural networks. Reasons are given suggesting that long-term memory is stored in DNA or RNA. Neural networks are an important component of the human memory system, and their purpose is for information retrieval, not for information storage. The brain's neural networks are analog devices, subject to drift and unplanned change. Only with constant training is reliable action possible. Good training time is during sleep and while awake and making use of one's memory. A cognitive memory is a learning system. Learning involves storage of patterns or data in a cognitive memory. The learning process for cognitive memory is unsupervised, i.e. autonomous. Copyright © 2013 Elsevier Ltd. All rights reserved.

Interactive Volume Exploration of Petascale Microscopy Data Streams Using a Visualization-Driven Virtual Memory Approach.

PubMed

Hadwiger, M; Beyer, J; Jeong, Won-Ki; Pfister, H

2012-12-01

This paper presents the first volume visualization system that scales to petascale volumes imaged as a continuous stream of high-resolution electron microscopy images. Our architecture scales to dense, anisotropic petascale volumes because it: (1) decouples construction of the 3D multi-resolution representation required for visualization from data acquisition, and (2) decouples sample access time during ray-casting from the size of the multi-resolution hierarchy. Our system is designed around a scalable multi-resolution virtual memory architecture that handles missing data naturally, does not pre-compute any 3D multi-resolution representation such as an octree, and can accept a constant stream of 2D image tiles from the microscopes. A novelty of our system design is that it is visualization-driven: we restrict most computations to the visible volume data. Leveraging the virtual memory architecture, missing data are detected during volume ray-casting as cache misses, which are propagated backwards for on-demand out-of-core processing. 3D blocks of volume data are only constructed from 2D microscope image tiles when they have actually been accessed during ray-casting. We extensively evaluate our system design choices with respect to scalability and performance, compare to previous best-of-breed systems, and illustrate the effectiveness of our system for real microscopy data from neuroscience.

Knowledge representation and user interface concepts to support mixed-initiative diagnosis

NASA Technical Reports Server (NTRS)

Sobelman, Beverly H.; Holtzblatt, Lester J.

1989-01-01

The Remote Maintenance Monitoring System (RMMS) provides automated support for the maintenance and repair of ModComp computer systems used in the Launch Processing System (LPS) at Kennedy Space Center. RMMS supports manual and automated diagnosis of intermittent hardware failures, providing an efficient means for accessing and analyzing the data generated by catastrophic failure recovery procedures. This paper describes the design and functionality of the user interface for interactive analysis of memory dump data, relating it to the underlying declarative representation of memory dumps.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

Josephson 4 K-bit cache memory design for a prototype signal processor. I - General overview

NASA Astrophysics Data System (ADS)

Henkels, W. H.; Geppert, L. M.; Kadlec, J.; Epperlein, P. W.; Beha, H.

1985-09-01

In the early stages of thg Josephson computer project conducted at an American computer company, it was recognized that a very fast cache memory was needed to complement Josephson logic. A subnanosecond access time memory was implemented experimentally on the basis of a 2.5-micron Pb-alloy technology. It was then decided to switch over to a Nb-base-electrode technology with the objective to alleviate problems with the long-term reliability and aging of Pb-based junctions. The present paper provides a general overview of the status of a 4 x 1 K-bit Josephson cache design employing a 2.5-micron Nb-edge-junction technology. Attention is given to the fabrication process and its implications, aspects of circuit design methodology, an overview of system environment and chip components, design changes and status, and various difficulties and uncertainties.

Evaluating Non-In-Place Update Techniques for Flash-Based Transaction Processing Systems

NASA Astrophysics Data System (ADS)

Wang, Yongkun; Goda, Kazuo; Kitsuregawa, Masaru

Recently, flash memory is emerging as the storage device. With price sliding fast, the cost per capacity is approaching to that of SATA disk drives. So far flash memory has been widely deployed in consumer electronics even partly in mobile computing environments. For enterprise systems, the deployment has been studied by many researchers and developers. In terms of the access performance characteristics, flash memory is quite different from disk drives. Without the mechanical components, flash memory has very high random read performance, whereas it has a limited random write performance because of the erase-before-write design. The random write performance of flash memory is comparable with or even worse than that of disk drives. Due to such a performance asymmetry, naive deployment to enterprise systems may not exploit the potential performance of flash memory at full blast. This paper studies the effectiveness of using non-in-place-update (NIPU) techniques through the IO path of flash-based transaction processing systems. Our deliberate experiments using both open-source DBMS and commercial DBMS validated the potential benefits; x3.0 to x6.6 performance improvement was confirmed by incorporating non-in-place-update techniques into file system without any modification of applications or storage devices.

From brain synapses to systems for learning and memory: Object recognition, spatial navigation, timed conditioning, and movement control.

PubMed

Grossberg, Stephen

2015-09-24

This article provides an overview of neural models of synaptic learning and memory whose expression in adaptive behavior depends critically on the circuits and systems in which the synapses are embedded. It reviews Adaptive Resonance Theory, or ART, models that use excitatory matching and match-based learning to achieve fast category learning and whose learned memories are dynamically stabilized by top-down expectations, attentional focusing, and memory search. ART clarifies mechanistic relationships between consciousness, learning, expectation, attention, resonance, and synchrony. ART models are embedded in ARTSCAN architectures that unify processes of invariant object category learning, recognition, spatial and object attention, predictive remapping, and eye movement search, and that clarify how conscious object vision and recognition may fail during perceptual crowding and parietal neglect. The generality of learned categories depends upon a vigilance process that is regulated by acetylcholine via the nucleus basalis. Vigilance can get stuck at too high or too low values, thereby causing learning problems in autism and medial temporal amnesia. Similar synaptic learning laws support qualitatively different behaviors: Invariant object category learning in the inferotemporal cortex; learning of grid cells and place cells in the entorhinal and hippocampal cortices during spatial navigation; and learning of time cells in the entorhinal-hippocampal system during adaptively timed conditioning, including trace conditioning. Spatial and temporal processes through the medial and lateral entorhinal-hippocampal system seem to be carried out with homologous circuit designs. Variations of a shared laminar neocortical circuit design have modeled 3D vision, speech perception, and cognitive working memory and learning. A complementary kind of inhibitory matching and mismatch learning controls movement. This article is part of a Special Issue entitled SI: Brain and Memory. Copyright © 2014 Elsevier B.V. All rights reserved.

Features of the solar array drive mechanism for the space telescope

NASA Technical Reports Server (NTRS)

Hostenkamp, R. G.

1985-01-01

The solar array drive mechanism for the Space Telescope embodies several features not customarily found on solar array drives. Power and signal transfer is achieved by means of a flexible wire harness for which the chosen solution, consisting of 168 standard wires, is described. The torque performance data of the harness over its temperature range are presented. The off load system which protects the bearings from the launch loads is released by a trigger made from Nitinol, the memory alloy. The benefits of memory alloy and the caveats for the design are briefly discussed. The design of the off load system is described and test experience is reported.

Electroactive polymer and shape memory alloy actuators in biomimetics and humanoids

NASA Astrophysics Data System (ADS)

Tadesse, Yonas

2013-04-01

There is a strong need to replicate natural muscles with artificial materials as the structure and function of natural muscle is optimum for articulation. Particularly, the cylindrical shape of natural muscle fiber and its interconnected structure promote the critical investigation of artificial muscles geometry and implementation in the design phase of certain platforms. Biomimetic robots and Humanoid Robot heads with Facial Expressions (HRwFE) are some of the typical platforms that can be used to study the geometrical effects of artificial muscles. It has been shown that electroactive polymer and shape memory alloy artificial muscles and their composites are some of the candidate materials that may replicate natural muscles and showed great promise for biomimetics and humanoid robots. The application of these materials to these systems reveals the challenges and associated technologies that need to be developed in parallel. This paper will focus on the computer aided design (CAD) models of conductive polymer and shape memory alloys in various biomimetic systems and Humanoid Robot with Facial Expressions (HRwFE). The design of these systems will be presented in a comparative manner primarily focusing on three critical parameters: the stress, the strain and the geometry of the artificial muscle.

Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

NASA Astrophysics Data System (ADS)

Liu, T.; Deptuch, G.; Hoff, J.; Jindariani, S.; Joshi, S.; Olsen, J.; Tran, N.; Trimpl, M.

2015-02-01

An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the short latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking; in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.

Design and testing of the first 2D Prototype Vertically Integrated Pattern Recognition Associative Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, T.; Deptuch, G.; Hoff, J.

An associative memory-based track finding approach has been proposed for a Level 1 tracking trigger to cope with increasing luminosities at the LHC. The associative memory uses a massively parallel architecture to tackle the intrinsically complex combinatorics of track finding algorithms, thus avoiding the typical power law dependence of execution time on occupancy and solving the pattern recognition in times roughly proportional to the number of hits. This is of crucial importance given the large occupancies typical of hadronic collisions. The design of an associative memory system capable of dealing with the complexity of HL-LHC collisions and with the shortmore » latency required by Level 1 triggering poses significant, as yet unsolved, technical challenges. For this reason, an aggressive R&D program has been launched at Fermilab to advance state of-the-art associative memory technology, the so called VIPRAM (Vertically Integrated Pattern Recognition Associative Memory) project. The VIPRAM leverages emerging 3D vertical integration technology to build faster and denser Associative Memory devices. The first step is to implement in conventional VLSI the associative memory building blocks that can be used in 3D stacking, in other words, the building blocks are laid out as if it is a 3D design. In this paper, we report on the first successful implementation of a 2D VIPRAM demonstrator chip (protoVIPRAM00). The results show that these building blocks are ready for 3D stacking.« less

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jones, J.P.; Bangs, A.L.; Butler, P.L.

Hetero Helix is a programming environment which simulates shared memory on a heterogeneous network of distributed-memory computers. The machines in the network may vary with respect to their native operating systems and internal representation of numbers. Hetero Helix presents a simple programming model to developers, and also considers the needs of designers, system integrators, and maintainers. The key software technology underlying Hetero Helix is the use of a compiler'' which analyzes the data structures in shared memory and automatically generates code which translates data representations from the format native to each machine into a common format, and vice versa. Themore » design of Hetero Helix was motivated in particular by the requirements of robotics applications. Hetero Helix has been used successfully in an integration effort involving 27 CPUs in a heterogeneous network and a body of software totaling roughly 100,00 lines of code. 25 refs., 6 figs.« less

Behavior of Shape Memory Epoxy Foams in Microgravity: Experimental Results of STS-134 Mission

NASA Astrophysics Data System (ADS)

Santo, Loredana; Quadrini, Fabrizio; Squeo, Erica Anna; Dolce, Ferdinando; Mascetti, Gabriele; Bertolotto, Delfina; Villadei, Walter; Ganga, Pier Luigi; Zolesi, Valfredo

2012-09-01

Shape memory epoxy foams were used for an experiment on the International Space Station to evaluate the feasibility of their use for building multi-functional composite structures. A small equipment was designed and built to simulate the actuation of simple devices in micro-gravity conditions: three different configurations (compression, bending and torsion) were chosen during the memory step of the foams so as to produce their recovery on ISS. Two systems were used for the experimentation to avoid damages of the flight model during laboratory tests; however a single ground experiment was performed also on the flight model before the mission. Micro-gravity does not affect the ability of the foams to recover their shape but it poses strong limits for the heating system design because of the difference in heat transfer on earth and in orbit. A full recovery of the foam samples was not achieved due to some limitations in the maximum allowable temperature on ISS for safety reasons: anyway a 70% recovery was also measured at a temperature of 110°C. Ground laboratory experiments showed that 100% recovery could be reached by increasing the maximum temperature to 120°C. Experiment results have provided many useful information for the designing of a new structural composite actuator by using shape memory foams.

Chip architecture - A revolution brewing

NASA Astrophysics Data System (ADS)

Guterl, F.

1983-07-01

Techniques being explored by microchip designers and manufacturers to both speed up memory access and instruction execution while protecting memory are discussed. Attention is given to hardwiring control logic, pipelining for parallel processing, devising orthogonal instruction sets for interchangeable instruction fields, and the development of hardware for implementation of virtual memory and multiuser systems to provide memory management and protection. The inclusion of microcode in mainframes eliminated logic circuits that control timing and gating of the CPU. However, improvements in memory architecture have reduced access time to below that needed for instruction execution. Hardwiring the functions as a virtual memory enhances memory protection. Parallelism involves a redundant architecture, which allows identical operations to be performed simultaneously, and can be directed with microcode to avoid abortion of intermediate instructions once on set of instructions has been completed.

Design of a biomimetic self-healing superalloy composite

NASA Astrophysics Data System (ADS)

Files, Bradley Steven

1997-10-01

Use of systems engineering concepts to design technologically advanced materials has allowed ambitious goals of self-healing alloys to be realized. Shape memory alloy reinforcements are embedded in an alloy matrix to demonstrate concepts of stable crack growth and matrix crack closure. Computer methods are used to design thermodynamically compatible iron-based alloys using bio-inspired concepts of crack bridging and self-healing. Feasibility of crack closure and stable crack growth is shown in a prototype system with a Sn-Bi matrix and TiNi fibers. Design of Fe-Ni-Co-Ti-Al alloys using thermodynamic models to determine stabilities and phase equilibria allows for a methodical system designing compatible multicomponent alloys for composite systems. Final alloy computations for this project led to the alloy Fe-27.6Ni-18.2Co-4.1Ti-1.6Al as a compatible shape memory a with a 650sp°C 90 minute heat treatment leading to martensite and austenite start temperatures (Msbs and Asbs) near room temperature. Thin slices of this alloy were able to fully recover at least 5% strain upon unloading heating. Composites made from the designed shape memory alloy and a compatible Fe-based B2 matrix were used to test self-healing concepts in the superalloy system. Diffusion couple experiments verified thermodynamic compatibility between matrix and reinforcement alloys at the solution treatment temperature of 1100sp°C. Concepts of stable crack growth and crack bridging were demonstrated in the composite, leading to enhanced toughness of the brittle matrix. However, healing behavior in this system was limited by intergranular fracture of the reinforcement alloy. It is believed that use of rapidly solidified powders could eliminate intergranular fracture, leading to greatly enhanced properties of toughening and healing. Crack clamping and stable crack growth were achieved in a feasibility study using a Sn-Bi matrix reinforced with TiNi fibers. Tensile specimens with less than 1% fibers showed an ability upon heating to recover over 80% of the plastic deformation induced during a tensile test. Further straining proved that stable crack growth can be realized in this system due to crack bridging of the shape memory fibers. Macroscopic cracks were clamped shut after heating of the material above the TiNi reversion temperature.

Investigation and design of a Project Management Decision Support System for the 4950th Test Wing.

DTIC Science & Technology

1986-03-01

all decision makers is the need for memory aids (reports, hand written notes, mental memory joggers, etc.). 4. Even in similar decision making ... memories to synthesize a decision- making process based on their individual styles, skills, and knowledge (Sprague, 1982: 106). Control mechanisms...representations shown in Figures 4.9 and 4.10 provide a means to this objective. By enabling a manager to make and record reasonable changes to

CREB regulates memory allocation in the insular cortex

PubMed Central

Sano, Yoshitake; Shobe, Justin L.; Zhou, Miou; Huang, Shan; Shuman, Tristan; Cai, Denise J.; Golshani, Peyman; Kamata, Masakazu; Silva, Alcino J.

2016-01-01

Summary The molecular and cellular mechanisms of memory storage have attracted a great deal of attention. By comparison, little is known about memory allocation, the process that determines which specific neurons in a neural network will store a given memory [1, 2]. Previous studies demonstrated that memory allocation is not random in the amygdala; these studies showed that amygdala neurons with higher levels of the cAMP response element binding protein (CREB) are more likely to be recruited into encoding and storing fear memory [3–6]. To determine whether specific mechanisms also regulate memory allocation in other brain regions, and whether CREB also has a role in this process, we studied insular cortical memory representations for conditioned taste aversion (CTA). In this task, an animal learns to associate a taste (CS) with the experience of malaise (such as that induced by LiCl; US). The insular cortex is required for CTA memory formation and retrieval [7–12]. CTA learning activates a subpopulation of neurons in this structure [13–15], and the insular cortex and the basolateral amygdala (BLA) interact during CTA formation [16, 17]. Here, we used a combination of approaches, including viral vector transfections of insular cortex, arc Fluorescence In Situ Hybridization (FISH) and Designer Receptors Exclusively Activated by Designer Drugs (DREADD) system, to show that CREB levels determine which insular cortical neurons go on to encode a given conditioned taste memory. PMID:25454591

Characterization and application of Shape Memory Alloy wires for micro and meso positioning systems

NASA Astrophysics Data System (ADS)

Khan, Afzal

The properties of Shape Memory Alloy (SMA) wires are determined by experimentation, and previously used experimental equipment contributes to measurement errors in data. In this study, various characterization experiments are designed and carried out using a precision characterization instrument for shape memory alloy wires to determine the properties and parameters of the alloy. These experiments demonstrate the behavior of SMA wires under different thermal and loading conditions as they occur in actuation applications. As SMA wires go through phase transformation, a significant amount of contraction force is produced. This actuation force has been used in bias spring actuators and differential actuators. In this dissertation, the force generated during the twinning of martensite is used to actuate positioning systems with small displacements at the micrometer level. A micropositioning system is designed and tested that has a positioning accuracy of about +/-0.15 mum. A relation between the current input and the displacement output is determined for the specific preload. The transformation force generated during the phase change from martensite to austenite is used as an actuation force for a second positioning system that uses linear bearing with a displacement range of about a millimeter. This positioning system actuated with a single nitinol wire and guided by symmetric parallel diaphragm flexures, was designed and tested. The actuation is repeatable to about +/-15 mum with variation of about +/-5 mum in postion at steady temperature.

A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; King, Brent

1995-01-01

This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

SUMC fault tolerant computer system

NASA Technical Reports Server (NTRS)

1980-01-01

The results of the trade studies are presented. These trades cover: establishing the basic configuration, establishing the CPU/memory configuration, establishing an approach to crosstrapping interfaces, defining the requirements of the redundancy management unit (RMU), establishing a spare plane switching strategy for the fault-tolerant memory (FTM), and identifying the most cost effective way of extending the memory addressing capability beyond the 64 K-bytes (K=1024) of SUMC-II B. The results of the design are compiled in Contract End Item (CEI) Specification for the NASA Standard Spacecraft Computer II (NSSC-II), IBM 7934507. The implementation of the FTM and memory address expansion.

Prospective memory failures in aviation: effects of cue salience, workload, and individual differences.

PubMed

Van Benthem, Kathleen D; Herdman, Chris M; Tolton, Rani G; LeFevre, Jo-Anne

2015-04-01

Prospective memory allows people to complete intended tasks in the future. Prospective memory failures, such as pilots forgetting to inform pattern traffic of their locations, can have fatal consequences. The present research examined the impact of system factors (memory cue salience and workload) and individual differences (pilot age, cognitive health, and expertise) on prospective memory for communication tasks in the cockpit. Pilots (N = 101) flew a Cessna 172 simulator at a non-towered aerodrome while maintaining communication with traffic and attending to flight parameters. Memory cue salience (the prominence of cues that signal an intended action) and workload were manipulated. Prospective memory was measured as radio call completion rates. Pilots' prospective memory was adversely affected by low-salience cues and high workload. An interaction of cue salience, pilots' age, and cognitive health reflected the effects of system and individual difference factors on prospective memory failures. For example, younger pilots with low levels of cognitive health completed 78% of the radio calls associated with low-salience memory cues, whereas older pilots with low cognitive health scores completed just 61% of similar radio calls. Our findings suggest that technologies designed to signal intended future tasks should target those tasks with inherently low-salience memory cues. In addition, increasing the salience of memory cues is most likely to benefit pilots with lower levels of cognitive health in high-workload conditions.

Improved memory for reward cues following acute buprenorphine administration in humans.

PubMed

Syal, Supriya; Ipser, Jonathan; Terburg, David; Solms, Mark; Panksepp, Jaak; Malcolm-Smith, Susan; Bos, Peter A; Montoya, Estrella R; Stein, Dan J; van Honk, Jack

2015-03-01

In rodents, there is abundant evidence for the involvement of the opioid system in the processing of reward cues, but this system has remained understudied in humans. In humans, the happy facial expression is a pivotal reward cue. Happy facial expressions activate the brain's reward system and are disregarded by subjects scoring high on depressive mood who are low in reward drive. We investigated whether a single 0.2mg administration of the mixed mu-opioid agonist/kappa-antagonist, buprenorphine, would influence short-term memory for happy, angry or fearful expressions relative to neutral faces. Healthy human subjects (n38) participated in a randomized placebo-controlled within-subject design, and performed an emotional face relocation task after administration of buprenorphine and placebo. We show that, compared to placebo, buprenorphine administration results in a significant improvement of memory for happy faces. Our data demonstrate that acute manipulation of the opioid system by buprenorphine increases short-term memory for social reward cues. Copyright © 2015. Published by Elsevier Ltd.

PANDA: A distributed multiprocessor operating system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chubb, P.

1989-01-01

PANDA is a design for a distributed multiprocessor and an operating system. PANDA is designed to allow easy expansion of both hardware and software. As such, the PANDA kernel provides only message passing and memory and process management. The other features needed for the system (device drivers, secondary storage management, etc.) are provided as replaceable user tasks. The thesis presents PANDA's design and implementation, both hardware and software. PANDA uses multiple 68010 processors sharing memory on a VME bus, each such node potentially connected to others via a high speed network. The machine is completely homogeneous: there are no differencesmore » between processors that are detectable by programs running on the machine. A single two-processor node has been constructed. Each processor contains memory management circuits designed to allow processors to share page tables safely. PANDA presents a programmers' model similar to the hardware model: a job is divided into multiple tasks, each having its own address space. Within each task, multiple processes share code and data. Tasks can send messages to each other, and set up virtual circuits between themselves. Peripheral devices such as disc drives are represented within PANDA by tasks. PANDA divides secondary storage into volumes, each volume being accessed by a volume access task, or VAT. All knowledge about the way that data is stored on a disc is kept in its volume's VAT. The design is such that PANDA should provide a useful testbed for file systems and device drivers, as these can be installed without recompiling PANDA itself, and without rebooting the machine.« less

Engineering Design Tools for Shape Memory Alloy Actuators: CASMART Collaborative Best Practices and Case Studies

NASA Technical Reports Server (NTRS)

Wheeler, Robert W.; Benafan, Othmane; Gao, Xiujie; Calkins, Frederick T; Ghanbari, Zahra; Hommer, Garrison; Lagoudas, Dimitris; Petersen, Andrew; Pless, Jennifer M.; Stebner, Aaron P.;

New trends in logic synthesis for both digital designing and data processing

NASA Astrophysics Data System (ADS)

Borowik, Grzegorz; Łuba, Tadeusz; Poźniak, Krzysztof

2016-09-01

FPGA devices are equipped with memory-based structures. These memories act as very large logic cells where the number of inputs equals the number of address lines. At the same time, there is a huge demand in the market of Internet of Things for devices implementing virtual routers, intrusion detection systems, etc.; where such memories are crucial for realizing pattern matching circuits, IP address tables, and other. Unfortunately, existing CAD tools are not well suited to utilize capabilities that such large memory blocks offer due to the lack of appropriate synthesis procedures. This paper presents methods which are useful for memory-based implementations: minimization of the number of input variables and functional decomposition.

SEPAC flight software detailed design specifications, volume 1

NASA Technical Reports Server (NTRS)

1982-01-01

The detailed design specifications (as built) for the SEPAC Flight Software are defined. The design includes a description of the total software system and of each individual module within the system. The design specifications describe the decomposition of the software system into its major components. The system structure is expressed in the following forms: the control-flow hierarchy of the system, the data-flow structure of the system, the task hierarchy, the memory structure, and the software to hardware configuration mapping. The component design description includes details on the following elements: register conventions, module (subroutines) invocaton, module functions, interrupt servicing, data definitions, and database structure.

Design and Fabrication of Aspheric Microlens Array for Optical Read-Only-Memory Card System

NASA Astrophysics Data System (ADS)

Kim, Hongmin; Jeong, Gibong; Kim, Young‑Joo; Kang, Shinill

2006-08-01

An optical head based on the Talbot effect with an aspheric microlens array for an optical read-only-memory (ROM) card system was designed and fabricated. The mathematical expression for the wavefield diffracted by a periodic microlens array showed that the amplitude distribution at the Talbot plane from the focal plane of the microlens array was identically equal to that at the focal plane. To use a reflow microlens array as a master pattern of an ultraviolet-imprinted (UV-imprinted) microlens array, the reflow microlens was defined as having an aspheric shape. To obtain optical probes with good optical qualities, a microlens array with the minimum spherical aberration was designed by ray tracing. The reflow condition was optimized to realize the master pattern of a microlens with a designed aspheric shape. The intensity distribution of the optical probes at the Talbot plane from the focal plane showed a diffraction-limited shape.

Set-Membership Identification for Robust Control Design

DTIC Science & Technology

1993-04-28

system G can be regarded as having no memory in (18) in terms of G and 0, we get of events prior to t = 1, the initial time. Roughly, this means all...algorithm in [1]. Also in our application, the size of the matrices involved is quite large and special attention should be paid to the memory ...management and algorithmic implementation; otherwise huge amounts of memory will be required to perform the optimization even for modest values of M and N

Android Protection Mechanism: A Signed Code Security Mechanism for Smartphone Applications

DTIC Science & Technology

2011-03-01

status registers, exceptions, endian support, unaligned access support, synchronization primitives , the Jazelle Extension, and saturated integer...supports comprehensive non-blocking shared-memory synchronization primitives that scale for multiple-processor system designs. This is an improvement... synchronization . Memory semaphores can be loaded and altered without interruption because the load and store operations are atomic. Processor

Providing the Public with Online Access to Large Bibliographic Data Bases.

ERIC Educational Resources Information Center

Firschein, Oscar; Summit, Roger K.

DIALOG, an interactive, computer-based information retrieval language, consists of a series of computer programs designed to make use of direct access memory devices in order to provide the user with a rapid means of identifying records within a specific memory bank. Using the system, a library user can be provided access to sixteen distinct and…

Studies of Human Memory and Language Processing.

ERIC Educational Resources Information Center

Collins, Allan M.

The purposes of this study were to determine the nature of human semantic memory and to obtain knowledge usable in the future development of computer systems that can converse with people. The work was based on a computer model which is designed to comprehend English text, relating the text to information stored in a semantic data base that is…

A microprogrammed data acquisition system for renography.

PubMed

Imperiale, C

1983-01-01

The purpose of this project was to design an efficient, low cost, and portable system for renography suitable for clinical use. The principles involved in the renographic test, and the procedures and calculations which act on the design of our system, are given. The system consists of an Apple II Plus computer equipped with 48K memory, two disk drives with diskettes of 143K each, a thermal printer with graphic capability, the Microsoft Z80 card, and an interface which is specifically designed for renographic data acquisition.

Portable wireless neurofeedback system of EEG alpha rhythm enhances memory.

PubMed

Wei, Ting-Ying; Chang, Da-Wei; Liu, You-De; Liu, Chen-Wei; Young, Chung-Ping; Liang, Sheng-Fu; Shaw, Fu-Zen

2017-11-13

Effect of neurofeedback training (NFT) on enhancement of cognitive function or amelioration of clinical symptoms is inconclusive. The trainability of brain rhythm using a neurofeedback system is uncertainty because various experimental designs are used in previous studies. The current study aimed to develop a portable wireless NFT system for alpha rhythm and to validate effect of the NFT system on memory with a sham-controlled group. The proposed system contained an EEG signal analysis device and a smartphone with wireless Bluetooth low-energy technology. Instantaneous 1-s EEG power and contiguous 5-min EEG power throughout the training were developed as feedback information. The training performance and its progression were kept to boost usability of our device. Participants were blinded and randomly assigned into either the control group receiving random 4-Hz power or Alpha group receiving 8-12-Hz power. Working memory and episodic memory were assessed by the backward digital span task and word-pair task, respectively. The portable neurofeedback system had advantages of a tiny size and long-term recording and demonstrated trainability of alpha rhythm in terms of significant increase of power and duration of 8-12 Hz. Moreover, accuracies of the backward digital span task and word-pair task showed significant enhancement in the Alpha group after training compared to the control group. Our tiny portable device demonstrated success trainability of alpha rhythm and enhanced two kinds of memories. The present study suggest that the portable neurofeedback system provides an alternative intervention for memory enhancement.

Air Support Control Officer Individual Position Training Simulation

DTIC Science & Technology

2017-06-01

Analysis design development implementation evaluation ASCO Air support control officer ASLT Air support liaison team ASNO Air support net operator...Instructional system design LSTM Long-short term memory MACCS Marine Air Command and Control System MAGTF Marine Air Ground Task Force MASS Marine Air...information to designated MACCS agencies. ASCOs play an important part in facilitating the safe and successful conduct of air operations in DASC- controlled

The ASSIST: Bringing Information and Software Together for Scientists

NASA Technical Reports Server (NTRS)

Mandel, Eric

1997-01-01

The ASSIST was developed as a step toward overcoming the problems faced by researchers when trying to utilize complex and often conflicting astronomical data analysis systems. It implements a uniform graphical interface to analysis systems, documentation, data, and organizational memory. It is layered on top of the Answer Garden Substrate (AGS), a system specially designed to facilitate the collection and dissemination of organizational memory. Under the AISRP program, we further developed the ASSIST to make it even easier for researchers to overcome the difficulties of accessing software and information in a complex computer environment.

Measuring autobiographical fluency in the self-memory system.

PubMed

Rathbone, Clare J; Moulin, Chris J A

2014-01-01

Autobiographical memory is widely considered to be fundamentally related to concepts of self and identity. However, few studies have sought to test models of self and memory directly using experimental designs. Using a novel autobiographical fluency paradigm, the present study investigated memory accessibility for different levels of self-related knowledge. Forty participants generated 20 "I am" statements about themselves, from which the 1st, 5th, 10th, 15th, and 20th were used as cues in a two-minute autobiographical fluency task. The most salient aspects of the self, measured by both serial position and ratings of personal significance, were associated with more accessible sets of autobiographical memories. This finding supports theories that view the self as a powerful organizational structure in memory. Results are discussed with reference to models of self and memory.

Reed Solomon codes for error control in byte organized computer memory systems

NASA Technical Reports Server (NTRS)

Lin, S.; Costello, D. J., Jr.

1984-01-01

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial.

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

DOE PAGES

Mittal, Sparsh; Vetter, Jeffrey S.

2015-04-24

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made `reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. In this study, we provide a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory, GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based onmore » their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. Finally, we believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.« less

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh; Vetter, Jeffrey S.

Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made `reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. In this study, we provide a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory, GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based onmore » their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. Finally, we believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.« less

Toshiba TDF-500 High Resolution Viewing And Analysis System

NASA Astrophysics Data System (ADS)

Roberts, Barry; Kakegawa, M.; Nishikawa, M.; Oikawa, D.

1988-06-01

A high resolution, operator interactive, medical viewing and analysis system has been developed by Toshiba and Bio-Imaging Research. This system provides many advanced features including high resolution displays, a very large image memory and advanced image processing capability. In particular, the system provides CRT frame buffers capable of update in one frame period, an array processor capable of image processing at operator interactive speeds, and a memory system capable of updating multiple frame buffers at frame rates whilst supporting multiple array processors. The display system provides 1024 x 1536 display resolution at 40Hz frame and 80Hz field rates. In particular, the ability to provide whole or partial update of the screen at the scanning rate is a key feature. This allows multiple viewports or windows in the display buffer with both fixed and cine capability. To support image processing features such as windowing, pan, zoom, minification, filtering, ROI analysis, multiplanar and 3D reconstruction, a high performance CPU is integrated into the system. This CPU is an array processor capable of up to 400 million instructions per second. To support the multiple viewer and array processors' instantaneous high memory bandwidth requirement, an ultra fast memory system is used. This memory system has a bandwidth capability of 400MB/sec and a total capacity of 256MB. This bandwidth is more than adequate to support several high resolution CRT's and also the fast processing unit. This fully integrated approach allows effective real time image processing. The integrated design of viewing system, memory system and array processor are key to the imaging system. It is the intention to describe the architecture of the image system in this paper.

Design of membrane actuators based on ferromagnetic shape memory alloy composite for the synthetic jet actuator

NASA Astrophysics Data System (ADS)

Liang, Yuanchang; Taya, Minoru; Kuga, Yasuo

2004-07-01

A new membrane actuator based on our previous diaphragm actuator was designed and constructed to improve the dynamic performance. The finite element analysis was used to estimate the frequency response of the composite membrane which will be driven close to its resonance to obtain a large stroke. The membrane is made of ferromagnetic shape memory alloy (FSMA) composite including a ferromagnetic soft iron pad and a superelastic grade of NiTi shape memory alloy (SMA). The actuation mechanism for the FSMA composite membrane of the actuator is the hybrid mechanism that we proposed previously. This membrane actuator is designed for a new synthetic jet actuator package that will be used for active flow control technology on airplane wings. Based on the FEM results, the new membrane actuator system was assembled and its static and dynamic performance was experimentally evaluated including the dynamic magnetic response of the hybrid magnet.

Evolution of cellular automata with memory: The Density Classification Task.

PubMed

Stone, Christopher; Bull, Larry

2009-08-01

The Density Classification Task is a well known test problem for two-state discrete dynamical systems. For many years researchers have used a variety of evolutionary computation approaches to evolve solutions to this problem. In this paper, we investigate the evolvability of solutions when the underlying Cellular Automaton is augmented with a type of memory based on the Least Mean Square algorithm. To obtain high performance solutions using a simple non-hybrid genetic algorithm, we design a novel representation based on the ternary representation used for Learning Classifier Systems. The new representation is found able to produce superior performance to the bit string traditionally used for representing Cellular automata. Moreover, memory is shown to improve evolvability of solutions and appropriate memory settings are able to be evolved as a component part of these solutions.

Study and Design of Flight Data Recording Systems for Military Aircraft

DTIC Science & Technology

1976-06-01

minicomputer (PDP-11/ 40 ) with 24K of core memory and a disk operating system. Peripherals include a CRT terminal, two 9-track magnetic tape drives, a 19 high...in question-answer mode. The NTSB plans to adapt an existing routine to the PDP 11/ 40 which will prepare a ground track of the aircraft from the...20 microseconds). Like PMOS memory, multiple power supplies were required. The next generation of microprocessors were implemented on a 40 pin package

Integrating Software Modules For Robot Control

NASA Technical Reports Server (NTRS)

Volpe, Richard A.; Khosla, Pradeep; Stewart, David B.

1993-01-01

Reconfigurable, sensor-based control system uses state variables in systematic integration of reusable control modules. Designed for open-architecture hardware including many general-purpose microprocessors, each having own local memory plus access to global shared memory. Implemented in software as extension of Chimera II real-time operating system. Provides transparent computing mechanism for intertask communication between control modules and generic process-module architecture for multiprocessor realtime computation. Used to control robot arm. Proves useful in variety of other control and robotic applications.

Environmental Containment Property Estimation Using QSARs in an Expert System

DTIC Science & Technology

1993-01-15

2 megabytes of memory (RAM), with 1000 kBytes of memory allocated for HyperCard. PEP overview The PEP system currently consists of four HyperCard...BCF Universel I ’ mI Figure 6. TSA module card from PEP The TSA module is also designed to accept files generated by other hardware/software... allocated to 1500 MB. * Installation of PEP PEP is typically shipped on one 3.5 inch 1.44 Megabyte floppy disk. To install PEP: 1. Insert the PEP disk into

Hypercluster Parallel Processor

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Cole, Gary L.; Milner, Edward J.; Quealy, Angela

1992-01-01

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Spacecraft optical disk recorder memory buffer control

NASA Technical Reports Server (NTRS)

Hodson, Robert F.

1992-01-01

The goal of this project is to develop an Application Specific Integrated Circuit (ASIC) for use in the control electronics of the Spacecraft Optical Disk Recorder (SODR). Specifically, this project is to design an extendable memory buffer controller ASIC for rate matching between a system Input/Output port and the SODR's device interface. The aforementioned goal can be partitioned into the following sub-goals: (1) completion of ASIC design and simulation (on-going via ASEE fellowship); (2) ASIC Fabrication (at ASIC manufacturer); and (3) ASIC Testing (NASA/LaRC, Christopher Newport University).

Achieving enlightenment: what do we know about the implicit learning system and its interaction with explicit knowledge?

PubMed

Vidoni, Eric D; Boyd, Lara A

2007-09-01

Two major memory and learning systems operate in the brain: one for facts and ideas (ie, the declarative or explicit system), one for habits and behaviors (ie, the procedural or implicit system). Broadly speaking these two memory systems can operate either in concert or entirely independently of one another during the performance and learning of skilled motor behaviors. This Special Issue article has two parts. In the first, we present a review of implicit motor skill learning that is largely centered on the interactions between declarative and procedural learning and memory. Because distinct neuroanatomical substrates support unique aspects of learning and memory and thus focal injury can cause impairments that are dependent on lesion location, we also broadly consider which brain regions mediate implicit and explicit learning and memory. In the second part of this article, the interactive nature of these two memory systems is illustrated by the presentation of new data that reveal that both learning implicitly and acquiring explicit knowledge through physical practice lead to motor sequence learning. In our new data, we discovered that for healthy individuals use of the implicit versus explicit memory system differently affected variability of performance during acquisition practice; variability was higher early in practice for the implicit group and later in practice for the acquired explicit group. Despite the difference in performance variability, by retention both groups demonstrated comparable change in tracking accuracy and thus, motor sequence learning. Clinicians should be aware of the potential effects of implicit and explicit interactions when designing rehabilitation interventions, particularly when delivering explicit instructions before task practice, working with individuals with focal brain damage, and/or adjusting therapeutic parameters based on acquisition performance variability.

Vascular system modeling in parallel environment - distributed and shared memory approaches

PubMed Central

Jurczuk, Krzysztof; Kretowski, Marek; Bezy-Wendling, Johanne

2011-01-01

The paper presents two approaches in parallel modeling of vascular system development in internal organs. In the first approach, new parts of tissue are distributed among processors and each processor is responsible for perfusing its assigned parts of tissue to all vascular trees. Communication between processors is accomplished by passing messages and therefore this algorithm is perfectly suited for distributed memory architectures. The second approach is designed for shared memory machines. It parallelizes the perfusion process during which individual processing units perform calculations concerning different vascular trees. The experimental results, performed on a computing cluster and multi-core machines, show that both algorithms provide a significant speedup. PMID:21550891

Synthetic Analog and Digital Circuits for Cellular Computation and Memory

PubMed Central

Purcell, Oliver; Lu, Timothy K.

2014-01-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene circuits that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. PMID:24794536

Optical computing, optical memory, and SBIRs at Foster-Miller

NASA Astrophysics Data System (ADS)

Domash, Lawrence H.

1994-03-01

A desktop design and manufacturing system for binary diffractive elements, MacBEEP, was developed with the optical researcher in mind. Optical processing systems for specialized tasks such as cellular automation computation and fractal measurement were constructed. A new family of switchable holograms has enabled several applications for control of laser beams in optical memories. New spatial light modulators and optical logic elements have been demonstrated based on a more manufacturable semiconductor technology. Novel synthetic and polymeric nonlinear materials for optical storage are under development in an integrated memory architecture. SBIR programs enable creative contributions from smaller companies, both product oriented and technology oriented, and support advances that might not otherwise be developed.

General-purpose interface bus for multiuser, multitasking computer system

NASA Technical Reports Server (NTRS)

Generazio, Edward R.; Roth, Don J.; Stang, David B.

1990-01-01

The architecture of a multiuser, multitasking, virtual-memory computer system intended for the use by a medium-size research group is described. There are three central processing units (CPU) in the configuration, each with 16 MB memory, and two 474 MB hard disks attached. CPU 1 is designed for data analysis and contains an array processor for fast-Fourier transformations. In addition, CPU 1 shares display images viewed with the image processor. CPU 2 is designed for image analysis and display. CPU 3 is designed for data acquisition and contains 8 GPIB channels and an analog-to-digital conversion input/output interface with 16 channels. Up to 9 users can access the third CPU simultaneously for data acquisition. Focus is placed on the optimization of hardware interfaces and software, facilitating instrument control, data acquisition, and processing.

Fatigue Resistance of Liquid-assisted Self-repairing Aluminum Alloys Reinforced with Shape Memory Alloys

NASA Technical Reports Server (NTRS)

Wright, M. Clara; Manuel, Michele; Wallace, Terryl

2013-01-01

A self-repairing aluminum-based composite system has been developed using a liquid-assisted healing theory in conjunction with the shape memory effect of wire reinforcements. The metal-metal composite was thermodynamically designed to have a matrix with a relatively even dispersion of a low-melting eutectic phase, allowing for repair of cracks at a predetermined temperature. Additionally, shape memory alloy (SMA) wire reinforcements were used within the composite to provide crack closure. Investigators focused the research on fatigue cracks propagating through the matrix in order to show a proof-of-concept Shape Memory Alloy Self-Healing (SMASH) technology for aeronautical applications.

Two-bit trinary full adder design based on restricted signed-digit numbers

NASA Astrophysics Data System (ADS)

Ahmed, J. U.; Awwal, A. A. S.; Karim, M. A.

1994-08-01

A 2-bit trinary full adder using a restricted set of a modified signed-digit trinary numeric system is designed. When cascaded together to design a multi-bit adder machine, the resulting system is able to operate at a speed independent of the size of the operands. An optical non-holographic content addressable memory based on binary coded arithmetic is considered for implementing the proposed adder.

YAPPA: a Compiler-Based Parallelization Framework for Irregular Applications on MPSoCs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lovergine, Silvia; Tumeo, Antonino; Villa, Oreste

Modern embedded systems include hundreds of cores. Because of the difficulty in providing a fast, coherent memory architecture, these systems usually rely on non-coherent, non-uniform memory architectures with private memories for each core. However, programming these systems poses significant challenges. The developer must extract large amounts of parallelism, while orchestrating communication among cores to optimize application performance. These issues become even more significant with irregular applications, which present data sets difficult to partition, unpredictable memory accesses, unbalanced control flow and fine grained communication. Hand-optimizing every single aspect is hard and time-consuming, and it often does not lead to the expectedmore » performance. There is a growing gap between such complex and highly-parallel architectures and the high level languages used to describe the specification, which were designed for simpler systems and do not consider these new issues. In this paper we introduce YAPPA (Yet Another Parallel Programming Approach), a compilation framework for the automatic parallelization of irregular applications on modern MPSoCs based on LLVM. We start by considering an efficient parallel programming approach for irregular applications on distributed memory systems. We then propose a set of transformations that can reduce the development and optimization effort. The results of our initial prototype confirm the correctness of the proposed approach.« less

Modeling and Implementation of HfO2-based Ferroelectric Tunnel Junctions

NASA Astrophysics Data System (ADS)

Pringle, Spencer Allen

HfO2-based ferroelectric tunnel junctions (FTJs) represent a unique opportunity as both a next-generation digital non-volatile memory and as synapse devices in braininspired logic systems, owing to their higher reliability compared to filamentary resistive random-access memory (ReRAM) and higher speed and lower power consumption compared to competing devices, including phase-change memory (PCM) and state-of-the-art FTJ. Ferroelectrics are often easier to deposit and have simpler material structure than films for magnetic tunnel junctions (MTJs). Ferroelectric HfO2 also enables complementary metal-oxide-semiconductor (CMOS) compatibility, since lead zirconate titanate (PZT) and BaTiO3-based FTJs often are not. No other groups have yet demonstrated a HfO2-based FTJ (to best of the author's knowledge) or applied it to a suitable system. For such devices to be useful, system designers require models based on both theoretical physical analysis and experimental results of fabricated devices in order to confidently design control systems. Both the CMOS circuitry and FTJs must then be designed in layout and fabricated on the same die. This work includes modeling of proposed device structures using a custom python script, which calculates theoretical potential barrier heights as a function of material properties and corresponding current densities (ranging from 8x103 to 3x10-2 A/cm 2 with RHRS/RLRS ranging from 5x105 to 6, depending on ferroelectric thickness). These equations were then combined with polynomial fits of experimental timing data and implemented in a Verilog-A behavioral analog model in Cadence Virtuoso. The author proposes tristate CMOS control systems, and circuits, for implementation of FTJ devices as digital memory and presents simulated performance. Finally, a process flow for fabrication of FTJ devices with CMOS is presented. This work has therefore enabled the fabrication of FTJ devices at RIT and the continued investigation of them as applied to any appropriate systems.

Real time imaging and infrared background scene analysis using the Naval Postgraduate School infrared search and target designation (NPS-IRSTD) system

NASA Astrophysics Data System (ADS)

Bernier, Jean D.

1991-09-01

The imaging in real time of infrared background scenes with the Naval Postgraduate School Infrared Search and Target Designation (NPS-IRSTD) System was achieved through extensive software developments in protected mode assembly language on an Intel 80386 33 MHz computer. The new software processes the 512 by 480 pixel images directly in the extended memory area of the computer where the DT-2861 frame grabber memory buffers are mapped. Direct interfacing, through a JDR-PR10 prototype card, between the frame grabber and the host computer AT bus enables each load of the frame grabber memory buffers to be effected under software control. The protected mode assembly language program can refresh the display of a six degree pseudo-color sector in the scanner rotation within the two second period of the scanner. A study of the imaging properties of the NPS-IRSTD is presented with preliminary work on image analysis and contrast enhancement of infrared background scenes.

PCI bus content-addressable-memory (CAM) implementation on FPGA for pattern recognition/image retrieval in a distributed environment

NASA Astrophysics Data System (ADS)

Megherbi, Dalila B.; Yan, Yin; Tanmay, Parikh; Khoury, Jed; Woods, C. L.

2004-11-01

Recently surveillance and Automatic Target Recognition (ATR) applications are increasing as the cost of computing power needed to process the massive amount of information continues to fall. This computing power has been made possible partly by the latest advances in FPGAs and SOPCs. In particular, to design and implement state-of-the-Art electro-optical imaging systems to provide advanced surveillance capabilities, there is a need to integrate several technologies (e.g. telescope, precise optics, cameras, image/compute vision algorithms, which can be geographically distributed or sharing distributed resources) into a programmable system and DSP systems. Additionally, pattern recognition techniques and fast information retrieval, are often important components of intelligent systems. The aim of this work is using embedded FPGA as a fast, configurable and synthesizable search engine in fast image pattern recognition/retrieval in a distributed hardware/software co-design environment. In particular, we propose and show a low cost Content Addressable Memory (CAM)-based distributed embedded FPGA hardware architecture solution with real time recognition capabilities and computing for pattern look-up, pattern recognition, and image retrieval. We show how the distributed CAM-based architecture offers a performance advantage of an order-of-magnitude over RAM-based architecture (Random Access Memory) search for implementing high speed pattern recognition for image retrieval. The methods of designing, implementing, and analyzing the proposed CAM based embedded architecture are described here. Other SOPC solutions/design issues are covered. Finally, experimental results, hardware verification, and performance evaluations using both the Xilinx Virtex-II and the Altera Apex20k are provided to show the potential and power of the proposed method for low cost reconfigurable fast image pattern recognition/retrieval at the hardware/software co-design level.

Super-Memorizers Are Not Super-Recognizers

PubMed Central

Ramon, Meike; Miellet, Sebastien; Dzieciol, Anna M.; Konrad, Boris Nikolai

2016-01-01

Humans have a natural expertise in recognizing faces. However, the nature of the interaction between this critical visual biological skill and memory is yet unclear. Here, we had the unique opportunity to test two individuals who have had exceptional success in the World Memory Championships, including several world records in face-name association memory. We designed a range of face processing tasks to determine whether superior/expert face memory skills are associated with distinctive perceptual strategies for processing faces. Superior memorizers excelled at tasks involving associative face-name learning. Nevertheless, they were as impaired as controls in tasks probing the efficiency of the face system: face inversion and the other-race effect. Super memorizers did not show increased hippocampal volumes, and exhibited optimal generic eye movement strategies when they performed complex multi-item face-name associations. Our data show that the visual computations of the face system are not malleable and are robust to acquired expertise involving extensive training of associative memory. PMID:27008627

Super-Memorizers Are Not Super-Recognizers.

PubMed

Ramon, Meike; Miellet, Sebastien; Dzieciol, Anna M; Konrad, Boris Nikolai; Dresler, Martin; Caldara, Roberto

2016-01-01

Humans have a natural expertise in recognizing faces. However, the nature of the interaction between this critical visual biological skill and memory is yet unclear. Here, we had the unique opportunity to test two individuals who have had exceptional success in the World Memory Championships, including several world records in face-name association memory. We designed a range of face processing tasks to determine whether superior/expert face memory skills are associated with distinctive perceptual strategies for processing faces. Superior memorizers excelled at tasks involving associative face-name learning. Nevertheless, they were as impaired as controls in tasks probing the efficiency of the face system: face inversion and the other-race effect. Super memorizers did not show increased hippocampal volumes, and exhibited optimal generic eye movement strategies when they performed complex multi-item face-name associations. Our data show that the visual computations of the face system are not malleable and are robust to acquired expertise involving extensive training of associative memory.

Design and application of shape memory actuators

NASA Astrophysics Data System (ADS)

Mertmann, M.; Vergani, G.

2008-05-01

The use of shape memory alloys in actuators allows the development of robust, simple and lightweight elements for application in a multitude of different industries. Over the years, the intermetallic compound Nickel-Titanium (NiTi or Nitinol) together with its ternary and quaternary derivates has gained general acceptance as a standard alloy. Even though as many as 99% of all shape memory actuator applications make use of Nitinol there are certain properties of this alloy system which require further research in order to find improvements and new markets: • Lack of higher transformation temperatures in the available alloys in order to open the field of automotive applications (Mf temperature > 80 °C) • Non-linearity in the electrical resistivity in order to improve the controllability of the actuator, • Wide hysteresis in the temperature-vs.-strain behaviour, which has a signi-ficant effect on both, the dynamics of the actuator and its controllability. Hence, there is a constant strive in the field towards an improvement of the related properties. However, these improvements are not always just alloy composition related. There is also a tremendous potential in the thermomechanical treatment of the material and in the design of the actuator. Significant improvement steps are already possible if the usage of the existent materials is optimized for the projected application and if the actuator system is designed in the most efficient way. This paper provides an overview about existent designs, applications and alloys for use in actuators, as well as examples of new shape memory actuator application with improved performance. It also gives an overview about general design rules and reflects about the strengths of the material and the related opportunities for its application.

Prototype Morphing Fan Nozzle Demonstrated

NASA Technical Reports Server (NTRS)

Lee, Ho-Jun; Song, Gang-Bing

2004-01-01

Ongoing research in NASA Glenn Research Center's Structural Mechanics and Dynamics Branch to develop smart materials technologies for aeropropulsion structural components has resulted in the design of the prototype morphing fan nozzle shown in the photograph. This prototype exploits the potential of smart materials to significantly improve the performance of existing aircraft engines by introducing new inherent capabilities for shape control, vibration damping, noise reduction, health monitoring, and flow manipulation. The novel design employs two different smart materials, a shape-memory alloy and magnetorheological fluids, to reduce the nozzle area by up to 30 percent. The prototype of the variable-area fan nozzle implements an overlapping spring leaf assembly to simplify the initial design and to provide ease of structural control. A single bundle of shape memory alloy wire actuators is used to reduce the nozzle geometry. The nozzle is subsequently held in the reduced-area configuration by using magnetorheological fluid brakes. This prototype uses the inherent advantages of shape memory alloys in providing large induced strains and of magnetorheological fluids in generating large resistive forces. In addition, the spring leaf design also functions as a return spring, once the magnetorheological fluid brakes are released, to help force the shape memory alloy wires to return to their original position. A computerized real-time control system uses the derivative-gain and proportional-gain algorithms to operate the system. This design represents a novel approach to the active control of high-bypass-ratio turbofan engines. Researchers have estimated that such engines will reduce thrust specific fuel consumption by 9 percent over that of fixed-geometry fan nozzles. This research was conducted under a cooperative agreement (NCC3-839) at the University of Akron.

Design of a memory-access controller with 3.71-times-enhanced energy efficiency for Internet-of-Things-oriented nonvolatile microcontroller unit

NASA Astrophysics Data System (ADS)

Natsui, Masanori; Hanyu, Takahiro

2018-04-01

In realizing a nonvolatile microcontroller unit (MCU) for sensor nodes in Internet-of-Things (IoT) applications, it is important to solve the data-transfer bottleneck between the central processing unit (CPU) and the nonvolatile memory constituting the MCU. As one circuit-oriented approach to solving this problem, we propose a memory access minimization technique for magnetoresistive-random-access-memory (MRAM)-embedded nonvolatile MCUs. In addition to multiplexing and prefetching of memory access, the proposed technique realizes efficient instruction fetch by eliminating redundant memory access while considering the code length of the instruction to be fetched and the transition of the memory address to be accessed. As a result, the performance of the MCU can be improved while relaxing the performance requirement for the embedded MRAM, and compact and low-power implementation can be performed as compared with the conventional cache-based one. Through the evaluation using a system consisting of a general purpose 32-bit CPU and embedded MRAM, it is demonstrated that the proposed technique increases the peak efficiency of the system up to 3.71 times, while a 2.29-fold area reduction is achieved compared with the cache-based one.

Comparison of two paradigms for distributed shared memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Levelt, W.G.; Kaashoek, M.F.; Bal, H.E.

1990-08-01

The paper compares two paradigms for Distributed Shared Memory on loosely coupled computing systems: the shared data-object model as used in Orca, a programming language specially designed for loosely coupled computing systems and the Shared Virtual Memory model. For both paradigms the authors have implemented two systems, one using only point-to-point messages, the other using broadcasting as well. They briefly describe these two paradigms and their implementations. Then they compare their performance on four applications: the traveling salesman problem, alpha-beta search, matrix multiplication and the all pairs shortest paths problem. The measurements show that both paradigms can be used efficientlymore » for programming large-grain parallel applications. Significant speedups were obtained on all applications. The unstructured Shared Virtual Memory paradigm achieves the best absolute performance, although this is largely due to the preliminary nature of the Orca compiler used. The structured shared data-object model achieves the highest speedups and is much easier to program and to debug.« less

FPGA Flash Memory High Speed Data Acquisition

NASA Technical Reports Server (NTRS)

Gonzalez, April

2013-01-01

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

A method to compute SEU fault probabilities in memory arrays with error correction

NASA Technical Reports Server (NTRS)

Gercek, Gokhan

1994-01-01

With the increasing packing densities in VLSI technology, Single Event Upsets (SEU) due to cosmic radiations are becoming more of a critical issue in the design of space avionics systems. In this paper, a method is introduced to compute the fault (mishap) probability for a computer memory of size M words. It is assumed that a Hamming code is used for each word to provide single error correction. It is also assumed that every time a memory location is read, single errors are corrected. Memory is read randomly whose distribution is assumed to be known. In such a scenario, a mishap is defined as two SEU's corrupting the same memory location prior to a read. The paper introduces a method to compute the overall mishap probability for the entire memory for a mission duration of T hours.

Robotic Vision, Tray-Picking System Design Using Multiple, Optical Matched Filters

NASA Astrophysics Data System (ADS)

Leib, Kenneth G.; Mendelsohn, Jay C.; Grieve, Philip G.

1986-10-01

The optical correlator is applied to a robotic vision, tray-picking problem. Complex matched filters (MFs) are designed to provide sufficient optical memory for accepting any orientation of the desired part, and a multiple holographic lens (MHL) is used to increase the memory for continuous coverage. It is shown that with appropriate thresholding a small part can be selected using optical matched filters. A number of criteria are presented for optimizing the vision system. Two of the part-filled trays that Mendelsohn used are considered in this paper which is the analog (optical) expansion of his paper. Our view in this paper is that of the optical correlator as a cueing device for subsequent, finer vision techniques.

A space release/deployment system actuated by shape memory wires

NASA Astrophysics Data System (ADS)

Fragnito, Marino; Vetrella and, Sergio

2002-11-01

In this paper, the design of an innovative hold down/release and deployment device actuated by shape memory wires, to be used for the first time for the S MA RT microsatellite solar wings is shown. The release and deployment mechanisms are actuated by a Shape Memory wire (Nitinol), which allows a complete symmetrical and synchronous release, in a very short time, of the four wings in pairs. The hold down kinematic mechanism is preloaded to avoid vibration nonlinearities and unwanted deployment at launch. The deployment mechanism is a simple pulley system. The stiffness of the deployed panel-hinge system needs to be dimensioned in order to meet the on-orbit requirement for attitude control. One-way roller clutches are used to keep the panel at the desired angle during the mission. An ad hoc software has been developed to simulate both the release and deployment operations, coupling the SMA wire behavior with the system mechanics.

A ferrofluid-based neural network: design of an analogue associative memory

NASA Astrophysics Data System (ADS)

Palm, R.; Korenivski, V.

2009-02-01

We analyse an associative memory based on a ferrofluid, consisting of a system of magnetic nano-particles suspended in a carrier fluid of variable viscosity subject to patterns of magnetic fields from an array of input and output magnetic pads. The association relies on forming patterns in the ferrofluid during a training phase, in which the magnetic dipoles are free to move and rotate to minimize the total energy of the system. Once equilibrated in energy for a given input-output magnetic field pattern pair, the particles are fully or partially immobilized by cooling the carrier liquid. Thus produced particle distributions control the memory states, which are read out magnetically using spin-valve sensors incorporated into the output pads. The actual memory consists of spin distributions that are dynamic in nature, realized only in response to the input patterns that the system has been trained for. Two training algorithms for storing multiple patterns are investigated. Using Monte Carlo simulations of the physical system, we demonstrate that the device is capable of storing and recalling two sets of images, each with an accuracy approaching 100%.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Seyong; Vetter, Jeffrey S

Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation in mind, we present NVL-C: a novel programming system that facilitates the efficient and correct programming of NVM main memory systems. The NVL-C programming abstraction extends C with a small set of intuitive language features that target NVM main memory, and can be combined directly with traditional C memory model features for DRAM. We have designed these new features to enable compiler analyses and run-time checks that can improve performance and guard againstmore » a number of subtle programming errors, which, when left uncorrected, can corrupt NVM-stored data. Moreover, to enable recovery of data across application or system failures, these NVL-C features include a flexible directive for specifying NVM transactions. So that our implementation might be extended to other compiler front ends and languages, the majority of our compiler analyses are implemented in an extended version of LLVM's intermediate representation (LLVM IR). We evaluate NVL-C on a number of applications to show its flexibility, performance, and correctness.« less

3-DIMENSIONAL Optoelectronic

NASA Astrophysics Data System (ADS)

Krishnamoorthy, Ashok Venketaraman

This thesis covers the design, analysis, optimization, and implementation of optoelectronic (N,M,F) networks. (N,M,F) networks are generic space-division networks that are well suited to implementation using optoelectronic integrated circuits and free-space optical interconnects. An (N,M,F) networks consists of N input channels each having a fanout F_{rm o}, M output channels each having a fanin F_{rm i}, and Log_{rm K}(N/F) stages of K x K switches. The functionality of the fanout, switching, and fanin stages depends on the specific application. Three applications of optoelectronic (N,M,F) networks are considered. The first is an optoelectronic (N,1,1) content -addressable memory system that achieves associative recall on two-dimensional images retrieved from a parallel-access optical memory. The design and simulation of the associative memory are discussed, and an experimental emulation of a prototype system using images from a parallel-readout optical disk is presented. The system design provides superior performance to existing electronic content-addressable memory chips in terms of capacity and search rate, and uses readily available optical disk and VLSI technologies. Next, a scalable optoelectronic (N,M,F) neural network that uses free-space holographic optical interconnects is presented. The neural architecture minimizes the number of optical transmitters needed, and provides accurate electronic fanin with low signal skew, and dendritic-type fan-in processing capability in a compact layout. Optimal data-encoding methods and circuit techniques are discussed. The implementation of an prototype optoelectronic neural system, and its application to a simple recognition task is demonstrated. Finally, the design, analysis, and optimization of a (N,N,F) self-routing, packet-switched multistage interconnection network is described. The network is suitable for parallel computing and broadband switching applications. The tradeoff between optical and electronic interconnects is examined quantitatively by varying the electronic switch size K. The performance of the (N,N,F) network versus the fanning parameter F, is also analyzed. It is shown that the optoelectronic (N,N,F) networks provide a range of performance-cost alternatives, and offer superior performance-per-cost to fully electronic switching networks and to previous networks designs.

Interfacing a high performance disk array file server to a Gigabit LAN

NASA Technical Reports Server (NTRS)

Seshan, Srinivasan; Katz, Randy H.

1993-01-01

Our previous prototype, RAID-1, identified several bottlenecks in typical file server architectures. The most important bottleneck was the lack of a high-bandwidth path between disk, memory, and the network. Workstation servers, such as the Sun-4/280, have very slow access to peripherals on busses far from the CPU. For the RAID-2 system, we addressed this problem by designing a crossbar interconnect, Xbus board, that provides a 40MB/s path between disk, memory, and the network interfaces. However, this interconnect does not provide the system CPU with low latency access to control the various interfaces. To provide a high data rate to clients on the network, we were forced to carefully and efficiently design the network software. A block diagram of the system hardware architecture is given. In the following subsections, we describe pieces of the RAID-2 file server hardware that had a significant impact on the design of the network interface.

DESTINY

DOE Office of Scientific and Technical Information (OSTI.GOV)

2015-03-10

DESTINY is a comprehensive tool for modeling 3D and 2D cache designs using SRAM,embedded DRAM (eDRAM), spin transfer torque RAM (STT-RAM), resistive RAM (ReRAM), and phase change RAM (PCN). In its purpose, it is similar to CACTI, CACTI-3DD or NVSim. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g. latency, area or energy-delay product) for agiven memory technology, choosing the suitable memory technology or fabrication method (i.e. 2D v/s 3D) for a given optimization target, etc. DESTINY has been validated against several cache prototypes. DESTINY is expected to boost studies ofmore » next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers.« less

Priming Effects Associated with the Hierarchical Levels of Classification Systems

ERIC Educational Resources Information Center

Loehrlein, Aaron J.

2012-01-01

The act of categorization produces conceptual representations in memory while knowledge organization (KO) systems provide conceptual representations that are used in information storage and retrieval systems. Previous research has explored how KO systems can be designed to resemble the user's internal conceptual structures. However, the more…

Programs for Testing Processor-in-Memory Computing Systems

NASA Technical Reports Server (NTRS)

Katz, Daniel S.

2006-01-01

The Multithreaded Microbenchmarks for Processor-In-Memory (PIM) Compilers, Simulators, and Hardware are computer programs arranged in a series for use in testing the performances of PIM computing systems, including compilers, simulators, and hardware. The programs at the beginning of the series test basic functionality; the programs at subsequent positions in the series test increasingly complex functionality. The programs are intended to be used while designing a PIM system, and can be used to verify that compilers, simulators, and hardware work correctly. The programs can also be used to enable designers of these system components to examine tradeoffs in implementation. Finally, these programs can be run on non-PIM hardware (either single-threaded or multithreaded) using the POSIX pthreads standard to verify that the benchmarks themselves operate correctly. [POSIX (Portable Operating System Interface for UNIX) is a set of standards that define how programs and operating systems interact with each other. pthreads is a library of pre-emptive thread routines that comply with one of the POSIX standards.

Application of neural networks to group technology

NASA Astrophysics Data System (ADS)

Caudell, Thomas P.; Smith, Scott D. G.; Johnson, G. C.; Wunsch, Donald C., II

1991-08-01

Adaptive resonance theory (ART) neural networks are being developed for application to the industrial engineering problem of group technology--the reuse of engineering designs. Two- and three-dimensional representations of engineering designs are input to ART-1 neural networks to produce groups or families of similar parts. These representations, in their basic form, amount to bit maps of the part, and can become very large when the part is represented in high resolution. This paper describes an enhancement to an algorithmic form of ART-1 that allows it to operate directly on compressed input representations and to generate compressed memory templates. The performance of this compressed algorithm is compared to that of the regular algorithm on real engineering designs and a significant savings in memory storage as well as a speed up in execution is observed. In additions, a `neural database'' system under development is described. This system demonstrates the feasibility of training an ART-1 network to first cluster designs into families, and then to recall the family when presented a similar design. This application is of large practical value to industry, making it possible to avoid duplication of design efforts.

Acute stress impairs recall after interference in older people, but not in young people.

PubMed

Hidalgo, Vanesa; Almela, Mercedes; Villada, Carolina; Salvador, Alicia

2014-03-01

Stress has been associated with negative changes observed during the aging process. However, very little research has been carried out on the role of age in acute stress effects on memory. We aimed to explore the role of age and sex in the relationship between hypothalamus-pituitary-adrenal axis (HPA-axis) and sympathetic nervous system (SNS) reactivity to psychosocial stress and short-term declarative memory performance. To do so, sixty-seven participants divided into two age groups (each group with a similar number of men and women) were exposed to the Trier Social Stress Test (TSST) and a control condition in a crossover design. Memory performance was assessed by the Rey Auditory Verbal Learning Test (RAVLT). As expected, worse memory performance was associated with age; but more interestingly, the stressor impaired recall after interference only in the older group. In addition, this effect was negatively correlated with the alpha-amylase over cortisol ratio, which has recently been suggested as a good marker of stress system dysregulation. However, we failed to find sex differences in memory performance. These results show that age moderates stress-induced effects on declarative memory, and they point out the importance of studying both of the physiological systems involved in the stress response together. Copyright © 2014 Elsevier Inc. All rights reserved.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to nanocrystal charge has a strong effect on the memory characteristics. Also, the programming operation of the memory cell has been investigated. The tunneling rate from quantum well channel to quantum dot (nanocrystal) gate is calculated. The calculations include various memory parameters, wavefunctions, and energies of quantum well channel and quantum dot gate. The use of floating gate nanocrystal memory as a transistor with a programmable threshold voltage has been demonstrated. The incorporation of FG-NCFETs to design programmable integrated circuit building blocks has been discussed. This includes the design of programmable current and voltage reference circuits. Finally, we demonstrated the design of tunable gain op-amp incorporating FG-NCFETs. Programmable integrated circuit building blocks can be used in intelligent analog and digital systems.

Effects of Δ9-tetrahydrocannabinol administration on human encoding and recall memory function: a pharmacological FMRI study.

PubMed

Bossong, Matthijs G; Jager, Gerry; van Hell, Hendrika H; Zuurman, Lineke; Jansma, J Martijn; Mehta, Mitul A; van Gerven, Joop M A; Kahn, René S; Ramsey, Nick F

2012-03-01

Deficits in memory function are an incapacitating aspect of various psychiatric and neurological disorders. Animal studies have recently provided strong evidence for involvement of the endocannabinoid (eCB) system in memory function. Neuropsychological studies in humans have shown less convincing evidence but suggest that administration of cannabinoid substances affects encoding rather than recall of information. In this study, we examined the effects of perturbation of the eCB system on memory function during both encoding and recall. We performed a pharmacological MRI study with a placebo-controlled, crossover design, investigating the effects of Δ9-tetrahydrocannabinol (THC) inhalation on associative memory-related brain function in 13 healthy volunteers. Performance and brain activation during associative memory were assessed using a pictorial memory task, consisting of separate encoding and recall conditions. Administration of THC caused reductions in activity during encoding in the right insula, the right inferior frontal gyrus, and the left middle occipital gyrus and a network-wide increase in activity during recall, which was most prominent in bilateral cuneus and precuneus. THC administration did not affect task performance, but while during placebo recall activity significantly explained variance in performance, this effect disappeared after THC. These findings suggest eCB involvement in encoding of pictorial information. Increased precuneus activity could reflect impaired recall function, but the absence of THC effects on task performance suggests a compensatory mechanism. These results further emphasize the eCB system as a potential novel target for treatment of memory disorders and a promising target for development of new therapies to reduce memory deficits in humans.

Memory and Energy Optimization Strategies for Multithreaded Operating System on the Resource-Constrained Wireless Sensor Node

PubMed Central

Liu, Xing; Hou, Kun Mean; de Vaulx, Christophe; Xu, Jun; Yang, Jianfeng; Zhou, Haiying; Shi, Hongling; Zhou, Peng

2015-01-01

Memory and energy optimization strategies are essential for the resource-constrained wireless sensor network (WSN) nodes. In this article, a new memory-optimized and energy-optimized multithreaded WSN operating system (OS) LiveOS is designed and implemented. Memory cost of LiveOS is optimized by using the stack-shifting hybrid scheduling approach. Different from the traditional multithreaded OS in which thread stacks are allocated statically by the pre-reservation, thread stacks in LiveOS are allocated dynamically by using the stack-shifting technique. As a result, memory waste problems caused by the static pre-reservation can be avoided. In addition to the stack-shifting dynamic allocation approach, the hybrid scheduling mechanism which can decrease both the thread scheduling overhead and the thread stack number is also implemented in LiveOS. With these mechanisms, the stack memory cost of LiveOS can be reduced more than 50% if compared to that of a traditional multithreaded OS. Not is memory cost optimized, but also the energy cost is optimized in LiveOS, and this is achieved by using the multi-core “context aware” and multi-core “power-off/wakeup” energy conservation approaches. By using these approaches, energy cost of LiveOS can be reduced more than 30% when compared to the single-core WSN system. Memory and energy optimization strategies in LiveOS not only prolong the lifetime of WSN nodes, but also make the multithreaded OS feasible to run on the memory-constrained WSN nodes. PMID:25545264

Thermosetting epoxy resin/thermoplastic system with combined shape memory and self-healing properties

NASA Astrophysics Data System (ADS)

Yao, Yongtao; Wang, Jingjie; Lu, Haibao; Xu, Ben; Fu, Yongqing; Liu, Yanju; Leng, Jinsong

2016-01-01

A novel and facile strategy was proposed to construct a thermosetting/thermoplastic system with both shape memory and self-healing properties based on commercial epoxy resin and poly(ɛ-caprolactone)-PCL. Thermoplastic material is capable of re-structuring and changing the stiffness/modulus when the temperature is above melting temperature. PCL microfiber was used as a plasticizer in epoxy resin-based blends, and served as a ‘hard segment’ to fix a temporary shape of the composites during shape memory cycles. In this study, the electrospun PCL membrane with a porous network structure enabled a homogenous PCL fibrous distribution and optimized interaction between fiber and epoxy resin. The self-healing capability is achieved by phase transition during curing of the composites. The mechanism of the shape memory effect of the thermosetting (rubber)/thermoplastic composite is attributed to the structural design of the thermoplastic network inside the thermosetting resin/rubber matrix.

The single event upset environment for avionics at high latitude

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sims, A.J.; Dyer, C.S.; Peerless, C.L.

1994-12-01

Modern avionic systems for civil and military applications are becoming increasingly reliant upon embedded microprocessors and associated memory devices. The phenomenon of single event upset (SEU) is well known in space systems and designers have generally been careful to use SEU tolerant devices or to implement error detection and correction (EDAC) techniques where appropriate. In the past, avionics designers have had no reason to consider SEU effects but is clear that the more prevalent use of memory devices combined with increasing levels of IC integration will make SEU mitigation an important design consideration for future avionic systems. To this end,more » it is necessary to work towards producing models of the avionics SEU environment which will permit system designers to choose components and EDAC techniques which are based on predictions of SEU rates correct to much better than an order of magnitude. Measurements of the high latitude SEU environment at avionics altitude have been made on board a commercial airliner. Results are compared with models of primary and secondary cosmic rays and atmospheric neutrons. Ground based SEU tests of static RAMs are used to predict rates in flight.« less

Multiple memory systems as substrates for multiple decision systems

PubMed Central

Doll, Bradley B.; Shohamy, Daphna; Daw, Nathaniel D.

2014-01-01

It has recently become widely appreciated that value-based decision making is supported by multiple computational strategies. In particular, animal and human behavior in learning tasks appears to include habitual responses described by prominent model-free reinforcement learning (RL) theories, but also more deliberative or goal-directed actions that can be characterized by a different class of theories, model-based RL. The latter theories evaluate actions by using a representation of the contingencies of the task (as with a learned map of a spatial maze), called an “internal model.” Given the evidence of behavioral and neural dissociations between these approaches, they are often characterized as dissociable learning systems, though they likely interact and share common mechanisms. In many respects, this division parallels a longstanding dissociation in cognitive neuroscience between multiple memory systems, describing, at the broadest level, separate systems for declarative and procedural learning. Procedural learning has notable parallels with model-free RL: both involve learning of habits and both are known to depend on parts of the striatum. Declarative memory, by contrast, supports memory for single events or episodes and depends on the hippocampus. The hippocampus is thought to support declarative memory by encoding temporal and spatial relations among stimuli and thus is often referred to as a relational memory system. Such relational encoding is likely to play an important role in learning an internal model, the representation that is central to model-based RL. Thus, insofar as the memory systems represent more general-purpose cognitive mechanisms that might subserve performance on many sorts of tasks including decision making, these parallels raise the question whether the multiple decision systems are served by multiple memory systems, such that one dissociation is grounded in the other. Here we investigated the relationship between model-based RL and relational memory by comparing individual differences across behavioral tasks designed to measure either capacity. Human subjects performed two tasks, a learning and generalization task (acquired equivalence) which involves relational encoding and depends on the hippocampus; and a sequential RL task that could be solved by either a model-based or model-free strategy. We assessed the correlation between subjects’ use of flexible, relational memory, as measured by generalization in the acquired equivalence task, and their differential reliance on either RL strategy in the decision task. We observed a significant positive relationship between generalization and model-based, but not model-free, choice strategies. These results are consistent with the hypothesis that model-based RL, like acquired equivalence, relies on a more general-purpose relational memory system. PMID:24846190

Design of the Wind Tunnel Model Communication Controller Board. Degree awarded by Christopher Newport Univ. on Dec. 1998

NASA Technical Reports Server (NTRS)

Wilson, William C.

1999-01-01

The NASA Langley Research Center's Wind Tunnel Reinvestment project plans to shrink the existing data acquisition electronics to fit inside a wind tunnel model. Space limitations within a model necessitate a distributed system of Application Specific Integrated Circuits (ASICs) rather than a centralized system based on PC boards. This thesis will focus on the design of the prototype of the communication Controller board. A portion of the communication Controller board is to be used as the basis of an ASIC design. The communication Controller board will communicate between the internal model modules and the external data acquisition computer. This board is based around an Field Programmable Gate Array (FPGA), to allow for reconfigurability. In addition to the FPGA, this board contains buffer Random Access Memory (RAM), configuration memory (EEPROM), drivers for the communications ports, and passive components.

Eternal Sunshine of the Spotless Machine: Protecting Privacy with Ephemeral Channels

PubMed Central

Dunn, Alan M.; Lee, Michael Z.; Jana, Suman; Kim, Sangman; Silberstein, Mark; Xu, Yuanzhong; Shmatikov, Vitaly; Witchel, Emmett

2014-01-01

Modern systems keep long memories. As we show in this paper, an adversary who gains access to a Linux system, even one that implements secure deallocation, can recover the contents of applications’ windows, audio buffers, and data remaining in device drivers—long after the applications have terminated. We design and implement Lacuna, a system that allows users to run programs in “private sessions.” After the session is over, all memories of its execution are erased. The key abstraction in Lacuna is an ephemeral channel, which allows the protected program to talk to peripheral devices while making it possible to delete the memories of this communication from the host. Lacuna can run unmodified applications that use graphics, sound, USB input devices, and the network, with only 20 percentage points of additional CPU utilization. PMID:24755709

Analysis and Synthesis of Memory-Based Fuzzy Sliding Mode Controllers.

PubMed

Zhang, Jinhui; Lin, Yujuan; Feng, Gang

2015-12-01

This paper addresses the sliding mode control problem for a class of Takagi-Sugeno fuzzy systems with matched uncertainties. Different from the conventional memoryless sliding surface, a memory-based sliding surface is proposed which consists of not only the current state but also the delayed state. Both robust and adaptive fuzzy sliding mode controllers are designed based on the proposed memory-based sliding surface. It is shown that the sliding surface can be reached and the closed-loop control system is asymptotically stable. Furthermore, to reduce the chattering, some continuous sliding mode controllers are also presented. Finally, the ball and beam system is used to illustrate the advantages and effectiveness of the proposed approaches. It can be seen that, with the proposed control approaches, not only can the stability be guaranteed, but also its transient performance can be improved significantly.

Synthetic analog and digital circuits for cellular computation and memory.

PubMed

Purcell, Oliver; Lu, Timothy K

2014-10-01

Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss recent progress in designing gene networks that exhibit memory, and how memory and computation have been integrated to yield more complex systems that can both process and record information. Finally, we suggest new directions for engineering biological circuits capable of computation. Copyright © 2014 The Authors. Published by Elsevier Ltd.. All rights reserved.

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

DOE PAGES

Bender, Michael A.; Berry, Jonathan W.; Hammond, Simon D.; ...

2017-01-03

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” andmore » if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.« less

A test of the reward-contrast hypothesis.

PubMed

Dalecki, Stefan J; Panoz-Brown, Danielle E; Crystal, Jonathon D

2017-12-01

Source memory, a facet of episodic memory, is the memory of the origin of information. Whereas source memory in rats is sustained for at least a week, spatial memory degraded after approximately a day. Different forgetting functions may suggest that two memory systems (source memory and spatial memory) are dissociated. However, in previous work, the two tasks used baiting conditions consisting of chocolate and chow flavors; notably, the source memory task used the relatively better flavor. Thus, according to the reward-contrast hypothesis, when chocolate and chow were presented within the same context (i.e., within a single radial maze trial), the chocolate location was more memorable than the chow location because of contrast. We tested the reward-contrast hypothesis using baiting configurations designed to produce reward-contrast. The reward-contrast hypothesis predicts that under these conditions, spatial memory will survive a 24-h retention interval. We documented elimination of spatial memory performance after a 24-h retention interval using a reward-contrast baiting pattern. These data suggest that reward contrast does not explain our earlier findings that source memory survives unusually long retention intervals. Copyright © 2017 Elsevier B.V. All rights reserved.

Exascale Hardware Architectures Working Group

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hemmert, S; Ang, J; Chiang, P

2011-03-15

The ASC Exascale Hardware Architecture working group is challenged to provide input on the following areas impacting the future use and usability of potential exascale computer systems: processor, memory, and interconnect architectures, as well as the power and resilience of these systems. Going forward, there are many challenging issues that will need to be addressed. First, power constraints in processor technologies will lead to steady increases in parallelism within a socket. Additionally, all cores may not be fully independent nor fully general purpose. Second, there is a clear trend toward less balanced machines, in terms of compute capability compared tomore » memory and interconnect performance. In order to mitigate the memory issues, memory technologies will introduce 3D stacking, eventually moving on-socket and likely on-die, providing greatly increased bandwidth but unfortunately also likely providing smaller memory capacity per core. Off-socket memory, possibly in the form of non-volatile memory, will create a complex memory hierarchy. Third, communication energy will dominate the energy required to compute, such that interconnect power and bandwidth will have a significant impact. All of the above changes are driven by the need for greatly increased energy efficiency, as current technology will prove unsuitable for exascale, due to unsustainable power requirements of such a system. These changes will have the most significant impact on programming models and algorithms, but they will be felt across all layers of the machine. There is clear need to engage all ASC working groups in planning for how to deal with technological changes of this magnitude. The primary function of the Hardware Architecture Working Group is to facilitate codesign with hardware vendors to ensure future exascale platforms are capable of efficiently supporting the ASC applications, which in turn need to meet the mission needs of the NNSA Stockpile Stewardship Program. This issue is relatively immediate, as there is only a small window of opportunity to influence hardware design for 2018 machines. Given the short timeline a firm co-design methodology with vendors is of prime importance.« less

Development of a high capacity bubble domain memory element and related epitaxial garnet materials for application in spacecraft data recorders. Item 2: The optimization of material-device parameters for application in bubble domain memory elements for spacecraft data recorders

NASA Technical Reports Server (NTRS)

Besser, P. J.

1976-01-01

Bubble domain materials and devices are discussed. One of the materials development goals was a materials system suitable for operation of 16 micrometer period bubble domain devices at 150 kHz over the temperature range -10 C to +60 C. Several material compositions and hard bubble suppression techniques were characterized and the most promising candidates were evaluated in device structures. The technique of pulsed laser stroboscopic microscopy was used to characterize bubble dynamic properties and device performance at 150 kHz. Techniques for large area LPE film growth were developed as a separate task. Device studies included detector optimization, passive replicator design and test and on-chip bridge evaluation. As a technology demonstration an 8 chip memory cell was designed, tested and delivered. The memory elements used in the cell were 10 kilobit serial registers.

Optical mass memory system (AMM-13). AMM-13 system segment specification

NASA Technical Reports Server (NTRS)

Bailey, G. A.

1980-01-01

The performance, design, development, and test requirements for an optical mass data storage and retrieval system prototype (AMM-13) are established. This system interfaces to other system segments of the NASA End-to-End Data System via the Data Base Management System segment and is designed to have a storage capacity of 10 to the 13th power bits (10 to the 12th power bits on line). The major functions of the system include control, input and output, recording of ingested data, fiche processing/replication and storage and retrieval.

A /31,15/ Reed-Solomon Code for large memory systems

NASA Technical Reports Server (NTRS)

Lim, R. S.

1979-01-01

This paper describes the encoding and the decoding of a (31,15) Reed-Solomon Code for multiple-burst error correction for large memory systems. The decoding procedure consists of four steps: (1) syndrome calculation, (2) error-location polynomial calculation, (3) error-location numbers calculation, and (4) error values calculation. The principal features of the design are the use of a hardware shift register for both high-speed encoding and syndrome calculation, and the use of a commercially available (31,15) decoder for decoding Steps 2, 3 and 4.

Holographic optical elements: Fabrication and testing

NASA Technical Reports Server (NTRS)

Zech, R. G.; Shareck, M.; Ralston, L. M.

1974-01-01

The basic properties and use of holographic optical elements were investigated to design and construct wide-angle, Fourier-transform holographic optical systems for use in a Bragg-effect optical memory. The performance characteristics are described along with the construction of the holographic system.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

Optical interconnection network for parallel access to multi-rank memory in future computing systems.

PubMed

Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

2015-08-10

With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

Radiation Tolerant Intelligent Memory Stack (RTIMS)

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong; Herath, Jeffrey A.

2006-01-01

The Radiation Tolerant Intelligent Memory Stack (RTIMS), suitable for both geostationary and low earth orbit missions, has been developed. The memory module is fully functional and undergoing environmental and radiation characterization. A self-contained flight-like module is expected to be completed in 2006. RTIMS provides reconfigurable circuitry and 2 gigabits of error corrected or 1 gigabit of triple redundant digital memory in a small package. RTIMS utilizes circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuitries are stacked into a module of 42.7mm x 42.7mm x 13.00mm. Triple module redundancy, current limiting, configuration scrubbing, and single event function interrupt detection are employed to mitigate radiation effects. The mitigation techniques significantly simplify system design. RTIMS is well suited for deployment in real-time data processing, reconfigurable computing, and memory intensive applications.

Influence of transactive memory on perceived performance, job satisfaction and identification in anaesthesia teams.

PubMed

Michinov, E; Olivier-Chiron, E; Rusch, E; Chiron, B

2008-03-01

There is an increasing awareness in the medical community that human factors are involved in effectiveness of anaesthesia teams. Communication and coordination between physicians and nurses seems to play a crucial role in maintaining a good level of performance under time pressure, particularly for anaesthesia teams, who are confronted with uncertainty, rapid changes in the environment, and multi-tasking. The aim of this study was to examine the relationship between a specific form of implicit coordination--the transactive memory system--and perceptions of team effectiveness and work attitudes such as job satisfaction and team identification. A cross-sectional study was conducted among 193 nurse and physician anaesthetists from eight French public hospitals. The questionnaire included some measures of transactive memory system (coordination, specialization, and credibility components), perception of team effectiveness, and work attitudes (Minnesota Job Satisfaction Questionnaire, team identification scale). The questionnaire was designed to be filled anonymously, asking only biographical data relating to sex, age, status, and tenure. Hierarchical multiple regression analyses revealed as predicted that transactive memory system predicted members' perceptions of team effectiveness, and also affective outcomes such as job satisfaction and team identification. Moreover, the results demonstrated that transactive memory processes, and especially the coordination component, were a better predictor of teamwork perceptions than socio-demographic (i.e. gender or status) or contextual variables (i.e. tenure and size of team). These findings provided empirical evidence of the existence of a transactive memory system among real anaesthesia teams, and highlight the need to investigate whether transactive memory is actually linked with objective measures of performance.

Optimal Design for Hetero-Associative Memory: Hippocampal CA1 Phase Response Curve and Spike-Timing-Dependent Plasticity

PubMed Central

Miyata, Ryota; Ota, Keisuke; Aonishi, Toru

2013-01-01

Recently reported experimental findings suggest that the hippocampal CA1 network stores spatio-temporal spike patterns and retrieves temporally reversed and spread-out patterns. In this paper, we explore the idea that the properties of the neural interactions and the synaptic plasticity rule in the CA1 network enable it to function as a hetero-associative memory recalling such reversed and spread-out spike patterns. In line with Lengyel’s speculation (Lengyel et al., 2005), we firstly derive optimally designed spike-timing-dependent plasticity (STDP) rules that are matched to neural interactions formalized in terms of phase response curves (PRCs) for performing the hetero-associative memory function. By maximizing object functions formulated in terms of mutual information for evaluating memory retrieval performance, we search for STDP window functions that are optimal for retrieval of normal and doubly spread-out patterns under the constraint that the PRCs are those of CA1 pyramidal neurons. The system, which can retrieve normal and doubly spread-out patterns, can also retrieve reversed patterns with the same quality. Finally, we demonstrate that purposely designed STDP window functions qualitatively conform to typical ones found in CA1 pyramidal neurons. PMID:24204822

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gebis, Joseph; Oliker, Leonid; Shalf, John

The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changesmore » to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x-13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.« less

Design of a Multi-Level/Analog Ferroelectric Memory Device

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2006-01-01

Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

ART/Ada design project, phase 1: Project plan

NASA Technical Reports Server (NTRS)

Allen, Bradley P.

1988-01-01

The plan and schedule for Phase 1 of the Ada based ESBT Design Research Project is described. The main platform for the project is a DEC Ada compiler on VAX mini-computers and VAXstations running the Virtual Memory System (VMS) operating system. The Ada effort and lines of code are given in tabular form. A chart is given of the entire project life cycle.

Does Growth in the Executive System of Working Memory Underlie Growth in Literacy for Bilingual Children with and without Reading Disabilities?

ERIC Educational Resources Information Center

Swanson, H. Lee; Orosco, Michael J.; Kudo, Milagros

2017-01-01

This cohort-sequential study explored the components of working memory (WM) that underlie second language (L2) reading growth in 450 children at risk and not at risk for reading disabilities (RD) whose first language is Spanish. English language learners designated as balanced and nonbalanced bilinguals with and without risk for RD in Grades 1, 2,…

Improved Writing-Conductor Designs For Magnetic Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1994-01-01

Writing currents reduced to practical levels. Improved conceptual designs for writing conductors in micromagnet/Hall-effect random-access integrated-circuit memory reduces electrical current needed to magnetize micromagnet in each memory cell. Basic concept of micromagnet/Hall-effect random-access memory presented in "Magnetic Analog Random-Access Memory" (NPO-17999).

Intelligent holographic databases

NASA Astrophysics Data System (ADS)

Barbastathis, George

Memory is a key component of intelligence. In the human brain, physical structure and functionality jointly provide diverse memory modalities at multiple time scales. How could we engineer artificial memories with similar faculties? In this thesis, we attack both hardware and algorithmic aspects of this problem. A good part is devoted to holographic memory architectures, because they meet high capacity and parallelism requirements. We develop and fully characterize shift multiplexing, a novel storage method that simplifies disk head design for holographic disks. We develop and optimize the design of compact refreshable holographic random access memories, showing several ways that 1 Tbit can be stored holographically in volume less than 1 m3, with surface density more than 20 times higher than conventional silicon DRAM integrated circuits. To address the issue of photorefractive volatility, we further develop the two-lambda (dual wavelength) method for shift multiplexing, and combine electrical fixing with angle multiplexing to demonstrate 1,000 multiplexed fixed holograms. Finally, we propose a noise model and an information theoretic metric to optimize the imaging system of a holographic memory, in terms of storage density and error rate. Motivated by the problem of interfacing sensors and memories to a complex system with limited computational resources, we construct a computer game of Desert Survival, built as a high-dimensional non-stationary virtual environment in a competitive setting. The efficacy of episodic learning, implemented as a reinforced Nearest Neighbor scheme, and the probability of winning against a control opponent improve significantly by concentrating the algorithmic effort to the virtual desert neighborhood that emerges as most significant at any time. The generalized computational model combines the autonomous neural network and von Neumann paradigms through a compact, dynamic central representation, which contains the most salient features of the sensory inputs, fused with relevant recollections, reminiscent of the hypothesized cognitive function of awareness. The Declarative Memory is searched both by content and address, suggesting a holographic implementation. The proposed computer architecture may lead to a novel paradigm that solves 'hard' cognitive problems at low cost.

Toward Millions of File System IOPS on Low-Cost, Commodity Hardware

PubMed Central

Zheng, Da; Burns, Randal; Szalay, Alexander S.

2013-01-01

We describe a storage system that removes I/O bottlenecks to achieve more than one million IOPS based on a user-space file abstraction for arrays of commodity SSDs. The file abstraction refactors I/O scheduling and placement for extreme parallelism and non-uniform memory and I/O. The system includes a set-associative, parallel page cache in the user space. We redesign page caching to eliminate CPU overhead and lock-contention in non-uniform memory architecture machines. We evaluate our design on a 32 core NUMA machine with four, eight-core processors. Experiments show that our design delivers 1.23 million 512-byte read IOPS. The page cache realizes the scalable IOPS of Linux asynchronous I/O (AIO) and increases user-perceived I/O performance linearly with cache hit rates. The parallel, set-associative cache matches the cache hit rates of the global Linux page cache under real workloads. PMID:24402052

Toward Millions of File System IOPS on Low-Cost, Commodity Hardware.

PubMed

Zheng, Da; Burns, Randal; Szalay, Alexander S

2013-01-01

We describe a storage system that removes I/O bottlenecks to achieve more than one million IOPS based on a user-space file abstraction for arrays of commodity SSDs. The file abstraction refactors I/O scheduling and placement for extreme parallelism and non-uniform memory and I/O. The system includes a set-associative, parallel page cache in the user space. We redesign page caching to eliminate CPU overhead and lock-contention in non-uniform memory architecture machines. We evaluate our design on a 32 core NUMA machine with four, eight-core processors. Experiments show that our design delivers 1.23 million 512-byte read IOPS. The page cache realizes the scalable IOPS of Linux asynchronous I/O (AIO) and increases user-perceived I/O performance linearly with cache hit rates. The parallel, set-associative cache matches the cache hit rates of the global Linux page cache under real workloads.

Shape memory alloy TiNi actuators for twist control of smart wing designs

NASA Astrophysics Data System (ADS)

Jardine, A. Peter; Kudva, Jayanth N.; Martin, Christopher A.; Appa, Kari

1996-05-01

On high performance military aircraft, small changes in both wing twist and wing camber have the potential to provide substantial payoffs in terms of additional lift and enhanced maneuverability. To achieve the required wing shape, actuators made of smart materials are currently being studied under an ARPA/WL contract for a subscale model of a fighter aircraft. The use of the shape memory alloy TiNi for wing twist actuation was investigated using shape memory effect (SME) torque tube actuator configurations. The actuator configurations were sized to fit inside a 16% scale model of an aircraft wing and the torque's supplied to the wing were similarly calculated from full-scale requirements. The actuator systems were tested in a conventional laboratory setting. Design and calibration of the actuators for wing twist are discussed.

Logic design and implementation of FPGA for a high frame rate ultrasound imaging system

NASA Astrophysics Data System (ADS)

Liu, Anjun; Wang, Jing; Lu, Jian-Yu

2002-05-01

Recently, a method has been developed for high frame rate medical imaging [Jian-yu Lu, ``2D and 3D high frame rate imaging with limited diffraction beams,'' IEEE Trans. Ultrason. Ferroelectr. Freq. Control 44(4), 839-856 (1997)]. To realize this method, a complicated system [multiple-channel simultaneous data acquisition, large memory in each channel for storing up to 16 seconds of data at 40 MHz and 12-bit resolution, time-variable-gain (TGC) control, Doppler imaging, harmonic imaging, as well as coded transmissions] is designed. Due to the complexity of the system, field programmable gate array (FPGA) (Xilinx Spartn II) is used. In this presentation, the design and implementation of the FPGA for the system will be reported. This includes the synchronous dynamic random access memory (SDRAM) controller and other system controllers, time sharing for auto-refresh of SDRAMs to reduce peak power, transmission and imaging modality selections, ECG data acquisition and synchronization, 160 MHz delay locked loop (DLL) for accurate timing, and data transfer via either a parallel port or a PCI bus for post image processing. [Work supported in part by Grant 5RO1 HL60301 from NIH.

A Network Architecture for Data-Driven Systems

DTIC Science & Technology

1985-07-01

ELABORATION. ..... ..... 26 Real - Time Operating System . ....... ......... 26 Secondary Memory Utilization. ........ ....... 26 Data Flow Graphical...discussions followed by a flight simulator exam~ple. REAL - TIME OPERATING SYSTEM An operating system needs to be designed exclusively for real-time...Assessment. (SDWA) module. The SDWA module is tightly coupled to the real - time operating system . This module must determine the sensitivity to

Stand-alone development system using a KIM-1 microcomputer module

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1978-01-01

A small microprocessor-based system designed to: contain all or most of the interface hardware, designed to be easy to access and modify the hardware, to be capable of being strapped to the seat of a small general aviation aircraft, and to be independent of the aircraft power system is described. The system is used to develop a low cost Loran C sensor processor, but is designed such that the Loran interface boards may be removed and other hardware interfaces inserted into the same connectors. This flexibility is achieved through memory-mapping techniques into the microprocessor.

Reducing Interprocessor Dependence in Recoverable Distributed Shared Memory

NASA Technical Reports Server (NTRS)

Janssens, Bob; Fuchs, W. Kent

1994-01-01

Checkpointing techniques in parallel systems use dependency tracking and/or message logging to ensure that a system rolls back to a consistent state. Traditional dependency tracking in distributed shared memory (DSM) systems is expensive because of high communication frequency. In this paper we show that, if designed correctly, a DSM system only needs to consider dependencies due to the transfer of blocks of data, resulting in reduced dependency tracking overhead and reduced potential for rollback propagation. We develop an ownership timestamp scheme to tolerate the loss of block state information and develop a passive server model of execution where interactions between processors are considered atomic. With our scheme, dependencies are significantly reduced compared to the traditional message-passing model.

Enhancing effects of acute psychosocial stress on priming of non-declarative memory in healthy young adults.

PubMed

Hidalgo, Vanesa; Villada, Carolina; Almela, Mercedes; Espín, Laura; Gómez-Amor, Jesús; Salvador, Alicia

2012-05-01

Social stress affects cognitive processes in general, and memory performance in particular. However, the direction of these effects has not been clearly established, as it depends on several factors. Our aim was to determine the impact of the hypothalamus-pituitary-adrenal (HPA) axis and sympathetic nervous system (SNS) reactivity to psychosocial stress on short-term non-declarative memory and declarative memory performance. Fifty-two young participants (18 men, 34 women) were subjected to the Trier Social Stress Task (TSST) and a control condition in a crossover design. Implicit memory was assessed by a priming test, and explicit memory was assessed by the Rey Auditory Verbal Learning Test (RAVLT). The TSST provoked greater salivary cortisol and salivary alpha-amylase (sAA) responses than the control task. Men had a higher cortisol response to stress than women, but no sex differences were found for sAA release. Stress was associated with an enhancement of priming but did not affect declarative memory. Additionally, the enhancement on the priming test was higher in those whose sAA levels increased more in response to stress (r(48) = 0.339, p = 0.018). Our results confirm an effect of acute stress on priming, and that this effect is related to SNS activity. In addition, they suggest a different relationship between stress biomarkers and the different memory systems.

An alternative design for a sparse distributed memory

NASA Technical Reports Server (NTRS)

Jaeckel, Louis A.

1989-01-01

A new design for a Sparse Distributed Memory, called the selected-coordinate design, is described. As in the original design, there are a large number of memory locations, each of which may be activated by many different addresses (binary vectors) in a very large address space. Each memory location is defined by specifying ten selected coordinates (bit positions in the address vectors) and a set of corresponding assigned values, consisting of one bit for each selected coordinate. A memory location is activated by an address if, for all ten of the locations's selected coordinates, the corresponding bits in the address vector match the respective assigned value bits, regardless of the other bits in the address vector. Some comparative memory capacity and signal-to-noise ratio estimates for the both the new and original designs are given. A few possible hardware embodiments of the new design are described.

NASA Space Engineering Research Center for VLSI systems design

NASA Technical Reports Server (NTRS)

1991-01-01

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

A Very Low Cost BCH Decoder for High Immunity of On-Chip Memories

NASA Astrophysics Data System (ADS)

Seo, Haejun; Han, Sehwan; Heo, Yoonseok; Cho, Taewon

BCH(Bose-Chaudhuri-Hoquenbhem) code, a type of block codes-cyclic codes, has very strong error-correcting ability which is vital for performing the error protection on the memory system. BCH code has many kinds of dual algorithms, PGZ(Pererson-Gorenstein-Zierler) algorithm out of them is advantageous in view of correcting the errors through the simple calculation in t value. However, this is problematic when this becomes 0 (divided by zero) in case ν ≠ t. In this paper, the circuit would be simplified by suggesting the multi-mode hardware architecture in preparation that v were 0~3. First, production cost would be less thanks to the smaller number of gates. Second, lessening power consumption could lengthen the recharging period. The very low cost and simple datapath make our design a good choice in small-footprint SoC(System on Chip) as ECC(Error Correction Code/Circuit) in memory system.

Unconstrained Recovery Characterization of Shape-Memory Polymer Networks for Cardiovascular Applications

PubMed Central

Yakacki, Christopher M.; Shandas, Robin; Lanning, Craig; Rech, Bryan; Eckstein, Alex; Gall, Ken

2009-01-01

Shape-memory materials have been proposed in biomedical device design due to their ability to facilitate minimally invasive surgery and recover to a predetermined shape in-vivo. Use of the shape-memory effect in polymers is proposed for cardiovascular stent interventions to reduce the catheter size for delivery and offer highly controlled and tailored deployment at body temperature. Shape-memory polymer networks were synthesized via photopolymerization of tert-butyl acrylate and poly (ethylene glycol) dimethacrylate to provide precise control over the thermomechanical response of the system. The free recovery response of the polymer stents at body temperature was studied as a function of glass transition temperature (Tg), crosslink density, geometrical perforation, and deformation temperature, all of which can be independently controlled. Room temperature storage of the stents was shown to be highly dependent on Tg and crosslink density. The pressurized response of the stents is also demonstrated to depend on crosslink density. This polymer system exhibits a wide range of shape-memory and thermomechanical responses to adapt and meet specific needs of minimally invasive cardiovascular devices. PMID:17296222

A class of designs for a sparse distributed memory

NASA Technical Reports Server (NTRS)

Jaeckel, Louis A.

1989-01-01

A general class of designs for a space distributed memory (SDM) is described. The author shows that Kanerva's original design and the selected-coordinate design are related, and that there is a series of possible intermediate designs between those two designs. In each such design, the set of addresses that activate a memory location is a sphere in the address space. We can also have hybrid designs, in which the memory locations may be a mixture of those found in the other designs. In some applications, the bits of the read and write addresses that will actually be used might be mostly zeros; that is, the addresses might lie on or near z hyperplane in the address space. The author describes a hyperplane design which is adapted to this situation and compares it to an adaptation of Kanerva's design. To study the performance of these designs, he computes the expected number of memory locations activated by both of two addresses.

Nanogap-Engineerable Electromechanical System for Ultralow Power Memory.

PubMed

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei; Chu, Weiguo; Zhou, Haiqing; Sun, Lianfeng

2018-02-01

Nanogap engineering of low-dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub-5 nm nanogaped single-walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10 -19 J bit -1 ), ON/OFF ratio of 10 5 , stable switching ON operations, and over 30 h retention time in ambient conditions.

Nanogap‐Engineerable Electromechanical System for Ultralow Power Memory

PubMed Central

Zhang, Jian; Deng, Ya; Hu, Xiao; Nshimiyimana, Jean Pierre; Liu, Siyu; Chi, Xiannian; Wu, Pei; Dong, Fengliang; Chen, Peipei

2017-01-01

Abstract Nanogap engineering of low‐dimensional nanomaterials has received considerable interest in a variety of fields, ranging from molecular electronics to memories. Creating nanogaps at a certain position is of vital importance for the repeatable fabrication of the devices. Here, a rational design of nonvolatile memories based on sub‐5 nm nanogaped single‐walled carbon nanotubes (SWNTs) via the electromechanical motion is reported. The nanogaps are readily realized by electroburning in a partially suspended SWNT device with nanoscale region. The SWNT memory devices are applicable for both metallic and semiconducting SWNTs, resolving the challenge of separation of semiconducting SWNTs from metallic ones. Meanwhile, the memory devices exhibit excellent performance: ultralow writing energy (4.1 × 10−19 J bit−1), ON/OFF ratio of 105, stable switching ON operations, and over 30 h retention time in ambient conditions. PMID:29619307

Designing high-performance cost-efficient embedded SRAM in deep-submicron era

NASA Astrophysics Data System (ADS)

Kobozeva, Olga; Venkatraman, Ramnath; Castagnetti, Ruggero; Duan, Franklin; Kamath, Arvind; Ramesh, Shiva

2004-05-01

We have previously presented the smallest and fastest 6 Transistor (6T)-Static Random Access Memories (SRAM) bitcells for System-on-Chip (SoC) high-density (HD) memories in 0.18 μm and 0.13 μm technologies. Our 1.87 μm2 6TSRAM bitcell with cell current of 47 μA and industry lowest soft error rate (0.35 FIT/Kbit) is used to assemble memory blocks embedded into SoC designs in 0.13 μm process technology. Excellent performance is achieved at a low overall cost, as our bitcells are based on standard CMOS process and demonstrate high yields in manufacturing. This paper discusses our methodology of embedded SRAM bitcell design. The key aspects of our approach are: 1) judicious selection of tightest achievable yet manufacturable design rules to build the cell; 2) compatibility with standard Optical Proximity Correction (OPC) flow; 3) use of parametric testing and yield analysis to achieve excellent design robustness and manufacturability. A thorough understanding of process limitations, particularly those related to photolithography was critical to the successful design and manufacturing of our aggressive, yet robust SRAM bitcells. The patterning of critical layers, such as diffusion, poly gate, contact and metal 1 has profound implications on functionality, electrical performance and manufacturability of memories. We have conducted the development of SRAM bitcells using two approaches for OPC: a) "manual" OPC, wherein the bitcell layout of each of the critical layers is achieved using iterative improvement of layout & aerial image simulation and b) automated OPC-compatible design, wherein the drawn bitcell layout becomes a subject of a full chip OPC. While manual-OPC remains a popular option, automated OPC-compatible bitcell design is very attractive, as it does not require additional development costs to achieve fab-to-fab portability. In both cases we have obtained good results with respect to patterning of the critical layers, electrical performance of the bitcell and memory yields. A critical part of our memory technology development effort is the design of memory-specific test structures that are used for: a) verifying electrical characteristics of SRAM transistors and b) confirming the robustness of the design rules used within the SRAM cell. In addition to electrical test structures, we have a fully functional SRAM test chip called RAMPCM that is composed of sub-blocks each designated to evaluate the robustness of a specific critical design rule used within the bitcells. The results from the electrical testing and RAMPCM yield analysis are used to identify opportunities for improvements in the layout design. The paper will also suggest some techniques that can result in more design friendly OPC solutions. Our work indicates that future IC designs can benefit from an automated OPC tool that can intelligently handle layout modifications according to design priorities.

Performance of Integrated Fiber Optic, Piezoelectric, and Shape Memory Alloy Actuators/Sensors in Thermoset Composites

NASA Technical Reports Server (NTRS)

Trottier, C. Michael

1996-01-01

Recently, scientists and engineers have investigated the advantages of smart materials and structures by including actuators in material systems for controlling and altering the response of structural environments. Applications of these materials systems include vibration suppression/isolation, precision positioning, damage detection and tunable devices. Some of the embedded materials being investigated for accomplishing these tasks include piezoelectric ceramics, shape memory alloys, and fiber optics. These materials have some benefits and some shortcomings; each is being studied for use in active material design in the SPICES (Synthesis and Processing of Intelligent Cost Effective Structures) Consortium. The focus of this paper concerns the manufacturing aspects of smart structures by incorporating piezoelectric ceramics, shape memory alloys and fiber optics in a reinforced thermoset matrix via resin transfer molding (RTM).

Parallel processing for scientific computations

NASA Technical Reports Server (NTRS)

Alkhatib, Hasan S.

1995-01-01

The scope of this project dealt with the investigation of the requirements to support distributed computing of scientific computations over a cluster of cooperative workstations. Various experiments on computations for the solution of simultaneous linear equations were performed in the early phase of the project to gain experience in the general nature and requirements of scientific applications. A specification of a distributed integrated computing environment, DICE, based on a distributed shared memory communication paradigm has been developed and evaluated. The distributed shared memory model facilitates porting existing parallel algorithms that have been designed for shared memory multiprocessor systems to the new environment. The potential of this new environment is to provide supercomputing capability through the utilization of the aggregate power of workstations cooperating in a cluster interconnected via a local area network. Workstations, generally, do not have the computing power to tackle complex scientific applications, making them primarily useful for visualization, data reduction, and filtering as far as complex scientific applications are concerned. There is a tremendous amount of computing power that is left unused in a network of workstations. Very often a workstation is simply sitting idle on a desk. A set of tools can be developed to take advantage of this potential computing power to create a platform suitable for large scientific computations. The integration of several workstations into a logical cluster of distributed, cooperative, computing stations presents an alternative to shared memory multiprocessor systems. In this project we designed and evaluated such a system.

Ultra-dense magnetoresistive mass memory

NASA Technical Reports Server (NTRS)

Daughton, J. M.; Sinclair, R.; Dupuis, T.; Brown, J.

1992-01-01

This report details the progress and accomplishments of Nonvolatile Electronics (NVE), Inc., on the design of the wafer scale MRAM mass memory system during the fifth quarter of the project. NVE has made significant progress this quarter on the one megabit design in several different areas. A test chip, which will verify a working GMR bit with the dimensions required by the 1 Meg chip, has been designed, laid out, and is currently being processed in the NVE labs. This test chip will allow electrical specifications, tolerances, and processing issues to be finalized before construction of the actual chip, thus providing a greater assurance of success of the final 1 Meg design. A model has been developed to accurately simulate the parasitic effects of unselected sense lines. This model gives NVE the ability to perform accurate simulations of the array electronic and test different design concepts. Much of the circuit design for the 1 Meg chip has been completed and simulated and these designs are included. Progress has been made in the wafer scale design area to verify the reliable operation of the 16 K macrocell. This is currently being accomplished with the design and construction of two stand alone test systems which will perform life tests and gather data on reliabiliy and wearout mechanisms for analysis.

Modification of existing human motor memories is enabled by primary cortical processing during memory reactivation.

PubMed

Censor, Nitzan; Dimyan, Michael A; Cohen, Leonardo G

2010-09-14

One of the most challenging tasks of the brain is to constantly update the internal neural representations of existing memories. Animal studies have used invasive methods such as direct microfusion of protein inhibitors to designated brain areas, in order to study the neural mechanisms underlying modification of already existing memories after their reactivation during recall [1-4]. Because such interventions are not possible in humans, it is not known how these neural processes operate in the human brain. In a series of experiments we show here that when an existing human motor memory is reactivated during recall, modification of the memory is blocked by virtual lesion [5] of the related primary cortical human brain area. The virtual lesion was induced by noninvasive repetitive transcranial magnetic stimulation guided by a frameless stereotactic brain navigation system and each subject's brain image. The results demonstrate that primary cortical processing in the human brain interacting with pre-existing reactivated memory traces is critical for successful modification of the existing related memory. Modulation of reactivated memories by noninvasive cortical stimulation may have important implications for human memory research and have far-reaching clinical applications. Copyright © 2010 Elsevier Ltd. All rights reserved.

Novel memory architecture for video signal processor

NASA Astrophysics Data System (ADS)

Hung, Jen-Sheng; Lin, Chia-Hsing; Jen, Chein-Wei

1993-11-01

An on-chip memory architecture for video signal processor (VSP) is proposed. This memory structure is a two-level design for the different data locality in video applications. The upper level--Memory A provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level--Memory B provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. The needed memory size is decided by the memory usage analysis for video algorithms and the number of function units. Both levels of memory adopted a dual-port memory scheme to sustain the simultaneous read and write operations. Especially, Memory B uses multiple one-read-one-write memory banks to emulate the real multiport memory. Therefore, one can change the configuration of Memory B to several sets of memories with variable read/write ports by adjusting the bus switches. Then the numbers of read ports and write ports in proposed memory can meet requirement of data flow patterns in different video coding algorithms. We have finished the design of a prototype memory design using 1.2- micrometers SPDM SRAM technology and will fabricated it through TSMC, in Taiwan.

Creative Classroom Assignment Through Database Management.

ERIC Educational Resources Information Center

Shah, Vivek; Bryant, Milton

1987-01-01

The Faculty Scheduling System (FSS), a database management system designed to give administrators the ability to schedule faculty in a fast and efficient manner is described. The FSS, developed using dBASE III, requires an IBM compatible microcomputer with a minimum of 256K memory. (MLW)

A test of the reward-value hypothesis.

PubMed

Smith, Alexandra E; Dalecki, Stefan J; Crystal, Jonathon D

2017-03-01

Rats retain source memory (memory for the origin of information) over a retention interval of at least 1 week, whereas their spatial working memory (radial maze locations) decays within approximately 1 day. We have argued that different forgetting functions dissociate memory systems. However, the two tasks, in our previous work, used different reward values. The source memory task used multiple pellets of a preferred food flavor (chocolate), whereas the spatial working memory task provided access to a single pellet of standard chow-flavored food at each location. Thus, according to the reward-value hypothesis, enhanced performance in the source memory task stems from enhanced encoding/memory of a preferred reward. We tested the reward-value hypothesis by using a standard 8-arm radial maze task to compare spatial working memory accuracy of rats rewarded with either multiple chocolate or chow pellets at each location using a between-subjects design. The reward-value hypothesis predicts superior accuracy for high-valued rewards. We documented equivalent spatial memory accuracy for high- and low-value rewards. Importantly, a 24-h retention interval produced equivalent spatial working memory accuracy for both flavors. These data are inconsistent with the reward-value hypothesis and suggest that reward value does not explain our earlier findings that source memory survives unusually long retention intervals.

Evaluation of reinitialization-free nonvolatile computer systems for energy-harvesting Internet of things applications

NASA Astrophysics Data System (ADS)

Onizawa, Naoya; Tamakoshi, Akira; Hanyu, Takahiro

2017-08-01

In this paper, reinitialization-free nonvolatile computer systems are designed and evaluated for energy-harvesting Internet of things (IoT) applications. In energy-harvesting applications, as power supplies generated from renewable power sources cause frequent power failures, data processed need to be backed up when power failures occur. Unless data are safely backed up before power supplies diminish, reinitialization processes are required when power supplies are recovered, which results in low energy efficiencies and slow operations. Using nonvolatile devices in processors and memories can realize a faster backup than a conventional volatile computer system, leading to a higher energy efficiency. To evaluate the energy efficiency upon frequent power failures, typical computer systems including processors and memories are designed using 90 nm CMOS or CMOS/magnetic tunnel junction (MTJ) technologies. Nonvolatile ARM Cortex-M0 processors with 4 kB MRAMs are evaluated using a typical computing benchmark program, Dhrystone, which shows a few order-of-magnitude reductions in energy in comparison with a volatile processor with SRAM.

A Virtual Radial Arm Maze for the Study of Multiple Memory Systems in a Functional Magnetic Resonance Imaging Environment

PubMed Central

Xu, Dongrong; Hao, Xuejun; Wang, Zhishun; Duan, Yunsuo; Liu, Feng; Marsh, Rachel; Yu, Shan; Peterson, Bradley S.

2015-01-01

An increasing number of functional brain imaging studies are employing computer-based virtual reality (VR) to study changes in brain activity during the performance of high-level psychological and cognitive tasks. We report the development of a VR radial arm maze that adapts for human use in a scanning environment with the same general experimental design of behavioral tasks as that has been used with remarkable effectiveness for the study of multiple memory systems in rodents. The software platform is independent of specific computer hardware and operating systems, as we aim to provide shared access to this technology by the research community. We hope that doing so will provide greater standardization of software platform and study paradigm that will reduce variability and improve the comparability of findings across studies. We report the details of the design and implementation of this platform and provide information for downloading of the system for demonstration and research applications. PMID:26366052

Supercomputing '91; Proceedings of the 4th Annual Conference on High Performance Computing, Albuquerque, NM, Nov. 18-22, 1991

NASA Technical Reports Server (NTRS)

1991-01-01

Various papers on supercomputing are presented. The general topics addressed include: program analysis/data dependence, memory access, distributed memory code generation, numerical algorithms, supercomputer benchmarks, latency tolerance, parallel programming, applications, processor design, networks, performance tools, mapping and scheduling, characterization affecting performance, parallelism packaging, computing climate change, combinatorial algorithms, hardware and software performance issues, system issues. (No individual items are abstracted in this volume)

Computing Equilibrium Chemical Compositions

NASA Technical Reports Server (NTRS)

Mcbride, Bonnie J.; Gordon, Sanford

1995-01-01

Chemical Equilibrium With Transport Properties, 1993 (CET93) computer program provides data on chemical-equilibrium compositions. Aids calculation of thermodynamic properties of chemical systems. Information essential in design and analysis of such equipment as compressors, turbines, nozzles, engines, shock tubes, heat exchangers, and chemical-processing equipment. CET93/PC is version of CET93 specifically designed to run within 640K memory limit of MS-DOS operating system. CET93/PC written in FORTRAN.

Quantifying Precision and Availability of Location Memory in Everyday Pictures and Some Implications for Picture Database Design

ERIC Educational Resources Information Center

Lansdale, Mark W.; Oliff, Lynda; Baguley, Thom S.

2005-01-01

The authors investigated whether memory for object locations in pictures could be exploited to address known difficulties of designing query languages for picture databases. M. W. Lansdale's (1998) model of location memory was adapted to 4 experiments observing memory for everyday pictures. These experiments showed that location memory is…

Fault-tolerant computer study. [logic designs for building block circuits

NASA Technical Reports Server (NTRS)

Rennels, D. A.; Avizienis, A. A.; Ercegovac, M. D.

1981-01-01

A set of building block circuits is described which can be used with commercially available microprocessors and memories to implement fault tolerant distributed computer systems. Each building block circuit is intended for VLSI implementation as a single chip. Several building blocks and associated processor and memory chips form a self checking computer module with self contained input output and interfaces to redundant communications buses. Fault tolerance is achieved by connecting self checking computer modules into a redundant network in which backup buses and computer modules are provided to circumvent failures. The requirements and design methodology which led to the definition of the building block circuits are discussed.

HOLOMEM, optical mass memory investigations, volume 1

NASA Technical Reports Server (NTRS)

Roberts, H. N.

1977-01-01

Research and design activities in support of the development of a 10 to the 12th power-bit holographic read/write optical mass memory (HOLOMEM) with some moving parts for space applications are summarized. The report consists of four sections: (1) a general introduction, which includes a summary of key accomplishments and the principal conclusions of the study; (2) a comprehensive analysis of alternative HOLOMEM system concepts; (3) a discussion of important design and tradeoff considerations related to the fabrication, test, and evaluation of a breadboard holographic recorder/reproducer; and (4) a summary of experimental data generated to define the holographic recording performance of two quasi-commercial photoplastic recording films.

Concurrent Image Processing Executive (CIPE)

NASA Technical Reports Server (NTRS)

Lee, Meemong; Cooper, Gregory T.; Groom, Steven L.; Mazer, Alan S.; Williams, Winifred I.

1988-01-01

The design and implementation of a Concurrent Image Processing Executive (CIPE), which is intended to become the support system software for a prototype high performance science analysis workstation are discussed. The target machine for this software is a JPL/Caltech Mark IIIfp Hypercube hosted by either a MASSCOMP 5600 or a Sun-3, Sun-4 workstation; however, the design will accommodate other concurrent machines of similar architecture, i.e., local memory, multiple-instruction-multiple-data (MIMD) machines. The CIPE system provides both a multimode user interface and an applications programmer interface, and has been designed around four loosely coupled modules; (1) user interface, (2) host-resident executive, (3) hypercube-resident executive, and (4) application functions. The loose coupling between modules allows modification of a particular module without significantly affecting the other modules in the system. In order to enhance hypercube memory utilization and to allow expansion of image processing capabilities, a specialized program management method, incremental loading, was devised. To minimize data transfer between host and hypercube a data management method which distributes, redistributes, and tracks data set information was implemented.

Design and realization of flash translation layer in tiny embedded system

NASA Astrophysics Data System (ADS)

Ren, Xiaoping; Sui, Chaoya; Luo, Zhenghua; Cao, Wenji

2018-05-01

We design a solution of tiny embedded device NAND Flash storage system on the basis of deeply studying the characteristics of widely used NAND Flash in the embedded devices in order to adapt to the development of intelligent interconnection trend and solve the storage problem of large data volume in tiny embedded system. The hierarchical structure and function purposes of the system are introduced. The design and realization of address mapping, error correction, bad block management, wear balance, garbage collection and other algorithms in flash memory transformation layer are described in details. NAND Flash drive and management are realized on STM32 micro-controller, thereby verifying design effectiveness and feasibility.

Numerical aerodynamic simulation facility preliminary study, volume 2 and appendices

NASA Technical Reports Server (NTRS)

1977-01-01

Data to support results obtained in technology assessment studies are presented. Objectives, starting points, and future study tasks are outlined. Key design issues discussed in appendices include: data allocation, transposition network design, fault tolerance and trustworthiness, logic design, processing element of existing components, number of processors, the host system, alternate data base memory designs, number representation, fast div 521 instruction, architectures, and lockstep array versus synchronizable array machine comparison.

BAE Systems Radiation Hardened SpaceWire ASIC and Roadmap

NASA Technical Reports Server (NTRS)

Berger, Richard; Milliser, Myrna; Kapcio, Paul; Stanley, Dan; Moser, David; Koehler, Jennifer; Rakow, Glenn; Schnurr, Richard

2006-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS, technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASlC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a 4-port SpaceWire router with two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, -and a memory controller for additional external memory use. The SpaceWire ASlC is planned for use on both the Geostationary Operational Environmental Satellites (GOES)-R and the Lunar Reconnaissance Orbiter (LRO). Engineering parts have already been delivered to both programs. This paper discusses the SpaceWire protocol and those elements of it that have been built into the current SpaceWire reusable core. There are features within the core that go beyond the current standard that can be enabled or disabled by the user and these will be described. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be discussed. Optional configurations within user systems will be shown. The physical imp!ementation of the design will be described and test results from the hardware will be discussed. Finally, the BAE Systems roadmap for SpaceWire developments will be discussed, including some products already in design as well as longer term plans.

Cultural resource applications for a GIS: Stone conservation at Jefferson and Lincoln Memorials

USGS Publications Warehouse

Joly, Kyle; Donald, Tony; Comer, Douglas

1998-01-01

Geographical information systems are rapidly becoming essential tools for land management. They provide a way to link landscape features to the wide variety of information that managers must consider when formulating plans for a site, designing site improvement and restoration projects, determining maintenance projects and protocols, and even interpreting the site. At the same time, they can be valuable research tools.Standing structures offer a different sort of geography, even though a humanly contrived one. Therefore, the capability of a geographical information system (GIS) to link geographical units to the information pertinent to the site and resource management can be employed in the management of standing structures. This was the idea that inspired the use of a GIS software, ArcView, to link computer aided design CAD) drawings of the Jefferson and Lincoln Memorials with inventories of the stones in the memorials. Both the CAD drawings and the inventory were in existence; what remained to be done was to modify the CAD files and place the inventory in an appropriately designed computerized database, and then to link the two in a GIS project. This work was carried out at the NPS Denver Service Center, Resource Planning Group, Applied Archaeology Center (DSC-RPG-AAC), in Silver Spring, Maryland, with the assistance of US/ICOMOS summer interns Katja Marasovic (Croatia) and Rastislav Gromnica (Slovakia), under the supervision of AAC office manager Douglas Comer. Project guidance was provided by Tony Donald, the Denver Service Center (DSC) project architect for the restoration of the Jefferson and Lincoln Memorials, and GIS consultation services by Kyle Joly.

Quantum memristors

DOE PAGES

Pfeiffer, P.; Egusquiza, I. L.; Di Ventra, M.; ...

2016-07-06

Technology based on memristors, resistors with memory whose resistance depends on the history of the crossing charges, has lately enhanced the classical paradigm of computation with neuromorphic architectures. However, in contrast to the known quantized models of passive circuit elements, such as inductors, capacitors or resistors, the design and realization of a quantum memristor is still missing. Here, we introduce the concept of a quantum memristor as a quantum dissipative device, whose decoherence mechanism is controlled by a continuous-measurement feedback scheme, which accounts for the memory. Indeed, we provide numerical simulations showing that memory effects actually persist in the quantummore » regime. Our quantization method, specifically designed for superconducting circuits, may be extended to other quantum platforms, allowing for memristor-type constructions in different quantum technologies. As a result, the proposed quantum memristor is then a building block for neuromorphic quantum computation and quantum simulations of non-Markovian systems.« less

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing

NASA Astrophysics Data System (ADS)

Rao, Feng; Ding, Keyuan; Zhou, Yuxing; Zheng, Yonghui; Xia, Mengjiao; Lv, Shilong; Song, Zhitang; Feng, Songlin; Ronneberger, Ider; Mazzarello, Riccardo; Zhang, Wei; Ma, Evan

2017-12-01

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge2Sb2Te5). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb2Te3) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.

Digital Holographic Data Storage with Fast Access

NASA Astrophysics Data System (ADS)

Ma, J.; Chang, T.; Choi, S.; Hong, J.

Recent investigations in holographic mass memory systems have produced proof of concept demonstrations that have highlighted their potential for providing unprecedented capacity, data transfer rates and fast random access performance [1-4]. The exploratory nature of most such investigations has been largely confined to benchtop experiments in which the practical constraints of packaging and environmental concerns have been ignored. We have embarked on an effort to demonstrate the holographic mass memory concept by developing a compact prototype system geared for avionics and similar applications, which demand the following features (mostly interdependent factors): (1) solid-state design (no moving parts), (2) fast data-seek time, (3) robustness with respect to environmental factors (temperature, vibration, shock). In this chapter, we report on the development and demonstration of two systems, one with 100 Mbytes and the other with more than 1 Gbyte of storage capacity. Both systems feature solid-state design with the addressing mechanism realized with acousto-optic deflectors that are capable of better than 50 µs data seek time. Since the basic designs for the two systems are similar, we describe only the larger system in detail. The operation of the smaller system has been demonstrated in various environments, including hand-held operation and thermal/mechanical shock, and a photograph of the smaller system is provided as well as actual digital data retrieved from the same system.

Packaged digital holographic data storage with fast access

NASA Astrophysics Data System (ADS)

Ma, Jian; Chang, Tallis Y.; Choi, Sung; Hong, John H.

1998-11-01

Recent investigations in holographic mass memory systems have produced proof of concept demonstrations that have highlighted their potential for providing unprecedented capacity, data transfer rates and fast random access performance. The exploratory nature of most such investigations have been largely confined to benchtop experiments in which the practical constraints of packaging and environmental concerns have been ignored. We have embarked on an effort to demonstrate the holographic mass memory concept by developing a compact prototype system geared for avionics and similar applications which demand the following features (mostly interdependent factors): (1) solid state design (no moving parts), (2) fast data seek time, (3) robust with respect to environmental factors (temperature, vibration, shock). In this paper, we report on the development and demonstration of two systems, one with 100 Mbytes and the other with more than 1 Gbyte of storage capacity. Both systems feature solid state design with the addressing mechanism realized with acousto- optic deflectors that are capable of better than 50 microseconds data seek time. Since the basic designs for the two systems are similar, we describe only the larger system in detail. The operation of the smaller system has been demonstrated in various environments including hand-held operation and thermal/mechanical shock and a photograph of the smaller system is provided as well as actual digital data retrieved from the same system.

Estimating Production Cost While Linking Combat Systems and Ship Design

DTIC Science & Technology

2012-12-01

individuals:  In memory of CAPT Alan Goodwin “Dex” Poindexter USN, whose words of encouragement motivated me to put forth my best effort for this thesis...Boston: Butterworth-Heinemann. The University of Arizona. (2004, December 30). System movement: Autobiographical retrospectives: Contributions to the

Design of a modular digital computer system, CDRL no. D001, final design plan

NASA Technical Reports Server (NTRS)

Easton, R. A.

1975-01-01

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics.

Initial Results from On-Orbit Testing of the Fram Memory Test Experiment on the Fastsat Micro-Satellite

NASA Technical Reports Server (NTRS)

MacLeond, Todd C.; Sims, W. Herb; Varnavas,Kosta A.; Ho, Fat D.

2011-01-01

The Memory Test Experiment is a space test of a ferroelectric memory device on a low Earth orbit satellite that launched in November 2010. The memory device being tested is a commercial Ramtron Inc. 512K memory device. The circuit was designed into the satellite avionics and is not used to control the satellite. The test consists of writing and reading data with the ferroelectric based memory device. Any errors are detected and are stored on board the satellite. The data is sent to the ground through telemetry once a day. Analysis of the data can determine the kind of error that was found and will lead to a better understanding of the effects of space radiation on memory systems. The test is one of the first flight demonstrations of ferroelectric memory in a near polar orbit which allows testing in a varied radiation environment. The initial data from the test is presented. This paper details the goals and purpose of this experiment as well as the development process. The process for analyzing the data to gain the maximum understanding of the performance of the ferroelectric memory device is detailed.

Dopaminergic influences on formation of a motor memory.

PubMed

Flöel, Agnes; Breitenstein, Caterina; Hummel, Friedhelm; Celnik, Pablo; Gingert, Christian; Sawaki, Lumy; Knecht, Stefan; Cohen, Leonardo G

2005-07-01

The ability of the central nervous system to form motor memories, a process contributing to motor learning and skill acquisition, decreases with age. Dopaminergic activity, one of the mechanisms implicated in memory formation, experiences a similar decline with aging. It is possible that restoring dopaminergic function in elderly adults could lead to improved formation of motor memories with training. We studied the influence of a single oral dose of levodopa (100mg) administered preceding training on the ability to encode an elementary motor memory in the primary motor cortex of elderly and young healthy volunteers in a randomized, double-blind, placebo-controlled design. Attention to the task and motor training kinematics were comparable across age groups and sessions. In young subjects, encoding a motor memory under placebo was more prominent than in older subjects, and the encoding process was accelerated by intake of levodopa. In the elderly group, diminished motor memory encoding under placebo was enhanced by intake of levodopa to levels present in younger subjects. Therefore, upregulation of dopaminergic activity accelerated memory formation in young subjects and restored the ability to form a motor memory in elderly subjects; possible mechanisms underlying the beneficial effects of dopaminergic agents on motor learning in neurorehabilitation.

Design and implementation of a medium speed communications interface and protocol for a low cost, refreshed display computer

NASA Technical Reports Server (NTRS)

Phyne, J. R.; Nelson, M. D.

1975-01-01

The design and implementation of hardware and software systems involved in using a 40,000 bit/second communication line as the connecting link between an IMLAC PDS 1-D display computer and a Univac 1108 computer system were described. The IMLAC consists of two independent processors sharing a common memory. The display processor generates the deflection and beam control currents as it interprets a program contained in the memory; the minicomputer has a general instruction set and is responsible for starting and stopping the display processor and for communicating with the outside world through the keyboard, teletype, light pen, and communication line. The processing time associated with each data byte was minimized by designing the input and output processes as finite state machines which automatically sequence from each state to the next. Several tests of the communication link and the IMLAC software were made using a special low capacity computer grade cable between the IMLAC and the Univac.

A site oriented supercomputer for theoretical physics: The Fermilab Advanced Computer Program Multi Array Processor System (ACMAPS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nash, T.; Atac, R.; Cook, A.

1989-03-06

The ACPMAPS multipocessor is a highly cost effective, local memory parallel computer with a hypercube or compound hypercube architecture. Communication requires the attention of only the two communicating nodes. The design is aimed at floating point intensive, grid like problems, particularly those with extreme computing requirements. The processing nodes of the system are single board array processors, each with a peak power of 20 Mflops, supported by 8 Mbytes of data and 2 Mbytes of instruction memory. The system currently being assembled has a peak power of 5 Gflops. The nodes are based on the Weitek XL Chip set. Themore » system delivers performance at approximately $300/Mflop. 8 refs., 4 figs.« less

The neural substrates of recognition memory for verbal information: spanning the divide between short- and long-term memory.

PubMed

Buchsbaum, Bradley R; Padmanabhan, Aarthi; Berman, Karen Faith

2011-04-01

One of the classic categorical divisions in the history of memory research is that between short-term and long-term memory. Indeed, because memory for the immediate past (a few seconds) and memory for the relatively more remote past (several seconds and beyond) are assumed to rely on distinct neural systems, more often than not, memory research has focused either on short- (or "working memory") or on long-term memory. Using an auditory-verbal continuous recognition paradigm designed for fMRI, we examined how the neural signatures of recognition memory change across an interval of time (from 2.5 to 30 sec) that spans this hypothetical division between short- and long-term memory. The results revealed that activity during successful auditory-verbal item recognition in inferior parietal cortex and the posterior superior temporal lobe was maximal for early lags, whereas, conversely, activity in the left inferior frontal gyrus increased as a function of lag. Taken together, the results reveal that as the interval between item repetitions increases, there is a shift in the distribution of memory-related activity that moves from posterior temporo-parietal cortex (lags 1-4) to inferior frontal regions (lags 5-10), indicating that as time advances, the burden of recognition memory is increasingly placed on top-down retrieval mechanisms that are mediated by structures in inferior frontal cortex.

Embedded real-time operating system micro kernel design

NASA Astrophysics Data System (ADS)

Cheng, Xiao-hui; Li, Ming-qiang; Wang, Xin-zheng

2005-12-01

Embedded systems usually require a real-time character. Base on an 8051 microcontroller, an embedded real-time operating system micro kernel is proposed consisting of six parts, including a critical section process, task scheduling, interruption handle, semaphore and message mailbox communication, clock managent and memory managent. Distributed CPU and other resources are among tasks rationally according to the importance and urgency. The design proposed here provides the position, definition, function and principle of micro kernel. The kernel runs on the platform of an ATMEL AT89C51 microcontroller. Simulation results prove that the designed micro kernel is stable and reliable and has quick response while operating in an application system.

Innovative microwave design leads to smart, small EW systems

NASA Astrophysics Data System (ADS)

Niehenke, Edward C.

1988-02-01

An account is given of the state-of-the-art in microwave component and system design for EW systems, whose size and weight has been progressively reduced in recent years as a result of continuing design innovation in microwave circuitry. Typically, AI-function computers are employed to control microwave functions in a way that allows rapid RAM or ROM software modification to meet new performance requirements, thereby obviating hardware modifications. Attention is given to high-isolation GaAs MMIC filters, switches and amplifiers, frequency converters, instantaneous frequency measurement systems, frequency translators, digital RF memories, and high effective radiated power solid-state active antenna arrays.

Static Behavior of Chalcogenide Based Programmable Metallization Cells

NASA Astrophysics Data System (ADS)

Rajabi, Saba

Nonvolatile memory (NVM) technologies have been an integral part of electronic systems for the past 30 years. The ideal non-volatile memory have minimal physical size, energy usage, and cost while having maximal speed, capacity, retention time, and radiation hardness. A promising candidate for next-generation memory is ion-conducting bridging RAM which is referred to as programmable metallization cell (PMC), conductive bridge RAM (CBRAM), or electrochemical metallization memory (ECM), which is likely to surpass flash memory in all the ideal memory characteristics. A comprehensive physics-based model is needed to completely understand PMC operation and assist in design optimization. To advance the PMC modeling effort, this thesis presents a precise physical model parameterizing materials associated with both ion-rich and ion-poor layers of the PMC's solid electrolyte, so that captures the static electrical behavior of the PMC in both its low-resistance on-state (LRS) and high resistance off-state (HRS). The experimental data is measured from a chalcogenide glass PMC designed and manufactured at ASU. The static on- and off-state resistance of a PMC device composed of a layered (Ag-rich/Ag-poor) Ge30Se70 ChG film is characterized and modeled using three dimensional simulation code written in Silvaco Atlas finite element analysis software. Calibrating the model to experimental data enables the extraction of device parameters such as material bandgaps, workfunctions, density of states, carrier mobilities, dielectric constants, and affinities. The sensitivity of our modeled PMC to the variation of its prominent achieved material parameters is examined on the HRS and LRS impedance behavior. The obtained accurate set of material parameters for both Ag-rich and Ag-poor ChG systems and process variation verification on electrical characteristics enables greater fidelity in PMC device simulation, which significantly enhances our ability to understand the underlying physics of ChG-based resistive switching memory.

Development of a character, line and point display system. [for medical records

NASA Technical Reports Server (NTRS)

Owen, E. W.

1977-01-01

A compact graphics terminal for use as the input to a computerized medical records system is described. The principal mode of communication between the terminal and the records system is by checklists and menu selection. However, the terminal accepts short, handwritten messages as well as conventional alphanumeric input. The terminal consists of an electronic tablet, a display, a microcomputer controller, a character generator, and a refresh memory for the display. An Intel SBC 80/10 microcomputer controls the flow of information and a 16 kilobyte memory stores the point-by-point array of information to be displayed. A specially designed interface continuously generates the raster display without the intervention of the microcomputer.

Low Temperature Shape Memory Alloys for Adaptive, Autonomous Systems Project

NASA Technical Reports Server (NTRS)

Falker, John; Zeitlin, Nancy; Williams, Martha; Benafan, Othmane; Fesmire, James

2015-01-01

The objective of this joint activity between Kennedy Space Center (KSC) and Glenn Research Center (GRC) is to develop and evaluate the applicability of 2-way SMAs in proof-of-concept, low-temperature adaptive autonomous systems. As part of this low technology readiness (TRL) activity, we will develop and train low-temperature novel, 2-way shape memory alloys (SMAs) with actuation temperatures ranging from 0 C to 150 C. These experimental alloys will also be preliminary tested to evaluate their performance parameters and transformation (actuation) temperatures in low- temperature or cryogenic adaptive proof-of-concept systems. The challenge will be in the development, design, and training of the alloys for 2-way actuation at those temperatures.

Makalu: fast recoverable allocation of non-volatile memory

DOE PAGES

Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

2016-10-19

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

Makalu: fast recoverable allocation of non-volatile memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bhandari, Kumud; Chakrabarti, Dhruva R.; Boehm, Hans-J.

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive andmore » a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.« less

Memory feedback PID control for exponential synchronisation of chaotic Lur'e systems

NASA Astrophysics Data System (ADS)

Zhang, Ruimei; Zeng, Deqiang; Zhong, Shouming; Shi, Kaibo

2017-09-01

This paper studies the problem of exponential synchronisation of chaotic Lur'e systems (CLSs) via memory feedback proportional-integral-derivative (PID) control scheme. First, a novel augmented Lyapunov-Krasovskii functional (LKF) is constructed, which can make full use of the information on time delay and activation function. Second, improved synchronisation criteria are obtained by using new integral inequalities, which can provide much tighter bounds than what the existing integral inequalities can produce. In comparison with existing results, in which only proportional control or proportional derivative (PD) control is used, less conservative results are derived for CLSs by PID control. Third, the desired memory feedback controllers are designed in terms of the solution to linear matrix inequalities. Finally, numerical simulations of Chua's circuit and neural network are provided to show the effectiveness and advantages of the proposed results.

Performance Measurement of a Multi-Level/Analog Ferroelectric Memory Device Design

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2007-01-01

Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

Dopamine loss alters the hippocampus-nucleus accumbens synaptic transmission in the Tg2576 mouse model of Alzheimer's disease.

PubMed

Cordella, Alberto; Krashia, Paraskevi; Nobili, Annalisa; Pignataro, Annabella; La Barbera, Livia; Viscomi, Maria Teresa; Valzania, Alessandro; Keller, Flavio; Ammassari-Teule, Martine; Mercuri, Nicola Biagio; Berretta, Nicola; D'Amelio, Marcello

2018-08-01

The functional loop involving the ventral tegmental area (VTA), dorsal hippocampus and nucleus accumbens (NAc) plays a pivotal role in the formation of spatial memory and persistent memory traces. In particular, the dopaminergic innervation from the VTA to the hippocampus is critical for hippocampal-related memory function and alterations in the midbrain dopaminergic system are frequently reported in Alzheimer's disease (AD), contributing to age-related decline in memory and non-cognitive functions. However, much less is known about the hippocampus-NAc connectivity in AD. Here, we evaluated the functioning of the hippocampus-to-NAc core connectivity in the Tg2576 mouse model of AD that shows a selective and progressive degeneration of VTA dopaminergic neurons. We show that reduced dopaminergic innervation in the Tg2576 hippocampus results in reduced synaptic plasticity and excitability of dorsal subiculum pyramidal neurons. Importantly, the glutamatergic transmission from the hippocampus to the NAc core is also impaired. Chemogenetic depolarisation of Tg2576 subicular pyramidal neurons with an excitatory Designer Receptor Exclusively Activated by Designer Drugs, or systemic administration of the DA precursor levodopa, can both rescue the deficits in Tg2576 mice. Our data suggest that the dopaminergic signalling in the hippocampus is essential for the proper functioning of the hippocampus-NAc excitatory synaptic transmission. Copyright © 2018 Elsevier Inc. All rights reserved.

Design of a QoS-controlled ATM-based communications system in chorus

NASA Astrophysics Data System (ADS)

Coulson, Geoff; Campbell, Andrew; Robin, Philippe; Blair, Gordon; Papathomas, Michael; Shepherd, Doug

1995-05-01

We describe the design of an application platform able to run distributed real-time and multimedia applications alongside conventional UNIX programs. The platform is embedded in a microkernel/PC environment and supported by an ATM-based, QoS-driven communications stack. In particular, we focus on resource-management aspects of the design and deal with CPU scheduling, network resource-management and memory-management issues. An architecture is presented that guarantees QoS levels of both communications and processing with varying degrees of commitment as specified by user-level QoS parameters. The architecture uses admission tests to determine whether or not new activities can be accepted and includes modules to translate user-level QoS parameters into representations usable by the scheduling, network, and memory-management subsystems.

Spreading activation in nonverbal memory networks.

PubMed

Foster, Paul S; Wakefield, Candias; Pryjmak, Scott; Roosa, Katelyn M; Branch, Kaylei K; Drago, Valeria; Harrison, David W; Ruff, Ronald

2017-09-01

Theories of spreading activation primarily involve semantic memory networks. However, the existence of separate verbal and visuospatial memory networks suggests that spreading activation may also occur in visuospatial memory networks. The purpose of the present investigation was to explore this possibility. Specifically, this study sought to create and describe the design frequency corpus and to determine whether this measure of visuospatial spreading activation was related to right hemisphere functioning and spreading activation in verbal memory networks. We used word frequencies taken from the Controlled Oral Word Association Test and design frequencies taken from the Ruff Figural Fluency Test as measures of verbal and visuospatial spreading activation, respectively. Average word and design frequencies were then correlated with measures of left and right cerebral functioning. The results indicated that a significant relationship exists between performance on a test of right posterior functioning (Block Design) and design frequency. A significant negative relationship also exists between spreading activation in semantic memory networks and design frequency. Based on our findings, the hypotheses were supported. Further research will need to be conducted to examine whether spreading activation exists in visuospatial memory networks as well as the parameters that might modulate this spreading activation, such as the influence of neurotransmitters.

Planning Coverage Campaigns for Mission Design and Analysis: CLASP for DESDynl

NASA Technical Reports Server (NTRS)

Knight, Russell L.; McLaren, David A.; Hu, Steven

2013-01-01

Mission design and analysis presents challenges in that almost all variables are in constant flux, yet the goal is to achieve an acceptable level of performance against a concept of operations, which might also be in flux. To increase responsiveness, automated planning tools are used that allow for the continual modification of spacecraft, ground system, staffing, and concept of operations, while returning metrics that are important to mission evaluation, such as area covered, peak memory usage, and peak data throughput. This approach was applied to the DESDynl mission design using the CLASP planning system, but since this adaptation, many techniques have changed under the hood for CLASP, and the DESDynl mission concept has undergone drastic changes. The software produces mission evaluation products, such as memory highwater marks, coverage percentages, given a mission design in the form of coverage targets, concept of operations, spacecraft parameters, and orbital parameters. It tries to overcome the lack of fidelity and timeliness of mission requirements coverage analysis during mission design. Previous techniques primarily use Excel in ad hoc fashion to approximate key factors in mission performance, often falling victim to overgeneralizations necessary in such an adaptation. The new program allows designers to faithfully represent their mission designs quickly, and get more accurate results just as quickly.

Smart photodetector arrays for error control in page-oriented optical memory

NASA Astrophysics Data System (ADS)

Schaffer, Maureen Elizabeth

1998-12-01

Page-oriented optical memories (POMs) have been proposed to meet high speed, high capacity storage requirements for input/output intensive computer applications. This technology offers the capability for storage and retrieval of optical data in two-dimensional pages resulting in high throughput data rates. Since currently measured raw bit error rates for these systems fall several orders of magnitude short of industry requirements for binary data storage, powerful error control codes must be adopted. These codes must be designed to take advantage of the two-dimensional memory output. In addition, POMs require an optoelectronic interface to transfer the optical data pages to one or more electronic host systems. Conventional charge coupled device (CCD) arrays can receive optical data in parallel, but the relatively slow serial electronic output of these devices creates a system bottleneck thereby eliminating the POM advantage of high transfer rates. Also, CCD arrays are "unintelligent" interfaces in that they offer little data processing capabilities. The optical data page can be received by two-dimensional arrays of "smart" photo-detector elements that replace conventional CCD arrays. These smart photodetector arrays (SPAs) can perform fast parallel data decoding and error control, thereby providing an efficient optoelectronic interface between the memory and the electronic computer. This approach optimizes the computer memory system by combining the massive parallelism and high speed of optics with the diverse functionality, low cost, and local interconnection efficiency of electronics. In this dissertation we examine the design of smart photodetector arrays for use as the optoelectronic interface for page-oriented optical memory. We review options and technologies for SPA fabrication, develop SPA requirements, and determine SPA scalability constraints with respect to pixel complexity, electrical power dissipation, and optical power limits. Next, we examine data modulation and error correction coding for the purpose of error control in the POM system. These techniques are adapted, where possible, for 2D data and evaluated as to their suitability for a SPA implementation in terms of BER, code rate, decoder time and pixel complexity. Our analysis shows that differential data modulation combined with relatively simple block codes known as array codes provide a powerful means to achieve the desired data transfer rates while reducing error rates to industry requirements. Finally, we demonstrate the first smart photodetector array designed to perform parallel error correction on an entire page of data and satisfy the sustained data rates of page-oriented optical memories. Our implementation integrates a monolithic PN photodiode array and differential input receiver for optoelectronic signal conversion with a cluster error correction code using 0.35-mum CMOS. This approach provides high sensitivity, low electrical power dissipation, and fast parallel correction of 2 x 2-bit cluster errors in an 8 x 8 bit code block to achieve corrected output data rates scalable to 102 Gbps in the current technology increasing to 1.88 Tbps in 0.1-mum CMOS.

Caveats on psychological models of sleep and memory: a compass in an overgrown scenario.

PubMed

Conte, Francesca; Ficca, Gianluca

2013-04-01

The search for a unitary model of sleep-memory relationships seems still far from accomplished, despite the huge body of data produced in the latest twenty years. So far, inconsistent results have been mainly addressed by parcelling out memory through a continuous refinement of its classification systems, with a major focus on dichotomic distinctions such as the one concerning the declarative vs. procedural memory systems, or the implicit vs. explicit nature of learning. Although this approach has provided a remarkable contribution, it has somehow resulted in an extreme fragmentation of the scenario, where it is even more complex to get a clear picture of the way sleep and memory are connected. This article, starting from a review of the most recent literature on sleep-memory relationships, is intended to provide a compass in this frantically moving landscape. By sorting out the most promising research lines, we highlight some crucial "ongoing" theoretical developments, such as: the rediscovery of the classical notion in psychology of memory that learning has a reconstructive rather than a reproductive nature, with the need of addressing phenomena such as the delicate balance between remembering and forgetting and the integration of different items of knowledge; the growing interest in the role of additional factors influencing memory processes, such as intentionality and learning strategies; the possibility that organizational rather than structural features of sleep are essential to sleep-dependent memory consolidation. We will also discuss how these recent perspectives disclose a number of relevant methodological caveats to be carefully taken into account when conceiving experimental designs. Copyright © 2012 Elsevier Ltd. All rights reserved.

Episodic Memory Does Not Add Up: Verbatim-Gist Superposition Predicts Violations of the Additive Law of Probability

PubMed Central

Brainerd, C. J.; Wang, Zheng; Reyna, Valerie. F.; Nakamura, K.

2015-01-01

Fuzzy-trace theory’s assumptions about memory representation are cognitive examples of the familiar superposition property of physical quantum systems. When those assumptions are implemented in a formal quantum model (QEMc), they predict that episodic memory will violate the additive law of probability: If memory is tested for a partition of an item’s possible episodic states, the individual probabilities of remembering the item as belonging to each state must sum to more than 1. We detected this phenomenon using two standard designs, item false memory and source false memory. The quantum implementation of fuzzy-trace theory also predicts that violations of the additive law will vary in strength as a function of reliance on gist memory. That prediction, too, was confirmed via a series of manipulations (e.g., semantic relatedness, testing delay) that are thought to increase gist reliance. Surprisingly, an analysis of the underlying structure of violations of the additive law revealed that as a general rule, increases in remembering correct episodic states do not produce commensurate reductions in remembering incorrect states. PMID:26236091

The neural basis of visual dominance in the context of audio-visual object processing.

PubMed

Schmid, Carmen; Büchel, Christian; Rose, Michael

2011-03-01

Visual dominance refers to the observation that in bimodal environments vision often has an advantage over other senses in human. Therefore, a better memory performance for visual compared to, e.g., auditory material is assumed. However, the reason for this preferential processing and the relation to the memory formation is largely unknown. In this fMRI experiment, we manipulated cross-modal competition and attention, two factors that both modulate bimodal stimulus processing and can affect memory formation. Pictures and sounds of objects were presented simultaneously in two levels of recognisability, thus manipulating the amount of cross-modal competition. Attention was manipulated via task instruction and directed either to the visual or the auditory modality. The factorial design allowed a direct comparison of the effects between both modalities. The resulting memory performance showed that visual dominance was limited to a distinct task setting. Visual was superior to auditory object memory only when allocating attention towards the competing modality. During encoding, cross-modal competition and attention towards the opponent domain reduced fMRI signals in both neural systems, but cross-modal competition was more pronounced in the auditory system and only in auditory cortex this competition was further modulated by attention. Furthermore, neural activity reduction in auditory cortex during encoding was closely related to the behavioural auditory memory impairment. These results indicate that visual dominance emerges from a less pronounced vulnerability of the visual system against competition from the auditory domain. Copyright © 2010 Elsevier Inc. All rights reserved.

Sparse distributed memory prototype: Principles of operation

NASA Technical Reports Server (NTRS)

Flynn, Michael J.; Kanerva, Pentti; Ahanin, Bahram; Bhadkamkar, Neal; Flaherty, Paul; Hickey, Philip

1988-01-01

Sparse distributed memory is a generalized random access memory (RAM) for long binary words. Such words can be written into and read from the memory, and they can be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original right address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech and scene analysis, in signal detection and verification, and in adaptive control of automated equipment. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. The research is aimed at resolving major design issues that have to be faced in building the memories. The design of a prototype memory with 256-bit addresses and from 8K to 128K locations for 256-bit words is described. A key aspect of the design is extensive use of dynamic RAM and other standard components.

The magic words: Using computers to uncover mental associations for use in magic trick design.

PubMed

Williams, Howard; McOwan, Peter W

2017-01-01

The use of computational systems to aid in the design of magic tricks has been previously explored. Here further steps are taken in this direction, introducing the use of computer technology as a natural language data sourcing and processing tool for magic trick design purposes. Crowd sourcing of psychological concepts is investigated; further, the role of human associative memory and its exploitation in magical effects is explored. A new trick is developed and evaluated: a physical card trick partially designed by a computational system configured to search for and explore conceptual spaces readily understood by spectators.

Exploring the Role of Social Memory of Floods for Designing Flood Early Warning Operations

NASA Astrophysics Data System (ADS)

Girons Lopez, Marc; Di Baldassarre, Giuliano; Grabs, Thomas; Halldin, Sven; Seibert, Jan

2016-04-01

Early warning systems are an important tool for natural disaster mitigation practices, especially for flooding events. Warnings rely on near-future forecasts to provide time to take preventive actions before a flood occurs, thus reducing potential losses. However, on top of the technical capacities, successful warnings require an efficient coordination and communication among a range of different actors and stakeholders. The complexity of integrating the technical and social spheres of warning systems has, however, resulted in system designs neglecting a number of important aspects such as social awareness of floods thus leading to suboptimal results. A better understanding of the interactions and feedbacks among the different elements of early warning systems is therefore needed to improve their efficiency and therefore social resilience. When designing an early warning system two important decisions need to be made regarding (i) the hazard magnitude at and from which a warning should be issued and (ii) the degree of confidence required for issuing a warning. The first decision is usually taken based on the social vulnerability and climatic variability while the second one is related to the performance (i.e. accuracy) of the forecasting tools. Consequently, by estimating the vulnerability and the accuracy of the forecasts, these two variables can be optimized to minimize the costs and losses. Important parameters with a strong influence on the efficiency of warning systems such as social awareness are however not considered in their design. In this study we present a theoretical exploration of the impact of social awareness on the design of early warning systems. For this purpose we use a definition of social memory of flood events as a proxy for flood risk awareness and test its effect on the optimization of the warning system design variables. Understanding the impact of social awareness on warning system design is important to make more robust warnings that can better adapt to different social settings and more efficiently reduce vulnerability.

Optimal proximity correction: application for flash memory design

NASA Astrophysics Data System (ADS)

Chen, Y. O.; Huang, D. L.; Sung, K. T.; Chiang, J. J.; Yu, M.; Teng, F.; Chu, Lung; Rey, Juan C.; Bernard, Douglas A.; Li, Jiangwei; Li, Junling; Moroz, V.; Boksha, Victor V.

1998-06-01

Proximity Correction is the technology for which the most of IC manufacturers are committed already. The final intended result of correction is affected by many factors other than the optical characteristics of the mask-stepper system, such as photoresist exposure, post-exposure bake and development parameters, etch selectivity and anisotropy, and underlying topography. The most advanced industry and research groups already reported immediate need to consider wafer topography as one of the major components during a Proximity Correction procedure. In the present work we are discussing the corners rounding effect (which eventually cause electrical leakage) observed for the elements of Poly2 layer for a Flash Memory Design. It was found that the rounding originated by three- dimensional effects due to variation of photoresist thickness resulting from the non-planar substrate. Our major goal was to understand the reasons and correct corner rounding. As a result of this work highly effective layout correction methodology was demonstrated and manufacturable Depth Of Focus was achieved. Another purpose of the work was to demonstrate complete integration flow for a Flash Memory Design based on photolithography; deposition/etch; ion implantation/oxidation/diffusion; and device simulators.

Design and testing of shape memory alloy actuation mechanism for flapping wing micro unmanned aerial vehicles

NASA Astrophysics Data System (ADS)

Kamaruzaman, N. F.; Abdullah, E. J.

2017-12-01

Shape memory alloy (SMA) actuator offers great solution for aerospace applications with low weight being its most attractive feature. A SMA actuation mechanism for the flapping micro unmanned aerial vehicle (MAV) is proposed in this study, where SMA material is the primary system that provides the flapping motion to the wings. Based on several established design criteria, a design prototype has been fabricated to validate the design. As a proof of concept, an experiment is performed using an electrical circuit to power the SMA actuator to evaluate the flapping angle. During testing, several problems have been observed and their solutions for future development are proposed. Based on the experiment, the average recorded flapping wing angle is 14.33° for upward deflection and 12.12° for downward deflection. This meets the required design criteria and objective set forth for this design. The results prove the feasibility of employing SMA actuators in flapping wing MAV.

CLOCS (Computer with Low Context-Switching Time) Architecture Reference Documents

DTIC Science & Technology

1988-05-06

Peculiarities The only state inside the central processing unit(CPU) is a program status word. All data operations are memory to memory. One result of this... to the challenge "if I whore to design RISC, this is how I would do it." The architecture was designed by Mark Davis and Bill Gallmeister. 1.2...are memory to memory. Any special devices added should be memory mapped. The program counter is even memory mapped. 1.3.1 Working storage There is no

Designer Receptors Enhance Memory in a Mouse Model of Down Syndrome

PubMed Central

Fortress, Ashley M.; Hamlett, Eric D.; Vazey, Elena M.; Aston-Jones, Gary; Cass, Wayne A.; Boger, Heather A.

2015-01-01

Designer receptors exclusively activated by designer drugs (DREADDs) are novel and powerful tools to investigate discrete neuronal populations in the brain. We have used DREADDs to stimulate degenerating neurons in a Down syndrome (DS) model, Ts65Dn mice. Individuals with DS develop Alzheimer's disease (AD) neuropathology and have elevated risk for dementia starting in their 30s and 40s. Individuals with DS often exhibit working memory deficits coupled with degeneration of the locus coeruleus (LC) norepinephrine (NE) neurons. It is thought that LC degeneration precedes other AD-related neuronal loss, and LC noradrenergic integrity is important for executive function, working memory, and attention. Previous studies have shown that LC-enhancing drugs can slow the progression of AD pathology, including amyloid aggregation, oxidative stress, and inflammation. We have shown that LC degeneration in Ts65Dn mice leads to exaggerated memory loss and neuronal degeneration. We used a DREADD, hM3Dq, administered via adeno-associated virus into the LC under a synthetic promoter, PRSx8, to selectively stimulate LC neurons by exogenous administration of the inert DREADD ligand clozapine-N-oxide. DREADD stimulation of LC-NE enhanced performance in a novel object recognition task and reduced hyperactivity in Ts65Dn mice, without significant behavioral effects in controls. To confirm that the noradrenergic transmitter system was responsible for the enhanced memory function, the NE prodrug l-threo-dihydroxyphenylserine was administered in Ts65Dn and normosomic littermate control mice, and produced similar behavioral results. Thus, NE stimulation may prevent memory loss in Ts65Dn mice, and may hold promise for treatment in individuals with DS and dementia. PMID:25632113

Cryogenic Memories based on Spin-Singlet and Spin-Triplet Ferromagnetic Josephson Junctions

NASA Astrophysics Data System (ADS)

Gingrich, Eric

The last several decades have seen an explosion in the use and size of computers for scientific applications. The US Department of Energy has set an ExaScale computing goal for high performance computing that is projected to be unattainable by current CMOS computing designs. This has led to a renewed interest in superconducting computing as a means of beating these projections. One of the primary requirements of this thrust is the development of an efficient cryogenic memory. Estimates of power consumption of early Rapid Single Flux Quantum (RSFQ) memory designs are on the order of MW, far too steep for any real application. Therefore, other memory concepts are required. S/F/S Josephson Junctions, a class of device in which two superconductors (S) are separated by one or more ferromagnetic layers (F) has shown promise as a memory element. Several different systems have been proposed utilizing either the spin-singlet or spin-triplet superconducting states. This talk will discuss the concepts underpinning these devices, and the recent work done to demonstrate their feasibility. This research is supported in part by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via U.S. Army Research Office Contract W911NF-14-C-0115.

Serum Dioxin and Memory Among Veterans of Operation Ranch Hand

DTIC Science & Technology

2007-09-01

logical memory and visual reproductions subtests. In 1987, the WMS-R was published, expanding on the original WMS and creating a more thorough and...the Verbal Paired Associates subtest, the Logical Memory subtest (immediate and delayed recall), and the Visual Reproduction subtest (immediate and...Visual Reproduction subtest, designed to assess visual memory, the veteran was asked to draw from memory four simple geometric designs that were each

Acute effects of alcohol on the development of intrusive memories.

PubMed

Bisby, James A; Brewin, Chris R; Leitz, Julie R; Valerie Curran, H

2009-07-01

Post-traumatic stress disorder is characterised by repeated intrusive imagery of the traumatic event. Despite alcohol's impairing effect on memory and frequent involvement in real-life trauma, virtually nothing is known of the interaction between alcohol and trauma memory. We aimed to investigate the acute alcohol effects on spontaneous memories following a trauma film as well as explicit memory for the film. Utilising an independent-group double-blind design, 48 healthy volunteers were randomly allocated to receive alcohol of 0.4 or 0.8 g/kg or a matched placebo drink. A stressful film was viewed post-drink. Skin conductance was monitored throughout and mood and dissociative symptoms were indexed. Volunteers recorded their spontaneous memories of the film daily in an online diary over the following week. Their explicit memory for both gist and details of the film was tested on day 7. Intriguingly, an inverted 'U' alcohol dose-response was observed on intrusive memories with a low dose of alcohol increasing memory intrusions while a high dose decreased intrusions. In contrast, explicit memory performance after 7 days showed a linear dose-response effect of alcohol with both recall and recognition decreasing as dose increased. These findings highlight a striking differential pattern of alcohol's effects on spontaneous memories as compared with explicit memories. Alcohol's effect on spontaneous memories may reflect a dose-dependent impairment of two separate memory systems integral to the processing of different aspects of a traumatic event.

Regional information guidance system based on hypermedia concept

NASA Astrophysics Data System (ADS)

Matoba, Hiroshi; Hara, Yoshinori; Kasahara, Yutako

1990-08-01

A regional information guidance system has been developed on an image workstation. Two main features of this system are hypermedia data structure and friendly visual interface realized by the full-color frame memory system. As the hypermedia data structure manages regional information such as maps, pictures and explanations of points of interest, users can retrieve those information one by one, next to next according to their interest change. For example, users can retrieve explanation of a picture through the link between pictures and text explanations. Users can also traverse from one document to another by using keywords as cross reference indices. The second feature is to utilize a full-color, high resolution and wide space frame memory for visual interface design. This frame memory system enables real-time operation of image data and natural scene representation. The system also provides half tone representing function which enables fade-in/out presentations. This fade-in/out functions used in displaying and erasing menu and image data, makes visual interface soft for human eyes. The system we have developed is a typical example of multimedia applications. We expect the image workstation will play an important role as a platform for multimedia applications.

NASA's 3D Flight Computer for Space Applications

NASA Technical Reports Server (NTRS)

Alkalai, Leon

2000-01-01

The New Millennium Program (NMP) Integrated Product Development Team (IPDT) for Microelectronics Systems was planning to validate a newly developed 3D Flight Computer system on its first deep-space flight, DS1, launched in October 1998. This computer, developed in the 1995-97 time frame, contains many new computer technologies previously never used in deep-space systems. They include: advanced 3D packaging architecture for future low-mass and low-volume avionics systems; high-density 3D packaged chip-stacks for both volatile and non-volatile mass memory: 400 Mbytes of local DRAM memory, and 128 Mbytes of Flash memory; high-bandwidth Peripheral Component Interface (Per) local-bus with a bridge to VME; high-bandwidth (20 Mbps) fiber-optic serial bus; and other attributes, such as standard support for Design for Testability (DFT). Even though this computer system did not complete on time for delivery to the DS1 project, it was an important development along a technology roadmap towards highly integrated and highly miniaturized avionics systems for deep-space applications. This continued technology development is now being performed by NASA's Deep Space System Development Program (also known as X2000) and within JPL's Center for Integrated Space Microsystems (CISM).

Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

Ropes: Support for collective opertions among distributed threads

NASA Technical Reports Server (NTRS)

Haines, Matthew; Mehrotra, Piyush; Cronk, David

1995-01-01

Lightweight threads are becoming increasingly useful in supporting parallelism and asynchronous control structures in applications and language implementations. Recently, systems have been designed and implemented to support interprocessor communication between lightweight threads so that threads can be exploited in a distributed memory system. Their use, in this setting, has been largely restricted to supporting latency hiding techniques and functional parallelism within a single application. However, to execute data parallel codes independent of other threads in the system, collective operations and relative indexing among threads are required. This paper describes the design of ropes: a scoping mechanism for collective operations and relative indexing among threads. We present the design of ropes in the context of the Chant system, and provide performance results evaluating our initial design decisions.

DIGIMEN, optical mass memory investigations, volume 2

NASA Technical Reports Server (NTRS)

1977-01-01

The DIGIMEM phase of the Optical Mass Memory Investigation Program addressed problems related to the analysis, design, and implementation of a direct digital optical recorder/reproducer. Effort was placed on developing an operational archival mass storage system to support one or more key NASA missions. The primary activity of the DIGIMEM program phase was the design, fabrication, and test and evaluation of a breadboard digital optical recorder/reproducer. Starting with technology and subsystem perfected during the HOLOMEM program phase, a fully operational optical spot recording breadboard that met or exceeded all program goals was evaluated. A thorough evaluation of several high resolution electrophotographic recording films was performed and a preliminary data base management/end user requirements survey was completed.

Digital MOS integrated circuits

NASA Astrophysics Data System (ADS)

Elmasry, M. I.

MOS in digital circuit design is considered along with aspects of digital VLSI, taking into account a comparison of MOSFET logic circuits, 1-micrometer MOSFET VLSI technology, a generalized guide for MOSFET miniaturization, processing technologies, novel circuit structures for VLSI, and questions of circuit and system design for VLSI. MOS memory cells and circuits are discussed, giving attention to a survey of high-density dynamic RAM cell concepts, one-device cells for dynamic random-access memories, variable resistance polysilicon for high density CMOS Ram, high performance MOS EPROMs using a stacked-gate cell, and the optimization of the latching pulse for dynamic flip-flop sensors. Programmable logic arrays are considered along with digital signal processors, microprocessors, static RAMs, and dynamic RAMs.

HTMT-class Latency Tolerant Parallel Architecture for Petaflops Scale Computation

NASA Technical Reports Server (NTRS)

Sterling, Thomas; Bergman, Larry

2000-01-01

Computational Aero Sciences and other numeric intensive computation disciplines demand computing throughputs substantially greater than the Teraflops scale systems only now becoming available. The related fields of fluids, structures, thermal, combustion, and dynamic controls are among the interdisciplinary areas that in combination with sufficient resolution and advanced adaptive techniques may force performance requirements towards Petaflops. This will be especially true for compute intensive models such as Navier-Stokes are or when such system models are only part of a larger design optimization computation involving many design points. Yet recent experience with conventional MPP configurations comprising commodity processing and memory components has shown that larger scale frequently results in higher programming difficulty and lower system efficiency. While important advances in system software and algorithms techniques have had some impact on efficiency and programmability for certain classes of problems, in general it is unlikely that software alone will resolve the challenges to higher scalability. As in the past, future generations of high-end computers may require a combination of hardware architecture and system software advances to enable efficient operation at a Petaflops level. The NASA led HTMT project has engaged the talents of a broad interdisciplinary team to develop a new strategy in high-end system architecture to deliver petaflops scale computing in the 2004/5 timeframe. The Hybrid-Technology, MultiThreaded parallel computer architecture incorporates several advanced technologies in combination with an innovative dynamic adaptive scheduling mechanism to provide unprecedented performance and efficiency within practical constraints of cost, complexity, and power consumption. The emerging superconductor Rapid Single Flux Quantum electronics can operate at 100 GHz (the record is 770 GHz) and one percent of the power required by convention semiconductor logic. Wave Division Multiplexing optical communications can approach a peak per fiber bandwidth of 1 Tbps and the new Data Vortex network topology employing this technology can connect tens of thousands of ports providing a bi-section bandwidth on the order of a Petabyte per second with latencies well below 100 nanoseconds, even under heavy loads. Processor-in-Memory (PIM) technology combines logic and memory on the same chip exposing the internal bandwidth of the memory row buffers at low latency. And holographic storage photorefractive storage technologies provide high-density memory with access a thousand times faster than conventional disk technologies. Together these technologies enable a new class of shared memory system architecture with a peak performance in the range of a Petaflops but size and power requirements comparable to today's largest Teraflops scale systems. To achieve high-sustained performance, HTMT combines an advanced multithreading processor architecture with a memory-driven coarse-grained latency management strategy called "percolation", yielding high efficiency while reducing the much of the parallel programming burden. This paper will present the basic system architecture characteristics made possible through this series of advanced technologies and then give a detailed description of the new percolation approach to runtime latency management.

Ensemble coding remains accurate under object and spatial visual working memory load.

PubMed

Epstein, Michael L; Emmanouil, Tatiana A

2017-10-01

A number of studies have provided evidence that the visual system statistically summarizes large amounts of information that would exceed the limitations of attention and working memory (ensemble coding). However the necessity of working memory resources for ensemble coding has not yet been tested directly. In the current study, we used a dual task design to test the effect of object and spatial visual working memory load on size averaging accuracy. In Experiment 1, we tested participants' accuracy in comparing the mean size of two sets under various levels of object visual working memory load. Although the accuracy of average size judgments depended on the difference in mean size between the two sets, we found no effect of working memory load. In Experiment 2, we tested the same average size judgment while participants were under spatial visual working memory load, again finding no effect of load on averaging accuracy. Overall our results reveal that ensemble coding can proceed unimpeded and highly accurately under both object and spatial visual working memory load, providing further evidence that ensemble coding reflects a basic perceptual process distinct from that of individual object processing.

Robust relationship between reading span and speech recognition in noise.

PubMed

Souza, Pamela; Arehart, Kathryn

2015-01-01

Working memory refers to a cognitive system that manages information processing and temporary storage. Recent work has demonstrated that individual differences in working memory capacity measured using a reading span task are related to ability to recognize speech in noise. In this project, we investigated whether the specific implementation of the reading span task influenced the strength of the relationship between working memory capacity and speech recognition. The relationship between speech recognition and working memory capacity was examined for two different working memory tests that varied in approach, using a within-subject design. Data consisted of audiometric results along with the two different working memory tests; one speech-in-noise test; and a reading comprehension test. The test group included 94 older adults with varying hearing loss and 30 younger adults with normal hearing. Listeners with poorer working memory capacity had more difficulty understanding speech in noise after accounting for age and degree of hearing loss. That relationship did not differ significantly between the two different implementations of reading span. Our findings suggest that different implementations of a verbal reading span task do not affect the strength of the relationship between working memory capacity and speech recognition.

Hypothalamic-pituitary-adrenal axis reactivity to psychological stress and memory in middle-aged women: high responders exhibit enhanced declarative memory performance.

PubMed

Domes, G; Heinrichs, M; Reichwald, U; Hautzinger, M

2002-10-01

According to recent studies, elevated cortisol levels are associated with impaired declarative memory performance. This specific effect of cortisol has been shown in several studies using pharmacological doses of cortisol. The present study was designed to determine the effects of endogenously stimulated cortisol secretion on memory performance in healthy middle-aged women. For psychological stress challenging, we employed the Trier Social Stress Test (TSST). Subjects were assigned to either the TSST or a non-stressful control condition. Declarative and non-declarative memory performance was measured by a combined priming-free-recall-task. No significant group differences were found for memory performance. Post hoc analyses of variance indicated that regardless of experimental condition the subjects with remarkably high cortisol increase in response to the experimental procedure (high responders) showed increased memory performance in the declarative task compared to subjects with low cortisol response (low responders). The results suggest that stress-induced cortisol failed to impair memory performance. The results are discussed with respect to gender-specific effects and modulatory effects of the sympathetic nervous system and psychological variables. Copyright 2002 Elsevier Science Ltd.

MicroShell Minimalist Shell for Xilinx Microprocessors

NASA Technical Reports Server (NTRS)

Werne, Thomas A.

2011-01-01

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is discovered in a routine but the system cannot be rebooted: Shell allows a skilled operator to directly edit the binary executable in memory. With some forethought, MicroShell code can be located in a different memory location from custom code, permitting the custom functionality to be overwritten at any time without stopping the controlling shell.

Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC upgrades

NASA Astrophysics Data System (ADS)

Madorsky, A.

2017-07-01

To accommodate high-luminosity LHC operation at a 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide robust track reconstruction, the trigger system must now import all available trigger primitives generated by the Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources. To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The μ TCA architecture (adopted by CMS) was used for this design. The talk presents the details of the hardware and firmware design of the production system based on Xilinx Virtex-7 FPGA family. The next round of LHC and CMS upgrades starts in 2019, followed by a major High-Luminosity (HL) LHC upgrade starting in 2024. In the course of these upgrades, new Gas Electron Multiplier (GEM) detectors and more RPC chambers will be added to the Endcap Muon system. In order to keep up with all these changes, a new Advanced Processor unit is being designed. This device will be based on Xilinx UltraScale+ FPGAs. It will be able to accommodate up to 100 serial links with bit rates of up to 25 Gb/s, and provide up to 2.5 times more logic resources than the device used currently. The amount of PTLUT memory will be significantly increased to provide more flexibility for the Pt assignment algorithm. The talk presents preliminary details of the hardware design program.

Development of Next Generation Memory Test Experiment for Deployment on a Small Satellite

NASA Technical Reports Server (NTRS)

MacLeod, Todd; Ho, Fat D.

2012-01-01

The original Memory Test Experiment successfully flew on the FASTSAT satellite launched in November 2010. It contained a single Ramtron 512K ferroelectric memory. The memory device went through many thousands of read/write cycles and recorded any errors that were encountered. The original mission length was schedule to last 6 months but was extended to 18 months. New opportunities exist to launch a similar satellite and considerations for a new memory test experiment should be examined. The original experiment had to be designed and integrated in less than two months, so the experiment was a simple design using readily available parts. The follow-on experiment needs to be more sophisticated and encompass more technologies. This paper lays out the considerations for the design and development of this follow-on flight memory experiment. It also details the results from the original Memory Test Experiment that flew on board FASTSAT. Some of the design considerations for the new experiment include the number and type of memory devices to be used, the kinds of tests that will be performed, other data needed to analyze the results, and best use of limited resources on a small satellite. The memory technologies that are considered are FRAM, FLASH, SONOS, Resistive Memory, Phase Change Memory, Nano-wire Memory, Magneto-resistive Memory, Standard DRAM, and Standard SRAM. The kinds of tests that could be performed are read/write operations, non-volatile memory retention, write cycle endurance, power measurements, and testing Error Detection and Correction schemes. Other data that may help analyze the results are GPS location of recorded errors, time stamp of all data recorded, radiation measurements, temperature, and other activities being perform by the satellite. The resources of power, volume, mass, temperature, processing power, and telemetry bandwidth are extremely limited on a small satellite. Design considerations must be made to allow the experiment to not interfere with the satellite s primary mission.

Application of a microcomputer-based system to control and monitor bacterial growth.

PubMed

Titus, J A; Luli, G W; Dekleva, M L; Strohl, W R

1984-02-01

A modular microcomputer-based system was developed to control and monitor various modes of bacterial growth. The control system was composed of an Apple II Plus microcomputer with 64-kilobyte random-access memory; a Cyborg ISAAC model 91A multichannel analog-to-digital and digital-to-analog converter; paired MRR-1 pH, pO(2), and foam control units; and in-house-designed relay, servo control, and turbidimetry systems. To demonstrate the flexibility of the system, we grew bacteria under various computer-controlled and monitored modes of growth, including batch, turbidostat, and chemostat systems. The Apple-ISAAC system was programmed in Labsoft BASIC (extended Applesoft) with an average control program using ca. 6 to 8 kilobytes of memory and up to 30 kilobytes for datum arrays. This modular microcomputer-based control system was easily coupled to laboratory scale fermentors for a variety of fermentations.

Application of a Microcomputer-Based System to Control and Monitor Bacterial Growth

PubMed Central

Titus, Jeffrey A.; Luli, Gregory W.; Dekleva, Michael L.; Strohl, William R.

1984-01-01

A modular microcomputer-based system was developed to control and monitor various modes of bacterial growth. The control system was composed of an Apple II Plus microcomputer with 64-kilobyte random-access memory; a Cyborg ISAAC model 91A multichannel analog-to-digital and digital-to-analog converter; paired MRR-1 pH, pO2, and foam control units; and in-house-designed relay, servo control, and turbidimetry systems. To demonstrate the flexibility of the system, we grew bacteria under various computer-controlled and monitored modes of growth, including batch, turbidostat, and chemostat systems. The Apple-ISAAC system was programmed in Labsoft BASIC (extended Applesoft) with an average control program using ca. 6 to 8 kilobytes of memory and up to 30 kilobytes for datum arrays. This modular microcomputer-based control system was easily coupled to laboratory scale fermentors for a variety of fermentations. PMID:16346462

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

NASA Astrophysics Data System (ADS)

He, Huimin; Liu, Fengman; Li, Baoxia; Xue, Haiyun; Wang, Haidong; Qiu, Delong; Zhou, Yunyan; Cao, Liqiang

2016-11-01

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth-distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

Concurrent Image Processing Executive (CIPE). Volume 1: Design overview

NASA Technical Reports Server (NTRS)

Lee, Meemong; Groom, Steven L.; Mazer, Alan S.; Williams, Winifred I.

1990-01-01

The design and implementation of a Concurrent Image Processing Executive (CIPE), which is intended to become the support system software for a prototype high performance science analysis workstation are described. The target machine for this software is a JPL/Caltech Mark 3fp Hypercube hosted by either a MASSCOMP 5600 or a Sun-3, Sun-4 workstation; however, the design will accommodate other concurrent machines of similar architecture, i.e., local memory, multiple-instruction-multiple-data (MIMD) machines. The CIPE system provides both a multimode user interface and an applications programmer interface, and has been designed around four loosely coupled modules: user interface, host-resident executive, hypercube-resident executive, and application functions. The loose coupling between modules allows modification of a particular module without significantly affecting the other modules in the system. In order to enhance hypercube memory utilization and to allow expansion of image processing capabilities, a specialized program management method, incremental loading, was devised. To minimize data transfer between host and hypercube, a data management method which distributes, redistributes, and tracks data set information was implemented. The data management also allows data sharing among application programs. The CIPE software architecture provides a flexible environment for scientific analysis of complex remote sensing image data, such as planetary data and imaging spectrometry, utilizing state-of-the-art concurrent computation capabilities.

Soft error rate simulation and initial design considerations of neutron intercepting silicon chip (NISC)

NASA Astrophysics Data System (ADS)

Celik, Cihangir

Advances in microelectronics result in sub-micrometer electronic technologies as predicted by Moore's Law, 1965, which states the number of transistors in a given space would double every two years. The most available memory architectures today have submicrometer transistor dimensions. The International Technology Roadmap for Semiconductors (ITRS), a continuation of Moore's Law, predicts that Dynamic Random Access Memory (DRAM) will have an average half pitch size of 50 nm and Microprocessor Units (MPU) will have an average gate length of 30 nm over the period of 2008-2012. Decreases in the dimensions satisfy the producer and consumer requirements of low power consumption, more data storage for a given space, faster clock speed, and portability of integrated circuits (IC), particularly memories. On the other hand, these properties also lead to a higher susceptibility of IC designs to temperature, magnetic interference, power supply, and environmental noise, and radiation. Radiation can directly or indirectly affect device operation. When a single energetic particle strikes a sensitive node in the micro-electronic device, it can cause a permanent or transient malfunction in the device. This behavior is called a Single Event Effect (SEE). SEEs are mostly transient errors that generate an electric pulse which alters the state of a logic node in the memory device without having a permanent effect on the functionality of the device. This is called a Single Event Upset (SEU) or Soft Error . Contrary to SEU, Single Event Latchup (SEL), Single Event Gate Rapture (SEGR), or Single Event Burnout (SEB) they have permanent effects on the device operation and a system reset or recovery is needed to return to proper operations. The rate at which a device or system encounters soft errors is defined as Soft Error Rate (SER). The semiconductor industry has been struggling with SEEs and is taking necessary measures in order to continue to improve system designs in nano-scale technologies. Prevention of SEEs has been studied and applied in the semiconductor industry by including radiation protection precautions in the system architecture or by using corrective algorithms in the system operation. Decreasing 10B content (20%of natural boron) in the natural boron of Borophosphosilicate glass (BPSG) layers that are conventionally used in the fabrication of semiconductor devices was one of the major radiation protection approaches for the system architecture. Neutron interaction in the BPSG layer was the origin of the SEEs because of the 10B (n,alpha) 7Li reaction products. Both of the particles produced have the capability of ionization in the silicon substrate region, whose thickness is comparable to the ranges of these particles. Using the soft error phenomenon in exactly the opposite manner of the semiconductor industry can provide a new neutron detection system based on the SERs in the semiconductor memories. By investigating the soft error mechanisms in the available semiconductor memories and enhancing the soft error occurrences in these devices, one can convert all memory using intelligent systems into portable, power efficient, directiondependent neutron detectors. The Neutron Intercepting Silicon Chip (NISC) project aims to achieve this goal by introducing 10B-enriched BPSG layers to the semiconductor memory architectures. This research addresses the development of a simulation tool, the NISC Soft Error Analysis Tool (NISCSAT), for soft error modeling and analysis in the semiconductor memories to provide basic design considerations for the NISC. NISCSAT performs particle transport and calculates the soft error probabilities, or SER, depending on energy depositions of the particles in a given memory node model of the NISC. Soft error measurements were performed with commercially available, off-the-shelf semiconductor memories and microprocessors to observe soft error variations with the neutron flux and memory supply voltage. Measurement results show that soft errors in the memories increase proportionally with the neutron flux, whereas they decrease with increasing the supply voltages. NISC design considerations include the effects of device scaling, 10B content in the BPSG layer, incoming neutron energy, and critical charge of the node for this dissertation. NISCSAT simulations were performed with various memory node models to account these effects. Device scaling simulations showed that any further increase in the thickness of the BPSG layer beyond 2 mum causes self-shielding of the incoming neutrons due to the BPSG layer and results in lower detection efficiencies. Moreover, if the BPSG layer is located more than 4 mum apart from the depletion region in the node, there are no soft errors in the node due to the fact that both of the reaction products have lower ranges in the silicon or any possible node layers. Calculation results regarding the critical charge indicated that the mean charge deposition of the reaction products in the sensitive volume of the node is about 15 fC. It is evident that the NISC design should have a memory architecture with a critical charge of 15 fC or less to obtain higher detection efficiencies. Moreover, the sensitive volume should be placed in close proximity to the BPSG layers so that its location would be within the range of alpha and 7Li particles. Results showed that the distance between the BPSG layer and the sensitive volume should be less than 2 mum to increase the detection efficiency of the NISC. Incoming neutron energy was also investigated by simulations and the results obtained from these simulations showed that NISC neutron detection efficiency is related with the neutron cross-sections of 10B (n,alpha) 7Li reaction, e.g., ratio of the thermal (0.0253 eV) to fast (2 MeV) neutron detection efficiencies is approximately equal to 8000:1. Environmental conditions and their effects on the NISC performance were also studied in this research. Cosmic rays were modeled and simulated via NISCSAT to investigate detection reliability of the NISC. Simulation results show that cosmic rays account for less than 2 % of the soft errors for the thermal neutron detection. On the other hand, fast neutron detection by the NISC, which already has a poor efficiency due to the low neutron cross-sections, becomes almost impossible at higher altitudes where the cosmic ray fluxes and their energies are higher. NISCSAT simulations regarding soft error dependency of the NISC for temperature and electromagnetic fields show that there are no significant effects in the NISC detection efficiency. Furthermore, the detection efficiency of the NISC decreases with both air humidity and use of moderators since the incoming neutrons scatter away before reaching the memory surface.

TMS communications hardware. Volume 1: Computer interfaces

NASA Technical Reports Server (NTRS)

Brown, J. S.; Weinrich, S. S.

1979-01-01

A prototpye coaxial cable bus communications system was designed to be used in the Trend Monitoring System (TMS) to connect intelligent graphics terminals (based around a Data General NOVA/3 computer) to a MODCOMP IV host minicomputer. The direct memory access (DMA) interfaces which were utilized for each of these computers are identified. It is shown that for the MODCOMP, an off-the-shell board was suitable, while for the NOVAs, custon interface circuitry was designed and implemented.

Operating Systems for Wireless Sensor Networks: A Survey

PubMed Central

Farooq, Muhammad Omer; Kunz, Thomas

2011-01-01

This paper presents a survey on the current state-of-the-art in Wireless Sensor Network (WSN) Operating Systems (OSs). In recent years, WSNs have received tremendous attention in the research community, with applications in battlefields, industrial process monitoring, home automation, and environmental monitoring, to name but a few. A WSN is a highly dynamic network because nodes die due to severe environmental conditions and battery power depletion. Furthermore, a WSN is composed of miniaturized motes equipped with scarce resources e.g., limited memory and computational abilities. WSNs invariably operate in an unattended mode and in many scenarios it is impossible to replace sensor motes after deployment, therefore a fundamental objective is to optimize the sensor motes’ life time. These characteristics of WSNs impose additional challenges on OS design for WSN, and consequently, OS design for WSN deviates from traditional OS design. The purpose of this survey is to highlight major concerns pertaining to OS design in WSNs and to point out strengths and weaknesses of contemporary OSs for WSNs, keeping in mind the requirements of emerging WSN applications. The state-of-the-art in operating systems for WSNs has been examined in terms of the OS Architecture, Programming Model, Scheduling, Memory Management and Protection, Communication Protocols, Resource Sharing, Support for Real-Time Applications, and additional features. These features are surveyed for both real-time and non-real-time WSN operating systems. PMID:22163934

Operating systems for wireless sensor networks: a survey.

PubMed

Farooq, Muhammad Omer; Kunz, Thomas

2011-01-01

This paper presents a survey on the current state-of-the-art in Wireless Sensor Network (WSN) Operating Systems (OSs). In recent years, WSNs have received tremendous attention in the research community, with applications in battlefields, industrial process monitoring, home automation, and environmental monitoring, to name but a few. A WSN is a highly dynamic network because nodes die due to severe environmental conditions and battery power depletion. Furthermore, a WSN is composed of miniaturized motes equipped with scarce resources e.g., limited memory and computational abilities. WSNs invariably operate in an unattended mode and in many scenarios it is impossible to replace sensor motes after deployment, therefore a fundamental objective is to optimize the sensor motes' life time. These characteristics of WSNs impose additional challenges on OS design for WSN, and consequently, OS design for WSN deviates from traditional OS design. The purpose of this survey is to highlight major concerns pertaining to OS design in WSNs and to point out strengths and weaknesses of contemporary OSs for WSNs, keeping in mind the requirements of emerging WSN applications. The state-of-the-art in operating systems for WSNs has been examined in terms of the OS Architecture, Programming Model, Scheduling, Memory Management and Protection, Communication Protocols, Resource Sharing, Support for Real-Time Applications, and additional features. These features are surveyed for both real-time and non-real-time WSN operating systems.

Quantifying precision and availability of location memory in everyday pictures and some implications for picture database design.

PubMed

Lansdale, Mark W; Oliff, Lynda; Baguley, Thom S

2005-06-01

The authors investigated whether memory for object locations in pictures could be exploited to address known difficulties of designing query languages for picture databases. M. W. Lansdale's (1998) model of location memory was adapted to 4 experiments observing memory for everyday pictures. These experiments showed that location memory is quantified by 2 parameters: a probability that memory is available and a measure of its precision. Availability is determined by controlled attentional processes, whereas precision is mostly governed by picture composition beyond the viewer's control. Additionally, participants' confidence judgments were good predictors of availability but were insensitive to precision. This research suggests that databases using location memory are feasible. The implications of these findings for database design and for further research and development are discussed. (c) 2005 APA

System and method for memory allocation in a multiclass memory system

DOEpatents

Loh, Gabriel; Meswani, Mitesh; Ignatowski, Michael; Nutter, Mark

2016-06-28

A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.

MUSIC - Multifunctional stereo imaging camera system for wide angle and high resolution stereo and color observations on the Mars-94 mission

NASA Astrophysics Data System (ADS)

Oertel, D.; Jahn, H.; Sandau, R.; Walter, I.; Driescher, H.

1990-10-01

Objectives of the multifunctional stereo imaging camera (MUSIC) system to be deployed on the Soviet Mars-94 mission are outlined. A high-resolution stereo camera (HRSC) and wide-angle opto-electronic stereo scanner (WAOSS) are combined in terms of hardware, software, technology aspects, and solutions. Both HRSC and WAOSS are push-button instruments containing a single optical system and focal plates with several parallel CCD line sensors. Emphasis is placed on the MUSIC system's stereo capability, its design, mass memory, and data compression. A 1-Gbit memory is divided into two parts: 80 percent for HRSC and 20 percent for WAOSS, while the selected on-line compression strategy is based on macropixel coding and real-time transform coding.

Generic, Type-Safe and Object Oriented Computer Algebra Software

NASA Astrophysics Data System (ADS)

Kredel, Heinz; Jolly, Raphael

Advances in computer science, in particular object oriented programming, and software engineering have had little practical impact on computer algebra systems in the last 30 years. The software design of existing systems is still dominated by ad-hoc memory management, weakly typed algorithm libraries and proprietary domain specific interactive expression interpreters. We discuss a modular approach to computer algebra software: usage of state-of-the-art memory management and run-time systems (e.g. JVM) usage of strongly typed, generic, object oriented programming languages (e.g. Java) and usage of general purpose, dynamic interactive expression interpreters (e.g. Python) To illustrate the workability of this approach, we have implemented and studied computer algebra systems in Java and Scala. In this paper we report on the current state of this work by presenting new examples.

Early detection of memory impairment in people over 65 years old consulting at Health Examination Centers for the French health insurance: the EVATEM protocol

PubMed Central

2013-01-01

Background Only half of those living with Alzheimer’s disease in France are currently diagnosed, and only one patient in three is supported during the early stages of dementia. This study aims to evaluate three cognitive tests for their predictive ability to diagnose mild cognitive impairments and Alzheimer’s disease and related disorders. For people aged 65 years or over, presenting with a memory complaint, these tests can be performed easily during a preventative consultation. Method/design The EVATEM (évaluation des troubles de l’équilibre et de la mémoire (evaluation of balance and memory problems)) cohort study was designed to prospectively assess the predictive value of tests for the diagnosis of mild cognitive impairments and Alzheimer’s disease in elderly subjects aged 65 years or over. Subjects were recruited from three health examination centers that are part of the French health insurance system. If a memory complaint was identified (using a dedicated questionnaire), the five-word test, the cognitive disorders examination test and the verbal fluency test were administered during a preventative consultation. A memory consultation was performed at a University Hospital to diagnosis any potential cognitive disorder and a one-year follow-up consultation was also scheduled. We recorded 2041 cases of memory complaint at our Health Examination Centers. Cognitive tests were refused by 33.6% of people who had a memory complaint. The number of subjects sent to a University Hospital memory consultation was 832 and 74.5% of them completed this consultation. The study population therefore includes 620 subjects. Discussion Tests for the early diagnosis of a mild cognitive impairment or Alzheimer’s disease and related disorders should be used in centers dedicated to disease prevention. These should guide subjects with memory impairment to full memory consultations at hospitals and improve the access to early medical and behavioral support. Trial registration ClinicalTrials.gov:NCT01316562 PMID:23742705

Aerothermodynamic Design Sensitivities for a Reacting Gas Flow Solver on an Unstructured Mesh Using a Discrete Adjoint Formulation

NASA Astrophysics Data System (ADS)

Thompson, Kyle Bonner

An algorithm is described to efficiently compute aerothermodynamic design sensitivities using a decoupled variable set. In a conventional approach to computing design sensitivities for reacting flows, the species continuity equations are fully coupled to the conservation laws for momentum and energy. In this algorithm, the species continuity equations are solved separately from the mixture continuity, momentum, and total energy equations. This decoupling simplifies the implicit system, so that the flow solver can be made significantly more efficient, with very little penalty on overall scheme robustness. Most importantly, the computational cost of the point implicit relaxation is shown to scale linearly with the number of species for the decoupled system, whereas the fully coupled approach scales quadratically. Also, the decoupled method significantly reduces the cost in wall time and memory in comparison to the fully coupled approach. This decoupled approach for computing design sensitivities with the adjoint system is demonstrated for inviscid flow in chemical non-equilibrium around a re-entry vehicle with a retro-firing annular nozzle. The sensitivities of the surface temperature and mass flow rate through the nozzle plenum are computed with respect to plenum conditions and verified against sensitivities computed using a complex-variable finite-difference approach. The decoupled scheme significantly reduces the computational time and memory required to complete the optimization, making this an attractive method for high-fidelity design of hypersonic vehicles.

Electronics Shielding and Reliability Design Tools

NASA Technical Reports Server (NTRS)

Wilson, John W.; ONeill, P. M.; Zang, Thomas A., Jr.; Pandolf, John E.; Koontz, Steven L.; Boeder, P.; Reddell, B.; Pankop, C.

2006-01-01

It is well known that electronics placement in large-scale human-rated systems provides opportunity to optimize electronics shielding through materials choice and geometric arrangement. For example, several hundred single event upsets (SEUs) occur within the Shuttle avionic computers during a typical mission. An order of magnitude larger SEU rate would occur without careful placement in the Shuttle design. These results used basic physics models (linear energy transfer (LET), track structure, Auger recombination) combined with limited SEU cross section measurements allowing accurate evaluation of target fragment contributions to Shuttle avionics memory upsets. Electronics shielding design on human-rated systems provides opportunity to minimize radiation impact on critical and non-critical electronic systems. Implementation of shielding design tools requires adequate methods for evaluation of design layouts, guiding qualification testing, and an adequate follow-up on final design evaluation including results from a systems/device testing program tailored to meet design requirements.

Structurally Integrated Versus Structurally Segregated Memory Representations: Implications for the Design of Instructional Materials.

ERIC Educational Resources Information Center

Hayes-Roth, Barbara

Two kinds of memory organization are distinguished: segregrated versus integrated. In segregated memory organizations, related learned propositions have separate memory representations. In integrated memory organizations, memory representations of related propositions share common subrepresentations. Segregated memory organizations facilitate…

Apparatus and Method for Low-Temperature Training of Shape Memory Alloys

NASA Technical Reports Server (NTRS)

Swanger, A. M.; Fesmire, J. E.; Trigwell, S.; Gibson, T. L.; Williams, M. K.; Benafan, O.

2015-01-01

An apparatus and method for the low-temperature thermo-mechanical training of shape memory alloys (SMA) has been developed. The experimental SMA materials are being evaluated as prototypes for applicability in novel thermal management systems for future cryogenic applications. Alloys providing two-way actuation at cryogenic temperatures are the chief target. The mechanical training regimen was focused on the controlled movement of rectangular strips, with S-bend configurations, at temperatures as low as 30 K. The custom holding fixture included temperature sensors and a low heat-leak linear actuator with a magnetic coupling. The fixture was mounted to a Gifford-McMahon cryocooler providing up to 25 W of cooling power at 20 K and housed within a custom vacuum chamber. Operations included both training cycles and verification of shape memory movement. The system design and operation are discussed. Results of the training for select prototype alloys are presented.

A Design of Finite Memory Residual Generation Filter for Sensor Fault Detection

NASA Astrophysics Data System (ADS)

Kim, Pyung Soo

2017-04-01

In the current paper, a residual generation filter with finite memory structure is proposed for sensor fault detection. The proposed finite memory residual generation filter provides the residual by real-time filtering of fault vector using only the most recent finite measurements and inputs on the window. It is shown that the residual given by the proposed residual generation filter provides the exact fault for noisefree systems. The proposed residual generation filter is specified to the digital filter structure for the amenability to hardware implementation. Finally, to illustrate the capability of the proposed residual generation filter, extensive simulations are performed for the discretized DC motor system with two types of sensor faults, incipient soft bias-type fault and abrupt bias-type fault. In particular, according to diverse noise levels and windows lengths, meaningful simulation results are given for the abrupt bias-type fault.

Apparatus and method for low-temperature training of shape memory alloys

NASA Astrophysics Data System (ADS)

Swanger, A. M.; Fesmire, J. E.; Trigwell, S.; Gibson, T. L.; Williams, M. K.; Benafan, O.

2015-12-01

An apparatus and method for the low-temperature thermo-mechanical training of shape memory alloys (SMA) has been developed. The experimental SMA materials are being evaluated as prototypes for applicability in novel thermal management systems for future cryogenic applications. Alloys providing two-way actuation at cryogenic temperatures are the chief target. The mechanical training regimen was focused on the controlled movement of rectangular strips, with S-bend configurations, at temperatures as low as 30 K. The custom holding fixture included temperature sensors and a low heat-leak linear actuator with a magnetic coupling. The fixture was mounted to a Gifford-McMahon cryocooler providing up to 25 W of cooling power at 20 K and housed within a custom vacuum chamber. Operations included both training cycles and verification of shape memory movement. The system design and operation are discussed. Results of the training for select prototype alloys are presented.

Self-Repairing Fatigue Damage in Metallic Structures for Aerospace Vehicles Using Shape Memory Alloy Self-healing (SMASH) Technology

NASA Technical Reports Server (NTRS)

Wright, M. Clara; Manuel, Michele; Wallace, Terryl; Newman, Andy; Brinson, Kate

2015-01-01

This DAA is for the Phase II webinar presentation of the ARMD-funded SMASH technology. A self-repairing aluminum-based composite system has been developed using liquid-assisted healing theory in conjunction with the shape memory effect of wire reinforcements. The metal matrix composite was thermodynamically designed to have a matrix with a relatively even dispersion of low-melting phase, allowing for repair of cracks at a pre-determined temperature. Shape memory alloy wire reinforcements were used within the composite to provide crack closure. Investigators focused the research on fatigue cracks propagating through the matrix in order to optimize and computer model the SMASH technology for aeronautical applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Lingda; Hayes, Ari; Song, Shuaiwen

Modern GPUs employ cache to improve memory system efficiency. However, large amount of cache space is underutilized due to irregular memory accesses and poor spatial locality which exhibited commonly in GPU applications. Our experiments show that using smaller cache lines could improve cache space utilization, but it also frequently suffers from significant performance loss by introducing large amount of extra cache requests. In this work, we propose a novel cache design named tag-split cache (TSC) that enables fine-grained cache storage to address the problem of cache space underutilization while keeping memory request number unchanged. TSC divides tag into two partsmore » to reduce storage overhead, and it supports multiple cache line replacement in one cycle.« less

Non-Volatile Memory Technology Symposium 2000: Proceedings

NASA Technical Reports Server (NTRS)

Aranki, Nazeeh (Editor)

2000-01-01

This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.

The role of GABAA in the expression of updated information through the reconsolidation process in humans.

PubMed

Fernández, Rodrigo S; Moyano, Malen D; Radloff, Michael; Campos, Jorge; Carbó-Tano, Martin; Allegri, Ricardo F; Pedreira, María E; Forcato, Cecilia

2017-07-01

Consolidated memory can be again destabilized by the presentation of a memory cue (reminder) of the previously acquired information. During this process of labilization/restabilization memory traces can be either impaired, strengthened or updated in content. Here, we study if a consolidated memory can be updated by linking one original cue to two different outcomes and whether this process was modulated by the GABAergic system. To aim that, we designed two experiments carried out in three consecutive days. All participants learned a list of non-sense syllable pairs on day 1. On day 2 the new information was introduced after the reminder or no-reminder presentation. Participants were tested on day 3 for the updated or original list (Exp. 1). In Exp. 2 we tested whether this new information was incorporated by an inhibitory process mediated by the GABAergic system. For that, participants retrieved the original information before being taken Clonazepam 0.25mg (GABA A agonist) or Placebo pill. We found that the groups that received the reminder correctly recalled the old and new information. However, the no reminder groups only correctly recalled the original information. Furthermore, when testing occurred in the presence of Clonazepam, the group that received the reminder plus the new information showed an impaired original memory performance compared to the group that received only Clonazepam (without reminder) or the reminder plus Placebo pill. These results show that new information can be added to a reactivated declarative memory in humans by linking one cue to two different outcomes. Furthermore, we shed light on the mechanisms of memory updating being the GABAergic system involved in the modulation of the old and new information expression. Copyright © 2017 Elsevier Inc. All rights reserved.

Sparse distributed memory: Principles and operation

NASA Technical Reports Server (NTRS)

Flynn, M. J.; Kanerva, P.; Bhadkamkar, N.

1989-01-01

Sparse distributed memory is a generalized random access memory (RAM) for long (1000 bit) binary words. Such words can be written into and read from the memory, and they can also be used to address the memory. The main attribute of the memory is sensitivity to similarity, meaning that a word can be read back not only by giving the original write address but also by giving one close to it as measured by the Hamming distance between addresses. Large memories of this kind are expected to have wide use in speech recognition and scene analysis, in signal detection and verification, and in adaptive control of automated equipment, in general, in dealing with real world information in real time. The memory can be realized as a simple, massively parallel computer. Digital technology has reached a point where building large memories is becoming practical. Major design issues were resolved which were faced in building the memories. The design is described of a prototype memory with 256 bit addresses and from 8 to 128 K locations for 256 bit words. A key aspect of the design is extensive use of dynamic RAM and other standard components.

Modular data acquisition system and its use in gas-filled detector readout at ESRF

NASA Astrophysics Data System (ADS)

Sever, F.; Epaud, F.; Poncet, F.; Grave, M.; Rey-Bakaikoa, V.

1996-09-01

Since 1992, 18 ESRF beamlines are open to users. Although the data acquisition requirements vary a lot from one beamline to another, we are trying to implement a modular data acquisition system architecture that would fit with the maximum number of acquisition projects at ESRF. Common to all of these systems are large acquisition memories and the requirement to visualize the data during an acquisition run and to transfer them quickly after the run to safe storage. We developed a general memory API handling the acquisition memory and its organization and another library that provides calls for transferring the data over TCP/IP sockets. Interesting utility programs using these libraries are the `online display' program and the `data transfer' program. The data transfer program as well as an acquisition control program rely on our well-established `device server model', which was originally designed for the machine control system and then successfully reused in beamline control systems. In the second half of this paper, the acquisition system for a 2D gas-filled detector is presented, which is one of the first concrete examples using the proposed modular data acquisition architecture.

Coordinated design of coding and modulation systems

NASA Technical Reports Server (NTRS)

Massey, J. L.

1976-01-01

Work on partial unit memory codes continued; it was shown that for a given virtual state complexity, the maximum free distance over the class of all convolutional codes is achieved within the class of unit memory codes. The effect of phase-lock loop (PLL) tracking error on coding system performance was studied by using the channel cut-off rate as the measure of quality of a modulation system. Optimum modulation signal sets for a non-white Gaussian channel considered an heuristic selection rule based on a water-filling argument. The use of error correcting codes to perform data compression by the technique of syndrome source coding was researched and a weight-and-error-locations scheme was developed that is closely related to LDSC coding.

Evaluation of a multifunctional technology system in a memory care unit: Opportunities for innovation in dementia care.

PubMed

Lazar, Amanda; Demiris, George; Thompson, Hilaire J

2016-12-01

Stimulating recreational and leisure activities (RLAs) are essential to physical and mental well-being; however, people living in memory care units (MCUs) may lack access to them. Technology has the potential to facilitate and enrich activity engagement in this context. In this 6-month study, we evaluated a commercially available system designed to encourage the engagement of people with dementia in activities and social interactions, using a mixed-methods approach in a MCU. Quantitative measures included those to evaluate cognition, depression, quality of life, and resource utilization. We qualitatively evaluated the system using semi-structured interviews with family members and staff. Five residents with dementia, four family members, and seven staff were included in the 6-month study. Staff and family members reported benefits for residents such as enjoyment, interactions and connections with others, and mental stimulation. Findings also highlight challenges such as technical and ethical concerns. Factors that influence system use and integration are also discussed. It was feasible to introduce a system designed for recreation and engagement in a MCU, and staff, family members, and residents experienced benefits. However, barriers existed in the introduction and use of the system.

Evaluation of a multifunctional technology system in a memory care unit: Opportunities for innovation in dementia care

PubMed Central

Lazar, Amanda; Demiris, George; Thompson, Hilaire J.

2016-01-01

Introduction Stimulating recreational and leisure activities (RLAs) are essential to physical and mental well-being; however, people living in memory care units (MCUs) may lack access to them. Technology has the potential to facilitate and enrich activity engagement in this context. Objectives In this 6-month study, we evaluated a commercially available system designed to encourage the engagement of people with dementia in activities and social interactions, using a mixed-methods approach in a MCU. Methods Quantitative measures included those to evaluate cognition, depression, quality of life, and resource utilization. We qualitatively evaluated the system using semi-structured interviews with family members and staff. Five residents with dementia, four family members, and seven staff were included in the 6-month study. Results Staff and family members reported benefits for residents such as enjoyment, interactions and connections with others, and mental stimulation. Findings also highlight challenges such as technical and ethical concerns. Factors that influence system use and integration are also discussed. Conclusion It was feasible to introduce a system designed for recreation and engagement in a MCU, and staff, family members, and residents experienced benefits. However, barriers existed in the introduction and use of the system. PMID:26819070

Cricket: A Mapped, Persistent Object Store

NASA Technical Reports Server (NTRS)

Shekita, Eugene; Zwilling, Michael

1996-01-01

This paper describes Cricket, a new database storage system that is intended to be used as a platform for design environments and persistent programming languages. Cricket uses the memory management primitives of the Mach operating system to provide the abstraction of a shared, transactional single-level store that can be directly accessed by user applications. In this paper, we present the design and motivation for Cricket. We also present some initial performance results which show that, for its intended applications, Cricket can provide better performance than a general-purpose database storage system.

Research in software allocation for advanced manned mission communications and tracking systems

NASA Technical Reports Server (NTRS)

Warnagiris, Tom; Wolff, Bill; Kusmanoff, Antone

1990-01-01

An assessment of the planned processing hardware and software/firmware for the Communications and Tracking System of the Space Station Freedom (SSF) was performed. The intent of the assessment was to determine the optimum distribution of software/firmware in the processing hardware for maximum throughput with minimum required memory. As a product of the assessment process an assessment methodology was to be developed that could be used for similar assessments of future manned spacecraft system designs. The assessment process was hampered by changing requirements for the Space Station. As a result, the initial objective of determining the optimum software/firmware allocation was not fulfilled, but several useful conclusions and recommendations resulted from the assessment. It was concluded that the assessment process would not be completely successful for a system with changing requirements. It was also concluded that memory requirements and hardware requirements were being modified to fit as a consequence of the change process, and although throughput could not be quantitized, potential problem areas could be identified. Finally, inherent flexibility of the system design was essential for the success of a system design with changing requirements. Recommendations resulting from the assessment included development of common software for some embedded controller functions, reduction of embedded processor requirements by hardwiring some Orbital Replacement Units (ORUs) to make better use of processor capabilities, and improvement in communications between software development personnel to enhance the integration process. Lastly, a critical observation was made regarding the software integration tasks did not appear to be addressed in the design process to the degree necessary for successful satisfaction of the system requirements.

Long-term antibody memory induced by synthetic peptide vaccination is protective against Streptococcus pyogenes infection and is independent of memory T-cell help

PubMed Central

Pandey, Manisha; Wykes, Michelle N; Hartas, Jon; Good, Michael F; Batzloff, Michael R

2013-01-01

Streptococcus pyogenes (group A streptococcus; GAS) is a leading human pathogen associated with a diverse array of mucosal and systemic infections. Vaccination with J8, a conserved region synthetic peptide derived from the M-protein of GAS and containing only 12 amino acids from GAS, when conjugated to DT, has been shown to protect mice against a lethal GAS challenge. Protection has been previously shown to be antibody-mediated. J8 does not contain a dominant GAS-specific T-cell epitope. The current study examined long-term antibody memory and dissected the role of B and T-cells. Our results demonstrated that vaccination generates specific memory B-cells and long-lasting antibody responses. The memory B-cell response can be activated following boost with antigen or limiting numbers of whole bacteria. We further show that these memory responses protect against systemic infection with GAS. T-cell help is required for activation of memory B-cells but can be provided by naïve T-cells responding directly to GAS at the time of infection. Thus, individuals whose T-cells do not recognize the short synthetic peptide in the vaccine will be able to generate a protective and rapid memory antibody response at the time of infection. These studies significantly strengthen previous findings, which showed that protection by the J8-DT vaccine is antibody-mediated and suggest that in vaccine design for other organisms the source of T-cell help for antibody responses need not be limited to sequences from the organism itself. PMID:23401589

Initial Performance Results on IBM POWER6

NASA Technical Reports Server (NTRS)

Saini, Subbash; Talcott, Dale; Jespersen, Dennis; Djomehri, Jahed; Jin, Haoqiang; Mehrotra, Piysuh

2008-01-01

The POWER5+ processor has a faster memory bus than that of the previous generation POWER5 processor (533 MHz vs. 400 MHz), but the measured per-core memory bandwidth of the latter is better than that of the former (5.7 GB/s vs. 4.3 GB/s). The reason for this is that in the POWER5+, the two cores on the chip share the L2 cache, L3 cache and memory bus. The memory controller is also on the chip and is shared by the two cores. This serializes the path to memory. For consistently good performance on a wide range of applications, the performance of the processor, the memory subsystem, and the interconnects (both latency and bandwidth) should be balanced. Recognizing this, IBM has designed the Power6 processor so as to avoid the bottlenecks due to the L2 cache, memory controller and buffer chips of the POWER5+. Unlike the POWER5+, each core in the POWER6 has its own L2 cache (4 MB - double that of the Power5+), memory controller and buffer chips. Each core in the POWER6 runs at 4.7 GHz instead of 1.9 GHz in POWER5+. In this paper, we evaluate the performance of a dual-core Power6 based IBM p6-570 system, and we compare its performance with that of a dual-core Power5+ based IBM p575+ system. In this evaluation, we have used the High- Performance Computing Challenge (HPCC) benchmarks, NAS Parallel Benchmarks (NPB), and four real-world applications--three from computational fluid dynamics and one from climate modeling.

Activation of endocannabinoid system in the rat basolateral amygdala improved scopolamine-induced memory consolidation impairment.

PubMed

Nedaei, Seyed Ershad; Rezayof, Ameneh; Pourmotabbed, Ali; Nasehi, Mohammad; Zarrindast, Mohammad-Reza

2016-09-15

The current study was designed to examine the involvement of cannabinoid CB1 receptors in the basolateral amygdala (BLA) in scopolamine-induced memory impairment in adult male Wistar rats. The animals were bilaterally implanted with the cannulas in the BLA and submitted to a step-through type passive avoidance task to measure the memory formation. The results showed that intraperitoneal (i.p.) administration of different doses of scopolamine (0.5-1.5mg/kg) immediately after the training phase (post-training) impaired memory consolidation. Bilateral microinjection of the cannabinoid CB1 receptor agonist, arachydonilcyclopropylamide (ACPA; 1-4ng/rat), into the BLA significantly improved scopolamine-induced memory consolidation impairment. On the other hand, co-administration of AM251, a cannabinoid CB1 receptor antagonist (0.25-1ng/rat, intra-BLA), with an ineffective dose of scopolamine (0.5mg/kg, i.p.), significantly impaired memory consolidation and mimicked the response of a higher dose of scopolamine. It is important to note that post-training intra-BLA microinjections of the same doses of ACPA or AM251 alone had no effect on memory consolidation. Moreover, the blockade of the BLA CB1 receptors by 0.3ng/rat of AM251 prevented ACPA-induced improvement of the scopolamine response. In view of the known actions of the drugs used, the present data pointed to the involvement of the BLA CB1 receptors in scopolamine-induced memory consolidation impairment. Furthermore, it seems that a functional interaction between the BLA endocannabinoid and cholinergic muscarinic systems may be critical for memory formation. Copyright © 2016. Published by Elsevier B.V.

Histamine H1 receptor antagonist cetirizine impairs working memory processing speed, but not episodic memory.

PubMed

van Ruitenbeek, P; Vermeeren, A; Riedel, W J

2010-09-01

The histaminergic neurotransmitter system is currently under investigation as a target for drug treatment of cognitive deficits in clinical disorders. The therapeutic potential of new drugs may initially be screened using a model of histaminergic dysfunction, for example, as associated with the use of centrally active antihistamines. Of the selective second generation antihistamines, cetirizine has been found to have central nervous system effects. The aim of the present study was to determine whether cetirizine can be used as a tool to model cognitive deficits associated with histaminergic hypofunction. The study was conducted according to a three-way, double-blind, cross-over design. Treatments were single oral doses of cetirizine 10 and 20 mg and placebo. Effects on cognition were assessed using tests of word learning, memory scanning, vigilance, divided attention, tracking and visual information processing speed. Cetirizine 10 mg impaired tracking performance and both doses impaired memory scanning speed. None of the other measures indicated impaired performance. Cetirizine affects information processing speed, but these effects were not sufficient to serve as a model for cognitive deficits in clinical disorders.

Autosophy: an alternative vision for satellite communication, compression, and archiving

NASA Astrophysics Data System (ADS)

Holtz, Klaus; Holtz, Eric; Kalienky, Diana

2006-08-01

Satellite communication and archiving systems are now designed according to an outdated Shannon information theory where all data is transmitted in meaningless bit streams. Video bit rates, for example, are determined by screen size, color resolution, and scanning rates. The video "content" is irrelevant so that totally random images require the same bit rates as blank images. An alternative system design, based on the newer Autosophy information theory, is now evolving, which transmits data "contend" or "meaning" in a universally compatible 64bit format. This would allow mixing all multimedia transmissions in the Internet's packet stream. The new systems design uses self-assembling data structures, which grow like data crystals or data trees in electronic memories, for both communication and archiving. The advantages for satellite communication and archiving may include: very high lossless image and video compression, unbreakable encryption, resistance to transmission errors, universally compatible data formats, self-organizing error-proof mass memories, immunity to the Internet's Quality of Service problems, and error-proof secure communication protocols. Legacy data transmission formats can be converted by simple software patches or integrated chipsets to be forwarded through any media - satellites, radio, Internet, cable - without needing to be reformatted. This may result in orders of magnitude improvements for all communication and archiving systems.

Energy efficient hybrid computing systems using spin devices

NASA Astrophysics Data System (ADS)

Sharad, Mrigank

Emerging spin-devices like magnetic tunnel junctions (MTJ's), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ˜20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode' processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ˜100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters.

Hierarchical resilience with lightweight threads.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wheeler, Kyle Bruce

2011-10-01

This paper proposes methodology for providing robustness and resilience for a highly threaded distributed- and shared-memory environment based on well-defined inputs and outputs to lightweight tasks. These inputs and outputs form a failure 'barrier', allowing tasks to be restarted or duplicated as necessary. These barriers must be expanded based on task behavior, such as communication between tasks, but do not prohibit any given behavior. One of the trends in high-performance computing codes seems to be a trend toward self-contained functions that mimic functional programming. Software designers are trending toward a model of software design where their core functions are specifiedmore » in side-effect free or low-side-effect ways, wherein the inputs and outputs of the functions are well-defined. This provides the ability to copy the inputs to wherever they need to be - whether that's the other side of the PCI bus or the other side of the network - do work on that input using local memory, and then copy the outputs back (as needed). This design pattern is popular among new distributed threading environment designs. Such designs include the Barcelona STARS system, distributed OpenMP systems, the Habanero-C and Habanero-Java systems from Vivek Sarkar at Rice University, the HPX/ParalleX model from LSU, as well as our own Scalable Parallel Runtime effort (SPR) and the Trilinos stateless kernels. This design pattern is also shared by CUDA and several OpenMP extensions for GPU-type accelerators (e.g. the PGI OpenMP extensions).« less

Differential Effects of Paced and Unpaced Responding on delayed Serial Order Recall in Schizophrenia

PubMed Central

Hill, S. Kristian; Griffin, Ginny B.; Houk, James C.; Sweeney, John A.

2011-01-01

Working memory for temporal order is a component of working memory that is especially dependent on striatal systems, but has not been extensively studied in schizophrenia. This study was designed to characterize serial order reproduction by adapting a spatial serial order task developed for nonhuman primate studies, while controlling for working memory load and whether responses were initiated freely (unpaced) or in an externally paced format. Clinically stable schizophrenia patients (n=27) and psychiatrically healthy individuals (n=25) were comparable on demographic variables and performance on standardized tests of immediate serial order recall (Digit Span, Spatial Span). No group differences were observed for serial order recall when read sequence reproduction was unpaced. However, schizophrenia patients exhibited significant impairments when responding was paced, regardless of sequence length or retention delay. Intact performance by schizophrenia patients during the unpaced condition indicates that prefrontal storage and striatal output systems are sufficiently intact to learn novel response sequences and hold them in working memory to perform serial order tasks. However, retention for newly learned response sequences was disrupted in schizophrenia patients by paced responding, when read-out of each element in the response sequence was externally controlled. The disruption of memory for serial order in paced read-out condition indicates a deficit in frontostriatal interaction characterized by an inability to update working memory stores and deconstruct ‘chunked’ information. PMID:21705197

Acute Effects of Ecstasy on Memory Are more Extensive than Chronic Effects.

PubMed

Shariati, Mohamad Bakhtiar Hesam; Sohrabi, Maryam; Shahidi, Siamak; Nikkhah, Ali; Mirzaei, Fatemeh; Medizadeh, Mehdi; Asl, Sara Soleimani

2014-01-01

Exposure to 3, 4- methylenedioxymethamphetamine (MDMA) could lead to serotonergic system toxicity in the brain. This system is responsible for learning and memory functions. Studies show that MDMA causes memory impairment dose-dependently and acutely. The present study was designed to evaluate the chronic and acute effects of MDMD on spatial memory and acquisition of passive avoidance. Adult male Wistar rats (200-250 g) were given single or multiple injections of MDMA (10 mg/kg, IP). Using passive avoidance and Morris Water Maze (MWM) tasks, learning and spatial memory functions were assessed. The data were analyzed by SPSS 16 software and one- way analysis of variance (ANOVA) test. Our results showed that there were significant differences in latency to enter the dark compartment (STL) between sham and MDMA- treated groups. Acute group significantly showed more STL in comparison with chronic group. Furthermore, MDMA groups spent more time in dark compartment (TDS) than the sham group. Administration of single dose of MDMA significantly caused an increase in TDS compared with the chronic group. In the MWM, MDMA treatment significantly increased the traveled distance and escaped latency compared to the sham group. Like to passive avoidance task, percentage of time spent in the target quadrant in MDMA- treated animals impaired in MWM compared with sham group. These data suggest that MDMA treatment impairs learning and memory functions that are more extensive in acute- treated rats.

Fault Tolerant Frequent Pattern Mining

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shohdy, Sameh; Vishnu, Abhinav; Agrawal, Gagan

FP-Growth algorithm is a Frequent Pattern Mining (FPM) algorithm that has been extensively used to study correlations and patterns in large scale datasets. While several researchers have designed distributed memory FP-Growth algorithms, it is pivotal to consider fault tolerant FP-Growth, which can address the increasing fault rates in large scale systems. In this work, we propose a novel parallel, algorithm-level fault-tolerant FP-Growth algorithm. We leverage algorithmic properties and MPI advanced features to guarantee an O(1) space complexity, achieved by using the dataset memory space itself for checkpointing. We also propose a recovery algorithm that can use in-memory and disk-based checkpointing,more » though in many cases the recovery can be completed without any disk access, and incurring no memory overhead for checkpointing. We evaluate our FT algorithm on a large scale InfiniBand cluster with several large datasets using up to 2K cores. Our evaluation demonstrates excellent efficiency for checkpointing and recovery in comparison to the disk-based approach. We have also observed 20x average speed-up in comparison to Spark, establishing that a well designed algorithm can easily outperform a solution based on a general fault-tolerant programming model.« less

AM06: the Associative Memory chip for the Fast TracKer in the upgraded ATLAS detector

NASA Astrophysics Data System (ADS)

Annovi, A.; Beretta, M. M.; Calderini, G.; Crescioli, F.; Frontini, L.; Liberali, V.; Shojaii, S. R.; Stabile, A.

2017-04-01

This paper describes the AM06 chip, which is a highly parallel processor for pattern recognition in the ATLAS high energy physics experiment. The AM06 contains memory banks that store data organized in 18 bit words; a group of 8 words is called "pattern". Each AM06 chip can store up to 131 072 patterns. The AM06 is a large chip, designed in 65 nm CMOS, and it combines full-custom memory arrays, standard logic cells and serializer/deserializer IP blocks at 2 Gbit/s for input/output communication. The overall silicon area is 168 mm2 and the chip contains about 421 million transistors. The AM06 receives the detector data for each event accepted by Level-1 trigger, up to 100 kHz, and it performs a track reconstruction based on hit information from channels of the ATLAS silicon detectors. Thanks to the design of a new associative memory cell and to the layout optimization, the AM06 consumption is only about 1 fJ/bit per comparison. The AM06 has been fabricated and successfully tested with a dedicated test system.

Experimental and numerical investigation into the behavior of shape memory alloys

NASA Astrophysics Data System (ADS)

Philander, Oscar; Oliver, Graeme John; Sun, Bohua

2012-11-01

Research and development of smart alignment systems is currently being undertaken at the Smart Devices and MEMS Laboratory at the Cape Peninsula University of Technology. The intended devices will harness the remarkable phenomena of shape memory alloys (SMAs), i.e. the shape memory effect and pseudo-elasticity, for actuation purposes. These unique characteristics of shape memory alloy behavior results from an austenitic ⇔ martensitic phase transformation during heating or cooling and/or a de-twinning of the martensitic variants due to an applied load. This paper investigates the microscopic and macroscopic behavior of SMA wires and uses the dynamic one-dimensional thermodynamic and statistical thermodynamic constitutive model proposed by Müller and Achenbach and further refined by Müller and Seelecke in the design of SMA line actuators. This model permits the simulation of the response of a tensile specimen to a thermodynamic input and calculates all phase transformations, phase proportions and deformations as functions of time if the temperature and applied load are prescribed as functions of time. The aim of this research is to develop an understanding of the numerical model and its implementation in the design of SMA line actuators. Specific results should show response time of a given length of SMA wire subjected to an applied load and temperature increase, and the load - displacement relationships for both quasi-plastic and pseudo-elastic behaviors. This paper also introduces some of the devices currently under investigation by the Smart Alignment Systems Research Group.

The magic words: Using computers to uncover mental associations for use in magic trick design

PubMed Central

2017-01-01

The use of computational systems to aid in the design of magic tricks has been previously explored. Here further steps are taken in this direction, introducing the use of computer technology as a natural language data sourcing and processing tool for magic trick design purposes. Crowd sourcing of psychological concepts is investigated; further, the role of human associative memory and its exploitation in magical effects is explored. A new trick is developed and evaluated: a physical card trick partially designed by a computational system configured to search for and explore conceptual spaces readily understood by spectators. PMID:28792941

Thiol-vinyl systems as shape memory polymers and novel two-stage reactive polymer systems

NASA Astrophysics Data System (ADS)

Nair, Devatha P.

2011-12-01

The focus of this research was to formulate, characterize and tailor the reaction methodologies and material properties of thiol-vinyl systems to develop novel polymer platforms for a range of engineering applications. Thiol-ene photopolymers were demonstrated to exhibit several advantageous characteristics for shape memory polymer systems for a range of biomedical applications. The thiol-ene shape memory polymer systems were tough and flexible as compared to the acrylic control systems with glass transition temperatures between 30 and 40 °C; ideal for actuation at body temperature. The thiol-ene polymers also exhibited excellent shape fixity and a rapid and distinct shape memory actuation response along with free strain recoveries of greater than 96% and constrained stress recoveries of 100%. Additionally, two-stage reactive thiol-acrylate systems were engineered as a polymer platform technology enabling two independent sets of polymer processing and material properties. There are distinct advantages to designing polymer systems that afford two distinct sets of material properties -- an intermediate polymer that would enable optimum handling and processing of the material (stage 1), while maintaining the ability to tune in different, final properties that enable the optimal functioning of the polymeric material (stage 2). To demonstrate the range of applicability of the two-stage reactive systems, three specific applications were demonstrated; shape memory polymers, lithographic impression materials, and optical materials. The thiol-acrylate reactions exhibit a wide range of application versatility due to the range of available thiol and acrylate monomers as well as reaction mechanisms such as Michael Addition reactions and free radical polymerizations. By designing a series of non-stoichiometeric thiol-acrylate systems, a polymer network is initially formed via a base catalyzed 'click' Michael addition reaction. This self-limiting reaction results in a Stage 1 polymer with excess acrylic functional groups within the network. At a later point in time, the photoinitiated, free radical polymerization of the excess acrylic functional groups results in a highly crosslinked, robust material system. By varying the monomers within the system as well as the stoichiometery of thiol to acrylate functional groups, the ability of the two-stage reactive systems to encompass a wide range of properties at the end of both the stage 1 and stage 2 polymerizations was demonstrated. The thiol-acrylate networks exhibited intermediate Stage 1 rubbery moduli and glass transition temperatures that range from 0.5 MPa and -10 ºC to 22 MPa and 22 ºC respectively. The same polymer networks can then attain glass transition temperatures that range from 5 ºC to 195 ºC and rubbery moduli of up to 200 MPa after the subsequent photocure stage. Two-stage reactive polymer composite systems were also formulated and characterized for thermomechanical and mechanical properties. Thermomechanical analysis showed that the fillers resulted in a significant increase in the modulus at both stage 1 and stage 2 polymerizations without a significant change in the glass transition temperatures (Tg). The two-stage reactive matrix composite formed with a hexafunctional acrylate matrix and 20 volume % silica particles showed a 125% increase in stage 1 modulus and 101% increase in stage 2 modulus, when compared with the modulus of the neat matrix. Finally, the two-stage reactive polymeric devices were formulated and designed as orthopedic suture anchors for arthroscopic surgeries and mechanically characterized. The Stage 1 device was designed to exhibit properties ideal for arthroscopic delivery and device placement with glass transition temperatures 25 -- 30 °C and rubbery moduli ˜ 95 MPa. The subsequent photopolymerization generated Stage 2 polymers designed to match the local bone environment with moduli ranging up to 2 GPa. Additionally, pull-out strengths of 140 N were demonstrated and are equivalent to the pull-strengths achieved by other commercially available suture anchors.

Furoxans (Oxadiazole-4 N-oxides) with Attenuated Reactivity are Neuroprotective, Cross the Blood Brain Barrier, and Improve Passive Avoidance Memory.

PubMed

Horton, Austin; Nash, Kevin; Tackie-Yarboi, Ethel; Kostrevski, Alexander; Novak, Adam; Raghavan, Aparna; Tulsulkar, Jatin; Alhadidi, Qasim; Wamer, Nathan; Langenderfer, Bryn; Royster, Kalee; Ducharme, Maxwell; Hagood, Katelyn; Post, Megan; Shah, Zahoor A; Schiefer, Isaac T

2018-05-07

Nitric oxide (NO) mimetics and other agents capable of enhancing NO/cGMP signaling have demonstrated efficacy as potential therapies for Alzheimer's disease. A group of thiol-dependent NO mimetics known as furoxans may be designed to exhibit attenuated reactivity to provide slow onset NO effects. The present study describes the design, synthesis, and evaluation of a furoxan library resulting in the identification of a prototype furoxan, 5a, which was profiled for use in the central nervous system. Furoxan 5a demonstrated negligible reactivity toward generic cellular thiols under physiological conditions. Nonetheless, cGMP-dependent neuroprotection was observed, and 5a (20 mg/kg) reversed cholinergic memory deficits in a mouse model of passive avoidance fear memory. Importantly, 5a can be prepared as a pharmaceutically acceptable salt and is observed in the brain 12 h after oral administration, suggesting potential for daily dosing and excellent metabolic stability. Continued investigation into furoxans as attenuated NO mimetics for the CNS is warranted.

Robust holographic storage system design.

PubMed

Watanabe, Takahiro; Watanabe, Minoru

2011-11-21

Demand is increasing daily for large data storage systems that are useful for applications in spacecraft, space satellites, and space robots, which are all exposed to radiation-rich space environment. As candidates for use in space embedded systems, holographic storage systems are promising because they can easily provided the demanded large-storage capability. Particularly, holographic storage systems, which have no rotation mechanism, are demanded because they are virtually maintenance-free. Although a holographic memory itself is an extremely robust device even in a space radiation environment, its associated lasers and drive circuit devices are vulnerable. Such vulnerabilities sometimes engendered severe problems that prevent reading of all contents of the holographic memory, which is a turn-off failure mode of a laser array. This paper therefore presents a proposal for a recovery method for the turn-off failure mode of a laser array on a holographic storage system, and describes results of an experimental demonstration. © 2011 Optical Society of America

Memory for time distinguishes between perception and action.

PubMed

Bueti, Domenica; Walsh, Vincent

2010-01-01

Our experience of time is unlike that of other features of the sensory world such as colour, movement, touch, or sound because there is no unique receptor system through which it is received. However, since time can be perceived, remembered, estimated, and compared in a way analogous to other sensory experiences, it should perhaps be subject to some of the same architectures or principles that have advanced understanding in these other domains. By adapting a task designed to test visual memory within a perception/action framework we investigated whether memory for time is affected by the use to which temporal information is put. When remembering a visual or auditory duration for subsequent motor production, storage is biased by a delay of up to 8 s. When the same duration is remembered for subsequent perception, however, there is no such effect of delay on memory. The results suggest a distinction in temporal memory that parallels the perception/action dichotomy in vision.

Brain oscillations track the formation of episodic memories in the real world.

PubMed

Griffiths, Benjamin; Mazaheri, Ali; Debener, Stefan; Hanslmayr, Simon

2016-12-01

Despite the well-known influence of environmental context on episodic memory, little has been done to increase contextual richness within the lab. This leaves a blind spot lingering over the neuronal correlates of episodic memory formation in day-to-day life. To address this, we presented participants with a series of words to memorise along a pre-designated route across campus while a mobile EEG system acquired ongoing neural activity. Replicating lab-based subsequent memory effects (SMEs), we identified significant low to mid frequency power decreases (<30Hz), including beta power decreases over the left inferior frontal gyrus. When investigating the oscillatory correlates of temporal and spatial context binding, we found that items strongly bound to spatial context exhibited significantly greater theta power decreases than items strongly bound to temporal context. These findings expand upon lab-based studies by demonstrating the influence of real world contextual factors that underpin memory formation. Copyright © 2016 Elsevier Inc. All rights reserved.

Shape memory alloy wire for self-sensing servo actuation

NASA Astrophysics Data System (ADS)

Josephine Selvarani Ruth, D.; Dhanalakshmi, K.

2017-01-01

This paper reports on the development of a straightforward approach to realise self-sensing shape memory alloy (SMA) wire actuated control. A differential electrical resistance measurement circuit (the sensorless signal conditioning (SSC) circuit) is designed; this sensing signal is directly used as the feedback for control. Antagonistic SMA wire actuators designed for servo actuation is realized in self-sensing actuation (SSA) mode for direct control with the differential electrical resistance feedback. The self-sensing scheme is established on a 1-DOF manipulator with the discrete time sliding mode controls which demonstrates good control performance, whatever be the disturbance and loading conditions. The uniqueness of this work is the design of the generic electronic SSC circuit for SMA actuated system, for measurement and control. With a concern to the implementation of self-sensing technique in SMA, this scheme retains the systematic control architecture by using the sensing signal (self-sensed, electrical resistance corresponding to the system position) for feedback, without requiring any processing as that of the methods adopted and reported previously for SSA techniques of SMA.

Implementing a bubble memory hierarchy system

NASA Technical Reports Server (NTRS)

Segura, R.; Nichols, C. D.

1979-01-01

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

[Memory assessment by means of virtual reality: its present and future].

PubMed

Diaz-Orueta, Unai; Climent, Gema; Cardas-Ibanez, Jaione; Alonso, Laura; Olmo-Osa, Juan; Tirapu-Ustarroz, Javier

2016-01-16

The human memory is a complex cognitive system whose close relationship with executive functions implies that, in many occasions, a mnemonic deficit comprises difficulties to operate with correctly stored contents. Traditional memory tests, more focused in the information storage than in its processing, may be poorly sensitive both to subjects' daily life functioning and to changes originated by rehabilitation programs. In memory assessment, there is plenty evidence with regards to the need of improving it by means of tests which offer a higher ecological validity, with information that may be presented in various sensorial modalities and produced in a simultaneous way. Virtual reality reproduces three-dimensional environments with which the patient interacts in a dynamic way, with a sense of immersion in the environment similar to the presence and exposure to a real environment, and in which presentation of such stimuli, distractors and other variables may be systematically controlled. The current review aims to go deeply into the trajectory of neuropsychological assessment of memory based in virtual reality environments, making a tour through existing tests designed for assessing learning, prospective, episodic and spatial memory, as well as the most recent attempts to perform a comprehensive evaluation of all memory components.

Examination of long-term visual memorization capacity in the Clark's nutcracker (Nucifraga columbiana).

PubMed

Qadri, Muhammad A J; Leonard, Kevin; Cook, Robert G; Kelly, Debbie M

2018-02-15

Clark's nutcrackers exhibit remarkable cache recovery behavior, remembering thousands of seed locations over the winter. No direct laboratory test of their visual memory capacity, however, has yet been performed. Here, two nutcrackers were tested in an operant procedure used to measure different species' visual memory capacities. The nutcrackers were incrementally tested with an ever-expanding pool of pictorial stimuli in a two-alternative discrimination task. Each picture was randomly assigned to either a right or a left choice response, forcing the nutcrackers to memorize each picture-response association. The nutcrackers' visual memorization capacity was estimated at a little over 500 pictures, and the testing suggested effects of primacy, recency, and memory decay over time. The size of this long-term visual memory was less than the approximately 800-picture capacity established for pigeons. These results support the hypothesis that nutcrackers' spatial memory is a specialized adaptation tied to their natural history of food-caching and recovery, and not to a larger long-term, general memory capacity. Furthermore, despite millennia of separate and divergent evolution, the mechanisms of visual information retention seem to reflect common memory systems of differing capacities across the different species tested in this design.

The effects of GABAA and NMDA receptors in the shell-accumbens on spatial memory of METH-treated rats.

PubMed

Heysieattalab, Soomaayeh; Naghdi, Nasser; Zarrindast, Mohammad-Reza; Haghparast, Abbas; Mehr, Shahram Ejtemaei; Khoshbouei, Habibeh

2016-03-01

Methamphetamine (METH) is a highly addictive and neurotoxic psychostimulant. Its use in humans is often associated with neurocognitive impairment and deficits in hippocampal plasticity. Striatal dopamine system is one of the main targets of METH. The dopamine neurons in the striatum directly or indirectly regulate the GABA and glutamatergic signaling in this region and thus their outputs. This is consistent with previous reports showing modification of neuronal activity in the striatum modulates the expression of hippocampal LTP and hippocampal-dependent memory tasks such as Morris water maze (MWM). Therefore, reversing or preventing METH-induced synaptic modifications via pharmacological manipulations of the shell-nucleus accumbens (shell-NAc) may introduce a viable therapeutic target to attenuate the METH-induced memory deficits. This study is designed to investigate the role of intra-shell NAc manipulation of GABAA and NMDA receptors and their interaction with METH on memory performance in MWM task. Pharmacological manipulations were performed in rats received METH or saline. We found systemic saline plus intra-shell NAc infusions of muscimol dose-dependently impaired performance, while bicuculline had no effect. Surprisingly, the intra-NAc infusions of 0.005μg/rat muscimol that has no effect on memory performance (ineffective dose) prevented METH-induced memory impairment. In the contrary, the intra-NAc infusions of bicuculline (0.2μg/rat) increased METH-induced memory impairment. However, pre-training intra-NAc infusions of D-AP5 dose-dependently impaired performance, while NMDA had no effect in rats received systemic saline (control group). The intra-NAc infusions with an ineffective dose of NMDA (0.1μg/rat) increased METH-induced memory impairment. Furthermore, intra-NAc infusions of D-AP5 with an ineffective dose (0.1μg/rat) prevented METH-induced memory impairment. Our result is consistent with the interpretation that METH-mediated learning deficit might be due to modification of hippocampus-VTA loop and that augmentation of GABAA receptor function in the shell-NAc may provide a new therapeutic target for alleviating METH-induced memory deficits. Copyright © 2015. Published by Elsevier Inc.

Exponential lag function projective synchronization of memristor-based multidirectional associative memory neural networks via hybrid control

NASA Astrophysics Data System (ADS)

Yuan, Manman; Wang, Weiping; Luo, Xiong; Li, Lixiang; Kurths, Jürgen; Wang, Xiao

2018-03-01

This paper is concerned with the exponential lag function projective synchronization of memristive multidirectional associative memory neural networks (MMAMNNs). First, we propose a new model of MMAMNNs with mixed time-varying delays. In the proposed approach, the mixed delays include time-varying discrete delays and distributed time delays. Second, we design two kinds of hybrid controllers. Traditional control methods lack the capability of reflecting variable synaptic weights. In this paper, the controllers are carefully designed to confirm the process of different types of synchronization in the MMAMNNs. Third, sufficient criteria guaranteeing the synchronization of system are derived based on the derive-response concept. Finally, the effectiveness of the proposed mechanism is validated with numerical experiments.

Complexity, Training Paradigm Design, and the Contribution of Memory Subsystems to Grammar Learning

PubMed Central

Ettlinger, Marc; Wong, Patrick C. M.

2016-01-01

Although there is variability in nonnative grammar learning outcomes, the contributions of training paradigm design and memory subsystems are not well understood. To examine this, we presented learners with an artificial grammar that formed words via simple and complex morphophonological rules. Across three experiments, we manipulated training paradigm design and measured subjects' declarative, procedural, and working memory subsystems. Experiment 1 demonstrated that passive, exposure-based training boosted learning of both simple and complex grammatical rules, relative to no training. Additionally, procedural memory correlated with simple rule learning, whereas declarative memory correlated with complex rule learning. Experiment 2 showed that presenting corrective feedback during the test phase did not improve learning. Experiment 3 revealed that structuring the order of training so that subjects are first exposed to the simple rule and then the complex improved learning. The cumulative findings shed light on the contributions of grammatical complexity, training paradigm design, and domain-general memory subsystems in determining grammar learning success. PMID:27391085

A novel ternary content addressable memory design based on resistive random access memory with high intensity and low search energy

NASA Astrophysics Data System (ADS)

Han, Runze; Shen, Wensheng; Huang, Peng; Zhou, Zheng; Liu, Lifeng; Liu, Xiaoyan; Kang, Jinfeng

2018-04-01

A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ∼60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

Temperature and leakage aware techniques to improve cache reliability

NASA Astrophysics Data System (ADS)

Akaaboune, Adil

Decreasing power consumption in small devices such as handhelds, cell phones and high-performance processors is now one of the most critical design concerns. On-chip cache memories dominate the chip area in microprocessors and thus arises the need for power efficient cache memories. Cache is the simplest cost effective method to attain high speed memory hierarchy and, its performance is extremely critical for high speed computers. Cache is used by the microprocessor for channeling the performance gap between processor and main memory (RAM) hence the memory bandwidth is frequently a bottleneck which can affect the peak throughput significantly. In the design of any cache system, the tradeoffs of area/cost, performance, power consumption, and thermal management must be taken into consideration. Previous work has mainly concentrated on performance and area/cost constraints. More recent works have focused on low power design especially for portable devices and media-processing systems, however fewer research has been done on the relationship between heat management, Leakage power and cost per die. Lately, the focus of power dissipation in the new generations of microprocessors has shifted from dynamic power to idle power, a previously underestimated form of power loss that causes battery charge to drain and shutdown too early due the waste of energy. The problem has been aggravated by the aggressive scaling of process; device level method used originally by designers to enhance performance, conserve dissipation and reduces the sizes of digital circuits that are increasingly condensed. This dissertation studies the impact of hotspots, in the cache memory, on leakage consumption and microprocessor reliability and durability. The work will first prove that by eliminating hotspots in the cache memory, leakage power will be reduced and therefore, the reliability will be improved. The second technique studied is data quality management that improves the quality of the data stored in the cache to reduce power consumption. The initial work done on this subject focuses on the type of data that increases leakage consumption and ways to manage without impacting the performance of the microprocessor. The second phase of the project focuses on managing the data storage in different blocks of the cache to smooth the leakage power as well as dynamic power consumption. The last technique is a voltage controlled cache to reduce the leakage consumption of the cache while in execution and even in idle state. Two blocks of the 4-way set associative cache go through a voltage regulator before getting to the voltage well, and the other two are directly connected to the voltage well. The idea behind this technique is to use the replacement algorithm information to increase or decrease voltage of the two blocks depending on the need of the information stored on them.

A non-destructive crossbar architecture of multi-level memory-based resistor

NASA Astrophysics Data System (ADS)

Sahebkarkhorasani, Seyedmorteza

Nowadays, researchers are trying to shrink the memory cell in order to increase the capacity of the memory system and reduce the hardware costs. In recent years, there has been a revolution in electronics by using fundamentals of physics to build a new memory for computer application in order to increase the capacity and decrease the power consumption. Increasing the capacity of the memory causes a growth in the chip area. From 1971 to 2012 semiconductor manufacturing process improved from 6mum to 22 mum. In May 2008, S.Williams stated that "it is time to stop shrinking". In his paper, he declared that the process of shrinking memory element has recently become very slow and it is time to use another alternative in order to create memory elements [9]. In this project, we present a new design of a memory array using the new element named Memristor [3]. Memristor is a two-terminal passive electrical element that relates the charge and magnetic flux to each other. The device remained unknown since 1971 when it was discovered by Chua and introduced as the fourth fundamental passive element like capacitor, inductor and resistor [3]. Memristor has a dynamic resistance and it can retain its previous value even after disconnecting the power supply. Due to this interesting behavior of the Memristor, it can be a good replacement for all of the Non-Volatile Memories (NVMs) in the near future. Combination of this newly introduced element with the nanowire crossbar architecture would be a great structure which is called Crossbar Memristor. Some frameworks have recently been introduced in literature that utilized Memristor crossbar array, but there are many challenges to implement the Memristor crossbar array due to fabrication and device limitations. In this work, we proposed a simple design of Memristor crossbar array architecture which uses input feedback in order to preserve its data after each read operation.

Optimization of Apparatus Design and Behavioral Measures for the Assessment of Visuo-Spatial Learning and Memory of Mice on the Barnes Maze

ERIC Educational Resources Information Center

O'Leary, Timothy P.; Brown, Richard E.

2013-01-01

We have previously shown that apparatus design can affect visual-spatial cue use and memory performance of mice on the Barnes maze. The present experiment extends these findings by determining the optimal behavioral measures and test procedure for analyzing visuo-spatial learning and memory in three different Barnes maze designs. Male and female…

Programming model for distributed intelligent systems

NASA Technical Reports Server (NTRS)

Sztipanovits, J.; Biegl, C.; Karsai, G.; Bogunovic, N.; Purves, B.; Williams, R.; Christiansen, T.

1988-01-01

A programming model and architecture which was developed for the design and implementation of complex, heterogeneous measurement and control systems is described. The Multigraph Architecture integrates artificial intelligence techniques with conventional software technologies, offers a unified framework for distributed and shared memory based parallel computational models and supports multiple programming paradigms. The system can be implemented on different hardware architectures and can be adapted to strongly different applications.

MOBS - A modular on-board switching system

NASA Astrophysics Data System (ADS)

Berner, W.; Grassmann, W.; Piontek, M.

The authors describe a multibeam satellite system that is designed for business services and for communications at a high bit rate. The repeater is regenerative with a modular onboard switching system. It acts not only as baseband switch but also as the central node of the network, performing network control and protocol evaluation. The hardware is based on a modular bus/memory architecture with associated processors.

Design, Implementation, and Evaluation of a Virtual Shared Memory System in a Multi-Transputer Network.

DTIC Science & Technology

1987-12-01

Synchronization and Data Passing Mechanism ........ 50 4. System Shut Down .................................................................. 51 5...high performance, fault tolerance, and extensibility. These features are attained by synchronizing and coordinating the dis- tributed multicomputer... synchronizing all processors in the network. In a multitransputer network, processes that communicate with each other do so synchronously . This makes

Cholinergic blockade under working memory demands encountered by increased rehearsal strategies: evidence from fMRI in healthy subjects.

PubMed

Voss, Bianca; Thienel, Renate; Reske, Martina; Kellermann, Thilo; Sheldrick, Abigail J; Halfter, Sarah; Radenbach, Katrin; Shah, Nadim J; Habel, Ute; Kircher, Tilo T J

2012-06-01

The connection between cholinergic transmission and cognitive performance has been established in behavioural studies. The specific contribution of the muscarinic receptor system on cognitive performance and brain activation, however, has not been evaluated satisfyingly. To investigate the specific contribution of the muscarinic transmission on neural correlates of working memory, we examined the effects of scopolamine, an antagonist of the muscarinic receptors, using functional magnetic resonance imaging (fMRI). Fifteen healthy male, non-smoking subjects performed a fMRI scanning session following the application of scopolamine (0.4 mg, i.v.) or saline in a placebo-controlled, repeated measure, pseudo-randomized, single-blind design. Working memory was probed using an n-back task. Compared to placebo, challenging the cholinergic transmission with scopolamine resulted in hypoactivations in parietal, occipital and cerebellar areas and hyperactivations in frontal and prefrontal areas. These alterations are interpreted as compensatory strategies used to account for downregulation due to muscarinic acetylcholine blockade in parietal and cerebral storage systems by increased activation in frontal and prefrontal areas related to working memory rehearsal. Our results further underline the importance of cholinergic transmission to working memory performance and determine the specific contribution of muscarinic transmission on cerebral activation associated with executive functioning.

Flight control system design factors for applying automated testing techniques

NASA Technical Reports Server (NTRS)

Sitz, Joel R.; Vernon, Todd H.

1990-01-01

The principal design features and operational experiences of the X-29 forward-swept-wing aircraft and F-18 high alpha research vehicle (HARV) automated test systems are discussed. It is noted that operational experiences in developing and using these automated testing techniques have highlighted the need for incorporating target system features to improve testability. Improved target system testability can be accomplished with the addition of nonreal-time and real-time features. Online access to target system implementation details, unobtrusive real-time access to internal user-selectable variables, and proper software instrumentation are all desirable features of the target system. Also, test system and target system design issues must be addressed during the early stages of the target system development. Processing speeds of up to 20 million instructions/s and the development of high-bandwidth reflective memory systems have improved the ability to integrate the target system and test system for the application of automated testing techniques. It is concluded that new methods of designing testability into the target systems are required.

Multi-petascale highly efficient parallel supercomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time andmore » supports DMA functionality allowing for parallel processing message-passing.« less

On the Mechanisms of Formation of Memory Channels and Development of Negative Differential Resistance in Solid Solutions of the TlInTe2-TlYbTe2 System

NASA Astrophysics Data System (ADS)

Akhmedova, A. M.

2018-04-01

The behavior of an electronic subsystem is investigated in the course of formation and development of a memory channel in solid solutions of the TlInTe2-TlYbTe2 system. An analysis of the current-voltage characteristics allows getting an insight into the reason for a sharp change in electrical conductance of the specimens under study during their transition from the high-resistance to high-conductance state and the reasons for the well known instability of threshold converters, which makes it possible to design devices with high threshold voltage stability.

A decomposition approach to the design of a multiferroic memory bit

NASA Astrophysics Data System (ADS)

Acevedo, Ruben; Liang, Cheng-Yen; Carman, Gregory P.; Sepulveda, Abdon E.

2017-06-01

The objective of this paper is to present a methodology for the design of a memory bit to minimize the energy required to write data at the bit level. By straining a ferromagnetic nickel nano-dot by means of a piezoelectric substrate, its magnetization vector rotates between two stable states defined as a 1 and 0 for digital memory. The memory bit geometry, actuation mechanism and voltage control law were used as design variables. The approach used was to decompose the overall design process into simpler sub-problems whose structure can be exploited for a more efficient solution. This method minimizes the number of fully dynamic coupled finite element analyses required to converge to a near optimal design, thus decreasing the computational time for the design process. An in-plane sample design problem is presented to illustrate the advantages and flexibility of the procedure.

A review of visual memory capacity: Beyond individual items and towards structured representations

PubMed Central

Brady, Timothy F.; Konkle, Talia; Alvarez, George A.

2012-01-01

Traditional memory research has focused on identifying separate memory systems and exploring different stages of memory processing. This approach has been valuable for establishing a taxonomy of memory systems and characterizing their function, but has been less informative about the nature of stored memory representations. Recent research on visual memory has shifted towards a representation-based emphasis, focusing on the contents of memory, and attempting to determine the format and structure of remembered information. The main thesis of this review will be that one cannot fully understand memory systems or memory processes without also determining the nature of memory representations. Nowhere is this connection more obvious than in research that attempts to measure the capacity of visual memory. We will review research on the capacity of visual working memory and visual long-term memory, highlighting recent work that emphasizes the contents of memory. This focus impacts not only how we estimate the capacity of the system - going beyond quantifying how many items can be remembered, and moving towards structured representations - but how we model memory systems and memory processes. PMID:21617025

Performance and scalability evaluation of "Big Memory" on Blue Gene Linux.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yoshii, K.; Iskra, K.; Naik, H.

2011-05-01

We address memory performance issues observed in Blue Gene Linux and discuss the design and implementation of 'Big Memory' - an alternative, transparent memory space introduced to eliminate the memory performance issues. We evaluate the performance of Big Memory using custom memory benchmarks, NAS Parallel Benchmarks, and the Parallel Ocean Program, at a scale of up to 4,096 nodes. We find that Big Memory successfully resolves the performance issues normally encountered in Blue Gene Linux. For the ocean simulation program, we even find that Linux with Big Memory provides better scalability than does the lightweight compute node kernel designed solelymore » for high-performance applications. Originally intended exclusively for compute node tasks, our new memory subsystem dramatically improves the performance of certain I/O node applications as well. We demonstrate this performance using the central processor of the LOw Frequency ARray radio telescope as an example.« less

Acute effects of alcohol on memory: impact of emotional context and serial position.

PubMed

Brown, Jennie; Brignell, Catherine M; Dhiman, Sharinjeet K; Curran, H Valerie; Kamboj, Sunjeev K

2010-03-01

Although the amnestic effects of alcohol in humans are well known, its effects on emotional memory are unclear. In this study, using a randomized double-blind placebo-controlled design, we examine narrative emotional episodic memory in healthy human female volunteers (n=32) who received either a single dose of alcohol (0.6g/kg), or a placebo and then viewed neutral story elements presented in either a neutral or emotional context. Memory was tested for gist and detail of the neutral elements 3days later in a surprise recognition test. Since alcohol modulates GABAergic neurotransmission and may exert its effects on emotion through the limbic system, we predicted that acute alcohol treatment would reduce the expected emotional memory-advantage for gist, leaving detail memory relatively unaffected. Furthermore, given previous findings showing that 'primacy' memory is enhanced by physiological arousal, we predicted that reduced arousal produced by alcohol would have the opposite effect and impair primacy memory relative to the middle or 'recency' sections of the narrative. Emotional arousal was expected to oppose this effect, so impaired primacy memory following alcohol was only expected in the neutral version of the narrative. Although there was a main effect of story phase (though not of story version), contrary to expectations, alcohol impaired primacy memory for emotionally encoded neutral material. The results suggest that under certain circumstances emotional context or physiological arousal make memories labile and susceptible to disruption through pharmacological manipulation during encoding. 2009 Elsevier Inc. All rights reserved.

Reliability of Memories Protected by Multibit Error Correction Codes Against MBUs

NASA Astrophysics Data System (ADS)

Ming, Zhu; Yi, Xiao Li; Chang, Liu; Wei, Zhang Jian

2011-02-01

As technology scales, more and more memory cells can be placed in a die. Therefore, the probability that a single event induces multiple bit upsets (MBUs) in adjacent memory cells gets greater. Generally, multibit error correction codes (MECCs) are effective approaches to mitigate MBUs in memories. In order to evaluate the robustness of protected memories, reliability models have been widely studied nowadays. Instead of irradiation experiments, the models can be used to quickly evaluate the reliability of memories in the early design. To build an accurate model, some situations should be considered. Firstly, when MBUs are presented in memories, the errors induced by several events may overlap each other, which is more frequent than single event upset (SEU) case. Furthermore, radiation experiments show that the probability of MBUs strongly depends on angles of the radiation event. However, reliability models which consider the overlap of multiple bit errors and angles of radiation event have not been proposed in the present literature. In this paper, a more accurate model of memories with MECCs is presented. Both the overlap of multiple bit errors and angles of event are considered in the model, which produces a more precise analysis in the calculation of mean time to failure (MTTF) for memory systems under MBUs. In addition, memories with scrubbing and nonscrubbing are analyzed in the proposed model. Finally, we evaluate the reliability of memories under MBUs in Matlab. The simulation results verify the validity of the proposed model.

Mission STS-134: Results of Shape Memory Foam Experiment

NASA Astrophysics Data System (ADS)

Santo, Loredana; Quadrini, Fabrizio; Mascetti, Gabriele; Dolce, Ferdinando; Zolesi, Valfredo

2013-10-01

Shape memory epoxy foams were used for an experiment aboard the International Space Station (ISS) to evaluate the feasibility of their use for building light actuators and expandable/deployable structures. The experiment named I-FOAM was performed by an autonomous device contained in the BIOKON container (by Kayser Italia) which was in turn composed of control and heating system, battery pack and data acquisition system. To simulate the actuation of simple devices in micro-gravity conditions, three different configurations (compression, bending and torsion) were chosen during the memory step of the foams so as to produce their recovery on ISS. Micro-gravity does not affect the ability of the foams to recover their shape but it poses limits for the heating system design because of the difference in heat transfer on Earth and in orbit. A recovery about 70% was measured at a temperature of 110 °C for the bending and torsion configuration whereas poor recovery was observed for the compression case. Thanks to these results, a new experiment has been developed for a future mission by the same device: for the first time a shape memory composite will be recovered, and the actuation load during time will be measured during the recovery of an epoxy foam sample.

System Assessment of a High Power 3-U CubeSat

NASA Technical Reports Server (NTRS)

Shaw, Katie

2016-01-01

The Advanced eLectrical Bus (ALBus) CubeSat project is a technology demonstration mission of a 3-UCubeSat with an advanced, digitally controlled electrical power system capability and novel use of Shape Memory Alloy (SMA) technology for reliable deployable solar array mechanisms. The objective of the project is to, through an on orbit demonstration, advance the state of power management and distribution (PMAD) capabilities to enable future missions requiring higher power, flexible and reliable power systems. The goals of the mission include demonstration of: 100 Watt distribution to a target electrical load, efficient battery charging in the orbital environment, flexible power system distribution interfaces, adaptation of power system control on orbit, and reliable deployment of solar arrays and antennas utilizing re-settable SMA mechanisms. The power distribution function of the ALBus PMAD system is unique in the total power to target load capability of 100 W, the flexibility to support centralized or point-to-load regulation and ability to respond to fast transient power requirements. Power will be distributed from batteries at 14.8 V, 6.5 A to provide 100 W of power directly to a load. The deployable solar arrays utilize NASA Glenn Research Center superelastic and activated Nitinol(Nickel-Titanium alloy) Shape Memory Alloy (SMA) technology for hinges and a retention and release mechanism. The deployable solar array hinge design features utilization of the SMA material properties for dual purpose. The hinge uses the shape memory properties of the SMA to provide the spring force to deploy the arrays. The electrical conductivity properties of the SMA also enables the design to provide clean conduits for power transfer from the deployable arrays to the power management system. This eliminates the need for electrical harnesses between the arrays and the PMAD system in the ALBus system design. The uniqueness of the SMA retention and release mechanism design is the ability to reset the mechanism, allowing functional tests of the mechanisms prior to flight with no degradation of performance. The project is currently in preparation at the NASA Glenn Research Center for a launch in late calendar year of 2017. The 100 Watt power distribution and dual purpose, re-settable SMA mechanisms introduced several system level challenges due to the physical constraints in volume, mass and surface area of 3-U CubeSats. Several trade studies and design cycles have been completed to develop a system which supports the project objectives. This paper is a report on the results of the system level trade studies and assessments. The results include assessment of options for thermal control of 100 Watts of power dissipation, data from system analyses and engineering development tests, limitations of the 3-U system and extensibility to larger scale CubeSat missions.

The Impact of Software Structure and Policy on CPU and Memory System Performance

DTIC Science & Technology

1994-05-01

Mach 3.0 is that Ultrix is a monolithic or integrated system, and Mach 3.0 is a microkernel or kernelized system. In a monolithic system, all system...services are implemented in a single system context, the monolithic kernel . In a microkernel system such as Mach 3.0, primitive abstractions such as...separate protection domain as a server. Many current operating system text books discuss microkernel and monolithic kernel design. (See [17, 73, 77].) The

Multifunctional wearable devices for diagnosis and therapy of movement disorders.

PubMed

Son, Donghee; Lee, Jongha; Qiao, Shutao; Ghaffari, Roozbeh; Kim, Jaemin; Lee, Ji Eun; Song, Changyeong; Kim, Seok Joo; Lee, Dong Jun; Jun, Samuel Woojoo; Yang, Shixuan; Park, Minjoon; Shin, Jiho; Do, Kyungsik; Lee, Mincheol; Kang, Kwanghun; Hwang, Cheol Seong; Lu, Nanshu; Hyeon, Taeghwan; Kim, Dae-Hyeong

2014-05-01

Wearable systems that monitor muscle activity, store data and deliver feedback therapy are the next frontier in personalized medicine and healthcare. However, technical challenges, such as the fabrication of high-performance, energy-efficient sensors and memory modules that are in intimate mechanical contact with soft tissues, in conjunction with controlled delivery of therapeutic agents, limit the wide-scale adoption of such systems. Here, we describe materials, mechanics and designs for multifunctional, wearable-on-the-skin systems that address these challenges via monolithic integration of nanomembranes fabricated with a top-down approach, nanoparticles assembled by bottom-up methods, and stretchable electronics on a tissue-like polymeric substrate. Representative examples of such systems include physiological sensors, non-volatile memory and drug-release actuators. Quantitative analyses of the electronics, mechanics, heat-transfer and drug-diffusion characteristics validate the operation of individual components, thereby enabling system-level multifunctionalities.

Methods to measure olfactory behavior in mice

PubMed Central

Zou, Junhui; Wang, Wenbin; Pan, Yung-Wei; Lu, Song; Xia, Zhengui

2015-01-01

Mice rely on the sense of olfaction to detect food sources, recognize social and mating partners, and avoid predators. Many behaviors of mice including learning and memory, social interaction, fear, and anxiety are closely associated with their function of olfaction, and behavior tasks designed to evaluate those brain functions may use odors as cues. Accurate assessment of olfaction is not only essential for the study of olfactory system but also critical for proper interpretation of various mouse behaviors especially learning and memory, emotionality and affect, and sociality. Here we describe a series of behavior experiments that offer multidimensional and quantitative assessments for mouse’s olfactory function, including olfactory habituation, discrimination, odor preference, odor detection sensitivity, and olfactory memory, to both social and nonsocial odors. PMID:25645244

Consumer holographic read-only memory reader with mastering and replication technology.

PubMed

Chuang, Ernest; Curtis, Kevin; Yang, Yunping; Hill, Adrian

2006-04-15

What is believed to be a novel holographic design for read-only memory systems allows a compact low-cost consumer drive within a 10 mm drive height, using a lensless phase conjugate readout and a combination of polytopic and angle multiplexing. A two-step mastering method enables production of high-efficiency holographic masters, and fast replication is possible by using only a series of plane-wave illuminations. Mastering and replication techniques are verified experimentally with an array of 125 holograms with no measured bit errors.

Parallel processing approach to transform-based image coding

NASA Astrophysics Data System (ADS)

Normile, James O.; Wright, Dan; Chu, Ken; Yeh, Chia L.

1991-06-01

This paper describes a flexible parallel processing architecture designed for use in real time video processing. The system consists of floating point DSP processors connected to each other via fast serial links, each processor has access to a globally shared memory. A multiple bus architecture in combination with a dual ported memory allows communication with a host control processor. The system has been applied to prototyping of video compression and decompression algorithms. The decomposition of transform based algorithms for decompression into a form suitable for parallel processing is described. A technique for automatic load balancing among the processors is developed and discussed, results ar presented with image statistics and data rates. Finally techniques for accelerating the system throughput are analyzed and results from the application of one such modification described.

Merlin - Massively parallel heterogeneous computing

NASA Technical Reports Server (NTRS)

Wittie, Larry; Maples, Creve

1989-01-01

Hardware and software for Merlin, a new kind of massively parallel computing system, are described. Eight computers are linked as a 300-MIPS prototype to develop system software for a larger Merlin network with 16 to 64 nodes, totaling 600 to 3000 MIPS. These working prototypes help refine a mapped reflective memory technique that offers a new, very general way of linking many types of computer to form supercomputers. Processors share data selectively and rapidly on a word-by-word basis. Fast firmware virtual circuits are reconfigured to match topological needs of individual application programs. Merlin's low-latency memory-sharing interfaces solve many problems in the design of high-performance computing systems. The Merlin prototypes are intended to run parallel programs for scientific applications and to determine hardware and software needs for a future Teraflops Merlin network.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

A One Chip Hardened Solution for High Speed SpaceWire System Implementations. Session: Components

NASA Technical Reports Server (NTRS)

Marshall, Joseph R.; Berger, Richard W.; Rakow, Glenn P.

2007-01-01

An Application Specific Integrated Circuit (ASIC) that implements the SpaceWire protocol has been developed in a radiation hardened 0.25 micron CMOS technology. This effort began in March 2003 as a joint development between the NASA Goddard Space Flight Center (GSFC) and BAE Systems. The BAE Systems SpaceWire ASIC is comprised entirely of reusable core elements, many of which are already flight-proven. It incorporates a router with 4 SpaceWire ports and two local ports, dual PC1 bus interfaces, a microcontroller, 32KB of internal memory, and a memory controller for additional external memory use. The SpaceWire cores are also reused in other ASICs under development. The SpaceWire ASIC is planned for use on the Geostationary Operational Environmental Satellites (GOES)-R, the Lunar Reconnaissance Orbiter (LRO) and other missions. Engineering and flight parts have been delivered to programs and users. This paper reviews the SpaceWire protocol and those elements of it that have been built into the current and next SpaceWire reusable cores and features within the core that go beyond the current standard and can be enabled or disabled by the user. The adaptation of SpaceWire to BAE Systems' On Chip Bus (OCB) for compatibility with the other reusable cores will be reviewed and highlighted. Optional configurations within user systems and test boards will be shown. The physical implementation of the design will be described and test results from the hardware will be discussed. Application of this ASIC and other ASICs containing the SpaceWire cores and embedded microcontroller to Plug and Play and reconfigurable implementations will be described. Finally, the BAE Systems roadmap for SpaceWire developments will be updated, including some products already in design as well as longer term plans.

Assessing Spatial Learning and Memory in Rodents

PubMed Central

Vorhees, Charles V.; Williams, Michael T.

2014-01-01

Maneuvering safely through the environment is central to survival of almost all species. The ability to do this depends on learning and remembering locations. This capacity is encoded in the brain by two systems: one using cues outside the organism (distal cues), allocentric navigation, and one using self-movement, internal cues and nearby proximal cues, egocentric navigation. Allocentric navigation involves the hippocampus, entorhinal cortex, and surrounding structures; in humans this system encodes allocentric, semantic, and episodic memory. This form of memory is assessed in laboratory animals in many ways, but the dominant form of assessment is the Morris water maze (MWM). Egocentric navigation involves the dorsal striatum and connected structures; in humans this system encodes routes and integrated paths and, when overlearned, becomes procedural memory. In this article, several allocentric assessment methods for rodents are reviewed and compared with the MWM. MWM advantages (little training required, no food deprivation, ease of testing, rapid and reliable learning, insensitivity to differences in body weight and appetite, absence of nonperformers, control methods for proximal cue learning, and performance effects) and disadvantages (concern about stress, perhaps not as sensitive for working memory) are discussed. Evidence-based design improvements and testing methods are reviewed for both rats and mice. Experimental factors that apply generally to spatial navigation and to MWM specifically are considered. It is concluded that, on balance, the MWM has more advantages than disadvantages and compares favorably with other allocentric navigation tasks. PMID:25225309

Method and apparatus for faulty memory utilization

DOEpatents

Cher, Chen-Yong; Andrade Costa, Carlos H.; Park, Yoonho; Rosenburg, Bryan S.; Ryu, Kyung D.

2016-04-19

A method for faulty memory utilization in a memory system includes: obtaining information regarding memory health status of at least one memory page in the memory system; determining an error tolerance of the memory page when the information regarding memory health status indicates that a failure is predicted to occur in an area of the memory system affecting the memory page; initiating a migration of data stored in the memory page when it is determined that the data stored in the memory page is non-error-tolerant; notifying at least one application regarding a predicted operating system failure and/or a predicted application failure when it is determined that data stored in the memory page is non-error-tolerant and cannot be migrated; and notifying at least one application regarding the memory failure predicted to occur when it is determined that data stored in the memory page is error-tolerant.

Perspective view, northeast. Billings Memorial Library was designed by H.H. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

Perspective view, northeast. Billings Memorial Library was designed by H.H. Richardson in 1883-85 in his characteristic Romanesque Revival mode. Located on the University of Vermont campus, it is now a student center. - University of Vermont, Billings Memorial Library, 48 University Place, Burlington, Chittenden County, VT

The role of trigeminal nucleus caudalis orexin 1 receptors in orofacial pain transmission and in orofacial pain-induced learning and memory impairment in rats.

PubMed

Kooshki, Razieh; Abbasnejad, Mehdi; Esmaeili-Mahani, Saeed; Raoof, Maryam

2016-04-01

It is widely accepted that the spinal trigeminal nuclear complex, especially the subnucleus caudalis (Vc), receives input from orofacial structures. The neuropeptides orexin-A and -B are expressed in multiple neuronal systems. Orexin signaling has been implicated in pain-modulating system as well as learning and memory processes. Orexin 1 receptor (OX1R) has been reported in trigeminal nucleus caudalis. However, its roles in trigeminal pain modulation have not been elucidated so far. This study was designed to investigate the role of Vc OX1R in the modulation of orofacial pain as well as pain-induced learning and memory deficits. Orofacial pain was induced by subcutaneous injection of capsaicin in the right upper lip of the rats. OX1R agonist (orexin-A) and antagonist (SB-334867-A) were microinjected into Vc prior capsaicin administration. After recording nociceptive times, learning and memory was investigated using Morris water maze (MWM) test. The results indicated that, orexin-A (150 pM/rat) significantly reduced the nociceptive times, while SB334867-A (80 nM/rat) exaggerated nociceptive behavior in response to capsaicin injection. In MWM test, capsaicin-treated rats showed a significant learning and memory impairment. Moreover, SB-334867-A (80 nM/rat) significantly exaggerated learning and memory impairment in capsaicin-treated rats. However, administration of orexin-A (100 pM/rat) prevented learning and memory deficits. Taken together, these results indicate that Vc OX1R was at least in part involved in orofacial pain transmission and orexin-A has also a beneficial inhibitory effect on orofacial pain-induced deficits in abilities of spatial learning and memory. Copyright © 2016 Elsevier Inc. All rights reserved.

Symbolic and Sub-Symbolic Robotic Intelligence Control System (SS-RICS) Users Manual

DTIC Science & Technology

2017-10-01

platform and simulators via either a serial or Transmission Control Protocol (TCP)/IP connection. The implementation of SS-RICS was designed and...box 4.2 SubSim Config Dialog This interface (Fig. 22) is designed to provide execution and property control of all of the subsimprocessors... post fixed with a “_” to designate the end of the variable (e.g., $Line1_memory was found). Example: rTestDollarSign { (* $LookType Distance

Research and Development of Collaborative Environments for Command and Control

DTIC Science & Technology

2011-05-01

at any state of building. The viewer tool presents the designed model with 360-degree perspective views even after regeneration of the design, which...and it shows the following prompt. GUM > APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED...11 First initialize the microSD card by typing GUM > mmcinit Then erase the old Linux kernel and the root file system on the flash memory

Strategies To Enhance Memory Based on Brain-Research.

ERIC Educational Resources Information Center

Banikowski, Alison K.; Mehring, Teresa A.

1999-01-01

This article reviews the literature on three aspects of memory: (1) an information processing model of memory (including the sensory register, attention, short-term memory, and long-term memory); (2) instructional strategies designed to enhance memory (which stress gaining students' attention and active involvement); and (3) reasons why…

A computer package for the design and eigenproblem solution of damped linear multidegree of freedom systems

NASA Technical Reports Server (NTRS)

Ahmadian, M.; Inman, D. J.

1982-01-01

Systems described by the matrix differental equation are considered. An interactive design routine is presented for positive definite mass, damping, and stiffness matrices. Designing is accomplished by adjusting the mass, damping, and stiffness matrices to obtain a desired oscillation behavior. The algorithm also features interactively modifying the physical structure of the system, obtaining the matrix structure and a number of other system properties. In case of a general system, where the M, C, and K matrices lack any special properties, a routine for the eigenproblem solution of the system is developed. The latent roots are obtained by computing the characteristic polynomial of the system and solving for its roots. The above routines are prepared in FORTRAN IV and prove to be usable for the machines with low core memory.

Interaction between hippocampal serotonin and cannabinoid systems in reactivity to spatial and object novelty detection.

PubMed

Nasehi, Mohammad; Rostam-Nezhad, Elnaz; Ebrahimi-Ghiri, Mohaddeseh; Zarrindast, Mohammad-Reza

2017-01-15

Functional interaction between cannabinoid and serotonin neuronal systems have been reported in different tasks related to memory assessment. The present study investigated the effect of serotonin 5-HT4 agents into the dorsal hippocampus (the CA1 region) on spatial and object novelty detection deficits induced by activation of cannabinoid CB1 receptors (CB1Rs) using arachidonylcyclopropylamide (ACPA) in a non-associative behavioral task designed to forecast the ability of rodents to encode spatial and non-spatial relationships between distinct stimuli. Post-training, intra-CA1 microinjection of 5-HT4 receptor agonist RS67333 or 5-HT4 receptor antagonist RS23597 both at the dose of 0.016μg/mouse impaired spatial memory, while cannabinoid CB1R antagonist AM251 (0.1μg/mouse) facilitated object novelty memory. Also, post-training, intraperitoneal administration of CB1R agonist ACPA (0.005-0.05mg/kg) impaired both memories. However, a subthreshold dose of RS67333 restored ACPA response on both memories. Moreover, a subthreshold dose of RS23597 potentiated ACPA (0.01mg/kg) and reversed ACPA (0.05mg/kg) responses on spatial memory, while it potentiated ACPA response at the dose of 0.005 or 0.05mg/kg on object novelty memory. Furthermore, effective dose of AM251 restored ACPA response at the higher dose. AM251 blocked response induced by combination of RS67333 or RS23597 and the higher dose of ACPA on both memories. Our results highlight that hippocampal 5-HT4 receptors differently affect cannabinoid signaling in spatial and object novelty memories. The inactivation of CB1 receptors blocks the effect of 5-HT4 agents into the CA1 region on memory deficits induced by activation of CB1Rs via ACPA. Copyright © 2016. Published by Elsevier B.V.

Adolescents with and without gestational cocaine exposure: Longitudinal analysis of inhibitory control, memory and receptive language.

PubMed

Betancourt, Laura M; Yang, Wei; Brodsky, Nancy L; Gallagher, Paul R; Malmud, Elsa K; Giannetta, Joan M; Farah, Martha J; Hurt, Hallam

2011-01-01

Preclinical studies of gestational cocaine exposure (GCE) show evidence of changes in brain function at the anatomical, physiological, and behavioral levels, to include effects on developing dopaminergic systems. In contrast, human studies have produced less consistent results, with most showing small effects or no effects on developmental outcomes. Important changes in brain structure and function occur through adolescence, therefore it is possible that prenatal cocaine exposure has latent effects on neurocognitive (NC) outcome that do not manifest until adolescence or young adulthood. We examined NC function using a set of 5 tasks designed to tap 4 different systems: inhibitory control, working memory, receptive language, and incidental memory. For each NC task, data were collected longitudinally at ages 12, 14.5 and 17 years and examined using generalized estimating equations. One hundred and nine children completed at least two of the three evaluations. Covariates included in the final model were assessment number, gender, participant age at first assessment, caregiver depression, and two composites from the Home Observation for Measurement of the Environment (HOME), Environmental Stimulation and Parental Nurturance. We found no cocaine effects on inhibitory control, working memory, or receptive language (p=0.18). GCE effects were observed on incidental face memory task (p=0.055), and GCE by assessment number interaction effects were seen on the incidental word memory task (p=0.031). Participant performance on inhibitory control, working memory, and receptive language tasks improved over time. HOME Environmental Stimulation composite was associated with better receptive language functioning. With a larger sample size smaller differences between groups may have been detected. This report shows no evidence of latent effects of GCE on inhibitory control, working memory, or receptive language. GCE effects were observed on the incidental face memory task, and GCE by assessment number interaction effects was seen on the incidental word memory task. Copyright © 2010 Elsevier Inc. All rights reserved.

Working Memory Systems in the Rat.

PubMed

Bratch, Alexander; Kann, Spencer; Cain, Joshua A; Wu, Jie-En; Rivera-Reyes, Nilda; Dalecki, Stefan; Arman, Diana; Dunn, Austin; Cooper, Shiloh; Corbin, Hannah E; Doyle, Amanda R; Pizzo, Matthew J; Smith, Alexandra E; Crystal, Jonathon D

2016-02-08

A fundamental feature of memory in humans is the ability to simultaneously work with multiple types of information using independent memory systems. Working memory is conceptualized as two independent memory systems under executive control [1, 2]. Although there is a long history of using the term "working memory" to describe short-term memory in animals, it is not known whether multiple, independent memory systems exist in nonhumans. Here, we used two established short-term memory approaches to test the hypothesis that spatial and olfactory memory operate as independent working memory resources in the rat. In the olfactory memory task, rats chose a novel odor from a gradually incrementing set of old odors [3]. In the spatial memory task, rats searched for a depleting food source at multiple locations [4]. We presented rats with information to hold in memory in one domain (e.g., olfactory) while adding a memory load in the other domain (e.g., spatial). Control conditions equated the retention interval delay without adding a second memory load. In a further experiment, we used proactive interference [5-7] in the spatial domain to compromise spatial memory and evaluated the impact of adding an olfactory memory load. Olfactory and spatial memory are resistant to interference from the addition of a memory load in the other domain. Our data suggest that olfactory and spatial memory draw on independent working memory systems in the rat. Copyright © 2016 Elsevier Ltd. All rights reserved.

Commutated automatic gain control system

NASA Technical Reports Server (NTRS)

Yost, S. R.

1982-01-01

A commutated automatic gain control (AGC) system was designed and built for a prototype Loran C receiver. The receiver uses a microcomputer to control a memory aided phase-locked loop (MAPLL). The microcomputer also controls the input/output, latitude/longitude conversion, and the recently added AGC system. The circuit designed for the AGC is described, and bench and flight test results are presented. The AGC circuit described actually samples starting at a point 40 microseconds after a zero crossing determined by the software lock pulse ultimately generated by a 30 microsecond delay and add network in the receiver front end envelope detector.

GridTool: A surface modeling and grid generation tool

NASA Technical Reports Server (NTRS)

Samareh-Abolhassani, Jamshid

1995-01-01

GridTool is designed around the concept that the surface grids are generated on a set of bi-linear patches. This type of grid generation is quite easy to implement, and it avoids the problems associated with complex CAD surface representations and associated surface parameterizations. However, the resulting surface grids are close to but not on the original CAD surfaces. This problem can be alleviated by projecting the resulting surface grids onto the original CAD surfaces. GridTool is designed primary for unstructured grid generation systems. Currently, GridTool supports VGRID and FELISA systems, and it can be easily extended to support other unstructured grid generation systems. The data in GridTool is stored parametrically so that once the problem is set up, one can modify the surfaces and the entire set of points, curves and patches will be updated automatically. This is very useful in a multidisciplinary design and optimization process. GridTool is written entirely in ANSI 'C', the interface is based on the FORMS library, and the graphics is based on the GL library. The code has been tested successfully on IRIS workstations running IRIX4.0 and above. The memory is allocated dynamically, therefore, memory size will depend on the complexity of geometry/grid. GridTool data structure is based on a link-list structure which allows the required memory to expand and contract dynamically according to the user's data size and action. Data structure contains several types of objects such as points, curves, patches, sources and surfaces. At any given time, there is always an active object which is drawn in magenta, or in their highlighted colors as defined by the resource file which will be discussed later.

Shape Control of Solar Collectors Using Shape Memory Alloy Actuators

NASA Technical Reports Server (NTRS)

Lobitz, D. W.; Grossman, J. W.; Allen, J. J.; Rice, T. M.; Liang, C.; Davidson, F. M.

1996-01-01

Solar collectors that are focused on a central receiver are designed with a mechanism for defocusing the collector or disabling it by turning it out of the path of the sun's rays. This is required to avoid damaging the receiver during periods of inoperability. In either of these two cases a fail-safe operation is very desirable where during power outages the collector passively goes to its defocused or deactivated state. This paper is principally concerned with focusing and defocusing the collector in a fail-safe manner using shape memory alloy actuators. Shape memory alloys are well suited to this application in that once calibrated the actuators can be operated in an on/off mode using a minimal amount of electric power. Also, in contrast to other smart materials that were investigated for this application, shape memory alloys are capable of providing enough stroke at the appropriate force levels to focus the collector. Design and analysis details presented, along with comparisons to test data taken from an actual prototype, demonstrate that the collector can be repeatedly focused and defocused within accuracies required by typical solar energy systems. In this paper the design, analysis and testing of a solar collector which is deformed into its desired shape by shape memory alloy actuators is presented. Computations indicate collector shapes much closer to spherical and with smaller focal lengths can be achieved by moving the actuators inward to a radius of approximately 6 inches. This would require actuators with considerably more stroke and some alternate SMA actuators are currently under consideration. Whatever SMA actuator is finally chosen for this application, repeatability and fatigue tests will be required to investigate the long term performance of the actuator.

Not all order memory is equal: Test demands reveal dissociations in memory for sequence information.

PubMed

Jonker, Tanya R; MacLeod, Colin M

2017-02-01

Remembering the order of a sequence of events is a fundamental feature of episodic memory. Indeed, a number of formal models represent temporal context as part of the memory system, and memory for order has been researched extensively. Yet, the nature of the code(s) underlying sequence memory is still relatively unknown. Across 4 experiments that manipulated encoding task, we found evidence for 3 dissociable facets of order memory. Experiment 1 introduced a test requiring a judgment of which of 2 alternatives had immediately followed a word during encoding. This measure revealed better retention of interitem associations following relational encoding (silent reading) than relatively item-specific encoding (judging referent size), a pattern consistent with that observed in previous research using order reconstruction tests. In sharp contrast, Experiment 2 demonstrated the reverse pattern: Memory for the studied order of 2 sequentially presented items was actually better following item-specific encoding than following relational encoding. Experiment 3 reproduced this dissociation in a single experiment using both tests. Experiment 4 extended these findings by further dissociating the roles of relational encoding and item strength in the 2 tests. Taken together, these results indicate that memory for event sequence is influenced by (a) interitem associations, (b) the emphasized directionality of an association, and (c) an item's strength independent of other items. Memory for order is more complicated than has been portrayed in theories of memory and its nuances should be carefully considered when designing tests and models of temporal and relational memory. (PsycINFO Database Record (c) 2017 APA, all rights reserved).

Visual Memory in Methamphetamine Dependent Individuals: Deficient Strategic Control of Encoding and Retrieval

PubMed Central

Morgan, Erin E.; Woods, Steven Paul; Poquette, Amelia J.; Vigil, Ofilio; Heaton, Robert K.; Grant, Igor

2012-01-01

Objective Chronic use of methamphetamine (MA) has moderate effects on neurocognitive functions associated with frontal systems, including the executive aspects of verbal episodic memory. Extending this literature, the current study examined the effects of MA on visual episodic memory with the hypothesis that a profile of deficient strategic encoding and retrieval processes would be revealed for visuospatial information (i.e., simple geometric designs), including possible differential effects on source versus item recall. Method The sample comprised 114 MA-dependent (MA+) and 110 demographically-matched MA-nondependent comparison participants (MA−) who completed the Brief Visuospatial Memory Test – Revised (BVMT-R), which was scored for standard learning and memory indices, as well as novel item (i.e., figure) and source (i.e., location) memory indices. Results Results revealed a profile of impaired immediate and delayed free recall (p < .05) in the context of preserved learning slope, retention, and recognition discriminability in the MA+ group. The MA+ group also performed more poorly than MA− participants on Item visual memory (p < .05) but not Source visual memory (p > .05), and no group by task-type interaction was observed (p > .05). Item visual memory demonstrated significant associations with executive dysfunction, deficits in working memory, and shorter length of abstinence from MA use (p < 0.05). Conclusions These visual memory findings are commensurate with studies reporting deficient strategic verbal encoding and retrieval in MA users that are posited to reflect the vulnerability of frontostriatal circuits to the neurotoxic effects of MA. Potential clinical implications of these visual memory deficits are discussed. PMID:22311530

Demonstration of a shape memory alloy torque tube-based morphing radiator

NASA Astrophysics Data System (ADS)

Chong, Jorge B.; Walgren, Patrick; Hartl, Darren J.

2018-03-01

Long-distance crewed space exploration will require advanced thermal control systems (TCS) with the ability to handle a wide range of thermal loads. The ability of a TCS to adapt to the thermal environment is described by the turndown ratio. Developing radiators with high turndown ratios is critical for improving TCS technology. This paper describes a novel morphing radiator designed to achieve a high turndown ratio by varying its own radiative view factor and effective emissivity through the use of shape memory alloys (SMAs). This radiator features two SMA torque tubes cantilevered to a rigid fixture. The working fluid is transported within the SMA tubes through an annular flow system. In a cold environment, radiator panels fixed to the free ends of the tubes are oriented vertically in a parallel-plate fashion, where the high-emissivity interior faces have restricted views to the environment and heat rejection is minimized. When the system heats up, the tubes actuate by twisting in opposing directions, bringing the panels to a horizontal position with the interior faces exposed to maximize heat rejection. When the system cools down, the tubes twist in reverse, restoring the panels to the vertical orientation where heat rejection is again minimized. This variable heat rejection system has the potential for achieving higher turndown ratios than those of current state-of-the-art systems. A benchtop prototype has been designed and tested to demonstrate actuation and to explore internal heat transfer effects. Prototype design, testing, and results are herein described.

[Development of a video image system for wireless capsule endoscopes based on DSP].

PubMed

Yang, Li; Peng, Chenglin; Wu, Huafeng; Zhao, Dechun; Zhang, Jinhua

2008-02-01

A video image recorder to record video picture for wireless capsule endoscopes was designed. TMS320C6211 DSP of Texas Instruments Inc. is the core processor of this system. Images are periodically acquired from Composite Video Broadcast Signal (CVBS) source and scaled by video decoder (SAA7114H). Video data is transported from high speed buffer First-in First-out (FIFO) to Digital Signal Processor (DSP) under the control of Complex Programmable Logic Device (CPLD). This paper adopts JPEG algorithm for image coding, and the compressed data in DSP was stored to Compact Flash (CF) card. TMS320C6211 DSP is mainly used for image compression and data transporting. Fast Discrete Cosine Transform (DCT) algorithm and fast coefficient quantization algorithm are used to accelerate operation speed of DSP and decrease the executing code. At the same time, proper address is assigned for each memory, which has different speed;the memory structure is also optimized. In addition, this system uses plenty of Extended Direct Memory Access (EDMA) to transport and process image data, which results in stable and high performance.

Conscious and Unconscious Memory Systems

PubMed Central

Squire, Larry R.; Dede, Adam J.O.

2015-01-01

The idea that memory is not a single mental faculty has a long and interesting history but became a topic of experimental and biologic inquiry only in the mid-20th century. It is now clear that there are different kinds of memory, which are supported by different brain systems. One major distinction can be drawn between working memory and long-term memory. Long-term memory can be separated into declarative (explicit) memory and a collection of nondeclarative (implicit) forms of memory that include habits, skills, priming, and simple forms of conditioning. These memory systems depend variously on the hippocampus and related structures in the parahippocampal gyrus, as well as on the amygdala, the striatum, cerebellum, and the neocortex. This work recounts the discovery of declarative and nondeclarative memory and then describes the nature of declarative memory, working memory, nondeclarative memory, and the relationship between memory systems. PMID:25731765

Balance in machine architecture: Bandwidth on board and offboard, integer/control speed and flops versus memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fischler, M.

1992-04-01

The issues to be addressed here are those of balance'' in machine architecture. By this, we mean how much emphasis must be placed on various aspects of the system to maximize its usefulness for physics. There are three components that contribute to the utility of a system: How the machine can be used, how big a problem can be attacked, and what the effective capabilities (power) of the hardware are like. The effective power issue is a matter of evaluating the impact of design decisions trading off architectural features such as memory bandwidth and interprocessor communication capabilities. What is studiedmore » is the effect these machine parameters have on how quickly the system can solve desired problems. There is a reasonable method for studying this: One selects a few representative algorithms and computes the impact of changing memory bandwidths, and so forth. The only room for controversy here is in the selection of representative problems. The issue of how big a problem can be attacked boils down to a balance of memory size versus power. Although this is a balance issue it is very different than the effective power situation, because no firm answer can be given at this time. The power to memory ratio is highly problem dependent, and optimizing it requires several pieces of physics input, including: how big a lattice is needed for interesting results; what sort of algorithms are best to use; and how many sweeps are needed to get valid results. We seem to be at the threshold of learning things about these issues, but for now, the memory size issue will necessarily be addressed in terms of best guesses, rules of thumb, and researchers' opinions.« less

Balance in machine architecture: Bandwidth on board and offboard, integer/control speed and flops versus memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fischler, M.

1992-04-01

The issues to be addressed here are those of ``balance`` in machine architecture. By this, we mean how much emphasis must be placed on various aspects of the system to maximize its usefulness for physics. There are three components that contribute to the utility of a system: How the machine can be used, how big a problem can be attacked, and what the effective capabilities (power) of the hardware are like. The effective power issue is a matter of evaluating the impact of design decisions trading off architectural features such as memory bandwidth and interprocessor communication capabilities. What is studiedmore » is the effect these machine parameters have on how quickly the system can solve desired problems. There is a reasonable method for studying this: One selects a few representative algorithms and computes the impact of changing memory bandwidths, and so forth. The only room for controversy here is in the selection of representative problems. The issue of how big a problem can be attacked boils down to a balance of memory size versus power. Although this is a balance issue it is very different than the effective power situation, because no firm answer can be given at this time. The power to memory ratio is highly problem dependent, and optimizing it requires several pieces of physics input, including: how big a lattice is needed for interesting results; what sort of algorithms are best to use; and how many sweeps are needed to get valid results. We seem to be at the threshold of learning things about these issues, but for now, the memory size issue will necessarily be addressed in terms of best guesses, rules of thumb, and researchers` opinions.« less

Direct-write fabrication of 4D active shape-changing behavior based on a shape memory polymer and its nanocomposite (Conference Presentation)

NASA Astrophysics Data System (ADS)

Wei, Hongqiu; Zhang, Qiwei; Yao, Yongtao; Liu, Liwu; Liu, Yanju; Leng, Jinsong

2017-04-01

Shape memory polymers (SMPs), a typical class of smart materials, have been witnessed significant advances in the past decades. Based on the unique performance to recover the initial shape after going through a shape deformation, the applications of SMPs have aroused growing interests. However, most of the researches are hindered by traditional processing technologies which limit the design space of SMPs-based structures. Three-dimension (3D) printing as an emerging technology endows design freedom to manufacture materials with complex structures. In present article, we show that by employing direct-write printing method; one can realize the printing of SMPs to achieve 4D active shape-changing structures. We first fabricated a kind of 3D printable polylactide (PLA)-based SMPs and characterized the overall properties of such materials. Results demonstrated the prepared PLA-based SMPs presenting excellent shape memory effect. In what follows, the rheological properties of such PLA-based SMP ink during printing process were discussed in detail. Finally, we designed and printed several 3D configurations for investigation. By combining 3D printing with shape memory behavior, these printed structures achieve 4D active shape-changing performance under heat stimuli. This research presents a high flexible method to realize the fabrication of SMP-based 4D active shape-changing structures, which opens the way for further developments and improvements of high-tech fields like 4D printing, soft robotics, micro-systems and biomedical devices.

Loop-gap microwave resonator for hybrid quantum systems

NASA Astrophysics Data System (ADS)

Ball, Jason R.; Yamashiro, Yu; Sumiya, Hitoshi; Onoda, Shinobu; Ohshima, Takeshi; Isoya, Junichi; Konstantinov, Denis; Kubo, Yuimaru

2018-05-01

We designed a loop-gap microwave resonator for applications of spin-based hybrid quantum systems and tested it with impurity spins in diamond. Strong coupling with ensembles of nitrogen-vacancy (NV) centers and substitutional nitrogen (P1) centers was observed. These results show that loop-gap resonators are viable in the prospect of spin-based hybrid quantum systems, especially for an ensemble quantum memory or a quantum transducer.

Design of a Vertical Composite Thin Film System with Ultralow Leakage To Yield Large Converse Magnetoelectric Effect.

PubMed

Wu, Rui; Kursumovic, Ahmed; Gao, Xingyao; Yun, Chao; Vickers, Mary E; Wang, Haiyan; Cho, Seungho; MacManus-Driscoll, Judith L

2018-05-30

Electric field control of magnetism is a critical future technology for low-power, ultrahigh density memory. However, despite intensive research efforts, no practical material systems have emerged. Interface-coupled, composite systems containing ferroelectric and ferri-/ferromagnetic elements have been widely explored, but they have a range of problems, for example, substrate clamping, large leakage, and inability to miniaturize. In this work, through careful material selection, design, and nanoengineering, a high-performance room-temperature magnetoelectric system is demonstrated. The clamping problem is overcome by using a vertically aligned nanocomposite structure in which the strain coupling is independent of the substrate. To overcome the leakage problem, three key novel advances are introduced: a low leakage ferroelectric, Na 0.5 Bi 0.5 TiO 3 ; ferroelectric-ferrimagnetic vertical interfaces which are not conducting; and current blockage via a rectifying interface between the film and the Nb-doped SrTiO 3 substrate. The new multiferroic nanocomposite (Na 0.5 Bi 0.5 TiO 3 -CoFe 2 O 4 ) thin-film system enables, for the first time, large-scale in situ electric field control of magnetic anisotropy at room temperature in a system applicable for magnetoelectric random access memory, with a magnetoelectric coefficient of 1.25 × 10 -9 s m -1 .

Acute Effects of Ecstasy on Memory Are more Extensive than Chronic Effects

PubMed Central

Shariati, Mohamad Bakhtiar Hesam; Sohrabi, Maryam; Shahidi, Siamak; Nikkhah, Ali; Mirzaei, Fatemeh; Medizadeh, Mehdi; Asl, Sara Soleimani

2014-01-01

Introduction Exposure to 3, 4- methylenedioxymethamphetamine (MDMA) could lead to serotonergic system toxicity in the brain. This system is responsible for learning and memory functions. Studies show that MDMA causes memory impairment dose-dependently and acutely. The present study was designed to evaluate the chronic and acute effects of MDMD on spatial memory and acquisition of passive avoidance. Methods Adult male Wistar rats (200-250 g) were given single or multiple injections of MDMA (10 mg/kg, IP). Using passive avoidance and Morris Water Maze (MWM) tasks, learning and spatial memory functions were assessed. The data were analyzed by SPSS 16 software and one- way analysis of variance (ANOVA) test. Results Our results showed that there were significant differences in latency to enter the dark compartment (STL) between sham and MDMA- treated groups. Acute group significantly showed more STL in comparison with chronic group. Furthermore, MDMA groups spent more time in dark compartment (TDS) than the sham group. Administration of single dose of MDMA significantly caused an increase in TDS compared with the chronic group. In the MWM, MDMA treatment significantly increased the traveled distance and escaped latency compared to the sham group. Like to passive avoidance task, percentage of time spent in the target quadrant in MDMA- treated animals impaired in MWM compared with sham group. Discussion These data suggest that MDMA treatment impairs learning and memory functions that are more extensive in acute- treated rats. PMID:25337384

Norms for healthy adults aged 18-87 years for the Cognitive Drug Research System: An automated set of tests of attention, information processing and memory for use in clinical trials.

PubMed

Wesnes, Keith A; McNamara, Cynthia; Annas, Peter

2016-03-01

The Cognitive Drug Research (CDR) System is a set of nine computerized tests of attention, information processing, working memory, executive control and episodic memory which was designed for repeated assessments in research projects. The CDR System has been used extensively in clinical trials involving healthy volunteers for over 30 years, and a database of 7751 individuals aged 18-87 years has been accumulated for pre-treatment data from these studies. This database has been analysed, and the relationships between the various scores with factors, including age, gender and years of full-time education, have been identified. These analyses are reported in this paper, along with tables of norms for the various key measures from the core tasks stratified by age and gender. These norms can be used for a variety of purposes, including the determination of eligibility for participation in clinical trials and the everyday relevance of research findings from the system. In addition, these norms provide valuable information on gender differences and the effects of normal ageing on major aspects of human cognitive function. © The Author(s) 2016.

Sptrace

NASA Technical Reports Server (NTRS)

Burleigh, Scott C.

2011-01-01

Sptrace is a general-purpose space utilization tracing system that is conceptually similar to the commercial Purify product used to detect leaks and other memory usage errors. It is designed to monitor space utilization in any sort of heap, i.e., a region of data storage on some device (nominally memory; possibly shared and possibly persistent) with a flat address space. This software can trace usage of shared and/or non-volatile storage in addition to private RAM (random access memory). Sptrace is implemented as a set of C function calls that are invoked from within the software that is being examined. The function calls fall into two broad classes: (1) functions that are embedded within the heap management software [e.g., JPL's SDR (Simple Data Recorder) and PSM (Personal Space Management) systems] to enable heap usage analysis by populating a virtual time-sequenced log of usage activity, and (2) reporting functions that are embedded within the application program whose behavior is suspect. For ease of use, these functions may be wrapped privately inside public functions offered by the heap management software. Sptrace can be used for VxWorks or RTEMS realtime systems as easily as for Linux or OS/X systems.

Development of an Integrated Data Acquisition System for a Small Flight Probe

NASA Technical Reports Server (NTRS)

Swanson, Gregory T.; Empey, Daniel M.; Skokova, Kristina A.; Venkatapathy, Ethiraj

2012-01-01

In support of the SPRITE concept, an integrated data acquisition system has been developed and fabricated for preliminary testing. The data acquisition system has been designed to condition traditional thermal protection system sensors, store their data to an on-board memory card, and in parallel, telemeter to an external system. In the fall of 2010, this system was integrated into a 14 in. diameter, 45 degree sphere cone probe instrumented with thermal protection system sensors. This system was then tested at the NASA Ames Research Center Aerodynamic Heating Facility's arc jet at approximately 170 W/sq. cm. The first test in December 2010 highlighted hardware design issues that were redesigned and implemented leading to a successful test in February 2011.

Multi-sensor Array for High Altitude Balloon Missions to the Stratosphere

NASA Astrophysics Data System (ADS)

Davis, Tim; McClurg, Bryce; Sohl, John

2008-10-01

We have designed and built a microprocessor controlled and expandable multi-sensor array for data collection on near space missions. Weber State University has started a high altitude research balloon program called HARBOR. This array has been designed to data log a base set of measurements for every flight and has room for six guest instruments. The base measurements are absolute pressure, on-board temperature, 3-axis accelerometer for attitude measurement, and 2-axis compensated magnetic compass. The system also contains a real time clock and circuitry for logging data directly to a USB memory stick. In typical operation the measurements will be cycled through in sequence and saved to the memory stick along with the clock's time stamp. The microprocessor can be reprogrammed to adapt to guest experiments with either analog or digital interfacing. This system will fly with every mission and will provide backup data collection for other instrumentation for which the primary task is measuring atmospheric pressure and temperature. The attitude data will be used to determine the orientation of the onboard camera systems to aid in identifying features in the images. This will make these images easier to use for any future GIS (geographic information system) remote sensing missions.

Rapid prototyping prosthetic hand acting by a low-cost shape-memory-alloy actuator.

PubMed

Soriano-Heras, Enrique; Blaya-Haro, Fernando; Molino, Carlos; de Agustín Del Burgo, José María

2018-06-01

The purpose of this article is to develop a new concept of modular and operative prosthetic hand based on rapid prototyping and a novel shape-memory-alloy (SMA) actuator, thus minimizing the manufacturing costs. An underactuated mechanism was needed for the design of the prosthesis to use only one input source. Taking into account the state of the art, an underactuated mechanism prosthetic hand was chosen so as to implement the modifications required for including the external SMA actuator. A modular design of a new prosthesis was developed which incorporated a novel SMA actuator for the index finger movement. The primary objective of the prosthesis is achieved, obtaining a modular and functional low-cost prosthesis based on additive manufacturing executed by a novel SMA actuator. The external SMA actuator provides a modular system which allows implementing it in different systems. This paper combines rapid prototyping and a novel SMA actuator to develop a new concept of modular and operative low-cost prosthetic hand.

76 FR 32986 - National Capital Memorial Advisory Commission Meeting

Federal Register 2010, 2011, 2012, 2013, 2014

2011-06-07

.... (b) S. 253 and H.R. 938, bills to establish a World War I National Memorial Commission and reestablish the District of Columbia World War Memorial as the National World War I Memorial. (c) S. 883, a... is as follows: (1) Memorial to American Veterans Disabled for Life--Design presentation. (2) Memorial...

Flash memory management system and method utilizing multiple block list windows

NASA Technical Reports Server (NTRS)

Chow, James (Inventor); Gender, Thomas K. (Inventor)

2005-01-01

The present invention provides a flash memory management system and method with increased performance. The flash memory management system provides the ability to efficiently manage and allocate flash memory use in a way that improves reliability and longevity, while maintaining good performance levels. The flash memory management system includes a free block mechanism, a disk maintenance mechanism, and a bad block detection mechanism. The free block mechanism provides efficient sorting of free blocks to facilitate selecting low use blocks for writing. The disk maintenance mechanism provides for the ability to efficiently clean flash memory blocks during processor idle times. The bad block detection mechanism provides the ability to better detect when a block of flash memory is likely to go bad. The flash status mechanism stores information in fast access memory that describes the content and status of the data in the flash disk. The new bank detection mechanism provides the ability to automatically detect when new banks of flash memory are added to the system. Together, these mechanisms provide a flash memory management system that can improve the operational efficiency of systems that utilize flash memory.

Design of on-board parallel computer on nano-satellite

NASA Astrophysics Data System (ADS)

You, Zheng; Tian, Hexiang; Yu, Shijie; Meng, Li

2007-11-01

This paper provides one scheme of the on-board parallel computer system designed for the Nano-satellite. Based on the development request that the Nano-satellite should have a small volume, low weight, low power cost, and intelligence, this scheme gets rid of the traditional one-computer system and dual-computer system with endeavor to improve the dependability, capability and intelligence simultaneously. According to the method of integration design, it employs the parallel computer system with shared memory as the main structure, connects the telemetric system, attitude control system, and the payload system by the intelligent bus, designs the management which can deal with the static tasks and dynamic task-scheduling, protect and recover the on-site status and so forth in light of the parallel algorithms, and establishes the fault diagnosis, restoration and system restructure mechanism. It accomplishes an on-board parallel computer system with high dependability, capability and intelligence, a flexible management on hardware resources, an excellent software system, and a high ability in extension, which satisfies with the conception and the tendency of the integration electronic design sufficiently.

Propulsion/flight control integration technology (PROFIT) design analysis status

NASA Technical Reports Server (NTRS)

Carlin, C. M.; Hastings, W. J.

1978-01-01

The propulsion flight control integration technology (PROFIT) program was designed to develop a flying testbed dedicated to controls research. The preliminary design, analysis, and feasibility studies conducted in support of the PROFIT program are reported. The PROFIT system was built around existing IPCS hardware. In order to achieve the desired system flexibility and capability, additional interfaces between the IPCS hardware and F-15 systems were required. The requirements for additions and modifications to the existing hardware were defined. Those interfaces involving the more significant changes were studied. The DCU memory expansion to 32K with flight qualified hardware was completed on a brassboard basis. The uplink interface breadboard and a brassboard of the central computer interface were also tested. Two preliminary designs and corresponding program plans are presented.

Configurable memory system and method for providing atomic counting operations in a memory device

DOEpatents

Bellofatto, Ralph E.; Gara, Alan G.; Giampapa, Mark E.; Ohmacht, Martin

2010-09-14

A memory system and method for providing atomic memory-based counter operations to operating systems and applications that make most efficient use of counter-backing memory and virtual and physical address space, while simplifying operating system memory management, and enabling the counter-backing memory to be used for purposes other than counter-backing storage when desired. The encoding and address decoding enabled by the invention provides all this functionality through a combination of software and hardware.

Digital analyzer for point processes based on first-in-first-out memories

NASA Astrophysics Data System (ADS)

Basano, Lorenzo; Ottonello, Pasquale; Schiavi, Enore

1992-06-01

We present an entirely new version of a multipurpose instrument designed for the statistical analysis of point processes, especially those characterized by high bunching. A long sequence of pulses can be recorded in the RAM bank of a personal computer via a suitably designed front end which employs a pair of first-in-first-out (FIFO) memories; these allow one to build an analyzer that, besides being simpler from the electronic point of view, is capable of sustaining much higher intensity fluctuations of the point process. The overflow risk of the device is evaluated by treating the FIFO pair as a queueing system. The apparatus was tested using both a deterministic signal and a sequence of photoelectrons obtained from laser light scattered by random surfaces.

Implications of the Turing machine model of computation for processor and programming language design

NASA Astrophysics Data System (ADS)

Hunter, Geoffrey

2004-01-01

A computational process is classified according to the theoretical model that is capable of executing it; computational processes that require a non-predeterminable amount of intermediate storage for their execution are Turing-machine (TM) processes, while those whose storage are predeterminable are Finite Automation (FA) processes. Simple processes (such as traffic light controller) are executable by Finite Automation, whereas the most general kind of computation requires a Turing Machine for its execution. This implies that a TM process must have a non-predeterminable amount of memory allocated to it at intermediate instants of its execution; i.e. dynamic memory allocation. Many processes encountered in practice are TM processes. The implication for computational practice is that the hardware (CPU) architecture and its operating system must facilitate dynamic memory allocation, and that the programming language used to specify TM processes must have statements with the semantic attribute of dynamic memory allocation, for in Alan Turing"s thesis on computation (1936) the "standard description" of a process is invariant over the most general data that the process is designed to process; i.e. the program describing the process should never have to be modified to allow for differences in the data that is to be processed in different instantiations; i.e. data-invariant programming. Any non-trivial program is partitioned into sub-programs (procedures, subroutines, functions, modules, etc). Examination of the calls/returns between the subprograms reveals that they are nodes in a tree-structure; this tree-structure is independent of the programming language used to encode (define) the process. Each sub-program typically needs some memory for its own use (to store values intermediate between its received data and its computed results); this locally required memory is not needed before the subprogram commences execution, and it is not needed after its execution terminates; it may be allocated as its execution commences, and deallocated as its execution terminates, and if the amount of this local memory is not known until just before execution commencement, then it is essential that it be allocated dynamically as the first action of its execution. This dynamically allocated/deallocated storage of each subprogram"s intermediate values, conforms with the stack discipline; i.e. last allocated = first to be deallocated, an incidental benefit of which is automatic overlaying of variables. This stack-based dynamic memory allocation was a semantic implication of the nested block structure that originated in the ALGOL-60 programming language. AGLOL-60 was a TM language, because the amount of memory allocated on subprogram (block/procedure) entry (for arrays, etc) was computable at execution time. A more general requirement of a Turing machine process is for code generation at run-time; this mandates access to the source language processor (compiler/interpretor) during execution of the process. This fundamental aspect of computer science is important to the future of system design, because it has been overlooked throughout the 55 years since modern computing began in 1048. The popular computer systems of this first half-century of computing were constrained by compile-time (or even operating system boot-time) memory allocation, and were thus limited to executing FA processes. The practical effect was that the distinction between the data-invariant program and its variable data was blurred; programmers had to make trial and error executions, modifying the program"s compile-time constants (array dimensions) to iterate towards the values required at run-time by the data being processed. This era of trial and error computing still persists; it pervades the culture of current (2003) computing practice.

The scheme machine: A case study in progress in design derivation at system levels

NASA Technical Reports Server (NTRS)

Johnson, Steven D.

1995-01-01

The Scheme Machine is one of several design projects of the Digital Design Derivation group at Indiana University. It differs from the other projects in its focus on issues of system design and its connection to surrounding research in programming language semantics, compiler construction, and programming methodology underway at Indiana and elsewhere. The genesis of the project dates to the early 1980's, when digital design derivation research branched from the surrounding research effort in programming languages. Both branches have continued to develop in parallel, with this particular project serving as a bridge. However, by 1990 there remained little real interaction between the branches and recently we have undertaken to reintegrate them. On the software side, researchers have refined a mathematically rigorous (but not mechanized) treatment starting with the fully abstract semantic definition of Scheme and resulting in an efficient implementation consisting of a compiler and virtual machine model, the latter typically realized with a general purpose microprocessor. The derivation includes a number of sophisticated factorizations and representations and is also deep example of the underlying engineering methodology. The hardware research has created a mechanized algebra supporting the tedious and massive transformations often seen at lower levels of design. This work has progressed to the point that large scale devices, such as processors, can be derived from first-order finite state machine specifications. This is roughly where the language oriented research stops; thus, together, the two efforts establish a thread from the highest levels of abstract specification to detailed digital implementation. The Scheme Machine project challenges hardware derivation research in several ways, although the individual components of the system are of a similar scale to those we have worked with before. The machine has a custom dual-ported memory to support garbage collection. It consists of four tightly coupled processes--processor, collector, allocator, memory--with a very non-trivial synchronization relationship. Finally, there are deep issues of representation for the run-time objects of a symbolic processing language. The research centers on verification through integrated formal reasoning systems, but is also involved with modeling and prototyping environments. Since the derivation algebra is basd on an executable modeling language, there is opportunity to incorporate design animation in the design process. We are looking for ways to move smoothly and incrementally from executable specifications into hardware realization. For example, we can run the garbage collector specification, a Scheme program, directly against the physical memory prototype, and similarly, the instruction processor model against the heap implementation.

Building a Terabyte Memory Bandwidth Compute Node with Four Consumer Electronics GPUs

NASA Astrophysics Data System (ADS)

Omlin, Samuel; Räss, Ludovic; Podladchikov, Yuri

2014-05-01

GPUs released for consumer electronics are generally built with the same chip architectures as the GPUs released for professional usage. With regards to scientific computing, there are no obvious important differences in functionality or performance between the two types of releases, yet the price can differ up to one order of magnitude. For example, the consumer electronics release of the most recent NVIDIA Kepler architecture (GK110), named GeForce GTX TITAN, performed equally well in conducted memory bandwidth tests as the professional release, named Tesla K20; the consumer electronics release costs about one third of the professional release. We explain how to design and assemble a well adjusted computer with four high-end consumer electronics GPUs (GeForce GTX TITAN) combining more than 1 terabyte/s memory bandwidth. We compare the system's performance and precision with the one of hardware released for professional usage. The system can be used as a powerful workstation for scientific computing or as a compute node in a home-built GPU cluster.

The MNESIS model: Memory systems and processes, identity and future thinking.

PubMed

Eustache, Francis; Viard, Armelle; Desgranges, Béatrice

2016-07-01

The Memory NEo-Structural Inter-Systemic model (MNESIS; Eustache and Desgranges, Neuropsychology Review, 2008) is a macromodel based on neuropsychological data which presents an interactive construction of memory systems and processes. Largely inspired by Tulving's SPI model, MNESIS puts the emphasis on the existence of different memory systems in humans and their reciprocal relations, adding new aspects, such as the episodic buffer proposed by Baddeley. The more integrative comprehension of brain dynamics offered by neuroimaging has contributed to rethinking the existence of memory systems. In the present article, we will argue that understanding the concept of memory by dividing it into systems at the functional level is still valid, but needs to be considered in the light of brain imaging. Here, we reinstate the importance of this division in different memory systems and illustrate, with neuroimaging findings, the links that operate between memory systems in response to task demands that constrain the brain dynamics. During a cognitive task, these memory systems interact transiently to rapidly assemble representations and mobilize functions to propose a flexible and adaptative response. We will concentrate on two memory systems, episodic and semantic memory, and their links with autobiographical memory. More precisely, we will focus on interactions between episodic and semantic memory systems in support of 1) self-identity in healthy aging and in brain pathologies and 2) the concept of the prospective brain during future projection. In conclusion, this MNESIS global framework may help to get a general representation of human memory and its brain implementation with its specific components which are in constant interaction during cognitive processes. Copyright © 2016 Elsevier Ltd. All rights reserved.

Performance Study of the First 2D Prototype of Vertically Integrated Pattern Recognition Associative Memory (VIPRAM)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deptuch, Gregory; Hoff, James; Jindariani, Sergo

Extremely fast pattern recognition capabilities are necessary to find and fit billions of tracks at the hardware trigger level produced every second anticipated at high luminosity LHC (HL-LHC) running conditions. Associative Memory (AM) based approaches for fast pattern recognition have been proposed as a potential solution to the tracking trigger. However, at the HL-LHC, there is much less time available and speed performance must be improved over previous systems while maintaining a comparable number of patterns. The Vertically Integrated Pattern Recognition Associative Memory (VIPRAM) Project aims to achieve the target pattern density and performance goal using 3DIC technology. The firstmore » step taken in the VIPRAM work was the development of a 2D prototype (protoVIPRAM00) in which the associative memory building blocks were designed to be compatible with the 3D integration. In this paper, we present the results from extensive performance studies of the protoVIPRAM00 chip in both realistic HL-LHC and extreme conditions. Results indicate that the chip operates at the design frequency of 100 MHz with perfect correctness in realistic conditions and conclude that the building blocks are ready for 3D stacking. We also present performance boundary characterization of the chip under extreme conditions.« less

Raster Scan Computer Image Generation (CIG) System Based On Refresh Memory

NASA Astrophysics Data System (ADS)

Dichter, W.; Doris, K.; Conkling, C.

1982-06-01

A full color, Computer Image Generation (CIG) raster visual system has been developed which provides a high level of training sophistication by utilizing advanced semiconductor technology and innovative hardware and firmware techniques. Double buffered refresh memory and efficient algorithms eliminate the problem of conventional raster line ordering by allowing the generated image to be stored in a random fashion. Modular design techniques and simplified architecture provide significant advantages in reduced system cost, standardization of parts, and high reliability. The major system components are a general purpose computer to perform interfacing and data base functions; a geometric processor to define the instantaneous scene image; a display generator to convert the image to a video signal; an illumination control unit which provides final image processing; and a CRT monitor for display of the completed image. Additional optional enhancements include texture generators, increased edge and occultation capability, curved surface shading, and data base extensions.

Longitudinal association between hippocampus atrophy and episodic-memory decline.

PubMed

Gorbach, Tetiana; Pudas, Sara; Lundquist, Anders; Orädd, Greger; Josefsson, Maria; Salami, Alireza; de Luna, Xavier; Nyberg, Lars

2017-03-01

There is marked variability in both onset and rate of episodic-memory decline in aging. Structural magnetic resonance imaging studies have revealed that the extent of age-related brain changes varies markedly across individuals. Past studies of whether regional atrophy accounts for episodic-memory decline in aging have yielded inconclusive findings. Here we related 15-year changes in episodic memory to 4-year changes in cortical and subcortical gray matter volume and in white-matter connectivity and lesions. In addition, changes in word fluency, fluid IQ (Block Design), and processing speed were estimated and related to structural brain changes. Significant negative change over time was observed for all cognitive and brain measures. A robust brain-cognition change-change association was observed for episodic-memory decline and atrophy in the hippocampus. This association was significant for older (65-80 years) but not middle-aged (55-60 years) participants and not sensitive to the assumption of ignorable attrition. Thus, these longitudinal findings highlight medial-temporal lobe system integrity as particularly crucial for maintaining episodic-memory functioning in older age. Copyright © 2016 The Authors. Published by Elsevier Inc. All rights reserved.

Technical and economic assessment of design efficiency of information and measuring systems

NASA Astrophysics Data System (ADS)

Yurov, V. M.; Eremin, E. N.; Baisagov, Ya Zh; Arkhipov, V. V.

2018-01-01

A thermodynamic approach to the analysis of information-measuring systems (IMS) is developed in the work. Expressions for efficiency of IMS are obtained. The connection between the amount of processor memory and the amount of incoming information and the accuracy of the IMS is obtained. It is shown that the probability of information loss in IMS decreases with the increase in the amount of information from the object. Using the analogy method, economic aspects of IMS design are considered. The innate ability of IMS and Moore’s law are considered. The proposed approach and the resulting formulas will be useful in the design of new IMS.

Minimizing the Disruptive Effects of Prospective Memory in Simulated Air Traffic Control

PubMed Central

Loft, Shayne; Smith, Rebekah E.; Remington, Roger

2015-01-01

Prospective memory refers to remembering to perform an intended action in the future. Failures of prospective memory can occur in air traffic control. In two experiments, we examined the utility of external aids for facilitating air traffic management in a simulated air traffic control task with prospective memory requirements. Participants accepted and handed-off aircraft and detected aircraft conflicts. The prospective memory task involved remembering to deviate from a routine operating procedure when accepting target aircraft. External aids that contained details of the prospective memory task appeared and flashed when target aircraft needed acceptance. In Experiment 1, external aids presented either adjacent or non-adjacent to each of the 20 target aircraft presented over the 40min test phase reduced prospective memory error by 11% compared to a condition without external aids. In Experiment 2, only a single target aircraft was presented a significant time (39min–42min) after presentation of the prospective memory instruction, and the external aids reduced prospective memory error by 34%. In both experiments, costs to the efficiency of non-prospective memory air traffic management (non-target aircraft acceptance response time, conflict detection response time) were reduced by non-adjacent aids compared to no aids or adjacent aids. In contrast, in both experiments, the efficiency of the prospective memory air traffic management (target aircraft acceptance response time) was facilitated by adjacent aids compared to non-adjacent aids. Together, these findings have potential implications for the design of automated alerting systems to maximize multi-task performance in work settings where operators monitor and control demanding perceptual displays. PMID:24059825

Can false memories be created through nonconscious processes?

PubMed

Zeelenberg, René; Plomp, Gijs; Raaijmakers, Jeroen G W

2003-09-01

Presentation times of study words presented in the Deese/Roediger and McDermott (DRM) paradigm varied from 20 to 2000 ms per word in an attempt to replicate the false memory effect following extremely short presentations reported by. Both in a within-subjects design (Experiment 1) and in a between-subjects design (Experiment 2) subjects showed memory for studied words as well as a false memory effect for related critical lures in the 2000-ms condition. However, in the conditions with shorter presentation times (20 ms in Experiment 1; 20 and 40 ms in Experiment 2) no memory for studied words, nor a false memory effect was found. We argue that there is at present no strong evidence supporting the claim for a nonconscious basis of the false memory effect.

The design and testing of a memory metal actuated boom release mechanism

NASA Technical Reports Server (NTRS)

Powley, D. G.; Brook, G. B.

1979-01-01

A boom latch and release mechanism was designed, manufactured and tested, based on a specification for the ISEE-B satellite mechanism. From experimental results obtained, it is possible to calculate the energy available and the operating torques which can be achieved from a torsional shape memory element in terms of the reversible strain induced by prior working. Some guidelines to be followed when designing mechanisms actuated by shape memory elements are included.

Design of Cyber Attack Precursor Symptom Detection Algorithm through System Base Behavior Analysis and Memory Monitoring

NASA Astrophysics Data System (ADS)

Jung, Sungmo; Kim, Jong Hyun; Cagalaban, Giovanni; Lim, Ji-Hoon; Kim, Seoksoo

More recently, botnet-based cyber attacks, including a spam mail or a DDos attack, have sharply increased, which poses a fatal threat to Internet services. At present, antivirus businesses make it top priority to detect malicious code in the shortest time possible (Lv.2), based on the graph showing a relation between spread of malicious code and time, which allows them to detect after malicious code occurs. Despite early detection, however, it is not possible to prevent malicious code from occurring. Thus, we have developed an algorithm that can detect precursor symptoms at Lv.1 to prevent a cyber attack using an evasion method of 'an executing environment aware attack' by analyzing system behaviors and monitoring memory.

Multiple Memory Systems Are Unnecessary to Account for Infant Memory Development: An Ecological Model

ERIC Educational Resources Information Center

Rovee-Collier, Carolyn; Cuevas, Kimberly

2009-01-01

How the memory of adults evolves from the memory abilities of infants is a central problem in cognitive development. The popular solution holds that the multiple memory systems of adults mature at different rates during infancy. The "early-maturing system" (implicit or nondeclarative memory) functions automatically from birth, whereas the…

Experimental Studies on Dynamic Vibration Absorber using Shape Memory Alloy (NiTi) Springs

NASA Astrophysics Data System (ADS)

Kumar, V. Raj; Kumar, M. B. Bharathi Raj; Kumar, M. Senthil

2011-10-01

Shape memory alloy (SMA) springs have been used as actuators in many applications although their use in the vibration control area is very recent. Since shape memory alloys differ from conventional alloy materials in many ways, the traditional design approach for springs is not completely suitable for designing SMA springs. Some vibration control concepts utilizing unique characteristics of SMA's will be presented in this paper. A dynamic vibration absorber (DVA) using shape memory alloy (SMA) actuator is developed for attenuation of vibration in a cantilever beam. The design procedure of the DVA is presented. The system consists of a cantilever beam which is considered to generate the real-time vibration using shaker. A SMA spring is used with a mass attached to its end. The stiffness of the SMA spring is dynamically varied in such a way to attenuate the vibration. Both simulation and experimentation are carried out using PID controller. The experiments were carried out by interfacing the experimental setup with a computer using LabVIEW software, Data acquisition and control are implemented using a PCI data acquisition card. Standard PID controllers have been used to control the vibration of the beam. Experimental results are used to demonstrate the effectiveness of the controllers designed and the usefulness of the proposed test platform by exciting the structure at resonance. In experimental setup, an accelerometer is used to measure the vibration which is fed to computer and correspondingly the SMA spring is actuated to change its stiffness to control the vibration. The results obtained illustrate that the developed DVA using SMA actuator is very effective in reducing structural response and have great potential to be an active vibration control medium.

Experimental Studies on Dynamic Vibration Absorber using Shape Memory Alloy (NiTi) Springs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, V. Raj; Kumar, M. B. Bharathi Raj; Kumar, M. Senthil

2011-10-20

Shape memory alloy (SMA) springs have been used as actuators in many applications although their use in the vibration control area is very recent. Since shape memory alloys differ from conventional alloy materials in many ways, the traditional design approach for springs is not completely suitable for designing SMA springs. Some vibration control concepts utilizing unique characteristics of SMA's will be presented in this paper.A dynamic vibration absorber (DVA) using shape memory alloy (SMA) actuator is developed for attenuation of vibration in a cantilever beam. The design procedure of the DVA is presented. The system consists of a cantilever beammore » which is considered to generate the real-time vibration using shaker. A SMA spring is used with a mass attached to its end. The stiffness of the SMA spring is dynamically varied in such a way to attenuate the vibration. Both simulation and experimentation are carried out using PID controller. The experiments were carried out by interfacing the experimental setup with a computer using LabVIEW software, Data acquisition and control are implemented using a PCI data acquisition card. Standard PID controllers have been used to control the vibration of the beam. Experimental results are used to demonstrate the effectiveness of the controllers designed and the usefulness of the proposed test platform by exciting the structure at resonance. In experimental setup, an accelerometer is used to measure the vibration which is fed to computer and correspondingly the SMA spring is actuated to change its stiffness to control the vibration. The results obtained illustrate that the developed DVA using SMA actuator is very effective in reducing structural response and have great potential to be an active vibration control medium.« less

An Efficient Multiblock Method for Aerodynamic Analysis and Design on Distributed Memory Systems

NASA Technical Reports Server (NTRS)

Reuther, James; Alonso, Juan Jose; Vassberg, John C.; Jameson, Antony; Martinelli, Luigi

1997-01-01

The work presented in this paper describes the application of a multiblock gridding strategy to the solution of aerodynamic design optimization problems involving complex configurations. The design process is parallelized using the MPI (Message Passing Interface) Standard such that it can be efficiently run on a variety of distributed memory systems ranging from traditional parallel computers to networks of workstations. Substantial improvements to the parallel performance of the baseline method are presented, with particular attention to their impact on the scalability of the program as a function of the mesh size. Drag minimization calculations at a fixed coefficient of lift are presented for a business jet configuration that includes the wing, body, pylon, aft-mounted nacelle, and vertical and horizontal tails. An aerodynamic design optimization is performed with both the Euler and Reynolds Averaged Navier-Stokes (RANS) equations governing the flow solution and the results are compared. These sample calculations establish the feasibility of efficient aerodynamic optimization of complete aircraft configurations using the RANS equations as the flow model. There still exists, however, the need for detailed studies of the importance of a true viscous adjoint method which holds the promise of tackling the minimization of not only the wave and induced components of drag, but also the viscous drag.

A Neural Network Architecture For Rapid Model Indexing In Computer Vision Systems

NASA Astrophysics Data System (ADS)

Pawlicki, Ted

1988-03-01

Models of objects stored in memory have been shown to be useful for guiding the processing of computer vision systems. A major consideration in such systems, however, is how stored models are initially accessed and indexed by the system. As the number of stored models increases, the time required to search memory for the correct model becomes high. Parallel distributed, connectionist, neural networks' have been shown to have appealing content addressable memory properties. This paper discusses an architecture for efficient storage and reference of model memories stored as stable patterns of activity in a parallel, distributed, connectionist, neural network. The emergent properties of content addressability and resistance to noise are exploited to perform indexing of the appropriate object centered model from image centered primitives. The system consists of three network modules each of which represent information relative to a different frame of reference. The model memory network is a large state space vector where fields in the vector correspond to ordered component objects and relative, object based spatial relationships between the component objects. The component assertion network represents evidence about the existence of object primitives in the input image. It establishes local frames of reference for object primitives relative to the image based frame of reference. The spatial relationship constraint network is an intermediate representation which enables the association between the object based and the image based frames of reference. This intermediate level represents information about possible object orderings and establishes relative spatial relationships from the image based information in the component assertion network below. It is also constrained by the lawful object orderings in the model memory network above. The system design is consistent with current psychological theories of recognition by component. It also seems to support Marr's notions of hierarchical indexing. (i.e. the specificity, adjunct, and parent indices) It supports the notion that multiple canonical views of an object may have to be stored in memory to enable its efficient identification. The use of variable fields in the state space vectors appears to keep the number of required nodes in the network down to a tractable number while imposing a semantic value on different areas of the state space. This semantic imposition supports an interface between the analogical aspects of neural networks and the propositional paradigms of symbolic processing.

Method for refreshing a non-volatile memory

DOEpatents

Riekels, James E.; Schlesinger, Samuel

2008-11-04

A non-volatile memory and a method of refreshing a memory are described. The method includes allowing an external system to control refreshing operations within the memory. The memory may generate a refresh request signal and transmit the refresh request signal to the external system. When the external system finds an available time to process the refresh request, the external system acknowledges the refresh request and transmits a refresh acknowledge signal to the memory. The memory may also comprise a page register for reading and rewriting a data state back to the memory. The page register may comprise latches in lieu of supplemental non-volatile storage elements, thereby conserving real estate within the memory.

Design and implementation of highly parallel pipelined VLSI systems

NASA Astrophysics Data System (ADS)

Delange, Alphonsus Anthonius Jozef

A methodology and its realization as a prototype CAD (Computer Aided Design) system for the design and analysis of complex multiprocessor systems is presented. The design is an iterative process in which the behavioral specifications of the system components are refined into structural descriptions consisting of interconnections and lower level components etc. A model for the representation and analysis of multiprocessor systems at several levels of abstraction and an implementation of a CAD system based on this model are described. A high level design language, an object oriented development kit for tool design, a design data management system, and design and analysis tools such as a high level simulator and graphics design interface which are integrated into the prototype system and graphics interface are described. Procedures for the synthesis of semiregular processor arrays, and to compute the switching of input/output signals, memory management and control of processor array, and sequencing and segmentation of input/output data streams due to partitioning and clustering of the processor array during the subsequent synthesis steps, are described. The architecture and control of a parallel system is designed and each component mapped to a module or module generator in a symbolic layout library, compacted for design rules of VLSI (Very Large Scale Integration) technology. An example of the design of a processor that is a useful building block for highly parallel pipelined systems in the signal/image processing domains is given.

Mental time travel and the shaping of language.

PubMed

Corballis, Michael C

2009-01-01

Episodic memory can be regarded as part of a more general system, unique to humans, for mental time travel, and the construction of future episodes. This allows more detailed planning than is afforded by the more general mechanisms of instinct, learning, and semantic memory. To be useful, episodic memory need not provide a complete or even a faithful record of past events, and may even be part of a process whereby we construct fictional accounts. The properties of language are aptly designed for the communication and sharing of episodes, and for the telling of stories; these properties include symbolic representation of the elements of real-world events, time markers, and combinatorial rules. Language and mental time travel probably co-evolved during the Pleistocene, when brain size increased dramatically.

Design and performance of a large vocabulary discrete word recognition system. Volume 2: Appendixes. [flow charts and users manual

NASA Technical Reports Server (NTRS)

1973-01-01

The users manual for the word recognition computer program contains flow charts of the logical diagram, the memory map for templates, the speech analyzer card arrangement, minicomputer input/output routines, and assembly language program listings.

Thermomechanical Analysis of Shape-Memory Composite Tape Spring

NASA Astrophysics Data System (ADS)

Yang, H.; Wang, L. Y.

2013-06-01

Intelligent materials and structures have been extensively applied for satellite designs in order to minimize the mass and reduce the cost in the launch of the spacecraft. Elastic memory composites (EMCs) have the ability of high-strain packaging and shape-memory effect, but increase the parts and total weight due to the additional heating system. Shape-memory sandwich structures Li and Wang (J. Intell. Mater. Syst. Struct. 22(14), 1605-1612, 2011) can overcome such disadvantage by using the metal skin acting as the heating element. However, the high strain in the micro-buckled metal skin decreases the deployment efficiency. This paper aims to present an insight into the folding and deployment behaviors of shape-memory composite (SMC) tape springs. A thermomechanical process was analyzed, including the packaging deformation at an elevated temperature, shape frozen at the low temperature and shape recovery after reheating. The result shows that SMC tape springs can significantly decrease the strain concentration in the metal skin, as well as exhibiting excellent shape frozen and recovery behaviors. Additionally, possible failure modes of SMC tape springs were also analyzed.

pth moment exponential stability of stochastic memristor-based bidirectional associative memory (BAM) neural networks with time delays.

PubMed

Wang, Fen; Chen, Yuanlong; Liu, Meichun

2018-02-01

Stochastic memristor-based bidirectional associative memory (BAM) neural networks with time delays play an increasingly important role in the design and implementation of neural network systems. Under the framework of Filippov solutions, the issues of the pth moment exponential stability of stochastic memristor-based BAM neural networks are investigated. By using the stochastic stability theory, Itô's differential formula and Young inequality, the criteria are derived. Meanwhile, with Lyapunov approach and Cauchy-Schwarz inequality, we derive some sufficient conditions for the mean square exponential stability of the above systems. The obtained results improve and extend previous works on memristor-based or usual neural networks dynamical systems. Four numerical examples are provided to illustrate the effectiveness of the proposed results. Copyright © 2017 Elsevier Ltd. All rights reserved.

Artificial intelligence applications of fast optical memory access

NASA Astrophysics Data System (ADS)

Henshaw, P. D.; Todtenkopf, A. B.

The operating principles and performance of rapid laser beam-steering (LBS) techniques are reviewed and illustrated with diagrams; their applicability to fast optical-memory (disk) access is evaluated; and the implications of fast access for the design of expert systems are discussed. LBS methods examined include analog deflection (source motion, wavefront tilt, and phased arrays), digital deflection (polarization modulation, reflectivity modulation, interferometric switching, and waveguide deflection), and photorefractive LBS. The disk-access problem is considered, and typical LBS requirements are listed as 38,000 beam positions, rotational latency 25 ms, one-sector rotation time 1.5 ms, and intersector space 87 microsec. The value of rapid access for increasing the power of expert systems (by permitting better organization of blocks of information) is illustrated by summarizing the learning process of the MVP-FORTH system (Park, 1983).

Kmerind: A Flexible Parallel Library for K-mer Indexing of Biological Sequences on Distributed Memory Systems.

PubMed

Pan, Tony; Flick, Patrick; Jain, Chirag; Liu, Yongchao; Aluru, Srinivas

2017-10-09

Counting and indexing fixed length substrings, or k-mers, in biological sequences is a key step in many bioinformatics tasks including genome alignment and mapping, genome assembly, and error correction. While advances in next generation sequencing technologies have dramatically reduced the cost and improved latency and throughput, few bioinformatics tools can efficiently process the datasets at the current generation rate of 1.8 terabases every 3 days. We present Kmerind, a high performance parallel k-mer indexing library for distributed memory environments. The Kmerind library provides a set of simple and consistent APIs with sequential semantics and parallel implementations that are designed to be flexible and extensible. Kmerind's k-mer counter performs similarly or better than the best existing k-mer counting tools even on shared memory systems. In a distributed memory environment, Kmerind counts k-mers in a 120 GB sequence read dataset in less than 13 seconds on 1024 Xeon CPU cores, and fully indexes their positions in approximately 17 seconds. Querying for 1% of the k-mers in these indices can be completed in 0.23 seconds and 28 seconds, respectively. Kmerind is the first k-mer indexing library for distributed memory environments, and the first extensible library for general k-mer indexing and counting. Kmerind is available at https://github.com/ParBLiSS/kmerind.

Testing system for ferromagnetic shape memory microactuators.

PubMed

Ganor, Y; Shilo, D; Messier, J; Shield, T W; James, R D

2007-07-01

Ferromagnetic shape memory alloys are a class of smart materials that exhibit a unique combination of large strains and fast response when exposed to magnetic field. Accordingly, these materials have significant potential in motion generation applications such as microactuators and sensors. This article presents a novel experimental system that measures the dynamic magnetomechanical behavior of microscale ferromagnetic shape memory specimens. The system is comprised of an alternating magnetic field generator (AMFG) and a mechanical loading and sensing system. The AMFG generates a dynamic magnetic field that periodically alternates between two orthogonal directions to facilitate martensitic variant switching and to remotely achieve a full magnetic actuation cycle, without the need of mechanical resetting mechanisms. Moreover, the AMFG is designed to produce a magnetic field that inhibits 180 degrees magnetization domain switching, which causes energy loss without strain generation. The mechanical loading and sensing system maintains a constant mechanical load on the measured specimen by means of a cantilever beam, while the displacement is optically monitored with a resolution of approximately 0.1 microm. Preliminary measurements using Ni(2)MnGa single crystal specimens, with a cross section of 100x100 microm(2), verified their large actuation strains and established their potential to become a material of great importance in microactuation technology.

High-speed high-resolution epifluorescence imaging system using CCD sensor and digital storage for neurobiological research

NASA Astrophysics Data System (ADS)

Takashima, Ichiro; Kajiwara, Riichi; Murano, Kiyo; Iijima, Toshio; Morinaka, Yasuhiro; Komobuchi, Hiroyoshi

2001-04-01

We have designed and built a high-speed CCD imaging system for monitoring neural activity in an exposed animal cortex stained with a voltage-sensitive dye. Two types of custom-made CCD sensors were developed for this system. The type I chip has a resolution of 2664 (H) X 1200 (V) pixels and a wide imaging area of 28.1 X 13.8 mm, while the type II chip has 1776 X 1626 pixels and an active imaging area of 20.4 X 18.7 mm. The CCD arrays were constructed with multiple output amplifiers in order to accelerate the readout rate. The two chips were divided into either 24 (I) or 16 (II) distinct areas that were driven in parallel. The parallel CCD outputs were digitized by 12-bit A/D converters and then stored in the frame memory. The frame memory was constructed with synchronous DRAM modules, which provided a capacity of 128 MB per channel. On-chip and on-memory binning methods were incorporated into the system, e.g., this enabled us to capture 444 X 200 pixel-images for periods of 36 seconds at a rate of 500 frames/second. This system was successfully used to visualize neural activity in the cortices of rats, guinea pigs, and monkeys.

Research in the design of high-performance reconfigurable systems

NASA Technical Reports Server (NTRS)

Mcewan, S. D.; Spry, A. J.

1985-01-01

Computer aided design and computer aided manufacturing have the potential for greatly reducing the cost and lead time in the development of VLSI components. This potential paves the way for the design and fabrication of a wide variety of economically feasible high level functional units. It was observed that current computer systems have only a limited capacity to absorb new VLSI component types other than memory, microprocessors, and a relatively small number of other parts. The first purpose is to explore a system design which is capable of effectively incorporating a considerable number of VLSI part types and will both increase the speed of computation and reduce the attendant programming effort. A second purpose is to explore design techniques for VLSI parts which when incorporated by such a system will result in speeds and costs which are optimal. The proposed work may lay the groundwork for future efforts in the extensive simulation and measurements of the system's cost effectiveness and lead to prototype development.

Implementation of real-time digital signal processing systems

NASA Technical Reports Server (NTRS)

Narasimha, M.; Peterson, A.; Narayan, S.

1978-01-01

Special purpose hardware implementation of DFT Computers and digital filters is considered in the light of newly introduced algorithms and IC devices. Recent work by Winograd on high-speed convolution techniques for computing short length DFT's, has motivated the development of more efficient algorithms, compared to the FFT, for evaluating the transform of longer sequences. Among these, prime factor algorithms appear suitable for special purpose hardware implementations. Architectural considerations in designing DFT computers based on these algorithms are discussed. With the availability of monolithic multiplier-accumulators, a direct implementation of IIR and FIR filters, using random access memories in place of shift registers, appears attractive. The memory addressing scheme involved in such implementations is discussed. A simple counter set-up to address the data memory in the realization of FIR filters is also described. The combination of a set of simple filters (weighting network) and a DFT computer is shown to realize a bank of uniform bandpass filters. The usefulness of this concept in arriving at a modular design for a million channel spectrum analyzer, based on microprocessors, is discussed.

Numerical methods on some structured matrix algebra problems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jessup, E.R.

1996-06-01

This proposal concerned the design, analysis, and implementation of serial and parallel algorithms for certain structured matrix algebra problems. It emphasized large order problems and so focused on methods that can be implemented efficiently on distributed-memory MIMD multiprocessors. Such machines supply the computing power and extensive memory demanded by the large order problems. We proposed to examine three classes of matrix algebra problems: the symmetric and nonsymmetric eigenvalue problems (especially the tridiagonal cases) and the solution of linear systems with specially structured coefficient matrices. As all of these are of practical interest, a major goal of this work was tomore » translate our research in linear algebra into useful tools for use by the computational scientists interested in these and related applications. Thus, in addition to software specific to the linear algebra problems, we proposed to produce a programming paradigm and library to aid in the design and implementation of programs for distributed-memory MIMD computers. We now report on our progress on each of the problems and on the programming tools.« less

Error control for reliable digital data transmission and storage systems

NASA Technical Reports Server (NTRS)

Costello, D. J., Jr.; Deng, R. H.

1985-01-01

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code.

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing.

PubMed

Rao, Feng; Ding, Keyuan; Zhou, Yuxing; Zheng, Yonghui; Xia, Mengjiao; Lv, Shilong; Song, Zhitang; Feng, Songlin; Ronneberger, Ider; Mazzarello, Riccardo; Zhang, Wei; Ma, Evan

2017-12-15

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride (Ge 2 Sb 2 Te 5 ). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc 0.2 Sb 2 Te 3 ) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems. Copyright © 2017 The Authors, some rights reserved; exclusive licensee American Association for the Advancement of Science. No claim to original U.S. Government Works.

Fully integrated sub 100ps photon counting platform

NASA Astrophysics Data System (ADS)

Buckley, S. J.; Bellis, S. J.; Rosinger, P.; Jackson, J. C.

2007-02-01

Current state of the art high resolution counting modules, specifically designed for high timing resolution applications, are largely based on a computer card format. This has tended to result in a costly solution that is restricted to the computer it resides in. We describe a four channel timing module that interfaces to a computer via a USB port and operates with a resolution of less than 100 picoseconds. The core design of the system is an advanced field programmable gate array (FPGA) interfacing to a precision time interval measurement module, mass memory block and a high speed USB 2.0 serial data port. The FPGA design allows the module to operate in a number of modes allowing both continuous recording of photon events (time-tagging) and repetitive time binning. In time-tag mode the system reports, for each photon event, the high resolution time along with the chronological time (macro time) and the channel ID. The time-tags are uploaded in real time to a host computer via a high speed USB port allowing continuous storage to computer memory of up to 4 millions photons per second. In time-bin mode, binning is carried out with count rates up to 10 million photons per second. Each curve resides in a block of 128,000 time-bins each with a resolution programmable down to less than 100 picoseconds. Each bin has a limit of 65535 hits allowing autonomous curve recording until a bin reaches the maximum count or the system is commanded to halt. Due to the large memory storage, several curves/experiments can be stored in the system prior to uploading to the host computer for analysis. This makes this module ideal for integration into high timing resolution specific applications such as laser ranging and fluorescence lifetime imaging using techniques such as time correlated single photon counting (TCSPC).

Characterizing Effects of Nitric Oxide Sterilization on tert-Butyl Acrylate Shape Memory Polymers

NASA Astrophysics Data System (ADS)

Phillippi, Ben

As research into the potential uses of shape memory polymers (SMPs) as implantable medical devices continues to grow and expand, so does the need for an accurate and reliable sterilization mechanism. The ability of an SMP to precisely undergo a programmed shape change will define its ability to accomplish a therapeutic task. To ensure proper execution of the in vivo shape change, the sterilization process must not negatively affect the shape memory behavior of the material. To address this need, this thesis investigates the effectiveness of a benchtop nitric oxide (NOx) sterilization process and the extent to which the process affects the shape memory behavior of a well-studied tert-Butyl Acrylate (tBA) SMP. Quantifying the effects on shape memory behavior was performed using a two-tiered analysis. A two-tiered study design was used to determine if the sterilization process induced any premature shape recovery and to identify any effects that NOx has on the overall shape memory behavior of the foams. Determining the effectiveness of the NOx system--specially, whether the treated samples are more sterile/less contaminated than untreated--was also performed with a two-tiered analysis. In this case, the two-tiered analysis was employed to have a secondary check for contamination. To elaborate, all of the samples that were deemed not contaminated from the initial test were put through a second sterility test to check for contamination a second time. The results of these tests indicated the NOx system is an effective sterilization mechanism and the current protocol does not negatively impact the shape memory behavior of the tBA SMP. The samples held their compressed shape throughout the entirety of the sterilization process. Additionally, there were no observable impacts on the shape memory behavior induced by NOx. Lastly, the treated samples demonstrated lower contamination than the untreated. This thesis demonstrates the effectiveness of NOx as a laboratory scale sterilization mechanism for heat triggered shape memory polymers. The shape memory analysis indicated that the magnitude of the length changes induced by NOx is small enough that it does not make a statistically significant impact on the shape memory behavior of the foams. Additionally, there were no observable effects on the shape memory behavior induced by NOx. The results further indicated the NOx system is effective at sterilizing porous scaffolds, as none of the sterilized samples showed contamination. Testing methods proved to be effective because the initial sterility test was able to identify all of the contaminated samples and preliminary results indicated that NOx sterilization improves the sterility of the foams.

Development of the Wechsler Memory Scale--Revised.

ERIC Educational Resources Information Center

Herman, David O.; Young, Laura

A study involving a sample of people selected to represent the nonimpaired American population, aged 16 to 74 years, was undertaken to determine the effectiveness of the Wechsler Memory Scale--Revised. The scale's subtests were designed to assess memory of personal and general knowledge, logical memory, verbal paired association, figural memory,…

Memory: A Step toward Invention.

ERIC Educational Resources Information Center

Cypert, Rick

Freshman composition students were given six assignments designed to help them examine, analyze, and put their memories into context so that the students could use their memories to begin exploring and creating their own "truths" through language. Two essential types of memory were identified: (1) natural memory, memorizing word for word, which…

A general model for memory interference in a multiprocessor system with memory hierarchy

NASA Technical Reports Server (NTRS)

Taha, Badie A.; Standley, Hilda M.

1989-01-01

The problem of memory interference in a multiprocessor system with a hierarchy of shared buses and memories is addressed. The behavior of the processors is represented by a sequence of memory requests with each followed by a determined amount of processing time. A statistical queuing network model for determining the extent of memory interference in multiprocessor systems with clusters of memory hierarchies is presented. The performance of the system is measured by the expected number of busy memory clusters. The results of the analytic model are compared with simulation results, and the correlation between them is found to be very high.

Towards the formal specification of the requirements and design of a processor interface unit: HOL listings

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1993-01-01

This technical report contains the HOL listings of the specification of the design and major portions of the requirements for a commercially developed processor interface unit (or PIU). The PIU is an interface chip performing memory interface, bus interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. This report contains the actual HOL listings of the PIU specification as it currently exists. Section two of this report contains general-purpose HOL theories that support the PIU specification. These theories include definitions for the hardware components used in the PIU, our implementation of bit words, and our implementation of temporal logic. Section three contains the HOL listings for the PIU design specification. Aside from the PIU internal bus (I-Bus), this specification is complete. Section four contains the HOL listings for a major portion of the PIU requirements specification. Specifically, it contains most of the definition for the PIU behavior associated with memory accesses initiated by the local processor.

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

The effect of exogenous cortisol during sleep on the behavioral and neural correlates of emotional memory consolidation in humans.

PubMed

van Marle, Hein J F; Hermans, Erno J; Qin, Shaozheng; Overeem, Sebastiaan; Fernández, Guillén

2013-09-01

A host of animal work demonstrates that the retention benefit for emotionally aversive over neutral memories is regulated by glucocorticoid action during memory consolidation. Particularly, glucocorticoids may affect systems-level processes that promote the gradual reorganization of emotional memory traces. These effects remain largely uninvestigated in humans. Therefore, in this functional magnetic resonance imaging study we administered hydrocortisone during a polysomnographically monitored night of sleep directly after healthy volunteers studied negative and neutral pictures in a double-blind, placebo-controlled, between-subjects design. The following evening memory consolidation was probed during a recognition memory test in the MR scanner by assessing the difference in brain activity associated with memory for the consolidated items studied before sleep and new, unconsolidated items studied shortly before test (remote vs. recent memory paradigm). Hydrocortisone administration resulted in elevated cortisol levels throughout the experimental night with no group difference at recent encoding or test. Behaviorally, we showed that cortisol enhanced the difference between emotional and neutral consolidated memory, effectively prioritizing emotional memory consolidation. On a neural level, we found that cortisol reduced amygdala reactivity related to the retrieval of these same consolidated, negative items. These findings show that cortisol administration during first post-encoding sleep had a twofold effect on the first 24h of emotional memory consolidation. While cortisol prioritized recognition memory for emotional items, it reduced reactivation of the neural circuitry underlying emotional responsiveness during retrieval. These findings fit recent theories on emotional depotentiation following consolidation during sleep, although future research should establish the sleep-dependence of this effect. Moreover, our data may shed light on mechanisms underlying potential therapeutic effects of cortisol administration following psychological trauma. Copyright © 2013 Elsevier Ltd. All rights reserved.

AESOP- INTERACTIVE DESIGN OF LINEAR QUADRATIC REGULATORS AND KALMAN FILTERS

NASA Technical Reports Server (NTRS)

Lehtinen, B.

1994-01-01

AESOP was developed to solve a number of problems associated with the design of controls and state estimators for linear time-invariant systems. The systems considered are modeled in state-variable form by a set of linear differential and algebraic equations with constant coefficients. Two key problems solved by AESOP are the linear quadratic regulator (LQR) design problem and the steady-state Kalman filter design problem. AESOP is designed to be used in an interactive manner. The user can solve design problems and analyze the solutions in a single interactive session. Both numerical and graphical information are available to the user during the session. The AESOP program is structured around a list of predefined functions. Each function performs a single computation associated with control, estimation, or system response determination. AESOP contains over sixty functions and permits the easy inclusion of user defined functions. The user accesses these functions either by inputting a list of desired functions in the order they are to be performed, or by specifying a single function to be performed. The latter case is used when the choice of function and function order depends on the results of previous functions. The available AESOP functions are divided into several general areas including: 1) program control, 2) matrix input and revision, 3) matrix formation, 4) open-loop system analysis, 5) frequency response, 6) transient response, 7) transient function zeros, 8) LQR and Kalman filter design, 9) eigenvalues and eigenvectors, 10) covariances, and 11) user-defined functions. The most important functions are those that design linear quadratic regulators and Kalman filters. The user interacts with AESOP when using these functions by inputting design weighting parameters and by viewing displays of designed system response. Support functions obtain system transient and frequency responses, transfer functions, and covariance matrices. AESOP can also provide the user with open-loop system information including stability, controllability, and observability. The AESOP program is written in FORTRAN IV for interactive execution and has been implemented on an IBM 3033 computer using TSS 370. As currently configured, AESOP has a central memory requirement of approximately 2 Megs of 8 bit bytes. Memory requirements can be reduced by redimensioning arrays in the AESOP program. Graphical output requires adaptation of the AESOP plot routines to whatever device is available. The AESOP program was developed in 1984.

MIROS: A Hybrid Real-Time Energy-Efficient Operating System for the Resource-Constrained Wireless Sensor Nodes

PubMed Central

Liu, Xing; Hou, Kun Mean; de Vaulx, Christophe; Shi, Hongling; Gholami, Khalid El

2014-01-01

Operating system (OS) technology is significant for the proliferation of the wireless sensor network (WSN). With an outstanding OS; the constrained WSN resources (processor; memory and energy) can be utilized efficiently. Moreover; the user application development can be served soundly. In this article; a new hybrid; real-time; memory-efficient; energy-efficient; user-friendly and fault-tolerant WSN OS MIROS is designed and implemented. MIROS implements the hybrid scheduler and the dynamic memory allocator. Real-time scheduling can thus be achieved with low memory consumption. In addition; it implements a mid-layer software EMIDE (Efficient Mid-layer Software for User-Friendly Application Development Environment) to decouple the WSN application from the low-level system. The application programming process can consequently be simplified and the application reprogramming performance improved. Moreover; it combines both the software and the multi-core hardware techniques to conserve the energy resources; improve the node reliability; as well as achieve a new debugging method. To evaluate the performance of MIROS; it is compared with the other WSN OSes (TinyOS; Contiki; SOS; openWSN and mantisOS) from different OS concerns. The final evaluation results prove that MIROS is suitable to be used even on the tight resource-constrained WSN nodes. It can support the real-time WSN applications. Furthermore; it is energy efficient; user friendly and fault tolerant. PMID:25248069

MIROS: a hybrid real-time energy-efficient operating system for the resource-constrained wireless sensor nodes.

PubMed

Liu, Xing; Hou, Kun Mean; de Vaulx, Christophe; Shi, Hongling; El Gholami, Khalid

2014-09-22

Operating system (OS) technology is significant for the proliferation of the wireless sensor network (WSN). With an outstanding OS; the constrained WSN resources (processor; memory and energy) can be utilized efficiently. Moreover; the user application development can be served soundly. In this article; a new hybrid; real-time; memory-efficient; energy-efficient; user-friendly and fault-tolerant WSN OS MIROS is designed and implemented. MIROS implements the hybrid scheduler and the dynamic memory allocator. Real-time scheduling can thus be achieved with low memory consumption. In addition; it implements a mid-layer software EMIDE (Efficient Mid-layer Software for User-Friendly Application Development Environment) to decouple the WSN application from the low-level system. The application programming process can consequently be simplified and the application reprogramming performance improved. Moreover; it combines both the software and the multi-core hardware techniques to conserve the energy resources; improve the node reliability; as well as achieve a new debugging method. To evaluate the performance of MIROS; it is compared with the other WSN OSes (TinyOS; Contiki; SOS; openWSN and mantisOS) from different OS concerns. The final evaluation results prove that MIROS is suitable to be used even on the tight resource-constrained WSN nodes. It can support the real-time WSN applications. Furthermore; it is energy efficient; user friendly and fault tolerant.

GPU-based optimal control for RWM feedback in tokamaks

DOE PAGES

Clement, Mitchell; Hanson, Jeremy; Bialek, Jim; ...

2017-08-23

The design and implementation of a Graphics Processing Unit (GPU) based Resistive Wall Mode (RWM) controller to perform feedback control on the RWM using Linear Quadratic Gaussian (LQG) control is reported herein. Also, the control algorithm is based on a simplified DIII-D VALEN model. By using NVIDIA’s GPUDirect RDMA framework, the digitizer and output module are able to write and read directly to and from GPU memory, eliminating memory transfers between host and GPU. In conclusion, the system and algorithm was able to reduce plasma response excited by externally applied fields by 32% during development experiments.

GPU-based optimal control for RWM feedback in tokamaks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Clement, Mitchell; Hanson, Jeremy; Bialek, Jim

The design and implementation of a Graphics Processing Unit (GPU) based Resistive Wall Mode (RWM) controller to perform feedback control on the RWM using Linear Quadratic Gaussian (LQG) control is reported herein. Also, the control algorithm is based on a simplified DIII-D VALEN model. By using NVIDIA’s GPUDirect RDMA framework, the digitizer and output module are able to write and read directly to and from GPU memory, eliminating memory transfers between host and GPU. In conclusion, the system and algorithm was able to reduce plasma response excited by externally applied fields by 32% during development experiments.

Hold-up power supply for flash memory

NASA Technical Reports Server (NTRS)

Ott, William E. (Inventor)

2004-01-01

A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system. This power supplied by the storage capacitors allows the flash memory system to complete any erasures and writes, and thus allows the flash memory system to shut down gracefully.

A real-time multi-scale 2D Gaussian filter based on FPGA

NASA Astrophysics Data System (ADS)

Luo, Haibo; Gai, Xingqin; Chang, Zheng; Hui, Bin

2014-11-01

Multi-scale 2-D Gaussian filter has been widely used in feature extraction (e.g. SIFT, edge etc.), image segmentation, image enhancement, image noise removing, multi-scale shape description etc. However, their computational complexity remains an issue for real-time image processing systems. Aimed at this problem, we propose a framework of multi-scale 2-D Gaussian filter based on FPGA in this paper. Firstly, a full-hardware architecture based on parallel pipeline was designed to achieve high throughput rate. Secondly, in order to save some multiplier, the 2-D convolution is separated into two 1-D convolutions. Thirdly, a dedicate first in first out memory named as CAFIFO (Column Addressing FIFO) was designed to avoid the error propagating induced by spark on clock. Finally, a shared memory framework was designed to reduce memory costs. As a demonstration, we realized a 3 scales 2-D Gaussian filter on a single ALTERA Cyclone III FPGA chip. Experimental results show that, the proposed framework can computing a Multi-scales 2-D Gaussian filtering within one pixel clock period, is further suitable for real-time image processing. Moreover, the main principle can be popularized to the other operators based on convolution, such as Gabor filter, Sobel operator and so on.

Crystal that remembers: several ways to utilize nanocrystals in resistive switching memory

NASA Astrophysics Data System (ADS)

Banerjee, Writam; Liu, Qi; Long, Shibing; Lv, Hangbing; Liu, Ming

2017-08-01

The attractive usability of quantum phenomena in futuristic devices is possible by using zero-dimensional systems like nanocrystals (NCs). The performance of nonvolatile flash memory devices has greatly benefited from the use of NCs over recent decades. The quantum abilities of NCs have been used to improve the reliability of flash devices. Its appeal is extended to the design of emerging devices such as resistive random-access memory (RRAM), a technology where the use of silicon is optional. Here, we are going to review the recent progress in the design, characterization, and utilization of NCs in RRAM devices. We will first introduce the physical design of the RRAM devices using NCs and the improvement of electrical performance in NC-RRAM over conventional ones. In particular, special care has been taken to review the ways of development provided by the NCs in the RRAM devices. In a broad sense, the NCs can play a charge trapping role in the NC-RRAM structure or it can be responsible for the localization and improvement of the stability of the conductive filament or it can play a part in the formation of the conductive filament chain by the NC migration under applied bias. Finally, the scope of NCs in the RRAM devices has also been discussed.

Design and Development of the Terrain Information Extraction System

DTIC Science & Technology

1990-09-04

system successfully demonstrated relief measurement and orthophoto production, automated feature extraction has remained "the major problem of today’s...the hierarchical relaxation correlation method developed by Helava Associates, Inc. and digital orthophoto production. To achieve this high accuracy...image memory transfer rates will be achieved by using data blocks or "image tiles ." Further, an image fringe loading module will be implemented which

Models of Physiology/Cognition Relations: Their Prevalence in the Literature and Their Utility in Examining the Effect of Blood Pressure on Vocabulary and Memory for Designs.

ERIC Educational Resources Information Center

Sinnott, Jan D.; And Others

Interest in physiology/cognition relations is increasing, in step with the realization that the individual ages as a whole, adaptive, living system. If a physiological system declines, a person's cognitive abilities may be reduced, unless some compensatory mechanism operates. Understanding this set of relationships permits potential interventions.…

Advanced Integrated Display System V/STOL Program Performance Specification. Volume I.

DTIC Science & Technology

1980-06-01

sensor inputs required before the sensor can be designated acceptable. The reactivation count of each sensor parameter which satisfies its veri...129 3.5.2 AIDS Configuration Parameters .............. 133 3.5.3 AIDS Throughput Requirements ............... 133 4 QUALITY ASSURANCE...lists the adaptation parameters of the AIDS software; these parameters include the throughput and memory requirements of the software. 3.2 SYSTEM

A 128K-bit CCD buffer memory system

NASA Technical Reports Server (NTRS)

Siemens, K. H.; Wallace, R. W.; Robinson, C. R.

1976-01-01

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications.

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Memory Club: A Group Intervention for People with Early-Stage Dementia and Their Care Partners

ERIC Educational Resources Information Center

Zarit, Steven H.; Femia, Elia E.; Watson, Jennifer; Rice-Oeschger, Laura; Kakos, Bernadette

2004-01-01

Purpose: Diagnosis of dementia in its early stages presents a window of opportunity for examining the immediate and long-term consequences of the illness at a point when the individual with memory loss can still participate in decision making. Design and Methods: Memory Club is a l0-session group program designed to provide information about…

FMT (Flight Software Memory Tracker) For Cassini Spacecraft-Software Engineering Using JAVA

NASA Technical Reports Server (NTRS)

Kan, Edwin P.; Uffelman, Hal; Wax, Allan H.

1997-01-01

The software engineering design of the Flight Software Memory Tracker (FMT) Tool is discussed in this paper. FMT is a ground analysis software set, consisting of utilities and procedures, designed to track the flight software, i.e., images of memory load and updatable parameters of the computers on-board Cassini spacecraft. FMT is implemented in Java.

Plated wire memory subsystem

NASA Technical Reports Server (NTRS)

Reynolds, L.; Tweed, H.

1972-01-01

The work performed entailed the design, development, construction and testing of a 4000 word by 18 bit random access, NDRO plated wire memory for use in conjunction with a spacecraft imput/output unit and central processing unit. The primary design parameters, in order of importance, were high reliability, low power, volume and weight. A single memory unit, referred to as a qualification model, was delivered.

Reflexive aerostructures: increased vehicle survivability

NASA Astrophysics Data System (ADS)

Margraf, Thomas W.; Hemmelgarn, Christopher D.; Barnell, Thomas J.; Franklin, Mark A.

2007-04-01

Aerospace systems stand to benefit significantly from the advancement of reflexive aerostructure technologies for increased vehicle survivability. Cornerstone Research Group Inc. (CRG) is developing lightweight, healable composite systems for use as primary load-bearing aircraft components. The reflexive system is comprised of piezoelectric structural health monitoring systems, localized thermal activation systems, and lightweight, healable composite structures. The reflexive system is designed to mimic the involuntary human response to damage. Upon impact, the structural health monitoring system will identify the location and magnitude of the damage, sending a signal to a discrete thermal activation control system to resistively heat the shape memory polymer (SMP) matrix composite above activation temperature, resulting in localized shape recovery and healing of the damaged areas. CRG has demonstrated SMP composites that can recover 90 percent of flexural yield stress and modulus after postfailure healing. During the development, CRG has overcome issues of discrete activation, structural health monitoring integration, and healable resin systems. This paper will address the challenges associated with development of a reflexive aerostructure, including integration of structural health monitoring, discrete healing, and healable shape memory resin systems.

Memory Systems Do Not Divide on Consciousness: Reinterpreting Memory in Terms of Activation and Binding

PubMed Central

Reder, Lynne M.; Park, Heekyeong; Kieffaber, Paul D.

2009-01-01

There is a popular hypothesis that performance on implicit and explicit memory tasks reflects 2 distinct memory systems. Explicit memory is said to store those experiences that can be consciously recollected, and implicit memory is said to store experiences and affect subsequent behavior but to be unavailable to conscious awareness. Although this division based on awareness is a useful taxonomy for memory tasks, the authors review the evidence that the unconscious character of implicit memory does not necessitate that it be treated as a separate system of human memory. They also argue that some implicit and explicit memory tasks share the same memory representations and that the important distinction is whether the task (implicit or explicit) requires the formation of a new association. The authors review and critique dissociations from the behavioral, amnesia, and neuroimaging literatures that have been advanced in support of separate explicit and implicit memory systems by highlighting contradictory evidence and by illustrating how the data can be accounted for using a simple computational memory model that assumes the same memory representation for those disparate tasks. PMID:19210052

Trends in modern system theory

NASA Technical Reports Server (NTRS)

Athans, M.

1976-01-01

The topics considered are related to linear control system design, adaptive control, failure detection, control under failure, system reliability, and large-scale systems and decentralized control. It is pointed out that the design of a linear feedback control system which regulates a process about a desirable set point or steady-state condition in the presence of disturbances is a very important problem. The linearized dynamics of the process are used for design purposes. The typical linear-quadratic design involving the solution of the optimal control problem of a linear time-invariant system with respect to a quadratic performance criterion is considered along with gain reduction theorems and the multivariable phase margin theorem. The stumbling block in many adaptive design methodologies is associated with the amount of real time computation which is necessary. Attention is also given to the desperate need to develop good theories for large-scale systems, the beginning of a microprocessor revolution, the translation of the Wiener-Hopf theory into the time domain, and advances made in dynamic team theory, dynamic stochastic games, and finite memory stochastic control.

Stress Effects on Multiple Memory System Interactions

PubMed Central

Ness, Deborah; Calabrese, Pasquale

2016-01-01

Extensive behavioural, pharmacological, and neurological research reports stress effects on mammalian memory processes. While stress effects on memory quantity have been known for decades, the influence of stress on multiple memory systems and their distinct contributions to the learning process have only recently been described. In this paper, after summarizing the fundamental biological aspects of stress/emotional arousal and recapitulating functionally and anatomically distinct memory systems, we review recent animal and human studies exploring the effects of stress on multiple memory systems. Apart from discussing the interaction between distinct memory systems in stressful situations, we will also outline the fundamental role of the amygdala in mediating such stress effects. Additionally, based on the methods applied in the herein discussed studies, we will discuss how memory translates into behaviour. PMID:27034845

Transactive memory in organizational groups: the effects of content, consensus, specialization, and accuracy on group performance.

PubMed

Austin, John R

2003-10-01

Previous research on transactive memory has found a positive relationship between transactive memory system development and group performance in single project laboratory and ad hoc groups. Closely related research on shared mental models and expertise recognition supports these findings. In this study, the author examined the relationship between transactive memory systems and performance in mature, continuing groups. A group's transactive memory system, measured as a combination of knowledge stock, knowledge specialization, transactive memory consensus, and transactive memory accuracy, is positively related to group goal performance, external group evaluations, and internal group evaluations. The positive relationship with group performance was found to hold for both task and external relationship transactive memory systems.