A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Technical Reports Server (NTRS)

Sewell, James S.; Bozada, Christopher A.

1994-01-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

NASA Astrophysics Data System (ADS)

Sewell, James S.; Bozada, Christopher A.

1994-02-01

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

NASA Astrophysics Data System (ADS)

Sharma, Dheeraj; Singh, Deepika; Pandey, Sunil; Yadav, Shivendra; Kondekar, P. N.

2017-11-01

In this work, we have done a comprehensive study between full-gate and short-gate dielectrically modulated (DM) electrically doped tunnel field-effect transistor (SGDM-EDTFET) based biosensors of equivalent dimensions. However, in both the structures, dielectric constant and charge density are considered as a sensing parameter for sensing the charged and non-charged biomolecules in the given solution. In SGDM-EDTFET architecture, the reduction in gate length results a significant improvement in the tunneling current due to occurrence of strong coupling between gate and channel region which ensures higher drain current sensitivity for detection of the biomolecules. Moreover, the sensitivity of dual metal SGDM-EDTFET is compared with the single metal SGDM-EDTFET to analyze the better sensing capability of both the devices for the biosensor application. Further, the effect of sensing parameter i.e., ON-current (ION), and ION/IOFF ratio is analysed for dual metal SGDM-EDTFET in comparison with dual metal SGDM-EDFET. From the comparison, it is found that dual metal SGDM-EDTFET based biosensor attains relatively better sensitivity and can be utilized as a suitable candidate for biosensing applications.

Differential-Mode Biosensor Using Dual Extended-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Choi, Jinhyeon; Lee, Hee Ho; Ahn, Jungil; Seo, Sang-Ho; Shin, Jang-Kyoo

2012-06-01

In this paper, we present a differential-mode biosensor using dual extended-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), which possesses the advantages of both the extended-gate structure and the differential-mode operation. The extended-gate MOSFET was fabricated using a 0.6 µm standard complementary metal oxide semiconductor (CMOS) process. The Au extended gate is the sensing gate on which biomolecules are immobilized, while the Pt extended gate is the dummy gate for use in the differential-mode detection circuit. The differential-mode operation offers many advantages such as insensitivity to the variation of temperature and light, as well as low noise. The outputs were measured using a semiconductor parameter analyzer in a phosphate buffered saline (PBS; pH 7.4) solution. A standard Ag/AgCl reference electrode was used to apply the gate bias. We measured the variation of output voltage with time, temperature, and light intensity. The bindings of self-assembled monolayer (SAM), streptavidin, and biotin caused a variation in the output voltage of the differential-mode detection circuit and this was confirmed by surface plasmon resonance (SPR) experiment. Biotin molecules could be detected up to a concentration of as low as 0.001 µg/ml.

Thermally stable In0.7Ga0.3As/In0.52Al0.48As pHEMTs using thermally evaporated palladium gate metallization

NASA Astrophysics Data System (ADS)

Ian, Ka Wa; Zawawiand, Mohamad Adzhar Md; Missous, Mohamed

2014-03-01

This work described the fabrication and performances of strained channel In0.52Al0.47As/In0.7Ga0.3As/InP pHEMTs with thermally evaporated Pd/Ti/Au gate metallization. The electrical characteristics of these Pd-gate devices are studied to investigate the effects of changing the Pd metal thickness, annealing temperature and annealing time. Following annealing at 200 °C for 35 min, a 10 nm Pd-gate device displays a VTH of -0.25 V, which is significantly smaller compared to those with Ti/Au gate schemes showing VTH = -0.75 V. A 1 um gate length device exhibits an improved Gm of 580 mS mm-1 (from 500 mS mm-1), a high IDSmax of 400 mA mm-1 (from 330 mA mm-1) and good fT and fmax of 24.5 and 49 GHz commensurate with the 1 µm gate length. All these enhancements are attributed to the controllable gate sinking of Pd. The device shows no significant degradation even after annealing at 230 °C for more than 5 h, which implies that the reliability of these Pd-gate structures is excellent.

Direct Structural Identification of Gas Induced Gate-Opening Coupled with Commensurate Adsorption in a Microporous Metal-Organic Framework.

PubMed

Banerjee, Debasis; Wang, Hao; Plonka, Anna M; Emge, Thomas J; Parise, John B; Li, Jing

2016-08-08

Gate-opening is a unique and interesting phenomenon commonly observed in flexible porous frameworks, where the pore characteristics and/or crystal structures change in response to external stimuli such as adding or removing guest molecules. For gate-opening that is induced by gas adsorption, the pore-opening pressure often varies for different adsorbate molecules and, thus, can be applied to selectively separate a gas mixture. The detailed understanding of this phenomenon is of fundamental importance to the design of industrially applicable gas-selective sorbents, which remains under investigated due to the lack of direct structural evidence for such systems. We report a mechanistic study of gas-induced gate-opening process of a microporous metal-organic framework, [Mn(ina)2 ] (ina=isonicotinate) associated with commensurate adsorption, by a combination of several analytical techniques including single crystal X-ray diffraction, in situ powder X-ray diffraction coupled with differential scanning calorimetry (XRD-DSC), and gas adsorption-desorption methods. Our study reveals that the pronounced and reversible gate opening/closing phenomena observed in [Mn(ina)2 ] are coupled with a structural transition that involves rotation of the organic linker molecules as a result of interaction of the framework with adsorbed gas molecules including carbon dioxide and propane. The onset pressure to open the gate correlates with the extent of such interaction. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Transparent conducting oxide induced by liquid electrolyte gating

NASA Astrophysics Data System (ADS)

ViolBarbosa, Carlos; Karel, Julie; Kiss, Janos; Gordan, Ovidiu-dorin; Altendorf, Simone G.; Utsumi, Yuki; Samant, Mahesh G.; Wu, Yu-Han; Tsuei, Ku-Ding; Felser, Claudia; Parkin, Stuart S. P.

2016-10-01

Optically transparent conducting materials are essential in modern technology. These materials are used as electrodes in displays, photovoltaic cells, and touchscreens; they are also used in energy-conserving windows to reflect the infrared spectrum. The most ubiquitous transparent conducting material is tin-doped indium oxide (ITO), a wide-gap oxide whose conductivity is ascribed to n-type chemical doping. Recently, it has been shown that ionic liquid gating can induce a reversible, nonvolatile metallic phase in initially insulating films of WO3. Here, we use hard X-ray photoelectron spectroscopy and spectroscopic ellipsometry to show that the metallic phase produced by the electrolyte gating does not result from a significant change in the bandgap but rather originates from new in-gap states. These states produce strong absorption below ˜1 eV, outside the visible spectrum, consistent with the formation of a narrow electronic conduction band. Thus WO3 is metallic but remains colorless, unlike other methods to realize tunable electrical conductivity in this material. Core-level photoemission spectra show that the gating reversibly modifies the atomic coordination of W and O atoms without a substantial change of the stoichiometry; we propose a simple model relating these structural changes to the modifications in the electronic structure. Thus we show that ionic liquid gating can tune the conductivity over orders of magnitude while maintaining transparency in the visible range, suggesting the use of ionic liquid gating for many applications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gelinck, G. H., E-mail: Gerwin.Gelinck@tno.nl; Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven; Breemen, A. J. J. M. van

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

Control of interlayer physics in 2H transition metal dichalcogenides

NASA Astrophysics Data System (ADS)

Wang, Kuang-Chung; Stanev, Teodor K.; Valencia, Daniel; Charles, James; Henning, Alex; Sangwan, Vinod K.; Lahiri, Aritra; Mejia, Daniel; Sarangapani, Prasad; Povolotskyi, Michael; Afzalian, Aryan; Maassen, Jesse; Klimeck, Gerhard; Hersam, Mark C.; Lauhon, Lincoln J.; Stern, Nathaniel P.; Kubis, Tillmann

2017-12-01

It is assessed in detail both experimentally and theoretically how the interlayer coupling of transition metal dichalcogenides controls the electronic properties of the respective devices. Gated transition metal dichalcogenide structures show electrons and holes to either localize in individual monolayers, or delocalize beyond multiple layers—depending on the balance between spin-orbit interaction and interlayer hopping. This balance depends on the layer thickness, momentum space symmetry points, and applied gate fields. The design range of this balance, the effective Fermi levels, and all relevant effective masses is analyzed in great detail. A good quantitative agreement of predictions and measurements of the quantum confined Stark effect in gated MoS2 systems unveils intralayer excitons as the major source for the observed photoluminescence.

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE PAGES

Black, Jennifer M.; Come, Jeremy; Bi, Sheng; ...

2017-10-24

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Role of Electrical Double Layer Structure in Ionic Liquid Gated Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Black, Jennifer M.; Come, Jeremy; Bi, Sheng

Ionic liquid gating of transition metal oxides has enabled new states (magnetic, electronic, metal–insulator), providing fundamental insights into the physics of strongly correlated oxides. However, despite much research activity, little is known about the correlation of the structure of the liquids in contact with the transition metal oxide surface, its evolution with the applied electric potential, and its correlation with the measured electronic properties of the oxide. Here, we investigate the structure of an ionic liquid at a semiconducting oxide interface during the operation of a thin film transistor where the electrical double layer gates the device using experiment andmore » theory. We show that the transition between the ON and OFF states of the amorphous indium gallium zinc oxide transistor is accompanied by a densification and preferential spatial orientation of counterions at the oxide channel surface. This process occurs in three distinct steps, corresponding to ion orientations, and consequently, regimes of different electrical conductivity. The reason for this can be found in the surface charge densities on the oxide surface when different ion arrangements are present. Overall, the field-effect gating process is elucidated in terms of the interfacial ionic liquid structure, and this provides unprecedented insight into the working of a liquid gated transistor linking the nanoscopic structure to the functional properties. This knowledge will enable both new ionic liquid design as well as advanced device concepts.« less

Novel WSi/Au T-shaped gate GaAs metal-semiconductor field-effect-transistor fabrication process for super low-noise microwave monolithic integrated circuit amplifiers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takano, H.; Hosogi, K.; Kato, T.

1995-05-01

A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier withmore » an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs.« less

Exploring the structure and function of Thermotoga maritima CorA reveals the mechanism of gating and ion selectivity in Co2+/Mg2+ transport

PubMed Central

Nordin, Nurhuda; Guskov, Albert; Phua, Terri; Sahaf, Newsha; Xia, Yu; Lu, Siyan; Eshaghi, Hojjat; Eshaghi, Said

2013-01-01

The CorA family of divalent cation transporters utilizes Mg2+ and Co2+ as primary substrates. The molecular mechanism of its function, including ion selectivity and gating, has not been fully characterized. Recently we reported a new structure of a CorA homologue from Methanocaldococcus jannaschii, which provided novel structural details that offered the conception of a unique gating mechanism involving conversion of an open hydrophilic gate into a closed hydrophobic one. In the present study we report functional evidence for this novel gating mechanism in the Thermotoga maritima CorA together with an improved crystal structure of this CorA to 2.7 Å (1 Å=0.1 nm) resolution. The latter reveals the organization of the selectivity filter to be similar to that of M. jannaschii CorA and also the previously unknown organization of the second signature motif of the CorA family. The proposed gating is achieved by a helical rotation upon the binding of a metal ion substrate to the regulatory binding sites. Additionally, our data suggest that the preference of this CorA for Co2+ over Mg2+ is controlled by the presence of threonine side chains in the channel. Finally, the roles of the intracellular metal-binding sites have been assigned to increased thermostability and regulation of the gating. These mechanisms most likely apply to the entire CorA family as they are regulated by the highly conserved amino acids. PMID:23425532

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Electrochemical formation of field emitters

DOEpatents

Bernhardt, Anthony F.

1999-01-01

Electrochemical formation of field emitters, particularly useful in the fabrication of flat panel displays. The fabrication involves field emitting points in a gated field emitter structure. Metal field emitters are formed by electroplating and the shape of the formed emitter is controlled by the potential imposed on the gate as well as on a separate counter electrode. This allows sharp emitters to be formed in a more inexpensive and manufacturable process than vacuum deposition processes used at present. The fabrication process involves etching of the gate metal and the dielectric layer down to the resistor layer, and then electroplating the etched area and forming an electroplated emitter point in the etched area.

Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure. Electronic supplementary information (ESI) available: Energy-dispersive X-ray spectroscopy (EDS) spectra of the metal NPs, SEM image of MoS2 on Au NPs, erasing operations of the metal NPs-MoS2 memory device, transfer characteristics of the standard FET devices and Ag NP devices under programming operation, tapping-mode AFM height image of the fabricated MoS2 film for pristine MoS2 flash memory, gate signals used for programming the Au NPs-MoS2 and Pt NPs-MoS2 flash memories, and data levels recorded for 100 sequential cycles. See DOI: 10.1039/c5nr05054e

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

ZnO-based multiple channel and multiple gate FinMOSFETs

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Huang, Hung-Lin; Tseng, Chun-Yen; Lee, Hsin-Ying

2016-02-01

In recent years, zinc oxide (ZnO)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted much attention, because ZnO-based semiconductors possess several advantages, including large exciton binding energy, nontoxicity, biocompatibility, low material cost, and wide direct bandgap. Moreover, the ZnO-based MOSFET is one of most potential devices, due to the applications in microwave power amplifiers, logic circuits, large scale integrated circuits, and logic swing. In this study, to enhance the performances of the ZnO-based MOSFETs, the ZnObased multiple channel and multiple gate structured FinMOSFETs were fabricated using the simple laser interference photolithography method and the self-aligned photolithography method. The multiple channel structure possessed the additional sidewall depletion width control ability to improve the channel controllability, because the multiple channel sidewall portions were surrounded by the gate electrode. Furthermore, the multiple gate structure had a shorter distance between source and gate and a shorter gate length between two gates to enhance the gate operating performances. Besides, the shorter distance between source and gate could enhance the electron velocity in the channel fin structure of the multiple gate structure. In this work, ninety one channels and four gates were used in the FinMOSFETs. Consequently, the drain-source saturation current (IDSS) and maximum transconductance (gm) of the ZnO-based multiple channel and multiple gate structured FinFETs operated at a drain-source voltage (VDS) of 10 V and a gate-source voltage (VGS) of 0 V were respectively improved from 11.5 mA/mm to 13.7 mA/mm and from 4.1 mS/mm to 6.9 mS/mm in comparison with that of the conventional ZnO-based single channel and single gate MOSFETs.

Investigation of the novel attributes in double recessed gate SiC MESFETs at drain side

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Razavi, S. M.; Ebrahim Hosseini, Seyed; Amini Moghadam, Hamid

2011-11-01

In this paper, the potential impact of drain side-double recessed gate (DS-DRG) on silicon carbide (SiC)-based metal semiconductor field effect transistors (MESFETs) is studied. We investigate the device performance focusing on breakdown voltage, threshold voltage, drain current and dc output conductance with two-dimensional and two-carrier device simulation. Our simulation results demonstrate that the channel thickness under the gate in the drain side is an important factor in the breakdown voltage. Also, the positive shift in the threshold voltage for the DS-DRG structure is larger in comparison with that for the source side-double recessed gate (SS-DRG) SiC MESFET. The saturated drain current for the DS-DRG structure is larger compared to that for the SS-DRG structure. The maximum dc output conductance in the DS-DRG structure is smaller than that in the SS-DRG structure.

Probing the structural flexibility of MOFs by constructing metal oxide@MOF-based heterostructures for size-selective photoelectrochemical response

NASA Astrophysics Data System (ADS)

Zhan, Wenwen; He, Yue; Guo, Jiangbin; Chen, Luning; Kong, Xiangjian; Zhao, Haixia; Kuang, Qin; Xie, Zhaoxiong; Zheng, Lansun

2016-07-01

It is becoming a challenge to achieve simpler characterization and wider application of flexible metal organic frameworks (MOFs) exhibiting the gate-opening or breathing behavior. Herein, we designed an intelligent MOF-based system where the gate-opening or breathing behavior of MOFs can be facially visualized in solution. Two types of metal oxide@MOF core-shell heterostructures, ZnO@ZIF-7 and ZnO@ZIF-71, were prepared using ZnO nanorods as self-sacrificial templates. The structural flexibility of both the MOFs can be easily judged from the distinct molecular-size-related formation modes and photoelectrochemical performances between the two ZnO@ZIF heterostructures. Moreover, the rotational dynamics of the flexible parts of ZIF-7 were studied by analyzing the intrinsic physical properties, such as dielectric constants, of the structure. The present work reminds us to pay particular attention to the influences of the structural flexibility of MOFs on the structure and properties of MOF-involved heterostructures in future studies.It is becoming a challenge to achieve simpler characterization and wider application of flexible metal organic frameworks (MOFs) exhibiting the gate-opening or breathing behavior. Herein, we designed an intelligent MOF-based system where the gate-opening or breathing behavior of MOFs can be facially visualized in solution. Two types of metal oxide@MOF core-shell heterostructures, ZnO@ZIF-7 and ZnO@ZIF-71, were prepared using ZnO nanorods as self-sacrificial templates. The structural flexibility of both the MOFs can be easily judged from the distinct molecular-size-related formation modes and photoelectrochemical performances between the two ZnO@ZIF heterostructures. Moreover, the rotational dynamics of the flexible parts of ZIF-7 were studied by analyzing the intrinsic physical properties, such as dielectric constants, of the structure. The present work reminds us to pay particular attention to the influences of the structural flexibility of MOFs on the structure and properties of MOF-involved heterostructures in future studies. Electronic supplementary information (ESI) available: Experimental details, XRD patterns and SEM images of products in other reactions, concentration-dependent photocurrent responses, and supplementary data of dielectric measurements. See DOI: 10.1039/c6nr02257j

Electrochemical formation of field emitters

DOEpatents

Bernhardt, A.F.

1999-03-16

Electrochemical formation of field emitters, particularly useful in the fabrication of flat panel displays is disclosed. The fabrication involves field emitting points in a gated field emitter structure. Metal field emitters are formed by electroplating and the shape of the formed emitter is controlled by the potential imposed on the gate as well as on a separate counter electrode. This allows sharp emitters to be formed in a more inexpensive and manufacturable process than vacuum deposition processes used at present. The fabrication process involves etching of the gate metal and the dielectric layer down to the resistor layer, and then electroplating the etched area and forming an electroplated emitter point in the etched area. 12 figs.

Trace metals in the brain: allosteric modulators of ligand-gated receptor channels, the case of ATP-gated P2X receptors.

PubMed

Huidobro-Toro, J Pablo; Lorca, Ramón A; Coddou, Claudio

2008-03-01

Zinc and copper are indispensable trace metals for life with a recognized role as catalysts in enzyme actions. We now review evidence supporting the role of trace metals as novel allosteric modulators of ionotropic receptors: a new and fundamental physiological role for zinc and copper in neuronal and brain excitability. The review is focussed on ionotropic receptor channels including nucleotide receptors, in particular the P2X receptor family. Since zinc and copper are stored within synaptic vesicles in selected brain regions, and released to the synaptic cleft upon electrical nerve ending depolarization, it is plausible that zinc and copper reach concentrations in the synapse that profoundly affect ligand-gated ionic channels, including the ATP-gated currents of P2X receptors. The identification of key P2X receptor amino acids that act as ligands for trace metal coordination, carves the structural determinants underlying the allosteric nature of the trace metal modulation. The recognition that the identified key residues such as histidines, aspartic and glutamic acids or cysteines in the extracellular domain are different for each P2X receptor subtype and may be different for each metal, highlights the notion that each P2X receptor subtype evolved independent strategies for metal coordination, which form upon the proper three-dimensional folding of the receptor channels. The understanding of the molecular mechanism of allosteric modulation of ligand-operated ionic channels by trace metals is a new contribution to metallo-neurobiology.

A Secondary Structural Transition in the C-helix Promotes Gating of Cyclic Nucleotide-regulated Ion Channels*

PubMed Central

Puljung, Michael C.; Zagotta, William N.

2013-01-01

Cyclic nucleotide-regulated ion channels bind second messengers like cAMP to a C-terminal domain, consisting of a β-roll, followed by two α-helices (B- and C-helices). We monitored the cAMP-dependent changes in the structure of the C-helix of a C-terminal fragment of HCN2 channels using transition metal ion FRET between fluorophores on the C-helix and metal ions bound between histidine pairs on the same helix. cAMP induced a change in the dimensions of the C-helix and an increase in the metal binding affinity of the histidine pair. cAMP also caused an increase in the distance between a fluorophore on the C-helix and metal ions bound to the B-helix. Stabilizing the C-helix of intact CNGA1 channels by metal binding to a pair of histidines promoted channel opening. These data suggest that ordering of the C-helix is part of the gating conformational change in cyclic nucleotide-regulated channels. PMID:23525108

Hydrogen-terminated diamond vertical-type metal oxide semiconductor field-effect transistors with a trench gate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Inaba, Masafumi, E-mail: inaba-ma@ruri.waseda.jp; Muta, Tsubasa; Kobayashi, Mikinori

2016-07-18

The hydrogen-terminated diamond surface (C-H diamond) has a two-dimensional hole gas (2DHG) layer independent of the crystal orientation. A 2DHG layer is ubiquitously formed on the C-H diamond surface covered by atomic-layer-deposited-Al{sub 2}O{sub 3}. Using Al{sub 2}O{sub 3} as a gate oxide, C-H diamond metal oxide semiconductor field-effect transistors (MOSFETs) operate in a trench gate structure where the diamond side-wall acts as a channel. MOSFETs with a side-wall channel exhibit equivalent performance to the lateral C-H diamond MOSFET without a side-wall channel. Here, a vertical-type MOSFET with a drain on the bottom is demonstrated in diamond with channel current modulationmore » by the gate and pinch off.« less

A novel approach for the improvement of electrostatic behaviour of physically doped TFET using plasma formation and shortening of gate electrode with hetero-gate dielectric

NASA Astrophysics Data System (ADS)

Soni, Deepak; Sharma, Dheeraj; Aslam, Mohd.; Yadav, Shivendra

2018-04-01

This article presents a new device configuration to enhance current drivability and suppress negative conduction (ambipolar conduction) with improved RF characteristics of physically doped TFET. Here, we used a new approach to get excellent electrical characteristics of hetero-dielectric short gate source electrode TFET (HD-SG SE-TFET) by depositing a metal electrode of 5.93 eV work function over the heavily doped source (P+) region. Deposition of metal electrode induces the plasma (thin layer) of holes under the Si/HfO2 interface due to work function difference of metal and semiconductor. Plasma layer of holes is advantageous to increase abruptness as well as decrease the tunneling barrier at source/channel junction for attaining higher tunneling rate of charge carriers (i.e., electrons), which turns into 86.66 times higher ON-state current compared with the conventional physically doped TFET (C-TFET). Along with metal electrode deposition, gate electrode is under-lapped for inducing asymmetrical concentration of charge carriers in the channel region, which is helpful for widening the tunneling barrier width at the drain/channel interface. Consequently, HD-SG SE-TFET shows suppression of ambipolar behavior with reduction in gate-to-drain capacitance which is beneficial for improvement in RF performance. Furthermore, the effectiveness of hetero-gate dielectric concept has been used for improving the RF performance. Furthermore, reliability of C-TFET and proposed structures has been confirmed in term of linearity.

Submicron Silicon MOSFET

NASA Technical Reports Server (NTRS)

Daud, T.

1986-01-01

Process for making metal-oxide/semiconductor field-effect transistors (MOSFET's) results in gate-channel lengths of only few hundred angstroms about 100 times as small as state-of-the-art devices. Gates must be shortened to develop faster MOSFET's; proposed fabrication process used to study effects of size reduction in MOS devices and eventually to build practical threedimensional structures.

Novel failure mechanism and improvement for split-gate trench MOSFET with large current under unclamped inductive switch stress

NASA Astrophysics Data System (ADS)

Tian, Ye; Yang, Zhuo; Xu, Zhiyuan; Liu, Siyang; Sun, Weifeng; Shi, Longxing; Zhu, Yuanzheng; Ye, Peng; Zhou, Jincheng

2018-04-01

In this paper, a novel failure mechanism under unclamped inductive switch (UIS) for Split-Gate Trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with large current is investigated. The device sample is tested and analyzed in detail. The simulation results demonstrate that the nonuniform potential distribution of the source poly should be responsible for the failure. Three structures are proposed and verified available to improve the device UIS ruggedness by TCAD simulation. The best one of the structures the device with source metal inserting into source poly through contacts in the field oxide is carried out and measured. The results demonstrate that the optimized structure can balance the trade-off between the UIS ruggedness and the static characteristics.

Gate-tuned Josephson effect on the surface of a topological insulator

PubMed Central

2014-01-01

In the study, we investigate the Josephson supercurrent of a superconductor/normal metal/superconductor junction on the surface of a topological insulator, where a gate electrode is attached to the normal metal. It is shown that the Josephson supercurrent not only can be tuned largely by the temperature but also is related to the potential and the length of the weak-link region. Especially, the asymmetry excess critical supercurrent, oscillatory character, and plateau-like structure have been revealed. We except those phenomena that can be observed in the recent experiment. PMID:25249827

Possibility of transforming the electronic structure of one species of graphene adatoms into that of another by application of gate voltage: First-principles calculations

NASA Astrophysics Data System (ADS)

Chan, Kevin T.; Lee, Hoonkyung; Cohen, Marvin L.

2011-10-01

Graphene provides many advantages for controlling the electronic structure of adatoms and other adsorbates via gating. Using the projected density of states and charge density obtained from first-principles density-functional periodic supercell calculations, we investigate the possibility of performing “alchemy” of adatoms on graphene, i.e., transforming the electronic structure of one species of adatom into that of another species by application of a gate voltage. Gating is modeled as a change in the number of electrons in the unit cell, with the inclusion of a compensating uniform background charge. Within this model and the generalized gradient approximation to the exchange-correlation functional, we find that such transformations are possible for K, Ca, and several transition-metal adatoms. Gate control of the occupation of the p states of In on graphene is also investigated. The validity of the supercell approximation with uniform compensating charge and the model for exchange and correlation is also discussed.

Low trap states in in situ SiN{sub x}/AlN/GaN metal-insulator-semiconductor structures grown by metal-organic chemical vapor deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Xing; Ma, Jun; Jiang, Huaxing

2014-09-08

We report the use of SiN{sub x} grown in situ by metal-organic chemical vapor deposition as the gate dielectric for AlN/GaN metal-insulator-semiconductor (MIS) structures. Two kinds of trap states with different time constants were identified and characterized. In particular, the SiN{sub x}/AlN interface exhibits remarkably low trap state densities in the range of 10{sup 11}–10{sup 12 }cm{sup −2}eV{sup −1}. Transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the in situ SiN{sub x} layer can provide excellent passivation without causing chemical degradation to the AlN surface. These results imply the great potential of in situ SiN{sub x} as an effectivemore » gate dielectric for AlN/GaN MIS devices.« less

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Simulation study of short-channel effects of tunnel field-effect transistors

NASA Astrophysics Data System (ADS)

Fukuda, Koichi; Asai, Hidehiro; Hattori, Junichi; Mori, Takahiro; Morita, Yukinori; Mizubayashi, Wataru; Masahara, Meishoku; Migita, Shinji; Ota, Hiroyuki; Endo, Kazuhiro; Matsukawa, Takashi

2018-04-01

Short-channel effects of tunnel field-effect transistors (FETs) are investigated in detail using simulations of a nonlocal band-to-band tunneling model. Discussion is limited to silicon. Several simulation scenarios were considered to address different effects, such as source overlap and drain offset effects. Adopting the drain offset to suppress the drain leakage current suppressed the short channel effects. The physical mechanism underlying the short-channel behavior of the tunnel FETs (TFETs) was very different from that of metal-oxide-semiconductor FETs (MOSFETs). The minimal gate lengths that do not lose on-state current by one order are shown to be 3 nm for single-gate structures and 2 nm for double gate structures, as determined from the drain offset structure.

DIFMOS - A floating-gate electrically erasable nonvolatile semiconductor memory technology. [Dual Injector Floating-gate MOS

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1977-01-01

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.

Direct visualization and in-depth physical study of metal filament formation in percolated high-κ dielectrics

NASA Astrophysics Data System (ADS)

Li, X.; Pey, K. L.; Bosman, M.; Liu, W. H.; Kauerauf, T.

2010-01-01

The migration of Ta atoms from a transistor gate electrode into the percolated high-κ (HK) gate dielectrics is directly shown using transmission electron microscopy analysis. A nanoscale metal filament that formed under high current injection is identified to be the physical defect responsible for the ultrafast transient breakdown (BD) of the metal-gate/high-κ (MG/HK) gate stacks. This highly conductive metal filament poses reliability concerns for MG/HK gate stacks as it significantly reduces the post-BD reliability margin of a transistor.

Enhancement mode GaN-based multiple-submicron channel array gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors

NASA Astrophysics Data System (ADS)

Lee, Ching-Ting; Wang, Chun-Chi

2018-04-01

To study the function of channel width in multiple-submicron channel array, we fabricated the enhancement mode GaN-based gate-recessed fin metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs) with a channel width of 450 nm and 195 nm, respectively. In view of the enhanced gate controllability in a narrower fin-channel structure, the transconductance was improved from 115 mS/mm to 151 mS/mm, the unit gain cutoff frequency was improved from 6.2 GHz to 6.8 GHz, and the maximum oscillation frequency was improved from 12.1 GHz to 13.1 GHz of the devices with a channel width of 195 nm, compared with the devices with a channel width of 450 nm.

Structural and thermodynamic consideration of metal oxide doped GeO{sub 2} for gate stack formation on germanium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Zhang, Wenfeng

2014-11-07

A systematic investigation was carried out on the material and electrical properties of metal oxide doped germanium dioxide (M-GeO{sub 2}) on Ge. We propose two criteria on the selection of desirable M-GeO{sub 2} for gate stack formation on Ge. First, metal oxides with larger cation radii show stronger ability in modifying GeO{sub 2} network, benefiting the thermal stability and water resistance in M-GeO{sub 2}/Ge stacks. Second, metal oxides with a positive Gibbs free energy for germanidation are required for good interface properties of M-GeO{sub 2}/Ge stacks in terms of preventing the Ge-M metallic bond formation. Aggressive equivalent oxide thickness scalingmore » to 0.5 nm is also demonstrated based on these understandings.« less

Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

NASA Astrophysics Data System (ADS)

Esakky, Papanasam; Kailath, Binsu J.

2017-08-01

HfO2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO2/SiC capacitors offer higher sensitivity than SiO2/SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO2/SiC interface. Effect of post deposition annealing in N2O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO2/SiC MIS capacitors are reported in this work. N2O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N2 result in formation of Hf silicate at the HfO2/SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40 min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N2O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO2/SiC capacitors.

Photo-electronic current transport in back-gated graphene transistor

NASA Astrophysics Data System (ADS)

Srivastava, Ashok; Chen, Xinlu; Pradhan, Aswini K.

2017-04-01

In this work, we have studied photo-electronic current transport in a back-gated graphene field-effect transistor. Under the light illumination, band bending at the metal/graphene interface develops a built-in potential which generates photonic current at varying back-gate biases. A typical MOSFET type back-gated transistor structure uses a monolayer graphene as the channel layer formed over the silicon dioxide/silicon substrate. It is shown that the photo-electronic current consists of current contributions from photovoltaic, photo-thermoelectric and photo-bolometric effects. A maximum external responsivity close to 0.0009A/W is achieved at 30μW laser power source and 633nm wavelength.

Visible to short wavelength infrared In2Se3-nanoflake photodetector gated by a ferroelectric polymer

NASA Astrophysics Data System (ADS)

Wu, Guangjian; Wang, Xudong; Wang, Peng; Huang, Hai; Chen, Yan; Sun, Shuo; Shen, Hong; Lin, Tie; Wang, Jianlu; Zhang, Shangtao; Bian, Lifeng; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao

2016-09-01

Photodetectors based on two-dimensional (2D) transition-metal dichalcogenides have been studied extensively in recent years. However, the detective spectral ranges, dark current and response time are still unsatisfactory, even under high gate and source-drain bias. In this work, the photodetectors of In2Se3 have been fabricated on a ferroelectric field effect transistor structure. Based on this structure, high performance photodetectors have been achieved with a broad photoresponse spectrum (visible to 1550 nm) and quick response (200 μs). Most importantly, with the intrinsic huge electric field derived from the polarization of ferroelectric polymer (P(VDF-TrFE)) gating, a low dark current of the photodetector can be achieved without additional gate bias. These studies present a crucial step for further practical applications for 2D semiconductors.

Liquid-Solid Dual-Gate Organic Transistors with Tunable Threshold Voltage for Cell Sensing.

PubMed

Zhang, Yu; Li, Jun; Li, Rui; Sbircea, Dan-Tiberiu; Giovannitti, Alexander; Xu, Junling; Xu, Huihua; Zhou, Guodong; Bian, Liming; McCulloch, Iain; Zhao, Ni

2017-11-08

Liquid electrolyte-gated organic field effect transistors and organic electrochemical transistors have recently emerged as powerful technology platforms for sensing and simulation of living cells and organisms. For such applications, the transistors are operated at a gate voltage around or below 0.3 V because prolonged application of a higher voltage bias can lead to membrane rupturing and cell death. This constraint often prevents the operation of the transistors at their maximum transconductance or most sensitive regime. Here, we exploit a solid-liquid dual-gate organic transistor structure, where the threshold voltage of the liquid-gated conduction channel is controlled by an additional gate that is separated from the channel by a metal-oxide gate dielectric. With this design, the threshold voltage of the "sensing channel" can be linearly tuned in a voltage window exceeding 0.4 V. We have demonstrated that the dual-gate structure enables a much better sensor response to the detachment of human mesenchymal stem cells. In general, the capability of tuning the optimal sensing bias will not only improve the device performance but also broaden the material selection for cell-based organic bioelectronics.

Impact of metal gates on remote phonon scattering in titanium nitride/hafnium dioxide n-channel metal-oxide-semiconductor field effect transistors-low temperature electron mobility study

NASA Astrophysics Data System (ADS)

Maitra, Kingsuk; Frank, Martin M.; Narayanan, Vijay; Misra, Veena; Cartier, Eduard A.

2007-12-01

We report low temperature (40-300 K) electron mobility measurements on aggressively scaled [equivalent oxide thickness (EOT)=1 nm] n-channel metal-oxide-semiconductor field effect transistors (nMOSFETs) with HfO2 gate dielectrics and metal gate electrodes (TiN). A comparison is made with conventional nMOSFETs containing HfO2 with polycrystalline Si (poly-Si) gate electrodes. No substantial change in the temperature acceleration factor is observed when poly-Si is replaced with a metal gate, showing that soft optical phonons are not significantly screened by metal gates. A qualitative argument based on an analogy between remote phonon scattering and high-resolution electron energy-loss spectroscopy (HREELS) is provided to explain the underlying physics of the observed phenomenon. It is also shown that soft optical phonon scattering is strongly damped by thin SiO2 interface layers, such that room temperature electron mobility values at EOT=1 nm become competitive with values measured in nMOSFETs with SiON gate dielectrics used in current high performance processors.

Reconfigurable quadruple quantum dots in a silicon nanowire transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Betz, A. C., E-mail: ab2106@cam.ac.uk; Broström, M.; Gonzalez-Zalba, M. F.

2016-05-16

We present a reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consists of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.

Identifying the Role of Terahertz Vibrations in Metal-Organic Frameworks: From Gate-Opening Phenomenon to Shear-Driven Structural Destabilization

NASA Astrophysics Data System (ADS)

Ryder, Matthew R.; Civalleri, Bartolomeo; Bennett, Thomas D.; Henke, Sebastian; Rudić, Svemir; Cinque, Gianfelice; Fernandez-Alonso, Felix; Tan, Jin-Chong

2014-11-01

We present an unambiguous identification of low-frequency terahertz vibrations in the archetypal imidazole-based metal-organic framework (MOF) materials: ZIF-4, ZIF-7, and ZIF-8, all of which adopt a zeolite-like nanoporous structure. Using inelastic neutron scattering and synchrotron radiation far-infrared absorption spectroscopy, in conjunction with density functional theory (DFT), we have pinpointed all major sources of vibrational modes. Ab initio DFT calculations revealed the complex nature of the collective THz modes, which enable us to establish detailed correlations with experiments. We discover that low-energy conformational dynamics offers multiple pathways to elucidate novel physical phenomena observed in MOFs. New evidence demonstrates that THz modes are intrinsically linked, not only to anomalous elasticity underpinning gate-opening and pore-breathing mechanisms, but also to shear-induced phase transitions and the onset of structural instability.

Positron studies of metal-oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Au, H. L.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-03-01

Positron annihilation spectroscopy provides a new probe to study the properties of interface traps in metal-oxide semiconductors (MOS). Using positrons, we have examined the behavior of the interface traps as a function of gate bias. We propose a simple model to explain the positron annihilation spectra from the interface region of a MOS capacitor.

A transparent electrochromic metal-insulator switching device with three-terminal transistor geometry

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Onozato, Takaki; Hirono, Misako; Mizuno, Taku; Ohta, Hiromichi

2016-05-01

Proton and hydroxyl ion play an essential role for tuning functionality of oxides because their electronic state can be controlled by modifying oxygen off-stoichiometry and/or protonation. Tungsten trioxide (WO3), a well-known electrochromic (EC) material for smart window, is a wide bandgap insulator, whereas it becomes a metallic conductor HxWO3 by protonation. Although one can utilize electrochromism together with metal-insulator (MI) switching for one device, such EC-MI switching cannot be utilized in current EC devices because of their two-terminal structure with parallel-plate configuration. Here we demonstrate a transparent EC-MI switchable device with three-terminal TFT-type structure using amorphous (a-) WO3 channel layer, which was fabricated on glass substrate at room temperature. We used water-infiltrated nano-porous glass, CAN (calcium aluminate with nano-pores), as a liquid-leakage-free solid gate insulator. At virgin state, the device was fully transparent in the visible-light region. For positive gate voltage, the active channel became dark blue, and electrical resistivity of the a-WO3 layer drastically decreased with protonation. For negative gate voltage, deprotonation occurred and the active channel returned to transparent insulator. Good cycleability of the present transparent EC-MI switching device would have potential for the development of advanced smart windows.

Performance and Design Considerations of a Novel Dual-Material Gate Carbon Nanotube Field-Effect Transistors: Nonequilibrium Green's Function Approach

NASA Astrophysics Data System (ADS)

Arefinia, Zahra; Orouji, Ali A.

2009-02-01

The concept of dual-material gate (DMG) is applied to the carbon nanotube field-effect transistor (CNTFET) with doped source and drain extensions, and the features exhibited by the resulting new structure, i.e., the DMG-CNTFET structure, have been examined for the first time by developing a two-dimensional (2D) full quantum simulation. The simulations have been done by the self-consistent solution of 2D Poisson-Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. The results show DMG-CNTFET decreases significantly leakage current and drain conductance and increases on-off current ratio and voltage gain as compared to the single material gate counterparts CNTFET. It is seen that short channel effects in this structure are suppressed because of the perceivable step in the surface potential profile, which screens the drain potential. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate metals. Therefore, this work provides an incentive for further experimental exploration.

A novel high-performance high-frequency SOI MESFET by the damped electric field

NASA Astrophysics Data System (ADS)

Orouji, Ali A.; Khayatian, Ahmad; Keshavarzi, Parviz

2016-06-01

In this paper, we introduce a novel silicon-on-insulator (SOI) metal-semiconductor field-effect-transistor (MESFET) using the damped electric field (DEF). The proposed structure is geometrically symmetric and compatible with common SOI CMOS fabrication processes. It has two additional oxide regions under the side gates in order to improve DC and RF characteristics of the DEF structure due to changes in the electrical potential, the electrical field distributions, and rearrangement of the charge carriers. Improvement of device performance is investigated by two-dimensional and two-carrier simulation of fundamental parameters such as breakdown voltage (VBR), drain current (ID), output power density (Pmax), transconductance (gm), gate-drain and gate-source capacitances, cut-off frequency (fT), unilateral power gain (U), current gain (h21), maximum available gain (MAG), and minimum noise figure (Fmin). The results show that proposed structure operates with higher performances in comparison with the similar conventional SOI structure.

Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri

In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure.more » The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.« less

Scanning gate microscopy of electronic inhomogeneities in single-walled carbon nanotube (SWCNT) devices

NASA Astrophysics Data System (ADS)

Hunt, Steven R.; Collins, Phillip G.

2010-03-01

The electronic properties of graphitic carbon devices are primarily determined by the contact metal and the carbon band structure. However, inhomogeneities such as substrate imperfections, surface defects, and mobile contaminants also contribute and can lead to transistor-like behaviors. We experimentally investigate this phenomena in the 1-D limit using metallic single-walled carbon nanotubes (SWCNTs) before and after the electrochemical creation of sidewall defects. While scanning gate microscopy readily identifies the defect sites, the energy-dependence of the technique allows quantitative analysis of the defects and discrimination of different defect types. This research is partly supported by the NSF (DMR 08-xxxx).

37 CFR 211.4 - Registration of claims of protection in mask works.

Code of Federal Regulations, 2010 CFR

2010-07-01

... adding metal-connection layers to unpersonalized gate arrays may separately register the entire unpersonalized gate array and the custom metallization layers. Applicants seeking to register separately entire unpersonalized gate arrays or custom metallization layers should make the nature of their claim clear at Space 8...

Radiation Effects On Emerging Electronic Materials And Devices

DTIC Science & Technology

2010-01-17

RADIATION EFFECTS ON EMERGING ELECTRONIC MATERIALS AND DEVICES FINAL PERFORMANCE REPORT PREPARED FOR: Kitt Reinhardt AFOSR/NE 875 N...and the other with metal gates and a high-K gate dielectric. These devices were programmed using both back-gate pulse and gate induced drain leakage... metal gate process GIDL method Fig. 1. Sensing margin as a function of total ionizing dose for nMOS 1T-DRAM cells programmed by back-gate pulse and

Fabrication of Ta2O5/GeNx gate insulator stack for Ge metal-insulator-semiconductor structures by electron-cyclotron-resonance plasma nitridation and sputtering deposition techniques

NASA Astrophysics Data System (ADS)

Otani, Yohei; Itayama, Yasuhiro; Tanaka, Takuo; Fukuda, Yukio; Toyota, Hiroshi; Ono, Toshiro; Mitsui, Minoru; Nakagawa, Kiyokazu

2007-04-01

The authors have fabricated germanium (Ge) metal-insulator-semiconductor (MIS) structures with a 7-nm-thick tantalum pentaoxide (Ta2O5)/2-nm-thick germanium nitride (GeNx) gate insulator stack by electron-cyclotron-resonance plasma nitridation and sputtering deposition. They found that pure GeNx ultrathin layers can be formed by the direct plasma nitridation of the Ge surface without substrate heating. X-ray photoelectron spectroscopy revealed no oxidation of the GeNx layer after the Ta2O5 sputtering deposition. The fabricated MIS capacitor with a capacitance equivalent thickness of 4.3nm showed excellent leakage current characteristics. The interface trap density obtained by the modified conductance method was 4×1011cm-2eV-1 at the midgap.

Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

NASA Astrophysics Data System (ADS)

Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

2013-06-01

In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Liu, L.; Lu, H. H.; Lai, P. T.; Tang, W. M.

2015-03-01

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm-2 eV-1 at midgap), smaller gate leakage current (9.5 × 10-5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors using Sc2O3 as the gate oxide and surface passivation

NASA Astrophysics Data System (ADS)

Mehandru, R.; Luo, B.; Kim, J.; Ren, F.; Gila, B. P.; Onstine, A. H.; Abernathy, C. R.; Pearton, S. J.; Gotthold, D.; Birkhahn, R.; Peres, B.; Fitch, R.; Gillespie, J.; Jenkins, T.; Sewell, J.; Via, D.; Crespo, A.

2003-04-01

We demonstrated that Sc2O3 thin films deposited by plasma-assisted molecular-beam epitaxy can be used simultaneously as a gate oxide and as a surface passivation layer on AlGaN/GaN high electron mobility transistors (HEMTs). The maximum drain source current, IDS, reaches a value of over 0.8 A/mm and is ˜40% higher on Sc2O3/AlGaN/GaN transistors relative to conventional HEMTs fabricated on the same wafer. The metal-oxide-semiconductor HEMTs (MOS-HEMTs) threshold voltage is in good agreement with the theoretical value, indicating that Sc2O3 retains a low surface state density on the AlGaN/GaN structures and effectively eliminates the collapse in drain current seen in unpassivated devices. The MOS-HEMTs can be modulated to +6 V of gate voltage. In particular, Sc2O3 is a very promising candidate as a gate dielectric and surface passivant because it is more stable on GaN than is MgO.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

High-Resolution Inkjet-Printed Oxide Thin-Film Transistors with a Self-Aligned Fine Channel Bank Structure.

PubMed

Zhang, Qing; Shao, Shuangshuang; Chen, Zheng; Pecunia, Vincenzo; Xia, Kai; Zhao, Jianwen; Cui, Zheng

2018-05-09

A self-aligned inkjet printing process has been developed to construct small channel metal oxide (a-IGZO) thin-film transistors (TFTs) with independent bottom gates on transparent glass substrates. Poly(methylsilsesquioxane) was used to pattern hydrophobic banks on the transparent substrate instead of commonly used self-assembled octadecyltrichlorosilane. Photolithographic exposure from backside using bottom-gate electrodes as mask formed hydrophilic channel areas for the TFTs. IGZO ink was selectively deposited by an inkjet printer in the hydrophilic channel region and confined by the hydrophobic bank structure, resulting in the precise deposition of semiconductor layers just above the gate electrodes. Inkjet-printed IGZO TFTs with independent gate electrodes of 10 μm width have been demonstrated, avoiding completely printed channel beyond the broad of the gate electrodes. The TFTs showed on/off ratios of 10 8 , maximum mobility of 3.3 cm 2 V -1 s -1 , negligible hysteresis, and good uniformity. This method is conductive to minimizing the area of printed TFTs so as to the development of high-resolution printing displays.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Guest-Induced Switchable Breathing Behavior in a Flexible Metal-Organic Framework with Pronounced Negative Gas Pressure.

PubMed

Shi, Yi-Xiang; Li, Wu-Xiang; Zhang, Wen-Hua; Lang, Jian-Ping

2018-06-29

Flexible metal-organic frameworks (MOFs) have attracted great interest for their dynamically structural transformability in response to external stimuli. Herein, we report a switchable "breathing" or "gate-opening" behavior associated with the phase transformation between a narrow pore (np) and a large pore (lp) in a flexible pillared-layered MOF, denoted as MOF-1 as, which is also confirmed by SCXRD and PXRD. The desolvated phase (MOF-1 des) features a unique stepwise adsorption isotherm for N 2 coupled with a pronounced negative gas adsorption pressure. For comparison, however, no appreciable CO 2 adsorption and gate-opening phenomenon with stepwise sorption can be observed. Furthermore, the polar micropore walls decorated with thiophene groups in MOF-1 des reveals the selective sorption of toluene over benzene and p-xylene associated with self-structural adjustment in spite of the markedly similar physicochemical properties of these vapor molecules.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

PubMed

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-20

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

NASA Astrophysics Data System (ADS)

Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

2018-07-01

We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

Statistical evaluation of metal fill widths for emulated metal fill in parasitic extraction methodology

NASA Astrophysics Data System (ADS)

J-Me, Teh; Noh, Norlaili Mohd.; Aziz, Zalina Abdul

2015-05-01

In the chip industry today, the key goal of a chip development organization is to develop and market chips within a short time frame to gain foothold on market share. This paper proposes a design flow around the area of parasitic extraction to improve the design cycle time. The proposed design flow utilizes the usage of metal fill emulation as opposed to the current flow which performs metal fill insertion directly. By replacing metal fill structures with an emulation methodology in earlier iterations of the design flow, this is targeted to help reduce runtime in fill insertion stage. Statistical design of experiments methodology utilizing the randomized complete block design was used to select an appropriate emulated metal fill width to improve emulation accuracy. The experiment was conducted on test cases of different sizes, ranging from 1000 gates to 21000 gates. The metal width was varied from 1 x minimum metal width to 6 x minimum metal width. Two-way analysis of variance and Fisher's least significant difference test were used to analyze the interconnect net capacitance values of the different test cases. This paper presents the results of the statistical analysis for the 45 nm process technology. The recommended emulated metal fill width was found to be 4 x the minimum metal width.

SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

NASA Astrophysics Data System (ADS)

Yongliang, Li; Qiuxia, Xu

2009-12-01

Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

Conformational plasticity in the selectivity filter of the TRPV2 ion channel.

PubMed

Zubcevic, Lejla; Le, Son; Yang, Huanghe; Lee, Seok-Yong

2018-05-01

Transient receptor potential vanilloid (TRPV) channels are activated by ligands and heat and are involved in various physiological processes. In contrast to the architecturally related voltage-gated cation channels, TRPV1 and TRPV2 subtypes possess another activation gate at the selectivity filter that can open widely enough to permeate large organic cations. Despite recent structural advances, the mechanism of selectivity filter gating and permeation for both metal ions and large molecules by TRPV1 or TRPV2 is not well known. Here, we determined two crystal structures of rabbit TRPV2 in its Ca 2+ -bound and resiniferatoxin (RTx)- and Ca 2+ -bound forms, to 3.9 Å and 3.1 Å, respectively. Notably, our structures show that RTx binding leads to two-fold symmetric opening of the selectivity filter of TRPV2 that is wide enough for large organic cation permeation. Combined with functional characterizations, our studies reveal a structural basis for permeation of Ca 2+ and large organic cations in TRPV2.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Photolithographically Patterned TiO2 Films for Electrolyte-Gated Transistors.

PubMed

Valitova, Irina; Kumar, Prajwal; Meng, Xiang; Soavi, Francesca; Santato, Clara; Cicoira, Fabio

2016-06-15

Metal oxides constitute a class of materials whose properties cover the entire range from insulators to semiconductors to metals. Most metal oxides are abundant and accessible at moderate cost. Metal oxides are widely investigated as channel materials in transistors, including electrolyte-gated transistors, where the charge carrier density can be modulated by orders of magnitude upon application of relatively low electrical bias (2 V). Electrolyte gating offers the opportunity to envisage new applications in flexible and printed electronics as well as to improve our current understanding of fundamental processes in electronic materials, e.g. insulator/metal transitions. In this work, we employ photolithographically patterned TiO2 films as channels for electrolyte-gated transistors. TiO2 stands out for its biocompatibility and wide use in sensing, electrochromics, photovoltaics and photocatalysis. We fabricated TiO2 electrolyte-gated transistors using an original unconventional parylene-based patterning technique. By using a combination of electrochemical and charge carrier transport measurements we demonstrated that patterning improves the performance of electrolyte-gated TiO2 transistors with respect to their unpatterned counterparts. Patterned electrolyte-gated (EG) TiO2 transistors show threshold voltages of about 0.9 V, ON/OFF ratios as high as 1 × 10(5), and electron mobility above 1 cm(2)/(V s).

Gate control of spin-polarized conductance in alloyed transitional metal nanocontacts

NASA Astrophysics Data System (ADS)

Sivkov, Ilia N.; Brovko, Oleg O.; Rungger, Ivan; Stepanyuk, Valeri S.

2017-03-01

To date, endeavors in nanoscale spintronics are dominated by the use of single-electron or single-spin transistors having at their heart a semiconductor, metallic, or molecular quantum dot whose localized states are non-spin-degenerate and can be controlled by an external bias applied via a gate electrode. Adjusting the bias of the gate one can realign those states with respect to the chemical potentials of the leads and thus tailor the spin-polarized transmission properties of the device. Here we show that similar functionality can be achieved in a purely metallic junction comprised of a metallic magnetic chain attached to metallic paramagnetic leads and biased by a gate electrode. Our ab initio calculations of electron transport through mixed Pt-Fe (Fe-Pd and Fe-Rh) atomic chains suspended between Pt (Pd and Rh) electrodes show that spin-polarized confined states of the chain can be shifted by the gate bias causing a change in the relative contributions of majority and minority channels to the nanocontact's conductance. As a result, we observe strong dependence of conductance spin polarization on the applied gate potential. In some cases the spin polarization of conductance can even be reversed in sign upon gate potential application, which is a remarkable and promising trait for spintronic applications.

Tuning the metal-insulator crossover and magnetism in SrRuO 3 by ionic gating

DOE PAGES

Yi, Hee Taek; Gao, Bin; Xie, Wei; ...

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. We report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO 3. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90–250 K and 70–100 K,more » respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.« less

Tuning the metal-insulator crossover and magnetism in SrRuO₃ by ionic gating.

PubMed

Yi, Hee Taek; Gao, Bin; Xie, Wei; Cheong, Sang-Wook; Podzorov, Vitaly

2014-10-13

Reversible control of charge transport and magnetic properties without degradation is a key for device applications of transition metal oxides. Chemical doping during the growth of transition metal oxides can result in large changes in physical properties, but in most of the cases irreversibility is an inevitable constraint. Here we report a reversible control of charge transport, metal-insulator crossover and magnetism in field-effect devices based on ionically gated archetypal oxide system - SrRuO₃. In these thin-film devices, the metal-insulator crossover temperature and the onset of magnetoresistance can be continuously and reversibly tuned in the range 90-250 K and 70-100 K, respectively, by application of a small gate voltage. We infer that a reversible diffusion of oxygen ions in the oxide lattice dominates the response of these materials to the gate electric field. These findings provide critical insights into both the understanding of ionically gated oxides and the development of novel applications.

Interface band alignment in high-k gate stacks

NASA Astrophysics Data System (ADS)

Eric, Bersch; Hartlieb, P.

2005-03-01

In order to successfully implement alternate high-K dielectric materials into MOS structures, the interface properties of MOS gate stacks must be better understood. Dipoles that may form at the metal/dielectric and dielectric/semiconductor interfaces make the band offsets difficult to predict. We have measured the conduction and valence band densities of states for a variety MOS stacks using in situ using inverse photoemission (IPE) and photoemission spectroscopy (PES), respectively. Results obtained from clean and metallized (with Ru or Al) HfO2/Si, SiO2/Si and mixed silicate films will be presented. IPE indicates a shift of the conduction band minimum (CBM) to higher energy (i.e. away from EF) with increasing SiO2. The effect of metallization on the location of band edges depends upon the metal species. The addition of N to the dielectrics shifts the CBM in a way that is thickness dependent. Possible mechanisms for these observed effects will be discussed.

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

NASA Astrophysics Data System (ADS)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Scanning gate study of organic thin-film field-effect transistor

NASA Astrophysics Data System (ADS)

Aoki, N.; Sudou, K.; Matsusaki, K.; Okamoto, K.; Ochiai, Y.

2008-03-01

Scanning gate microscopy (SGM) has been applied for a study of organic thin-film field effect transistor (OFET). In contrast to one-dimensional nano-material such a carbon nanonube or nano-structure such a quantum point contact, visualization a transport characteristic of OFET channel is basically rather difficult since the channel width is much larger than the size of the SGM tip. Nevertheless, Schottky barriers are successfully visualized at the boundary between the metal electrodes and the OFET channel at ambient atmosphere.

Positron annihilation at the Si/SiO2 interface

NASA Astrophysics Data System (ADS)

Leung, T. C.; Weinberg, Z. A.; Asoka-Kumar, P.; Nielsen, B.; Rubloff, G. W.; Lynn, K. G.

1992-01-01

Variable-energy positron annihilation depth-profiling has been applied to the study of the Si/SiO2 interface in Al-gate metal-oxide-semiconductor (MOS) structures. For both n- and p-type silicon under conditions of negative gate bias, the positron annihilation S-factor characteristic of the interface (Sint) is substantially modified. Temperature and annealing behavior, combined with known MOS physics, suggest strongly that Sint depends directly on holes at interface states or traps at the Si/SiO2 interface.

Voltage-dependent conformational changes in connexin channels.

PubMed

Bargiello, Thaddeus A; Tang, Qingxiu; Oh, Seunghoon; Kwon, Taekyung

2012-08-01

Channels formed by connexins display two distinct types of voltage-dependent gating, termed V(j)- or fast-gating and loop- or slow-gating. Recent studies, using metal bridge formation and chemical cross-linking have identified a region within the channel pore that contributes to the formation of the loop-gate permeability barrier. The conformational changes are remarkably large, reducing the channel pore diameter from 15 to 20Å to less than 4Å. Surprisingly, the largest conformational change occurs in the most stable region of the channel pore, the 3(10) or parahelix formed by amino acids in the 42-51 segment. The data provide a set of positional constraints that can be used to model the structure of the loop-gate closed state. Less is known about the conformation of the V(j)-gate closed state. There appear to be two different mechanisms; one in which conformational changes in channel structure are linked to a voltage sensor contained in the N-terminus of Cx26 and Cx32 and a second in which the C-terminus of Cx43 and Cx40 may act either as a gating particle to block the channel pore or alternatively to stabilize the closed state. The later mechanism utilizes the same domains as implicated in effecting pH gating of Cx43 channels. It is unclear if the two V(j)-gating mechanisms are related or if they represent different gating mechanisms that operate separately in different subsets of connexin channels. A model of the V(j)-closed state of Cx26 hemichannel that is based on the X-ray structure of Cx26 and electron crystallographic structures of a Cx26 mutation suggests that the permeability barrier for V(j)-gating is formed exclusively by the N-terminus, but recent information suggests that this conformation may not represent a voltage-closed state. Closed state models are considered from a thermodynamic perspective based on information from the 3.5Å Cx26 crystal structure and molecular dynamics (MD) simulations. The applications of computational and experimental methods to define the path of allosteric molecular transitions that link the open and closed states are discussed. This article is part of a Special Issue entitled: The Communicating junctions, composition, structure and characteristics. Copyright © 2011 Elsevier B.V. All rights reserved.

All 2D, high mobility, flexible, transparent thin film transistor

DOEpatents

Das, Saptarshi; Sumant, Anirudha V.; Roelofs, Andreas

2017-01-17

A two-dimensional thin film transistor and a method for manufacturing a two-dimensional thin film transistor includes layering a semiconducting channel material on a substrate, providing a first electrode material on top of the semiconducting channel material, patterning a source metal electrode and a drain metal electrode at opposite ends of the semiconducting channel material from the first electrode material, opening a window between the source metal electrode and the drain metal electrode, removing the first electrode material from the window located above the semiconducting channel material providing a gate dielectric above the semiconducting channel material, and providing a top gate above the gate dielectric, the top gate formed from a second electrode material. The semiconducting channel material is made of tungsten diselenide, the first electrode material and the second electrode material are made of graphene, and the gate dielectric is made of hexagonal boron nitride.

Thin Film Transistors On Plastic Substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

2004-01-20

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250.degree. C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Dual metal gate tunneling field effect transistors based on MOSFETs: A 2-D analytical approach

NASA Astrophysics Data System (ADS)

Ramezani, Zeinab; Orouji, Ali A.

2018-01-01

A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed Tunneling FET is extracted from a MOSFET structure by employing an additional electrode in the source region with an appropriate work function to induce holes in the N+ source region and hence makes it as a P+ source region. The electric field is derived which is utilized to extract the expression of the drain current by analytically integrating the band to band tunneling generation rate in the tunneling region based on the potential profile by solving the Poisson's equation. Through this model, the effects of the thin film thickness and gate voltage on the potential, the electric field, and the effects of the thin film thickness on the tunneling current can be studied. To validate our present model we use SILVACO ATLAS device simulator and the analytical results have been compared with it and found a good agreement.

First-principles simulations of Graphene/Transition-metal-Dichalcogenides/Graphene Field-Effect Transistor

NASA Astrophysics Data System (ADS)

Li, Xiangguo; Wang, Yun-Peng; Zhang, X.-G.; Cheng, Hai-Ping

A prototype field-effect transistor (FET) with fascinating properties can be made by assembling graphene and two-dimensional insulating crystals into three-dimensional stacks with atomic layer precision. Transition metal dichalcogenides (TMDCs) such as WS2, MoS2 are good candidates for the atomically thin barrier between two layers of graphene in the vertical FET due to their sizable bandgaps. We investigate the electronic properties of the Graphene/TMDCs/Graphene sandwich structure using first-principles method. We find that the effective tunnel barrier height of the TMDC layers in contact with the graphene electrodes has a layer dependence and can be modulated by a gate voltage. Consequently a very high ON/OFF ratio can be achieved with appropriate number of TMDC layers and a suitable range of the gate voltage. The spin-orbit coupling in TMDC layers is also layer dependent but unaffected by the gate voltage. These properties can be important in future nanoelectronic device designs. DOE/BES-DE-FG02-02ER45995; NERSC.

High-κ/Metal Gate Science and Technology

NASA Astrophysics Data System (ADS)

Guha, Supratik; Narayanan, Vijay

2009-08-01

High-κ/metal gate technology is on the verge of replacing conventional oxynitride dielectrics in state-of-the-art transistors for both high-performance and low-power applications. In this review we discuss some of the key materials issues that complicated the introduction of high-κ dielectrics, including reduced electron mobility, oxygen-based thermal instabilities, and the absence of thermally stable dual-metal electrodes. We show that through a combination of materials innovations and engineering ingenuity these issues were successfully overcome, thereby paving the way for high-κ/metal gate implementation.

Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

NASA Astrophysics Data System (ADS)

Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

2018-04-01

We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

Subunit Dissociation and Metal Binding by Escherichia coli apo-Manganese Superoxide Dismutase

PubMed Central

Whittaker, Mei M.; Lerch, Thomas F.; Kirillova, Olga; Chapman, Michael S.; Whittaker, James W.

2010-01-01

Metal binding by apo-manganese superoxide dismutase (apo-MnSOD) is essential for functional maturation of the enzyme. Previous studies have demonstrated that metal binding by apo-MnSOD is conformationally gated, requiring protein reorganization for the metal to bind. We have now solved the X-ray crystal structure of apo-MnSOD at 1.9 Å resolution. The organization of active site residues is independent of the presence of the metal cofactor, demonstrating that protein itself templates the unusual metal coordination geometry. Electrophoretic analysis of mixtures of apo- and (Mn2)-MnSOD, dye-conjugated protein, or C-terminal Strep-tag II fusion protein reveals a dynamic subunit exchange process associated with cooperative metal binding by the two subunits of the dimeric protein. In contrast, (S126C) (SS) apo-MnSOD, which contains an inter-subunit covalent disulfide crosslink, exhibits anticooperative metal binding. The protein concentration dependence of metal uptake kinetics implies that protein dissociation is involved in metal binding by the wild type apo-protein, although other processes may also contribute to gating metal uptake. Protein concentration dependent small-zone size exclusion chromatography is consistent with apo-MnSOD dimer dissociation at low protein concentration (KD = 1×10−6 M). Studies on metal uptake by apo-MnSOD in Escherichia coli cells show that the protein exhibits similar behavior in vivo and in vitro. PMID:21044611

Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

NASA Astrophysics Data System (ADS)

Kim, Young-Hee

Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is still necessary to understand what is intrinsic we can not change, or what is extrinsic one we can improve.

Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

NASA Astrophysics Data System (ADS)

Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

2018-04-01

The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

FLUID PRESSURE AND CAM OPERATED VACUUM VALVE

DOEpatents

Batzer, T.H.

1963-11-26

An ultra-high vacuum valve that is bakable, reusable, and capable of being quickly opened and closed is described. A translationally movable valve gate having an annular ridge is adapted to contact an annular soft metal gasket disposed at the valve seat such that the soft metal gasket extends beyond the annular ridge on all sides. The valve gate is closed, by first laterally aligning the valve gate with the valve seat and then bringing the valve gate and valve seat into seating contact by the translational movement of a ramp-like wedging means that engages similar ramp-like stractures at the base of the valve gate to force the valve gate into essentially pressureless contact with the annular soft metal gasket. This gasket is then pressurized from beneath by a fluid thereby effecting a vacuura tight seal between the gasket and the ridge. (AEC)

Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

NASA Astrophysics Data System (ADS)

Kitano, Naomu; Horie, Shinya; Arimura, Hiroaki; Kawahara, Takaaki; Sakashita, Shinsuke; Nishida, Yukio; Yugami, Jiro; Minami, Takashi; Kosuda, Motomu; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2007-12-01

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal-insulator-semiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (Vth) were realized by reducing the carbon impurity in the gate stacks and improving the Vth stability against thermal treatment. As a result, we obtained superior current drivability (Ion = 350 μA/μm at Ioff = 200 pA/μm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Nano-scale zirconia and hafnia dielectrics grown by atomic layer deposition: Crystallinity, interface structures and electrical properties

NASA Astrophysics Data System (ADS)

Kim, Hyoungsub

With the continued scaling of transistors, leakage current densities across the SiO2 gate dielectric have increased enormously through direct tunneling. Presently, metal oxides having higher dielectric constants than SiO2 are being investigated to reduce the leakage current by increasing the physical thickness of the dielectric. Many possible techniques exist for depositing high-kappa gate dielectrics. Atomic layer deposition (ALD) has drawn attention as a method for preparing ultrathin metal oxide layers with excellent electrical characteristics and near-perfect film conformality due to the layer-by-layer nature of the deposition mechanism. For this research, an ALD system using ZrCl4/HfCl4 and H2O was built and optimized. The microstructural and electrical properties of ALD-ZrO2 and HfO2 grown on SiO2/Si substrates were investigated and compared using various characterization tools. In particular, the crystallization kinetics of amorphous ALD-HfO2 films were studied using in-situ annealing experiments in a TEM. The effect of crystallization on the electrical properties of ALD-HfO 2 was also investigated using various in-situ and ex-situ post-deposition anneals. Our results revealed that crystallization had little effect on the magnitude of the gate leakage current or on the conduction mechanisms. Building upon the results for each metal oxide separately, more advanced investigations were made. Several nanolaminate structures using ZrO2 and HfO2 with different sequences and layer thicknesses were characterized. The effects of the starting microstructure on the microstructural evolution of nanolaminate stacks were studied. Additionally, a promising new approach for engineering the thickness of the SiO2-based interface layer between the metal oxide and silicon substrate after deposition of the metal oxide layer was suggested. Through experimental measurements and thermodynamic analysis, it is shown that a Ti overlayer, which exhibits a high oxygen solubility, can effectively getter oxygen from the interface layer, thus decomposing SiO2 and reducing the interface layer thickness in a controllable fashion. As one of several possible applications, ALD-ZrO2 and HfO 2 gate dielectric films were deposited on Ge (001) substrates with different surface passivations. After extensive characterization using various microstructural, electrical, and chemical analyses, excellent MOS electrical properties of high-kappa gate dielectrics on Ge were successfully demonstrated with optimized surface nitridation of the Ge substrates.

Study of SiO2-Si and metal-oxide-semiconductor structures using positrons

NASA Astrophysics Data System (ADS)

Leung, T. C.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-01-01

Studies of SiO2-Si and metal-oxide-semiconductor (MOS) structures using positrons are summarized and a concise picture of the present understanding of positrons in these systems is provided. Positron annihilation line-shape S data are presented as a function of the positron incident energy, gate voltage, and annealing, and are described with a diffusion-annihilation equation for positrons. The data are compared with electrical measurements. Distinct annihilation characteristics were observed at the SiO2-Si interface and have been studied as a function of bias voltage and annealing conditions. The shift of the centroid (peak) of γ-ray energy distributions in the depletion region of the MOS structures was studied as a function of positron energy and gate voltage, and the shifts are explained by the corresponding variations in the strength of the electric field and thickness of the depletion layer. The potential role of the positron annihilation technique as a noncontact, nondestructive, and depth-sensitive characterization tool for the technologically important, deeply buried interface is shown.

Nanowire systems: technology and design

PubMed Central

Gaillardon, Pierre-Emmanuel; Amarù, Luca Gaetano; Bobba, Shashikanth; De Marchi, Michele; Sacchetto, Davide; De Micheli, Giovanni

2014-01-01

Nanosystems are large-scale integrated systems exploiting nanoelectronic devices. In this study, we consider double independent gate, vertically stacked nanowire field effect transistors (FETs) with gate-all-around structures and typical diameter of 20 nm. These devices, which we have successfully fabricated and evaluated, control the ambipolar behaviour of the nanostructure by selectively enabling one type of carriers. These transistors work as switches with electrically programmable polarity and thus realize an exclusive or operation. The intrinsic higher expressive power of these FETs, when compared with standard complementary metal oxide semiconductor technology, enables us to realize more efficient logic gates, which we organize as tiles to realize nanowire systems by regular arrays. This article surveys both the technology for double independent gate FETs as well as physical and logic design tools to realize digital systems with this fabrication technology. PMID:24567471

Fabrication and independent control of patterned polymer gate for a few-layer WSe{sub 2} field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hong, Sung Ju; Park, Min; Kang, Hojin

We report the fabrication of a patterned polymer electrolyte for a two-dimensional (2D) semiconductor, few-layer tungsten diselenide (WSe{sub 2}) field-effect transistor (FET). We expose an electron-beam in a desirable region to form the patterned structure. The WSe{sub 2} FET acts as a p-type semiconductor in both bare and polymer-covered devices. We observe a highly efficient gating effect in the polymer-patterned device with independent gate control. The patterned polymer gate operates successfully in a molybdenum disulfide (MoS{sub 2}) FET, indicating the potential for general applications to 2D semiconductors. The results of this study can contribute to large-scale integration and better flexibilitymore » in transition metal dichalcogenide (TMD)-based electronics.« less

Gate tunneling current and quantum capacitance in metal-oxide-semiconductor devices with graphene gate electrodes

NASA Astrophysics Data System (ADS)

An, Yanbin; Shekhawat, Aniruddh; Behnam, Ashkan; Pop, Eric; Ural, Ant

2016-11-01

Metal-oxide-semiconductor (MOS) devices with graphene as the metal gate electrode, silicon dioxide with thicknesses ranging from 5 to 20 nm as the dielectric, and p-type silicon as the semiconductor are fabricated and characterized. It is found that Fowler-Nordheim (F-N) tunneling dominates the gate tunneling current in these devices for oxide thicknesses of 10 nm and larger, whereas for devices with 5 nm oxide, direct tunneling starts to play a role in determining the total gate current. Furthermore, the temperature dependences of the F-N tunneling current for the 10 nm devices are characterized in the temperature range 77-300 K. The F-N coefficients and the effective tunneling barrier height are extracted as a function of temperature. It is found that the effective barrier height decreases with increasing temperature, which is in agreement with the results previously reported for conventional MOS devices with polysilicon or metal gate electrodes. In addition, high frequency capacitance-voltage measurements of these MOS devices are performed, which depict a local capacitance minimum under accumulation for thin oxides. By analyzing the data using numerical calculations based on the modified density of states of graphene in the presence of charged impurities, it is shown that this local minimum is due to the contribution of the quantum capacitance of graphene. Finally, the workfunction of the graphene gate electrode is extracted by determining the flat-band voltage as a function of oxide thickness. These results show that graphene is a promising candidate as the gate electrode in metal-oxide-semiconductor devices.

Threading the biophysics of mammalian Slo1 channels onto structures of an invertebrate Slo1 channel

PubMed Central

2017-01-01

For those interested in the machinery of ion channel gating, the Ca2+ and voltage-activated BK K+ channel provides a compelling topic for investigation, by virtue of its dual allosteric regulation by both voltage and intracellular Ca2+ and because its large-single channel conductance facilitates detailed kinetic analysis. Over the years, biophysical analyses have illuminated details of the allosteric regulation of BK channels and revealed insights into the mechanism of BK gating, e.g., inner cavity size and accessibility and voltage sensor-pore coupling. Now the publication of two structures of an Aplysia californica BK channel—one liganded and one metal free—promises to reinvigorate functional studies and interpretation of biophysical results. The new structures confirm some of the previous functional inferences but also suggest new perspectives regarding cooperativity between Ca2+-binding sites and the relationship between voltage- and Ca2+-dependent gating. Here we consider the extent to which the two structures explain previous functional data on pore-domain properties, voltage-sensor motions, and divalent cation binding and activation of the channel. PMID:29025867

Gate-controlled topological conducting channels in bilayer graphene

NASA Astrophysics Data System (ADS)

Li, Jing; Wang, Ke; McFaul, Kenton J.; Zern, Zachary; Ren, Yafei; Watanabe, Kenji; Taniguchi, Takashi; Qiao, Zhenhua; Zhu, Jun

2016-12-01

The existence of inequivalent valleys K and K‧ in the momentum space of 2D hexagonal lattices provides a new electronic degree of freedom, the manipulation of which can potentially lead to new types of electronics, analogous to the role played by electron spin. In materials with broken inversion symmetry, such as an electrically gated bilayer graphene (BLG), the momentum-space Berry curvature Ω carries opposite sign in the K and K‧ valleys. A sign reversal of Ω along an internal boundary of the sheet gives rise to counterpropagating 1D conducting modes encoded with opposite-valley indices. These metallic states are topologically protected against backscattering in the absence of valley-mixing scattering, and thus can carry current ballistically. In BLG, the reversal of Ω can occur at the domain wall of AB- and BA-stacked domains, or at the line junction of two oppositely gated regions. The latter approach can provide a scalable platform to implement valleytronic operations, such as valves and waveguides, but it is technically challenging to realize. Here, we fabricate a dual-split-gate structure in BLG and present evidence of the predicted metallic states in electrical transport. The metallic states possess a mean free path (MFP) of up to a few hundred nanometres in the absence of a magnetic field. The application of a perpendicular magnetic field suppresses the backscattering significantly and enables a junction 400 nm in length to exhibit conductance close to the ballistic limit of 4e2/h at 8 T. Our experiment paves the way to the realization of gate-controlled ballistic valley transport and the development of valleytronic applications in atomically thin materials.

Development of non-volatile semiconductor memory

NASA Technical Reports Server (NTRS)

Heikkila, W. W.

1979-01-01

A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

NASA Astrophysics Data System (ADS)

Lagger, P.; Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J.; Pogany, D.; Ostermaier, C.

2014-07-01

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Spin-dependent transport and current modulation in a current-in-plane spin-valve field-effect transistor

NASA Astrophysics Data System (ADS)

Kanaki, Toshiki; Koyama, Tomohiro; Chiba, Daichi; Ohya, Shinobu; Tanaka, Masaaki

2016-10-01

We propose a current-in-plane spin-valve field-effect transistor (CIP-SV-FET), which is composed of a ferromagnet/nonferromagnet/ferromagnet trilayer structure and a gate electrode. This is a promising device alternative to spin metal-oxide-semiconductor field-effect transistors. Here, we fabricate a ferromagnetic-semiconductor GaMnAs-based CIP-SV-FET and demonstrate its basic operation of the resistance modulation both by the magnetization configuration and by the gate electric field. Furthermore, we present the electric-field-assisted magnetization reversal in this device.

Micromachined mold-type double-gated metal field emitters

NASA Astrophysics Data System (ADS)

Lee, Yongjae; Kang, Seokho; Chun, Kukjin

1997-12-01

Electron field emitters with double gates were fabricated using micromachining technology and the effect of the electric potential of the focusing gate (or second gate) was experimentally evaluated. The molybdenum field emission tip was made by filling a cusplike mold formed when a conformal film was deposited on the hole-trench that had been patterned on stacked metals and dielectric layers. The hole-trench was patterned by electron beam lithography and reactive ion etching. Each field emitter has a 0960-1317/7/4/009/img1 diameter extraction gate (or first gate) and a 0960-1317/7/4/009/img2 diameter focusing gate (or second gate). To make a path for the emitted electrons, silicon bulk was etched anisotropically in KOH and EDP (ethylene-diamine pyrocatechol) solution successively. The I - V characteristics and anode current change due to the focusing gate potential were measured.

Electric-field control of conductance in metal quantum point contacts by electric-double-layer gating

NASA Astrophysics Data System (ADS)

Shibata, K.; Yoshida, K.; Daiguji, K.; Sato, H.; , T., Ii; Hirakawa, K.

2017-10-01

An electric-field control of quantized conductance in metal (gold) quantum point contacts (QPCs) is demonstrated by adopting a liquid-gated electric-double-layer (EDL) transistor geometry. Atomic-scale gold QPCs were fabricated by applying the feedback-controlled electrical break junction method to the gold nanojunction. The electric conductance in gold QPCs shows quantized conductance plateaus and step-wise increase/decrease by the conductance quantum, G0 = 2e2/h, as EDL-gate voltage is swept, demonstrating a modulation of the conductance of gold QPCs by EDL gating. The electric-field control of conductance in metal QPCs may open a way for their application to local charge sensing at room temperature.

Defectivity control of aluminum chemical mechanical planarization in replacement metal gate process of MOSFET

NASA Astrophysics Data System (ADS)

Jin, Zhang; Yuling, Liu; Chenqi, Yan; Yangang, He; Baohong, Gao

2016-04-01

The replacement metal gate (RMG) defectivity performance control is very challenging in high-k metal gate (HKMG) chemical mechanical polishing (CMP). In this study, three major defect types, including fall-on particles, micro-scratch and corrosion have been investigated. The research studied the effects of polishing pad, pressure, rotating speed, flow rate and post-CMP cleaning on the three kinds of defect, which finally eliminated the defects and achieved good surface morphology. This study will provide an important reference value for the future research of aluminum metal gate CMP. Project supported by the Major National Science and Technology Special Projects (No. 2009ZX02308), the Natural Science Foundation for the Youth of Hebei Province (Nos. F2012202094, F2015202267), and the Outstanding Youth Science and Technology Innovation Fund of Hebei University of Technology (No. 2013010).

Fabrication of quantum dots in undoped Si/Si 0.8Ge 0.2 heterostructures using a single metal-gate layer

DOE PAGES

Lu, T. M.; Gamble, J. K.; Muller, R. P.; ...

2016-08-01

Enhancement-mode Si/SiGe electron quantum dots have been pursued extensively by many groups for their potential in quantum computing. Most of the reported dot designs utilize multiple metal-gate layers and use Si/SiGe heterostructures with Ge concentration close to 30%. Here, we report the fabrication and low-temperature characterization of quantum dots in the Si/Si 0.8Ge 0.2 heterostructures using only one metal-gate layer. We find that the threshold voltage of a channel narrower than 1 μm increases as the width decreases. The higher threshold can be attributed to the combination of quantum confinement and disorder. We also find that the lower Ge ratiomore » used here leads to a narrower operational gate bias range. The higher threshold combined with the limited gate bias range constrains the device design of lithographic quantum dots. We incorporate such considerations in our device design and demonstrate a quantum dot that can be tuned from a single dot to a double dot. Furthermore, the device uses only a single metal-gate layer, greatly simplifying device design and fabrication.« less

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

PubMed Central

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R.J. Dwayne

2016-01-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence. PMID:28008918

Measurement of transverse emittance and coherence of double-gate field emitter array cathodes

NASA Astrophysics Data System (ADS)

Tsujino, Soichiro; Das Kanungo, Prat; Monshipouri, Mahta; Lee, Chiwon; Miller, R. J. Dwayne

2016-12-01

Achieving small transverse beam emittance is important for high brightness cathodes for free electron lasers and electron diffraction and imaging experiments. Double-gate field emitter arrays with on-chip focussing electrode, operating with electrical switching or near infrared laser excitation, have been studied as cathodes that are competitive with photocathodes excited by ultraviolet lasers, but the experimental demonstration of the low emittance has been elusive. Here we demonstrate this for a field emitter array with an optimized double-gate structure by directly measuring the beam characteristics. Further we show the successful application of the double-gate field emitter array to observe the low-energy electron beam diffraction from suspended graphene in minimal setup. The observed low emittance and long coherence length are in good agreement with theory. These results demonstrate that our all-metal double-gate field emitters are highly promising for applications that demand extremely low-electron bunch-phase space volume and large transverse coherence.

Analysis of electric field distribution in GaAs metal-semiconductor field effect transistor with a field-modulating plate

NASA Astrophysics Data System (ADS)

Hori, Yasuko; Kuzuhara, Masaaki; Ando, Yuji; Mizuta, Masashi

2000-04-01

Electric field distribution in the channel of a field effect transistor (FET) with a field-modulating plate (FP) has been theoretically investigated using a two-dimensional ensemble Monte Carlo simulation. This analysis revealed that the introduction of FP is effective in canceling the influence of surface traps under forward bias conditions and in reducing the electric field intensity at the drain side of the gate edge under pinch-off bias conditions. This study also found that a partial overlap of the high-field region under the gate and that at the FP electrode is important for reducing the electric field intensity. The optimized metal-semiconductor FET with FP (FPFET) (LGF˜0.2 μm) exhibited a much lower peak electric field intensity than a conventional metal-semiconductor FET. Based on these numerically calculated results, we have proposed a design procedure to optimize the power FPFET structure with extremely high breakdown voltages while maintaining reasonable gain performance.

Improving off-state leakage characteristics for high voltage AlGaN/GaN-HFETs on Si substrates

NASA Astrophysics Data System (ADS)

Moon, Sung-Woon; Twynam, John; Lee, Jongsub; Seo, Deokwon; Jung, Sungdal; Choi, Hong Goo; Shim, Heejae; Yim, Jeong Soon; Roh, Sungwon D.

2014-06-01

We present a reliable process and design technique for realizing high voltage AlGaN/GaN hetero-junction field effect transistors (HFETs) on Si substrates with very low and stable off-state leakage current characteristics. In this work, we have investigated the effects of the surface passivation layer, prepared by low pressure chemical vapor deposition (LPCVD) of silicon nitride (SiNx), and gate bus isolation design on the off-state leakage characteristics of metal-oxide-semiconductor (MOS) gate structure-based GaN HFETs. The surface passivated devices with gate bus isolation fully surrounding the source and drain regions showed extremely low off-state leakage currents of less than 20 nA/mm at 600 V, with very small variation. These techniques were successfully applied to high-current devices with 80-mm gate width, yielding excellent off-state leakage characteristics within a drain voltage range 0-700 V.

Rectification of graphene self-switching diodes: First-principles study

NASA Astrophysics Data System (ADS)

Ghaziasadi, Hassan; Jamasb, Shahriar; Nayebi, Payman; Fouladian, Majid

2018-05-01

The first principles calculations based on self-consistent charge density functional tight-binding have performed to investigate the electrical properties and rectification behavior of the graphene self-switching diodes (GSSD). The devices contained two structures called CG-GSSD and DG-GSSD which have metallic or semiconductor gates depending on their side gates have a single or double hydrogen edge functionalized. We have relaxed the devices and calculated I-V curves, transmission spectrums and maximum rectification ratios. We found that the DG-MSM devices are more favorable and more stable. Also, the DG-MSM devices have better maximum rectification ratios and current. Moreover, by changing the side gates widths and behaviors from semiconductor to metal, the threshold voltages under forward bias changed from +1.2 V to +0.3 V. Also, the maximum currents are obtained from 1.12 μA to 10.50 μA. Finally, the MSM and SSS type of all devices have minimum and maximum values of voltage threshold and maximum rectification ratios, but the 769-DG devices don't obey this rule.

Pseudo 2-transistor active pixel sensor using an n-well/gate-tied p-channel metal oxide semiconductor field eeffect transistor-type photodetector with built-in transfer gate

NASA Astrophysics Data System (ADS)

Seo, Sang-Ho; Seo, Min-Woong; Kong, Jae-Sung; Shin, Jang-Kyoo; Choi, Pyung

2008-11-01

In this paper, a pseudo 2-transistor active pixel sensor (APS) has been designed and fabricated by using an n-well/gate-tied p-channel metal oxide semiconductor field effect transistor (PMOSFET)-type photodetector with built-in transfer gate. The proposed sensor has been fabricated using a 0.35 μm 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) logic process. The pseudo 2-transistor APS consists of two NMOSFETs and one photodetector which can amplify the generated photocurrent. The area of the pseudo 2-transistor APS is 7.1 × 6.2 μm2. The sensitivity of the proposed pixel is 49 lux/(V·s). By using this pixel, a smaller pixel area and a higher level of sensitivity can be realized when compared with a conventional 3-transistor APS which uses a pn junction photodiode.

Field ion source development for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Holland, C. E.; Resnick, P. J.; Hertz, K. L.; Chichester, D. L.

2012-01-01

An ion source based on the principles of electrostatic field desorption is being developed to improve the performance of existing compact neutron generators. The ion source is an array of gated metal tips derived from field electron emitter array microfabrication technology. A comprehensive summary of development and experimental activities is presented. Many structural modifications to the arrays have been incorporated to achieve higher tip operating fields, while lowering fields at the gate electrode to prevent gate field electron emission which initiates electrical breakdown in the array. The latest focus of fabrication activities has been on rounding the gate electrode edge and surrounding the gate electrode with dielectric material. Array testing results have indicated a steady progression of increased array tip operating fields with each new design tested. The latest arrays have consistently achieved fields beyond those required for the onset of deuterium desorption (˜20 V/nm), and have demonstrated the desorption of deuterium at fields up to 36 V/nm. The number of ions desorbed from an array has been quantified, and field desorption of metal tip substrate material from array tips has been observed for the first time. Gas-phase field ionization studies with ˜10,000 tip arrays have achieved deuterium ion currents of ˜50 nA. Neutron production by field ionization has yielded ˜10 2 n/s from ˜1 mm 2 of array area using the deuterium-deuterium fusion reaction at 90 kV.

SiO 2/SiC interface proved by positron annihilation

NASA Astrophysics Data System (ADS)

Maekawa, M.; Kawasuso, A.; Yoshikawa, M.; Itoh, H.

2003-06-01

We have studied positron annihilation in a Silicon carbide (SiC)-metal/oxide/semiconductor (MOS) structure using a monoenergetic positron beam. The Doppler broadening of annihilation quanta were measured as functions of the incident positron energy and the gate bias. Applying negative gate bias, significant increases in S-parameters were observed. This indicates the migration of implanted positrons towards SiO 2/SiC interface and annihilation at open-volume type defects. The behavior of S-parameters depending on the bias voltage was well correlated with the capacitance-voltage ( C- V) characteristics. We observed higher S-parameters and the interfacial trap density in MOS structures fabricated using the dry oxidation method as compared to those by pyrogenic oxidation method.

Liquid/vapor-induced reversible dynamic structural transformation of a three-dimensional Cu-based MOF to a one-dimensional MOF showing gate adsorption.

PubMed

Kondo, Atsushi; Suzuki, Takayuki; Kotani, Ryosuke; Maeda, Kazuyuki

2017-05-23

A new 3D metal-organic framework (MOF), in which 2D layers are interlaced to form a 3D architecture, was synthesized by a reaction of Cu(BF 4 ) 2 and 1,3-bis(4-pyridyl)propane (bpp) in a water/1-hexanol solvent system, and the crystal structure of the MOF was successfully solved. The MOF is reversibly transformed to a 1D chain MOF, which shows gate adsorption properties. The dynamic transformation gives crystal size reduction resulting in a slight change in CO 2 adsorption isotherms. The 1D MOF shows selective adsorption/separation properties on benzene and its analogues with similar sizes and shapes (benzene, toluene, and cyclohexane).

Scan direction induced charging dynamics and the application for detection of gate to S/D shorts in logic devices

NASA Astrophysics Data System (ADS)

Lei, Ming; Tian, Qing; Wu, Kevin; Zhao, Yan

2016-03-01

Gate to source/drain (S/D) short is the most common and detrimental failure mechanism for advanced process technology development in Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) device manufacturing. Especially for sub-1Xnm nodes, MOSFET device is more vulnerable to gate-S/D shorts due to the aggressive scaling. The detection of this kind of electrical short defect is always challenging for in-line electron beam inspection (EBI), especially new shorting mechanisms on atomic scale due to new material/process flow implementation. The second challenge comes from the characterization of the shorts including identification of the exact shorting location. In this paper, we demonstrate unique scan direction induced charging dynamics (SDCD) phenomenon which stems from the transistor level response from EBI scan at post metal contact chemical-mechanical planarization (CMP) layers. We found that SDCD effect is exceptionally useful for gate-S/D short induced voltage contrast (VC) defect detection, especially for identification of shorting locations. The unique SDCD effect signatures of gate-S/D shorts can be used as fingerprint for ground true shorting defect detection. Correlation with other characterization methods on the same defective location from EBI scan shows consistent results from various shorting mechanism. A practical work flow to implement the application of SDCD effect for in-line EBI monitor of critical gate-S/D short defects is also proposed, together with examples of successful application use cases which mostly focus on static random-access memory (SRAM) array regions. Although the capability of gate-S/D short detection as well as expected device response is limited to passing transistors and pull-down transistors due to the design restriction from standard 6-cell SRAM structure, SDCD effect is proven to be very effective for gate-S/D short induced VC defect detection as well as yield learning for advanced technology development.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

Gate-controlled quantum collimation in nanocolumn resonant tunneling transistors.

PubMed

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Indlekofer, K M; Lüth, H

2009-11-18

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n++/i/n++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Electric-field driven insulator-metal transition and tunable magnetoresistance in ZnO thin film

NASA Astrophysics Data System (ADS)

Zhang, Le; Chen, Shanshan; Chen, Xiangyang; Ye, Zhizhen; Zhu, Liping

2018-04-01

Electrical control of the multistate phase in semiconductors offers the promise of nonvolatile functionality in the future semiconductor spintronics. Here, by applying an external electric field, we have observed a gate-induced insulator-metal transition (MIT) with the temperature dependence of resistivity in ZnO thin films. Due to a high-density carrier accumulation, we have shown the ability to inverse change magnetoresistance in ZnO by ionic liquid gating from 10% to -2.5%. The evolution of photoluminescence under gate voltage was also consistent with the MIT, which is due to the reduction of dislocation. Our in-situ gate-controlled photoluminescence, insulator-metal transition, and the conversion of magnetoresistance open up opportunities in searching for quantum materials and ZnO based photoelectric devices.

Metal-semiconductor barrier modulation for high photoresponse in transition metal dichalcogenide field effect transistors.

PubMed

Li, Hua-Min; Lee, Dae-Yeong; Choi, Min Sup; Qu, Deshun; Liu, Xiaochi; Ra, Chang-Ho; Yoo, Won Jong

2014-02-10

A gate-controlled metal-semiconductor barrier modulation and its effect on carrier transport were investigated in two-dimensional (2D) transition metal dichalcogenide (TMDC) field effect transistors (FETs). A strong photoresponse was observed in both unipolar MoS2 and ambipolar WSe2 FETs (i) at the high drain voltage due to a high electric field along the channel for separating photo-excited charge carriers and (ii) at the certain gate voltage due to the optimized barriers for the collection of photo-excited charge carriers at metal contacts. The effective barrier height between Ti/Au and TMDCs was estimated by a low temperature measurement. An ohmic contact behavior and drain-induced barrier lowering (DIBL) were clearly observed in MoS2 FET. In contrast, a Schottky-to-ohmic contact transition was observed in WSe2 FET as the gate voltage increases, due to the change of majority carrier transport from holes to electrons. The gate-dependent barrier modulation effectively controls the carrier transport, demonstrating its great potential in 2D TMDCs for electronic and optoelectronic applications.

Estimation of matal balances a tool for improving of management in a farm from polluted area Copsa Mica

NASA Astrophysics Data System (ADS)

Olimpia Vrinceanu, Nicoleta; Simota, Catalin; Motelica, Dumitru-Marian; Dumitru, Mihail; Ignat, Petru; Vrinceanu, Andrei; Mircea Rotaru, Lucian

2015-04-01

Long-term accumulation of heavy metals in arable ecosystems from Copsa Mica area negatively affecting soil fertility and product quality. A sustainable heavy metal management in these agro-ecosystems allows to ensure that the soils continues to fulfill its functions and to provide its ecosystem services (especially supporting and provisioning services). An analysis of the input and output flows of heavy metals in agro-ecosystems and of their resulting accumulation is necessary to define strategies that ensure sustainable management of these metals in agricultural systems. The aim of this study was to calculate the farm-gate and barn balances for the heavy metals (Cd, Pb and Zn) using the data from a farm located in polluted area Copşa Mică. For all heavy metals (Cd, Pb and Zn) farm-gate balances are negative; the export of metal in the farm was done mainly through the manure. The barn balance for cadmium was positive, indicating an accumulation of metal in the system. Inputs of cadmium in the system were estimated at 163.67 g Cd / year and losses of cadmium from the system were made mainly through manure (77.22g Cd / year). Both lead and zinc barn-gate balances are negative. Also externalization of lead and zinc in the system was achieved by manure (969 g Pb / year and 2390 g Zn / year). Monitoring metal balances at different scales (farm-gate, barn) proved to a successful way to identifying farm management issues not revealed by determining metal balances at the farm-gate alone. The main finding was that the substantial amounts of cadmium, lead and zinc were released from internal sources, mainly through fodder obtained from their own land (some plots are located in polluted area). The manure is the main contributor to outflows both for heavy metals. Using this manure as organic fertilizer could lead to accumulation of cadmium in soil with major risk on soil fertility and crop quality.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

NASA Astrophysics Data System (ADS)

Priya, Anjali; Mishra, Ram Awadh

2016-04-01

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

A Self-Aligned InGaAs Quantum-Well Metal-Oxide-Semiconductor Field-Effect Transistor Fabricated through a Lift-Off-Free Front-End Process

NASA Astrophysics Data System (ADS)

Lin, Jianqiang; Kim, Tae-Woo; Antoniadis, Dimitri A.; del Alamo, Jesús A.

2012-06-01

We present a novel n-type InGaAs quantum-well metal-oxide-semiconductor field-effect transistor (QW-MOSFET) fabricated by a self-aligned gate-last process and investigate relevant Si-like manufacturing issues in future III-V MOSFETs. The device structure features a composite InP/Al2O3 gate barrier with a capacitance equivalent thickness (CET) of 3 nm and non alloyed Mo ohmic contacts. We have found that RIE introduces significant damage to the intrinsic device resulting in poor current drive and subthreshold swing. The effect is largely removed through a thermal annealing step. Thermally annealed QW-MOSFETs exhibit a subthreshold swing of 95 mV/dec, indicative of excellent interfacial characteristics. The peak mobility of the MOSFET is 2780 cm2 V-1 s-1.

Active pixel sensor pixel having a photodetector whose output is coupled to an output transistor gate

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Nakamura, Junichi (Inventor); Kemeny, Sabrina E. (Inventor)

2005-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node. There is also a readout circuit, part of which can be disposed at the bottom of each column of cells and be common to all the cells in the column. A Simple Floating Gate (SFG) pixel structure could also be employed in the imager to provide a non-destructive readout and smaller pixel sizes.

Lithographically fabricated gold nanowire waveguides for plasmonic routers and logic gates.

PubMed

Gao, Long; Chen, Li; Wei, Hong; Xu, Hongxing

2018-06-14

Fabricating plasmonic nanowire waveguides and circuits by lithographic fabrication methods is highly desired for nanophotonic circuitry applications. Here we report an approach for fabricating metal nanowire networks by using electron beam lithography and metal film deposition techniques. The gold nanowire structures are fabricated on quartz substrates without using any adhesion layer but coated with a thin layer of Al2O3 film for immobilization. The thermal annealing during the Al2O3 deposition process decreases the surface plasmon loss. In a Y-shaped gold nanowire network, the surface plasmons can be routed to different branches by controlling the polarization of the excitation light, and the routing behavior is dependent on the length of the main nanowire. Simulated electric field distributions show that the zigzag distribution of the electric field in the nanowire network determines the surface plasmon routing. By using two laser beams to excite surface plasmons in a Y-shaped nanowire network, the output intensity can be modulated by the interference of surface plasmons, which can be used to design Boolean logic gates. We experimentally demonstrate that AND, OR, XOR and NOT gates can be realized in three-terminal nanowire networks, and NAND, NOR and XNOR gates can be realized in four-terminal nanowire networks. This work takes a step toward the fabrication of on-chip integrated plasmonic circuits.

MOCVD of HfO2 and ZrO2 high-k gate dielectrics for InAlN/AlN/GaN MOS-HEMTs

NASA Astrophysics Data System (ADS)

Abermann, S.; Pozzovivo, G.; Kuzmik, J.; Strasser, G.; Pogany, D.; Carlin, J.-F.; Grandjean, N.; Bertagnolli, E.

2007-12-01

We apply metal organic chemical vapour deposition (MOCVD) of HfO2 and of ZrO2 from β-diketonate precursors to grow high-k gate dielectrics for InAlN/AlN/GaN metal oxide semiconductor (MOS)-high electron mobility transistors (HEMTs). High-k oxides of about 12 nm-14 nm are deposited for the MOS-HEMTs incorporating Ni/Au gates, whereas as a reference, Ni-contact-based 'conventional' Schottky-barrier (SB)-HEMTs are processed. The processed dielectrics decrease the gate current leakage of the HEMTs by about four orders of magnitude if compared with the SB-gated HEMTs and show superior device characteristics in terms of IDS and breakdown.

Leakage current conduction in metal gate junctionless nanowire transistors

NASA Astrophysics Data System (ADS)

Oproglidis, T. A.; Karatsori, T. A.; Barraud, S.; Ghibaudo, G.; Dimitriadis, C. A.

2017-05-01

In this paper, the experimental off-state drain leakage current behavior is systematically explored in n- and p-channel junctionless nanowire transistors with HfSiON/TiN/p+-polysilicon gate stack. The analysis of the drain leakage current is based on experimental data of the gate leakage current. It has been shown that the off-state drain leakage current in n-channel devices is negligible, whereas in p-channel devices it is significant and dramatically increases with drain voltage. The overall results indicate that the off-state drain leakage current in p-channel devices is mainly due to trap-assisted Fowler-Nordheim tunneling of electrons through the gate oxide of electrons from the metal gate to the silicon layer near the drain region.

Fabrication, testing and reliability modeling of copper/titanium-metallized GaAs MESFETs and HEMTs for low-noise applications

NASA Astrophysics Data System (ADS)

Feng, Ting

Today, GaAs based field effect transistors (FETs) have been used in a broad range of high-speed electronic military and commercial applications. However, their reliability still needs to be improved. Particularly the hydrogen induced degradation is a large remaining issue in the reliability of GaAs FETs, because hydrogen can easily be incorporated into devices during the crystal growth and virtually every device processing step. The main objective of this research work is to develop a new gate metallization system in order to reduce the hydrogen induced degradation from the gate region for GaAs based MESFETs and HEMTs. Cu/Ti gate metallization has been introduced into the GaAs MESFETs and HEMTs in our work in order to solve the hydrogen problem. The purpose of the use of copper is to tie up the hydrogen atoms and prevent hydrogen penetration into the device active region as well as to keep a low gate resistance for low noise applications. In this work, the fabrication technology of GaAs MESFETs and AlGaAs/GaAs HEMTs with Cu/Ti metallized gates have been successfully developed and the fabricated Cu/Ti FETs have shown comparable DC performance with similar Au-based GaAs FETs. The Cu/Ti FETs were subjected to temperature accelerated testing at NOT under 5% hydrogen forming gas and the experimental results show the hydrogen induced degradation has been reduced for the Cu/Ti FETs compared to commonly used AuPtTi based GaAs FETs. A long-term reliability testing for Cu/Ti FETs has also been carried out at 200°C and up to 1000hours and testing results show Cu/Ti FETs performed with adequate reliability. The failure modes were found to consist of a decrease in drain saturation current and pinch-off voltage and an increase in source ohmic contact resistance. Material characterization tools including Rutherford backscattering spectroscopy and a back etching technique were used in Cu/Ti GaAs FETs, and pronounced gate metal copper in-diffusion and intermixing compounds at the interface between the gate and GaAs channel layer were found. A quantifying gate sinking degradation model was developed in order to extend device physics models to reliability testing results of Cu/Ti GaAs FETs. The gate sinking degradation model includes the gate metal and hydrogen in-diffusion effect, decrease of effective channel due to the formation of interfacial compounds, decrease of electron mobility due to the increase of in-diffused impurities, and donor compensation from in-diffused metal impurity acceptors or hydrogen passivation. A variational charge control model was applied to simulate and understand the degradation mechanisms of Cu/Ti HEMTs, including hydrogen induced degradation due to the neutralization of donors. The degradation model established in this study is also applicable to other Au or Al metallized GaAs FETs for understanding the failure mechanisms induced by gate sinking and hydrogen neutralization of donors and con-elating the device physics model with reliability testing results.

Origin of noise in liquid-gated Si nanowire troponin biosensors.

PubMed

Kutovyi, Y; Zadorozhnyi, I; Hlukhova, H; Handziuk, V; Petrychuk, M; Ivanchuk, Andriy; Vitusevich, S

2018-04-27

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

Origin of noise in liquid-gated Si nanowire troponin biosensors

NASA Astrophysics Data System (ADS)

Kutovyi, Y.; Zadorozhnyi, I.; Hlukhova, H.; Handziuk, V.; Petrychuk, M.; Ivanchuk, Andriy; Vitusevich, S.

2018-04-01

Liquid-gated Si nanowire field-effect transistor (FET) biosensors are fabricated using a complementary metal-oxide-semiconductor-compatible top-down approach. The transport and noise properties of the devices reflect the high performance of the FET structures, which allows label-free detection of cardiac troponin I (cTnI) molecules. Moreover, after removing the troponin antigens the structures demonstrate the same characteristics as before cTnI detection, indicating the reusable operation of biosensors. Our results show that the additional noise is related to the troponin molecules and has characteristics which considerably differ from those usually recorded for conventional FETs without target molecules. We describe the origin of the noise and suggest that noise spectroscopy represents a powerful tool for understanding molecular dynamic processes in nanoscale FET-based biosensors.

30 CFR 56.19100 - Shaft landing gates.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Shaft landing gates. 56.19100 Section 56.19100 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL MINE... § 56.19100 Shaft landing gates. Shaft landings shall be equipped with substantial safety gates so...

30 CFR 56.19100 - Shaft landing gates.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Shaft landing gates. 56.19100 Section 56.19100 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL MINE... § 56.19100 Shaft landing gates. Shaft landings shall be equipped with substantial safety gates so...

30 CFR 57.19100 - Shaft landing gates.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 30 Mineral Resources 1 2010-07-01 2010-07-01 false Shaft landing gates. 57.19100 Section 57.19100 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL MINE... Shafts § 57.19100 Shaft landing gates. Shaft landings shall be equipped with substantial safety gates so...

30 CFR 57.19100 - Shaft landing gates.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 30 Mineral Resources 1 2011-07-01 2011-07-01 false Shaft landing gates. 57.19100 Section 57.19100 Mineral Resources MINE SAFETY AND HEALTH ADMINISTRATION, DEPARTMENT OF LABOR METAL AND NONMETAL MINE... Shafts § 57.19100 Shaft landing gates. Shaft landings shall be equipped with substantial safety gates so...

[Design and synthesis of imine compound for metal cation logical gates recognition and setup of double-control fluorescent molecule switch].

PubMed

Huang, Tao; Zhu, Yu-lian; Dai, Xue-qin; Zhang, Qi; Huang, Yan

2011-07-01

The Schiff base's reduced product N,N-bis(4-methoxybenzyl) ethane-1,2-diamine, which was used as a receptor L, was designed and synthesized for the first time in the present article. It was found that Cu2+ and Fe3+ could quench L in fluorescence observably and Zn2+ and Cd2+ could enhance L remarkably. So the two pair metal cation could set up "OR" logical gate relation with the receptor molecule L, then a logical recognition system be formed. The data of resolved ZnL's single crystal indicated that ZnL belonged to monoclinic (CCDC No. 747994). Integrated spectrum instrument was used to characterize the structure of its alike series of complex compound. According to ZnL's excellent fluorescence character and the ability to exchange with contiguous metal cation, ZnZ+/ZnL/Co2+, Zn2+/ZnL/Nit+ fluorescent molecule switch was designed. It is hoped that the work above could be positive for the development of molecule computer, bio-intellectualized inspection technology (therapy) and instrument.

A two-dimensional (2D) analytical subthreshold swing and transconductance model of underlap dual-material double-gate (DMDG) MOSFET for analog/RF applications

NASA Astrophysics Data System (ADS)

Narendar, Vadthiya; Rai, Saurabh; Tiwari, Siddharth; Mishra, R. A.

2016-12-01

The double-gate (DG) metal-oxide-semiconductor field effect transistors (MOSFETs) are the choice of technology in sub -100 nm regime of leading microelectronics industry. To enhance the analog and RF performance of DG MOSFET, an underlap dual-material (DM) DG MOSFET device structure has been considered because, it has the advantages of both underlap as well as that of dual-material gate (DMG). A 2D analytical surface potential, subthreshold current, subthreshold swing as well as transconductance modelling of underlap DMDG MOSFET has been done by solving the Poisson's equation. It has also been found that, numerically simulated data approves the analytically modelled data with commendable accuracy. As underlap length (Lun) increases, a substantial reduction of subthreshold current due to enhanced gate control over channel regime is observed. DMG structure facilitates to improve the average velocity of carriers which leads to superior drive current of the device. The underlap DMDG MOSFET device structure demonstrates an ameliorated subthreshold characteristic. The analog figure of merits (FOMs) such as transconductance (gm), transconductance generation factor (TGF), output conductance (gd), early voltage (VEA), intrinsic gain (AV) and RF FOMs namely cut-off frequency (fT), gain frequency product (GFP), transconductance frequency product (TFP) and gain transconductance frequency product (GTFP) have been evaluated. The aforesaid analysis revels that, the device is best suited for communication related Analog/RF applications.

High performance multi-finger MOSFET on SOI for RF amplifiers

NASA Astrophysics Data System (ADS)

Adhikari, M. Singh; Singh, Y.

2017-10-01

In this paper, we propose structural modifications in the conventional planar metal-oxide-semiconductor field-effect transistor (MOSFET) on silicon-on-insulator by utilizing trenches in the epitaxial layer. The proposed multi-finger MOSFET (MF-MOSFET) has dual vertical-gates placed in separate trenches to form multiple channels in the p-base which carry the drain current in parallel. The proposed device uses TaN as gate electrode and SiO2 as gate dielectric. Simultaneous conduction of multiple channels enhances the drain current (ID) and provides higher transconductance (gm) leading to significant improvement in cut-off frequency (ft). Two-dimensional simulations are performed to evaluate and compare the performance of the MF-MOSFET with the conventional MOSFET. At a gate length of 60 nm, the proposed device provides 4 times higher ID, 3 times improvement in gm and 1.25 times increase in ft with better control over the short channel effects as compared with the conventional device.

Electron-beam-evaporated thin films of hafnium dioxide for fabricating electronic devices

DOE PAGES

Xiao, Zhigang; Kisslinger, Kim

2015-06-17

Thin films of hafnium dioxide (HfO 2) are widely used as the gate oxide in fabricating integrated circuits because of their high dielectric constants. In this paper, the authors report the growth of thin films of HfO 2 using e-beam evaporation, and the fabrication of complementary metal-oxide semiconductor (CMOS) integrated circuits using this HfO 2 thin film as the gate oxide. The authors analyzed the thin films using high-resolution transmission electron microscopy and electron diffraction, thereby demonstrating that the e-beam-evaporation-grown HfO 2 film has a polycrystalline structure and forms an excellent interface with silicon. Accordingly, we fabricated 31-stage CMOS ringmore » oscillator to test the quality of the HfO 2 thin film as the gate oxide, and obtained excellent rail-to-rail oscillation waveforms from it, denoting that the HfO 2 thin film functioned very well as the gate oxide.« less

All-printed thin-film transistors from networks of liquid-exfoliated nanosheets

NASA Astrophysics Data System (ADS)

Kelly, Adam G.; Hallam, Toby; Backes, Claudia; Harvey, Andrew; Esmaeily, Amir Sajad; Godwin, Ian; Coelho, João; Nicolosi, Valeria; Lauth, Jannika; Kulkarni, Aditya; Kinge, Sachin; Siebbeles, Laurens D. A.; Duesberg, Georg S.; Coleman, Jonathan N.

2017-04-01

All-printed transistors consisting of interconnected networks of various types of two-dimensional nanosheets are an important goal in nanoscience. Using electrolytic gating, we demonstrate all-printed, vertically stacked transistors with graphene source, drain, and gate electrodes, a transition metal dichalcogenide channel, and a boron nitride (BN) separator, all formed from nanosheet networks. The BN network contains an ionic liquid within its porous interior that allows electrolytic gating in a solid-like structure. Nanosheet network channels display on:off ratios of up to 600, transconductances exceeding 5 millisiemens, and mobilities of >0.1 square centimeters per volt per second. Unusually, the on-currents scaled with network thickness and volumetric capacitance. In contrast to other devices with comparable mobility, large capacitances, while hindering switching speeds, allow these devices to carry higher currents at relatively low drive voltages.

Modulating Thin Film Transistor Characteristics by Texturing the Gate Metal.

PubMed

Nair, Aswathi; Bhattacharya, Prasenjit; Sambandan, Sanjiv

2017-12-20

The development of reliable, high performance integrated circuits based on thin film transistors (TFTs) is of interest for the development of flexible electronic circuits. In this work we illustrate the modulation of TFT transconductance via the texturing of the gate metal created by the addition of a conductive pattern on top of a planar gate. Texturing results in the semiconductor-insulator interface acquiring a non-planar geometry with local variations in the radius of curvature. This influences various TFT parameters such as the subthreshold slope, gate voltage at the onset of conduction, contact resistance and gate capacitance. Specific studies are performed on textures based on periodic striations oriented along different directions. Textured TFTs showed upto ±40% variation in transconductance depending on the texture orientation as compared to conventional planar gate TFTs. Analytical models are developed and compared with experiments. Gain boosting in common source amplifiers based on textured TFTs as compared to conventional TFTs is demonstrated.

Influence of gate recess on the electronic characteristics of β-Ga2O3 MOSFETs

NASA Astrophysics Data System (ADS)

Lv, Yuanjie; Mo, Jianghui; Song, Xubo; He, Zezhao; Wang, Yuangang; Tan, Xin; Zhou, Xingye; Gu, Guodong; Guo, Hongyu; Feng, Zhihong

2018-05-01

Gallium oxide (Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with gate recess depths of 110 nm and 220 nm, respectively. The gate recess was formed by dry plasma etching with Cr metal as the mask. The fabricated devices with a 25-nm HfO2 gate dielectric both showed a low off-state drain current of about 1.8 × 10-10 A/mm. The effects of recess depth on the electronic characteristics of Ga2O3 MOSFETs were investigated. Upon increasing the recess depth from 110 nm to 220 nm, the saturated drain current decreased from 20.7 mA/mm to 2.6 mA/mm, while the threshold voltage moved increased to +3 V. Moreover, the breakdown voltage increased from 122 V to 190 V. This is mainly because the inverted-trapezoidal gate played the role of a gate-field plate, which suppressed the peak electric field close to the gate.

Combinatorial study of Ni-Ti-Pt ternary metal gate electrodes on HfO{sub 2} for the advanced gate stack

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chang, K.-S.; Green, M. L.; Suehle, J.

2006-10-02

The authors have fabricated combinatorial Ni-Ti-Pt ternary metal gate thin film libraries on HfO{sub 2} using magnetron co-sputtering to investigate flatband voltage shift ({delta}V{sub fb}), work function ({phi}{sub m}), and leakage current density (J{sub L}) variations. A more negative {delta}V{sub fb} is observed close to the Ti-rich corner than at the Ni- and Pt-rich corners, implying smaller {phi}{sub m} near the Ti-rich corners and higher {phi}{sub m} near the Ni- and Pt-rich corners. In addition, measured J{sub L} values can be explained consistently with the observed {phi}{sub m} variations. Combinatorial methodologies prove to be useful in surveying the large compositionalmore » space of ternary alloy metal gate electrode systems.« less

Gating geometry studies of thin-walled 17-4PH investment castings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire, M.C.; Zanner, F.J.

1992-11-01

The ability to design gating systems that reliably feed and support investment castings is often the result of ``cut-and-try`` methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channelmore » thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.« less

Gating geometry studies of thin-walled 17-4PH investment castings

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maguire, M.C.; Zanner, F.J.

1992-01-01

The ability to design gating systems that reliably feed and support investment castings is often the result of cut-and-try'' methodology. Factors such as hot tearing, porosity, cold shuts, misruns, and shrink are defects often corrected by several empirical gating design iterations. Sandia National Laboratories is developing rules that aid in removing the uncertainty involved in the design of gating systems for investment castings. In this work, gating geometries used for filling of thin walled investment cast 17-4PH stainless steel flat plates were investigated. A full factorial experiment evaluating the influence of metal pour temperature, mold preheat temperature, and mold channelmore » thickness were conducted for orientations that filled a horizontal flat plate from the edge. A single wedge gate geometry was used for the edge-gated configuration. Thermocouples placed along the top of the mold recorded metal front temperatures, and a real-time x-ray imaging system tracked the fluid flow behavior during filling of the casting. Data from these experiments were used to determine the terminal fill volumes and terminal fill times for each gate design.« less

Gate-tunable gigantic lattice deformation in VO{sub 2}

DOE Office of Scientific and Technical Information (OSTI.GOV)

Okuyama, D., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp; Hatano, T.; Nakano, M., E-mail: okuyama@riken.jp, E-mail: nakano@imr.tohoku.ac.jp, E-mail: iwasa@ap.t.u-tokyo.ac.jp

2014-01-13

We examined the impact of electric field on crystal lattice of vanadium dioxide (VO{sub 2}) in a field-effect transistor geometry by in-situ synchrotron x-ray diffraction measurements. Whereas the c-axis lattice parameter of VO{sub 2} decreases through the thermally induced insulator-to-metal phase transition, the gate-induced metallization was found to result in a significant increase of the c-axis length by almost 1% from that of the thermally stabilized insulating state. We also found that this gate-induced gigantic lattice deformation occurs even at the thermally stabilized metallic state, enabling dynamic control of c-axis lattice parameter by more than 1% at room temperature.

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

NASA Astrophysics Data System (ADS)

Kumar, Manoj; Haldar, Subhasis; Gupta, Mridula; Gupta, R. S.

2016-10-01

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (N it) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/- LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as N it is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal-semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

Noise And Charge Transport In Carbon Nanotube Devices

NASA Astrophysics Data System (ADS)

Reza, Shahed; Huynh, Quyen T.; Bosman, Gijs; Sippel, Jennifer; Rinzler, Andrew G.

2005-11-01

The charge transport and noise properties of three terminal, gated devices containing multiple, single wall, metallic and semiconductor carbon nanotubes have been measured as a function of gate and drain bias at 300K. Using pulsed bias the metallic tubes could be burned sequentially enabling the separation of measured conductance and low frequency excess noise into metallic and semiconductor contributions. The relative low frequency excess noise of the metallic tubes was about a factor 100 lower than that of the semiconductor tubes, whereas the conductance of the metallic tubes was significantly higher (10 to 50 times) than that of the semiconductor tubes.

Heterointegration of Dissimilar Materials

DTIC Science & Technology

2015-07-28

computing capabilities. This has been possible due to the aggressive scaling undertaken by the Si industry for complementary metal oxide semiconductor...current due to quantum mechanical tunneling. After years of research and development, Hf- based gate dielectric with metal gates is now being used in CMOS...the oxide in this study was 1ML or ~3.9 Å/ min. The native SiO2 was removed using a low temperature process involving the deposition of Sr metal

Optimization of Squeeze Casting for Aluminum Alloy Parts

DOE Office of Scientific and Technical Information (OSTI.GOV)

David Schwam; John F. Wallace; Qingming Chang

2002-07-30

This study was initiated with the installation of a new production size UBE 350 Ton VSC Squeeze Casting system in the Metal Casting Laboratory at Case Western University. A Lindberg 75k W electrical melting furnace was installed alongside. The challenge of installation and operation of such industrial-size equipment in an academic environment was met successfully. Subsequently, a Sterling oil die heater and a Visi-Track shot monitoring system were added. A significant number of inserts were designed and fabricated over the span of the project, primarily for squeeze casting different configurations of test bars and plates. A spiral ''ribbon insert'' formore » evaluation of molten metal fluidity was also fabricated. These inserts were used to generate a broad range of processing conditions and determine their effect on the quality of the squeeze cast parts. This investigation has studied the influence of the various casting variables on the quality of indirect squeeze castings primarily of aluminum alloys. The variables studied include gating design, fill time and fill patter, metal pressure and die temperature variations. The quality of the die casting was assessed by an analysis of both their surface condition and internal soundness. The primary metal tested was an aluminum 356 alloy. In addition to determining the effect of these casting variables on casting quality as measured by a flat plate die of various thickness, a number of test bar inserts with different gating designs have been inserted in the squeeze casting machine. The mechanical properties of these test bars produced under different squeeze casting conditions were measured and reported. The investigation of the resulting properties also included an analysis of the microstructure of the squeeze castings and the effect of the various structural constituents on the resulting properties. The main conclusions from this investigation are as follows: The ingate size and shape are very important since it must remain open until the casting is solidified and pressure is maintained on the solidifying casting. Fanned gates, particularly on the smaller section castings avoid jetting effects at the ingate end. The fan type ingate helps accomplish a rapid fill without high velocities. The molten metal has to fill the cavity before localized solidification occurs. This is best accomplished with a larger ingate to attain rapid filling without excessive velocity or jetting that occurs at high metal velocities. Straight gates are prone to case jetting of the metal stream even a low velocities. Fanned gates allow use of higher fill velocity without excessive jetting. A higher metal pressure provides a more complete fill of the die including improved compensation for solidification shrinkage. With the proper filling pattern, ingates, overflows and die temperature for a given die, very good tensile properties can be attained in squeeze casting. In general, the smaller squeeze castings require higher die temperatures. Computer models using the UES Procast and MagmaSoft finite element software can, after suitable adjustments, predict the flow pattern in the die cavity.« less

Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

NASA Astrophysics Data System (ADS)

Olga Gneri, Paula; Jardim, Marcos

Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Spin Transport in Nondegenerate Si with a Spin MOSFET Structure at Room Temperature

NASA Astrophysics Data System (ADS)

Sasaki, Tomoyuki; Ando, Yuichiro; Kameno, Makoto; Tahara, Takayuki; Koike, Hayato; Oikawa, Tohru; Suzuki, Toshio; Shiraishi, Masashi

2014-09-01

Spin transport in nondegenerate semiconductors is expected to pave the way to the creation of spin transistors, spin logic devices, and reconfigurable logic circuits, because room-temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in nondegenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observe the modulation of the Hanle-type spin-precession signals, which is a characteristic spin dynamics in nondegenerate semiconductors. We obtain long spin transport of more than 20 μm and spin rotation greater than 4π at RT. We also observe gate-induced modulation of spin-transport signals at RT. The modulation of the spin diffusion length as a function of a gate voltage is successfully observed, which we attribute to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to lead to the creation of practical Si-based spin MOSFETs.

Role of Oxygen in Ionic Liquid Gating on Two-Dimensional Cr2Ge2Te6: A Non-oxide Material.

PubMed

Chen, Yangyang; Xing, Wenyu; Wang, Xirui; Shen, Bowen; Yuan, Wei; Su, Tang; Ma, Yang; Yao, Yunyan; Zhong, Jiangnan; Yun, Yu; Xie, X C; Jia, Shuang; Han, Wei

2018-01-10

Ionic liquid gating can markedly modulate a material's carrier density so as to induce metallization, superconductivity, and quantum phase transitions. One of the main issues is whether the mechanism of ionic liquid gating is an electrostatic field effect or an electrochemical effect, especially for oxide materials. Recent observation of the suppression of the ionic liquid gate-induced metallization in the presence of oxygen for oxide materials suggests the electrochemical effect. However, in more general scenarios, the role of oxygen in the ionic liquid gating effect is still unclear. Here, we perform ionic liquid gating experiments on a non-oxide material: two-dimensional ferromagnetic Cr 2 Ge 2 Te 6 . Our results demonstrate that despite the large increase of the gate leakage current in the presence of oxygen, the oxygen does not affect the ionic liquid gating effect on  the channel resistance of Cr 2 Ge 2 Te 6 devices (<5% difference), which suggests the electrostatic field effect as the mechanism on non-oxide materials. Moreover, our results show that ionic liquid gating is more effective on the modulation of the channel resistances compared to the back gating across the 300 nm thick SiO 2 .

Impact of process parameters on the structural and electrical properties of metal/PZT/Al2O3/silicon gate stack for non-volatile memory applications

NASA Astrophysics Data System (ADS)

Singh, Prashant; Jha, Rajesh Kumar; Singh, Rajat Kumar; Singh, B. R.

2018-02-01

In this paper, we present the structural and electrical properties of the Al2O3 buffer layer on non-volatile memory behavior using Metal/PZT/Al2O3/Silicon structures. Metal/PZT/Silicon and Metal/Al2O3/Silicon structures were also fabricated and characterized to obtain capacitance and leakage current parameters. Lead zirconate titanate (PZT::35:65) and Al2O3 films were deposited by sputtering on the silicon substrate. Memory window, PUND, endurance, breakdown voltage, effective charges, flat-band voltage and leakage current density parameters were measured and the effects of process parameters on the structural and electrical characteristics were investigated. X-ray data show dominant (110) tetragonal phase of the PZT film, which crystallizes at 500 °C. The sputtered Al2O3 film annealed at different temperatures show dominant (312) orientation and amorphous nature at 425 °C. Multiple angle laser ellipsometric analysis reveals the temperature dependence of PZT film refractive index and extinction coefficient. Electrical characterization shows the maximum memory window of 3.9 V and breakdown voltage of 25 V for the Metal/Ferroelectric/Silicon (MFeS) structures annealed at 500 °C. With 10 nm Al2O3 layer in the Metal/Ferroelectric/Insulator/Silicon (MFeIS) structure, the memory window and breakdown voltage was improved to 7.21 and 35 V, respectively. Such structures show high endurance with no significant reduction polarization charge for upto 2.2 × 109 iteration cycles.

Semiconductor to metallic transition in bulk accumulated amorphous indium-gallium-zinc-oxide dual gate thin-film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Chowdhury, Md Delwar Hossain; Jang, Jin, E-mail: jjang@khu.ac.kr

We investigated the effects of top gate voltage (V{sub TG}) and temperature (in the range of 25 to 70 {sup o}C) on dual-gate (DG) back-channel-etched (BCE) amorphous-indium-gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) characteristics. The increment of V{sub TG} from -20V to +20V, decreases the threshold voltage (V{sub TH}) from 19.6V to 3.8V and increases the electron density to 8.8 x 10{sup 18}cm{sup −3}. Temperature dependent field-effect mobility in saturation regime, extracted from bottom gate sweep, show a critical dependency on V{sub TG}. At V{sub TG} of 20V, the mobility decreases from 19.1 to 15.4 cm{sup 2}/V ⋅ s with increasingmore » temperature, showing a metallic conduction. On the other hand, at V{sub TG} of - 20V, the mobility increases from 6.4 to 7.5cm{sup 2}/V ⋅ s with increasing temperature. Since the top gate bias controls the position of Fermi level, the temperature dependent mobility shows metallic conduction when the Fermi level is above the conduction band edge, by applying high positive bias to the top gate.« less

Surface-confined assemblies and polymers for molecular logic.

PubMed

de Ruiter, Graham; van der Boom, Milko E

2011-08-16

Stimuli responsive materials are capable of mimicking the operation characteristics of logic gates such as AND, OR, NOR, and even flip-flops. Since the development of molecular sensors and the introduction of the first AND gate in solution by de Silva in 1993, Molecular (Boolean) Logic and Computing (MBLC) has become increasingly popular. In this Account, we present recent research activities that focus on MBLC with electrochromic polymers and metal polypyridyl complexes on a solid support. Metal polypyridyl complexes act as useful sensors to a variety of analytes in solution (i.e., H(2)O, Fe(2+/3+), Cr(6+), NO(+)) and in the gas phase (NO(x) in air). This information transfer, whether the analyte is present, is based on the reversible redox chemistry of the metal complexes, which are stable up to 200 °C in air. The concurrent changes in the optical properties are nondestructive and fast. In such a setup, the input is directly related to the output and, therefore, can be represented by one-input logic gates. These input-output relationships are extendable for mimicking the diverse functions of essential molecular logic gates and circuits within a set of Boolean algebraic operations. Such a molecular approach towards Boolean logic has yielded a series of proof-of-concept devices: logic gates, multiplexers, half-adders, and flip-flop logic circuits. MBLC is a versatile and, potentially, a parallel approach to silicon circuits: assemblies of these molecular gates can perform a wide variety of logic tasks through reconfiguration of their inputs. Although these developments do not require a semiconductor blueprint, similar guidelines such as signal propagation, gate-to-gate communication, propagation delay, and combinatorial and sequential logic will play a critical role in allowing this field to mature. For instance, gate-to-gate communication by chemical wiring of the gates with metal ions as electron carriers results in the integration of stand-alone systems: the output of one gate is used as the input for another gate. Using the same setup, we were able to display both combinatorial and sequential logic. We have demonstrated MBLC by coupling electrochemical inputs with optical readout, which resulted in various logic architectures built on a redox-active, functionalized surface. Electrochemically operated sequential logic systems such as flip-flops, multivalued logic, and multistate memory could enhance computational power without increasing spatial requirements. Applying multivalued digits in data storage could exponentially increase memory capacity. Furthermore, we evaluate the pros and cons of MBLC and identify targets for future research in this Account. © 2011 American Chemical Society

Low-voltage organic thin film transistors (OTFTs) using crosslinked polyvinyl alcohol (PVA)/neodymium oxide (Nd2O3) bilayer gate dielectrics

NASA Astrophysics Data System (ADS)

Khound, Sagarika; Sarma, Ranjit

2018-01-01

We have reported here on the design, processing and dielectric properties of pentacene-based organic thin film transitors (OTFTs) with a bilayer gate dilectrics of crosslinked PVA/Nd2O3 which enables low-voltage organic thin film operations. The dielectric characteristics of PVA/Nd2O3 bilayer films are studied by capacitance-voltage ( C- V) and current-voltage ( I- V) curves in the metal-insulator-metal (MIM) structure. We have analysed the output electrical responses and transfer characteristics of the OTFT devices to determine their performance of OTFT parameters. The mobility of 0.94 cm2/Vs, the threshold voltage of - 2.8 V, the current on-off ratio of 6.2 × 105, the subthreshold slope of 0.61 V/decade are evaluated. Low leakage current of the device is observed from current density-electric field ( J- E) curve. The structure and the morphology of the device are studied using X-ray diffraction (XRD) and atomic force microscope (AFM), respectively. The study demonstrates an effective way to realize low-voltage, high-performance OTFTs at low cost.

Material parameters from frequency dispersion simulation of floating gate memory with Ge nanocrystals in HfO2

NASA Astrophysics Data System (ADS)

Palade, C.; Lepadatu, A. M.; Slav, A.; Lazanu, S.; Teodorescu, V. S.; Stoica, T.; Ciurea, M. L.

2018-01-01

Trilayer memory capacitors with Ge nanocrystals (NCs) floating gate in HfO2 were obtained by magnetron sputtering deposition on p-type Si substrate followed by rapid thermal annealing at relatively low temperature of 600 °C. The frequency dispersion of capacitance and resistance was measured in accumulation regime of Al/HfO2 gate oxide/Ge NCs in HfO2 floating gate/HfO2 tunnel oxide/SiOx/p-Si/Al memory capacitors. For simulation of the frequency dispersion a complex circuit model was used considering an equivalent parallel RC circuit for each layer of the trilayer structure. A series resistance due to metallic contacts and Si substrate was necessary to be included in the model. A very good fit to the experimental data was obtained and the parameters of each layer in the memory capacitor, i.e. capacitances and resistances were determined and in turn the intrinsic material parameters, i.e. dielectric constants and resistivities of layers were evaluated. The results are very important for the study and optimization of the hysteresis behaviour of floating gate memories based on NCs embedded in oxide.

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

NASA Astrophysics Data System (ADS)

Kumar, Sunil; Loan, Sajad A.; Alamoud, Abdulrahman M.

2017-04-01

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The transistors used to realize the transmission path and the SSS inverter in the proposed TG are the double gate Schottky barrier devices, employing stacks of two metal silicides, platinum silicide (PtSi) and erbium silicide (ErSi). It has been observed that the realization of the TG gate by the proposed technology has resulted into a compact structure, with reduced component count, junctions, interconnections and regions in comparison to the conventional technology. The further focus of this work is on the application part of the proposed technology. So for the first time, the proposed technology has been used to realize various combinational circuits, like a two input AND gate, a 2:1 multiplexer and a two input XOR circuits. It has been observed that the transistor count has got reduced by half in a TG, two input AND gate, 2:1 multiplexer and in a two input XOR gate. Therefore, a significant reduction in transistor count and area requirement can be achieved by using the proposed technology. The proposed technology can be also used to perform the compact realization of other combinational and sequential circuitry in future.

Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

NASA Astrophysics Data System (ADS)

Caraveo-Frescas, J. A.; Hedhili, M. N.; Wang, H.; Schwingenschlögl, U.; Alshareef, H. N.

2012-03-01

It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ˜350 mV negative shift with the Si overlayer present and a ˜110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Frequency-Stable Ionic-Type Hybrid Gate Dielectrics for High Mobility Solution-Processed Metal-Oxide Thin-Film Transistors

PubMed Central

Heo, Jae Sang; Choi, Seungbeom; Jo, Jeong-Wan; Kang, Jingu; Park, Ho-Hyun; Kim, Yong-Hoon; Park, Sung Kyu

2017-01-01

In this paper, we demonstrate high mobility solution-processed metal-oxide thin-film transistors (TFTs) by using a high-frequency-stable ionic-type hybrid gate dielectric (HGD). The HGD gate dielectric, a blend of sol-gel aluminum oxide (AlOx) and poly(4-vinylphenol) (PVP), exhibited high dielectric constant (ε~8.15) and high-frequency-stable characteristics (1 MHz). Using the ionic-type HGD as a gate dielectric layer, an minimal electron-double-layer (EDL) can be formed at the gate dielectric/InOx interface, enhancing the field-effect mobility of the TFTs. Particularly, using the ionic-type HGD gate dielectrics annealed at 350 °C, InOx TFTs having an average field-effect mobility of 16.1 cm2/Vs were achieved (maximum mobility of 24 cm2/Vs). Furthermore, the ionic-type HGD gate dielectrics can be processed at a low temperature of 150 °C, which may enable their applications in low-thermal-budget plastic and elastomeric substrates. In addition, we systematically studied the operational stability of the InOx TFTs using the HGD gate dielectric, and it was observed that the HGD gate dielectric effectively suppressed the negative threshold voltage shift during the negative-illumination-bias stress possibly owing to the recombination of hole carriers injected in the gate dielectric with the negatively charged ionic species in the HGD gate dielectric. PMID:28772972

Back-gated Nb-doped MoS2 junctionless field-effect-transistors

NASA Astrophysics Data System (ADS)

Mirabelli, Gioele; Schmidt, Michael; Sheehan, Brendan; Cherkaoui, Karim; Monaghan, Scott; Povey, Ian; McCarthy, Melissa; Bell, Alan P.; Nagle, Roger; Crupi, Felice; Hurley, Paul K.; Duffy, Ray

2016-02-01

Electrical measurements were carried out to measure the performance and evaluate the characteristics of MoS2 flakes doped with Niobium (Nb). The flakes were obtained by mechanical exfoliation and transferred onto 85 nm thick SiO2 oxide and a highly doped Si handle wafer. Ti/Au (5/45 nm) deposited on top of the flake allowed the realization of a back-gate structure, which was analyzed structurally through Scanning Electron Microscopy (SEM) and Transmission Electron Microscopy (TEM). To best of our knowledge this is the first cross-sectional TEM study of exfoliated Nb-doped MoS2 flakes. In fact to date TEM of transition-metal-dichalcogenide flakes is extremely rare in the literature, considering the recent body of work. The devices were then electrically characterized by temperature dependent Ids versus Vds and Ids versus Vbg curves. The temperature dependency of the device shows a semiconductor behavior and, the doping effect by Nb atoms introduces acceptors in the structure, with a p-type concentration 4.3 × 1019 cm-3 measured by Hall effect. The p-type doping is confirmed by all the electrical measurements, making the structure a junctionless transistor. In addition, other parameters regarding the contact resistance between the top metal and MoS2 are extracted thanks to a simple Transfer Length Method (TLM) structure, showing a promising contact resistivity of 1.05 × 10-7 Ω/cm2 and a sheet resistance of 2.36 × 102 Ω/sq.

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Macleod, Todd C.; Ho, Fat D.

2006-01-01

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

The electrical and interfacial properties of metal-high-k oxide-semiconductor field effect transistors with CeO2/HfO2 laminated gate dielectrics

NASA Astrophysics Data System (ADS)

Chang, Ingram Yin-ku; Chen, Chun-Heng; Chiu, Fu-Chien; Lee, Joseph Ya-min

2007-11-01

Metal-oxide-semiconductor field-effect transistors with CeO2/HfO2 laminated gate dielectrics were fabricated. The transistors have a subthreshold slope of 74.9mV/decade. The interfacial properties were measured using gated diodes. The surface state density Dit was 9.78×1011cm-2eV-1. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diode were about 6.11×103cm /s and 1.8×10-8s, respectively. The effective capture cross section of surface state (σs) extracted using the subthreshold-swing measurement and the gated diode was about 7.69×10-15cm2. The effective electron mobility of CeO2/HfO2 laminated gated transistors was determined to be 212cm2/Vs.

Field dependence of interface-trap buildup in polysilicon and metal gate MOS devices

NASA Astrophysics Data System (ADS)

Shaneyfelt, M. R.; Schwank, J. R.; Fleetwood, D. M.; Winokur, P. S.; Hughes, K. L.

1990-12-01

The electric field dependence of radiation-induced oxide- and interface-trap charge (Delta Vot and Delta Vit) generation for polysilicon- and metal-gate MOS transistors is investigated at electric fields (Eox) from -4.2 MV/cm to +4.7 MV/cm. If electron-hole recombination effects are taken into account, the absolute value of Delta Vot and the saturated value of Delta Vit for both polysilicon- and metal-gate transistors are shown to follow an approximate E exp -1/2 field dependence for Eox = 0.4 MV/cm or greater. An E exp -1/2 dependence for the saturated value of Delta Vit was also observed for negative-bias irradiation followed by a constant positive-bias anneal. The E exp -1/2 field dependence observed suggests that the total number of interface traps created in these devices may be determined by hole trapping near the Si/SiO2 interface for positive-bias irradiation or near the gate/SiO2 interface for negative bias irradiation, though H+ drift remains the likely rate-limiting step in the process. Based on these results, a hole-trapping/hydrogen transport model-involving hole trapping and subsequent near-interfacial H+ release, transport, and reaction at the interface-is proposed as a possible explanation of Delta Vit buildup in these polysilicon- and metal-gate transistors.

G4-FETs as Universal and Programmable Logic Gates

NASA Technical Reports Server (NTRS)

Johnson, Travis; Fijany, Amir; Mojarradi, Mohammad; Vatan, Farrokh; Toomarian, Nikzad; Kolawa, Elizabeth; Cristoloveanu, Sorin; Blalock, Benjamin

2007-01-01

An analysis of a patented generic silicon- on-insulator (SOI) electronic device called a G4-FET has revealed that the device could be designed to function as a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer discrete components than are required for conventional transistor-based circuits performing the same logic functions. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G4-FET can also be regarded as a single transistor having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of the SOI substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. With proper choice of the specific dimensions for the gates, channels, and ancillary features of the generic G4-FET, the device could be made to function as a three-input, one-output logic gate. As illustrated by the truth table in the top part of the figure, the behavior of this logic gate would be the inverse (the NOT) of that of a majority gate. In other words, the device would function as a NOT-majority gate. By simply adding an inverter, one could obtain a majority gate. In contrast, to construct a majority gate in conventional complementary metal oxide/semiconductor (CMOS) circuitry, one would need four three-input AND gates and a four-input OR gate, altogether containing 32 transistors.

Dopant-controlled single-electron pumping through a metallic island

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wenz, Tobias, E-mail: tobias.wenz@ptb.de; Hohls, Frank, E-mail: frank.hohls@ptb.de; Jehl, Xavier

We investigate a hybrid metallic island/single dopant electron pump based on fully depleted silicon-on-insulator technology. Electron transfer between the central metallic island and the leads is controlled by resonant tunneling through single phosphorus dopants in the barriers. Top gates above the barriers are used to control the resonance conditions. Applying radio frequency signals to the gates, non-adiabatic quantized electron pumping is achieved. A simple deterministic model is presented and confirmed by comparing measurements with simulations.

Approach to Multifunctional Device Platform with Epitaxial Graphene on Transition Metal Oxide (Postprint)

DTIC Science & Technology

2015-09-23

with a metal oxide ( TiO2 ). Our novel direct synthesis of graphene/ TiO2 heterostructure is achieved by C60 deposition on transition Ti metal surface...of TiO2 and C 2p orbitals in the conduction band of graphene enabled by Coulomb interactions at the interface. In addition, this heterostructure...provides a platform for realization of bottom gated graphene field effect devices with graphene and TiO2 playing the roles of channel and gate dielectric

Impact of Interface States and Bulk Carrier Lifetime on Photocapacitance of Metal/Insulator/GaN Structure for Ultraviolet Light Detection

NASA Astrophysics Data System (ADS)

Bidzinski, Piotr; Miczek, Marcin; Adamowicz, Boguslawa; Mizue, Chihoko; Hashizume, Tamotsu

2011-04-01

The influence of interface state density and bulk carrier lifetime on the dependencies of photocapacitance versus wide range of gate bias (-0.1 to -3 V) and light intensity (109 to 1020 photon cm-2 s-1) was studied for metal/insulator/n-GaN UV light photodetector by means of numerical simulations. The light detection limit and photocapacitance saturation were analyzed in terms of the interface charge and interface Fermi level for electrons and holes and effective interface recombination velocity. It was proven that the excess carrier recombination through interface states is the main reason of photocapacitance signal quenching. It was found that the photodetector can work in various modes (on-off or quantitative light measurement) adjusted by the gate bias. A comparison between experimental data and theoretical capacitance-light intensity characteristics was made. A new method for the determination of the interface state density distribution from capacitance-voltage-light intensity measurements was also proposed.

Modelling and simulation of parallel triangular triple quantum dots (TTQD) by using SIMON 2.0

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fathany, Maulana Yusuf, E-mail: myfathany@gmail.com; Fuada, Syifaul, E-mail: fsyifaul@gmail.com; Lawu, Braham Lawas, E-mail: bram-labs@rocketmail.com

2016-04-19

This research presents analysis of modeling on Parallel Triple Quantum Dots (TQD) by using SIMON (SIMulation Of Nano-structures). Single Electron Transistor (SET) is used as the basic concept of modeling. We design the structure of Parallel TQD by metal material with triangular geometry model, it is called by Triangular Triple Quantum Dots (TTQD). We simulate it with several scenarios using different parameters; such as different value of capacitance, various gate voltage, and different thermal condition.

A Survey of Corrosion and Conditions of Corrosion Protection Systems in Civil Works Structures of the U.S. Army Corps of Engineers

DTIC Science & Technology

2014-09-01

corrosion: coatings and cathodic protection (CP). Coatings consist of paints, epoxies, enamels , metalizing, and other coatings. CP is a chem- ical means...environmental factors such as water quality and resistivity. One of the major problems associated with lock gates is structural cracking in the...One of the problems described by Mr. Davis is fatigue crack growth resulting from the poor welding usually associated with stress risers and

Analytical Modeling of Triple-Metal Hetero-Dielectric DG SON TFET

NASA Astrophysics Data System (ADS)

Mahajan, Aman; Dash, Dinesh Kumar; Banerjee, Pritha; Sarkar, Subir Kumar

2018-02-01

In this paper, a 2-D analytical model of triple-metal hetero-dielectric DG TFET is presented by combining the concepts of triple material gate engineering and hetero-dielectric engineering. Three metals with different work functions are used as both front- and back gate electrodes to modulate the barrier at source/channel and channel/drain interface. In addition to this, front gate dielectric consists of high-K HfO2 at source end and low-K SiO2 at drain side, whereas back gate dielectric is replaced by air to further improve the ON current of the device. Surface potential and electric field of the proposed device are formulated solving 2-D Poisson's equation and Young's approximation. Based on this electric field expression, tunneling current is obtained by using Kane's model. Several device parameters are varied to examine the behavior of the proposed device. The analytical model is validated with TCAD simulation results for proving the accuracy of our proposed model.

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

NASA Astrophysics Data System (ADS)

Pavel, Akeed A.; Khan, Mehjabeen A.; Kirawanich, Phumin; Islam, N. E.

2008-10-01

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al 2O 3 has been compared with similar structure consisting of Si nanocrystals in SiO 2 to validate the concept.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

NASA Astrophysics Data System (ADS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-06-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr0.52Ti0.48)-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (gm-Vg) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

Near-thermal limit gating in heavily doped III-V semiconductor nanowires using polymer electrolytes

NASA Astrophysics Data System (ADS)

Ullah, A. R.; Carrad, D. J.; Krogstrup, P.; Nygârd, J.; Micolich, A. P.

2018-02-01

Doping is a common route to reducing nanowire transistor on-resistance but it has limits. A high doping level gives significant loss in gate performance and ultimately complete gate failure. We show that electrolyte gating remains effective even when the Be doping in our GaAs nanowires is so high that traditional metal-oxide gates fail. In this regime we obtain a combination of subthreshold swing and contact resistance that surpasses the best existing p -type nanowire metal-oxide semiconductor field-effect transistors (MOSFETs). Our subthreshold swing of 75 mV/dec is within 25 % of the room-temperature thermal limit and comparable with n -InP and n -GaAs nanowire MOSFETs. Our results open a new path to extending the performance and application of nanowire transistors, and motivate further work on improved solid electrolytes for nanoscale device applications.

Analyzing Single-Event Gate Ruptures In Power MOSFET's

NASA Technical Reports Server (NTRS)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

Effect of the axial magnetic field on a metallic gas-puff pinch implosion

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rousskikh, A. G.; Zhigalin, A. S.; Frolova, V.

2016-06-15

The effect of an axial magnetic field B{sub z} on an imploding metallic gas-puff Z-pinch was studied using 2D time-gated visible self-emission imaging. Experiments were performed on the IMRI-5 generator (450 kA, 450 ns). The ambient field B{sub z} was varied from 0.15 to 1.35 T. It was found that the initial density profile of a metallic gas-puff Z-pinch can be approximated by a power law. Time-gated images showed that the magneto-Rayleigh–Taylor instabilities were suppressed during the run-in phase both without axial magnetic field and with axial magnetic field. Helical instability structures were detected during the stagnation phase for B{sub z} < 1.1 T. For B{submore » z} = 1.35 T, the pinch plasma boundary was observed to be stable in both run-in and stagnation phases. When a magnetic field of 0.3 T was applied to the pinch, the soft x-ray energy was about twice that generated without axial magnetic field, mostly due to longer dwell time at stagnation.« less

Giant Gating Tunability of Optical Refractive Index in Transition Metal Dichalcogenide Monolayers.

PubMed

Yu, Yiling; Yu, Yifei; Huang, Lujun; Peng, Haowei; Xiong, Liwei; Cao, Linyou

2017-06-14

We report that the refractive index of transition metal dichacolgenide (TMDC) monolayers, such as MoS 2 , WS 2 , and WSe 2 , can be substantially tuned by >60% in the imaginary part and >20% in the real part around exciton resonances using complementary metal-oxide-semiconductor (CMOS) compatible electrical gating. This giant tunablility is rooted in the dominance of excitonic effects in the refractive index of the monolayers and the strong susceptibility of the excitons to the influence of injected charge carriers. The tunability mainly results from the effects of injected charge carriers to broaden the spectral width of excitonic interband transitions and to facilitate the interconversion of neutral and charged excitons. The other effects of the injected charge carriers, such as renormalizing bandgap and changing exciton binding energy, only play negligible roles. We also demonstrate that the atomically thin monolayers, when combined with photonic structures, can enable the efficiencies of optical absorption (reflection) tuned from 40% (60%) to 80% (20%) due to the giant tunability of the refractive index. This work may pave the way toward the development of field-effect photonics in which the optical functionality can be controlled with CMOS circuits.

Oxygen Displacement in Cuprates under Ionic Liquid Field-Effect Gating

PubMed Central

Dubuis, Guy; Yacoby, Yizhak; Zhou, Hua; He, Xi; Bollinger, Anthony T.; Pavuna, Davor; Pindak, Ron; Božović, Ivan

2016-01-01

We studied structural changes in a 5 unit cell thick La1.96Sr0.04CuO4 film, epitaxially grown on a LaSrAlO4 substrate with a single unit cell buffer layer, when ultra-high electric fields were induced in the film by applying a gate voltage between the film (ground) and an ionic liquid in contact with it. Measuring the diffraction intensity along the substrate-defined Bragg rods and analyzing the results using a phase retrieval method we obtained the three-dimensional electron density in the film, buffer layer, and topmost atomic layers of the substrate under different applied gate voltages. The main structural observations were: (i) there were no structural changes when the voltage was negative, holes were injected into the film making it more metallic and screening the electric field; (ii) when the voltage was positive, the film was depleted of holes becoming more insulating, the electric field extended throughout the film, the partial surface monolayer became disordered, and equatorial oxygen atoms were displaced towards the surface; (iii) the changes in surface disorder and the oxygen displacements were both reversed when a negative voltage was applied; and (iv) the c-axis lattice constant of the film did not change in spite of the displacement of equatorial oxygen atoms. PMID:27578237

Complementary Metal-Oxide-Silicon (CMOS)-Memristor Hybrid Nanoelectronics for Advanced Encryption Standard (AES) Encryption

DTIC Science & Technology

2016-04-01

with Al top electrodes and Cu bottom electrodes. ................... 9 Figure 4. SPICE netlist structure...memory elements play a part in logic gate. 4.4.2 Simulation SPICE Simulation Program for Integrated Circuits Emphasis ( SPICE ) is a general-purpose...analog circuit simulator that was developed at the Electronics Research Laboratory of the University of California, Berkeley [6]. In 1975, SPICE

Atomic layer deposited TaCy metal gates: Impact on microstructure, electrical properties, and work function on HfO2 high-k dielectrics

NASA Astrophysics Data System (ADS)

Triyoso, D. H.; Gregory, R.; Schaeffer, J. K.; Werho, D.; Li, D.; Marcus, S.; Wilk, G. D.

2007-11-01

TaCy has been reported to have the appropriate work function for negative metal-oxide semiconductor metal in high-k metal-oxide field-effect transistors. As device size continues to shrink, a conformal deposition for metal gate electrodes is needed. In this work, we report on the development and characterization of a novel TaCy process by atomic layer deposition (ALD). Detailed physical properties of TaCy films are studied using ellipsometry, a four-point probe, Rutherford backscattering spectrometry (RBS), x-ray photoelectron spectroscopy (XPS), and x-ray diffraction (XRD). RBS and XPS analysis indicate that TaCy films are near-stoichiometric, nitrogen free, and have low oxygen impurities. Powder XRD spectra showed that ALD films have a cubic microstructure. XPS carbon bonding studies revealed that little or no glassy carbon is present in the bulk of the film. Excellent electrical properties are obtained using ALD TaCy as a metal gate electrode. Well-behaved capacitance-voltage characteristics with ALD HfO2 gate dielectrics are demonstrated for TaCy thicknesses of 50, 100, and 250 Å. A low fixed charge (˜2-4×10-11 cm-2) is observed for all ALD HfO2/ALD TaCy devices. Increasing the thickness of ALD TaCy results in a decrease in work function (4.77 to 4.54 eV) and lower threshold voltages.

Gas-controlled dynamic vacuum insulation with gas gate

DOEpatents

Benson, David K.; Potter, Thomas F.

1994-06-07

Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber.

Gas-controlled dynamic vacuum insulation with gas gate

DOEpatents

Benson, D.K.; Potter, T.F.

1994-06-07

Disclosed is a dynamic vacuum insulation comprising sidewalls enclosing an evacuated chamber and gas control means for releasing hydrogen gas into a chamber to increase gas molecule conduction of heat across the chamber and retrieving hydrogen gas from the chamber. The gas control means includes a metal hydride that absorbs and retains hydrogen gas at cooler temperatures and releases hydrogen gas at hotter temperatures; a hydride heating means for selectively heating the metal hydride to temperatures high enough to release hydrogen gas from the metal hydride; and gate means positioned between the metal hydride and the chamber for selectively allowing hydrogen to flow or not to flow between said metal hydride and said chamber. 25 figs.

Dimensionality-Driven Metal-Insulator Transition in Spin-Orbit-Coupled SrIrO3

NASA Astrophysics Data System (ADS)

Schütz, P.; Di Sante, D.; Dudy, L.; Gabel, J.; Stübinger, M.; Kamp, M.; Huang, Y.; Capone, M.; Husanu, M.-A.; Strocov, V. N.; Sangiovanni, G.; Sing, M.; Claessen, R.

2017-12-01

Upon reduction of the film thickness we observe a metal-insulator transition in epitaxially stabilized, spin-orbit-coupled SrIrO3 ultrathin films. By comparison of the experimental electronic dispersions with density functional theory at various levels of complexity we identify the leading microscopic mechanisms, i.e., a dimensionality-induced readjustment of octahedral rotations, magnetism, and electronic correlations. The astonishing resemblance of the band structure in the two-dimensional limit to that of bulk Sr2 IrO4 opens new avenues to unconventional superconductivity by "clean" electron doping through electric field gating.

Field ionization characteristics of an ion source array for neutron generators

NASA Astrophysics Data System (ADS)

Bargsten Johnson, B.; Schwoebel, P. R.; Resnick, P. J.; Holland, C. E.; Hertz, K. L.; Chichester, D. L.

2013-11-01

A new deuterium ion source is being developed to improve the performance of existing compact neutron generators. The ion source is a microfabricated array of metal tips with an integrated gate (i.e., grid) and produces deuterium ions by field ionizing (or field desorbing) a supply of deuterium gas. Deuterium field ion currents from arrays at source temperatures of 77 K and 293 K are studied. Ion currents from single etched-wire tips operating under the same conditions are used to help understand array results. I-F characteristics of the arrays were found to follow trends similar to those of the better understood single etched-wire tip results; however, the fields achieved by the arrays are limited by electrical breakdown of the structure. Neutron production by field ionization at 293 K was demonstrated for the first time from microfabricated array structures with integrated gates.

Electrochemically Induced Insulator-Metal-Insulator Transformations of Vanadium Dioxide Nanocrystal Films

NASA Astrophysics Data System (ADS)

Milliron, Delia; Dahlman, Clayton; Leblanc, Gabriel; Bergerud, Amy

Vanadium dioxide (VO2) undergoes significant optical, electronic, and structural changes as it transforms between the low-temperature monoclinic and high-temperature rutile phases. The low-temperature state is insulating and transparent, while the high-temperature state is metallic and IR blocking. Alternative stimuli have been utilized to trigger insulator-to-metal transformations in VO2, including electrochemical gating. Here, VO2 nanocrystal films have been prepared by solution deposition of V2O3 nanocrystals followed by oxidative annealing. Nanocrystalline VO2 films are electrochemically reduced, inducing changes in their electronic and optical properties. We observe a reversible transition between infrared transparent insulating phases and a darkened metallic phase by in situ visible-near-infrared spectroelectrochemistry and correlate these observations with structural and electronic changes monitored by X-ray absorption spectroscopy, X-ray diffraction, Raman spectroscopy, and conductivity measurements. Reduction causes an initial transformation to a metallic, IR-colored distorted monoclinic phase. However, an unexpected reversible transition from conductive, reduced monoclinic VO2 to an infrared-transparent insulating phase is observed upon further reduction.

Investigation of abrupt degradation of drain current caused by under-gate crack in AlGaN/GaN high electron mobility transistors during high temperature operation stress

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zeng, Chang; Liao, XueYang; Li, RuGuan

2015-09-28

In this paper, we investigate the degradation mode and mechanism of AlGaN/GaN based high electron mobility transistors (HEMTs) during high temperature operation (HTO) stress. It demonstrates that there was abrupt degradation mode of drain current during HTO stress. The abrupt degradation is ascribed to the formation of crack under the gate which was the result of the brittle fracture of epilayer based on failure analysis. The origin of the mechanical damage under the gate is further investigated and discussed based on top-down scanning electron microscope, cross section transmission electron microscope and energy dispersive x-ray spectroscopy analysis, and stress simulation. Basedmore » on the coupled analysis of the failure physical feature and stress simulation considering the coefficient of thermal expansion (CTE) mismatch in different materials in gate metals/semiconductor system, the mechanical damage under the gate is related to mechanical stress induced by CTE mismatch in Au/Ti/Mo/GaN system and stress concentration caused by the localized structural damage at the drain side of the gate edge. These results indicate that mechanical stress induced by CTE mismatch of materials inside the device plays great important role on the reliability of AlGaN/GaN HEMTs during HTO stress.« less

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors with atomic layer deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Lin, H. C.; Yang, T.; Sharifi, H.; Kim, S. K.; Xuan, Y.; Shen, T.; Mohammadi, S.; Ye, P. D.

2007-11-01

Enhancement-mode GaAs metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with ex situ atomic-layer-deposited Al2O3 as gate dielectrics are studied. Maximum drain currents of 211 and 263mA/mm are obtained for 1μm gate-length Al2O3 MOS-HEMTs with 3 and 6nm thick gate oxide, respectively. C-V characteristic shows negligible hysteresis and frequency dispersion. The gate leakage current density of the MOS-HEMTs is 3-5 orders of magnitude lower than the conventional HEMTs under similar bias conditions. The drain current on-off ratio of MOS-HEMTs is ˜3×103 with a subthreshold swing of 90mV/decade. A maximum cutoff frequency (fT) of 27.3GHz and maximum oscillation frequency (fmax) of 39.9GHz and an effective channel mobility of 4250cm2/Vs are measured for the 1μm gate-length Al2O3 MOS-HEMT with 6nm gate oxide. Hooge's constant measured by low frequency noise spectral density characterization is 3.7×10-5 for the same device.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Characterization of silicon-gate CMOS/SOS integrated circuits processed with ion implantation

NASA Technical Reports Server (NTRS)

Woo, D. S.

1980-01-01

The double layer metallization technology applied on p type silicon gate CMOS/SOS integrated circuits is described. A smooth metal surface was obtained by using the 2% Si-sputtered Al. More than 10% probe yield was achieved on solar cell controller circuit TCS136 (or MSFC-SC101). Reliability tests were performed on 15 arrays at 150 C. Only three arrays failed during the burn in, and 18 arrays out of 22 functioning arrays maintained the leakage current below 100 milli-A. Analysis indicates that this technology will be a viable process if the metal short circuit problem between the two metals can be reduced.

Integrating Partial Polarization into a Metal-Ferroelectric-Semiconductor Field Effect Transistor Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Ho, Fat Duen

1999-01-01

The ferroelectric channel in a Metal-Ferroelectric-Semiconductor Field Effect Transistor (MFSFET) can partially change its polarization when the gate voltage near the polarization threshold voltage. This causes the MFSFET Drain current to change with repeated pulses of the same gate voltage near the polarization threshold voltage. A previously developed model [11, based on the Fermi-Dirac function, assumed that for a given gate voltage and channel polarization, a sin-le Drain current value would be generated. A study has been done to characterize the effects of partial polarization on the Drain current of a MFSFET. These effects have been described mathematically and these equations have been incorporated into a more comprehensive mathematical model of the MFSFET. The model takes into account the hysteresis nature of the MFSFET and the time dependent decay as well as the effects of partial polarization. This model defines the Drain current based on calculating the degree of polarization from previous gate pulses, the present Gate voltage, and the amount of time since the last Gate volta-e pulse.

Interface Engineering for Atomic Layer Deposited Alumina Gate Dielectric on SiGe Substrates.

PubMed

Zhang, Liangliang; Guo, Yuzheng; Hassan, Vinayak Vishwanath; Tang, Kechao; Foad, Majeed A; Woicik, Joseph C; Pianetta, Piero; Robertson, John; McIntyre, Paul C

2016-07-27

Optimization of the interface between high-k dielectrics and SiGe substrates is a challenging topic due to the complexity arising from the coexistence of Si and Ge interfacial oxides. Defective high-k/SiGe interfaces limit future applications of SiGe as a channel material for electronic devices. In this paper, we identify the surface layer structure of as-received SiGe and Al2O3/SiGe structures based on soft and hard X-ray photoelectron spectroscopy. As-received SiGe substrates have native SiOx/GeOx surface layers, where the GeOx-rich layer is beneath a SiOx-rich surface. Silicon oxide regrows on the SiGe surface during Al2O3 atomic layer deposition, and both SiOx and GeOx regrow during forming gas anneal in the presence of a Pt gate metal. The resulting mixed SiOx-GeOx interface layer causes large interface trap densities (Dit) due to distorted Ge-O bonds across the interface. In contrast, we observe that oxygen-scavenging Al top gates decompose the underlying SiOx/GeOx, in a selective fashion, leaving an ultrathin SiOx interfacial layer that exhibits dramatically reduced Dit.

Fabrication and characterization of heterojunction transistors

NASA Astrophysics Data System (ADS)

Lo, Chien-Fong

2011-12-01

Submircon emitter finger high-speed double heterojunction InAlAs/InGaAsSb/InGaAs bipolar transistors (DHBTs) and a variety of nitride high electron mobility transistors (HEMTs) including AlGaN/GaN, InAlN/GaN, and AlN/GaN were fabricated and characterized. DHBT structures were grown by solid source molecular beam epitaxy (SSMBE) on Fe-doped semiinsulating InP substrates and nitride HEMTs were grown with a metal organic chemical vapor deposition (MOCVD) system on sapphire or SiC substrates. AlN/GaN HEMTs were grown with a RF-VMBE on sapphire substrates. Ultra low base contact resistance of 3.7 x 10-7 ohm-cm2 after 1 min 250¢XC thermal treatment on noval InGaAsSb base of DHBTs was achieved and a long-term thermal stability of base metallization was studied. Regarding small scale DHBT fabrication, tri-layer system was introduced to improve the resolution for submicron emitter patterning and help to pile up a thicker emitter metal stack; guard-ring technique was applied around the emitter periphery in order to preserve the current gain at small emitter dimensions. Ultra low turn-on voltage and high current gain can be realized with InGaAsSb-base DHBTs as compared to the conventional InGaAs-base DHBTs. A peak current gain cutoff frequency (fT) of 268 GHz and power gain cutoff frequency (fmax) of 485 GHz were achieved. GaN-based HEMTs herein were fabricated with gate lengths from 400 nm to 1im, and were deposited Ti/Al/Ni/Au as their Ohmic contact metallization. Effects of the Ohmic contact annealing for lattice-matched InAlN/GaN HEMTs with and without a thin GaN cap layer were exhibited and their optimal annealing temperature were obtained. A maximum drain current of 1.3 A/mm and an extrinsic transconductance of 366 mS/mm were demonstrated for InAlN/GaN HEMTs with the shortest gate length. A unity-gain cutoff frequency (fT) of 69 GHz and a maximum frequency of oscillation (fmax) of 80 GHz for InAlN/GaN HEMTs were extracted from measured scattering parameters. Passivation is one of the most important parts in device processing for preventing degradation from various environmental conditions and promising a better device performance. Simply, ozone treatment of AlN on AlN/GaN heterostructures produced effective aluminum oxide surface passivation and chemical resistance to the AZ positive photoresist developer used for subsequent device fabrication. Metal oxide semiconductor diode-like gate current-voltage characteristics and minimal drain current degradation during gate pulse measurements were observed. With an additional oxygen plasma treatment on the gate area prior to the gate metal deposition, enhancement-mode AlN/GaN HEMTs were realized. In addition, for AlGaN/GaN HEMTs in high electrical field applications, a high-dielectric-strength SiNx passivation over an optimum thickness was needed to suppress surface flashover during a high voltage or high power operation. An excellent isolation blocking voltage of 900 V with a leakage current at 1 muA/mm was obtained across a nitrogen-implanted isolation-gap of 10 mum between two Ohmic pads. The radiation hardness of HBTs and HEMTs is one of the critical factors that need to be established for military, space, and nuclear industry applications. The effects of proton radiation on the dc performance of InAlAs/InGaAsSb/InGaAs HBTs and AlN/GaN HEMTs were investigated. Both of these devices showed a remarkable resistance to high energy protoninduced degradation and appeared very promising for terrestrial or space-borne applications. The proton-irradiated devices with a dose of 2 x 1011 cm-2 (estimated to be equivalent to more than 40 years of exposure in low-earth orbit) showed only small changes in dc transfer characteristics, threshold voltage shift, and gate-lag with a high frequency pulse on the gate of the HEMTs and showed small changes in junction ideality factor, generation recombination leakage current, and output conductance for the HBTs. The effect the gate metallization on the nitride HEMT reliability was also examined. By replacing the conventional Ni/Au gate metallization with Pt/Ti/Au, the critical voltage for degradation of AlGaN/GaN HEMTs during off-state biasing stress was significantly improved from -55 V to over larger than -100 V. Besides the irradiation or high voltage stresses, the effects of ambient on the Pt-gated HEMT sensor for gas sensing application were also explored. For the hydrogen sensing, the sensitivity decreased proportional to the relative humidity but the presence of humidity dramatically improved the sensor recovery characteristics after exposure to the hydrogen ambient.

Insulator to metal transition in WO 3 induced by electrolyte gating

DOE PAGES

Leng, X.; Pereiro, J.; Strle, J.; ...

2017-07-03

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

PubMed

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Study of fully-depleted Ge double-gate n-type Tunneling Field-Effect Transistors for improvement in on-state current and sub-threshold swing

NASA Astrophysics Data System (ADS)

Liu, Xiangyu; Hu, Huiyong; Wang, Meng; Zhang, Heming; Cui, Shimin; Shu, Bin; Wang, Bin

2018-01-01

In this paper, a fully-depleted (FD) Ge double-gate (DG) n-type Tunneling Field-Effect Transistors (TFET) structure is studied in detail by two-dimensional numerical simulation. The simulation results indicated that the on-state current Ion and on-off ratio of the FD Ge DG-TFET increases about 1 order of magnitude comparing with the Conventional Ge DG-TFET, and Ion=3.95×10-5 A/μm and the below 60 mV/decade subthreshold swing S=26.4 mV/decade are achieved with the length of gate LD=20 nm, the workfuntion of metal gate Φm=0.2 eV and the doping concentration of n+-type-channel ND=1×1018 cm-3. Moreover, the impacts of Φm, ND and LD are investigated. The simulation results indicated that the off-state current Ioff includes the tunneling current at the middle of channel IB the gated-induced drain leakage (GIDL) current IGIDL. With optimized Φm and ND, Ioff is reduced about 2 orders of magnitude to 2.5×10-13 A/μm with LD increasing from 40 nm to 100 nm, and on-off ratio is increased to 1.58×107.

G(sup 4)FET Implementations of Some Logic Circuits

NASA Technical Reports Server (NTRS)

Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan

2009-01-01

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Low temperature mobility in hafnium-oxide gated germanium p-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Beer, Chris; Whall, Terry; Parker, Evan; Leadley, David; De Jaeger, Brice; Nicholas, Gareth; Zimmerman, Paul; Meuris, Marc; Szostak, Slawomir; Gluszko, Grzegorz; Lukasiak, Lidia

2007-12-01

Effective mobility measurements have been made at 4.2K on high performance high-k gated germanium p-type metal-oxide-semiconductor field effect transistors with a range of Ge/gate dielectric interface state densities. The mobility is successfully modelled by assuming surface roughness and interface charge scattering at the SiO2 interlayer/Ge interface. The deduced interface charge density is approximately equal to the values obtained from the threshold voltage and subthreshold slope measurements on each device. A hydrogen anneal reduces both the interface state density and the surface root mean square roughness by 20%.

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, Paul G.; Smith, Patrick M.; Sigmon, Thomas W.; Aceves, Randy C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Glutathione-facilitated design and fabrication of gold nanoparticle-based logic gates and keypad lock.

PubMed

Huang, Zhenzhen; Wang, Haonan; Yang, Wensheng

2014-07-21

In this paper, we describe how we developed a simple design and fabrication method for logic gates and a device by using a commercially available tripeptide, namely glutathione (GSH), together with metal ions and disodium ethylenediaminetetraacetate (EDTA) to control the dispersion and aggregation of gold nanoparticles (NPs). With the fast adsorption of GSH on gold NPs and the strong coordination of GSH with metal ions, the addition of GSH and Pb(2+) ions immediately resulted in the aggregation of gold NPs, giving rise to an AND function. Either Pb(2+) or Ba(2+) ions induced the aggregation of gold NPs in the presence of GSH, supporting an OR gate. Based on the fact that EDTA has a strong capacity to bind metal ions, thus preventing the aggregation of gold NPs, an INHIBIT gate was also fabricated. More interestingly, we found that the addition sequence of GSH and Hg(2+) ions influenced the aggregation of gold NPs in a controlled manner, which was used to design a sequential logic gate and a three-input keypad lock for potential use in information security. The GSH strategy addresses concerns of low cost, simple fabrication, versatile design and easy operation, and offers a promising platform for the development of functional logic systems.

Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

PubMed Central

Long, Rathnait D.; McIntyre, Paul C.

2012-01-01

The literature on polar Gallium Nitride (GaN) surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS) devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

Quantum Mechanical Modeling of Ballistic MOSFETs

NASA Technical Reports Server (NTRS)

Svizhenko, Alexei; Anantram, M. P.; Govindan, T. R.; Biegel, Bryan (Technical Monitor)

2001-01-01

The objective of this project was to develop theory, approximations, and computer code to model quasi 1D structures such as nanotubes, DNA, and MOSFETs: (1) Nanotubes: Influence of defects on ballistic transport, electro-mechanical properties, and metal-nanotube coupling; (2) DNA: Model electron transfer (biochemistry) and transport experiments, and sequence dependence of conductance; and (3) MOSFETs: 2D doping profiles, polysilicon depletion, source to drain and gate tunneling, understand ballistic limit.

Dissipation in graphene and nanotube resonators

NASA Astrophysics Data System (ADS)

Seoánez, C.; Guinea, F.; Castro Neto, A. H.

2007-09-01

Different damping mechanisms in graphene nanoresonators are studied: charges in the substrate, ohmic losses in the substrate and the graphene sheet, breaking and healing of surface bonds (Velcro effect), two level systems, attachment losses, and thermoelastic losses. We find that, for realistic structures and contrary to semiconductor resonators, dissipation is dominated by ohmic losses in the graphene layer and metallic gate. An extension of this study to carbon nanotube-based resonators is presented.

Superconductivity Series in Transition Metal Dichalcogenides by Ionic Gating

PubMed Central

Shi, Wu; Ye, Jianting; Zhang, Yijin; Suzuki, Ryuji; Yoshida, Masaro; Miyazaki, Jun; Inoue, Naoko; Saito, Yu; Iwasa, Yoshihiro

2015-01-01

Functionalities of two-dimensional (2D) crystals based on semiconducting transition metal dichalcogenides (TMDs) have now stemmed from simple field effect transistors (FETs) to a variety of electronic and opto-valleytronic devices, and even to superconductivity. Among them, superconductivity is the least studied property in TMDs due to methodological difficulty accessing it in different TMD species. Here, we report the systematic study of superconductivity in MoSe2, MoTe2 and WS2 by ionic gating in different regimes. Electrostatic gating using ionic liquid was able to induce superconductivity in MoSe2 but not in MoTe2 because of inefficient electron accumulation limited by electronic band alignment. Alternative gating using KClO4/polyethylene glycol enabled a crossover from surface doping to bulk doping, which induced superconductivities in MoTe2 and WS2 electrochemically. These new varieties greatly enriched the TMD superconductor families and unveiled critical methodology to expand the capability of ionic gating to other materials. PMID:26235962

Superconductivity Series in Transition Metal Dichalcogenides by Ionic Gating.

PubMed

Shi, Wu; Ye, Jianting; Zhang, Yijin; Suzuki, Ryuji; Yoshida, Masaro; Miyazaki, Jun; Inoue, Naoko; Saito, Yu; Iwasa, Yoshihiro

2015-08-03

Functionalities of two-dimensional (2D) crystals based on semiconducting transition metal dichalcogenides (TMDs) have now stemmed from simple field effect transistors (FETs) to a variety of electronic and opto-valleytronic devices, and even to superconductivity. Among them, superconductivity is the least studied property in TMDs due to methodological difficulty accessing it in different TMD species. Here, we report the systematic study of superconductivity in MoSe2, MoTe2 and WS2 by ionic gating in different regimes. Electrostatic gating using ionic liquid was able to induce superconductivity in MoSe2 but not in MoTe2 because of inefficient electron accumulation limited by electronic band alignment. Alternative gating using KClO4/polyethylene glycol enabled a crossover from surface doping to bulk doping, which induced superconductivities in MoTe2 and WS2 electrochemically. These new varieties greatly enriched the TMD superconductor families and unveiled critical methodology to expand the capability of ionic gating to other materials.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Tao; Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016; Xu, Ruimin

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectricmore » constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.« less

Near interface traps in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors monitored by temperature dependent gate current transient measurements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fiorenza, Patrick; La Magna, Antonino; Vivona, Marilena

This letter reports on the impact of gate oxide trapping states on the conduction mechanisms in SiO{sub 2}/4H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs). The phenomena were studied by gate current transient measurements, performed on n-channel MOSFETs operated in “gate-controlled-diode” configuration. The measurements revealed an anomalous non-steady conduction under negative bias (V{sub G} > |20 V|) through the SiO{sub 2}/4H-SiC interface. The phenomenon was explained by the coexistence of a electron variable range hopping and a hole Fowler-Nordheim (FN) tunnelling. A semi-empirical modified FN model with a time-depended electric field is used to estimate the near interface traps in the gate oxide (N{sub trap} ∼ 2 × 10{supmore » 11} cm{sup −2}).« less

Gate-Induced Interfacial Superconductivity in 1T-SnSe2.

PubMed

Zeng, Junwen; Liu, Erfu; Fu, Yajun; Chen, Zhuoyu; Pan, Chen; Wang, Chenyu; Wang, Miao; Wang, Yaojia; Xu, Kang; Cai, Songhua; Yan, Xingxu; Wang, Yu; Liu, Xiaowei; Wang, Peng; Liang, Shi-Jun; Cui, Yi; Hwang, Harold Y; Yuan, Hongtao; Miao, Feng

2018-02-14

Layered metal chalcogenide materials provide a versatile platform to investigate emergent phenomena and two-dimensional (2D) superconductivity at/near the atomically thin limit. In particular, gate-induced interfacial superconductivity realized by the use of an electric-double-layer transistor (EDLT) has greatly extended the capability to electrically induce superconductivity in oxides, nitrides, and transition metal chalcogenides and enable one to explore new physics, such as the Ising pairing mechanism. Exploiting gate-induced superconductivity in various materials can provide us with additional platforms to understand emergent interfacial superconductivity. Here, we report the discovery of gate-induced 2D superconductivity in layered 1T-SnSe 2 , a typical member of the main-group metal dichalcogenide (MDC) family, using an EDLT gating geometry. A superconducting transition temperature T c ≈ 3.9 K was demonstrated at the EDL interface. The 2D nature of the superconductivity therein was further confirmed based on (1) a 2D Tinkham description of the angle-dependent upper critical field B c2 , (2) the existence of a quantum creep state as well as a large ratio of the coherence length to the thickness of superconductivity. Interestingly, the in-plane B c2 approaching zero temperature was found to be 2-3 times higher than the Pauli limit, which might be related to an electric field-modulated spin-orbit interaction. Such results provide a new perspective to expand the material matrix available for gate-induced 2D superconductivity and the fundamental understanding of interfacial superconductivity.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

Investigation of field induced trapping on floating gates

NASA Technical Reports Server (NTRS)

Gosney, W. M.

1975-01-01

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

NASA Astrophysics Data System (ADS)

Maheran, A. H. Afifah; Menon, P. S.; Ahmad, I.; Shaari, S.; Faizah, Z. A. Noor

2015-04-01

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (ILEAK) on PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO2) and tungsten silicide (WSix). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum ILEAK where the maximum predicted ILEAK value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device's leakage current. The absolute process parameters combination results in ILEAK mean value of 3.96821 nA/µm where is far lower than the predicted value.

Development of process parameters for 22 nm PMOS using 2-D analytical modeling

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maheran, A. H. Afifah; Menon, P. S.; Shaari, S.

2015-04-24

The complementary metal-oxide-semiconductor field effect transistor (CMOSFET) has become major challenge to scaling and integration. Innovation in transistor structures and integration of novel materials are necessary to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern due to limitation of process control; over statistically variability related to the fundamental discreteness and materials. Minimizing the transistor variation through technology optimization and ensuring robust product functionality and performance is the major issue.In this article, the continuation study on process parameters variations is extended and delivered thoroughly in order to achieve a minimum leakage current (I{sub LEAK}) onmore » PMOS planar transistor at 22 nm gate length. Several device parameters are varies significantly using Taguchi method to predict the optimum combination of process parameters fabrication. A combination of high permittivity material (high-k) and metal gate are utilized accordingly as gate structure where the materials include titanium dioxide (TiO{sub 2}) and tungsten silicide (WSi{sub x}). Then the L9 of the Taguchi Orthogonal array is used to analyze the device simulation where the results of signal-to-noise ratio (SNR) of Smaller-the-Better (STB) scheme are studied through the percentage influences of the process parameters. This is to achieve a minimum I{sub LEAK} where the maximum predicted I{sub LEAK} value by International Technology Roadmap for Semiconductors (ITRS) 2011 is said to should not above 100 nA/µm. Final results shows that the compensation implantation dose acts as the dominant factor with 68.49% contribution in lowering the device’s leakage current. The absolute process parameters combination results in I{sub LEAK} mean value of 3.96821 nA/µm where is far lower than the predicted value.« less

Impact of post metal annealing on gate work function engineering for advanced MOS applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kumar, S. Sachin, E-mail: ssachikl995@yahoo.in; Prasad, Amitesh; Sinha, Amrita

2016-05-06

Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by Atomic Layer Deposition (ALD) technique. The influence of different types of metal gate electrodes (Al, Au, Pt) on electrical characteristics of Metal-Oxide-Semiconductor capacitors has been studied. Our results show that the electrical characteristics of MOS device are highly dependent on the gate electrodes used. The dependency of electrical characteristics on post metal annealing was studied in detail. The measured flat band (V{sub fb}) and hysteresis (ΔV{sub fb}) from high frequency C-V characteristics were used to study the pre-existing traps in the dielectric. Impactmore » of PMA on interface state density (D{sub it}), border trap density (N{sub bt}) and oxide trap density (Q{sub f/q}) of high-k gate stack were also examined for all the devices. The N{sub bt} and frequency dispersion significantly reduces to ~2.77x1010 cm{sup −2} and ~11.34 % respectively in case of Al electrode with a Dit value of ~4x10{sup 12} eV{sup −1}cm{sup −2} after PMA (350°C) in N{sub 2}, suggesting an improvement in device performance while Pt electrode shows a much less value of ΔVfb (~0.02 V) and Dit (~3.44x10{sup 12} eV{sup −1}cm{sup −2}) after PMA.« less

Piezo-phototronic Boolean logic and computation using photon and strain dual-gated nanowire transistors.

PubMed

Yu, Ruomeng; Wu, Wenzhuo; Pan, Caofeng; Wang, Zhaona; Ding, Yong; Wang, Zhong Lin

2015-02-04

Using polarization charges created at the metal-cadmium sulfide interface under strain to gate/modulate electrical transport and optoelectronic processes of charge carriers, the piezo-phototronic effect is applied to process mechanical and optical stimuli into electronic controlling signals. The cascade nanowire networks are demonstrated for achieving logic gates, binary computations, and gated D latches to store information carried by these stimuli. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

A highly manufacturable 0.2 {mu}m AlGaAs/InGaAs PHEMT fabricated using the single-layer integrated-metal FET (SLIMFET) process

DOE Office of Scientific and Technical Information (OSTI.GOV)

Havasy, C.K.; Quach, T.K.; Bozada, C.A.

1995-12-31

This work is the development of a single-layer integrated-metal field effect transistor (SLIMFET) process for a high performance 0.2 {mu}m AlGaAs/InGaAs pseudomorphic high electron mobility transistor (PHEMT). This process is compatible with MMIC fabrication and minimizes process variations, cycle time, and cost. This process uses non-alloyed ohmic contacts, a selective gate-recess etching process, and a single gate/source/drain metal deposition step to form both Schottky and ohmic contacts at the same time.

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

NASA Astrophysics Data System (ADS)

Yoon, Seonno; Lee, Seungmin; Kim, Hyun-Seop; Cha, Ho-Young; Lee, Hi-Deok; Oh, Jungwoo

2018-01-01

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance-voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of -20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10-7 mA mm-1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.

1992-06-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.

Degradation Mechanisms for GaN and GaAs High Speed Transistors

PubMed Central

Cheney, David J.; Douglas, Erica A.; Liu, Lu; Lo, Chien-Fong; Gila, Brent P.; Ren, Fan; Pearton, Stephen J.

2012-01-01

We present a review of reliability issues in AlGaN/GaN and AlGaAs/GaAs high electron mobility transistors (HEMTs) as well as Heterojunction Bipolar Transistors (HBTs) in the AlGaAs/GaAs materials systems. Because of the complex nature and multi-faceted operation modes of these devices, reliability studies must go beyond the typical Arrhenius accelerated life tests. We review the electric field driven degradation in devices with different gate metallization, device dimensions, electric field mitigation techniques (such as source field plate), and the effect of device fabrication processes for both DC and RF stress conditions. We summarize the degradation mechanisms that limit the lifetime of these devices. A variety of contact and surface degradation mechanisms have been reported, but differ in the two device technologies: For HEMTs, the layers are thin and relatively lightly doped compared to HBT structures and there is a metal Schottky gate that is directly on the semiconductor. By contrast, the HBT relies on pn junctions for current modulation and has only Ohmic contacts. This leads to different degradation mechanisms for the two types of devices.

Gate-tunable memristive phenomena mediated by grain boundaries in single-layer MoS2

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Jariwala, Deep; Kim, In Soo; Chen, Kan-Sheng; Marks, Tobin J.; Lauhon, Lincoln J.; Hersam, Mark C.

2015-05-01

Continued progress in high-speed computing depends on breakthroughs in both materials synthesis and device architectures. The performance of logic and memory can be enhanced significantly by introducing a memristor, a two-terminal device with internal resistance that depends on the history of the external bias voltage. State-of-the-art memristors, based on metal-insulator-metal (MIM) structures with insulating oxides, such as TiO2, are limited by a lack of control over the filament formation and external control of the switching voltage. Here, we report a class of memristors based on grain boundaries (GBs) in single-layer MoS2 devices. Specifically, the resistance of GBs emerging from contacts can be easily and repeatedly modulated, with switching ratios up to ˜103 and a dynamic negative differential resistance (NDR). Furthermore, the atomically thin nature of MoS2 enables tuning of the set voltage by a third gate terminal in a field-effect geometry, which provides new functionality that is not observed in other known memristive devices.

Oxygen Displacement in Cuprates under IonicLiquid Field-Effect Gating

DOE Office of Scientific and Technical Information (OSTI.GOV)

Dubuis, Guy; Yacoby, Yizhak; Zhou, Hua

We studied structural changes in a 5 unit cell thick La 1.96Sr 0.04CuO 4 film, epitaxially grown on a LaSrAlO 4 substrate with a single unit cell buffer layer, when ultra-high electric fields were induced in the film by applying a gate voltage between the film and an ionic liquid in contact with it. Measuring the diffraction intensity along the substrate-defined Bragg rods and analyzing the results using a phase retrieval method we obtained the three-dimensional electron density in the film, buffer layer, and topmost atomic layers of the substrate under different applied gate voltages. The main structural observations were:more » (i) there were no structural changes when the voltage was negative, holes were injected into the film making it more metallic and screening the electric field; (ii) when the voltage was positive, the film was depleted of holes becoming more insulating, the electric field extended throughout the film, the partial surface monolayer became disordered, and planar oxygen atoms were displaced towards the sample surface; (iii) the changes in surface disorder and the oxygen displacements were both reversed when a negative voltage was applied; and (iv) the c-axis lattice constant of the film did not change in spite of the displacement of planar oxygen atoms.« less

Oxygen Displacement in Cuprates under IonicLiquid Field-Effect Gating

DOE PAGES

Dubuis, Guy; Yacoby, Yizhak; Zhou, Hua; ...

2016-08-15

We studied structural changes in a 5 unit cell thick La 1.96Sr 0.04CuO 4 film, epitaxially grown on a LaSrAlO 4 substrate with a single unit cell buffer layer, when ultra-high electric fields were induced in the film by applying a gate voltage between the film and an ionic liquid in contact with it. Measuring the diffraction intensity along the substrate-defined Bragg rods and analyzing the results using a phase retrieval method we obtained the three-dimensional electron density in the film, buffer layer, and topmost atomic layers of the substrate under different applied gate voltages. The main structural observations were:more » (i) there were no structural changes when the voltage was negative, holes were injected into the film making it more metallic and screening the electric field; (ii) when the voltage was positive, the film was depleted of holes becoming more insulating, the electric field extended throughout the film, the partial surface monolayer became disordered, and planar oxygen atoms were displaced towards the sample surface; (iii) the changes in surface disorder and the oxygen displacements were both reversed when a negative voltage was applied; and (iv) the c-axis lattice constant of the film did not change in spite of the displacement of planar oxygen atoms.« less

Chemical gating of epitaxial graphene through ultrathin oxide layers.

PubMed

Larciprete, Rosanna; Lacovig, Paolo; Orlando, Fabrizio; Dalmiglio, Matteo; Omiciuolo, Luca; Baraldi, Alessandro; Lizzit, Silvano

2015-08-07

We achieved a controllable chemical gating of epitaxial graphene grown on metal substrates by exploiting the electrostatic polarization of ultrathin SiO2 layers synthesized below it. Intercalated oxygen diffusing through the SiO2 layer modifies the metal-oxide work function and hole dopes graphene. The graphene/oxide/metal heterostructure behaves as a gated plane capacitor with the in situ grown SiO2 layer acting as a homogeneous dielectric spacer, whose high capacity allows the Fermi level of graphene to be shifted by a few hundreds of meV when the oxygen coverage at the metal substrate is of the order of 0.5 monolayers. The hole doping can be finely tuned by controlling the amount of interfacial oxygen, as well as by adjusting the thickness of the oxide layer. After complete thermal desorption of oxygen the intrinsic doping of SiO2 supported graphene is evaluated in the absence of contaminants and adventitious adsorbates. The demonstration that the charge state of graphene can be changed by chemically modifying the buried oxide/metal interface hints at the possibility of tuning the level and sign of doping by the use of other intercalants capable of diffusing through the ultrathin porous dielectric and reach the interface with the metal.

Suppression of low-frequency charge noise in gates-defined GaAs quantum dots

DOE Office of Scientific and Technical Information (OSTI.GOV)

You, Jie; Li, Hai-Ou, E-mail: haiouli@ustc.edu.cn, E-mail: gpguo@ustc.edu.cn; Wang, Ke

To reduce the charge noise of a modulation-doped GaAs/AlGaAs quantum dot, we have fabricated shallow-etched GaAs/AlGaAs quantum dots using the wet-etching method to study the effects of two-dimensional electron gas (2DEG) underneath the metallic gates. The low-frequency 1/f noise in the Coulomb blockade region of the shallow-etched quantum dot is compared with a non-etched quantum dot on the same wafer. The average values of the gate noise are approximately 0.5 μeV in the shallow-etched quantum dot and 3 μeV in the regular quantum dot. Our results show the quantum dot low-frequency charge noise can be suppressed by the removal ofmore » the 2DEG underneath the metallic gates, which provides an architecture for noise reduction.« less

Logical regulation of the enzyme-like activity of gold nanoparticles by using heavy metal ions.

PubMed

Lien, Chia-Wen; Chen, Ying-Chieh; Chang, Huan-Tsung; Huang, Chih-Ching

2013-09-07

In this study we employed self-deposition and competitive or synergistic interactions between metal ions and gold nanoparticles (Au NPs) to develop OR, AND, INHIBIT, and XOR logic gates through regulation of the enzyme-like activity of Au NPs. In the presence of various metal ions (Ag(+), Bi(3+), Pb(2+), Pt(4+), and Hg(2+)), we found that Au NPs (13 nm) exhibited peroxidase-, oxidase-, or catalase-like activity. After Ag(+), Bi(3+), or Pb(2+) ions had been deposited on the Au NPs, the particles displayed strong peroxidase-like activity; on the other hand, they exhibited strong oxidase- and catalase-like activities after reactions with Ag(+)/Hg(2+) and Hg(2+)/Bi(3+) ions, respectively. The catalytic activities of these Au NPs arose mainly from the various oxidation states of the surface metal atoms/ions. Taking advantage of this behavior, we constructed multiplex logic operations-OR, AND, INHIBIT, and XOR logic gates-through regulation of the enzyme-like activity after the introduction of metal ions into the Au NP solution. When we deposited Hg(2+) and/or Bi(3+) ions onto the Au NPs, the catalase-like activities of the Au NPs were strongly enhanced (>100-fold). Therefore, we could construct an OR logic gate by using Hg(2+)/Bi(3+) as inputs and the catalase-like activity of the Au NPs as the output. Likewise, we constructed an AND logic gate by using Pt(4+) and Hg(2+) as inputs and the oxidase-like activity of the Au NPs as the output; the co-deposition of Pt and Hg atoms/ions on the Au NPs was responsible for this oxidase-like activity. Competition between Pb(2+) and Hg(2+) ions for the Au NPs allowed us to develop an INHIBIT logic gate-using Pb(2+) and Hg(2+) as inputs and the peroxidase-like activity of the Au NPs as the output. Finally, regulation of the peroxidase-like activity of the Au NPs through the two inputs Ag(+) and Bi(3+) enabled us to construct an XOR logic gate.

Side-gate modulation effects on high-quality BN-Graphene-BN nanoribbon capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Yang; Chen, Xiaolong; Ye, Weiguang

High-quality BN-Graphene-BN nanoribbon capacitors with double side-gates of graphene have been experimentally realized. The double side-gates can effectively modulate the electronic properties of graphene nanoribbon capacitors. By applying anti-symmetric side-gate voltages, we observed significant upward shifting and flattening of the V-shaped capacitance curve near the charge neutrality point. Symmetric side-gate voltages, however, only resulted in tilted upward shifting along the opposite direction of applied gate voltages. These modulation effects followed the behavior of graphene nanoribbons predicted theoretically for metallic side-gate modulation. The negative quantum capacitance phenomenon predicted by numerical simulations for graphene nanoribbons modulated by graphene side-gates was not observed,more » possibly due to the weakened interactions between the graphene nanoribbon and side-gate electrodes caused by the Ga{sup +} beam etching process.« less

Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

NASA Astrophysics Data System (ADS)

Wang, Yan-Rong; Yang, Hong; Xu, Hao; Wang, Xiao-Lei; Luo, Wei-Chun; Qi, Lu-Wei; Zhang, Shu-Xiang; Wang, Wen-Wu; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

2015-11-01

A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Hot-electron-induced hydrogen redistribution and defect generation in metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Buchanan, D. A.; Marwick, A. D.; Dimaria, D. J.; Dori, L.

1994-09-01

Redistribution of hydrogen caused by hot-electron injection has been studied by hydrogen depth profiling with N-15 nuclear reaction analysis and electrical methods. Internal photoemission and Fowler-Nordheim injection were used for electron injection into large Al-gate and polysilicon-gate capacitors, respectively. A hydrogen-rich layer (about 10(exp 15) atoms/sq cm) observed at the Al/SiO2 interface was found to serve as the source of hydrogen during the hot-electron stress. A small fraction of the hydrogen released from this layer was found to be retrapped near the Si/SiO2 interface for large electron fluences in the Al-gate samples. Within the limit of detectability, about 10(exp 14)/sq cm, no hydrogen was measured using nuclear reaction analysis in the polysilicon-gate samples. The buildup of hydrogen at the Si/SiO2 interface exhibits a threshold at about 1 MV/cm, consistent with the threshold for electron heating in SiO2. In the 'wet' SiO2 films with purposely introduced excess hydrogen, the rate of hydrogen buildup at the Si/SiO2 interface is found to be significantly greater than that found in the 'dry' films. During electron injection, hydrogen redistribution was also confirmed via the deactivation of boron dopant in the silicon substrate. The generation rates of interface states, neutral electron traps, and anomalous positive charge are found to increase with increasing hydrogen buildup in the substrate and the initial hydrogen concentration in the film. It is concluded that the generation of defects is preceded by the hot-electron-induced release and transport of atomic hydrogen and it is the chemical reaction of this species within the metal-oxide-semiconductor structure that generates the electrically active defects.

Interpreting Results from the Standardized UXO Test Sites

DTIC Science & Technology

2007-01-01

Detector Focusing Lens Cs Cell Split Polarizer Filter Collimating Lens Cs Lamp RF Coil Tiffany Mount H1 Coil Light rays Figure II-1. G-858 Cesium...conductive earth typically decay at a more rapid rate than the currents in metallic objects. Measurements are made in discrete “time gates,” or...time intervals, following the turnoff of the current pulse generated by the transmitter. The early time gates will detect both small and large metallic

Method for formation of thin film transistors on plastic substrates

DOEpatents

Carey, P.G.; Smith, P.M.; Sigmon, T.W.; Aceves, R.C.

1998-10-06

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics. 5 figs.

Single attosecond pulse generation by using plasmon-driven double optical gating technology in crossed metal nanostructures

NASA Astrophysics Data System (ADS)

Feng, Liqiang; Liu, Katheryn

2018-05-01

An effective method to obtain the single attosecond pulses (SAPs) by using the multi-cycle plasmon-driven double optical gating (DOG) technology in the specifically designed metal nanostructures has been proposed and investigated. It is found that with the introduction of the crossed metal nanostructures along the driven and the gating polarization directions, not only the harmonic cutoff can be extended, but also the efficient high-order harmonic generation (HHG) at the very highest orders occurs only at one side of the region inside the nanostructure. As a result, a 93 eV supercontinuum with the near stable phase can be found. Further, by properly introducing an ultraviolet (UV) pulse into the driven laser polarization direction (which is defined as the DOG), the harmonic yield can be enhanced by two orders of magnitude in comparison with the singe polarization gating (PG) technology. However, as the polarized angle or the ellipticity of the UV pulse increase, the enhancement of the harmonic yield is slightly reduced. Finally, by superposing the selected harmonics from the DOG scheme, a 30 as SAP with intensity enhancement of two orders of magnitude can be obtained.

Activating "Invisible" Glue: Using Electron Beam for Enhancement of Interfacial Properties of Graphene-Metal Contact.

PubMed

Kim, Songkil; Russell, Michael; Kulkarni, Dhaval D; Henry, Mathias; Kim, Steve; Naik, Rajesh R; Voevodin, Andrey A; Jang, Seung Soon; Tsukruk, Vladimir V; Fedorov, Andrei G

2016-01-26

Interfacial contact of two-dimensional graphene with three-dimensional metal electrodes is crucial to engineering high-performance graphene-based nanodevices with superior performance. Here, we report on the development of a rapid "nanowelding" method for enhancing properties of interface to graphene buried under metal electrodes using a focused electron beam induced deposition (FEBID). High energy electron irradiation activates two-dimensional graphene structure by generation of structural defects at the interface to metal contacts with subsequent strong bonding via FEBID of an atomically thin graphitic interlayer formed by low energy secondary electron-assisted dissociation of entrapped hydrocarbon contaminants. Comprehensive investigation is conducted to demonstrate formation of the FEBID graphitic interlayer and its impact on contact properties of graphene devices achieved via strong electromechanical coupling at graphene-metal interfaces. Reduction of the device electrical resistance by ∼50% at a Dirac point and by ∼30% at the gate voltage far from the Dirac point is obtained with concurrent improvement in thermomechanical reliability of the contact interface. Importantly, the process is rapid and has an excellent insertion potential into a conventional fabrication workflow of graphene-based nanodevices through single-step postprocessing modification of interfacial properties at the buried heterogeneous contact.

Effects of floating gate structures on the two-dimensional electron gas density and electron mobility in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhao, Jingtao; Zhao, Zhenguo; Chen, Zidong; Lin, Zhaojun; Xu, Fukai

2017-12-01

In this study, we have investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with floating gate structures using the measured capacitancevoltage (C-V) and current-voltage (I-V) characteristics. It is found that the two-dimensional electron gas (2DEG) density under the central gate cannot be changed by the floating gate structures. However, the floating gate structures can cause the strain variation in the barrier layer, which lead to the non-uniform distribution of the polarization charges, then induce a polarization Coulomb field and scatter the 2DEG. More floating gate structures and closer distance between the floating gates and the central gate will result in stronger scattering effect of the 2DEG.

Determination of work function of graphene under a metal electrode and its role in contact resistance.

PubMed

Song, Seung Min; Park, Jong Kyung; Sul, One Jae; Cho, Byung Jin

2012-08-08

Although the work function of graphene under a given metal electrode is critical information for the realization of high-performance graphene-based electronic devices, relatively little relevant research has been carried out to date. In this work, the work function values of graphene under various metals are accurately measured for the first time through a detailed analysis of the capacitance-voltage (C-V) characteristics of a metal-graphene-oxide-semiconductor (MGOS) capacitor structure. In contrast to the high work function of exposed graphene of 4.89-5.16 eV, the work function of graphene under a metal electrode varies depending on the metal species. With a Cr/Au or Ni contact, the work function of graphene is pinned to that of the contacted metal, whereas with a Pd or Au contact the work function assumes a value of ∼4.62 eV regardless of the work function of the contact metal. A study of the gate voltage dependence on the contact resistance shows that the latter case provides lower contact resistance.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

Catching the electron in action in real space inside a Ge-Si core-shell nanowire transistor.

PubMed

Jaishi, Meghnath; Pati, Ranjit

2017-09-21

Catching the electron in action in real space inside a semiconductor Ge-Si core-shell nanowire field effect transistor (FET), which has been demonstrated (J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, Nature, 2006, 441, 489) to outperform the state-of-the-art metal oxide semiconductor FET, is central to gaining unfathomable access into the origin of its functionality. Here, using a quantum transport approach that does not make any assumptions on electronic structure, charge, and potential profile of the device, we unravel the most probable tunneling pathway for electrons in a Ge-Si core-shell nanowire FET with orbital level spatial resolution, which demonstrates gate bias induced decoupling of electron transport between the core and the shell region. Our calculation yields excellent transistor characteristics as noticed in the experiment. Upon increasing the gate bias beyond a threshold value, we observe a rapid drop in drain current resulting in a gate bias driven negative differential resistance behavior and switching in the sign of trans-conductance. We attribute this anomalous behavior in drain current to the gate bias induced modification of the carrier transport pathway from the Ge core to the Si shell region of the nanowire channel. A new experiment involving a four probe junction is proposed to confirm our prediction on gate bias induced decoupling.

Visible-light-induced instability in amorphous metal-oxide based TFTs for transparent electronics

NASA Astrophysics Data System (ADS)

Ha, Tae-Jun

2014-10-01

We investigate the origin of visible-light-induced instability in amorphous metal-oxide based thin film transistors (oxide-TFTs) for transparent electronics by exploring the shift in threshold voltage (Vth). A large hysteresis window in amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs possessing large optical band-gap (≈3 eV) was observed in a visible-light illuminated condition whereas no hysteresis window was shown in a dark measuring condition. We also report the instability caused by photo irradiation and prolonged gate bias stress in oxide-TFTs. Larger Vth shift was observed after photo-induced stress combined with a negative gate bias than the sum of that after only illumination stress and only negative gate bias stress. Such results can be explained by trapped charges at the interface of semiconductor/dielectric and/or in the gate dielectric which play a role in a screen effect on the electric field applied by gate voltage, for which we propose that the localized-states-assisted transitions by visible-light absorption can be responsible.

Lithographically defined few-electron silicon quantum dots based on a silicon-on-insulator substrate

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horibe, Kosuke; Oda, Shunri; Kodera, Tetsuo, E-mail: kodera.t.ac@m.titech.ac.jp

2015-02-23

Silicon quantum dot (QD) devices with a proximal single-electron transistor (SET) charge sensor have been fabricated in a metal-oxide-semiconductor structure based on a silicon-on-insulator substrate. The charge state of the QDs was clearly read out using the charge sensor via the SET current. The lithographically defined small QDs enabled clear observation of the few-electron regime of a single QD and a double QD by charge sensing. Tunnel coupling on tunnel barriers of the QDs can be controlled by tuning the top-gate voltages, which can be used for manipulation of the spin quantum bit via exchange interaction between tunnel-coupled QDs. Themore » lithographically defined silicon QD device reported here is technologically simple and does not require electrical gates to create QD confinement potentials, which is advantageous for the integration of complicated constructs such as multiple QD structures with SET charge sensors for the purpose of spin-based quantum computing.« less

Ambipolar Barristors for Reconfigurable Logic Circuits.

PubMed

Liu, Yuan; Zhang, Guo; Zhou, Hailong; Li, Zheng; Cheng, Rui; Xu, Yang; Gambin, Vincent; Huang, Yu; Duan, Xiangfeng

2017-03-08

Vertical heterostructures based on graphene have emerged as a unique architecture for novel electronic devices with unusual characteristics. Here we report a new design of vertical ambipolar barristors based on metal-graphene-silicon-graphene sandwich structure, using the bottom graphene as a gate-tunable "active contact", the top graphene as an adaptable Ohmic contact, and the low doping thin silicon layer as the switchable channel. Importantly, with finite density of states and weak screening effect of graphene, we demonstrate, for the first time, that both the carrier concentration and majority carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar barristors with an ON-OFF ratio exceeding 10 3 . Significantly, these ambipolar barristors can be flexibly configured into either p-type or n-type transistors and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable characteristics can open up exciting opportunities in future electronics based on graphene or two-dimensional van der Waals heterostructures.

Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

NASA Astrophysics Data System (ADS)

Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

2015-06-01

High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

High-contrast terahertz wave modulation by gated graphene enhanced by extraordinary transmission through ring apertures.

PubMed

Gao, Weilu; Shu, Jie; Reichel, Kimberly; Nickel, Daniel V; He, Xiaowei; Shi, Gang; Vajtai, Robert; Ajayan, Pulickel M; Kono, Junichiro; Mittleman, Daniel M; Xu, Qianfan

2014-03-12

Gate-controllable transmission of terahertz (THz) radiation makes graphene a promising material for making high-speed THz wave modulators. However, to date, graphene-based THz modulators have exhibited only small on/off ratios due to small THz absorption in single-layer graphene. Here we demonstrate a ∼50% amplitude modulation of THz waves with gated single-layer graphene by the use of extraordinary transmission through metallic ring apertures placed right above the graphene layer. The extraordinary transmission induced ∼7 times near-filed enhancement of THz absorption in graphene. These results promise complementary metal-oxide-semiconductor compatible THz modulators with tailored operation frequencies, large on/off ratios, and high speeds, ideal for applications in THz communications, imaging, and sensing.

Microwave properties of peeled HEMT devices sapphire substrates

NASA Technical Reports Server (NTRS)

Young, Paul G.; Alterovitz, Samuel A.; Mena, Rafael A.; Smith, Edwyn D.

1992-01-01

The focus of this research is to demonstrate the first full radio frequency characterization of high electron mobility transistor (HEMT) device parameters. The results of this research are used in the design of circuits with peeled HEMT devices, e.g. 10 GHz amplifiers. Devices were fabricated using two HEMT structures grown by molecular beam epitaxy methods. A 500 A AlAs release layer for 'peel off' was included under the active layers of the structure. The structures are a homogeneously doped Al(0.3)GA(0.7)As/GaAs and a delta doped square well Al(.23)Ga(.77)As/GaAs HEMT structure. Devices were fabricated using a mesa isolation process. Contacts were done by sequentially evaporating Au/Ge/Au/Ni/Au followed by rapid thermal anneal at 400 C for 15 seconds. Gates were wet etch recessed and 1 to 1.4 micron Ti/Au gate metal was deposited. Devices were peeled off the GaAs substrate using Apiezon wax to support the active layer and a HF:DI (1:10) solution to remove the AlAs separation layer. Devices were then attached to sapphire substrates using van der Waals bonding.

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

NASA Technical Reports Server (NTRS)

Tabory, Charles N.; Young, Paul G.; Smith, Edwyn D.; Alterovitz, Samuel A.

1994-01-01

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

A static induction device manufactured by silicon direct bonding

NASA Astrophysics Data System (ADS)

Chen, Xin'an; Liu, Su; Huang, Qing'an

2004-07-01

It is always a key problem how to improve the gate-source breakdown voltage (VGK) of static induction devices during manufacturing. By using a silicon direct bonding process to replace the high resistivity epitaxy process, a bonding buried gate structure is formed, which is different from an epitaxy buried gate structure. The new structure can improve the gate-source breakdown voltage from the process and the structure. It is shown that the bonding buried gate structure is a promising structure, that can improve the VGK and other performances of devices, by manufacture of a static induction thyristor.

High Speed FETs Fabricated in GaAs/AlGaAs Layered Structures Prepared by Molecular Beam Epitaxy.

DTIC Science & Technology

1984-01-01

but proper measures, such as improved ohmic con - tacts, metal conductors and small geometrics are useful. In digital circuit applications in addition to...heterointerface encounter reduced scattering by ionized donors located in AlGaAs layer, the current con - ducting channel must be parallel to the...ments apply to the velocity saturated MOSFET as well. For the MESFET, in con - trast, the transconductance increases with increasing gate biases, since

Local gate control in carbon nanotube quantum devices

NASA Astrophysics Data System (ADS)

Biercuk, Michael Jordan

This thesis presents transport measurements of carbon nanotube electronic devices operated in the quantum regime. Nanotubes are contacted by source and drain electrodes, and multiple lithographically-patterned electrostatic gates are aligned to each device. Transport measurements of device conductance or current as a function of local gate voltages reveal that local gates couple primarily to the proximal section of the nanotube, hence providing spatially localized control over carrier density along the nanotube length. Further, using several different techniques we are able to produce local depletion regions along the length of a tube. This phenomenon is explored in detail for different contact metals to the nanotube. We utilize local gating techniques to study multiple quantum dots in carbon nanotubes produced both by naturally occurring defects, and by the controlled application of voltages to depletion gates. We study double quantum dots in detail, where transport measurements reveal honeycomb charge stability diagrams. We extract values of energy-level spacings, capacitances, and interaction energies for this system, and demonstrate independent control over all relevant tunneling rates. We report rf-reflectometry measurements of gate-defined carbon nanotube quantum dots with integrated charge sensors. Aluminum rf-SETs are electrostatically coupled to carbon nanotube devices and detect single electron charging phenomena in the Coulomb blockade regime. Simultaneous correlated measurements of single electron charging are made using reflected rf power from the nanotube itself and from the rf-SET on microsecond time scales. We map charge stability diagrams for the nanotube quantum dot via charge sensing, observing Coulomb charging diamonds beyond the first order. Conductance measurements of carbon nanotubes containing gated local depletion regions exhibit plateaus as a function of gate voltage, spaced by approximately 1e2/h, the quantum of conductance for a single (non-degenerate) mode. Plateau structure is investigated as a function of bias voltage, temperature, and magnetic field. We speculate on the origin of this surprising quantization, which appears to lack band and spin degeneracy.

On the physical operation and optimization of the p-GaN gate in normally-off GaN HEMT devices

NASA Astrophysics Data System (ADS)

Efthymiou, L.; Longobardi, G.; Camuso, G.; Chien, T.; Chen, M.; Udrea, F.

2017-03-01

In this study, an investigation is undertaken to determine the effect of gate design parameters on the on-state characteristics (threshold voltage and gate turn-on voltage) of pGaN/AlGaN/GaN high electron mobility transistors (HEMTs). Design parameters considered are pGaN doping and gate metal work function. The analysis considers the effects of variations on these parameters using a TCAD model matched with experimental results. A better understanding of the underlying physics governing the operation of these devices is achieved with a view to enable better optimization of such gate designs.

Quantum design rules for single molecule logic gates.

PubMed

Renaud, N; Hliwa, M; Joachim, C

2011-08-28

Recent publications have demonstrated how to implement a NOR logic gate with a single molecule using its interaction with two surface atoms as logical inputs [W. Soe et al., ACS Nano, 2011, 5, 1436]. We demonstrate here how this NOR logic gate belongs to the general family of quantum logic gates where the Boolean truth table results from a full control of the quantum trajectory of the electron transfer process through the molecule by very local and classical inputs practiced on the molecule. A new molecule OR gate is proposed for the logical inputs to be also single metal atoms, one per logical input.

Effect of Al-diffusion-induced positive flatband voltage shift on the electrical characteristics of Al-incorporated high-k metal-oxide-semiconductor field-effective transistor

NASA Astrophysics Data System (ADS)

Wang, Wenwu; Akiyama, Koji; Mizubayashi, Wataru; Nabatame, Toshihide; Ota, Hiroyuki; Toriumi, Akira

2009-03-01

We systematically studied what effect Al diffusion from high-k dielectrics had on the flatband voltage (Vfb) of Al-incorporated high-k gate stacks. An anomalous positive shift fin Vfb with the decreasing equivalent oxide thickness (EOT) of high-k gate stacks is reported. As the SiO2 interfacial layer is aggressively thinned in Al-incorporated HfxAl1-xOy gate stacks with a metal-gate electrode, the Vfb first lies on the well known linear Vfb-EOT plot and deviates toward the positive-voltage direction (Vfb roll-up), followed by shifting toward negative voltage (Vfb roll-off). We demonstrated that the Vfb roll-up behavior remarkably decreases the threshold voltage (Vth) of p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs), and does not cause severe degradation in the characteristics of hole mobility. The Vfb roll-up behavior, which is independent of gate materials but strongly dependent on high-k dielectrics, was ascribed to variations in fixed charges near the SiO2/Si interface, which are caused by Al diffusion from HfxAl1-xOy through SiO2 to the SiO2/Si interface. These results indicate that anomalous positive shift in Vfb, i.e., Vfb roll-up, should be taken into consideration in quantitatively adjusting Vfb in thin EOT regions and that it could be used to further tune Vth in p-MOSFETs.

Surface and Interface Chemistry for Gate Stacks on Silicon

NASA Astrophysics Data System (ADS)

Frank, M. M.; Chabal, Y. J.

This chapter addresses the fundamental silicon surface science associated with the continued progress of nanoelectronics along the path prescribed by Moore's law. Focus is on hydrogen passivation layers and on ultrathin oxide films encountered during silicon cleaning and gate stack formation in the fabrication of metal-oxide-semiconductor field-effect transistors (MOSFETs). Three main topics are addressed. (i) First, the current practices and understanding of silicon cleaning in aqueous solutions are reviewed, including oxidizing chemistries and cleans leading to a hydrogen passivation layer. The dependence of the final surface termination and morphology/roughness on reactant choice and pH and the influence of impurities such as dissolved oxygen or metal ions are discussed. (ii) Next, the stability of hydrogen-terminated silicon in oxidizing liquid and gas phase environments is considered. In particular, the remarkable stability of hydrogen-terminated silicon surface in pure water vapor is discussed in the context of atomic layer deposition (ALD) of high-permittivity (high-k) gate dielectrics where water is often used as an oxygen precursor. Evidence is also provided for co-operative action between oxygen and water vapor that accelerates surface oxidation in humid air. (iii) Finally, the fabrication of hafnium-, zirconium- and aluminum-based high-k gate stacks is described, focusing on the continued importance of the silicon/silicon oxide interface. This includes a review of silicon surface preparation by wet or gas phase processing and its impact on high-k nucleation during ALD growth, and the consideration of gate stack capacitance and carrier mobility. In conclusion, two issues are highlighted: the impact of oxygen vacancies on the electrical characteristics of high-k MOS devices, and the way alloyed metal ions (such as Al in Hf-based gate stacks) in contact with the interfacial silicon oxide layer can be used to control flatband and threshold voltages.

TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

NASA Astrophysics Data System (ADS)

Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

2018-04-01

Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

Synthesis and Characterization of the 2-Dimensional Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Browning, Robert

In the last 50 years, the semiconductor industry has been scaling the silicon transistor to achieve faster devices, lower power consumption, and improve device performance. Transistor gate dimensions have become so small that short channel effects and gate leakage have become a significant problem. To address these issues, performance enhancement techniques such as strained silicon are used to improve mobility, while new high-k gate dielectric materials replace silicon oxide to reduce gate leakage. At some point the fundamental limit of silicon will be reached and the semiconductor industry will need to find an alternate solution. The advent of graphene led to the discovery of other layered materials such as the transition metal dichalcogenides. These materials have a layered structure similar to graphene and therefore possess some of the same qualities, but unlike graphene, these materials possess sizeable bandgaps between 1-2 eV making them useful for digital electronic applications. Since initially discovered, most of the research on these films has been from mechanically exfoliated flakes, which are easily produced due to the weak van der Waals force binding the layers together. For these materials to be considered for use in mainstream semiconductor technology, methods need to be explored to grow these films uniformly over a large area. In this research, atomic layer deposition (ALD) was employed as the growth technique used to produce large area uniform thin films of several different transition metal dichalcogenides. By optimizing the ALD growth parameters, it is possible to grow high quality films a few to several monolayers thick over a large area with good uniformity. This has been demonstrated and verified using several physical analytical tests such as Raman spectroscopy, photoluminescence, x-ray photoelectron spectroscopy, x-ray diffraction, transmission electron spectroscopy, and scanning electron microscopy, which show that these films possess the same qualities as those of the mechanically exfoliated films. Back-gated field effect transistors were created and electrical characterization was performed to determine if ALD grown films possess the same electronic properties as films produced from other methods. The tests revealed that the ALD grown films have high field effect mobility and high current on/off ratios. The WSe2 films also exhibited ambipolar electrical behavior making them a possible candidate for complementary metal-oxide semiconductor (CMOS) technology. Ab-initio density functional theory calculations were performed and compared to experimental properties of MoS2 and WSe2 films, which show that the ALD films grown in this research match theoretical predictions. The transconductance measurements from the WSe2 devices used, matched very well with the theoretical calculations, bridging the gap between experimental data and theoretical predictions. Based upon this research, ALD growth of TMD films proves to be a viable alternative for silicon based digital electronics.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-01

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

PubMed

Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

2015-12-17

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Zinc as Allosteric Ion Channel Modulator: Ionotropic Receptors as Metalloproteins.

PubMed

Peralta, Francisco Andrés; Huidobro-Toro, Juan Pablo

2016-07-02

Zinc is an essential metal to life. This transition metal is a structural component of many proteins and is actively involved in the catalytic activity of cell enzymes. In either case, these zinc-containing proteins are metalloproteins. However, the amino acid residues that serve as ligands for metal coordination are not necessarily the same in structural proteins compared to enzymes. While crystals of structural proteins that bind zinc reveal a higher preference for cysteine sulfhydryls rather than histidine imidazole rings, catalytic enzymes reveal the opposite, i.e., a greater preference for the histidines over cysteines for catalysis, plus the influence of carboxylic acids. Based on this paradigm, we reviewed the putative ligands of zinc in ionotropic receptors, where zinc has been described as an allosteric modulator of channel receptors. Although these receptors do not strictly qualify as metalloproteins since they do not normally bind zinc in structural domains, they do transitorily bind zinc at allosteric sites, modifying transiently the receptor channel's ion permeability. The present contribution summarizes current information showing that zinc allosteric modulation of receptor channels occurs by the preferential metal coordination to imidazole rings as well as to the sulfhydryl groups of cysteine in addition to the carboxyl group of acid residues, as with enzymes and catalysis. It is remarkable that most channels, either voltage-sensitive or transmitter-gated receptor channels, are susceptible to zinc modulation either as positive or negative regulators.

Zinc as Allosteric Ion Channel Modulator: Ionotropic Receptors as Metalloproteins

PubMed Central

Peralta, Francisco Andrés; Huidobro-Toro, Juan Pablo

2016-01-01

Zinc is an essential metal to life. This transition metal is a structural component of many proteins and is actively involved in the catalytic activity of cell enzymes. In either case, these zinc-containing proteins are metalloproteins. However, the amino acid residues that serve as ligands for metal coordination are not necessarily the same in structural proteins compared to enzymes. While crystals of structural proteins that bind zinc reveal a higher preference for cysteine sulfhydryls rather than histidine imidazole rings, catalytic enzymes reveal the opposite, i.e., a greater preference for the histidines over cysteines for catalysis, plus the influence of carboxylic acids. Based on this paradigm, we reviewed the putative ligands of zinc in ionotropic receptors, where zinc has been described as an allosteric modulator of channel receptors. Although these receptors do not strictly qualify as metalloproteins since they do not normally bind zinc in structural domains, they do transitorily bind zinc at allosteric sites, modifying transiently the receptor channel’s ion permeability. The present contribution summarizes current information showing that zinc allosteric modulation of receptor channels occurs by the preferential metal coordination to imidazole rings as well as to the sulfhydryl groups of cysteine in addition to the carboxyl group of acid residues, as with enzymes and catalysis. It is remarkable that most channels, either voltage-sensitive or transmitter-gated receptor channels, are susceptible to zinc modulation either as positive or negative regulators. PMID:27384555

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

NASA Astrophysics Data System (ADS)

Martin, Dominik; Yurchuk, Ekaterina; Müller, Stefan; Müller, Johannes; Paul, Jan; Sundquist, Jonas; Slesazeck, Stefan; Schlösser, Till; van Bentum, Ralf; Trentzsch, Martin; Schröder, Uwe; Mikolajick, Thomas

2013-10-01

Throughout the 22 nm technology node HfO2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[ZrxTi1-x]O3 and SrBi2Ta2O9. However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

PRB CHEMISTRY CASE STUDY: DENVER FEDERAL CENTER

EPA Science Inventory

The Denver Federal Center permeable reactive barrier is a funnel-and-gate system with four reactive gates, each separated by up to about 120 m of metal sheet pile. In this study, ground water sampling, core collection, and solid phase characterization studies were carried out in...

Gate tunable parallel double quantum dots in InAs double-nanowire devices

NASA Astrophysics Data System (ADS)

Baba, S.; Matsuo, S.; Kamata, H.; Deacon, R. S.; Oiwa, A.; Li, K.; Jeppesen, S.; Samuelson, L.; Xu, H. Q.; Tarucha, S.

2017-12-01

We report fabrication and characterization of InAs nanowire devices with two closely placed parallel nanowires. The fabrication process we develop includes selective deposition of the nanowires with micron scale alignment onto predefined finger bottom gates using a polymer transfer technique. By tuning the double nanowire with the finger bottom gates, we observed the formation of parallel double quantum dots with one quantum dot in each nanowire bound by the normal metal contact edges. We report the gate tunability of the charge states in individual dots as well as the inter-dot electrostatic coupling. In addition, we fabricate a device with separate normal metal contacts and a common superconducting contact to the two parallel wires and confirm the dot formation in each wire from comparison of the transport properties and a superconducting proximity gap feature for the respective wires. With the fabrication techniques established in this study, devices can be realized for more advanced experiments on Cooper-pair splitting, generation of Parafermions, and so on.

Terahertz modulation based on surface plasmon resonance by self-gated graphene

NASA Astrophysics Data System (ADS)

Qian, Zhenhai; Yang, Dongxiao; Wang, Wei

2018-05-01

We theoretically and numerically investigate the extraordinary optical transmission through a terahertz metamaterial composed of metallic ring aperture arrays. The physical mechanism of different transmission peaks is elucidated to be magnetic polaritons or propagation surface plasmons with the help of surface current and electromagnetic field distributions at respective resonance frequencies. Then, we propose a high performance terahertz modulator based on the unique PSP resonance and combined with the metallic ring aperture arrays and a self-gated parallel-plate graphene capacitor. Because, to date, few researches have exhibited gate-controlled graphene modulation in terahertz region with low insertion losses, high modulation depth and low control voltage at room temperature. Here, we propose a 96% amplitude modulation with 0.7 dB insertion losses and ∼5.5 V gate voltage. Besides, we further study the absorption spectra of the modulator. When the transmission of modulator is very low, a 91% absorption can be achieved for avoiding damaging the source devices.

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Reliability investigation of high-k/metal gate in nMOSFETs by three-dimensional kinetic Monte-Carlo simulation with multiple trap interactions

NASA Astrophysics Data System (ADS)

Li, Yun; Jiang, Hai; Lun, Zhiyuan; Wang, Yijiao; Huang, Peng; Hao, Hao; Du, Gang; Zhang, Xing; Liu, Xiaoyan

2016-04-01

Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

Nanocharacterization Challenges in a Changing Microelectronics Landscape

NASA Astrophysics Data System (ADS)

Brilloüt, Michel

2011-11-01

As the microelectronics industry enters the "nano"-era new challenges emerge. Traditional scaling of the MOS transistor faces major obstacles in fulfilling "Moore's law". New features like strain and new materials (e.g. high k—metal gate stack) are introduced in order to sustain performance increases. For a better electrostatic control, devices will use the third dimension, e.g., in gate-all-around nanowire structures. Due to the escalating cost and complexity of sub-28 nm technologies fewer industrial players can afford the development and production of advanced CMOS processes and many companies acknowledge the fact that the value in products can also be obtained in using more diversified non-digital technologies (the so-called "More-than-Moore" domain). This evolving landscape brings new requirements—discussed in this paper—in terms of physical characterization of technologies and devices.

Examination of the high-frequency capability of carbon nanotube FETs

NASA Astrophysics Data System (ADS)

Pulfrey, David L.; Chen, Li

2008-09-01

New results are added to a recent critique of the high-frequency performance of carbon nanotube field-effect transistors (CNFETs). On the practical side, reduction of the number of metallic tubes in CNFETs fashioned from multiple nanotubes has allowed the measured fT to be increased to 30 GHz. On the theoretical side, the opinion that the band-structure-determined velocity limits the high-frequency performance has been reinforced by corrections to recent simulation results for doped-contact CNFETs, and by the ruling out of the possibility of favourable image-charge effects. Inclusion in the simulations of the features of finite gate-metal thickness and source/drain contact resistance has given an indication of likely practical values for fT. A meaningful comparison between CNFETs with doped-contacts and metallic contacts has been made.

Gate-Tunable Electron Transport Phenomena in Al-Ge⟨111⟩-Al Nanowire Heterostructures.

PubMed

Brunbauer, Florian M; Bertagnolli, Emmerich; Lugstein, Alois

2015-11-11

Electrostatically tunable negative differential resistance (NDR) is demonstrated in monolithic metal-semiconductor-metal (Al-Ge-Al) nanowire (NW) heterostructures integrated in back-gated field-effect transistors (FETs). Unambiguous signatures of NDR even at room temperature are attributed to intervalley electron transfer. At yet higher electric fields, impact ionization leads to an exponential increase of the current in the ⟨111⟩ oriented Ge NW segments. Modulation of the transfer rates, manifested as a large tunability of the peak-to-valley ratio (PVR) and the onset of impact ionization is achieved by the combined influences of electrostatic gating, geometric confinement, and heterojunction shape on hot electron transfer and by electron-electron scattering rates that can be altered by varying the charge carrier concentration in the NW FETs.

Multilayer ZnO/Pd/ZnO Structure as Sensing Membrane for Extended-Gate Field-Effect Transistor (EGFET) with High pH Sensitivity

NASA Astrophysics Data System (ADS)

Rasheed, Hiba S.; Ahmed, Naser M.; Matjafri, M. Z.; Al-Hardan, Naif H.; Almessiere, Munirah Abdullah; Sabah, Fayroz A.; Al-Hazeem, Nabeel Z.

2017-10-01

Metal oxide nanostructures have attracted considerable attention as pH-sensitive membranes because of their unique advantages. Specifically, the special properties of ZnO thin film, including high surface-to-volume ratio, nontoxicity, thermal stability, chemical stability, electrochemical activity, and high mechanical strength, have attracted massive interest. ZnO exhibits wide bandgap of 3.37 eV, good biocompatibility, high reactivity, robustness, and environmental stability. These unique properties explain why ZnO has the most applications among all nanostructured metal oxides based on its structure and properties. Moreover, ZnO has excellent electrical characteristics, enabling its use in accurate sensors with rapid response. ZnO nanostructures can be used in novel pH and biomedical sensing applications. However, ZnO thin film exhibits large sheet resistance and low conductivity. Increasing the conductivity or reducing the resistivity of ZnO sensing membranes is important to achieve low impedance. We propose herein a new design using a multilayer ZnO/Pd/ZnO structure as a pH-sensing membrane. Multiple layers were deposited by radio frequency (RF) sputtering for ZnO and direct current (DC) sputtering for Pd to achieve low sheet resistance. These multilayers with low sheet resistance of 15.8 Ω/sq were then successfully used to control the conductivity in extended-gate field-effect transistors (EGFETs). The resulting multilayered EGFET pH-sensor demonstrated improved sensing performance. The measured sensitivity of the pH sensor was 40 μA/pH and 52 mV/pH within the pH range from 2 to 12, rendering this structure suitable for use in various applications, including pH sensors and biosensors.

Proton Irradiation-Induced Metal Voids in Gallium Nitride High Electron Mobility Transistors

DTIC Science & Technology

2015-09-01

13. ABSTRACT (maximum 200 words) Gallium nitride/aluminum gallium nitride high electron mobility transistors with nickel/ gold (Ni/Au) and...platinum/ gold (Pt/Au) gating are irradiated with 2 MeV protons. Destructive physical analysis revealed material voids underneath the gate finger of the...nickel/ gold (Ni/Au) and platinum/ gold (Pt/Au) gating are irradiated with 2 MeV protons. Destructive physical analysis revealed material voids underneath

Voltage-Boosting Driver For Switching Regulator

NASA Technical Reports Server (NTRS)

Trump, Ronald C.

1990-01-01

Driver circuit assures availability of 10- to 15-V gate-to-source voltage needed to turn on n-channel metal oxide/semiconductor field-effect transistor (MOSFET) acting as switch in switching voltage regulator. Includes voltage-boosting circuit efficiently providing gate voltage 10 to 15 V above supply voltage. Contains no exotic parts and does not require additional power supply. Consists of NAND gate and dual voltage booster operating in conjunction with pulse-width modulator part of regulator.

High-sensitivity assay for Hg (II) and Ag (I) ion detection: A new class of droplet digital PCR logic gates for an intelligent DNA calculator.

PubMed

Cheng, Nan; Zhu, Pengyu; Xu, Yuancong; Huang, Kunlun; Luo, Yunbo; Yang, Zhansen; Xu, Wentao

2016-10-15

The first example of droplet digital PCR logic gates ("YES", "OR" and "AND") for Hg (II) and Ag (I) ion detection has been constructed based on two amplification events triggered by a metal-ion-mediated base mispairing (T-Hg(II)-T and C-Ag(I)-C). In this work, Hg(II) and Ag(I) were used as the input, and the "true" hierarchical colors or "false" green were the output. Through accurate molecular recognition and high sensitivity amplification, positive droplets were generated by droplet digital PCR and viewed as the basis of hierarchical digital signals. Based on this principle, YES gate for Hg(II) (or Ag(I)) detection, OR gate for Hg(II) or Ag(I) detection and AND gate for Hg(II) and Ag(I) detection were developed, and their sensitively and selectivity were reported. The results indicate that the ddPCR logic system developed based on the different indicators for Hg(II) and Ag(I) ions provides a useful strategy for developing advanced detection methods, which are promising for multiplex metal ion analysis and intelligent DNA calculator design applications. Copyright © 2016 Elsevier B.V. All rights reserved.

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

Graphene field-effect devices

NASA Astrophysics Data System (ADS)

Echtermeyer, T. J.; Lemme, M. C.; Bolten, J.; Baus, M.; Ramsteiner, M.; Kurz, H.

2007-09-01

In this article, graphene is investigated with respect to its electronic properties when introduced into field effect devices (FED). With the exception of manual graphene deposition, conventional top-down CMOS-compatible processes are applied. Few and monolayer graphene sheets are characterized by scanning electron microscopy, atomic force microscopy and Raman spectroscopy. The electrical properties of monolayer graphene sandwiched between two silicon dioxide films are studied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from double-gated Graphene-FEDs and silicon metal-oxide-semiconductor field-effect-transistors (MOSFETs).

Large-Scale Precise Printing of Ultrathin Sol-Gel Oxide Dielectrics for Directly Patterned Solution-Processed Metal Oxide Transistor Arrays.

PubMed

Lee, Won-June; Park, Won-Tae; Park, Sungjun; Sung, Sujin; Noh, Yong-Young; Yoon, Myung-Han

2015-09-09

Ultrathin and dense metal oxide gate di-electric layers are reported by a simple printing of AlOx and HfOx sol-gel precursors. Large-area printed indium gallium zinc oxide (IGZO) thin-film transistor arrays, which exhibit mobilities >5 cm(2) V(-1) s(-1) and gate leakage current of 10(-9) A cm(-2) at a very low operation voltage of 2 V, are demonstrated by continuous simple bar-coated processes. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Effect of Si-doping on InAs nanowire transport and morphology

NASA Astrophysics Data System (ADS)

Wirths, S.; Weis, K.; Winden, A.; Sladek, K.; Volk, C.; Alagha, S.; Weirich, T. E.; von der Ahe, M.; Hardtdegen, H.; Lüth, H.; Demarina, N.; Grützmacher, D.; Schäpers, Th.

2011-09-01

The effect of Si-doping on the morphology, structure, and transport properties of nanowires was investigated. The nanowires were deposited by selective-area metal organic vapor phase epitaxy in an N2 ambient. It is observed that doping systematically affects the nanowire morphology but not the structure of the nanowires. However, the transport properties of the wires are greatly affected. Room-temperature four-terminal measurements show that with an increasing dopant supply the conductivity monotonously increases. For the highest doping level the conductivity is higher by a factor of 25 compared to only intrinsically doped reference nanowires. By means of back-gate field-effect transistor measurements it was confirmed that the doping results in an increased carrier concentration. Temperature dependent resistance measurements reveal, for lower doping concentrations, a thermally activated semiconductor-type increase of the conductivity. In contrast, the nanowires with the highest doping concentration show a metal-type decrease of the resistivity with decreasing temperature.

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Nanocrystals embedded in hafnium dioxide-based dielectrics as charge storage nodes of nano-floating gate memory

NASA Astrophysics Data System (ADS)

Lee, Pui Fai

2007-12-01

Nanocrystals (NC) embedded in dielectrics have attracted a great deal of attention recently because they can potentially be applied in nonvolatile, high-speed, high-density and low-power memory devices. This device benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors. The nanocrystal materials suitable for such an application can be either metals or semiconductors. Recent studies have shown that high-k dielectrics, instead of SiO2 , for the tunneling layer in nanocrystal floating gate memory can improve the trade-off between data retention and program efficiency due to the unique band alignment of high-k dielectrics in the programming and retention modes. In this project, HfAlO has been selected as the high- k dielectric for the nanocrystal floating gate memory structure. The trilayer structure (HfAlO/Ge-NC/HfAlO) on Si was fabricated by PLD. Results revealed that relatively low substrate temperature and growth rate are favourable for the formation of smaller-size Ge nanocrystals. Effects of size/density of the Ge nanocrystal, the tunneling and control oxide layer thicknesses and the oxygen partial pressure during their growth on the charge storage and charge retention characteristics have also been studied. The island structure of the Ge nanocrystal suggests that the growth is based on the Volmer-Webber mode. The self-organized Ge nanocrystals so formed were uniform in size (5--20 nm diameter) and distribution with a density approaching 1012--1013cm-2. Flat-band voltage shift (DeltaVFB) of about 3.6 V and good retention property have been achieved. By varying aggregation distance, sputtering gas pressure and ionization power of the nanocluster source, nanoclusters of Ge with different sizes can be formed. The memory effect of the trilayer structure so formed with 10 nm Ge nanoclusters are manifested by the counter-clockwise hysteresis loop in the C-V curves and a maximum flat-band voltage shift of 5.0 V has been achieved. For comparison purposes, metal nanocrystals have also been investigated by utilizing both of the physical deposition methods as mentioned above. Silver (Ag) nanocrystals with size of 10--40 nm have been embedded in HfAlO matrix in the trilayer capacitor structure and a flat-band voltage shift of 2.0 V has been achieved.

Spin transport in lateral structures with semiconducting channel

NASA Astrophysics Data System (ADS)

Zainuddin, Abu Naser

Spintronics is an emerging field of electronics with the potential to be used in future integrated circuits. Spintronic devices are already making their mark in storage technologies in recent times and there are proposals for using spintronic effects in logic technologies as well. So far, major improvement in spintronic effects, for example, the `spin-valve' effect, is being achieved in metals or insulators as channel materials. But not much progress is made in semiconductors owing to the difficulty in injecting spins into them, which has only very recently been overcome with the combined efforts of many research groups around the world. The key motivations for semiconductor spintronics are their ease in integration with the existing semiconductor technology along with the gate controllability. At present semiconductor based spintronic devices are mostly lateral and are showing a very poor performance compared to their metal or insulator based vertical counterparts. The objective of this thesis is to analyze these devices based on spin-transport models and simulations. At first a lateral spin-valve device is modeled with the spin-diffusion equation based semiclassical approach. Identifying the important issues regarding the device performance, a compact circuit equivalent model is presented which would help to improve the device design. It is found that the regions outside the current path also have a significant influence on the device performance under certain conditions, which is ordinarily neglected when only charge transport is considered. Next, a modified spin-valve structure is studied where the spin signal is controlled with a gate in between the injecting and detecting contacts. The gate is used to modulate the rashba spin-orbit coupling of the channel which, in turn, modulates the spin-valve signal. The idea of gate controlled spin manipulation was originally proposed by Datta and Das back in 1990 and is called 'Datta-Das' effect. In this thesis, we have extended the model described in the original proposal to include the influence of channel dimensions on the nature of electron flow and the contact dimensions on the magnitude and phase of the spin-valve signal. In order to capture the spin-orbit effect a non-equilibrium Green's function (NEGF) based quantum transport model for spin-valve device have been developed which is also explained with simple theoretical treatment based on stationary phase approximation. The model is also compared against a recent experiment that demonstrated such gate modulated spin-valve effect. This thesis also evaluates the possibility of gate controlled magnetization reversal or spin-torque effect as a means to validate this, so called, 'Datta-Das' effect on a more solid footing. Finally, the scope for utilizing topological insulator material in semiconductor spintronics is discussed as a possible future work for this thesis.

Metal-like transport in proteins: A new paradigm for biological electron transfer

NASA Astrophysics Data System (ADS)

Malvankar, Nikhil; Vargas, Madeline; Tuominen, Mark; Lovley, Derek

2012-02-01

Electron flow in biologically proteins generally occurs via tunneling or hopping and the possibility of electron delocalization has long been discounted. Here we report metal-like transport in protein nanofilaments, pili, of bacteria Geobacter sulfurreducens that challenges this long-standing belief [1]. Pili exhibit conductivities comparable to synthetic organic metallic nanostructures. The temperature, magnetic field and gate-voltage dependence of pili conductivity is akin to that of quasi-1D disordered metals, suggesting a metal-insulator transition. Magnetoresistance (MR) data provide evidence for quantum interference and weak localization at room temperature, as well as a temperature and field-induced crossover from negative to positive MR. Furthermore, pili can be doped with protons. Structural studies suggest the possibility of molecular pi stacking in pili, causing electron delocalization. Reducing the disorder increases the metallic nature of pili. These electronically functional proteins are a new class of electrically conductive biological proteins that can be used to generate future generation of inexpensive and environmentally-sustainable nanomaterials and nanolectronic devices such as transistors and supercapacitors. [1] Malvankar et al. Nature Nanotechnology, 6, 573-579 (2011)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakhri, M.; Theisen, M.; Behrendt, A.

Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al{sub 2}O{sub 3}/ZrO{sub 2} as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices withmore » encapsulation.« less

Electrolysis-induced protonation of VO2 thin film transistor for the metal-insulator phase modulation

NASA Astrophysics Data System (ADS)

Katase, Takayoshi; Endo, Kenji; Ohta, Hiromichi

2016-02-01

Compared to state-of-the-art modulation techniques, protonation is the most ideal to control the electrical and optical properties of transition metal oxides (TMOs) due to its intrinsic non-volatile operation. However, the protonation of TMOs is not typically utilized for solid-state devices because of imperative high-temperature annealing treatment in hydrogen source. Although one solution for room temperature (RT) protonation of TMOs is liquid-phase electrochemistry, it is unsuited for practical purposes due to liquid-leakage problem. Herein we demonstrate solid-state RT-protonation of vanadium dioxide (VO2), which is a well-known thermochromic TMO. We fabricated the three terminal thin-film-transistor structure on an insulating VO2 film using a water-infiltrated nanoporous glass, which serves as a solid electrolyte. For gate voltage application, water electrolysis and protonation/deprotonation of VO2 film surface occurred, leading to reversible metal-insulator phase conversion of ~11-nm-thick VO2 layer. The protonation was clearly accompanied by the structural change from an insulating monoclinic to a metallic tetragonal phase. Present results offer a new route for the development of electro-optically active solid-state devices with TMO materials by engineering RT protonation.

Planarized thick copper gate polycrystalline silicon thin film transistors for ultra-large AMOLED displays

NASA Astrophysics Data System (ADS)

Yun, Seung Jae; Lee, Yong Woo; Son, Se Wan; Byun, Chang Woo; Reddy, A. Mallikarjuna; Joo, Seung Ki

2012-08-01

A planarized thick copper (Cu) gate low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) is fabricated for ultra-large active-matrix organic light-emitting diode (AMOLED) displays. We introduce a damascene and chemical mechanical polishing process to embed a planarized Cu gate of 500 nm thickness into a trench and Si3N4/SiO2 multilayer gate insulator, to prevent the Cu gate from diffusing into the silicon (Si) layer at 550°C, and metal-induced lateral crystallization (MILC) technology to crystallize the amorphous Si layer. A poly-Si TFT with planarized thick Cu gate exhibits a field effect mobility of 5 cm2/Vs and a threshold voltage of -9 V, and a subthreshold swing (S) of 1.4 V/dec.

Gate oxide thickness dependence of the leakage current mechanism in Ru/Ta2O5/SiON/Si structures

NASA Astrophysics Data System (ADS)

Ťapajna, M.; Paskaleva, A.; Atanassova, E.; Dobročka, E.; Hušeková, K.; Fröhlich, K.

2010-07-01

Leakage conduction mechanisms in Ru/Ta2O5/SiON/Si structures with rf-sputtered Ta2O5 with thicknesses ranging from 13.5 to 1.8 nm were systematically studied. Notable reaction at the Ru/Ta2O5 interface was revealed by capacitance-voltage measurements. Temperature-dependent current-voltage characteristics suggest the bulk-limited conduction mechanism in all metal-oxide-semiconductor structures. Under gate injection, Poole-Frenkel emission was identified as a dominant mechanism for 13.5 nm thick Ta2O5. With an oxide thickness decreasing down to 3.5 nm, the conduction mechanism transforms to thermionic trap-assisted tunnelling through the triangular barrier. Under substrate injection, the dominant mechanism gradually changes with decreasing thickness from thermionic trap-assisted tunnelling to trap-assisted tunnelling through the triangular barrier; Poole-Frenkel emission was not observed at all. A 0.7 eV deep defect level distributed over Ta2O5 is assumed to be responsible for bulk-limited conduction mechanisms and is attributed to H-related defects or oxygen vacancies in Ta2O5.

Graphene-based active slow surface plasmon polaritons

PubMed Central

Lu, Hua; Zeng, Chao; Zhang, Qiming; Liu, Xueming; Hossain, Md Muntasir; Reineck, Philipp; Gu, Min

2015-01-01

Finding new ways to control and slow down the group velocity of light in media remains a major challenge in the field of optics. For the design of plasmonic slow light structures, graphene represents an attractive alternative to metals due to its strong field confinement, comparably low ohmic loss and versatile tunability. Here we propose a novel nanostructure consisting of a monolayer graphene on a silicon based graded grating structure. An external gate voltage is applied to graphene and silicon, which are separated by a spacer layer of silica. Theoretical and numerical results demonstrate that the structure exhibits an ultra-high slowdown factor above 450 for the propagation of surface plasmon polaritons (SPPs) excited in graphene, which also enables the spatially resolved trapping of light. Slowdown and trapping occur in the mid-infrared wavelength region within a bandwidth of ~2.1 μm and on a length scale less than 1/6 of the operating wavelength. The slowdown factor can be precisely tuned simply by adjusting the external gate voltage, offering a dynamic pathway for the release of trapped SPPs at room temperature. The presented results will enable the development of highly tunable optoelectronic devices such as plasmonic switches and buffers. PMID:25676462

Degradation of Gate Oxide Integrity by Formation of Tiny Holes by Metal Contamination of Raw Wafer

NASA Astrophysics Data System (ADS)

Chen, Po-Ying

2008-12-01

Heavy metal atoms (such as Cu) spontaneously undergo a dissolution reaction when they come into contact with silicon. Most investigations in this extensively studied area begin with a clean, bare wafer and focus on metal contamination during the IC manufacturing stage. In this work, the effect of Fe and Cu contamination on raw wafers was elucidated. When two batches of raw wafers are scheduled, one uncontaminated and one with various degrees of contamination ranging from 0.1 to 10 ppb undergo the typical steps of the 90 nm LOGIC complementary metal-oxide-semiconductor (CMOS) semiconductor manufacturing process. The main contribution of this work is the discovery of a previously unidentified cause of gate oxide leakage: the formation of tiny holes by metal contamination during the wafer manufacturing stage. Because tiny holes are formed, a spontaneous reaction can occur even with at very low metal concentration (0.2 ppb), revealing that the wafer manufacturing stage is more vulnerable to metal contamination than the IC manufacturing stage and therefore requires stricter contamination control.

Comparative study of CAVET with dielectric and p-GaN gate and Mg ion-implanted current blocking layer

NASA Astrophysics Data System (ADS)

Mandal, Saptarshi; Agarwal, Anchal; Ahmadi, Elaheh; Mahadeva Bhat, K.; Laurent, Matthew A.; Keller, Stacia; Chowdhury, Srabanti

2017-08-01

In this work, a study of two different types of current aperture vertical electron transistor (CAVET) with ion-implanted blocking layer are presented. The device fabrication and performance limitation of a CAVET with a dielectric gate is discussed, and the breakdown limiting structure is evaluated using on-wafer test structures. The gate dielectric limited the device breakdown to 50V, while the blocking layer was able to withstand over 400V. To improve the device performance, an alternative CAVET structure with a p-GaN gate instead of dielectric is designed and realized. The pGaN gated CAVET structure increased the breakdown voltage to over 400V. Measurement of test structures on the wafer showed the breakdown was limited by the blocking layer instead of the gate p-n junction.

Modeling of Metal-Ferroelectric-Semiconductor Field Effect Transistors

NASA Technical Reports Server (NTRS)

Duen Ho, Fat; Macleod, Todd C.

1998-01-01

The characteristics for a MFSFET (metal-ferroelectric-semiconductor field effect transistor) is very different than a conventional MOSFET and must be modeled differently. The drain current has a hysteresis shape with respect to the gate voltage. The position along the hysteresis curve is dependent on the last positive or negative polling of the ferroelectric material. The drain current also has a logarithmic decay after the last polling. A model has been developed to describe the MFSFET drain current for both gate voltage on and gate voltage off conditions. This model takes into account the hysteresis nature of the MFSFET and the time dependent decay. The model is based on the shape of the Fermi-Dirac function which has been modified to describe the MFSFET's drain current. This is different from the model proposed by Chen et. al. and that by Wu.

GaN metal-oxide-semiconductor field-effect transistors on AlGaN/GaN heterostructure with recessed gate

NASA Astrophysics Data System (ADS)

Wang, Qingpeng; Ao, Jin-Ping; Wang, Pangpang; Jiang, Ying; Li, Liuan; Kawaharada, Kazuya; Liu, Yang

2015-04-01

GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure with a recess gate were fabricated and characterized. The device showed good pinch-off characteristics and a maximum field-effect mobility of 145.2 cm2·V-1·s-1. The effects of etching gas of Cl2 and SiCl4 were investigated in the gate recess process. SiCl4-etched devices showed higher channel mobility and lower threshold voltage. Atomic force microscope measurement was done to investigate the etching profile with different etching protection mask. Compared with photoresist, SiO2-masked sample showed lower surface roughness and better profile with stepper sidewall and weaker trenching effect resulting in higher channel mobility in the MOSFET.

INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY: Quantum-Mechanical Study on Surrounding-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Hu, Guang-Xi; Wang, Ling-Li; Liu, Ran; Tang, Ting-Ao; Qiu, Zhi-Jun

2010-10-01

As the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) scales into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrödinger equation is solved analytically. Some of the solutions are verified via results obtained from simulations. It is found that the percentage of the electrons with lighter conductivity mass increases as the silicon body radius decreases, or as the gate voltage reduces, or as the temperature decreases. The centroid of inversion-layer is driven away from the silicon-oxide interface towards the silicon body, therefore the carriers will suffer less scattering from the interface and the electrons effective mobility of the SG nMOSFETs will be enhanced.

Metal-oxide assisted surface treatment of polyimide gate insulators for high-performance organic thin-film transistors.

PubMed

Kim, Sohee; Ha, Taewook; Yoo, Sungmi; Ka, Jae-Won; Kim, Jinsoo; Won, Jong Chan; Choi, Dong Hoon; Jang, Kwang-Suk; Kim, Yun Ho

2017-06-14

We developed a facile method for treating polyimide-based organic gate insulator (OGI) surfaces with self-assembled monolayers (SAMs) by introducing metal-oxide interlayers, called the metal-oxide assisted SAM treatment (MAST). To create sites for surface modification with SAM materials on polyimide-based OGI (KPI) surfaces, the metal-oxide interlayer, here amorphous alumina (α-Al 2 O 3 ), was deposited on the KPI gate insulator using spin-coating via a rapid sol-gel reaction, providing an excellent template for the formation of a high-quality SAM with phosphonic acid anchor groups. The SAM of octadecylphosphonic acid (ODPA) was successfully treated by spin-coating onto the α-Al 2 O 3 -deposited KPI film. After the surface treatment by ODPA/α-Al 2 O 3 , the surface energy of the KPI thin film was remarkably decreased and the molecular compatibility of the film with an organic semiconductor (OSC), 2-decyl-7-phenyl-[1]benzothieno[3,2-b][1]benzothiophene (Ph-BTBT-C 10 ), was increased. Ph-BTBT-C 10 molecules were uniformly deposited on the treated gate insulator surface and grown with high crystallinity, as confirmed by atomic force microscopy (AFM) and X-ray diffraction (XRD) analysis. The mobility of Ph-BTBT-C 10 thin-film transistors (TFTs) was approximately doubled, from 0.56 ± 0.05 cm 2 V -1 s -1 to 1.26 ± 0.06 cm 2 V -1 s -1 , after the surface treatment. The surface treatment of α-Al 2 O 3 and ODPA significantly decreased the threshold voltage from -21.2 V to -8.3 V by reducing the trap sites in the OGI and improving the interfacial properties with the OSC. We suggest that the MAST method for OGIs can be applied to various OGI materials lacking reactive sites using SAMs. It may provide a new platform for the surface treatment of OGIs, similar to that of conventional SiO 2 gate insulators.

Origin of positive fixed charge at insulator/AlGaN interfaces and its control by AlGaN composition

NASA Astrophysics Data System (ADS)

Matys, M.; Stoklas, R.; Blaho, M.; Adamowicz, B.

2017-06-01

The key feature for the precise tuning of Vth in GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors is the control of the positive fixed charge (Qf) at the insulator/III-N interfaces, whose amount is often comparable to the negative surface polarization charge ( Qp o l -). In order to clarify the origin of Qf, we carried out a comprehensive capacitance-voltage (C-V) characterization of SiO2/AlxGa1-xN/GaN and SiN/AlxGa1-xN/GaN structures with Al composition (x) varying from 0.15 to 0.4. For both types of structures, we observed a significant Vth shift in C-V curves towards the positive gate voltage with increasing x. On the contrary, the Schottky gate structures exhibited Vth shift towards the more negative biases. From the numerical simulations of C-V curves using the Poisson's equation supported by the analytical calculations of Vth, we showed that the Vth shift in the examined MIS structures is due to a significant decrease in the positive Qf with rising x. Finally, we examined this result with respect to various hypotheses developed in the literature to explain the origin of the positive Qf at insulator/III-N interfaces.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Epitaxy of semiconductor-superconductor nanowires

NASA Astrophysics Data System (ADS)

Krogstrup, P.; Ziino, N. L. B.; Chang, W.; Albrecht, S. M.; Madsen, M. H.; Johnson, E.; Nygård, J.; Marcus, C. M.; Jespersen, T. S.

2015-04-01

Controlling the properties of semiconductor/metal interfaces is a powerful method for designing functionality and improving the performance of electrical devices. Recently semiconductor/superconductor hybrids have appeared as an important example where the atomic scale uniformity of the interface plays a key role in determining the quality of the induced superconducting gap. Here we present epitaxial growth of semiconductor-metal core-shell nanowires by molecular beam epitaxy, a method that provides a conceptually new route to controlled electrical contacting of nanostructures and the design of devices for specialized applications such as topological and gate-controlled superconducting electronics. Our materials of choice, InAs/Al grown with epitaxially matched single-plane interfaces, and alternative semiconductor/metal combinations allowing epitaxial interface matching in nanowires are discussed. We formulate the grain growth kinetics of the metal phase in general terms of continuum parameters and bicrystal symmetries. The method realizes the ultimate limit of uniform interfaces and seems to solve the soft-gap problem in superconducting hybrid structures.

Characterizing Radio Emission From Extensive Air Showers with the SLAC-T510 Experiment, with Applications to ANITA

NASA Astrophysics Data System (ADS)

McGuire, Felicia Ann

Essential to metal-oxide-semiconductor field-effect transistor (MOSFET) scaling is the reduction of the supply voltage to mitigate the power consumption and corresponding heat dissipation. Conventional dielectric materials are subject to the thermal limit imposed by the Boltzmann factor in the subthreshold swing, which places an absolute minimum on the supply voltage required to modulate the current. Furthermore, as technology approaches the 5 nm node, electrostatic control of a silicon channel becomes exceedingly difficult, regardless of the gating technique. This notion of "the end of silicon scaling" has rapidly increased research into more scalable channel materials as well as new methods of transistor operation. Among the many promising options are two-dimensional (2D) FETs and negative capacitance (NC) FETs. 2D-FETs make use of atomically thin semiconducting channels that have enabled demonstrated scalability beyond what silicon can offer. NC-FETs demonstrate an effective negative capacitance arising from the integration of a ferroelectric into the transistor gate stack, allowing sub-60 mV/dec switching. While both of these devices provide significant advantages, neither can accomplish the ultimate goal of a FET that is both low-voltage and scalable. However, an appropriate fusion of the 2D-FET and NC-FET into a 2D NC-FET has the potential of enabling a steep-switching device that is dimensionally scalable beyond the 5 nm technology node. In this work, the motivation for and operation of 2D NC-FETs is presented. Experimental realization of 2D NC-FETs using 2D transition metal dichalcogenide molybdenum disulfide (MoS2) as the channel is shown with two different ferroelectric materials: 1) a solution-processed, polymeric poly(vinylidene difluoride trifluoroethylene) ferroelectric and 2) an atomic layer deposition (ALD) grown hafnium zirconium oxide (HfZrO2) ferroelectric. Each ferroelectric was integrated into the gate stack of a 2D-FET having either a top-gate (polymeric ferroelectric) or bottom-gate (HfZrO2 ferroelectric) configuration. HfZrO 2 devices with metallic interfacial layers (between ferroelectric and dielectric) and thinner ferroelectric layers were found to reduce both the hysteresis and the threshold voltage. Detailed characterization of the devices was performed and, most significantly, the 2D NC-FETs with HfZrO2 reproducibly yielded subthreshold swings well below the thermal limit with over more than four orders of magnitude in drain current modulation. HfZrO 2 devices without metallic interfacial layers were utilized to explore the impact of ferroelectric thickness, dielectric thickness, and dielectric composition on device performance. The impact of an interfacial metallic layer on the device operation was investigated in devices with HfZrO2 and shown to be crucial at enabling sub-60 mV/dec switching and large internal voltage gains. The significance of dielectric material choice on device performance was explored and found to be a critical factor in 2D NC-FET transistor operation. These successful results pave the way for future integration of this new device structure into existing technology markets.

High voltage MOSFET devices and methods of making the devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Banerjee, Sujit; Matocha, Kevin; Chatty, Kiran

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+more » region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.« less

Compositional and gate tuning of the interfacial conductivity in LaAlO3/LaTiO3/SrTiO3 heterostructures

NASA Astrophysics Data System (ADS)

Hosoda, Masayuki; Bell, Christopher; Hikita, Yasuyuki; Hwang, Harold Y.

2013-03-01

We investigate the effect of LaTiO3 insertion at the interface between LaAlO3 and TiO2 terminated {100} SrTiO3 for a series of LaAlO3 and LaTiO3 thicknesses. A clear increase of the carrier density was observed while the Hall mobility was largely unchanged. In structures with LaAlO3 thickness ˜3 unit cells, close to the critical thickness for conductivity, as little as 0.25 unit cells of LaTiO3 drives an insulator-to-metal transition. These samples show a strong dependence of the conductivity on voltage with electrostatic back-gating, which can be understood in a two-carrier picture, and dominated by the change in carrier density at the interface.

Electrical level of defects in single-layer two-dimensional TiO2

NASA Astrophysics Data System (ADS)

Song, X. F.; Hu, L. F.; Li, D. H.; Chen, L.; Sun, Q. Q.; Zhou, P.; Zhang, D. W.

2015-11-01

The remarkable properties of graphene and transition metal dichalcogenides (TMDCs) have attracted increasing attention on two-dimensional materials, but the gate oxide, one of the key components of two-dimensional electronic devices, has rarely reported. We found the single-layer oxide can be used as the two dimensional gate oxide in 2D electronic structure, such as TiO2. However, the electrical performance is seriously influenced by the defects existing in the single-layer oxide. In this paper, a nondestructive and noncontact solution based on spectroscopic ellipsometry has been used to detect the defect states and energy level of single-layer TiO2 films. By fitting the Lorentz oscillator model, the results indicate the exact position of defect energy levels depends on the estimated band gap and the charge state of the point defects of TiO2.

High voltage MOSFET devices and methods of making the devices

DOEpatents

Banerjee, Sujit; Matocha, Kevin; Chatty, Kiran

2015-12-15

A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Performance analysis of SOI MOSFET with rectangular recessed channel

NASA Astrophysics Data System (ADS)

Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

2016-03-01

In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

Reconfigurable ultra-thin film GDNMOS device for ESD protection in 28 nm FD-SOI technology

NASA Astrophysics Data System (ADS)

Athanasiou, Sotirios; Legrand, Charles-Alexandre; Cristoloveanu, Sorin; Galy, Philippe

2017-02-01

We propose a novel ESD protection device (GDNMOS: Gated Diode merged NMOS) fabricated with 28 nm UTBB FD-SOI high-k metal gate technology. By modifying the combination of the diode and transistor gate stacks, the robustness of the device is optimized, achieving a maximum breakdown voltage (VBR) of 4.9 V. In addition, modifications of the gate length modulate the trigger voltage (Vt1) with a minimum value of 3.5 V. Variable electrostatic doping (gate-induced) in diode and transistor body enables reconfigurable operation. A lower doping of the base enhances the bipolar gain, leading to thyristor behavior. This innovative architecture demonstrates excellent capability for high-voltage protection while maintaining a latch-up free behavior.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Structural Modification of Organic Thin-Film Transistors for Photosensor Application

NASA Astrophysics Data System (ADS)

Jeong, Hyeon Seok; Bae, Jin-Hyuk; Lee, Hyeonju; Ndikumana, Joel; Park, Jaehoon

2018-05-01

We investigated the light response characteristics of bottom-gate/top-contact organic TFTs fabricated using pentacene and polystyrene as an organic semiconductor and a polymeric insulator, respectively. The pentacene TFT with overlaps (50 μm) between the source and gate electrodes as well as between the drain and gate electrodes exhibited negligible hysteresis in its transfer characteristics upon reversal of the gate voltage sweep direction. When the TFTs were structurally modified to produce an underlap structure between the source and gate electrodes, clockwise hysteresis and a drain-current decrease were observed, which were further augmented by increasing the gate underlap (from 30 μm to 50 μm and 70 μm). Herein, these results are explained in terms of space charge formation and accumulation capacitance reduction. Importantly, we found that space charges formed under the source electrode contributed to the drain currents via light irradiation through the underlap region. Under constant bias conditions, the TFTs with gate underlap structures thus exhibited on-state drain current changes in response to light signals. In our study, an optimal photosensitivity exceeding 11 was achieved by the TFT with a 30 μm gate underlap. Consequently, we suggest that gate underlap structure modification is a viable means of implementing light responsiveness in organic TFTs.

Nonvolatile memory with Co-SiO2 core-shell nanocrystals as charge storage nodes in floating gate

NASA Astrophysics Data System (ADS)

Liu, Hai; Ferrer, Domingo A.; Ferdousi, Fahmida; Banerjee, Sanjay K.

2009-11-01

In this letter, we reported nanocrystal floating gate memory with Co-SiO2 core-shell nanocrystal charge storage nodes. By using a water-in-oil microemulsion scheme, Co-SiO2 core-shell nanocrystals were synthesized and closely packed to achieve high density matrix in the floating gate without aggregation. The insulator shell also can help to increase the thermal stability of the nanocrystal metal core during the fabrication process to improve memory performance.

Manipulating molecular quantum states with classical metal atom inputs: demonstration of a single molecule NOR logic gate.

PubMed

Soe, We-Hyo; Manzano, Carlos; Renaud, Nicolas; de Mendoza, Paula; De Sarkar, Abir; Ample, Francisco; Hliwa, Mohamed; Echavarren, Antonio M; Chandrasekhar, Natarajan; Joachim, Christian

2011-02-22

Quantum states of a trinaphthylene molecule were manipulated by putting its naphthyl branches in contact with single Au atoms. One Au atom carries 1-bit of classical information input that is converted into quantum information throughout the molecule. The Au-trinaphthylene electronic interactions give rise to measurable energy shifts of the molecular electronic states demonstrating a NOR logic gate functionality. The NOR truth table of the single molecule logic gate was characterized by means of scanning tunnelling spectroscopy.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

PubMed Central

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors.

PubMed

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-07-03

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W).

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps

NASA Astrophysics Data System (ADS)

Hsu, Sheng-Chia; Li, Yiming

2014-11-01

In this work, we study the impact of random interface traps (RITs) at the interface of SiO x /Si on the electrical characteristic of 16-nm-gate high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state ( D it). The variability of the off-state current ( I off) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D it varying from 5 × 1012 to 5 × 1013 eV-1 cm-2 owing to significant threshold voltage ( V th) fluctuation. The results of this study indicate that if the level of D it is lower than 1 × 1012 eV-1 cm-2, the normalized variability of the on-state current, I off, V th, DIBL, and subthreshold swing is within 5%.

Solving A Corrosion Problem

NASA Technical Reports Server (NTRS)

1979-01-01

The corrosion problem, it turned out, stemmed from the process called electrolysis. When two different metals are in contact, an electrical potential is set up between them; when the metals are surrounded by an electrolyte, or a conducting medium, the resulting reaction causes corrosion, often very rapid corrosion. In this case the different metals were the copper grounding system and the ferry's aluminum hull; the dockside salt water in which the hull was resting served as the electrolyte. After identifying the source of the trouble, the Ames engineer provided a solution: a new wire-and-rod grounding system made of aluminum like the ferry's hull so there would no longer be dissimilar metals in contact. Ames research on the matter disclosed that the problem was not unique to the Golden Gate ferries. It is being experienced by many pleasure boat operators who are probably as puzzled about it as was the Golden Gate Transit Authority.

Extended Characterization of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field Effect Transistor

NASA Technical Reports Server (NTRS)

Hunt, Mitchell; Sayyah, Rana; Mitchell, Cody; Laws, Crystal; MacLeod, Todd C.; Ho, Fat D.

2013-01-01

Collected data for both common-source and common-gate amplifiers is presented in this paper. Characterizations of the two amplifier circuits using metal-ferroelectric-semiconductor field effect transistors (MFSFETs) are developed with wider input frequency ranges and varying device sizes compared to earlier characterizations. The effects of the ferroelectric layer's capacitance and variation load, quiescent point, or input signal on each circuit are discussed. Comparisons between the MFSFET and MOSFET circuit operation and performance are discussed at length as well as applications and advantages for the MFSFETs.

Enhanced two dimensional electron gas transport characteristics in Al2O3/AlInN/GaN metal-oxide-semiconductor high-electron-mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Freedsman, J. J.; Watanabe, A.; Urayama, Y.; Egawa, T.

2015-09-01

The authors report on Al2O3/Al0.85In0.15N/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistor (MOS-HEMT) on Si fabricated by using atomic layer deposited Al2O3 as gate insulator and passivation layer. The MOS-HEMT with the gate length of 2 μm exhibits excellent direct-current (dc) characteristics with a drain current maximum of 1270 mA/mm at a gate bias of 3 V and an off-state breakdown voltage of 180 V for a gate-drain spacing of 4 μm. Also, the 1 μm-gate MOS-HEMT shows good radio-frequency (rf) response such as current gain and maximum oscillation cut-off frequencies of 10 and 34 GHz, respectively. The capacitance-voltage characteristics at 1 MHz revealed significant increase in two-dimensional electron gas (2DEG) density for the MOS-HEMT compared to conventional Schottky barrier HEMTs. Analyses using drain-source conductivity measurements showed improvements in 2DEG transport characteristics for the MOS-HEMT. The enhancements in dc and rf performances of the Al2O3/Al0.85In0.15N/GaN MOS-HEMT are attributed to the improvements in 2DEG characteristics.

Electro-plasmonic 2 × 2 channel-routing switch arranged on a thin-Si-doped metal/insulator/semiconductor/metal structure.

PubMed

Moazzam, Mostafa Keshavarz; Kaatuzian, Hassan

2016-01-20

Plasmonics as a new field of chip-scale technology is the interesting substrate of this study to propose and numerically investigate a metal/insulator/semiconductor/metal (MISM)-structure 2×2 plasmonic routing switch. As a planar subwavelength arrangement, the presented design has two npn-doped side-coupled dual waveguides whose duty is to route the propagating surface plasmon polaritons through the device. Relying on the MISM structure, which has a MOS-like thin-film arrangement of typically 45 nm doped silicon covered by a layer of 8 nm thick HfO(2) gate insulator, the routing configuration is electrically addressed based on the carrier-induced plasma dispersion effects as an external electro-plasmonic switching control. Finite-element-method-conducted electromagnetic simulations are employed to evaluate the switch optical response at telecom wavelength of λ=1550  nm, due to which the balanced operation measure of extinction ratios larger than 10 dB and insertion losses of around -1.8  dB are obtained for both channels of CROSS and STRAIGHT. Compared with other photonic and plasmonic switching counterparts, this configuration, besides its potential for CMOS compatibility, can be utilized as a high-speed compact building block to sustain higher-speed, more miniaturized, and less consuming electro-optic routing/switching protocols toward complicated optical integrated circuits and systems.

Control-Structure Ratings on the Fox River at McHenry and Algonquin, Illinois

USGS Publications Warehouse

Straub, Timothy D.; Johnson, Gary P.; Hortness, Jon E.; Parker, Joseph R.

2009-01-01

The Illinois Department of Natural Resources-Office of Water Resources operates control structures on a reach of the Fox River in northeastern Illinois between McHenry and Algonquin. The structures maintain water levels in the river for flood-control and recreational purposes. This report documents flow ratings for hinged-crest gates, a broad-crested weir, sluice gates, and an ogee spillway on the control structures at McHenry and Algonquin. The ratings were determined by measuring headwater and tailwater stage along with streamflow at a wide range of flows at different gate openings. Standard control-structure rating techniques were used to rate each control structure. The control structures at McHenry consist of a 221-feet(ft)-long broad-crested weir, a 4-ft-wide fish ladder, a 50-ft-wide hinged-crest gate, five 13.75-ft-wide sluice gates, and a navigational lock. Sixty measurements were used to rate the McHenry structures. The control structures at Algonquin consist of a 242-ft-long ogee spillway and a 50-ft-wide hinged-crest gate. Forty-one measurements were used to rate the Algonquin control structures.

Metal-insulator and charge ordering transitions in oxide nanostructures

NASA Astrophysics Data System (ADS)

Singh, Sujay Kumar

Strongly correlated oxides are a class of materials wherein interplay of various degrees of freedom results in novel electronic and magnetic phenomena. Vanadium oxides are widely studied correlated materials that exhibit metal-insulator transitions (MIT) in a wide temperature range from 70 K to 380 K. In this Thesis, results from electrical transport measurements on vanadium dioxide (VO2) and vanadium oxide bronze (MxV 2O5) (where M: alkali, alkaline earth, and transition metal cations) are presented and discussed. Although the MIT in VO2 has been studied for more than 50 years, the microscopic origin of the transition is still debated since a slew of external parameters such as light, voltage, and strain are found to significantly alter the transition. Furthermore, recent works on electrically driven switching in VO2 have shown that the role of Joule heating to be a major cause as opposed to electric field. We explore the mechanisms behind the electrically driven switching in single crystalline nanobeams of VO2 through DC and AC transport measurements. The harmonic analysis of the AC measurement data shows that non-uniform Joule heating causes electronic inhomogeneities to develop within the nanobeam and is responsible for driving the transition in VO2. Surprisingly, field assisted emission mechanisms such as Poole-Frenkel effect is found to be absent and the role of percolation is also identified in the electrically driven transition. This Thesis also provides a new insight into the mechanisms behind the electrolyte gating induced resistance modulation and the suppression of MIT in VO2. We show that the metallic phase of VO2 induced by electrolyte gating is due to an electrochemical process and can be both reversible and irreversible under different conditions. The kinetics of the redox processes increase with temperature; a complete suppression of the transition and the stabilization of the metallic phase are achievable by gating in the rutile metallic phase. First principles calculations show that the destabilization of the insulating phase during the gating arises due to the formation of oxygen vacancies in VO2; the rutile phase is far more amenable to electrochemical reduction as compared to the monoclinic phase, likely due to its higher electrical conductivity. The generation of oxygen vacancies appears thermodynamically favorable if the removed oxygen atoms from VO2 oxidize the anions in the ionic liquid. Finally, electronic properties of single crystalline, individual nanowires of vanadium oxide bronzes (MxVO 2O5) are presented. The intercalation effects of metal cation and the stoichiometry (x) are explored and discussed. These nanowires exhibit thermally and electrically driven charge ordering and metal to insulator transitions. The electrolyte gating measurements show resistance modulations across the phase transition but the effect is not as dramatic as in VO2.

Suppression of gate leakage current in in-situ grown AlN/InAlN/AlN/GaN heterostructures based on the control of internal polarization fields

NASA Astrophysics Data System (ADS)

Kotani, Junji; Yamada, Atsushi; Ishiguro, Tetsuro; Yamaguchi, Hideshi; Nakamura, Norikazu

2017-03-01

This paper investigates the gate leakage characteristics of in-situ AlN capped InAlN/AlN/GaN heterostructures grown by metal-organic vapor phase epitaxy. It was revealed that the leakage characteristics of AlN capped InAlN/AlN/GaN heterostructures are strongly dependent on the growth temperature of the AlN cap. For an AlN capped structure with an AlN growth temperature of 740 °C, the leakage current even increased although there exists a large bandgap material on InAlN/AlN/GaN heterostructures. On the other hand, a large reduction of the gate leakage current by 4-5 orders of magnitudes was achieved with a very low AlN growth temperature of 430 °C. X-ray diffraction analysis of the AlN cap grown at 740 °C indicated that the AlN layer is tensile-strained. In contrast to this result, the amorphous structure was confirmed for the AlN cap grown at 430 °C by transmission electron microscopy. Furthermore, theoretical analysis based on one-dimensional band simulation was carried out, and the large increase in two-dimensional electron gas (2DEG) observed in Hall measurements was well reproduced by taking into account the spontaneous and piezo-electric polarization in the AlN layer grown at 740 °C. For the AlN capped structure grown at 430 °C, it is believed that the reduced polarization field in the AlN cap suppressed the penetration of 2DEG into the InAlN barrier layer, resulting in a small impact on 2DEG mobility and density. We believe that an in-situ grown AlN cap with a very low growth temperature of 430 °C is a promising candidate for high-frequency/high-power GaN-based devices with low gate leakage current.

Energy Saving Melting and Revert Reduction Technology (Energy-SMARRT): Clean Steel Casting Production

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kuyucak, Selcuk; Li, Delin

2013-12-31

Inclusions in steel castings can cause rework, scrap, poor machining, and reduced casting performance, which can obviously result in excess energy consumption. Significant progress in understanding inclusion source, formation and control has been made. Inclusions can be defined as non-metallic materials such as refractory, sand, slag, or coatings, embedded in a metallic matrix. This research project has focused on the mold filling aspects to examine the effects of pouring methods and gating designs on the steel casting cleanliness through water modeling, computer modeling, and melting/casting experiments. Early in the research project, comprehensive studies of bottom-pouring water modeling and low-alloy steelmore » casting experiments were completed. The extent of air entrainment in bottom-poured large castings was demonstrated by water modeling. Current gating systems are designed to prevent air aspiration. However, air entrainment is equally harmful and no prevention measures are in current practice. In this study, new basin designs included a basin dam, submerged nozzle, and nozzle extension. The entrained air and inclusions from the gating system were significantly reduced using the new basin method. Near the end of the project, there has been close collaboration with Wescast Industries Inc., a company manufacturing automotive exhaust components. Both computer modeling using Magma software and melting/casting experiments on thin wall turbo-housing stainless steel castings were completed in this short period of time. Six gating designs were created, including the current gating on the pattern, non-pressurized, partially pressurized, naturally pressurized, naturally pressurized without filter, and radial choke gating without filter, for Magma modeling. The melt filling velocity and temperature were determined from the modeling. Based on the simulation results, three gating designs were chosen for further melting and casting experiments on the same casting pattern using the lip pouring method. It was observed again that gating designs greatly influenced the melt filling velocity and the number of inclusion defects. The radial choked gating showed improvements in casting cleanliness and yield over the other gatings, even though no mold filters were used in the gating system.« less

A compact quantum correction model for symmetric double gate metal-oxide-semiconductor field-effect transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cho, Edward Namkyu; Shin, Yong Hyeon; Yun, Ilgu, E-mail: iyun@yonsei.ac.kr

2014-11-07

A compact quantum correction model for a symmetric double gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. The compact quantum correction model is proposed from the concepts of the threshold voltage shift (ΔV{sub TH}{sup QM}) and the gate capacitance (C{sub g}) degradation. First of all, ΔV{sub TH}{sup QM} induced by quantum mechanical (QM) effects is modeled. The C{sub g} degradation is then modeled by introducing the inversion layer centroid. With ΔV{sub TH}{sup QM} and the C{sub g} degradation, the QM effects are implemented in previously reported classical model and a comparison between the proposed quantum correction model and numerical simulationmore » results is presented. Based on the results, the proposed quantum correction model can be applicable to the compact model of DG MOSFET.« less

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

NASA Astrophysics Data System (ADS)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

Metal-oxide thin-film transistor-based pH sensor with a silver nanowire top gate electrode

NASA Astrophysics Data System (ADS)

Yoo, Tae-Hee; Sang, Byoung-In; Wang, Byung-Yong; Lim, Dae-Soon; Kang, Hyun Wook; Choi, Won Kook; Lee, Young Tack; Oh, Young-Jei; Hwang, Do Kyung

2016-04-01

Amorphous InGaZnO (IGZO) metal-oxide-semiconductor thin-film transistors (TFTs) are one of the most promising technologies to replace amorphous and polycrystalline Si TFTs. Recently, TFT-based sensing platforms have been gaining significant interests. Here, we report on IGZO transistor-based pH sensors in aqueous medium. In order to achieve stable operation in aqueous environment and enhance sensitivity, we used Al2O3 grown by using atomic layer deposition (ALD) and a porous Ag nanowire (NW) mesh as the top gate dielectric and electrode layers, respectively. Such devices with a Ag NW mesh at the top gate electrode rapidly respond to the pH of solutions by shifting the turn-on voltage. Furthermore, the output voltage signals induced by the voltage shifts can be directly extracted by implantation of a resistive load inverter.

75 FR 16453 - Domtar Maine LLC; Notice of Petition for Declaratory Order and Soliciting Comments, Protests, and...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-01

..., containing a gated timber spillway structure 65 feet wide, with 3 gates and a fish passage facility; (2) a... timber crib structure, 485 feet long and 13 feet high, containing a gated spillway structure, 77 feet... appurtenances; and (B) Sysladobsis Lake development: (1) Sysladobsis Lake Dam, an earth embankment structure...

Metal oxide, Group V-VI chalcogenides and GaN/AlGaN photodetectors

NASA Astrophysics Data System (ADS)

Hasan, Md. Rezaul

In this work, a simple, low-cost and catalyst free one-step solution processing of onedimensional Sb2S3 nanostructures on polyimide substrates was done. This structure demonstrated its potential application as a photoconductor in the UV and visible regime. Using-field emission scanning electron microscopy (SEM), grazing incidence X-Ray diffraction, Raman spectra and transmission electron microscopy measurements, it was shown that the Sb 2S3 films have high crystallinity, uniform morphology and nearstoichiometric composition. Further, using tauc plot, it was found that the films have a direct bandgap of 1.67 eV. MSM photodetectors, fabricated using these films showed a clear photo response in both UV as well as visible wavelength. These devices showed UV on/off ratio as high as 160 under the light intensity of 30 mW/cm2 and a small rise time and fall time of 44 ms 28 ms respectively. The effect of geometry of metal pad and bonding wire orientation of a multi-channel FET on the coupling of THz radiation was studied. The spatial variation images were taken by raster scan with the resolution of 0.07 mm steps in both x and y directions. An effective gate bias, where the effect of noise is minimum and photoresponse is maximum, was used for imaging. By applying VGS =-2.8V and VDS =380mV, the images were taken for all different combinations of activated bonding wires and metal pads. It was observed that, effect of bonding wire orientation is negligible for the large source pad as the radiation is coupled basically between drain and gate pad. Effect of drain bonding wire on coupling depends on the maximum width or diameter of metal pad and the incoming wavelength. In this work, Position of activated Drain pad and orientation of respective bonding wire defined the image tilting angle. Voltage drop across the shorting metal between drain pads, also played a role in increasing the asymmetry by selectively exciting a certain portion of FET Channels more than the other portion. Position of gate pad defined the center point of the image without tilting the image as the geometry of the gate pads were parallel to each other. And there was no effect of gate pad bonding wire orientation because of the larger width of gate pads. For the GaN/AlGaNHEMT, the effect of Al mole fraction in AlGaN layer and the effect of gate oxide on the DC and low frequency noise characterization was studied. MOSHEMT with SiO2 improved the Id(on)/I d(off) ratio up to more than 8 orders, while it is only 10 times in conventional HEMT. It was shown that the gate leakage and isolation leakage suppression efficiency improved dramatically with the oxide. Subthreshold swing (SS) of MOS-HEMTs with different Al mole fraction (from 20% to 35%) vary slightly from 72 mV/decade to 79 mV/decade, but the conventional GaN/AlGaN HEMT showed SS of 2.4V/decade. Low frequency noise study revealed the difference in transport mechanism between HEMT and MOS-HEMTs. By using Carrier Number Fluctuation (CNF) model on the measured data, it was found that the noise is predominantly coming from the surface states. While generation-recombination is very prominent in conventional HEMT, it is very weak and insignificant in both MOS-HEMTs at much higher frequencies. This study reveals that very high number of surface states assisting the tunneling in schottky/AlGaN barrier is responsible for unusually high leakage and higher noise level in conventional HEMT. Leakage level is improved from mA/mm range for HEMT to pA/mm range for MOS-HEMTs. Leakage suppression improvement and minimization of noise level can be mainly attributed to high quality SiO2. Hooge's constant was in the order of 5-6x10-3 in MOS-HEMTs, which is 5x10 -2 for conventional HEMT indicating much lower noise level in the MOS-HEMTs. (Abstract shortened by ProQuest.).

Materials properties of hafnium and zirconium silicates: Metal interdiffusion and dopant penetration studies

NASA Astrophysics Data System (ADS)

Quevedo Lopez, Manuel Angel

Hafnium and Zirconium based gate dielectrics are considered potential candidates to replace SiO2 or SiON as the gate dielectric in CMOS processing. Furthermore, the addition of nitrogen into this pseudo-binary alloy has been shown to improve their thermal stability, electrical properties, and reduce dopant penetration. Because CMOS processing requires high temperature anneals (up to 1050°C), it is important to understand the diffusion properties of any metal associated with the gate dielectric in silicon at these temperatures. In addition, dopant penetration from the doped polysilicon gate into the Si channel at these temperatures must also be studied. Impurity outdiffusion (Hf, Zr) from the dielectric, or dopant (B, As, P) penetration through the dielectric into the channel region would likely result in deleterious effects upon the carrier mobility. In this dissertation extensive thermal stability studies of alternate gate dielectric candidates ZrSixOy and HfSixO y are presented. Dopant penetration studies from doped-polysilicon through HfSixOy and HfSixOyNz are also presented. Rutherford Backscattering Spectroscopy (RBS), Heavy Ion RBS (HI-RBS), X-ray Photoelectron Spectroscopy (XPS), High Resolution Transmission Electron Microscopy (HR-TEM), and Time of Flight and Dynamic Secondary Ion Mass Spectroscopy (ToF-SIMS, D-SIMS) methods were used to characterize these materials. The dopant diffusivity is calculated by modeling of the dopant profiles in the Si substrate. In this disseration is reported that Hf silicate films are more stable than Zr silicate films, from the metal interdiffusion point of view. On the other hand, dopant (B, As, and P) penetration is observed for HfSixO y films. However, the addition of nitrogen to the Hf - Si - O systems improves the dopant penetration properties of the resulting HfSi xOyNz films.

Effect of top gate potential on bias-stress for dual gate amorphous indium-gallium-zinc-oxide thin film transistor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chun, Minkyu; Um, Jae Gwang; Park, Min Sang

We report the abnormal behavior of the threshold voltage (V{sub TH}) shift under positive bias Temperature stress (PBTS) and negative bias temperature stress (NBTS) at top/bottom gate in dual gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). It is found that the PBTS at top gate shows negative transfer shift and NBTS shows positive transfer shift for both top and bottom gate sweep. The shift of bottom/top gate sweep is dominated by top gate bias (V{sub TG}), while bottom gate bias (V{sub BG}) is less effect than V{sub TG}. The X-ray photoelectron spectroscopy (XPS) depth profile provides the evidence of Inmore » metal diffusion to the top SiO{sub 2}/a-IGZO and also the existence of large amount of In{sup +} under positive top gate bias around top interfaces, thus negative transfer shift is observed. On the other hand, the formation of OH{sup −} at top interfaces under the stress of negative top gate bias shows negative transfer shift. The domination of V{sub TG} both on bottom/top gate sweep after PBTS/NBTS is obviously occurred due to thin active layer.« less

Hydrogen-induced reversible changes in drain current in Sc2O3/AlGaN/GaN high electron mobility transistors

NASA Astrophysics Data System (ADS)

Kang, B. S.; Mehandru, R.; Kim, S.; Ren, F.; Fitch, R. C.; Gillespie, J. K.; Moser, N.; Jessen, G.; Jenkins, T.; Dettmer, R.; Via, D.; Crespo, A.; Gila, B. P.; Abernathy, C. R.; Pearton, S. J.

2004-06-01

Pt contacted AlGaN/GaN high electron mobility transistors with Sc2O3 gate dielectrics show reversible changes in drain-source current upon exposure to H2-containing ambients, even at room temperature. The changes in current (as high as 3 mA for relatively low gate voltage and drain-source voltage) are approximately an order of magnitude larger than for Pt/GaN Schottky diodes and a factor of 5 larger than Sc2O3/AlGaN/GaN metal-oxide-semiconductor (MOS) diodes exposed under the same conditions. This shows the advantage of using a transistor structure in which the gain produces larger current changes upon exposure to hydrogen-containing ambients. The increase in current is the result of a decrease in effective barrier height of the MOS gate of 30-50 mV at 25 °C for 10% H2/90% N2 ambients relative to pure N2 and is due to catalytic dissociation of the H2 on the Pt contact, followed by diffusion to the Sc2O3/AlGaN interface.

Analysis of e-beam impact on the resist stack in e-beam lithography process

NASA Astrophysics Data System (ADS)

Indykeiwicz, K.; Paszkiewicz, B.

2013-07-01

Paper presents research on the sub-micron gate, AlGaN /GaN HEMT type transistors, fabrication by e-beam lithography and lift-off technique. The impact of the electron beam on the resists layer and the substrate was analyzed by MC method in Casino v3.2 software. The influence of technological process parameters on the metal structures resolution and quality for paths 100 nm, 300 nm and 500 nm wide and 20 μm long was studied. Qualitative simulation correspondences to the conducted experiments were obtained.

Anomalous electron collimation in HgTe quantum wells with inverted band structure.

PubMed

Zou, Y L; Zhang, L B; Song, J T

2013-02-20

We investigate the electron collimation behavior in HgTe quantum wells (QWs) with a magnetic-electric barrier induced by a ferromagnetic metal stripe. We find that electrons can transmit perfectly through the magnetic-electric barrier at some specific incidence angles. These angles can be controlled by the tuning gate voltage, local magnetic field and Fermi energy of incident electrons in QWs with appropriate barrier length. This collimation feature can be used to construct momentum filters in HgTe QWs and has potential application in nanodevices.

Volumetric measurement of human red blood cells by MOSFET-based microfluidic gate.

PubMed

Guo, Jinhong; Ai, Ye; Cheng, Yuanbing; Li, Chang Ming; Kang, Yuejun; Wang, Zhiming

2015-08-01

In this paper, we present a MOSFET-based (metal oxide semiconductor field-effect transistor) microfluidic gate to characterize the translocation of red blood cells (RBCs) through a gate. In the microfluidic system, the bias voltage modulated by the particles or biological cells is connected to the gate of MOSFET. The particles or cells can be detected by monitoring the MOSFET drain current instead of DC/AC-gating method across the electronic gate. Polystyrene particles with various standard sizes are utilized to calibrate the proposed device. Furthermore, RBCs from both adults and newborn blood sample are used to characterize the performance of the device in distinguishing the two types of RBCs. As compared to conventional DC/AC current modulation method, the proposed device demonstrates a higher sensitivity and is capable of being a promising platform for bioassay analysis. © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Electronic Properties and Device Applications of III-V Compound Semiconductor Native Oxides

DTIC Science & Technology

2006-03-02

MRD X-ray diffractometer with CuKa as the radiation source. The doping level in GaAs was meassured by electrochemical voltage (ECV) using an Accent... hard to prevent the gate metal from overlapping the mesa edge thus creating a parasitic leakage path to the channel42. To reduce the gate leakage

Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nylund, Gustav; Storm, Kristian; Torstensson, Henrik

2013-12-04

We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

Meta-gated channel for the discrete control of electromagnetic fields

NASA Astrophysics Data System (ADS)

Yang, Rui; Wang, Hui; Shi, Ayuan; Zhang, Aofang; Wang, Jing; Gao, Dongxing; Lei, Zhenya; Hu, Bowei

2016-08-01

We demonstrate the meta-gate controlled wave propagation through multiple metallic plates with properly devised sub-wavelength defect apertures. Different from using gradient refractive-index meta-materials or phase-discontinuity meta-surfaces to produce the discrepancy between the incident angle and the refractive angle, our technique redirects electromagnetic fields by setting-up discrete transmission gateways between adjacent meta-gates and creates the perfect channels for the wave propagation. Electromagnetic fields can be assigned in the response of the driving frequency of meta-gates with extraordinary transmissions and propagate simply relying on their pre-set locations as illustrated by the meta-gate guided electromagnetic fields travelling in the paths of the Silk-Road and the contour line of Xi'an city where the Silk-Road starts. The meta-gate concept, offering the feasibility of the discrete control of electromagnetic fields with gating routes, may pave an alternative way for precisely transmitting of signals and efficiently sharing of resource in the communication.

Structure of a prokaryotic sodium channel pore reveals essential gating elements and an outer ion binding site common to eukaryotic channels

PubMed Central

Shaya, David; Findeisen, Felix; Abderemane-Ali, Fayal; Arrigoni, Cristina; Wong, Stephanie; Nurva, Shailika Reddy; Loussouarn, Gildas; Minor, Daniel L.

2013-01-01

Voltage-gated sodium channels (NaVs) are central elements of cellular excitation. Notwithstanding advances from recent bacterial NaV (BacNaV) structures, key questions about gating and ion selectivity remain. Here, we present a closed conformation of NaVAe1p, a pore-only BacNaV derived from NaVAe1, a BacNaV from the arsenite oxidizer Alkalilimnicola ehrlichei found in Mono Lake, California, that provides insight into both fundamental properties. The structure reveals a pore domain in which the pore-lining S6 helix connects to a helical cytoplasmic tail. Electrophysiological studies of full-length BacNaVs show that two elements defined by the NaVAe1p structure, an S6 activation gate position and the cytoplasmic tail ‘neck’, are central to BacNaV gating. The structure also reveals the selectivity filter ion entry site, termed the ‘outer ion’ site. Comparison with mammalian voltage-gated calcium channel (CaV) selectivity filters, together with functional studies shows that this site forms a previously unknown determinant of CaV high affinity calcium binding. Our findings underscore commonalities between BacNaVs and eukaryotic voltage-gated channels and provide a framework for understanding gating and ion permeation in this superfamily. PMID:24120938

Structure of the voltage-gated K⁺ channel Eag1 reveals an alternative voltage sensing mechanism.

PubMed

Whicher, Jonathan R; MacKinnon, Roderick

2016-08-12

Voltage-gated potassium (K(v)) channels are gated by the movement of the transmembrane voltage sensor, which is coupled, through the helical S4-S5 linker, to the potassium pore. We determined the single-particle cryo-electron microscopy structure of mammalian K(v)10.1, or Eag1, bound to the channel inhibitor calmodulin, at 3.78 angstrom resolution. Unlike previous K(v) structures, the S4-S5 linker of Eag1 is a five-residue loop and the transmembrane segments are not domain swapped, which suggest an alternative mechanism of voltage-dependent gating. Additionally, the structure and position of the S4-S5 linker allow calmodulin to bind to the intracellular domains and to close the potassium pore, independent of voltage-sensor position. The structure reveals an alternative gating mechanism for K(v) channels and provides a template to further understand the gating properties of Eag1 and related channels. Copyright © 2016, American Association for the Advancement of Science.

Utility of Electrocardiography (ECG)-Gated Computed Tomography (CT) for Preoperative Evaluations of Thymic Epithelial Tumors.

PubMed

Ozawa, Yoshiyuki; Hara, Masaki; Nakagawa, Motoo; Shibamoto, Yuta

2016-01-01

Preoperative evaluation of invasion to the adjacent organs is important for the thymic epithelial tumors on CT. The purpose of our study was to evaluate the utility of electrocardiography (ECG)-gated CT for assessing thymic epithelial tumors with regard to the motion artifacts produced and the preoperative diagnostic accuracy of the technique. Forty thymic epithelial tumors (36 thymomas and 4 thymic carcinomas) were examined with ECG-gated contrast-enhanced CT using a dual source scanner. The scan delay after the contrast media injection was 30 s for the non-ECG-gated CT and 100 s for the ECG-gated CT. Two radiologists blindly evaluated both the non-ECG-gated and ECG-gated CT images for motion artifacts and determined whether the tumors had invaded adjacent structures (mediastinal fat, superior vena cava, brachiocephalic veins, aorta, pulmonary artery, pericardium, or lungs) on each image. Motion artifacts were evaluated using a 3-grade scale. Surgical and pathological findings were used as a reference standard for tumor invasion. Motion artifacts were significantly reduced for all structures by ECG gating ( p =0.0089 for the lungs and p <0.0001 for the other structures). Non-ECG-gated CT and ECG-gated CT demonstrated 79% and 95% accuracy, respectively, during assessments of pericardial invasion ( p =0.03). ECG-gated CT reduced the severity of motion artifacts and might be useful for preoperative assessment whether thymic epithelial tumors have invaded adjacent structures.

Utility of Electrocardiography (ECG)-Gated Computed Tomography (CT) for Preoperative Evaluations of Thymic Epithelial Tumors

PubMed Central

Ozawa, Yoshiyuki; Hara, Masaki; Nakagawa, Motoo; Shibamoto, Yuta

2016-01-01

Summary Background Preoperative evaluation of invasion to the adjacent organs is important for the thymic epithelial tumors on CT. The purpose of our study was to evaluate the utility of electrocardiography (ECG)-gated CT for assessing thymic epithelial tumors with regard to the motion artifacts produced and the preoperative diagnostic accuracy of the technique. Material/Methods Forty thymic epithelial tumors (36 thymomas and 4 thymic carcinomas) were examined with ECG-gated contrast-enhanced CT using a dual source scanner. The scan delay after the contrast media injection was 30 s for the non-ECG-gated CT and 100 s for the ECG-gated CT. Two radiologists blindly evaluated both the non-ECG-gated and ECG-gated CT images for motion artifacts and determined whether the tumors had invaded adjacent structures (mediastinal fat, superior vena cava, brachiocephalic veins, aorta, pulmonary artery, pericardium, or lungs) on each image. Motion artifacts were evaluated using a 3-grade scale. Surgical and pathological findings were used as a reference standard for tumor invasion. Results Motion artifacts were significantly reduced for all structures by ECG gating (p=0.0089 for the lungs and p<0.0001 for the other structures). Non-ECG-gated CT and ECG-gated CT demonstrated 79% and 95% accuracy, respectively, during assessments of pericardial invasion (p=0.03). Conclusions ECG-gated CT reduced the severity of motion artifacts and might be useful for preoperative assessment whether thymic epithelial tumors have invaded adjacent structures. PMID:27920842

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-03-01

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Trap density of GeNx/Ge interface fabricated by electron-cyclotron-resonance plasma nitridation

NASA Astrophysics Data System (ADS)

Fukuda, Yukio; Otani, Yohei; Toyota, Hiroshi; Ono, Toshiro

2011-07-01

We have investigated GeNx/Ge interface properties using Si3N4(7 nm)/GeNx(2 nm)/Ge metal-insulator-semiconductor structures fabricated by the plasma nitridation of Ge substrates using an electron-cyclotron-resonance-generated nitrogen plasma. The interface trap density (Dit) measured by the conductance method is found to be distributed symmetrically in the Ge band gap with a minimum Dit value lower than 3 × 1011 cm-2eV-1 near the midgap. This result may lead to the development of processes for the fabrication of p- and n-Ge Schottky-barrier (SB) source/drain metal-insulator-semiconductor field-effect transistors using chemically and thermally robust GeNx dielectrics as interlayers for SB source/drain contacts and high-κ gate dielectrics.

Characterization of equipment for shaping and imaging hadron minibeams

NASA Astrophysics Data System (ADS)

Pugatch, V.; Brons, S.; Campbell, M.; Kovalchuk, O.; Llopart, X.; Martínez-Rovira, I.; Momot, Ie.; Okhrimenko, O.; Prezado, Y.; Sorokin, Yu.

2017-11-01

For the feasibility studies of spatially fractionated hadron therapy prototypes of the equipment for hadron minibeams shaping and monitoring have been designed, built and tested. The collimators design was based on Monte Carlo simulations (Gate v.6.2). Slit and matrix collimators were used for minibeams shaping. Gafchromic films, micropixel detectors Timepix in a hybrid as well as metal mode were tested for measuring hadrons intensity distribution in minibeams. An overall beam profile was measured by the metal microstrip detector. The performance of a mini-beams shaping and monitoring equipment was characterized exploring low energy protons at the KINR Tandem generator as well as high energy carbon and oxygen ion beams at HIT (Heidelberg). The results demonstrate reliable performance of the tested equipment for shaping and imaging hadron mini-beam structures.

Large Area CVD MoS2 RF transistors with GHz performance

NASA Astrophysics Data System (ADS)

Nagavalli Yogeesh, Maruthi; Sanne, Atresh; Park, Saungeun; Akinwade, Deji; Banerjee, Sanjay

Molybdenum disulfide (MoS2) is a 2D semiconductor in the family of transition metal dichalcogenides (TMDs). Its single layer direct bandgap of 1.8 eV allows for high ION/IOFF metal-oxide semiconducting field-effect transistors (FETs). More relevant for radio frequency (RF) wireless applications, theoretical studies predict MoS2 to have saturation velocities, vsat >3×106 cm/s. Facilitated by cm-scale CVD MoS2, here we design and fabricate both top-gated and embedded gate short channel MoS2 RF transistors, and provide a systematic comparison of channel length scaling, extrinsic doping from oxygen-deficient dielectrics, and a gate-first gate-last process flow. The intrinsic fT (fmax) obtained from the embedded gate transistors shows 3X (2X) improvement over top-gated CVD MoS2 RF FETs, and the largest high-field saturation velocity, vsat = 1.88 ×106 cm/s, in MoS2 reported so far. The gate-first approach, offers enhancement mode operation, ION/IOFF ratio of 10, 8< and the highest reported transconductance (gm) of 70 μS/ μm. By manipulating the interfacial oxygen vacancies in atomic layer deposited (ALD) HfO2-x we are able to achieve 2X current density over stoichiometric Al2O3. We demonstrate a common-source (CS) amplifier with voltage gain of 14 dB and an active frequency mixer with conversion gain of -15 dB. Our results of gigahertz frequency performance as well as analog circuit operation show that large area CVD MoS2 may be suitable for industrial-scale electronic applications.

High quality factor graphene varactors for wireless sensing applications

NASA Astrophysics Data System (ADS)

Koester, Steven J.

2011-10-01

A graphene wireless sensor concept is described. By utilizing thin gate dielectrics, the capacitance in a metal-insulator-graphene structure varies with charge concentration through the quantum capacitance effect. Simulations using realistic structural and transport parameters predict quality factors, Q, >60 at 1 GHz. When placed in series with an ideal inductor, a resonant frequency tuning ratio of 25% (54%) is predicted for sense charge densities ranging from 0.32 to 1.6 μC/cm2 at an equivalent oxide thickness of 2.0 nm (0.5 nm). The resonant frequency has a temperature sensitivity, df/dT, less than 0.025%/K for sense charge densities >0.32 μC/cm2.

Reconfigurable all-optical NOT, XOR, and NOR logic gates based on two dimensional photonic crystals

NASA Astrophysics Data System (ADS)

Parandin, Fariborz; Malmir, M. Reza; Naseri, Mosayeb; Zahedi, Abdulhamid

2018-01-01

Photonic crystals can be considered as one of the most important basis for designing optical devices. In this research, using two-dimensional photonic crystals with triangular lattices, ultra-compact logic gates are designed and simulated. The intended structure has the capability to be used as three logical gates (NOT, XOR, and NOR). The designed structures not only have characteristics of small dimensions which make them suitable for integrated optical circuits, but also exhibit very low power transfer delay which makes it possible to design high speed gates. On comparison with the previous works, our simulations show that at a wavelength of 1.55 μm , the gates indicate a time delay of about 0.1 ps and the contrast ratio for the XOR gate is about 30 dB, i.e., the proposed structures are more applicable in designing low error optical logic gates.

Stress Characterization of 4H-SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) using Raman Spectroscopy and the Finite Element Method.

PubMed

Yoshikawa, Masanobu; Kosaka, Kenichi; Seki, Hirohumi; Kimoto, Tsunenobu

2016-07-01

We measured the depolarized and polarized Raman spectra of a 4H-SiC metal-oxide-semiconductor field-effect transistor (MOSFET) and found that compressive stress of approximately 20 MPa occurs under the source and gate electrodes and tensile stress of approximately 10 MPa occurs between the source and gate electrodes. The experimental result was in close agreement with the result obtained by calculation using the finite element method (FEM). A combination of Raman spectroscopy and FEM provides much data on the stresses in 4H-SiC MOSFET. © The Author(s) 2016.

Extracting current induced spins from topological insulator wires: gate control of extracted spin polarization

NASA Astrophysics Data System (ADS)

Adagideli, Inanc

Spin-momentum locking featured by the surface states of 3D topological insulators (TIs) allows electrical generation of spin accumulations and provides a new avenue for spintronics applications. In this work, we explore how to extract electrically induced spins from topological insulator surfaces, where they are generated into topologically trivial metallic leads that are commonly used in conventional electronic devices. We first focus on an effective surface theory of current induced spin accumulation in topological insulators. Then we focus on a particular geometry: a metallic pocket attached to top and side faces of a 3D topological insulator quantum wire with a rectangular cross section, and explore spin extraction into topologically non-trivial materials. We find surprisingly that the doping in and/or a gate voltage applied to the metallic side pocket can control the direction of the extracted spin polarization opening the possibility for a spin transistor operation of these device geometries. We also perform numerical simulations of nonequilibrium spin accumulations generated by an applied bias in the same geometry and demonstrate the spin polarization control via applied gate voltages. Work funded by TUBITAK Grant No 114F163.

Probing charge transfer during metal-insulator transitions in graphene-LaAlO3/SrTiO3 systems

NASA Astrophysics Data System (ADS)

Aliaj, I.; Sambri, A.; Miseikis, V.; Stornaiuolo, D.; di Gennaro, E.; Coletti, C.; Pellegrini, V.; Miletto Granozio, F.; Roddaro, S.

2018-06-01

Two-dimensional electron systems (2DESs) at the interface between LaAlO3 (LAO) and SrTiO3 (STO) perovskite oxides display a wide class of tunable phenomena ranging from superconductivity to metal-insulator transitions. Most of these effects are strongly sensitive to surface physics and often involve charge transfer mechanisms, which are, however, hard to detect. In this work, we realize hybrid field-effect devices where graphene is used to modulate the transport properties of the LAO/STO 2DES. Different from a conventional gate, graphene is semimetallic and allows us to probe charge transfer with the oxide structure underneath the field-effect electrode. In LAO/STO samples with a low initial carrier density, graphene-covered regions turn insulating when the temperature is lowered to 3 K, but conduction can be restored in the oxide structure by increasing the temperature or by field effect. The evolution of graphene's electron density is found to be inconsistent with a depletion of LAO/STO, but it rather points to a localization of interfacial carriers in the oxide structure.

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications.

PubMed

Jeon, Sanghun; Park, Sungho; Song, Ihun; Hur, Ji-Hyun; Park, Jaechul; Kim, Hojung; Kim, Sunil; Kim, Sangwook; Yin, Huaxiang; Chung, U-In; Lee, Eunha; Kim, Changjung

2011-01-01

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.

Construction of a fuzzy and Boolean logic gates based on DNA.

PubMed

Zadegan, Reza M; Jepsen, Mette D E; Hildebrandt, Lasse L; Birkedal, Victoria; Kjems, Jørgen

2015-04-17

Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive DNA locks on one DNA origami box structure enabled fuzzy logical operation that allows biosensing of complex molecular signals. Integrating logic gates with DNA origami systems opens a vast avenue to applications in the fields of nanomedicine for diagnostics and therapeutics. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Design of Low-Noise Output Amplifiers for P-channel Charge-Coupled Devices Fabricated on High-Resistivity Silicon

DOE Office of Scientific and Technical Information (OSTI.GOV)

Haque, S; Frost, F Dion R.; Groulx, R

2011-12-22

We describe the design and optimization of low-noise, single-stage output amplifiers for p-channel charge-coupled devices (CCDs) used for scientific applications in astronomy and other fields. The CCDs are fabricated on high-resistivity, 4000–5000 -cm, n-type silicon substrates. Single-stage amplifiers with different output structure designs and technologies have been characterized. The standard output amplifier is designed with an n{sup +} polysilicon gate that has a metal connection to the sense node. In an effort to lower the output amplifier readout noise by minimizing the capacitance seen at the sense node, buried-contact technology has been investigated. In this case, the output transistor hasmore » a p{sup +} polysilicon gate that connects directly to the p{sup +} sense node. Output structures with buried-contact areas as small as 2 μm × 2 μm are characterized. In addition, the geometry of the source-follower transistor was varied, and we report test results on the conversion gain and noise of the various amplifier structures. By use of buried-contact technology, better amplifier geometry, optimization of the amplifier biases and improvements in the test electronics design, we obtain a 45% reduction in noise, corresponding to 1.7 e{sup -} rms at 70 kpixels/sec.« less

Effect of atomic-arrangement matching on La{sub 2}O{sub 3}/Ge heterostructures for epitaxial high-k-gate-stacks

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kanashima, T., E-mail: kanashima@ee.es.osaka-u.ac.jp; Zenitaka, M.; Kajihara, Y.

2015-12-14

We demonstrate a high-quality La{sub 2}O{sub 3} layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La{sub 2}O{sub 3}(001) and Ge(111). Structural analyses reveal that (001)-oriented La{sub 2}O{sub 3} layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La{sub 2}O{sub 3} layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La{sub 2}O{sub 3}/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we findmore » that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO{sub 2} monolayer. We discuss a model of the interfacial structure between La{sub 2}O{sub 3} and Ge(111) and comment on the C-V characteristics.« less

Top gating control of superconductivity at the LaAlO3 /SrTiO3 interfaces

NASA Astrophysics Data System (ADS)

Jouan, Alexis; Hurand, Simon; Feuillet-Palma, Cheryl; Singh, Gyanendra; Lesueur, Jerome; Bergeal, Nicolas; Lesne, Edouard; Reyren, Nicolas

2015-03-01

Transition metal oxides display a great variety of quantum electronic behaviors. Epitaxial interfaces involving such materials give a unique opportunity to engineer artificial materials where new electronic orders take place. It has been shown that a superconducting two-dimensional electron gas could form at the interface of two insulators such as LaAlO3 and SrTiO3 [1], or LaTiO3 and SrTiO3 [2]. An important feature of these interfaces lies in the possibility to control their electronic properties, including superconductivity and spin-orbit coupling (SOC) with field effect [3-5]. However, experiments have been performed almost exclusively with a metallic gate on the back of the sample. In this presentation, we will report on the realization of a top-gated LaAlO3/SrTiO3 device whose physical properties, including superconductivity and SOC, can be tuned over a wide range of electrostatic doping. In particular, we will present a phase diagram of the interface and compare the effect of the top-gate and back-gate. Finally, we will discuss the field-effect modulation of the Rashba spin-splitting energy extracted from the analysis of magneto-transport measurements. Our result paves the way for the realization of mesoscopic devices where both superconductivity and SOC can be tuned locally.

Polycrystalline diamond RF MOSFET with MoO3 gate dielectric

NASA Astrophysics Data System (ADS)

Ren, Zeyang; Zhang, Jinfeng; Zhang, Jincheng; Zhang, Chunfu; Chen, Dazheng; Quan, Rudai; Yang, Jiayin; Lin, Zhiyu; Hao, Yue

2017-12-01

We report the radio frequency characteristics of the diamond metal-oxide-semiconductor field effect transistor with MoO3 gate dielectric for the first time. The device with 2-μm gate length was fabricated on high quality polycrystalline diamond. The maximum drain current of 150 mA/mm at VGS = -5 V and the maximum transconductance of 27 mS/mm were achieved. The extrinsic cutoff frequency of 1.2 GHz and the maximum oscillation frequency of 1.9 GHz have been measured. The moderate frequency characteristics are attributed to the moderate transconductance limited by the series resistance along the channel. We expect that the frequency characteristics of the device can be improved by increasing the magnitude of gm, or fundamentally decreasing the gate-controlled channel resistance and series resistance along the channel, and down-scaling the gate length.

Gallium arsenide processing for gate array logic

NASA Technical Reports Server (NTRS)

Cole, Eric D.

1989-01-01

The development of a reliable and reproducible GaAs process was initiated for applications in gate array logic. Gallium Arsenide is an extremely important material for high speed electronic applications in both digital and analog circuits since its electron mobility is 3 to 5 times that of silicon, this allows for faster switching times for devices fabricated with it. Unfortunately GaAs is an extremely difficult material to process with respect to silicon and since it includes the arsenic component GaAs can be quite dangerous (toxic) especially during some heating steps. The first stage of the research was directed at developing a simple process to produce GaAs MESFETs. The MESFET (MEtal Semiconductor Field Effect Transistor) is the most useful, practical and simple active device which can be fabricated in GaAs. It utilizes an ohmic source and drain contact separated by a Schottky gate. The gate width is typically a few microns. Several process steps were required to produce a good working device including ion implantation, photolithography, thermal annealing, and metal deposition. A process was designed to reduce the total number of steps to a minimum so as to reduce possible errors. The first run produced no good devices. The problem occurred during an aluminum etch step while defining the gate contacts. It was found that the chemical etchant attacked the GaAs causing trenching and subsequent severing of the active gate region from the rest of the device. Thus all devices appeared as open circuits. This problem is being corrected and since it was the last step in the process correction should be successful. The second planned stage involves the circuit assembly of the discrete MESFETs into logic gates for test and analysis. Finally the third stage is to incorporate the designed process with the tested circuit in a layout that would produce the gate array as a GaAs integrated circuit.

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Structure of a prokaryotic sodium channel pore reveals essential gating elements and an outer ion binding site common to eukaryotic channels.

PubMed

Shaya, David; Findeisen, Felix; Abderemane-Ali, Fayal; Arrigoni, Cristina; Wong, Stephanie; Nurva, Shailika Reddy; Loussouarn, Gildas; Minor, Daniel L

2014-01-23

Voltage-gated sodium channels (NaVs) are central elements of cellular excitation. Notwithstanding advances from recent bacterial NaV (BacNaV) structures, key questions about gating and ion selectivity remain. Here, we present a closed conformation of NaVAe1p, a pore-only BacNaV derived from NaVAe1, a BacNaV from the arsenite oxidizer Alkalilimnicola ehrlichei found in Mono Lake, California, that provides insight into both fundamental properties. The structure reveals a pore domain in which the pore-lining S6 helix connects to a helical cytoplasmic tail. Electrophysiological studies of full-length BacNaVs show that two elements defined by the NaVAe1p structure, an S6 activation gate position and the cytoplasmic tail "neck", are central to BacNaV gating. The structure also reveals the selectivity filter ion entry site, termed the "outer ion" site. Comparison with mammalian voltage-gated calcium channel (CaV) selectivity filters, together with functional studies, shows that this site forms a previously unknown determinant of CaV high-affinity calcium binding. Our findings underscore commonalities between BacNaVs and eukaryotic voltage-gated channels and provide a framework for understanding gating and ion permeation in this superfamily. © 2013. Published by Elsevier Ltd. All rights reserved.

Correlation of interface states/border traps and threshold voltage shift on AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Tian-Li, E-mail: Tian-Li.Wu@imec.be; Groeseneken, Guido; Department of Electrical Engineering, KU Leuven, Leuven

2015-08-31

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-g{sub m}), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si{sub 3}N{sub 4}, Rapid Thermal Chemical Vapor Deposition Si{sub 3}N{sub 4}, and Atomic Layer Deposition (ALD) Al{sub 2}O{sub 3}) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (D{sub it}), the amount of border traps, and the threshold voltage (V{sub TH}) shift during a positive gate bias stress can be obtained. The results show that the V{sub TH} shift during a positive gate bias stress ismore » highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the V{sub TH} shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract D{sub it} needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the g{sub m} dispersion commonly attributed to border traps might be influenced by interface states.« less

Low dislocation density InAlN/AlN/GaN heterostructures grown on GaN substrates and the effects on gate leakage characteristics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kotani, Junji, E-mail: kotani.junji-01@jp.fujitsu.com; Yamada, Atsushi; Ishiguro, Tetsuro

2016-04-11

This paper reports on the electrical characterization of Ni/Au Schottky diodes fabricated on InAlN high-electron-mobility transistor (HEMT) structures grown on low dislocation density free-standing GaN substrates. InAlN HEMT structures were grown on sapphire and GaN substrates by metal-organic vapor phase epitaxy, and the effects of threading dislocation density on the leakage characteristics of Ni/Au Schottky diodes were investigated. Threading dislocation densities were determined to be 1.8 × 10{sup 4 }cm{sup −2} and 1.2 × 10{sup 9 }cm{sup −2} by the cathodoluminescence measurement for the HEMT structures grown on GaN and sapphire substrates, respectively. Leakage characteristics of Ni/Au Schottky diodes were compared between the two samples, andmore » a reduction of the leakage current of about three to four orders of magnitude was observed in the forward bias region. For the high reverse bias region, however, no significant improvement was confirmed. We believe that the leakage current in the low bias region is governed by a dislocation-related Frenkel–Poole emission, and the leakage current in the high reverse bias region originates from field emission due to the large internal electric field in the InAlN barrier layer. Our results demonstrated that the reduction of dislocation density is effective in reducing leakage current in the low bias region. At the same time, it was also revealed that another approach will be needed, for instance, band modulation by impurity doping and insertion of insulating layers beneath the gate electrodes for a substantial reduction of the gate leakage current.« less

Atomic layer deposition of sub-10 nm high-K gate dielectrics on top-gated MoS2 transistors without surface functionalization

NASA Astrophysics Data System (ADS)

Lin, Yu-Shu; Cheng, Po-Hsien; Huang, Kuei-Wen; Lin, Hsin-Chih; Chen, Miin-Jang

2018-06-01

Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al2O3 high-K gate dielectrics on MoS2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al2O3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al2O3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al2O3 nucleation layer on MoS2. With the high-quality sub-10 nm Al2O3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS2 transistors.

Transport Properties of Anatase-TiO2 Polycrystalline-Thin-Film Field-Effect Transistors with Electrolyte Gate Layers

NASA Astrophysics Data System (ADS)

Horita, Ryohei; Ohtani, Kyosuke; Kai, Takahiro; Murao, Yusuke; Nishida, Hiroya; Toya, Taku; Seo, Kentaro; Sakai, Mio; Okuda, Tetsuji

2013-11-01

We have fabricated anatase-TiO2 polycrystalline-thin-film field-effect transistors (FETs) with poly(vinyl alcohol) (PVA), ion-liquid (IL), and ion-gel (IG) gate layers, and have tried to improve the response to gate voltage by varying the concentration of mobile ions in these electrolyte gate layers. The increase in the concentration of mobile ions by doping NaOH into the PVA gate layer or reducing the gelator in the IG gate layer markedly increases the drain-source current and reduces the driving gate voltage, which show that the mobile ions in the PVA, IL, and IG gate layers cause the formation of electric double layers (EDLs), which act as nanogap capacitors. In these TiO2-EDL-FETs, the slow formation of EDLs and the oxidation reaction at the interface between the surface of the TiO2 film and the electrolytes cause unideal FET properties. In the optimized IL and IG TiO2-EDL-FETs, the driving gate voltage is less than 1 V and the ON/OFF ratios of the transfer characteristics are about 1×104 at RT, and the nearly metallic state is realized at the interface purely by applying a gate voltage.

Sub-0.5 V Highly Stable Aqueous Salt Gated Metal Oxide Electronics

PubMed Central

Park, Sungjun; Lee, SeYeong; Kim, Chang-Hyun; Lee, Ilseop; Lee, Won-June; Kim, Sohee; Lee, Byung-Geun; Jang, Jae-Hyung; Yoon, Myung-Han

2015-01-01

Recently, growing interest in implantable bionics and biochemical sensors spurred the research for developing non-conventional electronics with excellent device characteristics at low operation voltages and prolonged device stability under physiological conditions. Herein, we report high-performance aqueous electrolyte-gated thin-film transistors using a sol-gel amorphous metal oxide semiconductor and aqueous electrolyte dielectrics based on small ionic salts. The proper selection of channel material (i.e., indium-gallium-zinc-oxide) and precautious passivation of non-channel areas enabled the development of simple but highly stable metal oxide transistors manifested by low operation voltages within 0.5 V, high transconductance of ~1.0 mS, large current on-off ratios over 107, and fast inverter responses up to several hundred hertz without device degradation even in physiologically-relevant ionic solutions. In conjunction with excellent transistor characteristics, investigation of the electrochemical nature of the metal oxide-electrolyte interface may contribute to the development of a viable bio-electronic platform directly interfacing with biological entities in vivo. PMID:26271456

A modular design of molecular qubits to implement universal quantum gates

PubMed Central

Ferrando-Soria, Jesús; Moreno Pineda, Eufemio; Chiesa, Alessandro; Fernandez, Antonio; Magee, Samantha A.; Carretta, Stefano; Santini, Paolo; Vitorica-Yrezabal, Iñigo J.; Tuna, Floriana; Timco, Grigore A.; McInnes, Eric J.L.; Winpenny, Richard E.P.

2016-01-01

The physical implementation of quantum information processing relies on individual modules—qubits—and operations that modify such modules either individually or in groups—quantum gates. Two examples of gates that entangle pairs of qubits are the controlled NOT-gate (CNOT) gate, which flips the state of one qubit depending on the state of another, and the gate that brings a two-qubit product state into a superposition involving partially swapping the qubit states. Here we show that through supramolecular chemistry a single simple module, molecular {Cr7Ni} rings, which act as the qubits, can be assembled into structures suitable for either the CNOT or gate by choice of linker, and we characterize these structures by electron spin resonance spectroscopy. We introduce two schemes for implementing such gates with these supramolecular assemblies and perform detailed simulations, based on the measured parameters including decoherence, to demonstrate how the gates would operate. PMID:27109358

A localized interaction surface for voltage-sensing domains on the pore domain of a K+ channel.

PubMed

Li-Smerin, Y; Hackos, D H; Swartz, K J

2000-02-01

Voltage-gated K+ channels contain a central pore domain and four surrounding voltage-sensing domains. How and where changes in the structure of the voltage-sensing domains couple to the pore domain so as to gate ion conduction is not understood. The crystal structure of KcsA, a bacterial K+ channel homologous to the pore domain of voltage-gated K+ channels, provides a starting point for addressing this question. Guided by this structure, we used tryptophan-scanning mutagenesis on the transmembrane shell of the pore domain in the Shaker voltage-gated K+ channel to localize potential protein-protein and protein-lipid interfaces. Some mutants cause only minor changes in gating and when mapped onto the KcsA structure cluster away from the interface between pore domain subunits. In contrast, mutants producing large changes in gating tend to cluster near this interface. These results imply that voltage-sensing domains interact with localized regions near the interface between adjacent pore domain subunits.

Designed topology and site-selective metal composition in tetranuclear [MM'...M'M] linear complexes.

PubMed

Barrios, Leoní A; Aguilà, David; Roubeau, Olivier; Gamez, Patrick; Ribas-Ariño, Jordi; Teat, Simon J; Aromí, Guillem

2009-10-26

The ligand 1,3-bis[3-oxo-3-(2-hydroxyphenyl)propionyl]benzene (H(4)L), designed to align transition metals into tetranuclear linear molecules, reacts with M(II) salts (M=Ni, Co, Cu) to yield complexes with the expected [MMMM] topology. The novel complexes [Co(4)L(2)(py)(6)] (2; py=pyridine) and [Na(py)(2)][Cu(4)L(2)(py)(4)](ClO(4)) (3) have been crystallographically characterised. The metal sites in complexes 2 and 3, together with previously characterised [Ni(4)L(2)(py)(6)] (1), favour different coordination geometries. These have been exploited for the deliberate synthesis of the heterometallic complex [Cu(2)Ni(2)L(2)(py)(6)] (4). Complexes 1, 2, 3 and 4 exhibit antiferromagnetic interactions between pairs of metals within each cluster, leading to S=0 spin ground states, except for the latter cluster, which features two quasi-independent S=1/2 moieties within the molecule. Complex 4 gathers the structural and physical conditions, thus allowing it to be considered as prototype of a two-qbit quantum gate.

Analysis of stability improvement in ZnO thin film transistor with dual-gate structure under negative bias stress

NASA Astrophysics Data System (ADS)

Yun, Ho-Jin; Kim, Young-Su; Jeong, Kwang-Seok; Kim, Yu-Mi; Yang, Seung-dong; Lee, Hi-Deok; Lee, Ga-Won

2014-01-01

In this study, we fabricated dual-gate zinc oxide thin film transistors (ZnO TFTs) without additional processes and analyzed their stability characteristics under a negative gate bias stress (NBS) by comparison with conventional bottom-gate structures. The dual-gate device shows superior electrical parameters, such as subthreshold swing (SS) and on/off current ratio. NBS of VGS = -20 V with VDS = 0 was applied, resulting in a negative threshold voltage (Vth) shift. After applying stress for 1000 s, the Vth shift is 0.60 V in a dual-gate ZnO TFT, while the Vth shift is 2.52 V in a bottom-gate ZnO TFT. The stress immunity of the dual-gate device is caused by the change in field distribution in the ZnO channel by adding another gate as the technology computer aided design (TCAD) simulation shows. Additionally, in flicker noise analysis, a lower noise level with a different mechanism is observed in the dual-gate structure. This can be explained by the top side of the ZnO film having a larger crystal and fewer grain boundaries than the bottom side, which is revealed by the enhanced SS and XRD results. Therefore, the improved stability of the dual-gate ZnO TFT is greatly related to the E-field cancellation effect and crystal quality of the ZnO film.

1/f noise in metallic and semiconducting carbon nanotubes

NASA Astrophysics Data System (ADS)

Reza, Shahed; Huynh, Quyen T.; Bosman, Gijs; Sippel-Oakley, Jennifer; Rinzler, Andrew G.

2006-11-01

The charge transport and noise properties of three terminal, gated devices containing multiple single-wall metallic and semiconducting carbon nanotubes were measured at room temperature. Applying a high voltage pulsed bias at the drain terminal the metallic tubes were ablated sequentially, enabling the separation of measured conductance and 1/f noise into metallic and semiconducting nanotube contributions. The relative low frequency excess noise of the metallic tubes was observed to be two orders of magnitude lower than that of the semiconductor tubes.

Voltage-Gated Potassium Channels: A Structural Examination of Selectivity and Gating

PubMed Central

Kim, Dorothy M.; Nimigean, Crina M.

2016-01-01

Voltage-gated potassium channels play a fundamental role in the generation and propagation of the action potential. The discovery of these channels began with predictions made by early pioneers, and has culminated in their extensive functional and structural characterization by electrophysiological, spectroscopic, and crystallographic studies. With the aid of a variety of crystal structures of these channels, a highly detailed picture emerges of how the voltage-sensing domain reports changes in the membrane electric field and couples this to conformational changes in the activation gate. In addition, high-resolution structural and functional studies of K+ channel pores, such as KcsA and MthK, offer a comprehensive picture on how selectivity is achieved in K+ channels. Here, we illustrate the remarkable features of voltage-gated potassium channels and explain the mechanisms used by these machines with experimental data. PMID:27141052

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Dual field effects in electrolyte-gated spinel ferrite: electrostatic carrier doping and redox reactions.

PubMed

Ichimura, Takashi; Fujiwara, Kohei; Tanaka, Hidekazu

2014-07-24

Controlling the electronic properties of functional oxide materials via external electric fields has attracted increasing attention as a key technology for next-generation electronics. For transition-metal oxides with metallic carrier densities, the electric-field effect with ionic liquid electrolytes has been widely used because of the enormous carrier doping capabilities. The gate-induced redox reactions revealed by recent investigations have, however, highlighted the complex nature of the electric-field effect. Here, we use the gate-induced conductance modulation of spinel ZnxFe₃₋xO₄ to demonstrate the dual contributions of volatile and non-volatile field effects arising from electronic carrier doping and redox reactions. These two contributions are found to change in opposite senses depending on the Zn content x; virtual electronic and chemical field effects are observed at appropriate Zn compositions. The tuning of field-effect characteristics via composition engineering should be extremely useful for fabricating high-performance oxide field-effect devices.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Large-scale complementary macroelectronics using hybrid integration of carbon nanotubes and IGZO thin-film transistors.

PubMed

Chen, Haitian; Cao, Yu; Zhang, Jialu; Zhou, Chongwu

2014-06-13

Carbon nanotubes and metal oxide semiconductors have emerged as important materials for p-type and n-type thin-film transistors, respectively; however, realizing sophisticated macroelectronics operating in complementary mode has been challenging due to the difficulty in making n-type carbon nanotube transistors and p-type metal oxide transistors. Here we report a hybrid integration of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors to achieve large-scale (>1,000 transistors for 501-stage ring oscillators) complementary macroelectronic circuits on both rigid and flexible substrates. This approach of hybrid integration allows us to combine the strength of p-type carbon nanotube and n-type indium-gallium-zinc-oxide thin-film transistors, and offers high device yield and low device variation. Based on this approach, we report the successful demonstration of various logic gates (inverter, NAND and NOR gates), ring oscillators (from 51 stages to 501 stages) and dynamic logic circuits (dynamic inverter, NAND and NOR gates).

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Electron Doping of Ultrathin Black Phosphorus with Cu Adatoms.

PubMed

Koenig, Steven P; Doganov, Rostislav A; Seixas, Leandro; Carvalho, Alexandra; Tan, Jun You; Watanabe, Kenji; Taniguchi, Takashi; Yakovlev, Nikolai; Castro Neto, Antonio H; Özyilmaz, Barbaros

2016-04-13

Few-layer black phosphorus is a monatomic two-dimensional crystal with a direct band gap that has high carrier mobility for both holes and electrons. Similarly to other layered atomic crystals, like graphene or layered transition metal dichalcogenides, the transport behavior of few-layer black phosphorus is sensitive to surface impurities, adsorbates, and adatoms. Here we study the effect of Cu adatoms onto few-layer black phosphorus by characterizing few-layer black phosphorus field effect devices and by performing first-principles calculations. We find that the addition of Cu adatoms can be used to controllably n-dope few layer black phosphorus, thereby lowering the threshold voltage for n-type conduction without degrading the transport properties. We demonstrate a scalable 2D material-based complementary inverter which utilizes a boron nitride gate dielectric, a graphite gate, and a single bP crystal for both the p- and n-channels. The inverter operates at matched input and output voltages, exhibits a gain of 46, and does not require different contact metals or local electrostatic gating.

VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate

NASA Astrophysics Data System (ADS)

Ahmad, Nabihah; Hakimi Mokhtar, Ahmad; Othman, Nurmiza binti; Fhong Soon, Chin; Rahman, Ab Al Hadi Ab

2017-08-01

Multiplier is one of the essential component in the digital world such as in digital signal processing, microprocessor, quantum computing and widely used in arithmetic unit. Due to the complexity of the multiplier, tendency of errors are very high. This paper aimed to design a 2×2 bit Fault Tolerance Multiplier based on Reversible logic gate with low power consumption and high performance. This design have been implemented using 90nm Complemetary Metal Oxide Semiconductor (CMOS) technology in Synopsys Electronic Design Automation (EDA) Tools. Implementation of the multiplier architecture is by using the reversible logic gates. The fault tolerance multiplier used the combination of three reversible logic gate which are Double Feynman gate (F2G), New Fault Tolerance (NFT) gate and Islam Gate (IG) with the area of 160μm x 420.3μm (67.25 mm2). This design achieved a low power consumption of 122.85μW and propagation delay of 16.99ns. The fault tolerance multiplier proposed achieved a low power consumption and high performance which suitable for application of modern computing as it has a fault tolerance capabilities.

Voltage gating by molecular subunits of Na+ and K+ ion channels: higher-dimensional cubic kinetics, rate constants, and temperature

PubMed Central

2015-01-01

The structural similarity between the primary molecules of voltage-gated Na and K channels (alpha subunits) and activation gating in the Hodgkin-Huxley model is brought into full agreement by increasing the model's sodium kinetics to fourth order (m3 → m4). Both structures then virtually imply activation gating by four independent subprocesses acting in parallel. The kinetics coalesce in four-dimensional (4D) cubic diagrams (16 states, 32 reversible transitions) that show the structure to be highly failure resistant against significant partial loss of gating function. Rate constants, as fitted in phase plot data of retinal ganglion cell excitation, reflect the molecular nature of the gating transitions. Additional dimensions (6D cubic diagrams) accommodate kinetically coupled sodium inactivation and gating processes associated with beta subunits. The gating transitions of coupled sodium inactivation appear to be thermodynamically irreversible; response to dielectric surface charges (capacitive displacement) provides a potential energy source for those transitions and yields highly energy-efficient excitation. A comparison of temperature responses of the squid giant axon (apparently Arrhenius) and mammalian channel gating yields kinetic Q10 = 2.2 for alpha unit gating, whose transitions are rate-limiting at mammalian temperatures; beta unit kinetic Q10 = 14 reproduces the observed non-Arrhenius deviation of mammalian gating at low temperatures; the Q10 of sodium inactivation gating matches the rate-limiting component of activation gating at all temperatures. The model kinetics reproduce the physiologically large frequency range for repetitive firing in ganglion cells and the physiologically observed strong temperature dependence of recovery from inactivation. PMID:25867741

Study of proton radiation effects among diamond and rectangular gate MOSFET layouts

NASA Astrophysics Data System (ADS)

Seixas, L. E., Jr.; Finco, S.; Silveira, M. A. G.; Medina, N. H.; Gimenez, S. P.

2017-01-01

This paper describes an experimental comparative study of proton ionizing radiation effects between the metal-oxide-semiconductor (MOS) Field Effect Transistors (MOSFETs) implemented with hexagonal gate shapes (diamond) and their respective counterparts designed with the classical rectangular ones, regarding the same gate areas, channel widths and geometrical ratios (W/L). The devices were manufactured by using the 350 nm bulk complementary MOS (CMOS) integrated circuits technology. The diamond MOSFET with α angles higher or equal to 90° tends to present a smaller vulnerability to the high doses ionizing radiation than those observed in the typical rectangular MOSFET counterparts.

Enhanced performance of amorphous In-Ga-Zn-O thin-film transistors using different metals for source/drain electrodes

NASA Astrophysics Data System (ADS)

Pyo, Ju-Young; Cho, Won-Ju

2017-09-01

In this paper, we propose an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with off-planed source/drain electrodes. We applied different metals for the source/drain electrodes with Ni and Ti to control the work function as high and low. When we measured the configuration of Ni to drain and source to Ti, the a-IGZO TFT showed increased driving current, decreased leakage current, a high on/off current ratio, low subthreshold swing, and high mobility. In addition, we conducted a reliability test with a gate bias stress test at various temperatures. The results of the reliability test showed the Ni drain and Ti drain had an equivalent effective energy barrier height. Thus, we confirmed that the proposed off-planed structure improved the electrical characteristics of the fabricated devices without any degradation of characteristics. Through the a-IGZO TFT with different source/drain electrode metal engineering, we realized high-performance TFTs for next-generation display devices.

Design of a size-efficient tunable metamaterial absorber based on leaf-shaped cell at near-infrared regions

NASA Astrophysics Data System (ADS)

Huang, Hailong; Xia, Hui; Xie, Wenke; Guo, Zhibo; Li, Hongjian

2018-06-01

A size-efficient tunable metamaterial absorber (MA) composed of metallic leaf-shaped cell, graphene layer, silicon substrate, and bottom metal film is investigated theoretically and numerically at near-infrared (NIR) regions. Simulation results reveal that the single-band high absorption of 91.9% is obtained at 1268.7 nm. Further results show that the single-band can be simply changed into dual-band high absorption by varying the geometric parameters of top metallic layer at same wavelength regions, yielding two high absorption coefficients of 96.6% and 95.3% at the wavelengths of 1158.7 nm and 1323.6 nm, respectively. And the effect of related geometric parameter on dual-band absorption intensities is also investigated to obtain the optimized one. The peak wavelength can be tuned via modifying the Fermi energy of the graphene layer through controlling the external gate voltage. The work shows that the proposed strategy can be applied to other design of the dual-band structure at infrared regions.

Depletion-mode vertical Ga2O3 trench MOSFETs fabricated using Ga2O3 homoepitaxial films grown by halide vapor phase epitaxy

NASA Astrophysics Data System (ADS)

Sasaki, Kohei; Thieu, Quang Tu; Wakimoto, Daiki; Koishikawa, Yuki; Kuramata, Akito; Yamakoshi, Shigenobu

2017-12-01

We developed depletion-mode vertical Ga2O3 trench metal-oxide-semiconductor field-effect transistors by using n+ contact and n- drift layers. These epilayers were grown on an n+ (001) Ga2O3 single-crystal substrate by halide vapor phase epitaxy. Cu and HfO2 were used for the gate metal and dielectric film, respectively. The mesa width and gate length were approximately 2 and 1 µm, respectively. The devices showed good DC characteristics, with a specific on-resistance of 3.7 mΩ cm2 and clear current modulation. An on-off ratio of approximately 103 was obtained.

Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method

NASA Astrophysics Data System (ADS)

Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

2018-05-01

In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks

NASA Astrophysics Data System (ADS)

Kim, Kyoung H.; Gordon, Roy G.; Ritenour, Andrew; Antoniadis, Dimitri A.

2007-05-01

Atomic layer deposition (ALD) was used to deposit passivating interfacial nitride layers between Ge and high-κ oxides. High-κ oxides on Ge surfaces passivated by ultrathin (1-2nm) ALD Hf3N4 or AlN layers exhibited well-behaved C-V characteristics with an equivalent oxide thickness as low as 0.8nm, no significant flatband voltage shifts, and midgap density of interface states values of 2×1012cm-1eV-1. Functional n-channel and p-channel Ge field effect transistors with nitride interlayer/high-κ oxide/metal gate stacks are demonstrated.

Ion transport by gating voltage to nanopores produced via metal-assisted chemical etching method.

PubMed

Van Toan, Nguyen; Inomata, Naoki; Toda, Masaya; Ono, Takahito

2018-05-11

In this work, we report a simple and low-cost way to create nanopores that can be employed for various applications in nanofluidics. Nano sized Ag particles in the range from 1 to 20 nm are formed on a silicon substrate with a de-wetting method. Then the silicon nanopores with an approximate 15 nm average diameter and 200 μm height are successfully produced by the metal-assisted chemical etching method. In addition, electrically driven ion transport in the nanopores is demonstrated for nanofluidic applications. Ion transport through the nanopores is observed and could be controlled by an application of a gating voltage to the nanopores.

Gated CT imaging using a free-breathing respiration signal from flow-volume spirometry

DOE Office of Scientific and Technical Information (OSTI.GOV)

D'Souza, Warren D.; Kwok, Young; Deyoung, Chad

2005-12-15

Respiration-induced tumor motion is known to cause artifacts on free-breathing spiral CT images used in treatment planning. This leads to inaccurate delineation of target volumes on planning CT images. Flow-volume spirometry has been used previously for breath-holds during CT scans and radiation treatments using the active breathing control (ABC) system. We have developed a prototype by extending the flow-volume spirometer device to obtain gated CT scans using a PQ 5000 single-slice CT scanner. To test our prototype, we designed motion phantoms to compare image quality obtained with and without gated CT scan acquisition. Spiral and axial (nongated and gated) CTmore » scans were obtained of phantoms with motion periods of 3-5 s and amplitudes of 0.5-2 cm. Errors observed in the volume estimate of these structures were as much as 30% with moving phantoms during CT simulation. Application of motion-gated CT with active breathing control reduced these errors to within 5%. Motion-gated CT was then implemented in patients and the results are presented for two clinical cases: lung and abdomen. In each case, gated scans were acquired at end-inhalation, end-exhalation in addition to a conventional free-breathing (nongated) scan. The gated CT scans revealed reduced artifacts compared with the conventional free-breathing scan. Differences of up to 20% in the volume of the structures were observed between gated and free-breathing scans. A comparison of the overlap of structures between the gated and free-breathing scans revealed misalignment of the structures. These results demonstrate the ability of flow-volume spirometry to reduce errors in target volumes via gating during CT imaging.« less

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers

PubMed Central

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Abstract Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlOx), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers. PMID:28634499

Three-input gate logic circuits on chemically assembled single-electron transistors with organic and inorganic hybrid passivation layers.

PubMed

Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu

2017-01-01

Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.

A Low Temperature, Solution-Processed Poly(4-vinylphenol), YO(x) Nanoparticle Composite/Polysilazane Bi-Layer Gate Insulator for ZnO Thin Film Transistor.

PubMed

Shin, Hyeonwoo; Kang, Chan-Mo; Chae, Hyunsik; Kim, Hyun-Gwan; Baek, Kyu-Ha; Choi, Hyoung Jin; Park, Man-Young; Do, Lee-Mi; Lee, Changhee

2016-03-01

Low temperature, solution-processed metal oxide thin film transistors (MEOTFTs) have been widely investigated for application in low-cost, transparent, and flexible electronics. To enlarge the application area, solution-processed gate insulators (GI) have been investigated in recent years. We investigated the effects of the organic/inorganic bi-layer GI to ZnO thin film transistors (TFTs). PVP, YO(x) nanoparticle composite, and polysilazane bi-layer showed low leakage current (-10(-8) A/cm2 in 2 MV), which are applicable in low temperature processed MEOTFTs. Polysilazane was used as an interlayer between ZnO and PVP, YO(x) nanoparticle composite as a good charge transport interface with ZnO. By applying the PVP, YO(x), nanoparticle composite/polysilazane bi-layer structure to ZnO TFTs, we successfully suppressed the off current (I(off)) to -10(-11) and fabricated good MEOTFTs in 180 degrees C.

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

NASA Astrophysics Data System (ADS)

Ikeda, Sho; Lee, Sang-Yeop; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

2015-04-01

In this paper, we present a voltage-controlled oscillator (VCO), which achieves highly linear frequency tuning under a low supply voltage of 0.5 V. To obtain the linear frequency tuning of a VCO, the high linearity of the threshold voltage of a varactor versus its back-gate voltage is utilized. This enables the linear capacitance tuning of the varactor; thus, a highly linear VCO can be achieved. In addition, to decrease the power consumption of the VCO, a current-reuse structure is employed as a cross-coupled pair. The proposed VCO was fabricated using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. It shows the ratio of the maximum VCO gain (KVCO) to the minimum one to be 1.28. The dc power consumption is 0.33 mW at a supply voltage of 0.5 V. The measured phase noise at 10 MHz offset is -123 dBc/Hz at an output frequency of 5.8 GHz.

Neutral beam and ICP etching of HKMG MOS capacitors: Observations and a plasma-induced damage model

NASA Astrophysics Data System (ADS)

Kuo, Tai-Chen; Shih, Tzu-Lang; Su, Yin-Hsien; Lee, Wen-Hsi; Current, Michael Ira; Samukawa, Seiji

2018-04-01

In this study, TiN/HfO2/Si metal-oxide-semiconductor (MOS) capacitors were etched by a neutral beam etching technique under two contrasting conditions. The configurations of neutral beam etching technique were specially designed to demonstrate a "damage-free" condition or to approximate "reactive-ion-etching-like" conditions to verify the effect of plasma-induced damage on electrical characteristics of MOS capacitors. The results show that by neutral beam etching (NBE), the interface state density (Dit) and the oxide trapped charge (Qot) were lower than routine plasma etching. Furthermore, the decrease in capacitor size does not lead to an increase in leakage current density, indicating less plasma induced side-wall damage. We present a plasma-induced gate stack damage model which we demonstrate by using these two different etching configurations. These results show that NBE is effective in preventing plasma-induced damage at the high-k/Si interface and on the high-k oxide sidewall and thus improve the electrical performance of the gate structure.

Rhenium Disulfide Depletion-Load Inverter

NASA Astrophysics Data System (ADS)

McClellan, Connor; Corbet, Chris; Rai, Amritesh; Movva, Hema C. P.; Tutuc, Emanuel; Banerjee, Sanjay K.

2015-03-01

Many semiconducting Transition Metal Dichalcogenide (TMD) materials have been effectively used to create Field-Effect Transistor (FET) devices but have yet to be used in logic designs. We constructed a depletion-load voltage inverter using ultrathin layers of Rhenium Disulfide (ReS2) as the semiconducting channel. This ReS2 inverter was fabricated on a single micromechanically-exfoliated flake of ReS2. Electron beam lithography and physical vapor deposition were used to construct Cr/Au electrical contacts, an Alumina top-gate dielectric, and metal top-gate electrodes. By using both low (Aluminum) and high (Palladium) work-function metals as two separate top-gates on a single ReS2 flake, we create a dual-gated depletion mode (D-mode) and enhancement mode (E-mode) FETs in series. Both FETs displayed current saturation in the output characteristics as a result of the FET ``pinch-off'' mechanism and On/Off current ratios of 105. Field-effect mobilities of 23 and 17 cm2V-1s-1 and subthreshold swings of 97 and 551 mV/decade were calculated for the E-mode and D-mode FETs, respectively. With a supply voltage of 1V, at low/negative input voltages the inverter output was at a high logic state of 900 mV. Conversely with high/positive input voltages, the inverter output was at a low logic state of 500 mV. The inversion of the input signal demonstrates the potential for using ReS2 in future integrated circuit designs and the versatility of depletion-load logic devices for TMD research. NRI SWAN Center and ARL STTR Program.

Structured-gate organic field-effect transistors

NASA Astrophysics Data System (ADS)

Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.

2012-06-01

We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Study on effective MOSFET channel length extracted from gate capacitance

NASA Astrophysics Data System (ADS)

Tsuji, Katsuhiro; Terada, Kazuo; Fujisaka, Hisato

2018-01-01

The effective channel length (L GCM) of metal-oxide-semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which L GCM is extracted. It is found that L GCM is slightly less than the effective channel length (L CRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

Remote N2 plasma treatment to deposit ultrathin high-k dielectric as tunneling contact layer for single-layer MoS2 MOSFET

NASA Astrophysics Data System (ADS)

Qian, Qingkai; Zhang, Zhaofu; Hua, Mengyuan; Wei, Jin; Lei, Jiacheng; Chen, Kevin J.

2017-12-01

Remote N2 plasma treatment is explored as a surface functionalization technique to deposit ultrathin high-k dielectric on single-layer MoS2. The ultrathin dielectric is used as a tunneling contact layer, which also serves as an interfacial layer below the gate region for fabricating top-gate MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs). The fabricated devices exhibited small hysteresis and mobility as high as 14 cm2·V-1·s-1. The contact resistance was significantly reduced, which resulted in the increase of drain current from 20 to 56 µA/µm. The contact resistance reduction can be attributed to the alleviated metal-MoS2 interface reaction and the preserved conductivity of MoS2 below the source/drain metal contact.

Low-damage high-throughput grazing-angle sputter deposition on graphene

NASA Astrophysics Data System (ADS)

Chen, C.-T.; Casu, E. A.; Gajek, M.; Raoux, S.

2013-07-01

Despite the prevalence of sputter deposition in the microelectronics industry, it has seen very limited applications for graphene electronics. In this letter, we report systematic investigation of the sputtering induced damages in graphene and identify the energetic sputtering gas neutrals as the primary cause of graphene disorder. We further demonstrate a grazing-incidence sputtering configuration that strongly suppresses fast neutral bombardment and retains graphene structure integrity, creating considerably lower damage than electron-beam evaporation. Such sputtering technique yields fully covered, smooth thin dielectric films, highlighting its potential for contact metals, gate oxides, and tunnel barriers fabrication in graphene device applications.

Microscopic signature of insulator-to-metal transition in highly doped semicrystalline conducting polymers in ionic-liquid-gated transistors

NASA Astrophysics Data System (ADS)

Tanaka, Hisaaki; Nishio, Satoshi; Ito, Hiroshi; Kuroda, Shin-ichi

2015-12-01

Electronic state of charge carriers, in particular, in highly doped regions, in thin-film transistors of a semicrystalline conducting polymer poly(2,5-bis(3-alkylthiophene-2-yl)thieno[3,2-b]thiophene), has been studied by using field-induced electron spin resonance (ESR) spectroscopy. By adopting an ionic-liquid gate insulator, a gate-controlled reversible electrochemical hole-doping of the polymer backbone is achieved, as confirmed from the change of the optical absorption spectra. The edge-on molecular orientation in the pristine film is maintained even after the electrochemical doping, which is clarified from the angular dependence of the g value. As the doping level increases, spin 1/2 polarons transform into spinless bipolarons, which is demonstrated from the spin-charge relation showing a spin concentration peak around 1%, contrasting to the monotonic increase in the charge concentration. At high doping levels, a drastic change in the linewidth anisotropy due to the generation of conduction electrons is observed, indicating the onset of metallic state, which is also supported by the temperature dependence of the spin susceptibility and the ESR linewidth. Our results suggest that semicrystalline conducting polymers become metallic with retaining their molecular orientational order, when appropriate doping methods are chosen.

Low-frequency noise in AlN/AlGaN/GaN metal-insulator-semiconductor devices: A comparison with Schottky devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Nguyen, Tuan Quy; Shih, Hong-An

2014-08-07

We have systematically investigated low-frequency noise (LFN) in AlN/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, where the AlN gate insulator layer was sputtering-deposited on the AlGaN surface, in comparison with LFN in AlGaN/GaN Schottky devices. By measuring LFN in ungated two-terminal devices and heterojunction field-effect transistors (HFETs), we extracted LFN characteristics in the intrinsic gated region of the HFETs. Although there is a bias regime of the Schottky-HFETs in which LFN is dominated by the gate leakage current, LFN in the MIS-HFETs is always dominated by only the channel current. Analyzing the channel-current-dominated LFN, we obtained Hooge parameters α for the gated regionmore » as a function of the sheet electron concentration n{sub s} under the gate. In a regime of small n{sub s}, both the MIS- and Schottky-HFETs exhibit α∝n{sub s}{sup −1}. On the other hand, in a middle n{sub s} regime of the MIS-HFETs, α decreases rapidly like n{sub s}{sup −ξ} with ξ ∼ 2-3, which is not observed for the Schottky-HFETs. In addition, we observe strong increase in α∝n{sub s}{sup 3} in a large n{sub s} regime for both the MIS- and Schottky-HFETs.« less

The Use of Ferroelectrics and Dipeptides as Insulators in Organic Field-Effect Transistor Devices

NASA Astrophysics Data System (ADS)

Knotts, Grant

While the electrical transport characteristics of organic electronic devices are generally inferior to their inorganic counterparts, organic materials offer many advantages over inorganics. The materials used in organic devices can often be deposited using cheap and simple processing techniques such as spincoating, inkjet printing, or roll-to-roll processing; allow for large-scale, flexible devices; and can have the added benefits of being transparent or biodegradable. In this manuscript, we examine the role of solvents in the performance of pentacene-based devices using the ferroelectric copolymer polyvinylidene fluoride-trifluoroethylene (PVDF-TrFe) as a gate insulating layer. High dipole moment solvents, such as dimethyl sulfoxide, used to dissolve the copolymer for spincoating increase the charge carrier mobility in field-effect transistors (FETs) by nearly an order of magnitude as compared to lower dipole moment solvents. The polarization in Al/PVDF-TrFe/Au metal-ferroelectric-metal devices also shows an increase in remnant polarization of 20% in the sample using dimethyl sulfoxide as the solvent for the ferroelectric. Interestingly, at low applied electric fields of 100 MV/m a remnant polarization is seen in the high dipole moment device that is nearly 3.5 times larger than the value observed in the lower dipole moment samples, suggesting that the degree of dipolar order is higher at low operating voltages for the high dipole moment device. We will also discuss the use of peptide-based nanostructures derived from natural amino acids as building blocks for biocompatible devices. These peptides can be used in a bottom-up process without the need for expensive lithography. Thin films of L,L-diphenylalanine micro/nanostructures (FF-MNSs) were used as the dielectric layer in pentacene-based FETs and metal-insulator-semiconductor diodes both in bottom-gate and top-gate structures. It is demonstrated that the FFMNSs can be functionalized for detection of enzyme-analyte interactions. This work opens up a novel and facile route towards scalable organic electronics using peptide nanostructures as scaffolding and as a platform for biosensing.

A chimeric prokaryotic pentameric ligand–gated channel reveals distinct pathways of activation

DOE PAGES

Schmandt, Nicolaus; Velisetty, Phanindra; Chalamalasetti, Sreevatsa V.; ...

2015-09-28

Recent high resolution structures of several pentameric ligand–gated ion channels have provided unprecedented details of their molecular architecture. However, the conformational dynamics and structural rearrangements that underlie gating and allosteric modulation remain poorly understood. We used a combination of electrophysiology, double electron–electron resonance (DEER) spectroscopy, and x-ray crystallography to investigate activation mechanisms in a novel functional chimera with the extracellular domain (ECD) of amine-gated Erwinia chrysanthemi ligand–gated ion channel, which is activated by primary amines, and the transmembrane domain of Gloeobacter violaceus ligand–gated ion channel, which is activated by protons. We found that the chimera was independently gated by primarymore » amines and by protons. The crystal structure of the chimera in its resting state, at pH 7.0 and in the absence of primary amines, revealed a closed-pore conformation and an ECD that is twisted with respect to the transmembrane region. Amine- and pH-induced conformational changes measured by DEER spectroscopy showed that the chimera exhibits a dual mode of gating that preserves the distinct conformational changes of the parent channels. Collectively, our findings shed light on both conserved and divergent features of gating mechanisms in this class of channels, and will facilitate the design of better allosteric modulators.« less

A chimeric prokaryotic pentameric ligand–gated channel reveals distinct pathways of activation

PubMed Central

Schmandt, Nicolaus; Velisetty, Phanindra; Chalamalasetti, Sreevatsa V.; Stein, Richard A.; Bonner, Ross; Talley, Lauren; Parker, Mark D.; Mchaourab, Hassane S.; Yee, Vivien C.; Lodowski, David T.

2015-01-01

Recent high resolution structures of several pentameric ligand–gated ion channels have provided unprecedented details of their molecular architecture. However, the conformational dynamics and structural rearrangements that underlie gating and allosteric modulation remain poorly understood. We used a combination of electrophysiology, double electron–electron resonance (DEER) spectroscopy, and x-ray crystallography to investigate activation mechanisms in a novel functional chimera with the extracellular domain (ECD) of amine-gated Erwinia chrysanthemi ligand–gated ion channel, which is activated by primary amines, and the transmembrane domain of Gloeobacter violaceus ligand–gated ion channel, which is activated by protons. We found that the chimera was independently gated by primary amines and by protons. The crystal structure of the chimera in its resting state, at pH 7.0 and in the absence of primary amines, revealed a closed-pore conformation and an ECD that is twisted with respect to the transmembrane region. Amine- and pH-induced conformational changes measured by DEER spectroscopy showed that the chimera exhibits a dual mode of gating that preserves the distinct conformational changes of the parent channels. Collectively, our findings shed light on both conserved and divergent features of gating mechanisms in this class of channels, and will facilitate the design of better allosteric modulators. PMID:26415570

Epitaxial GeSn film formed by solid phase epitaxy and its application to Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor capacitors with sub-nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lee, Ching-Wei; Wu, Yung-Hsien; Hsieh, Ching-Heng

2014-11-17

Through the technique of solid phase epitaxy (SPE), an epitaxial Ge{sub 0.955}Sn{sub 0.045} film was formed on a Ge substrate by depositing an amorphous GeSn film followed by a rapid thermal annealing at 550 °C. A process that uses a SiO{sub 2} capping layer on the amorphous GeSn film during SPE was proposed and it prevents Sn precipitation from occurring while maintaining a smooth surface due to the reduced surface mobility of Sn atoms. The high-quality epitaxial GeSn film was observed to have single crystal structure, uniform thickness and composition, and tiny surface roughness with root mean square of 0.56 nm. Withmore » a SnO{sub x}-free surface, Yb{sub 2}O{sub 3}-gated GeSn metal-oxide-semiconductor (MOS) capacitors with equivalent oxide thickness (EOT) of 0.55 nm were developed. A small amount of traps inside the Yb{sub 2}O{sub 3} was verified by negligible hysteresis in capacitance measurement. Low leakage current of 0.4 A/cm{sup 2} at gate bias of flatband voltage (V{sub FB})-1 V suggests the high quality of the gate dielectric. In addition, the feasibility of using Yb{sub 2}O{sub 3} to well passivate GeSn surface was also evidenced by the small interface trap density (D{sub it}) of 4.02 × 10{sup 11} eV{sup −1} cm{sup −2}, which can be attributed to smooth GeSn surface and Yb{sub 2}O{sub 3} valency passivation. Both leakage current and D{sub it} performance outperform other passivation techniques at sub-nm EOT regime. The proposed epitaxial GeSn film along with Yb{sub 2}O{sub 3} dielectric paves an alternative way to enable high-performance GeSn MOS devices.« less

Tunable Mobility in Double-Gated MoTe2 Field-Effect Transistor: Effect of Coulomb Screening and Trap Sites.

PubMed

Ji, Hyunjin; Joo, Min-Kyu; Yi, Hojoon; Choi, Homin; Gul, Hamza Zad; Ghimire, Mohan Kumar; Lim, Seong Chu

2017-08-30

There is a general consensus that the carrier mobility in a field-effect transistor (FET) made of semiconducting transition-metal dichalcogenides (s-TMDs) is severely degraded by the trapping/detrapping and Coulomb scattering of carriers by ionic charges in the gate oxides. Using a double-gated (DG) MoTe 2 FET, we modulated and enhanced the carrier mobility by adjusting the top- and bottom-gate biases. The relevant mechanism for mobility tuning in this device was explored using static DC and low-frequency (LF) noise characterizations. In the investigations, LF-noise analysis revealed that for a strong back-gate bias the Coulomb scattering of carriers by ionized traps in the gate dielectrics is strongly screened by accumulation charges. This significantly reduces the electrostatic scattering of channel carriers by the interface trap sites, resulting in increased mobility. The reduction of the number of effective trap sites also depends on the gate bias, implying that owing to the gate bias, the carriers are shifted inside the channel. Thus, the number of active trap sites decreases as the carriers are repelled from the interface by the gate bias. The gate-controlled Coulomb-scattering parameter and the trap-site density provide new handles for improving the carrier mobility in TMDs, in a fundamentally different way from dielectric screening observed in previous studies.

Study and optimization of key parameters of a laser ablation ion mobility spectrometer

NASA Astrophysics Data System (ADS)

Ni, Kai; Li, Jianan; Tang, Binchao; Shi, Yuan; Yu, Quan; Qian, Xiang; Wang, Xiaohao

2016-11-01

Ion Mobility Spectrometry (IMS), having an advantage in real-time and on-line detection, is an atmospheric pressure detecting technique. LA-IMS (Laser Ablation Ion Mobility Spectrometry) uses Nd-YAG laser as ionization source, whose energy is high enough to ionize metal. In this work, we tested the signal in different electric field intensity by a home-made ion mobility spectrometer, using silicon wafers the sample. The transportation of metal ions was match with the formula: Td = d/K • 1/E, when the electric field intensity is greater than 350v/cm. The relationship between signal intensity and collection angle (the angle between drift tube and the surface of the sample) was studied. With the increasing of the collection angle, signal intensity had a significant increase; while the variation of incident angle of the laser had no significant influence. The signal intensity had a 140% increase when the collection angle varied from 0 to 45 degree, while the angle between the drift tube and incident laser beam keeping the same as 90 degree. The position of ion gate in LA-IMS(Laser Ablation Ion Mobility Spectrometry) is different from the traditional ones for the kinetic energy of the ions is too big, if the distance between ion gate and sampling points less than 2.5cm the ion gate will not work, the ions could go through ion gate when it closed. The SNR had been improved by define the signal when the ion gate is closed as background signal, the signal noise including shock wave and electrical field perturbation produced during the interaction between laser beam and samples is eliminated when the signal that the ion gate opened minus the background signal.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmandt, Nicolaus; Velisetty, Phanindra; Chalamalasetti, Sreevatsa V.

Recent high resolution structures of several pentameric ligand–gated ion channels have provided unprecedented details of their molecular architecture. However, the conformational dynamics and structural rearrangements that underlie gating and allosteric modulation remain poorly understood. We used a combination of electrophysiology, double electron–electron resonance (DEER) spectroscopy, and x-ray crystallography to investigate activation mechanisms in a novel functional chimera with the extracellular domain (ECD) of amine-gated Erwinia chrysanthemi ligand–gated ion channel, which is activated by primary amines, and the transmembrane domain of Gloeobacter violaceus ligand–gated ion channel, which is activated by protons. We found that the chimera was independently gated by primarymore » amines and by protons. The crystal structure of the chimera in its resting state, at pH 7.0 and in the absence of primary amines, revealed a closed-pore conformation and an ECD that is twisted with respect to the transmembrane region. Amine- and pH-induced conformational changes measured by DEER spectroscopy showed that the chimera exhibits a dual mode of gating that preserves the distinct conformational changes of the parent channels. Collectively, our findings shed light on both conserved and divergent features of gating mechanisms in this class of channels, and will facilitate the design of better allosteric modulators.« less

Voltage gating by molecular subunits of Na+ and K+ ion channels: higher-dimensional cubic kinetics, rate constants, and temperature.

PubMed

Fohlmeister, Jürgen F

2015-06-01

The structural similarity between the primary molecules of voltage-gated Na and K channels (alpha subunits) and activation gating in the Hodgkin-Huxley model is brought into full agreement by increasing the model's sodium kinetics to fourth order (m(3) → m(4)). Both structures then virtually imply activation gating by four independent subprocesses acting in parallel. The kinetics coalesce in four-dimensional (4D) cubic diagrams (16 states, 32 reversible transitions) that show the structure to be highly failure resistant against significant partial loss of gating function. Rate constants, as fitted in phase plot data of retinal ganglion cell excitation, reflect the molecular nature of the gating transitions. Additional dimensions (6D cubic diagrams) accommodate kinetically coupled sodium inactivation and gating processes associated with beta subunits. The gating transitions of coupled sodium inactivation appear to be thermodynamically irreversible; response to dielectric surface charges (capacitive displacement) provides a potential energy source for those transitions and yields highly energy-efficient excitation. A comparison of temperature responses of the squid giant axon (apparently Arrhenius) and mammalian channel gating yields kinetic Q10 = 2.2 for alpha unit gating, whose transitions are rate-limiting at mammalian temperatures; beta unit kinetic Q10 = 14 reproduces the observed non-Arrhenius deviation of mammalian gating at low temperatures; the Q10 of sodium inactivation gating matches the rate-limiting component of activation gating at all temperatures. The model kinetics reproduce the physiologically large frequency range for repetitive firing in ganglion cells and the physiologically observed strong temperature dependence of recovery from inactivation. Copyright © 2015 the American Physiological Society.

Plasmonics-enabled metal-semiconductor-metal photodiodes for high-speed interconnects and polarization sensitive detectors

NASA Astrophysics Data System (ADS)

Panchenko, Evgeniy; Cadusch, Jasper J.; James, Timothy D.; Roberts, Ann

2017-02-01

Metal-semiconductor-metal (MSM) photodiodes are commonly used in ultrafast photoelectronic devices. Recently it was shown that localized surface plasmons can sufficiently enhance photodetector capabilities at both infrared and visible wavelengths. Such structures are of great interest since they can be used for fast, broadband detection. By utilizing the properties of plasmonic structures it is possible to design photodetectors that are sensitive to the polarization state of the incident wave. The direct electrical readout of the polarization state of an incident optical beam has many important applications, especially in telecommunications, bio-imaging and photonic computing. Furthermore, the fact that surface plasmon polaritons can circumvent the diffraction limit, opens up significant opportunities to use them to guide signals between logic gates in modern integrated circuits where small dimensions are highly desirable. Here we demonstrate two MSM photodetectors integrated with aluminum nanoantennas capable of distinguishing orthogonal states of either linearly or circularly polarized light with no additional filters. The localized plasmon resonances of the antennas lead to selective screening of the underlying silicon from light with a particular polarization state. The non-null response of the devices to each of the basis states expands the potential utility of the photodetectors while improving precision. We also demonstrate a design of waveguide-coupled MSM photodetector suitable for planar detection of surface plasmons.

A novel double gate metal source/drain Schottky MOSFET as an inverter

NASA Astrophysics Data System (ADS)

Loan, Sajad A.; Kumar, Sunil; Alamoud, Abdulrahman M.

2016-03-01

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor count in implementing combinational and sequential circuits. Further, there is a significant reduction in the number of junctions and regions in the proposed device in comparison to the conventional CMOS inverter. Therefore, the proposed device is compact and can consume less power. The proposed device has been named as Sajad-Sunil-Schottky (SSS) device. The mixed mode circuit analysis of the proposed SSS device has shown that a CMOS inverter action with high logic level (VOH) and low logic level (VOL) as ∼VDD and ∼ground respectively. A two dimensional calibrated simulation study using the experimental data has revealed that the proposed SSS device in n and p type modes have subthreshold slopes (S) of 130 mV/decade and 85 mV/decade respectively and have reasonable high ION and ION/IOFF ratio's. Furthermore, it has been proved that such a device action cannot be realised by folding the conventional doped n and p MOS transistors.

8 MeV electron beam induced modifications in the thermal, structural and electrical properties of nanophase CeO2 for potential electronics applications

NASA Astrophysics Data System (ADS)

Babitha, K. K.; Sreedevi, A.; Priyanka, K. P.; Ganesh, S.; Varghese, Thomas

2018-06-01

The effect of 8 MeV electron beam irradiation on the thermal, structural and electrical properties of CeO2 nanoparticles synthesized by chemical precipitation route was investigated. The dose dependent effect of electron irradiation was studied using various characterization techniques such as, thermogravimetric and differential thermal analyses, X-ray diffraction, Fourier transformed infrared spectroscopy and impedance spectroscopy. Systematic investigation based on the results of structural studies confirm that electron beam irradiation induces defects and particle size variation on CeO2 nanoparticles, which in turn results improvements in AC conductivity, dielectric constant and loss tangent. Structural modifications and high value of dielectric constant for CeO2 nanoparticles due to electron beam irradiation make it as a promising material for the fabrication of gate dielectric in metal oxide semiconductor devices.

Porous Emitter Colloid Thruster Performance Characterization Using Optical Techniques

DTIC Science & Technology

2013-03-01

spacecraft. Liquid propellant has received a renewed interest as a viable propellant with the creation and proliferation of new ionic liquid compounds ...electrostatic gate) and collector (metallic plate) is unknown. Two factors cause this ambiguity, first, the gate needs to close fast enough to...simultaneously block all of the emitters and second, it is not directly known which emitter released the last particle hitting the collector plate

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Highly Mobile Two-Dimensional Electron Gases with a Strong Gating Effect at the Amorphous LaAlO3/KTaO3 Interface.

PubMed

Zhang, Hui; Zhang, Hongrui; Yan, Xi; Zhang, Xuejing; Zhang, Qinghua; Zhang, Jing; Han, Furong; Gu, Lin; Liu, Banggui; Chen, Yuansha; Shen, Baogen; Sun, Jirong

2017-10-18

Two-dimensional electron gas (2DEG) at the perovskite oxide interface exhibits a lot of exotic properties, presenting a promising platform for the exploration of emergent phenomena. While most of the previous works focused on SrTiO 3 -based 2DEG, here we report on the fabrication of high-quality 2DEGs by growing an amorphous LaAlO 3 layer on a (001)-orientated KTaO 3 substrate, which is a 5d metal oxide with a polar surface, at a high temperature that is usually adopted for crystalline LaAlO 3 . Metallic 2DEGs with a Hall mobility as high as ∼2150 cm 2 /(V s) and a sheet carrier density as low as 2 × 10 12 cm -2 are obtained. For the first time, the gating effect on the transport process is studied, and its influence on spin relaxation and inelastic and elastic scattering is determined. Remarkably, the spin relaxation time can be strongly tuned by a back gate. It is reduced by a factor of ∼69 while the gate voltage is swept from -25 to +100 V. The mechanism that dominates the spin relaxation is elucidated.

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

PubMed

Matsumoto, Tsubasa; Kato, Hiromitsu; Oyama, Kazuhiro; Makino, Toshiharu; Ogura, Masahiko; Takeuchi, Daisuke; Inokuma, Takao; Tokuda, Norio; Yamasaki, Satoshi

2016-08-22

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300 °C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5 μm were 1.6 mA/mm and 8.0 cm(2)/Vs, respectively, at room temperature.

Ambipolar transport in CVD grown MoSe2 monolayer using an ionic liquid gel gate dielectric

NASA Astrophysics Data System (ADS)

Ortiz, Deliris N.; Ramos, Idalia; Pinto, Nicholas J.; Zhao, Meng-Qiang; Kumar, Vinayak; Johnson, A. T. Charlie

2018-03-01

CVD grown MoSe2 monolayers were electrically characterized at room temperature in a field effect transistor (FET) configuration using an ionic liquid (IL) as the gate dielectric. During the growth, instead of using MoO3 powder, ammonium heptamolybdate was used for better Mo control of the source and sodium cholate added for lager MoSe2 growth areas. In addition, a high specific capacitance (˜7 μF/cm2) IL was used as the gate dielectric to significantly reduce the operating voltage. The device exhibited ambipolar charge transport at low voltages with enhanced parameters during n- and p-FET operation. IL gating thins the Schottky barrier at the metal/semiconductor interface permitting efficient charge injection into the channel and reduces the effects of contact resistance on device performance. The large specific capacitance of the IL was also responsible for a much higher induced charge density compared to the standard SiO2 dielectric. The device was successfully tested as an inverter with a gain of ˜2. Using a common metal for contacts simplifies fabrication of this ambipolar device, and the possibility of radiative recombination of holes and electrons could further extend its use in low power optoelectronic applications.

Low-voltage organic transistors on plastic comprising high-dielectric constant gate insulators

PubMed

Dimitrakopoulos; Purushothaman; Kymissis; Callegari; Shaw

1999-02-05

The gate bias dependence of the field-effect mobility in pentacene-based insulated gate field-effect transistors (IGFETs) was interpreted on the basis of the interaction of charge carriers with localized trap levels in the band gap. This understanding was used to design and fabricate IGFETs with mobility of more than 0.3 square centimeter per volt per second and current modulation of 10(5), with the use of amorphous metal oxide gate insulators. These values were obtained at operating voltage ranges as low as 5 volts, which are much smaller than previously reported results. An all-room-temperature fabrication process sequence was used, which enabled the demonstration of high-performance organic IGFETs on transparent plastic substrates, at low operating voltages for organic devices.

Low-Temperature Carrier Transport in Ionic-Liquid-Gated Hydrogen-Terminated Silicon

NASA Astrophysics Data System (ADS)

Sasama, Yosuke; Yamaguchi, Takahide; Tanaka, Masashi; Takeya, Hiroyuki; Takano, Yoshihiko

2017-11-01

We fabricated ionic-liquid-gated field-effect transistors on the hydrogen-terminated (111)-oriented surface of undoped silicon. Ion implantation underneath electrodes leads to good ohmic contacts, which persist at low temperatures down to 1.4 K. The sheet resistance of the channel decreases by more than five orders of magnitude as the gate voltage is changed from 0 to -1.6 V at 220 K. This is caused by the accumulation of hole carriers. The sheet resistance shows thermally activated behavior at temperatures below 10 K, which is attributed to hopping transport of the carriers. The activation energy decreases towards zero with increasing carrier density, suggesting the approach to an insulator-metal transition. We also report the variation of device characteristics induced by repeated sweeps of the gate voltage.

DNA-mediated gold nanoparticle signal transducers for combinatorial logic operations and heavy metal ions sensing.

PubMed

Zhang, Yuhuan; Liu, Wei; Zhang, Wentao; Yu, Shaoxuan; Yue, Xiaoyue; Zhu, Wenxin; Zhang, Daohong; Wang, Yanru; Wang, Jianlong

2015-10-15

Herein, the structure of two DNA strands which are complementary except fourteen T-T and C-C mismatches was programmed for the design of the combinatorial logic operation by utilizing the different protective capacities of single chain DNA, part-hybridized DNA and completed-hybridized DNA on unmodified gold nanoparticles. In the presence of either Hg(2+) or Ag(+), the T-Hg(2+)-T or C-Ag(+)-C coordination chemistry could lead to the formation of part-hybridized DNA which keeps gold nanoparticles from clumping after the addition of 40 μL 0.2M NaClO4 solution, but the protection would be screened by 120 μL 0.2M NaClO4 solution. While the coexistence of Hg(2+), Ag(+) caused the formation of completed-hybridized DNA and the protection for gold nanoparticles lost in either 40 μL or 120 μL NaClO4 solutions. Benefiting from sharing of the same inputs of Hg(2+) and Ag(+), OR and AND logic gates were easily integrated into a simple colorimetric combinatorial logic operation in one system, which make it possible to execute logic gates in parallel to mimic arithmetic calculations on a binary digit. Furthermore, two other logic gates including INHIBIT1 and INHIBIT2 were realized to integrated with OR logic gate both for simultaneous qualitative discrimination and quantitative determination of Hg(2+) and Ag(+). Results indicate that the developed logic system based on the different protective capacities of DNA structure on gold nanoparticles provides a new pathway for the design of the combinatorial logic operation in one system and presents a useful strategy for development of advanced sensors, which may have potential applications in multiplex chemical analysis and molecular-scale computer design. Copyright © 2015 Elsevier B.V. All rights reserved.

Enhancement of minority carrier injection in ambipolar carbon nanotube transistors using double-gate structures

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Bongjun; Liang, Kelly; Dodabalapur, Ananth, E-mail: ananth.dodabalapur@engr.utexas.edu

We show that double-gate ambipolar thin-film transistors can be operated to enhance minority carrier injection. The two gate potentials need to be significantly different for enhanced injection to be observed. This enhancement is highly beneficial in devices such as light-emitting transistors where balanced electron and hole injections lead to optimal performance. With ambipolar single-walled carbon nanotube semiconductors, we demonstrate that higher ambipolar currents are attained at lower source-drain voltages, which is desired for portable electronic applications, by employing double-gate structures. In addition, when the two gates are held at the same potential, the expected advantages of the double-gate transistors suchmore » as enhanced on-current are also observed.« less

Temporal dynamics of frequency-tunable graphene-based plasmonic grating structures for ultra-broadband terahertz communication

NASA Astrophysics Data System (ADS)

Jornet, Josep Miquel; Thawdar, Ngwe; Woo, Ethan; Andrello, Michael A.

2017-05-01

Terahertz (THz) communication is envisioned as a key wireless technology to satisfy the need for 1000x faster wireless data rates. To date, major progress on both electronic and photonic technologies are finally closing the so-called THz gap. Among others, graphene-based plasmonic nano-devices have been proposed as a way to enable ultra-broadband communications above 1THz. The unique dynamic complex conductivity of graphene enables the propagation of Surface Plasmon Polariton (SPP) waves at THz frequencies. In addition, the conductivity of graphene and, thus, the SPP propagation properties, can be dynamically tuned by means of electrostatic biasing or material doping. This result opens the door to frequency-tunable devices for THz communications. In this paper, the temporal dynamics of graphene-enhanced metallic grating structures used for excitation and detection of SPP waves at THz frequencies are analytically and numerically modeled. More specifically, the response of a metallic grating structure built on top of a graphene-based heterostructure is analyzed by taking into account the grating period and duty cycle and the Fermi energy of the graphene layer. Then, the interfacial charge transfer between a metallic back-gate and the graphene layer in a metal/dielectric/graphene stack is analytically modeled, and the range of achievable Fermi energies is determined. Finally, the rate at which the Fermi energy in graphene can be tuned is estimated starting from the transmission line model of graphene. Extensive numerical and simulation results with COMSOL Multi-physics are provided. The results show that the proposed structure enables dynamic frequency systems with THz bandwidths, thus, enabling resilient communication techniques such as time-hopping THz modulations.

Quantum cellular automata

NASA Astrophysics Data System (ADS)

Porod, Wolfgang; Lent, Craig S.; Bernstein, Gary H.

1994-06-01

The Notre Dame group has developed a new paradigm for ultra-dense and ultra-fast information processing in nanoelectronic systems. These Quantum Cellular Automata (QCA's) are the first concrete proposal for a technology based on arrays of coupled quantum dots. The basic building block of these cellular arrays is the Notre Dame Logic Cell, as it has been called in the literature. The phenomenon of Coulomb exclusion, which is a synergistic interplay of quantum confinement and Coulomb interaction, leads to a bistable behavior of each cell which makes possible their use in large-scale cellular arrays. The physical interaction between neighboring cells has been exploited to implement logic functions. New functionality may be achieved in this fashion, and the Notre Dame group invented a versatile majority logic gate. In a series of papers, the feasibility of QCA wires, wire crossing, inverters, and Boolean logic gates was demonstrated. A major finding is that all logic functions may be integrated in a hierarchial fashion which allows the design of complicated QCA structures. The most complicated system which was simulated to date is a one-bit full adder consisting of some 200 cells. In addition to exploring these new concepts, efforts are under way to physically realize such structures both in semiconductor and metal systems. Extensive modeling work of semiconductor quantum dot structures has helped identify optimum design parameters for QCA experimental implementations.

Method of making self-aligned lightly-doped-drain structure for MOS transistors

DOEpatents

Weiner, Kurt H.; Carey, Paul G.

2001-01-01

A process for fabricating lightly-doped-drains (LDD) for short-channel metal oxide semiconductor (MOS) transistors. The process utilizes a pulsed laser process to incorporate the dopants, thus eliminating the prior oxide deposition and etching steps. During the process, the silicon in the source/drain region is melted by the laser energy. Impurities from the gas phase diffuse into the molten silicon to appropriately dope the source/drain regions. By controlling the energy of the laser, a lightly-doped-drain can be formed in one processing step. This is accomplished by first using a single high energy laser pulse to melt the silicon to a significant depth and thus the amount of dopants incorporated into the silicon is small. Furthermore, the dopants incorporated during this step diffuse to the edge of the MOS transistor gate structure. Next, many low energy laser pulses are used to heavily dope the source/drain silicon only in a very shallow region. Because of two-dimensional heat transfer at the MOS transistor gate edge, the low energy pulses are inset from the region initially doped by the high energy pulse. By computer control of the laser energy, the single high energy laser pulse and the subsequent low energy laser pulses are carried out in a single operational step to produce a self-aligned lightly-doped-drain-structure.

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

NASA Astrophysics Data System (ADS)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Spin filter and spin valve in ferromagnetic graphene

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Yu, E-mail: kwungyusung@gmail.com; Dai, Gang; Research Center for Microsystems and Terahertz, China Academy of Engineering Physics, Mianyang 621999

2015-06-01

We propose and demonstrate that a EuO-induced and top-gated graphene ferromagnetic junction can be simultaneously operated as a spin filter and a spin valve. We attribute such a remarkable result to a coexistence of a half-metal band and a common energy gap for opposite spins in ferromagnetic graphene. We show that both the spin filter and the spin valve can be effectively controlled by a back gate voltage, and they survive for practical metal contacts and finite temperature. Specifically, larger single spin currents and on-state currents can be reached with contacts with work functions similar to graphene, and the spinmore » filter can operate at higher temperature than the spin valve.« less

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices

PubMed Central

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines. PMID:25763152

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

PubMed

Farhadi, Rozita; Farhadi, Bita

2014-01-01

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Study of Direct-Contact HfO2/Si Interfaces

PubMed Central

Miyata, Noriyuki

2012-01-01

Controlling monolayer Si oxide at the HfO2/Si interface is a challenging issue in scaling the equivalent oxide thickness of HfO2/Si gate stack structures. A concept that the author proposes to control the Si oxide interface by using ultra-high vacuum electron-beam HfO2 deposition is described in this review paper, which enables the so-called direct-contact HfO2/Si structures to be prepared. The electrical characteristics of the HfO2/Si metal-oxide-semiconductor capacitors are reviewed, which suggest a sufficiently low interface state density for the operation of metal-oxide-semiconductor field-effect-transistors (MOSFETs) but reveal the formation of an unexpected strong interface dipole. Kelvin probe measurements of the HfO2/Si structures provide obvious evidence for the formation of dipoles at the HfO2/Si interfaces. The author proposes that one-monolayer Si-O bonds at the HfO2/Si interface naturally lead to a large potential difference, mainly due to the large dielectric constant of the HfO2. Dipole scattering is demonstrated to not be a major concern in the channel mobility of MOSFETs. PMID:28817060

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

PubMed

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Ultrafast, superhigh gain visible-blind UV detector and optical logic gates based on nonpolar a-axial GaN nanowire

NASA Astrophysics Data System (ADS)

Wang, Xingfu; Zhang, Yong; Chen, Xinman; He, Miao; Liu, Chao; Yin, Yian; Zou, Xianshao; Li, Shuti

2014-09-01

Nonpolar a-axial GaN nanowire (NW) was first used to construct the MSM (metal-semiconductor-metal) symmetrical Schottky contact device for application as visible-blind ultraviolet (UV) detector. Without any surface or composition modifications, the fabricated device demonstrated a superior performance through a combination of its high sensitivity (up to 104 A W-1) and EQE value (up to 105), as well as ultrafast (<26 ms) response speed, which indicates that a balance between the photocurrent gain and the response speed has been achieved. Based on its excellent photoresponse performance, an optical logic AND gate and OR gate have been demonstrated for performing photo-electronic coupled logic devices by further integrating the fabricated GaN NW detectors, which logically convert optical signals to electrical signals in real time. These results indicate the possibility of using a nonpolar a-axial GaN NW not only as a high performance UV detector, but also as a stable optical logic device, both in light-wave communications and for future memory storage.Nonpolar a-axial GaN nanowire (NW) was first used to construct the MSM (metal-semiconductor-metal) symmetrical Schottky contact device for application as visible-blind ultraviolet (UV) detector. Without any surface or composition modifications, the fabricated device demonstrated a superior performance through a combination of its high sensitivity (up to 104 A W-1) and EQE value (up to 105), as well as ultrafast (<26 ms) response speed, which indicates that a balance between the photocurrent gain and the response speed has been achieved. Based on its excellent photoresponse performance, an optical logic AND gate and OR gate have been demonstrated for performing photo-electronic coupled logic devices by further integrating the fabricated GaN NW detectors, which logically convert optical signals to electrical signals in real time. These results indicate the possibility of using a nonpolar a-axial GaN NW not only as a high performance UV detector, but also as a stable optical logic device, both in light-wave communications and for future memory storage. Electronic supplementary information (ESI) available: Details of the EDS and SAED data, supplementary results of the UV detector, and the discussion of the transport properties of the MSM Schottky contact devices. See DOI: 10.1039/c4nr03581j

AlGaN/GaN high electron mobility transistors with selective area grown p-GaN gates

NASA Astrophysics Data System (ADS)

Yuliang, Huang; Lian, Zhang; Zhe, Cheng; Yun, Zhang; Yujie, Ai; Yongbing, Zhao; Hongxi, Lu; Junxi, Wang; Jinmin, Li

2016-11-01

We report a selective area growth (SAG) method to define the p-GaN gate of AlGaN/GaN high electron mobility transistors (HEMTs) by metal-organic chemical vapor deposition. Compared with Schottky gate HEMTs, the SAG p-GaN gate HEMTs show more positive threshold voltage (V th) and better gate control ability. The influence of Cp2Mg flux of SAG p-GaN gate on the AlGaN/GaN HEMTs has also been studied. With the increasing Cp2Mg from 0.16 μmol/min to 0.20 μmol/min, the V th raises from -0.67 V to -0.37 V. The maximum transconductance of the SAG HEMT at a drain voltage of 10 V is 113.9 mS/mm while that value of the Schottky HEMT is 51.6 mS/mm. The SAG method paves a promising way for achieving p-GaN gate normally-off AlGaN/GaN HEMTs without dry etching damage. Project supported by the National Natural Sciences Foundation of China (Nos. 61376090, 61306008) and the National High Technology Program of China (No. 2014AA032606).

Structure of a eukaryotic cyclic nucleotide-gated channel

PubMed Central

Li, Minghui; Zhou, Xiaoyuan; Wang, Shu; Michailidis, Ioannis; Gong, Ye; Su, Deyuan; Li, Huan; Li, Xueming; Yang, Jian

2018-01-01

Summary Cyclic nucleotide-gated (CNG) channels are essential for vision and olfaction. They belong to the voltage-gated ion channel superfamily but their activities are controlled by intracellular cyclic nucleotides instead of transmembrane voltage. Here we report a 3.5 Å-resolution single-particle electron cryomicroscopy structure of a CNG channel from C. elegans in the cGMP-bound open state. The channel has an unusual voltage-sensor-like domain (VSLD), accounting for its deficient voltage dependence. A C-terminal linker connecting S6 and the cyclic nucleotide-binding domain interacts directly with both the VSLD and pore domain, forming a gating ring that couples conformational changes triggered by cyclic nucleotide binding to the gate. The selectivity filter is lined by the carboxylate side chains of a functionally important glutamate and three rings of backbone carbonyls. This structure provides a new framework for understanding mechanisms of ion permeation, gating and channelopathy of CNG channels and cyclic nucleotide modulation of related channels. PMID:28099415

Zeolitic imidazolate framework-7: Novel ammonia atmosphere-assisted synthesis, thermal and chemical durability, phase reversibility and potential as highly efficient nanophotocatalyst

NASA Astrophysics Data System (ADS)

Ebrahimi, Arash; Mansournia, Mohammadreza

2018-07-01

This is the first representation of novel sodalite zeolitic imidazolate framework-7 (ZIF-7) which has been made in ethanolic solution at room temperature via an ammonia atmosphere. High thermal stability up to 400 °C is representative of great persistence which has been proved by XRD and TG data. Chemical durability of the as-made ZIF-7 especially at boiled DMF exhibited by XRD patterns can present it as an interesting material without structural alteration after treatment in such harsh condition. Reversible phase transformation of ZIF-7 was totally checked by immersing in ethanol and DMF indicated that the framework can maintain its structural flexibility under heat and solvent treatment. Moreover, the "gate-opening" phenomenon performed by CO2 adsorption-desorption reveals structural breathing effect of ZIF-7 framework that makes it as potential material in CO2 adsorption/separation. In the end, the sacrificial metal-doped (Mn2+, Ni2+, Cu2+, Cd2+ and Ag+) ZIF-7 precursors were applied for preparation of their corresponded metal-doped ZnO as the heterogeneous catalyst to degrade Rhodamine-B (RhB) dye in water under UV-irradiation (up to 99% within 90 min by 0.5% Ag-ZnO (S15)). The recyclability experiment after 5 runs for the optimized catalyst demonstrated that the metal-doped ZnO can be operated consecutively without remarkable decreasing in its activity. These observations exhibit the excellent and beneficial properties of metal-doped ZnO can be as heterogeneous photocatalyst for the removal of organic contaminants in water.

High- k Gate Dielectrics for Emerging Flexible and Stretchable Electronics.

PubMed

Wang, Binghao; Huang, Wei; Chi, Lifeng; Al-Hashimi, Mohammed; Marks, Tobin J; Facchetti, Antonio

2018-05-22

Recent advances in flexible and stretchable electronics (FSE), a technology diverging from the conventional rigid silicon technology, have stimulated fundamental scientific and technological research efforts. FSE aims at enabling disruptive applications such as flexible displays, wearable sensors, printed RFID tags on packaging, electronics on skin/organs, and Internet-of-things as well as possibly reducing the cost of electronic device fabrication. Thus, the key materials components of electronics, the semiconductor, the dielectric, and the conductor as well as the passive (substrate, planarization, passivation, and encapsulation layers) must exhibit electrical performance and mechanical properties compatible with FSE components and products. In this review, we summarize and analyze recent advances in materials concepts as well as in thin-film fabrication techniques for high- k (or high-capacitance) gate dielectrics when integrated with FSE-compatible semiconductors such as organics, metal oxides, quantum dot arrays, carbon nanotubes, graphene, and other 2D semiconductors. Since thin-film transistors (TFTs) are the key enablers of FSE devices, we discuss TFT structures and operation mechanisms after a discussion on the needs and general requirements of gate dielectrics. Also, the advantages of high- k dielectrics over low- k ones in TFT applications were elaborated. Next, after presenting the design and properties of high- k polymers and inorganic, electrolyte, and hybrid dielectric families, we focus on the most important fabrication methodologies for their deposition as TFT gate dielectric thin films. Furthermore, we provide a detailed summary of recent progress in performance of FSE TFTs based on these high- k dielectrics, focusing primarily on emerging semiconductor types. Finally, we conclude with an outlook and challenges section.

The polar T1 interface is linked to conformational changes that open the voltage-gated potassium channel.

PubMed

Minor, D L; Lin, Y F; Mobley, B C; Avelar, A; Jan, Y N; Jan, L Y; Berger, J M

2000-09-01

Kv voltage-gated potassium channels share a cytoplasmic assembly domain, T1. Recent mutagenesis of two T1 C-terminal loop residues implicates T1 in channel gating. However, structural alterations of these mutants leave open the question concerning direct involvement of T1 in gating. We find in mammalian Kv1.2 that gating depends critically on residues at complementary T1 surfaces in an unusually polar interface. An isosteric mutation in this interface causes surprisingly little structural alteration while stabilizing the closed channel and increasing the stability of T1 tetramers. Replacing T1 with a tetrameric coiled-coil destabilizes the closed channel. Together, these data suggest that structural changes involving the buried polar T1 surfaces play a key role in the conformational changes leading to channel opening.

Asymmetrical field emitter

DOEpatents

Fleming, J.G.; Smith, B.K.

1995-10-10

A method is disclosed for providing a field emitter with an asymmetrical emitter structure having a very sharp tip in close proximity to its gate. One preferred embodiment of the present invention includes an asymmetrical emitter and a gate. The emitter having a tip and a side is coupled to a substrate. The gate is connected to a step in the substrate. The step has a top surface and a side wall that is substantially parallel to the side of the emitter. The tip of the emitter is in close proximity to the gate. The emitter is at an emitter potential, and the gate is at a gate potential such that with the two potentials at appropriate values, electrons are emitted from the emitter. In one embodiment, the gate is separated from the emitter by an oxide layer, and the emitter is etched anisotropically to form its tip and its asymmetrical structure. 17 figs.

Piezophototronic Effect in Single-Atomic-Layer MoS2 for Strain-Gated Flexible Optoelectronics.

PubMed

Wu, Wenzhuo; Wang, Lei; Yu, Ruomeng; Liu, Yuanyue; Wei, Su-Huai; Hone, James; Wang, Zhong Lin

2016-10-01

Strain-gated flexible optoelectronics are reported based on monolayer MoS 2 . Utilizing the piezoelectric polarization created at the metal-MoS 2 interface to modulate the separation/transport of photogenerated carriers, the piezophototronic effect is applied to implement atomic-layer-thick phototransistor. Coupling between piezoelectricity and photogenerated carriers may enable the development of novel optoelectronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Initial Plasma Testing of the Ion Proportional Surface Emission Cathode

DTIC Science & Technology

2008-07-15

REPRINT 3. DATES COVERED (From - To) 4. TITLE AND SUBTITLE Initial Plasma Testing of the Ion Proportional Surface Emission Cathode 5a. CONTRACT NUMBER...substrate and an adjacent metal cathode element. The substrate potential is held positive of the cathode with gate elements. In plasma , the gate is...eliminated due to ambient ion flux which maintains the substrate potential near plasma ground. Prototype devices have been tested using a laboratory plasma

HgCdTe Surface and Defect Study Program.

DTIC Science & Technology

1983-07-01

RESkSTIVITY. Rm T 10 12 10> 9 i0 1 0 9 I i i i i TI/Au TI AI/Ni Ti/Ni In GATE METAL Figure 8. The Effect of Gate " fetal Type on dc Resistivity of 1500.4...2. J.A. Wilson, V.A. Cotton, J.A. Silkerman, 0. Lacer , W.E. Spicer and P. Morgen, J. Vac. Sci. Tech., Al (1983), 1719. 3. B.K. Janorsek, R.C

Electron lithography STAR design guidelines. Part 1: The STAR user design manual

NASA Technical Reports Server (NTRS)

Trotter, J. D.; Newman, W.

1982-01-01

The STAR system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computer programs to place, route, and display designs implemented with cells from the library. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Leakage current conduction, hole injection, and time-dependent dielectric breakdown of n-4H-SiC MOS capacitors during positive bias temperature stress

NASA Astrophysics Data System (ADS)

Samanta, Piyas; Mandal, Krishna C.

2017-01-01

The conduction mechanism(s) of gate leakage current JG through thermally grown silicon dioxide (SiO2) films on the silicon (Si) face of n-type 4H-silicon carbide (4H-SiC) has been studied in detail under positive gate bias. It was observed that at an oxide field above 5 MV/cm, the leakage current measured up to 303 °C can be explained by Fowler-Nordheim (FN) tunneling of electrons from the accumulated n-4H-SiC and Poole-Frenkel (PF) emission of trapped electrons from the localized neutral traps located at ≈2.5 eV below the SiO2 conduction band. However, the PF emission current IPF dominates the FN electron tunneling current IFN at oxide electric fields Eox between 5 and 10 MV/cm and in the temperature ranging from 31 to 303 °C. In addition, we have presented a comprehensive analysis of injection of holes and their subsequent trapping into as-grown oxide traps eventually leading to time-dependent dielectric breakdown during electron injection under positive bias temperature stress (PBTS) in n-4H-SiC metal-oxide-silicon carbide structures. Holes were generated in the heavily doped n-type polycrystalline silicon (n+-polySi) gate (anode) as well as in the oxide bulk via band-to-band ionization by the hot-electrons depending on their energy and SiO2 film thickness at Eox between 6 and 10 MV/cm (prior to the intrinsic oxide breakdown field). Transport of hot electrons emitted via both FN and PF mechanisms was taken into account. On the premise of the hole-induced oxide breakdown model, the time- and charge-to-breakdown ( tBD and QBD ) of 8.5 to 47 nm-thick SiO2 films on n-4H-SiC were estimated at a wide range of temperatures. tBD follows the Arrhenius law with activation energies varying inversely with initial applied constant field Eox supporting the reciprocal field ( 1 /E ) model of breakdown irrespective of SiO2 film thicknesses. We obtained an excellent margin (6.66 to 6.33 MV/cm at 31 °C and 5.11 to 4.55 MV/cm at 303 °C) of normal operating field for a 10-year projected lifetime of 8.5 to 47 nm-thick SiO2 films on n-4H-SiC under positive bias on the n+-polySi gate. Furthermore, the projected maximum operating oxide field was little higher in metal gate devices compared to n+-polySi gate devices having an identically thick thermal SiO2 films under PBTS.

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure

NASA Astrophysics Data System (ADS)

Chen, Meng; Lei, Jiefeng; Huang, Shengxiang; Liao, Congwei; Deng, Lianwen

2017-06-01

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive {V}{TH} shift within 0.4 V and negative {V}{TH} shift within -1.2 V and it is robust and promising for high-resolution display. Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

Thermal stability of atomic layer deposited WCxNy electrodes for metal oxide semiconductor devices

NASA Astrophysics Data System (ADS)

Zonensain, Oren; Fadida, Sivan; Fisher, Ilanit; Gao, Juwen; Danek, Michal; Eizenberg, Moshe

2018-01-01

This study is a thorough investigation of the chemical, structural, and electrical stability of W based organo-metallic films, grown by atomic layer deposition, for future use as gate electrodes in advanced metal oxide semiconductor structures. In an earlier work, we have shown that high effective work-function (4.7 eV) was produced by nitrogen enriched films (WCxNy) dominated by W-N chemical bonding, and low effective work-function (4.2 eV) was produced by hydrogen plasma resulting in WCx films dominated by W-C chemical bonding. In the current work, we observe, using x-ray diffraction analysis, phase transformation of the tungsten carbide and tungsten nitride phases after 900 °C annealing to the cubic tungsten phase. Nitrogen diffusion is also observed and is analyzed with time-of-flight secondary ion mass spectroscopy. After this 900 °C anneal, WCxNy effective work function tunability is lost and effective work-function values of 4.7-4.8 eV are measured, similar to stable effective work function values measured for PVD TiN up to 900 °C anneal. All the observed changes after annealing are discussed and correlated to the observed change in the effective work function.

Mechanism of Cd2+-coordination during Slow Inactivation in Potassium Channels

PubMed Central

Raghuraman, H.; Cordero-Morales, Julio F.; Jogini, Vishwanath; Pan, Albert C.; Kollewe, Astrid; Roux, Benoît; Perozo, Eduardo

2013-01-01

Summary In K+ channels, rearrangements of the pore outer-vestibule have been associated with C-type inactivation gating. Paradoxically, the crystal structure of Open/C-type inactivated KcsA suggest these movements to be modest in magnitude. Here, we show that under physiological conditions, the KcsA outer-vestibule undergoes relatively large dynamic rearrangements upon inactivation. External Cd2+ enhances the rate of C-type inactivation in an outer-vestibule cysteine mutant (Y82C) via metal-bridge formation. This effect is not present in a non-inactivating mutant (E71A/Y82C). Tandem dimer and tandem tetramer constructs of equivalent cysteine mutants in KcsA and Shaker K+ channels demonstrate that these Cd2+ metal bridges are formed only between adjacent subunits. This is well supported by molecular dynamics simulations. Based on the crystal structure of Cd2+-bound Y82C-KcsA in the closed state, together with EPR distance measurements in the KcsA outer-vestibule, we suggest that subunits must dynamically come in close proximity as the channels undergo inactivation. PMID:22771214

Monolithic integration of GaN-based light-emitting diodes and metal-oxide-semiconductor field-effect transistors.

PubMed

Lee, Ya-Ju; Yang, Zu-Po; Chen, Pin-Guang; Hsieh, Yung-An; Yao, Yung-Chi; Liao, Ming-Han; Lee, Min-Hung; Wang, Mei-Tan; Hwang, Jung-Min

2014-10-20

In this study, we report a novel monolithically integrated GaN-based light-emitting diode (LED) with metal-oxide-semiconductor field-effect transistor (MOSFET). Without additionally introducing complicated epitaxial structures for transistors, the MOSFET is directly fabricated on the exposed n-type GaN layer of the LED after dry etching, and serially connected to the LED through standard semiconductor-manufacturing technologies. Such monolithically integrated LED/MOSFET device is able to circumvent undesirable issues that might be faced by other kinds of integration schemes by growing a transistor on an LED or vice versa. For the performances of resulting device, our monolithically integrated LED/MOSFET device exhibits good characteristics in the modulation of gate voltage and good capability of driving injected current, which are essential for the important applications such as smart lighting, interconnection, and optical communication.

Interface engineering of quantum Hall effects in digital transition metal oxide heterostructures.

PubMed

Xiao, Di; Zhu, Wenguang; Ran, Ying; Nagaosa, Naoto; Okamoto, Satoshi

2011-12-20

Topological insulators are characterized by a non-trivial band topology driven by the spin-orbit coupling. To fully explore the fundamental science and application of topological insulators, material realization is indispensable. Here we predict, based on tight-binding modelling and first-principles calculations, that bilayers of perovskite-type transition-metal oxides grown along the [111] crystallographic axis are potential candidates for two-dimensional topological insulators. The topological band structure of these materials can be fine-tuned by changing dopant ions, substrates and external gate voltages. We predict that LaAuO(3) bilayers have a topologically non-trivial energy gap of about 0.15 eV, which is sufficiently large to realize the quantum spin Hall effect at room temperature. Intriguing phenomena, such as fractional quantum Hall effect, associated with the nearly flat topologically non-trivial bands found in e(g) systems are also discussed.

Diversity of Chemical Bonding and Oxidation States in MS 4 Molecules of Group 8 Elements

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang, Wei; Jiang, Ning; Schwarz, W. H. Eugen

The geometric and electronic ground-state structures of six MS 4 molecules (M = group-8 metals Fe, Ru, Os, Hs, Sm, and Pu) have been studied by using quantum-chemical density-functional and correlated wave-function approaches. The MS 4 species are compared to analogous MO 4 species recently investi-gated (Inorg. Chem. 2016, 55: 4616). Metal oxidation state (MOS) of high value VIII appears in low- spin singlet Td geometric species (Os,Hs)S 4 and (Ru,Os,Hs)O 4, whereas low MOS=II appears in high- spin septet D 2d species Fe(S 2) 2 and (slightly excited) metastable Fe(O 2) 2. The ground states of all other moleculesmore » have intermediate MOS values, containing S 2-, S 2 2-, S2 1- (and resp. O 2--, O 1-, O 2 2-, O 2 1-) ligands, bonded by ionic, covalent and correlative contributions.« less

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability

NASA Astrophysics Data System (ADS)

Li, Weiyi; Zhang, Zhili; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Sun, Shichuang; Song, Liang; Hao, Ronghui; Fan, Yaming; Cai, Yong; Zhang, Baoshun

2017-07-01

We proposed a novel AlGaN/GaN enhancement-mode (E-mode) high electron mobility transistor (HEMT) with a dual-gate structure and carried out the detailed numerical simulation of device operation using Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The simulation results show that electric field under the gate is decreased by more than 70% compared to that of the conventional E-mode MIS-HEMTs (from 2.83 MV/cm decreased to 0.83 MV/cm). Thus, with the discussion of ionized trap density, the proposed dual-gate structure can highly improve electric field-related reliability, such as, threshold voltage stability. In addition, compared with HEMT with field plate structure, the proposed structure exhibits a simplified fabrication process and a more effective suppression of high electric field. Project supported by the Key Technologies Support Program of Jiangsu Province (No. BE2013002-2) and the National Key Scientific Instrument and Equipment Development Projects of China (No. 2013YQ470767).

Process development of beam-lead silicon-gate COS/MOS integrated circuits

NASA Technical Reports Server (NTRS)

Baptiste, B.; Boesenberg, W.

1974-01-01

Two processes for the fabrication of beam-leaded COS/MOS integrated circuits are described. The first process utilizes a composite gate dielectric of 800 A of silicon dioxide and 450 A of pyrolytically deposited A12O3 as an impurity barrier. The second process utilizes polysilicon gate metallization over which a sealing layer of 1000 A of pyrolytic Si3N4 is deposited. Three beam-lead integrated circuits have been implemented with the first process: (1) CD4000BL - three-input NOR gate; (2) CD4007BL - triple inverter; and (3) CD4013BL - dual D flip flop. An arithmetic and logic unit (ALU) integrated circuit was designed and implemented with the second process. The ALU chip allows addition with four bit accuracy. Processing details, device design and device characterization, circuit performance and life data are presented.

Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

NASA Astrophysics Data System (ADS)

ShuXiang, Zhang; Hong, Yang; Bo, Tang; Zhaoyun, Tang; Yefeng, Xu; Jing, Xu; Jiang, Yan

2014-10-01

ALD HfO2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D&A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D&A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

Influence of gate overlap engineering on ambipolar and high frequency characteristics of tunnel-CNTFET

NASA Astrophysics Data System (ADS)

Shaker, Ahmed; Ossaimee, Mahmoud; Zekry, A.; Abouelatta, Mohamed

2015-10-01

In this paper, we have investigated the effect of gate overlapping-on-drain on the ambipolar behavior and high frequency performance of tunnel CNTFET (T-CNTFET). It is found that gate overlapping-on-drain suppresses the ambipolar behavior and improves OFF-state current. The simulation results show that there is an optimum choice for the overlapped length. On the other hand, this overlap deteriorates the high frequency performance. The high frequency figure of merit is analyzed in terms of the unit-gain cutoff frequency (fT). Further, we propose two different approaches to improve the high frequency performance of the overlapped T-CNTFET. The first one is based on inserting a high-dielectric constant material below the overlapped part of the gate and the second is based on depositing a different work function gate metal for the overlapped region. The two solutions show very good improvement in the high frequency performance with maintaining the suppression of the ambipolar characteristics.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

2017-06-01

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

An extensive investigation of work function modulated trapezoidal recessed channel MOSFET

NASA Astrophysics Data System (ADS)

Lenka, Annada Shankar; Mishra, Sikha; Mishra, Satyaranjan; Bhanja, Urmila; Mishra, Guru Prasad

2017-11-01

The concept of silicon on insulator (SOI) and grooved gate help to lessen the short channel effects (SCEs). Again the work function modulation along the metal gate gives a better drain current due to the uniform electric field along the channel. So all these concepts are combined and used in the proposed MOSFET structure for more improved performance. In this work, trapezoidal recessed channel silicon on insulator (TRC-SOI) MOSFET and work function modulated trapezoidal recessed channel silicon on insulator (WFM-TRC-SOI) MOSFET are compared with DC and RF parameters and later linearity of both the devices is tested. An analytical model is formulated by using a 2-D Poisson's equation and develops a compact equation for threshold voltage using minimum surface potential. In this work we analyze the effect of negative junction depth and the corner angle on various device parameters such as minimum surface potential, sub-threshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage. The analysis interprets that the switching performance of WFM-TRC-SOI MOSFET surpasses TRC-SOI MOSFET in terms of high Ion/Ioff ratio and also the proposed structure can minimize the short channel effects (SCEs) in RF application. The validity of proposed model has been verified with simulation result performed on Sentaurus TCAD device simulator.

Field calibration of submerged sluice gates in irrigation canals

USDA-ARS?s Scientific Manuscript database

Four rectangular sluice gates were calibrated for submerged-flow conditions using nearly 16,000 field-measured data points on Canal B of the B-XII irrigation scheme in Lebrija, Spain. Water depth and gate opening values were measured using acoustic sensors at each of the gate structures, and the dat...

Investigation of defect-induced abnormal body current in fin field-effect-transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, Kuan-Ju; Tsai, Jyun-Yu; Lu, Ying-Hsin

2015-08-24

This letter investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack fin field effect transistors. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.

Cyclical Annealing Technique To Enhance Reliability of Amorphous Metal Oxide Thin Film Transistors.

PubMed

Chen, Hong-Chih; Chang, Ting-Chang; Lai, Wei-Chih; Chen, Guan-Fu; Chen, Bo-Wei; Hung, Yu-Ju; Chang, Kuo-Jui; Cheng, Kai-Chung; Huang, Chen-Shuo; Chen, Kuo-Kuang; Lu, Hsueh-Hsing; Lin, Yu-Hsin

2018-02-26

This study introduces a cyclical annealing technique that enhances the reliability of amorphous indium-gallium-zinc-oxide (a-IGZO) via-type structure thin film transistors (TFTs). By utilizing this treatment, negative gate-bias illumination stress (NBIS)-induced instabilities can be effectively alleviated. The cyclical annealing provides several cooling steps, which are exothermic processes that can form stronger ionic bonds. An additional advantage is that the total annealing time is much shorter than when using conventional long-term annealing. With the use of cyclical annealing, the reliability of the a-IGZO can be effectively optimized, and the shorter process time can increase fabrication efficiency.

Highly Efficient Spin-Current Operation in a Cu Nano-Ring

NASA Astrophysics Data System (ADS)

Murphy, Benedict A.; Vick, Andrew J.; Samiepour, Marjan; Hirohata, Atsufumi

2016-11-01

An all-metal lateral spin-valve structure has been fabricated with a medial Copper nano-ring to split the diffusive spin-current path. We have demonstrated significant modulation of the non-local signal by the application of a magnetic field gradient across the nano-ring, which is up to 30% more efficient than the conventional Hanle configuration at room temperature. This was achieved by passing a dc current through a current-carrying bar to provide a locally induced Ampère field. We have shown that in this manner a lateral spin-valve gains an additional functionality in the form of three-terminal gate operation for future spintronic logic.

Effect of water current on the distribution of polycyclic aromatic hydrocarbons, heavy metals and benthic diatom community in sediments of Haihe estuary, China.

PubMed

Yan, Jinxia; Liu, Jingling; Li, Yi; Lang, Sisi

2014-10-01

The pollution loads continuously increased in Haihe estuary, of Tianjin, China, due to intensive human activities, especially the construction of the Haihe Gate and Lingang Industrial Area. In 2011, hydrological variability in Haihe estuary was investigated and sediments were collected. Total organic carbon (TOC), particle size, total polycyclic aromatic hydrocarbons (ΣPAHs), heavy metals (Cd, Cr, Cu, Ni, Pb, and Zn), and benthic diatom community were analyzed. The highest concentrations of ΣPAHs and heavy metals were found near the Haihe Gate. The Shannon diversity index and the relative abundance of Coscinodiscus perforatus (RC) indicated a decreasing trend seaward. Results of Pearson correlation analysis illustrated significant relations between water current velocity and ΣPAHs (p < 0.01), Cr (p < 0.05), and RC (p < 0.05). Path analysis further indicated that water current played an important role in the distribution of PAH, Cr, and RC.

Photocurrent measurements in Coupled Quantum Well van der Waals Heterostructures made of 2D Transition Metal Dichalcogenides

NASA Astrophysics Data System (ADS)

Joe, Andrew; Jauregui, Luis; High, Alex; Dibos, Alan; Gulpinar, Elgin; Pistunova, Kateryna; Park, Hongkun; Kim, Philip

, Luis A. Jauregui, Alex A. High, Alan Dibos, Elgin Gulpinar, Kateryna Pistunova, Hongkun Park, Philip Kim Harvard University, Physics Department -abstract- Single layer transition metal dichalcogenides (TMDC) are 2-dimensional (2D) semiconductors van der Waals (vdW) characterized by a direct optical bandgap in the visible wavelength (~2 eV). Characterization of the band alignment between TMDC and the barrier is important for the fabrication of tunneling devices. Here, we fabricate coupled quantum well (CQW) heterostructures made of 2D TMDCs with hexagonal Boron nitride (hBN) as an atomically thin barrier and gate dielectric and with top and bottom metal (or graphite) as gate electrodes. We observe a clear dependence of the photo-generated current with varying hBN thickness, electrode workfunctions, electric field, laser excitation power, excitation wavelength, and temperature. We will discuss the implication of photocurrent in relation to quantum transport process across the vdW interfaces.

Assembly and stoichiometry of the core structure of the bacterial flagellar type III export gate complex.

PubMed

Fukumura, Takuma; Makino, Fumiaki; Dietsche, Tobias; Kinoshita, Miki; Kato, Takayuki; Wagner, Samuel; Namba, Keiichi; Imada, Katsumi; Minamino, Tohru

2017-08-01

The bacterial flagellar type III export apparatus, which is required for flagellar assembly beyond the cell membranes, consists of a transmembrane export gate complex and a cytoplasmic ATPase complex. FlhA, FlhB, FliP, FliQ, and FliR form the gate complex inside the basal body MS ring, although FliO is required for efficient export gate formation in Salmonella enterica. However, it remains unknown how they form the gate complex. Here we report that FliP forms a homohexameric ring with a diameter of 10 nm. Alanine substitutions of conserved Phe-137, Phe-150, and Glu-178 residues in the periplasmic domain of FliP (FliPP) inhibited FliP6 ring formation, suppressing flagellar protein export. FliO formed a 5-nm ring structure with 3 clamp-like structures that bind to the FliP6 ring. The crystal structure of FliPP derived from Thermotoga maritia, and structure-based photo-crosslinking experiments revealed that Phe-150 and Ser-156 of FliPP are involved in the FliP-FliP interactions and that Phe-150, Arg-152, Ser-156, and Pro-158 are responsible for the FliP-FliO interactions. Overexpression of FliP restored motility of a ∆fliO mutant to the wild-type level, suggesting that the FliP6 ring is a functional unit in the export gate complex and that FliO is not part of the final gate structure. Copurification assays revealed that FlhA, FlhB, FliQ, and FliR are associated with the FliO/FliP complex. We propose that the assembly of the export gate complex begins with FliP6 ring formation with the help of the FliO scaffold, followed by FliQ, FliR, and FlhB and finally FlhA during MS ring formation.

Assembly and stoichiometry of the core structure of the bacterial flagellar type III export gate complex

PubMed Central

Fukumura, Takuma; Makino, Fumiaki; Dietsche, Tobias; Kinoshita, Miki; Kato, Takayuki; Wagner, Samuel; Namba, Keiichi; Imada, Katsumi

2017-01-01

The bacterial flagellar type III export apparatus, which is required for flagellar assembly beyond the cell membranes, consists of a transmembrane export gate complex and a cytoplasmic ATPase complex. FlhA, FlhB, FliP, FliQ, and FliR form the gate complex inside the basal body MS ring, although FliO is required for efficient export gate formation in Salmonella enterica. However, it remains unknown how they form the gate complex. Here we report that FliP forms a homohexameric ring with a diameter of 10 nm. Alanine substitutions of conserved Phe-137, Phe-150, and Glu-178 residues in the periplasmic domain of FliP (FliPP) inhibited FliP6 ring formation, suppressing flagellar protein export. FliO formed a 5-nm ring structure with 3 clamp-like structures that bind to the FliP6 ring. The crystal structure of FliPP derived from Thermotoga maritia, and structure-based photo-crosslinking experiments revealed that Phe-150 and Ser-156 of FliPP are involved in the FliP–FliP interactions and that Phe-150, Arg-152, Ser-156, and Pro-158 are responsible for the FliP–FliO interactions. Overexpression of FliP restored motility of a ∆fliO mutant to the wild-type level, suggesting that the FliP6 ring is a functional unit in the export gate complex and that FliO is not part of the final gate structure. Copurification assays revealed that FlhA, FlhB, FliQ, and FliR are associated with the FliO/FliP complex. We propose that the assembly of the export gate complex begins with FliP6 ring formation with the help of the FliO scaffold, followed by FliQ, FliR, and FlhB and finally FlhA during MS ring formation. PMID:28771466

The prospects of transition metal dichalcogenides for ultimately scaled CMOS

NASA Astrophysics Data System (ADS)

Thiele, S.; Kinberger, W.; Granzner, R.; Fiori, G.; Schwierz, F.

2018-05-01

MOSFET gate length scaling has been a main source of progress in digital electronics for decades. Today, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs, thereby exploring both new device architectures and alternative channel materials beyond Silicon such as two-dimensional TMDs (transition metal dichalcogenide). On the other hand, the envisaged scaling scenario for the next 15 years has undergone a significant change recently. While the 2013 ITRS edition required a continuation of aggressive gate length scaling for at least another 15 years, the 2015 edition of the ITRS suggests a deceleration and eventually a levelling off of gate length scaling and puts more emphasis on alternative options such as pitch scaling to keep Moore's Law alive. In the present paper, future CMOS scaling is discussed in the light of emerging two-dimensional MOSFET channel, in particular two-dimensional TMDs. To this end, the scaling scenarios of the 2013 and 2015 ITRS editions are considered and the scaling potential of TMD MOSFETs is investigated by means of quantum-mechanical device simulations. It is shown that for ultimately scaled MOSFETs as required in the 2013 ITRS, the heavy carrier effective masses of the Mo- and W-based TMDs are beneficial for the suppression of direct source-drain tunneling, while to meet the significantly relaxed scaling targets of the 2016 ITRS heavy-effective-mass channels are not needed.

Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

NASA Astrophysics Data System (ADS)

Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

2016-04-01

In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

NASA Astrophysics Data System (ADS)

Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

2015-05-01

This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

Structures of closed and open states of a voltage-gated sodium channel

PubMed Central

Lenaeus, Michael J.; Gamal El-Din, Tamer M.; Ramanadane, Karthik; Pomès, Régis; Zheng, Ning; Catterall, William A.

2017-01-01

Bacterial voltage-gated sodium channels (BacNavs) serve as models of their vertebrate counterparts. BacNavs contain conserved voltage-sensing and pore-forming domains, but they are homotetramers of four identical subunits, rather than pseudotetramers of four homologous domains. Here, we present structures of two NaVAb mutants that capture tightly closed and open states at a resolution of 2.8–3.2 Å. Introduction of two humanizing mutations in the S6 segment (NaVAb/FY: T206F and V213Y) generates a persistently closed form of the activation gate in which the intracellular ends of the four S6 segments are drawn tightly together to block ion permeation completely. This construct also revealed the complete structure of the four-helix bundle that forms the C-terminal domain. In contrast, truncation of the C-terminal 40 residues in NavAb/1–226 captures the activation gate in an open conformation, revealing the open state of a BacNav with intact voltage sensors. Comparing these structures illustrates the full range of motion of the activation gate, from closed with its orifice fully occluded to open with an orifice of ∼10 Å. Molecular dynamics and free-energy simulations confirm designation of NaVAb/1–226 as an open state that allows permeation of hydrated Na+, and these results also support a hydrophobic gating mechanism for control of ion permeation. These two structures allow completion of a closed–open–inactivated conformational cycle in a single voltage-gated sodium channel and give insight into the structural basis for state-dependent binding of sodium channel-blocking drugs. PMID:28348242

Geometric dependence of the parasitic components and thermal properties of HEMTs

NASA Astrophysics Data System (ADS)

Vun, Peter V.; Parker, Anthony E.; Mahon, Simon J.; Fattorini, Anthony

2007-12-01

For integrated circuit design up to 50GHz and beyond accurate models of the transistor access structures and intrinsic structures are necessary for prediction of circuit performance. The circuit design process relies on optimising transistor geometry parameters such as unit gate width, number of gates, number of vias and gate-to-gate spacing. So the relationship between electrical and thermal parasitic components in transistor access structures, and transistor geometry is important to understand when developing models for transistors of differing geometries. Current approaches to describing the geometric dependence of models are limited to empirical methods which only describe a finite set of geometries and only include unit gate width and number of gates as variables. A better understanding of the geometric dependence is seen as a way to provide scalable models that remain accurate for continuous variation of all geometric parameters. Understanding the distribution of parasitic elements between the manifold, the terminal fingers, and the reference plane discontinuities is an issue identified as important in this regard. Examination of dc characteristics and thermal images indicates that gate-to-gate thermal coupling and increased thermal conductance at the gate ends, affects the device total thermal conductance. Consequently, a distributed thermal model is proposed which accounts for these effects. This work is seen as a starting point for developing comprehensive scalable models that will allow RF circuit designers to optimise circuit performance parameters such as total die area, maximum output power, power-added-efficiency (PAE) and channel temperature/lifetime.

Modal Analysis of a Steel Radial Gate Exposed to Different Water Levels

NASA Astrophysics Data System (ADS)

Brusewicz, Krzysztof; Sterpejkowicz-Wersocki, Witold; Jankowski, Robert

2017-06-01

With the increase in water retention needs and planned river regulation, it might be important to investigate the dynamic resistance of vulnerable elements of hydroelectric power plants, including steelwater locks. The most frequent dynamic loads affecting hydroengineering structures in Poland include vibrations caused by heavy road and railway traffic, piling works and mining tremors. More destructive dynamic loads, including earthquakes, may also occur in our country, although their incidence is relatively low. However, given the unpredictable nature of such events, as well as serious consequences they might cause, the study of the seismic resistance of the steel water gate, as one of the most vulnerable elements of a hydroelectric power plant, seems to be important. In this study, a steel radial gate has been analyzed. As far as water gates are concerned, it is among the most popular solutions because of its relatively small weight, compared to plain gates. A modal analysis of the steel radial gate was conducted with the use of the FEM in the ABAQUS software. All structural members were modelled using shell elements with detailed geometry representing a real structure.Water was modelled as an added mass affecting the structure. Different water levels were used to determine the most vulnerable state of the working steel water gate. The results of the modal analysis allowed us to compare the frequencies and their eigenmodes in response to different loads, which is one of the first steps in researching the dynamic properties of steel water gates and their behaviour during extreme dynamic loads, including earthquakes.

Perspective: Optical measurement of feature dimensions and shapes by scatterometry

NASA Astrophysics Data System (ADS)

Diebold, Alain C.; Antonelli, Andy; Keller, Nick

2018-05-01

The use of optical scattering to measure feature shape and dimensions, scatterometry, is now routine during semiconductor manufacturing. Scatterometry iteratively improves an optical model structure using simulations that are compared to experimental data from an ellipsometer. These simulations are done using the rigorous coupled wave analysis for solving Maxwell's equations. In this article, we describe the Mueller matrix spectroscopic ellipsometry based scatterometry. Next, the rigorous coupled wave analysis for Maxwell's equations is presented. Following this, several example measurements are described as they apply to specific process steps in the fabrication of gate-all-around (GAA) transistor structures. First, simulations of measurement sensitivity for the inner spacer etch back step of horizontal GAA transistor processing are described. Next, the simulated metrology sensitivity for sacrificial (dummy) amorphous silicon etch back step of vertical GAA transistor processing is discussed. Finally, we present the application of plasmonically active test structures for improving the sensitivity of the measurement of metal linewidths.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leng, X.; Pereiro, J.; Strle, J.

Tungsten oxide and its associated bronzes (compounds of tungsten oxide and an alkali metal) are well known for their interesting optical and electrical characteristics. We have modified the transport properties of thin WO 3 films by electrolyte gating using both ionic liquids and polymer electrolytes. We are able to tune the resistivity of the gated film by more than five orders of magnitude, and a clear insulator-to-metal transition is observed. To clarify the doping mechanism, we have performed a series of incisive operando experiments, ruling out both a purely electronic effect (charge accumulation near the interface) and oxygen-related mechanisms. Wemore » propose instead that hydrogen intercalation is responsible for doping WO 3 into a highly conductive ground state and provide evidence that it can be described as a dense polaronic gas.« less

Review of mixer design for low voltage - low power applications

NASA Astrophysics Data System (ADS)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

Supramolecular regulation of bioorthogonal catalysis in cells using nanoparticle-embedded transition metal catalysts

NASA Astrophysics Data System (ADS)

Tonga, Gulen Yesilbag; Jeong, Youngdo; Duncan, Bradley; Mizuhara, Tsukasa; Mout, Rubul; Das, Riddha; Kim, Sung Tae; Yeh, Yi-Cheun; Yan, Bo; Hou, Singyuk; Rotello, Vincent M.

2015-07-01

Bioorthogonal catalysis broadens the functional possibilities of intracellular chemistry. Effective delivery and regulation of synthetic catalytic systems in cells are challenging due to the complex intracellular environment and catalyst instability. Here, we report the fabrication of protein-sized bioorthogonal nanozymes through the encapsulation of hydrophobic transition metal catalysts into the monolayer of water-soluble gold nanoparticles. The activity of these catalysts can be reversibly controlled by binding a supramolecular cucurbit[7]uril ‘gate-keeper’ onto the monolayer surface, providing a biomimetic control mechanism that mimics the allosteric regulation of enzymes. The potential of this gated nanozyme for use in imaging and therapeutic applications was demonstrated through triggered cleavage of allylcarbamates for pro-fluorophore activation and propargyl groups for prodrug activation inside living cells.

Positive and negative gain exceeding unity magnitude in silicon quantum well metal-oxide-semiconductor transistors

NASA Astrophysics Data System (ADS)

Hu, Gangyi; Wijesinghe, Udumbara; Naquin, Clint; Maggio, Ken; Edwards, H. L.; Lee, Mark

2017-10-01

Intrinsic gain (AV) measurements on Si quantum well (QW) n-channel metal-oxide-semiconductor (NMOS) transistors show that these devices can have |AV| > 1 in quantum transport negative transconductance (NTC) operation at room temperature. QW NMOS devices were fabricated using an industrial 45 nm technology node process incorporating ion implanted potential barriers to define a lateral QW in the conduction channel under the gate. While NTC at room temperature arising from transport through gate-controlled QW bound states has been previously established, it was unknown whether the quantum NTC mechanism could support gain magnitude exceeding unity. Bias conditions were found giving both positive and negative AV with |AV| > 1 at room temperature. This result means that QW NMOS devices could be useful in amplifier and oscillator applications.

Chronic Manganese Toxicity Associated with Voltage-Gated Potassium Channel Complex Antibodies in a Relapsing Neuropsychiatric Disorder

PubMed Central

Ho, Cyrus S.H.; Quek, Amy M.L.

2018-01-01

Heavy metal poisoning is a rare but important cause of encephalopathy. Manganese (Mn) toxicity is especially rare in the modern world, and clinicians’ lack of recognition of its neuropsychiatric manifestations can lead to misdiagnosis and mismanagement. We describe the case of a man who presented with recurrent episodes of confusion, psychosis, dystonic limb movement and cognitive impairment and was initially diagnosed with anti-voltage-gated potassium channel (VGKC) complex limbic encephalitis in view of previous positive autoantibodies. His failure to respond to immunotherapy prompted testing for heavy metal poisoning, which was positive for Mn. This is the first report to examine an association between Mn and VGKC antibodies and the effects of Mn on functional brain activity using functional near-infrared spectroscopy (fNIRS). PMID:29669989

Chronic Manganese Toxicity Associated with Voltage-Gated Potassium Channel Complex Antibodies in a Relapsing Neuropsychiatric Disorder.

PubMed

Ho, Cyrus S H; Ho, Roger C M; Quek, Amy M L

2018-04-18

Heavy metal poisoning is a rare but important cause of encephalopathy. Manganese (Mn) toxicity is especially rare in the modern world, and clinicians’ lack of recognition of its neuropsychiatric manifestations can lead to misdiagnosis and mismanagement. We describe the case of a man who presented with recurrent episodes of confusion, psychosis, dystonic limb movement and cognitive impairment and was initially diagnosed with anti-voltage-gated potassium channel (VGKC) complex limbic encephalitis in view of previous positive autoantibodies. His failure to respond to immunotherapy prompted testing for heavy metal poisoning, which was positive for Mn. This is the first report to examine an association between Mn and VGKC antibodies and the effects of Mn on functional brain activity using functional near-infrared spectroscopy (fNIRS).

Monolithic integration of a vertical cavity surface emitting laser and a metal semiconductor field effect transistor

NASA Astrophysics Data System (ADS)

Yang, Y. J.; Dziura, T. G.; Bardin, T.; Wang, S. C.; Fernandez, R.; Liao, Andrew S. H.

1993-02-01

Monolithic integration of a vertical cavity surface emitting laser (VCSEL) and a metal semiconductor field effect transistor (MESFET) is reported for the first time. The epitaxial layers for both GaAs VCSELs and MESFETs are grown on an n-type GaAs substrate by molecular-beam epitaxy at the same time. The VCSELs with a 10-micron diam active region exhibit an average threshold current (Ith) of 6 mA and a continuous wave (CW) maximum power of 1.1 mW. The MESFETs with a 3-micron gate length have a transconductance of 50 mS/mm. The laser output is modulated by the gate voltage of the MESFETs and exhibits an optical/electrical conversion factor of 0.5 mW/V.