Suppression of Leakage Current of Metal-Insulator-Semiconductor Ta2O5 Capacitors with Al2O3/SiON Buffer Layer

NASA Astrophysics Data System (ADS)

Tonomura, Osamu; Miki, Hiroshi; Takeda, Ken-ichi

2011-10-01

An Al2O3/SiO buffer layer was incorporated in a metal-insulator-semiconductor (MIS) Ta2O5 capacitor for dynamic random access memory (DRAM) application. Al2O3 was chosen for the buffer layer owing to its high band offset against silicon and oxidation resistance against increase in effective oxide thickness (EOT). It was clarified that post-deposition annealing in nitrogen at 800 °C for 600 s increased the band offset between Al2O3 and the lower electrode and decreased leakage current by two orders of magnitude at 1 V. Furthermore, we predicted and experimentally confirmed that there was an optimized value of y in (Si3N4)y(SiO2)(1-y), which is 0.58, for minimizing the leakage current and EOT of SiON. To clarify the oxidation resistance and appropriate thickness of Al2O3, a TiN/Ta2O5/Al2O3/SiON/polycrystalline-silicon capacitor was fabricated. It was confirmed that the lower electrode was not oxidized during the crystallization annealing of Ta2O5. By setting the Al2O3 thickness to 3.4 nm, the leakage current is lowered below the required value with an EOT of 3.6 nm.

Outline and comparison of the possible effects present in a metal-thin-film-insulator-semiconductor solar cell

NASA Technical Reports Server (NTRS)

Fonash, S. J.

1976-01-01

The advantages possible with the insertion of a thin-film insulating or semi-insulating layer between a metal and a semiconductor to form the MIS photovoltaic device have been presented previously in the literature. This MIS configuration may be considered as a specific example of a more general class of photovoltaic devices: electrode-thin-film-insulator-semiconductor devices. Since the advantages of the configuration were pointed out, there has been considerable experimental interest in these photovoltaic devices. Because the previous analysis showed that the introduction of the insulator layer could produce several different but advantageous effects, this paper presents a further outline giving a comparison of these effects together with their ramifications.

Impact of the silicon substrate resistivity and growth condition on the deep levels in Ni-Au/AlN/Si MIS Capacitors

NASA Astrophysics Data System (ADS)

Wang, Chong; Simoen, Eddy; Zhao, Ming; Li, Wei

2017-10-01

Deep levels formed under different growth conditions of a 200 nm AlN buffer layer on B-doped Czochralski Si(111) substrates with different resistivity were investigated by deep-level transient spectroscopy (DLTS) on metal-insulator-semiconductor capacitors. Growth-temperature-dependent Al diffusion in the Si substrate was derived from the free carrier density obtained by capacitance-voltage measurement on samples grown on p- substrates. The DLTS spectra revealed a high concentration of point and extended defects in the p- and p+ silicon substrates, respectively. This indicated a difference in the electrically active defects in the silicon substrate close to the AlN/Si interface, depending on the B doping concentration.

Evaluation of Intrinsic Charge Carrier Transport at Insulator-Semiconductor Interfaces Probed by a Non-Contact Microwave-Based Technique

PubMed Central

Honsho, Yoshihito; Miyakai, Tomoyo; Sakurai, Tsuneaki; Saeki, Akinori; Seki, Shu

2013-01-01

We have successfully designed the geometry of the microwave cavity and the thin metal electrode, achieving resonance of the microwave cavity with the metal-insulator-semiconductor (MIS) device structure. This very simple MIS device operates in the cavity, where charge carriers are injected quantitatively by an applied bias at the insulator-semiconductor interface. The local motion of the charge carriers was clearly probed through the applied external microwave field, also giving the quantitative responses to the injected charge carrier density and charge/discharge characteristics. By means of the present measurement system named field-induced time-resolved microwave conductivity (FI-TRMC), the pentacene thin film in the MIS device allowed the evaluation of the hole and electron mobility at the insulator-semiconductor interface of 6.3 and 0.34 cm2 V−1 s−1, respectively. This is the first report on the direct, intrinsic, non-contact measurement of charge carrier mobility at interfaces that has been fully experimentally verified. PMID:24212382

Estimation of carrier mobility and charge behaviors of organic semiconductor films in metal-insulator-semiconductor diodes consisting of high-k oxide/organic semiconductor double layers

NASA Astrophysics Data System (ADS)

Chosei, Naoya; Itoh, Eiji

2018-02-01

We have comparatively studied the charge behaviors of organic semiconductor films based on charge extraction by linearly increasing voltage in a metal-insulator-semiconductor (MIS) diode structure (MIS-CELIV) and by classical capacitance-voltage measurement. The MIS-CELIV technique allows the selective measurement of electron and hole mobilities of n- and p-type organic films with thicknesses representative of those of actual devices. We used an anodic oxidized sputtered Ta or Hf electrode as a high-k layer, and it effectively blocked holes at the insulator/semiconductor interface. We estimated the hole mobilities of the polythiophene derivatives regioregular poly(3-hexylthiophene) (P3HT) and poly(3,3‧‧‧-didodecylquarterthiophene) (PQT-12) before and after heat treatment in the ITO/high-k/(thin polymer insulator)/semiconductor/MoO3/Ag device structure. The hole mobility of PQT-12 was improved from 1.1 × 10-5 to 2.1 × 10-5 cm2 V-1 s-1 by the heat treatment of the device at 100 °C for 30 min. An almost two orders of magnitude higher mobility was obtained in MIS diodes with P3HT as the p-type layer. We also determined the capacitance from the displacement current in MIS diodes at a relatively low-voltage sweep, and it corresponded well to the classical capacitance-voltage and frequency measurement results.

High capacitance density MIS capacitor using Si nanowires by MACE and ALD alumina dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leontis, I.; Nassiopoulou, A. G., E-mail: A.Nassiopoulou@inn.demokritos.gr; Botzakaki, M. A.

2016-06-28

High capacitance density three-dimensional (3D) metal-insulator-semiconductor (MIS) capacitors using Si nanowires (SiNWs) by metal-assisted chemical etching and atomic-layer-deposited alumina dielectric film were fabricated and electrically characterized. A chemical treatment was used to remove structural defects from the nanowire surface, in order to reduce the density of interface traps at the Al{sub 2}O{sub 3}/SiNW interface. SiNWs with two different lengths, namely, 1.3 μm and 2.4 μm, were studied. A four-fold capacitance density increase compared to a planar reference capacitor was achieved with the 1.3 μm SiNWs. In the case of the 2.4 μm SiNWs this increase was ×7, reaching a value of 4.1 μF/cm{sup 2}. Capacitance-voltagemore » (C-V) measurements revealed that, following a two-cycle chemical treatment, frequency dispersion at accumulation regime and flat-band voltage shift disappeared in the case of the 1.3 μm SiNWs, which is indicative of effective removal of structural defects at the SiNW surface. In the case of the 2.4 μm SiNWs, frequency dispersion at accumulation persisted even after the two-step chemical treatment. This is attributed to a porous Si layer at the SiNW tops, which is not effectively removed by the chemical treatment. The electrical losses of MIS capacitors in both cases of SiNW lengths were studied and will be discussed.« less

Application of polymer-coated metal-insulator-semiconductor sensors for the detection of dissolved hydrogen

NASA Astrophysics Data System (ADS)

Li, Dongmei; Medlin, J. W.; Bastasz, R.

2006-06-01

The detection of dissolved hydrogen in liquids is crucial to many industrial applications, such as fault detection for oil-filled electrical equipment. To enhance the performance of metal-insulator-semiconductor (MIS) sensors for dissolved hydrogen detection, a palladium MIS sensor has been modified by depositing a polyimide (PI) layer above the palladium surface. Response measurements of the PI-coated sensors in mineral oil indicate that hydrogen is sensitively detected, while the effect of interfering gases on sensor response is minimized.

Fabrication and Properties of a Metal-Insulator - Type Oxygen Sensor Using Lanthanum Trifluoride as the Sole Dielectric.

NASA Astrophysics Data System (ADS)

Mattingly, William Brashear, III

1995-01-01

Oxygen sensors were fabricated using a metal-insulator -semiconductor construction where the sole 'insulator' is a thin film of LaF_3, an ionic conductor. The typical oxide or nitride layers were eliminated producing a simple Pt/LaF_3/Si design. LaF_3 films, 200-300nm thick, were directly deposited on n-type Si(111) using a high temperature effusion cell in an ultra high vacuum MBE chamber. The film morphology could be controlled from polycrystalline to near single crystal epitaxy. Epitaxial films exhibited a single relaxed variant with the LaF _3 c-axis normal to the silicon surface and the in-plane LaF_3(10^ -10) parallel to Si(110). Polycrystalline films also showed a high degree of LaF_3 c-axis normal texture. Films doped with strontium were also produced. Polycrystalline films were more robust and fabricated into MIS (metal-insulator-semiconductor) capacitors. Capacitance voltage tests of the devices demonstrate nearly ideal MIS capacitor behavior. The flatband voltages were typically within 300mV of the calculated value. Bias challenge tests developed in the lab showed less than 70mV flatband voltage shift. The dielectric constant of undoped LaF_3 films measured close to 14. Doped films, rm Sr_{x}La_ {1-x}F_3 x =.06, showed a dielectric constant of 275, at 100kHz. Oxygen partial pressure tests were performed with mixtures of dry nitrogen and dry oxygen. Oxygen partial pressures were varied between 2.5 times 10^{-4} and 1.0 atmosphere. The steady state data are consistent with a Pt/LaF _3 interface adsorption mechanism, where the work function of the platinum gate metal is modulated. The mechanism is not a half-cell Nernst-type response. Langmiur isotherm fitted data indicate the response range for undoped devices is 0.3 V. Signal drift was less than 5 mV/day. The metal free-surface reactions and the dipole species at the Pt/LaF_3 interface are yet to be determined. Device kinetic studies show the time required for full equilibration after a step in oxygen partial pressure is 24 hours at 90^circC. Initial response kinetics to downward steps in oxygen show the activation energy of the process is 0.54 eV.

Metal-Insulator-Semiconductor Nanowire Network Solar Cells.

PubMed

Oener, Sebastian Z; van de Groep, Jorik; Macco, Bart; Bronsveld, Paula C P; Kessels, W M M; Polman, Albert; Garnett, Erik C

2016-06-08

Metal-insulator-semiconductor (MIS) junctions provide the charge separating properties of Schottky junctions while circumventing the direct and detrimental contact of the metal with the semiconductor. A passivating and tunnel dielectric is used as a separation layer to reduce carrier recombination and remove Fermi level pinning. When applied to solar cells, these junctions result in two main advantages over traditional p-n-junction solar cells: a highly simplified fabrication process and excellent passivation properties and hence high open-circuit voltages. However, one major drawback of metal-insulator-semiconductor solar cells is that a continuous metal layer is needed to form a junction at the surface of the silicon, which decreases the optical transmittance and hence short-circuit current density. The decrease of transmittance with increasing metal coverage, however, can be overcome by nanoscale structures. Nanowire networks exhibit precisely the properties that are required for MIS solar cells: closely spaced and conductive metal wires to induce an inversion layer for homogeneous charge carrier extraction and simultaneously a high optical transparency. We experimentally demonstrate the nanowire MIS concept by using it to make silicon solar cells with a measured energy conversion efficiency of 7% (∼11% after correction), an effective open-circuit voltage (Voc) of 560 mV and estimated short-circuit current density (Jsc) of 33 mA/cm(2). Furthermore, we show that the metal nanowire network can serve additionally as an etch mask to pattern inverted nanopyramids, decreasing the reflectivity substantially from 36% to ∼4%. Our extensive analysis points out a path toward nanowire based MIS solar cells that exhibit both high Voc and Jsc values.

Electronic passivation of n- and p-type GaAs using chemical vapor deposited GaS

NASA Technical Reports Server (NTRS)

Tabib-Azar, Massood; Kang, Soon; Macinnes, Andrew N.; Power, Michael B.; Barron, Andrew R.; Jenkins, Phillip P.; Hepp, Aloysius F.

1993-01-01

We report on the electronic passivation of n- and p-type GaAs using CVD cubic GaS. Au/GaS/GaAs-fabricated metal-insulator-semiconductor (MIS) structures exhibit classical high-frequency capacitor vs voltage (C-V) behavior with well-defined accumulation and inversion regions. Using high- and low-frequency C-V, the interface trap densities of about 10 exp 11/eV per sq cm on both n- and p-type GaAs are determined. The electronic condition of GaS/GaAs interface did not show any deterioration after a six week time period.

Temperature dependent electrical characterisation of Pt/HfO{sub 2}/n-GaN metal-insulator-semiconductor (MIS) Schottky diodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shetty, Arjun, E-mail: arjun@ece.iisc.ernet.in; Vinoy, K. J.; Roul, Basanta

2015-09-15

This paper reports an improvement in Pt/n-GaN metal-semiconductor (MS) Schottky diode characteristics by the introduction of a layer of HfO{sub 2} (5 nm) between the metal and semiconductor interface. The resulting Pt/HfO{sub 2}/n-GaN metal-insulator-semiconductor (MIS) Schottky diode showed an increase in rectification ratio from 35.9 to 98.9(@ 2V), increase in barrier height (0.52 eV to 0.63eV) and a reduction in ideality factor (2.1 to 1.3) as compared to the MS Schottky. Epitaxial n-type GaN films of thickness 300nm were grown using plasma assisted molecular beam epitaxy (PAMBE). The crystalline and optical qualities of the films were confirmed using high resolutionmore » X-ray diffraction and photoluminescence measurements. Metal-semiconductor (Pt/n-GaN) and metal-insulator-semiconductor (Pt/HfO{sub 2}/n-GaN) Schottky diodes were fabricated. To gain further understanding of the Pt/HfO{sub 2}/GaN interface, I-V characterisation was carried out on the MIS Schottky diode over a temperature range of 150 K to 370 K. The barrier height was found to increase (0.3 eV to 0.79 eV) and the ideality factor decreased (3.6 to 1.2) with increase in temperature from 150 K to 370 K. This temperature dependence was attributed to the inhomogeneous nature of the contact and the explanation was validated by fitting the experimental data into a Gaussian distribution of barrier heights.« less

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

H2 evolution at Si-based metal-insulator-semiconductor photoelectrodes enhanced by inversion channel charge collection and H spillover.

PubMed

Esposito, Daniel V; Levin, Igor; Moffat, Thomas P; Talin, A Alec

2013-06-01

Photoelectrochemical (PEC) water splitting represents a promising route for renewable production of hydrogen, but trade-offs between photoelectrode stability and efficiency have greatly limited the performance of PEC devices. In this work, we employ a metal-insulator-semiconductor (MIS) photoelectrode architecture that allows for stable and efficient water splitting using narrow bandgap semiconductors. Substantial improvement in the performance of Si-based MIS photocathodes is demonstrated through a combination of a high-quality thermal SiO2 layer and the use of bilayer metal catalysts. Scanning probe techniques were used to simultaneously map the photovoltaic and catalytic properties of the MIS surface and reveal the spillover-assisted evolution of hydrogen off the SiO2 surface and lateral photovoltage driven minority carrier transport over distances that can exceed 2 cm. The latter finding is explained by the photo- and electrolyte-induced formation of an inversion channel immediately beneath the SiO2/Si interface. These findings have important implications for further development of MIS photoelectrodes and offer the possibility of highly efficient PEC water splitting.

The comprehensive study and the reduction of contact resistivity on the n-InGaAs M-I-S contact system with different inserted insulators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liao, M.-H., E-mail: mhliaoa@ntu.edu.tw; Lien, C.

2015-05-15

Five different kinds of insulators including BaTiO{sub 3}, TiO{sub 2}, Al{sub 2}O{sub 3}, CdO and ZnO on the n-type InGaAs metal-insulator-semiconductor (M-I-S) ohmic contact structure are studied. The effect for the dielectric constant (ε) of inserted insulator and the conduction band offset (CBO) between an insulator and semiconductor substrate is analyzed by a unified M-I-S contact model. Based on the theoretical model and experimental data, we demonstrates that the inserted ZnO insulator with the high electron affinity and the low CBO (∼0.1 eV) to the InGaAs substrate results in ∼10 times contact resistivity reduction, even the ε of ZnO ismore » not pretty high (∼10)« less

Graphene-insulator-semiconductor capacitors as superior test structures for photoelectric determination of semiconductor devices band diagrams

NASA Astrophysics Data System (ADS)

Piskorski, K.; Passi, V.; Ruhkopf, J.; Lemme, M. C.; Przewlocki, H. M.

2018-05-01

We report on the advantages of using Graphene-Insulator-Semiconductor (GIS) instead of Metal-Insulator-Semiconductor (MIS) structures in reliable and precise photoelectric determination of the band alignment at the semiconductor-insulator interface and of the insulator band gap determination. Due to the high transparency to light of the graphene gate in GIS structures large photocurrents due to emission of both electrons and holes from the substrate and negligible photocurrents due to emission of carriers from the gate can be obtained, which allows reliable determination of barrier heights for both electrons, Ee and holes, Eh from the semiconductor substrate. Knowing the values of both Ee and Eh allows direct determination of the insulator band gap EG(I). Photoelectric measurements were made of a series of Graphene-SiO2-Si structures and an example is shown of the results obtained in sequential measurements of the same structure giving the following barrier height values: Ee = 4.34 ± 0.01 eV and Eh = 4.70 ± 0.03 eV. Based on this result and results obtained for other structures in the series we conservatively estimate the maximum uncertainty of both barrier heights estimations at ± 0.05 eV. This sets the SiO2 band gap estimation at EG(I) = 7.92 ± 0.1 eV. It is shown that widely different SiO2 band gap values were found by research groups using various determination methods. We hypothesize that these differences are due to different sensitivities of measurement methods used to the existence of the SiO2 valence band tail.

Studies of Large-Area Inversion-Layer Metal-Insulator-Semiconductor (IL/MIS) Solar Cells and Arrays

NASA Technical Reports Server (NTRS)

Ho, Fat Duen

1996-01-01

Many inversion-layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. There are around eighteen 1 cm(exp 2) IL/MIS solar cells which have efficiencies greater than 7%. There are only about three 19 cm(exp 2) IL/MIS cells which have efficiencies greater than 4%. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved. A lot of effort and progress have been made in this area. A comprehensive model for MIS contacts under dark conditions has been developed that covers a wide range of parameters. It has been applied to MIS solar cells. One of the main advantages of these models is the prediction of the range of the thin oxide thickness versus the maximum efficiencies of the MIS solar cells. This is particularly important when the thickness is increased to 25 A. This study is very useful for our investigation of the IL/MIS solar cells. The two-dimensional numerical model for the IL/MIS solar cells has been tried to develop and the results are presented in this report.

Electrical properties of GaN-based metal-insulator-semiconductor structures with Al2O3 deposited by atomic layer deposition using water and ozone as the oxygen precursors

NASA Astrophysics Data System (ADS)

Kubo, Toshiharu; Freedsman, Joseph J.; Iwata, Yasuhiro; Egawa, Takashi

2014-04-01

Al2O3 deposited by atomic layer deposition (ALD) was used as an insulator in metal-insulator-semiconductor (MIS) structures for GaN-based MIS-devices. As the oxygen precursors for the ALD process, water (H2O), ozone (O3), and both H2O and O3 were used. The chemical characteristics of the ALD-Al2O3 surfaces were investigated by x-ray photoelectron spectroscopy. After fabrication of MIS-diodes and MIS-high-electron-mobility transistors (MIS-HEMTs) with the ALD-Al2O3, their electrical properties were evaluated by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The threshold voltage of the C-V curves for MIS-diodes indicated that the fixed charge in the Al2O3 layer is decreased when using both H2O and O3 as the oxygen precursors. Furthermore, MIS-HEMTs with the H2O + O3-based Al2O3 showed good dc I-V characteristics without post-deposition annealing of the ALD-Al2O3, and the drain leakage current in the off-state region was suppressed by seven orders of magnitude.

Admittance Investigation of MIS Structures with HgTe-Based Single Quantum Wells.

PubMed

Izhnin, Ihor I; Nesmelov, Sergey N; Dzyadukh, Stanislav M; Voitsekhovskii, Alexander V; Gorn, Dmitry I; Dvoretsky, Sergey A; Mikhailov, Nikolaj N

2016-12-01

This work presents results of the investigation of admittance of metal-insulator-semiconductor structure based on Hg1 - x Cd x Te grown by molecular beam epitaxy. The structure contains a single quantum well Hg0.35Cd0.65Te/HgTe/Hg0.35Cd0.65Te with thickness of 5.6 nm in the sub-surface layer of the semiconductor. Both the conductance-voltage and capacitance-voltage characteristics show strong oscillations when the metal-insulator-semiconductor (MIS) structure with a single quantum well based on HgTe is biased into the strong inversion mode. Also, oscillations on the voltage dependencies of differential resistance of the space charge region were observed. These oscillations were related to the recharging of quantum levels in HgTe.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

NASA Astrophysics Data System (ADS)

Gao, Tao; Xu, Ruimin; Kong, Yuechan; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng

2015-06-01

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr0.52Ti0.48)-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (gm-Vg) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

T-gate geometric (solution for submicrometer gate length) HEMT: Physical analysis, modeling and implementation as parasitic elements and its usage as dual gate for variable gain amplifiers

NASA Astrophysics Data System (ADS)

Gupta, Ritesh; Rathi, Servin; Kaur, Ravneet; Gupta, Mridula; Gupta, R. S.

2009-03-01

In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal-insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n +-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268-2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal-Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534-2540] are also being fabricated these days, mainly at the drain end ( Γ-gate) having Metal-Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal-Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189-198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model.

Electrical and carrier transport properties of the Au/Y2O3/n-GaN metal-insulator-semiconductor (MIS) diode with rare-earth oxide interlayer

NASA Astrophysics Data System (ADS)

Venkata Prasad, C.; Rajagopal Reddy, V.; Choi, Chel-Jong

2017-04-01

The electrical and transport properties of rare-earth Y2O3 on n-type GaN with Au electrode have been investigated by current-voltage and capacitance-voltage techniques at room temperature. The Au/Y2O3/n-GaN metal-insulator-semiconductor (MIS) diode shows a good rectification behavior compared to the Au/n-GaN metal-semiconductor (MS) diode. Statistical analysis showed that a mean barrier height (BH) and ideality factor are 0.78 eV and 1.93, and 0.96 eV and 2.09 for the Au/n-GaN MS and Au/Y2O3/n-GaN MIS diodes, respectively. Results indicate that the high BH is obtained for the MIS diode compared to the MS diode. The BH, ideality factor and series resistance are also estimated by Cheung's function and Norde method. From the forward current-voltage data, the interface state density ( N SS) is estimated for both the MS and MIS Schottky diodes, and found that the estimated N SS is lower for the MIS diode compared to the MS diode. The results reveal that the introduction of Y2O3 interlayer facilitated the reduction of N SS of the Au/n-GaN interface. Experimental results suggest that the Poole-Frenkel emission is a dominant conduction mechanism in the reverse bias region of both Au/n-GaN MS and Au/Y2O3/n-GaN MIS diodes.

Metal-ferroelectric-metal capacitor based persistent memory for electronic product code class-1 generation-2 uhf passive radio-frequency identification tag

NASA Astrophysics Data System (ADS)

Yoon, Bongno; Sung, Man Young; Yeon, Sujin; Oh, Hyun S.; Kwon, Yoonjoo; Kim, Chuljin; Kim, Kyung-Ho

2009-03-01

With the circuits using metal-ferroelectric-metal (MFM) capacitor, rf operational signal properties are almost the same or superior to those of polysilicon-insulator-polysilicon, metal-insulator-metal, and metal-oxide-semiconductor (MOS) capacitors. In electronic product code global class-1 generation-2 uhf radio-frequency identification (RFID) protocols, the MFM can play a crucial role in satisfying the specifications of the inventoried flag's persistence times (Tpt) for each session (S0-S3, SL). In this paper, we propose and design a new MFM capacitor based memory scheme of which persistence time for S1 flag is measured at 2.2 s as well as indefinite for S2, S3, and SL flags during the period of power-on. A ferroelectric random access memory embedded RFID tag chip is fabricated with an industry-standard complementary MOS process. The chip size is around 500×500 μm2 and the measured power consumption is about 10 μW.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe.

PubMed

Milotti, Valeria; Pietsch, Manuel; Strunk, Karl-Philipp; Melzer, Christian

2018-01-01

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Measuring the lateral charge-carrier mobility in metal-insulator-semiconductor capacitors via Kelvin-probe

NASA Astrophysics Data System (ADS)

Milotti, Valeria; Pietsch, Manuel; Strunk, Karl-Philipp; Melzer, Christian

2018-01-01

We report a Kelvin-probe method to investigate the lateral charge-transport properties of semiconductors, most notably the charge-carrier mobility. The method is based on successive charging and discharging of a pre-biased metal-insulator-semiconductor stack by an alternating voltage applied to one edge of a laterally confined semiconductor layer. The charge carriers spreading along the insulator-semiconductor interface are directly measured by a Kelvin-probe, following the time evolution of the surface potential. A model is presented, describing the device response for arbitrary applied biases allowing the extraction of the lateral charge-carrier mobility from experimentally measured surface potentials. The method is tested using the organic semiconductor poly(3-hexylthiophene), and the extracted mobilities are validated through current voltage measurements on respective field-effect transistors. Our widely applicable approach enables robust measurements of the lateral charge-carrier mobility in semiconductors with weak impact from the utilized contact materials.

Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, Tao; Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016; Xu, Ruimin

2015-06-15

We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectricmore » constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.« less

Low trap states in in situ SiN{sub x}/AlN/GaN metal-insulator-semiconductor structures grown by metal-organic chemical vapor deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lu, Xing; Ma, Jun; Jiang, Huaxing

2014-09-08

We report the use of SiN{sub x} grown in situ by metal-organic chemical vapor deposition as the gate dielectric for AlN/GaN metal-insulator-semiconductor (MIS) structures. Two kinds of trap states with different time constants were identified and characterized. In particular, the SiN{sub x}/AlN interface exhibits remarkably low trap state densities in the range of 10{sup 11}–10{sup 12 }cm{sup −2}eV{sup −1}. Transmission electron microscopy and X-ray photoelectron spectroscopy analyses revealed that the in situ SiN{sub x} layer can provide excellent passivation without causing chemical degradation to the AlN surface. These results imply the great potential of in situ SiN{sub x} as an effectivemore » gate dielectric for AlN/GaN MIS devices.« less

Thickness engineering of atomic layer deposited Al2O3 films to suppress interfacial reaction and diffusion of Ni/Au gate metal in AlGaN/GaN HEMTs up to 600 °C in air

NASA Astrophysics Data System (ADS)

Suria, Ateeq J.; Yalamarthy, Ananth Saran; Heuser, Thomas A.; Bruefach, Alexandra; Chapin, Caitlin A.; So, Hongyun; Senesky, Debbie G.

2017-06-01

In this paper, we describe the use of 50 nm atomic layer deposited (ALD) Al2O3 to suppress the interfacial reaction and inter-diffusion between the gate metal and semiconductor interface, to extend the operation limit up to 600 °C in air. Suppression of diffusion is verified through Auger electron spectroscopy (AES) depth profiling and X-ray diffraction (XRD) and is further supported with electrical characterization. An ALD Al2O3 thin film (10 nm and 50 nm), which functions as a dielectric layer, was inserted between the gate metal (Ni/Au) and heterostructure-based semiconductor material (AlGaN/GaN) to form a metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). This extended the 50 nm ALD Al2O3 MIS-HEMT (50-MIS) current-voltage (Ids-Vds) and gate leakage (Ig,leakage) characteristics up to 600 °C. Both, the 10 nm ALD Al2O3 MIS-HEMT (10-MIS) and HEMT, failed above 350 °C, as evidenced by a sudden increase of approximately 50 times and 5.3 × 106 times in Ig,leakage, respectively. AES on the HEMT revealed the formation of a Ni-Au alloy and Ni present in the active region. Additionally, XRD showed existence of metal gallides in the HEMT. The 50-MIS enables the operation of AlGaN/GaN based electronics in oxidizing high-temperature environments, by suppressing interfacial reaction and inter-diffusion of the gate metal with the semiconductor.

Low-frequency noise in AlN/AlGaN/GaN metal-insulator-semiconductor devices: A comparison with Schottky devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Le, Son Phuong; Nguyen, Tuan Quy; Shih, Hong-An

2014-08-07

We have systematically investigated low-frequency noise (LFN) in AlN/AlGaN/GaN metal-insulator-semiconductor (MIS) devices, where the AlN gate insulator layer was sputtering-deposited on the AlGaN surface, in comparison with LFN in AlGaN/GaN Schottky devices. By measuring LFN in ungated two-terminal devices and heterojunction field-effect transistors (HFETs), we extracted LFN characteristics in the intrinsic gated region of the HFETs. Although there is a bias regime of the Schottky-HFETs in which LFN is dominated by the gate leakage current, LFN in the MIS-HFETs is always dominated by only the channel current. Analyzing the channel-current-dominated LFN, we obtained Hooge parameters α for the gated regionmore » as a function of the sheet electron concentration n{sub s} under the gate. In a regime of small n{sub s}, both the MIS- and Schottky-HFETs exhibit α∝n{sub s}{sup −1}. On the other hand, in a middle n{sub s} regime of the MIS-HFETs, α decreases rapidly like n{sub s}{sup −ξ} with ξ ∼ 2-3, which is not observed for the Schottky-HFETs. In addition, we observe strong increase in α∝n{sub s}{sup 3} in a large n{sub s} regime for both the MIS- and Schottky-HFETs.« less

Insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor devices with Al2O3 or AlTiO gate dielectrics

NASA Astrophysics Data System (ADS)

Le, Son Phuong; Nguyen, Duong Dai; Suzuki, Toshi-kazu

2018-01-01

We have investigated insulator-semiconductor interface fixed charges in AlGaN/GaN metal-insulator-semiconductor (MIS) devices with Al2O3 or AlTiO (an alloy of Al2O3 and TiO2) gate dielectrics obtained by atomic layer deposition on AlGaN. Analyzing insulator-thickness dependences of threshold voltages for the MIS devices, we evaluated positive interface fixed charges, whose density at the AlTiO/AlGaN interface is significantly lower than that at the Al2O3/AlGaN interface. This and a higher dielectric constant of AlTiO lead to rather shallower threshold voltages for the AlTiO gate dielectric than for Al2O3. The lower interface fixed charge density also leads to the fact that the two-dimensional electron concentration is a decreasing function of the insulator thickness for AlTiO, whereas being an increasing function for Al2O3. Moreover, we discuss the relationship between the interface fixed charges and interface states. From the conductance method, it is shown that the interface state densities are very similar at the Al2O3/AlGaN and AlTiO/AlGaN interfaces. Therefore, we consider that the lower AlTiO/AlGaN interface fixed charge density is not owing to electrons trapped at deep interface states compensating the positive fixed charges and can be attributed to a lower density of oxygen-related interface donors.

Electron beam induced damage in PECVD Si3N4 and SiO2 films on InP

NASA Technical Reports Server (NTRS)

Pantic, Dragan M.; Kapoor, Vik J.; Young, Paul G.; Williams, Wallace D.; Dickman, John E.

1990-01-01

Phosphorus rich plasma enhanced chemical vapor deposition (PECVD) of silicon nitride and silicon dioxide films on n-type indium phosphide (InP) substrates were exposed to electron beam irradiation in the 5 to 40 keV range for the purpose of characterizing the damage induced in the dielectic. The electron beam exposure was on the range of 10(exp -7) to 10(exp -3) C/sq cm. The damage to the devices was characterized by capacitance-voltage (C-V) measurements of the metal insulator semiconductor (MIS) capacitors. These results were compared to results obtained for radiation damage of thermal silicon dioxide on silicon (Si) MOS capacitors with similar exposures. The radiation induced damage in the PECVD silicon nitride films on InP was successfully annealed out in an hydrogen/nitrogen (H2/N2) ambient at 400 C for 15 min. The PECVD silicon dioxide films on InP had the least radiation damage, while the thermal silicon dioxide films on Si had the most radiation damage.

High-performance flexible microwave passives on plastic

NASA Astrophysics Data System (ADS)

Ma, Zhenqiang; Seo, Jung-Hun; Cho, Sang June; Zhou, Weidong

2014-06-01

We report the demonstration of bendable inductors, capacitors and switches fabricated on a polyethylene terephthalate (PET) substrate that can operate at high microwave frequencies. By employing bendable dielectric and single crystalline semiconductor materials, spiral inductors and metal-insulator-metal (MIM) capacitors with high quality factors and high resonance frequencies and single-pole, single-throw (SPST) switches were archived. The effects of mechanical bending on the performance of inductors, capacitors and switches were also measured and analyzed. We further investigated the highest possible resonance frequencies and quality factors of inductors and capacitors and, high frequency responses and insertion loss. These demonstrations will lead to flexible radio-frequency and microwave systems in the future.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yan, S. A.; Tang, M. H., E-mail: mhtang@xtu.edu.cn, E-mail: lizheng@xtu.edu.cn; Xiao, Y. G.

In this work, metal-ferroelectric-insulator-semiconductor (MFIS) structure capacitors with SrBi{sub 2}Ta{sub 2}O{sub 9} (300 nm) as ferroelectric thin film and HfTaO (6 nm, 8 nm, 10 nm, and 12 nm) as insulating buffer layer were proposed and investigated. The prepared capacitors were fabricated and characterized before radiation and then subjected to {sup 60}Co gamma irradiation in steps of two dose levels. Significant irradiation-induced degradation of the electrical characteristics was observed. The radiation experimental results indicated that stability and reliability of as-fabricated MFIS capacitors for nonvolatile memory applications could become uncontrollable under strong irradiation dose and/or long irradiation time.

The improvement of retention time of metal-ferroelectric (PbZr0.53Ti0.47O3)-insulator (ZrO2)-semiconductor transistors and capacitors by leakage current reduction using surface treatment

NASA Astrophysics Data System (ADS)

Shih, Wen-Chieh; Kang, Kun-Yung; Lee, Joseph Ya-Min

2007-11-01

Metal-ferroelectric-insulator-semiconductor transistors (MFISFETs) and capacitors with the structure of Al /Pb (Zr0.53,Ti0.47) O3/ZrO2/Si were fabricated. The wafers were pretreated with H2O2 before ZrO2 deposition and/or post-treated with HCl after ZrO2 deposition. The leakage current density at 5V is reduced from 10-1to5×10-6A /cm2. The subthreshold slope was improved to 91mV/decade. The MFISFETs maintain a threshold voltage window of about 1.1V after an elapsed time of 3000s. The mobility is 267cm2/Vs. The improvements are most likely due to the reduction of interfacial layer thickness and the interface states at the ZrO2/Si interface.

Fast optical detecting media based on semiconductor nanostructures for recording images obtained using charges of free photocarriers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kasherininov, P. G., E-mail: peter.kasherininov@mail.ioffe.ru; Tomasov, A. A.; Beregulin, E. V.

2011-01-15

Available published data on the properties of optical recording media based on semiconductor structures are reviewed. The principles of operation, structure, parameters, and the range of application for optical recording media based on MIS structures formed of photorefractive crystals with a thick layer of insulator and MIS structures with a liquid crystal as the insulator (the MIS LC modulators), as well as the effect of optical bistability in semiconductor structures (semiconductor MIS structures with nanodimensionally thin insulator (TI) layer, M(TI)S nanostructures). Special attention is paid to recording media based on the M(TI)S nanostructures promising for fast processing of highly informativemore » images and to fabrication of optoelectronic correlators of images for noncoherent light.« less

Charge trapping phenomena of tetraethylorthosilicate thin film containing Si nanocrystals synthesized by solid-state reaction.

PubMed

Lau, H W; Tan, O K; Liu, Y; Trigg, D A; Chen, T P

2006-08-28

In this work, we report on the fabrication of tetraethylorthosilicate (TEOS) thin dielectric film containing silicon nanocrystals (Si nc), synthesized by solid-state reaction, in a capacitor structure. A metal-insulator-semi-conductor (MIS) capacitor, with 28 nm thick Si nc in a TEOS thin film, has been fabricated. For this MIS, both electron and hole trapping in the Si nc are possible, depending on the polarity of the bias voltage. A V(FB) shift greater than 1 V can be experienced by a bias voltage of 16 V applied to the metal electrode for 1 s. Though there is no top control oxide, the discharge time for 10% of charges can be up to 4480 s when it is biased at 16 V for 1 s. It is further demonstrated that charging and discharging mechanisms are due to the Si nc rather than the TEOS oxide defects. This form of Si nc in a TEOS thin film capacitor provides the possibility of memory applications at low cost.

Impact of total ionizing dose irradiation on Pt/SrBi2Ta2O9/HfTaO/Si memory capacitors

NASA Astrophysics Data System (ADS)

Yan, S. A.; Zhao, W.; Guo, H. X.; Xiong, Y.; Tang, M. H.; Li, Z.; Xiao, Y. G.; Zhang, W. L.; Ding, H.; Chen, J. W.; Zhou, Y. C.

2015-01-01

In this work, metal-ferroelectric-insulator-semiconductor (MFIS) structure capacitors with SrBi2Ta2O9 (300 nm) as ferroelectric thin film and HfTaO (6 nm, 8 nm, 10 nm, and 12 nm) as insulating buffer layer were proposed and investigated. The prepared capacitors were fabricated and characterized before radiation and then subjected to 60Co gamma irradiation in steps of two dose levels. Significant irradiation-induced degradation of the electrical characteristics was observed. The radiation experimental results indicated that stability and reliability of as-fabricated MFIS capacitors for nonvolatile memory applications could become uncontrollable under strong irradiation dose and/or long irradiation time.

The electrical behavior of GaAs-insulator interfaces - A discrete energy interface state model

NASA Technical Reports Server (NTRS)

Kazior, T. E.; Lagowski, J.; Gatos, H. C.

1983-01-01

The relationship between the electrical behavior of GaAs Metal Insulator Semiconductor (MIS) structures and the high density discrete energy interface states (0.7 and 0.9 eV below the conduction band) was investigated utilizing photo- and thermal emission from the interface states in conjunction with capacitance measurements. It was found that all essential features of the anomalous behavior of GaAs MIS structures, such as the frequency dispersion and the C-V hysteresis, can be explained on the basis of nonequilibrium charging and discharging of the high density discrete energy interface states.

Paramagnetic defects and charge trapping behavior of ZrO2 films deposited on germanium by plasma-enhanced CVD

NASA Astrophysics Data System (ADS)

Mahata, C.; Bera, M. K.; Bose, P. K.; Maiti, C. K.

2009-02-01

Internal photoemission and magnetic resonance studies have been performed to investigate the charge trapping behavior and chemical nature of defects in ultrathin (~14 nm) high-k ZrO2 dielectric films deposited on p-Ge (1 0 0) substrates at low temperature (<200 °C) by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma at a pressure of ~65 Pa. Both the band and defect-related electron states have been characterized using electron paramagnetic resonance, internal photoemission, capacitance-voltage and current-voltage measurements under UV illumination. Capacitance-voltage and photocurrent-voltage measurements were used to determine the centroid of oxide charge within the high-k gate stack. The observed shifts in photocurrent response of the Al/ZrO2/GeO2/p-Ge metal-insulator-semiconductor (MIS) capacitors indicate the location of the centroids to be within the ZrO2 dielectric near to the gate electrode. Moreover, the measured flat band voltage and photocurrent shifts also indicate a large density of traps in the dielectric. The impact of plasma nitridation on the interfacial quality of the oxides has been investigated. Different N sources, such as NO and NH3, have been used for nitrogen engineering. Oxynitride samples show a lower defect density and trapping over the non-nitrided samples. The charge trapping and detrapping properties of MIS capacitors under stressing in constant current and voltage modes have been investigated in detail.

Study of Sn and Mg doping effects on TiO2/Ge stack structure by combinatorial synthesis

NASA Astrophysics Data System (ADS)

Nagata, Takahiro; Suzuki, Yoshihisa; Yamashita, Yoshiyuki; Ogura, Atsushi; Chikyow, Toyohiro

2018-04-01

The effects of Sn and Mg doping of a TiO2 film on a Ge substrate were investigated to improve leakage current properties and Ge diffusion into the TiO2 film. For systematic analysis, dopant-composition-spread TiO2 samples with dopant concentrations of up to 20.0 at. % were fabricated by RF sputtering and a combinatorial method. X-ray photoelectron spectroscopy revealed that the instability of Mg doping of TiO2 at dopant concentrations above 10.5 at. %. Both Sn and Mg dopants reduced Ge diffusion into TiO2. Sn doping enhanced the crystallization of the rutile phase, which is a high-dielectric-constant phase, although the Mg-doped TiO2 film indicated an amorphous structure. Sn-doping indicated systematic leakage current reduction with increasing dopant concentration. Doping at Sn concentrations higher than 16.8 at. % improved the leakage properties (˜10-7 A/cm2 at -3.0 V) and capacitance-voltage properties of metal-insulator-semiconductor (MIS) operation. The Sn doping of TiO2 may be useful for interface control and as a dielectric material for Ge-based MIS capacitors.

Highly sensitive optically controlled tunable capacitor and photodetector based on a metal-insulator-semiconductor on silicon-on-insulator substrates

NASA Astrophysics Data System (ADS)

Mikhelashvili, V.; Cristea, D.; Meyler, B.; Yofis, S.; Shneider, Y.; Atiya, G.; Cohen-Hyams, T.; Kauffmann, Y.; Kaplan, W. D.; Eisenstein, G.

2015-01-01

We describe a new type of optically sensitive tunable capacitor with a wide band response ranging from the ultraviolet (245 nm) to the near infrared (880 nm). It is based on a planar Metal-Oxide-Semiconductor (MOS) structure fabricated on an insulator on silicon substrate where the insulator layer comprises a double layer dielectric stack of SiO2-HfO2. Two operating configurations have been examined, a single diode and a pair of back-to-back connected devices, where either one or both diodes are illuminated. The varactors exhibit, in all cases, very large sensitivities to illumination. Near zero bias, the capacitance dependence on illumination intensity is sub linear and otherwise it is nearly linear. In the back-to-back connected configuration, the reverse biased diode acts as a light tunable resistor whose value affects strongly the capacitance of the second, forward biased, diode and vice versa. The proposed device is superior to other optical varactors in its large sensitivity to illumination in a very broad wavelength range (245 nm-880 nm), the strong capacitance dependence on voltage and the superior current photo responsivity. Above and beyond that structure requires a very simple fabrication process which is CMOS compatible.

Effects of surface plasma treatment on threshold voltage hysteresis and instability in metal-insulator-semiconductor (MIS) AlGaN/GaN heterostructure HEMTs

NASA Astrophysics Data System (ADS)

Zaidi, Z. H.; Lee, K. B.; Roberts, J. W.; Guiney, I.; Qian, H.; Jiang, S.; Cheong, J. S.; Li, P.; Wallis, D. J.; Humphreys, C. J.; Chalker, P. R.; Houston, P. A.

2018-05-01

In a bid to understand the commonly observed hysteresis in the threshold voltage (VTH) in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors during forward gate bias stress, we have analyzed a series of measurements on devices with no surface treatment and with two different plasma treatments before the in-situ Al2O3 deposition. The observed changes between samples were quasi-equilibrium VTH, forward bias related VTH hysteresis, and electrical response to reverse bias stress. To explain these effects, a disorder induced gap state model, combined with a discrete level donor, at the dielectric/semiconductor interface was employed. Technology Computer-Aided Design modeling demonstrated the possible differences in the interface state distributions that could give a consistent explanation for the observations.

Plasmonic ruler on field-effect devices for kinase drug discovery applications.

PubMed

Bhalla, Nikhil; Formisano, Nello; Miodek, Anna; Jain, Aditya; Di Lorenzo, Mirella; Pula, Giordano; Estrela, Pedro

2015-09-15

Protein kinases are cellular switches that mediate phosphorylation of proteins. Abnormal phosphorylation of proteins is associated with lethal diseases such as cancer. In the pharmaceutical industry, protein kinases have become an important class of drug targets. This study reports a versatile approach for the detection of protein phosphorylation. The change in charge of the myelin basic protein upon phosphorylation by the protein kinase C-alpha (PKC-α) in the presence of adenosine 5'-[γ-thio] triphosphate (ATP-S) was detected on gold metal-insulator-semiconductor (Au-MIS) capacitor structures. Gold nanoparticles (AuNPs) can then be attached to the thio-phosphorylated proteins, forming a Au-film/AuNP plasmonic couple. This was detected by a localized surface plasmon resonance (LSPR) technique alongside MIS capacitance. All reactions were validated using surface plasmon resonance technique and the interaction of AuNPs with the thio-phosphorylated proteins quantified by quartz crystal microbalance. The plasmonic coupling was also visualized by simulations using finite element analysis. The use of this approach in drug discovery applications was demonstrated by evaluating the response in the presence of a known inhibitor of PKC-α kinase. LSPR and MIS on a single platform act as a cross check mechanism for validating kinase activity and make the system robust to test novel inhibitors. Copyright © 2015 Elsevier B.V. All rights reserved.

Effect of doping on the forward current-transport mechanisms in a metal-insulator-semiconductor contact to INP:ZN grown by metal organic vapor phase epitaxy

NASA Astrophysics Data System (ADS)

Cova, P.; Singh, A.; Medina, A.; Masut, R. A.

1998-04-01

A detailed study of the effect of doping density on current transport was undertaken in Au metal-insulator-semiconductor (MIS) contacts fabricated on Zn-doped InP layers grown by metal organic vapor phase epitaxy. A recently developed method was used for the simultaneous analysis of the current-voltage ( I- V) and capacitance-voltage ( C- V) characteristics in an epitaxial MIS diode which brings out the contributions of different current-transport mechanisms to the total current. I- V and high-frequency C- V measurements were performed on two MIS diodes at different temperatures in the range 220-395 K. The barrier height at zero bias of Au/InP:Zn MIS diodes, φ0 (1.06 V±10%), was independent both of the Zn-doping density and of the surface preparation. The interface state density distribution Nss as well as the thickness of the oxide layer (2.2±15% nm) unintentionally grown before Au deposition were independent of the Zn-doping concentration in the range 10 16< NA<10 17 cm -3; not so the effective potential barrier χ of the insulator layer and the density of the mid-gap traps. χ was much lower for the highly-doped sample. Our results indicate that at high temperatures, independent of the Zn-doping concentration, the interfacial layer-thermionic (ITE) and interfacial layer-diffusion (ID) mechanisms compete with each other to control the current transport. At intermediate temperatures, however, ITE and ID will no longer be the only dominant mechanisms in the MIS diode fabricated on the highly-doped sample. In this case, the assumption of a generation-recombination current permits a better fit to the experimental data. Analysis of the data suggests that the generation-recombination current, observed only in the highly-doped sample, is associated with an increase in the Zn-doping density. From the forward I- V data for this diode we obtained the energy level (0.60 eV from the conduction band) for the most effective recombination centers.

MIS-based sensors with hydrogen selectivity

DOEpatents

Li,; Dongmei, [Boulder, CO; Medlin, J William [Boulder, CO; McDaniel, Anthony H [Livermore, CA; Bastasz, Robert J [Livermore, CA

2008-03-11

The invention provides hydrogen selective metal-insulator-semiconductor sensors which include a layer of hydrogen selective material. The hydrogen selective material can be polyimide layer having a thickness between 200 and 800 nm. Suitable polyimide materials include reaction products of benzophenone tetracarboxylic dianhydride 4,4-oxydianiline m-phenylene diamine and other structurally similar materials.

Modification of electrical properties of Au/n-type InP Schottky diode with a high-k Ba0.6Sr0.4TiO3 interlayer

NASA Astrophysics Data System (ADS)

Thapaswini, P. Prabhu; Padma, R.; Balaram, N.; Bindu, B.; Rajagopal Reddy, V.

2016-05-01

Au/Ba0.6Sr0.4TiO3 (BST)/n-InP metal/insulator/semiconductor (MIS) Schottky diodes have been analyzed by current-voltage (I-V) and capacitance-voltage (C-V) measurements. The surface morphology of the BST films on InP is fairly smooth. The Au/BST/n-InP MIS Schottky diode shows better rectification ratio and low leakage current compared to the conventional Au/n-InP metal-semiconductor (MS) Schottky diode. Higher barrier height is achieved for the MIS Schottky diode compared to the MS Schottky diode. The Norde and Cheung's methods are employed to determine the barrier height, ideality factor and series resistance. The interface state density (NSS) is determined from the forward bias I-V data for both the MS and MIS Schottky diodes. Results reveal that the NSS of the MIS Schottky diode is lower than that of the MS Schottky diode. The Poole-Frenkel emission is found dominating the reverse current in both Au/n-InP MS and Au/BST/n-InP MIS Schottky diodes, indicating the presence of structural defects and trap levels in the dielectric film.

An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors.

PubMed

Liu, Jiangwei; Koide, Yasuo

2018-06-04

Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high- k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High- k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high- k oxides of ALD-Al₂O₃, ALD-HfO₂, ALD-HfO₂/ALD-Al₂O₃ multilayer, SD-HfO₂/ALD-HfO₂ bilayer, SD-TiO₂/ALD-Al₂O₃ bilayer, and ALD-TiO₂/ALD-Al₂O₃ bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al₂O₃/H-diamond and SD-HfO₂/ALD-HfO₂/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO₂/ALD-Al₂O₃ bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p -type channel characteristics for the ALD-Al₂O₃/H-diamond, SD-HfO₂/ALD-HfO₂/H-diamond, and ALD-TiO₂/ALD-Al₂O₃/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high- k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.

Analysis of Deep and Shallow Traps in Semi-Insulating CdZnTe

DOE PAGES

Kim, Kihyun; Yoon, Yongsu; James, Ralph B.

2018-03-13

Trap levels which are deep or shallow play an important role in the electrical and the optical properties of a semiconductor; thus, a trap level analysis is very important in most semiconductor devices. Deep-level defects in CdZnTe are essential in Fermi level pinning at the middle of the bandgap and are responsible for incomplete charge collection and polarization effects. However, a deep level analysis in semi-insulating CdZnTe (CZT) is very difficult. Theoretical capacitance calculation for a metal/insulator/CZT (MIS) device with deep-level defects exhibits inflection points when the donor/acceptor level crosses the Fermi level in the surface-charge layer (SCL). Three CZTmore » samples with different resistivities, 2 × 10 4 (n-type), 2 × 10 6 (p-type), and 2 × 10 10 (p-type) Ω·cm, were used in fabricating the MIS devices. These devices showed several peaks in their capacitance measurements due to upward/downward band bending that depend on the surface potential. In conclusion, theoretical and experimental capacitance measurements were in agreement, except in the fully compensated case.« less

Analysis of Deep and Shallow Traps in Semi-Insulating CdZnTe

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kim, Kihyun; Yoon, Yongsu; James, Ralph B.

Trap levels which are deep or shallow play an important role in the electrical and the optical properties of a semiconductor; thus, a trap level analysis is very important in most semiconductor devices. Deep-level defects in CdZnTe are essential in Fermi level pinning at the middle of the bandgap and are responsible for incomplete charge collection and polarization effects. However, a deep level analysis in semi-insulating CdZnTe (CZT) is very difficult. Theoretical capacitance calculation for a metal/insulator/CZT (MIS) device with deep-level defects exhibits inflection points when the donor/acceptor level crosses the Fermi level in the surface-charge layer (SCL). Three CZTmore » samples with different resistivities, 2 × 10 4 (n-type), 2 × 10 6 (p-type), and 2 × 10 10 (p-type) Ω·cm, were used in fabricating the MIS devices. These devices showed several peaks in their capacitance measurements due to upward/downward band bending that depend on the surface potential. In conclusion, theoretical and experimental capacitance measurements were in agreement, except in the fully compensated case.« less

Properties of TiO2 thin films and a study of the TiO2-GaAs interface

NASA Technical Reports Server (NTRS)

Chen, C. Y.; Littlejohn, M. A.

1977-01-01

Titanium dioxide (TiO2) films prepared by chemical vapor deposition were investigated in this study for the purpose of the application in the GaAs metal-insulator-semiconductor field-effect transistor. The degree of crystallization increases with the deposition temperature. The current-voltage study, utilizing an Al-TiO2-Al MIM structure, reveals that the d-c conduction through the TiO2 film is dominated by the bulk-limited Poole-Frenkel emission mechanism. The dependence of the resistivity of the TiO2 films on the deposition environment is also shown. The results of the capacitance-voltage study indicate that an inversion layer in an n-type substrate can be achieved in the MIS capacitor if the TiO2 films are deposited at a temperature higher than 275 C. A process of low temperature deposition followed by the pattern definition and a higher temperature annealing is suggested for device fabrications. A model, based on the assumption that the surface state densities are continuously distributed in energy within the forbidden band gap, is proposed to interpret the lack of an inversion layer in the Al-TiO2-GaAs MIS structure with the TiO2 films deposited at 200 C.

Computer modeling of inversion layer MOS solar cells and arrays

NASA Technical Reports Server (NTRS)

Ho, Fat Duen

1991-01-01

A two dimensional numerical model of the inversion layer metal insulator semiconductor (IL/MIS) solar cell is proposed by using the finite element method. The two-dimensional current flow in the device is taken into account in this model. The electrostatic potential distribution, the electron concentration distribution, and the hole concentration distribution for different terminal voltages are simulated. The results of simple calculation are presented. The existing problems for this model are addressed. Future work is proposed. The MIS structures are studied and some of the results are reported.

Analytical and numerical analysis of charge carriers extracted by linearly increasing voltage in a metal-insulator-semiconductor structure relevant to bulk heterojunction organic solar cells

NASA Astrophysics Data System (ADS)

Yumnam, Nivedita; Hirwa, Hippolyte; Wagner, Veit

2017-12-01

Analysis of charge extraction by linearly increasing voltage is conducted on metal-insulator-semiconductor capacitors in a structure relevant to organic solar cells. For this analysis, an analytical model is developed and is used to determine the conductivity of the active layer. Numerical simulations of the transient current were performed as a way to confirm the applicability of our analytical model and other analytical models existing in the literature. Our analysis is applied to poly(3-hexylthiophene)(P3HT) : phenyl-C61-butyric acid methyl ester (PCBM) which allows to determine the electron and hole mobility independently. A combination of experimental data analysis and numerical simulations reveals the effect of trap states on the transient current and where this contribution is crucial for data analysis.

Electrostatic analysis of n-doped SrTiO{sub 3} metal-insulator-semiconductor systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kamerbeek, A. M., E-mail: a.m.kamerbeek@rug.nl; Banerjee, T.; Hueting, R. J. E.

2015-12-14

Electron doped SrTiO{sub 3}, a complex-oxide semiconductor, possesses novel electronic properties due to its strong temperature and electric-field dependent permittivity. Due to the high permittivity, metal/n-SrTiO{sub 3} systems show reasonably strong rectification even when SrTiO{sub 3} is degenerately doped. Our experiments show that the insertion of a sub nanometer layer of AlO{sub x} in between the metal and n-SrTiO{sub 3} interface leads to a dramatic reduction of the Schottky barrier height (from around 0.90 V to 0.25 V). This reduces the interface resistivity by 4 orders of magnitude. The derived electrostatic analysis of the metal-insulator-semiconductor (n-SrTiO{sub 3}) system is consistent with thismore » trend. When compared with a Si based MIS system, the change is much larger and mainly governed by the high permittivity of SrTiO{sub 3}. The non-linear permittivity of n-SrTiO{sub 3} leads to unconventional properties such as a temperature dependent surface potential non-existent for semiconductors with linear permittivity such as Si. This allows tuning of the interfacial band alignment, and consequently the Schottky barrier height, in a much more drastic way than in conventional semiconductors.« less

Electrical characteristics of TMAH-surface treated Ni/Au/Al2O3/GaN MIS Schottky structures

NASA Astrophysics Data System (ADS)

Reddy, M. Siva Pratap; Lee, Jung-Hee; Jang, Ja-Soon

2014-03-01

The electrical characteristics and reverse leakage mechanisms of tetramethylammonium hydroxide (TMAH) surface-treated Ni/Au/Al2O3/GaN metal-insulator-semiconductor (MIS) diodes were investigated by using the current-voltage ( I-V) and capacitance-voltage ( C-V) characteristics. The MIS diode was formed on n-GaN after etching the AlGaN in the AlGaN/GaN heterostructures. The TMAH-treated MIS diode showed better Schottky characteristics with a lower ideality factor, higher barrier height and lower reverse leakage current compared to the TMAH-free MIS diode. In addition, the TMAH-free MIS diodes exhibited a transition from Poole-Frenkel emission at low voltages to Schottky emission at high voltages, whereas the TMAH-treated MIS diodes showed Schottky emission over the entire voltage range. Reasonable mechanisms for the improved device-performance characteristics in the TMAH-treated MIS diode are discussed in terms of the decreased interface state density or traps associated with an oxide material and the reduced tunneling probability.

Effect of annealing temperature on the electrical properties of Au/Ta2O5/n-GaN metal-insulator-semiconductor (MIS) structure

NASA Astrophysics Data System (ADS)

Prasanna Lakshmi, B.; Rajagopal Reddy, V.; Janardhanam, V.; Siva Pratap Reddy, M.; Lee, Jung-Hee

2013-11-01

We report on the effect of an annealing temperature on the electrical properties of Au/Ta2O5/n-GaN metal-insulator-semiconductor (MIS) structure by current-voltage ( I- V) and capacitance-voltage ( C- V) measurements. The measured Schottky barrier height ( Φ bo) and ideality factor n values of the as-deposited Au/Ta2O5/n-GaN MIS structure are 0.93 eV ( I- V) and 1.19. The barrier height (BH) increases to 1.03 eV and ideality factor decreases to 1.13 upon annealing at 500 ∘C for 1 min under nitrogen ambient. When the contact is annealed at 600 ∘C, the barrier height decreases and the ideality factor increases to 0.99 eV and 1.15. The barrier heights obtained from the C- V measurements are higher than those obtained from I- V measurements, and this indicates the existence of spatial inhomogeneity at the interface. Cheung’s functions are also used to calculate the barrier height ( Φ bo), ideality factor ( n), and series resistance ( R s ) of the Au/Ta2O5/n-GaN MIS structure. Investigations reveal that the Schottky emission is the dominant mechanism and the Poole-Frenkel emission occurs only in the high voltage region. The energy distribution of interface states is determined from the forward bias I- V characteristics by taking into account the bias dependence of the effective barrier height. It is observed that the density value of interface states for the annealed samples with interfacial layer is lower than that of the density value of interface states of the as-deposited sample.

Further study of inversion layer MIS solar cells

NASA Technical Reports Server (NTRS)

Ho, Fat Duen

1992-01-01

Many inversion layer metal-insulator-semiconductor (IL/MIS) solar cells have been fabricated. As of today, the best cell fabricated by us has a 9.138 percent AMO efficiency, with FF = 0.641, V(sub OC) = 0.557 V, and I(sub SC) = 26.9 micro A. Efforts made for fabricating an IL/MOS solar cell with reasonable efficiencies are reported. The more accurate control of the thickness of the thin layer of oxide between aluminum and silicon of the MIS contacts has been achieved by using two different process methods. Comparison of these two different thin oxide processings is reported. The effects of annealing time of the sample are discussed. The range of the resistivity of the substrates used in the IL cell fabrication is experimentally estimated. Theoretical study of the MIS contacts under dark conditions is addressed.

Effect of temperature on the electrical properties of a metal-ferroelectric (SrBi2Ta2O9)-insulator (HfTaO)-silicon capacitor

NASA Astrophysics Data System (ADS)

Chen, Y. Q.; Xu, X. B.; Lei, Z. F.; Y Liao, X.; Wang, X.; Zeng, C.; En, Y. F.; Huang, Y.

2015-01-01

A metal-ferroelectric (SrBi2Ta2O9)-insulator (HfTaO)-semiconductor capacitor was fabricated, and the temperature dependence of its electrical properties was investigated. Within the temperature range of 300-220 K, the maximum memory window is up to 1.26 V, and it could be attributed to a higher coercive field of the ferroelectric film at a lower temperature, which is induced by the deeper and more box-shaped potential well based on the defect-domain interaction model. The memory window decreases with increasing temperature from 300 to 400 K, and the larger sweep voltage leads to a smaller memory window at a higher temperature, which could be attributed to temperature-dependent polarization of the ferroelectric film and charge injection from an Si substrate of the capacitor. With the temperature increasing from 220 to 400 K, the leakage current density increases with temperature by about one order, and the corresponding conduction mechanism is discussed. The results could provide useful guidelines for design and application of ferroelectric memory.

Hafnium transistor process design for neural interfacing.

PubMed

Parent, David W; Basham, Eric J

2009-01-01

A design methodology is presented that uses 1-D process simulations of Metal Insulator Semiconductor (MIS) structures to design the threshold voltage of hafnium oxide based transistors used for neural recording. The methodology is comprised of 1-D analytical equations for threshold voltage specification, and doping profiles, and 1-D MIS Technical Computer Aided Design (TCAD) to design a process to implement a specific threshold voltage, which minimized simulation time. The process was then verified with a 2-D process/electrical TCAD simulation. Hafnium oxide films (HfO) were grown and characterized for dielectric constant and fixed oxide charge for various annealing temperatures, two important design variables in threshold voltage design.

Carbon monoxide sensor and method of use thereof

DOEpatents

McDaniel; Anthony H. , Medlin; J. Will , Bastasz; Robert J.

2007-09-04

Carbon monoxide sensors suitable for use in hydrogen feed streams and methods of use thereof are disclosed. The sensors are palladium metal/insulator/semiconductor (Pd-MIS) sensors which may possess a gate metal layer having uniform, Type 1, or non-uniform, Type 2, film morphology. Type 1 sensors display an increased sensor response in the presence of carbon monoxide while Type 2 sensors display a decreased response to carbon monoxide. The methods and sensors disclosed herein are particularly suitable for use in proton exchange membrane fuel cells (PEMFCs).

Improvement on the electrical characteristics of Pd/HfO2/6H-SiC MIS capacitors using post deposition annealing and post metallization annealing

NASA Astrophysics Data System (ADS)

Esakky, Papanasam; Kailath, Binsu J.

2017-08-01

HfO2 as a gate dielectric enables high electric field operation of SiC MIS structure and as gas sensor HfO2/SiC capacitors offer higher sensitivity than SiO2/SiC capacitors. The issue of higher density of oxygen vacancies and associated higher leakage current necessitates better passivation of HfO2/SiC interface. Effect of post deposition annealing in N2O plasma and post metallization annealing in forming gas on the structural and electrical characteristics of Pd/HfO2/SiC MIS capacitors are reported in this work. N2O plasma annealing suppresses crystallization during high temperature annealing thereby improving the thermal stability and plasma annealing followed by rapid thermal annealing in N2 result in formation of Hf silicate at the HfO2/SiC interface resulting in order of magnitude lower density of interface states and gate leakage current. Post metallization annealing in forming gas for 40 min reduces interface state density by two orders while gate leakage current density is reduced by thrice. Post deposition annealing in N2O plasma and post metallization annealing in forming gas are observed to be effective passivation techniques improving the electrical characteristics of HfO2/SiC capacitors.

Ni-BaTiO3-Based Base-Metal Electrode (BME) Ceramic Capacitors for Space Applications

NASA Technical Reports Server (NTRS)

Liu, Donhang; Fetter, Lula; Meinhold, Bruce

2015-01-01

A multi-layer ceramic capacitor (MLCC) is a high-temperature (1350C typical) co-fired ceramic monolithic that is composed of many layers of alternately stacked oxide-based dielectric and internal metal electrodes. To make the dielectric layers insulating and the metal electrode layers conducting, only highly oxidation-resistant precious metals, such as platinum, palladium, and silver, can be used for the co-firing of insulating MLCCs in a regular air atmosphere. MLCCs made with precious metals as internal electrodes and terminations are called precious-metal electrode (PME) capacitors. Currently, all military and space-level applications only address the use of PME capacitors.

Influence of metal work function and incorporation of Sr atom on WO3 thin films for MIS and MIM structured SBDs

NASA Astrophysics Data System (ADS)

Marnadu, R.; Chandrasekaran, J.; Raja, M.; Balaji, M.; Maruthamuthu, S.; Balraju, P.

2018-07-01

In this work, two different structure of Cu/Sr-WO3/p-Si metal-insulator-semiconductor (MIS) and Cu/Sr-WO3/FTO metal-insulator-metal (MIM) Schottky barrier diodes (SBDs) fabricated with an insulating layer of pure tungsten trioxide (WO3) and Sr-WO3 thin films have been reported. The Sr-WO3 layer was coated separately, with different concentrations (0, 4, 8 and 12 wt %) of strontium (Sr) via jet nebulizer spray pyrolysis technique (JNSP) on the p-type silica wafer (p-Si) and fluorine doped tin oxide (FTO) substrates which are been optimized at 400 °C. The XRD analysis reveals the multiphase crystalline structures for 12 wt % of Sr-WO3 film with higher average crystallite size. FE-SEM images show the randomly oriented sub-microsized slab and seashell like structures. Higher surface roughness with improved grain size for 12 wt % of Sr-WO3 film. The presence of W, O and Sr atoms was confirmed by EDX spectra. In optical studies, Maximum absorption with minimum optical band gap was observed for 12 wt % of Sr-WO3 composite film. There was a linear increase in the electrical conductivity of the films with higher wt. % of Sr. Evidently the activation energy decreased with Sr concentration which is in accordance with the bandgap values. The fitting results of the measured I-V, reveal that MIS (SBDs) under illumination condition have minimum ideality factor (n = 2.39) and maximum barrier height (Φb = 0.57) values for higher concentration (12 wt %) of Sr film compared to MIM SBDs.

ALD-Developed Plasmonic Two-Dimensional Au-WO3-TiO2 Heterojunction Architectonics for Design of Photovoltaic Devices.

PubMed

Karbalaei Akbari, Mohammad; Hai, Zhenyin; Wei, Zihan; Detavernier, Christophe; Solano, Eduardo; Verpoort, Francis; Zhuiykov, Serge

2018-03-28

Electrically responsive plasmonic devices, which benefit from the privilege of surface plasmon excited hot carries, have supported fascinating applications in the visible-light-assisted technologies. The properties of plasmonic devices can be tuned by controlling charge transfer. It can be attained by intentional architecturing of the metal-semiconductor (MS) interfaces. In this study, the wafer-scaled fabrication of two-dimensional (2D) TiO 2 semiconductors on the granular Au metal substrate is achieved using the atomic layer deposition (ALD) technique. The ALD-developed 2D MS heterojunctions exhibited substantial enhancement of the photoresponsivity and demonstrated the improvement of response time for 2D Au-TiO 2 -based plasmonic devices under visible light illumination. To circumvent the undesired dark current in the plasmonic devices, a 2D WO 3 nanofilm (∼0.7 nm) was employed as the intermediate layer on the MS interface to develop the metal-insulator-semiconductor (MIS) 2D heterostructure. As a result, 13.4% improvement of the external quantum efficiency was obtained for fabricated 2D Au-WO 3 -TiO 2 heterojunctions. The impedancometry measurements confirmed the modulation of charge transfer at the 2D MS interface using MIS architectonics. Broadband photoresponsivity from the UV to the visible light region was observed for Au-TiO 2 and Au-WO 3 -TiO 2 heterostructures, whereas near-infrared responsivity was not observed. Consequently, considering the versatile nature of the ALD technique, this approach can facilitate the architecturing and design of novel 2D MS and MIS heterojunctions for efficient plasmonic devices.

Organic memory device with self-assembly monolayered aptamer conjugated nanoparticles

NASA Astrophysics Data System (ADS)

Oh, Sewook; Kim, Minkeun; Kim, Yejin; Jung, Hunsang; Yoon, Tae-Sik; Choi, Young-Jin; Jung Kang, Chi; Moon, Myeong-Ju; Jeong, Yong-Yeon; Park, In-Kyu; Ho Lee, Hyun

2013-08-01

An organic memory structure using monolayered aptamer conjugated gold nanoparticles (Au NPs) as charge storage nodes was demonstrated. Metal-pentacene-insulator-semiconductor device was adopted for the non-volatile memory effect through self assembly monolayer of A10-aptamer conjugated Au NPs, which was formed on functionalized insulator surface with prostate-specific membrane antigen protein. The capacitance versus voltage (C-V) curves obtained for the monolayered Au NPs capacitor exhibited substantial flat-band voltage shift (ΔVFB) or memory window of 3.76 V under (+/-)7 V voltage sweep. The memory device format can be potentially expanded to a highly specific capacitive sensor for the aptamer-specific biomolecule detection.

Enhancement on crystallinity property of low annealed PbTiO3 thin films for metal-insulator-metal capacitor

NASA Astrophysics Data System (ADS)

Nurbaya, Z.; Wahid, M. H.; Rozana, M. D.; Alrokayan, S. A. H.; Khan, H. A.; Rusop, M.

2018-05-01

This study presents the investigation on crystallinity property of PbTiO3 thin films towards metal-insulator-metal capacitor device fabrication. The preparation of the thin films utilizes sol-gel spin coating method with low annealing temperature effect. Hence, structural and electrical characterization is brought to justify the thin films consistency.

Temperature dependence of frequency response characteristics in organic field-effect transistors

NASA Astrophysics Data System (ADS)

Lu, Xubing; Minari, Takeo; Liu, Chuan; Kumatani, Akichika; Liu, J.-M.; Tsukagoshi, Kazuhito

2012-04-01

The frequency response characteristics of semiconductor devices play an essential role in the high-speed operation of electronic devices. We investigated the temperature dependence of dynamic characteristics in pentacene-based organic field-effect transistors and metal-insulator-semiconductor capacitors. As the temperature decreased, the capacitance-voltage characteristics showed large frequency dispersion and a negative shift in the flat-band voltage at high frequencies. The cutoff frequency shows Arrhenius-type temperature dependence with different activation energy values for various gate voltages. These phenomena demonstrate the effects of charge trapping on the frequency response characteristics, since decreased mobility prevents a fast charge response for alternating current signals at low temperatures.

Study and modeling of the transport mechanism in a semi insulating GaAs Schottky diode

NASA Astrophysics Data System (ADS)

Resfa, A.; Smahi, Bourzig Y.; Menezla, Brahimi. R.

2012-09-01

The current through a metal-semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of carriers from the semiconductor into the metal, thermionic emission-diffusion (TED) of carriers across the Schottky barrier and quantum-mechanical tunneling through the barrier. The insulating layer converts the MS device in an MIS device and has a strong influence on its current-voltage (I-V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behavior of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase of the process of thermionic electrons and holes, which will in turn the IV characteristic of the diode, and an overflow maximum value [NT = 3 × 1020] is obtained. The I-V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yoshitake, Michiko, E-mail: yoshitake.michiko@nims.go.jp

Transition-metal carbides and nitrides (TMCs and TMNs) are promising electrode materials for various electronic devices such as metal-oxide-semiconductor field-effect transistors and metal-insulator-metal capacitors. In this paper, the work functions of TMCs and TMNs are discussed systematically. Based upon the origin of the work function, the effect upon transition metal species by different periodic table groups is explained, carbides are compared with nitrides for the same transition metal, and the effect of carbon or nitrogen vacancies is discussed. In addition, a method to estimate the generic trend of the work function is proposed for TMC{sub x}, TMN{sub x}, TMC{sub 1−y}N{sub y}more » (transition metal carbonitrides), and TM{sub 1−z}TM′{sub z}C (alloy carbides)« less

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

NASA Astrophysics Data System (ADS)

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-09-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec.

A mixed solution-processed gate dielectric for zinc-tin oxide thin-film transistor and its MIS capacitance

PubMed Central

Kim, Hunho; Kwack, Young-Jin; Yun, Eui-Jung; Choi, Woon-Seop

2016-01-01

Solution-processed gate dielectrics were fabricated with the combined ZrO2 and Al2O3 (ZAO) in the form of mixed and stacked types for oxide thin film transistors (TFTs). ZAO thin films prepared with double coatings for solid gate dielectrics were characterized by analytical tools. For the first time, the capacitance of the oxide semiconductor was extracted from the capacitance-voltage properties of the zinc-tin oxide (ZTO) TFTs with the combined ZAO dielectrics by using the proposed metal-insulator-semiconductor (MIS) structure model. The capacitance evolution of the semiconductor from the TFT model structure described well the threshold voltage shift observed in the ZTO TFT with the ZAO (1:2) gate dielectric. The electrical properties of the ZTO TFT with a ZAO (1:2) gate dielectric showed low voltage driving with a field effect mobility of 37.01 cm2/Vs, a threshold voltage of 2.00 V, an on-to-off current ratio of 1.46 × 105, and a subthreshold slope of 0.10 V/dec. PMID:27641430

Thermal stability of atomic layer deposition Al2O3 film on HgCdTe

NASA Astrophysics Data System (ADS)

Zhang, P.; Sun, C. H.; Zhang, Y.; Chen, X.; He, K.; Chen, Y. Y.; Ye, Z. H.

2015-06-01

Thermal stability of Atomic Layer Deposition Al2O3 film on HgCdTe was investigated by Al2O3 film post-deposition annealing treatment and Metal-Insulator-Semiconductor device low-temperature baking treatment. The effectiveness of Al2O3 film was evaluated by measuring the minority carrier lifetime and capacitance versus voltage characteristics. After annealing treatment, the minority carrier lifetime of the HgCdTe sample presented a slight decrease. Furthermore, the fixed charge density and the slow charge density decreased significantly in the annealed MIS device. After baking treatment, the fixed charge density and the slow charge density of the unannealed and annealed MIS devices decreased and increased, respectively.

Reaching state-of-the art requirements for MIM capacitors with a single-layer anodic Al2O3 dielectric and imprinted electrodes

NASA Astrophysics Data System (ADS)

Hourdakis, Emmanouel; Nassiopoulou, Androula G.

2017-07-01

Metal-Insulator-Metal (MIM) capacitors with a high capacitance density and low non-linearity coefficient using a single-layer dielectric of barrier-type anodic alumina (Al2O3) and an imprinted bottom Al electrode are presented. Imprinting of the bottom electrode aimed at increasing the capacitor effective surface area by creating a three-dimensional MIM capacitor architecture. The bottom Al electrode was only partly nanopatterned so as to ensure low series resistance of the MIM capacitor. With a 3 nm thick anodic Al2O3 dielectric, the capacitor with the imprinted electrode showed a 280% increase in capacitance density compared to the flat electrode capacitor, reaching a value of 20.5 fF/μm2. On the other hand, with a 30 nm thick anodic Al2O3 layer, the capacitance density was 7.9 fF/μm2 and the non-linearity coefficient was as low as 196 ppm/V2. These values are very close to reaching all requirements of the last International Technology Roadmap for Semiconductors for MIM capacitors [ITRS, http://www.itrs2.net/2013-itrs.html for ITRS Roadmap (2013)], and they are achieved by a single-layer dielectric instead of the complicated dielectric stacks of the literature. The obtained results constitute a real progress compared to previously reported results by our group for MIM capacitors using imprinted electrodes.

Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Colon, Albert; Stan, Liliana; Divan, Ralu

Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approachmore » this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both AlGaN/GaN and InAlN/GaN based devices.« less

Electrical characterizations of MIS structures based on variable-gap n(p)-HgCdTe grown by MBE on Si(0 1 3) substrates

NASA Astrophysics Data System (ADS)

Voitsekhovskii, A. V.; Nesmelov, S. N.; Dzyadukh, S. M.; Varavin, V. S.; Dvoretskii, S. A.; Mikhailov, N. N.; Yakushev, M. V.; Sidorov, G. Yu.

2017-12-01

Metal-insulator-semiconductor (MIS) structures based on n(p)-Hg1-xCdxTe (x = 0.22-0.40) with near-surface variable-gap layers were grown by the molecular-beam epitaxy (MBE) technique on the Si (0 1 3) substrates. Electrical properties of MIS structures were investigated experimentally at various temperatures (9-77 K) and directions of voltage sweep. The ;narrow swing; technique was used to determine the spectra of fast surface states with the exception of hysteresis effects. It is established that the density of fast surface states at the MCT/Al2O3 interface at a minimum does not exceed 3 × 1010 eV-1 × cm-2. For MIS structures based on n-MCT/Si(0 1 3), the differential resistance of the space-charge region in strong inversion mode in the temperature range 50-90 K is limited by the Shockley-Read-Hall generation in the space-charge region.

Radiation sensors based on the generation of mobile protons in organic dielectrics.

PubMed

Kapetanakis, Eleftherios; Douvas, Antonios M; Argitis, Panagiotis; Normand, Pascal

2013-06-26

A sensing scheme based on mobile protons generated by radiation, including ionizing radiation (IonR), in organic gate dielectrics is investigated for the development of metal-insulator-semiconductor (MIS)-type dosimeters. Application of an electric field to the gate dielectric moves the protons and thereby alters the flat band voltage (VFB) of the MIS device. The shift in the VFB is proportional to the IonR-generated protons and, therefore, to the IonR total dose. Triphenylsulfonium nonaflate (TPSNF) photoacid generator (PAG)-containing poly(methyl methacrylate) (PMMA) polymeric films was selected as radiation-sensitive gate dielectrics. The effects of UV (249 nm) and gamma (Co-60) irradiations on the high-frequency capacitance versus the gate voltage (C-VG) curves of the MIS devices were investigated for different total dose values. Systematic improvements in sensitivity can be accomplished by increasing the concentration of the TPSNF molecules embedded in the polymeric matrix.

Measurement of the quantum capacitance from two-dimensional surface state of a topological insulator at room temperature

NASA Astrophysics Data System (ADS)

Choi, Hyunwoo; Kim, Tae Geun; Shin, Changhwan

2017-06-01

A topological insulator (TI) is a new kind of material that exhibits unique electronic properties owing to its topological surface state (TSS). Previous studies focused on the transport properties of the TSS, since it can be used as the active channel layer in metal-oxide-semiconductor field-effect transistors (MOSFETs). However, a TI with a negative quantum capacitance (QC) effect can be used in the gate stack of MOSFETs, thereby facilitating the creation of ultra-low power electronics. Therefore, it is important to study the physics behind the QC in TIs in the absence of any external magnetic field, at room temperature. We fabricated a simple capacitor structure using a TI (TI-capacitor: Au-TI-SiO2-Si), which shows clear evidence of QC at room temperature. In the capacitance-voltage (C-V) measurement, the total capacitance of the TI-capacitor increases in the accumulation regime, since QC is the dominant capacitive component in the series capacitor model (i.e., CT-1 = CQ-1 + CSiO2-1). Based on the QC model of the two-dimensional electron systems, we quantitatively calculated the QC, and observed that the simulated C-V curve theoretically supports the conclusion that the QC of the TI-capacitor is originated from electron-electron interaction in the two-dimensional surface state of the TI.

Tracking ion irradiation effects using buried interface devices

NASA Astrophysics Data System (ADS)

Cutshall, D. B.; Kulkarni, D. D.; Miller, A. J.; Harriss, J. E.; Harrell, W. R.; Sosolik, C. E.

2018-05-01

We discuss how a buried interface device, specifically a metal-oxide-semiconductor (MOS) capacitor, can be utilized to track effects of ion irradiation on insulators. We show that the exposure of oxides within unfinished capacitor devices to ions can lead to significant changes in the capacitance of the finished devices. For multicharged ions, these capacitive effects can be traced to defect production within the oxide and ultimately point to a role for charge-dependent energy loss. In particular, we attribute the stretchout of the capacitance-voltage curves of MOS devices that include an irradiated oxide to the ion irradiation. The stretchout shows a power law dependence on the multicharged ion charge state (Q) that is similar to that observed for multicharged ion energy loss in other systems.

Preparation and characterisation of crystalline tris(acetylacetonato)Fe(III) films grown on p-Si substrate for dielectric applications

NASA Astrophysics Data System (ADS)

Dakhel, A. A.; Ali-Mohamed, A. Y.

2007-02-01

Thin tris(acetylacetonato)iron(III) films were prepared by sublimation in vacuum on glass and p-Si substrates. Then comprehensive studies of X-ray fluorescence (XRF), X-ray diffraction (XRD), optical absorption spectroscopy, AC-conductivity, and dielectric permittivity as a function of frequency and temperature have been performed. The prepared films show a polycrystalline of orthorhombic structure. The optical absorption spectrum of the film was identical with that of the bulk powder layer. For electrical measurements of the complex as insulator, sample in form of metal insulator semiconductor (MIS) structure was prepared and characterised by the measurement of the capacitance and AC-conductance as a function of gate voltage. From those measurements, the state density Dit at insulator/semiconductor interface and the density of the fixed charges in the complex film were determined. It was found that Dit was of order 1010 eV-1/cm2 and the surface charge density in the insulator film was of order 1010 cm-2. The frequency dependence of the electrical conductivity and dielectric properties of MIS structures were studied at room temperature. It was observed that the experimental data follow the correlated barrier-hopping (CBH) model, from which the fundamental absorption edge, the cut off hopping distance, and other parameters of the model were determined. It was found that the capacitance of the complex increases as temperature increases. Generally, the present study shows that the tris(acetylacetonato)iron(III) films grown on p-Si is a promising candidate for low-k dielectric applications, it displays low-k value around 2.0.

Effect of atomic layer deposition temperature on current conduction in Al2O3 films formed using H2O oxidant

NASA Astrophysics Data System (ADS)

Hiraiwa, Atsushi; Matsumura, Daisuke; Kawarada, Hiroshi

2016-08-01

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al2O3 films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al2O3 metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO2 capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al2O3 capacitors are found to outperform the SiO2 capacitors in the cases where the capacitors are negatively biased and the gate material is adequately selected to reduce virtual dipoles at the gate/Al2O3 interface. The Al2O3 electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al2O3 capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al2O3. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al2O3 capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al2O3/underlying SiO2 interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al2O3 films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al2O3 films.

Self-consistent performance modeling for dual band MIS UV photodetectors based on Si/SiO2 multilayer structure.

PubMed

Rostami, A; Leilaeioun, M; Golmmohamadi, S; Rasooli Saghai, H

2012-06-01

In this paper, we present a self-consistent theoretical model for a metal-insulator semiconductor (MIS) dual band ultraviolet (UV) photodetector with a modified structure implying an arbitrarily defined insulating potential barrier as its active region. Utilizing our proposed model, the dark and photocurrent density-voltage (J-V) characteristics of MIS UV photodetectors with multi-quantum wells of silicon (MQWs) are calculated. We demonstrate that dark current is reduced in the suggested structure, because the electron-tunneling probability becomes unity at energies coincident with the peak detection wavelength. This is due to the resonant tunneling and decreases at energies that are significantly smaller than this optimum value. In consequence, the number of carriers contributing to the dark current, which have a broad energy distribution at high temperatures, will decrease. It is also shown that the designed structure could detect two individual UV wavelengths, simultaneously. The width of each Si quantum well has been considered at around 1.2 nm, in order to observe these two absorption peaks in the middle and near UV regions of photon spectrum (about 365 nm, 175 nm).

Photovoltaic energy technologies: Health and environmental effects document

NASA Astrophysics Data System (ADS)

Moskowitz, P. D.; Hamilton, L. D.; Morris, S. C.; Rowe, M. D.

1980-09-01

The potential health and environmental consequences of producing electricity by photovoltaic energy systems was analyzed. Potential health and environmental risks are identified in representative fuel and material supply cycles including extraction, processing, refining, fabrication, installation, operation, and isposal for four photovoltaic energy systems (silicon N/P single crystal, silicon metal/insulator/semiconductor (MIS) cell, cadmium sulfide/copper sulfide backwall cell, and gallium arsenide heterojunction cell) delivering equal amounts of useful energy. Each step of the fuel and material supply cycles, materials demands, byproducts, public health, occupational health, and environmental hazards is identified.

Metal-Insulator-Semiconductor Photodetectors

PubMed Central

Lin, Chu-Hsuan; Liu, Chee Wee

2010-01-01

The major radiation of the Sun can be roughly divided into three regions: ultraviolet, visible, and infrared light. Detection in these three regions is important to human beings. The metal-insulator-semiconductor photodetector, with a simpler process than the pn-junction photodetector and a lower dark current than the MSM photodetector, has been developed for light detection in these three regions. Ideal UV photodetectors with high UV-to-visible rejection ratio could be demonstrated with III–V metal-insulator-semiconductor UV photodetectors. The visible-light detection and near-infrared optical communications have been implemented with Si and Ge metal-insulator-semiconductor photodetectors. For mid- and long-wavelength infrared detection, metal-insulator-semiconductor SiGe/Si quantum dot infrared photodetectors have been developed, and the detection spectrum covers atmospheric transmission windows. PMID:22163382

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tikhov, S. V.; Gorshkov, O. N.; Koryazhkina, M. N., E-mail: mahavenok@mail.ru

The properties of metal–insulator–semiconductor (MIS) structures based on n-GaAs in which silicon oxide and yttria-stabilized zirconia and hafnia are used as the insulator containing InAs quantum dots, which are embedded at the insulator/n-GaAs interface, are investigated. The structures manifest the resistive switching and synaptic behavior.

Temperature dependence of the dielectric response of anodized Al-Al2O3-metal capacitors

NASA Astrophysics Data System (ADS)

Hickmott, T. W.

2003-03-01

The temperature dependence of capacitance, CM, and conductance, GM, of Al-Al2O3-metal capacitors with Cu, Ag, and Au electrodes has been measured between 100 and 340 K at seven frequencies between 10 kHz and 1 MHz. Al2O3 films between 15 and 64 nm thick were formed by anodizing evaporated Al films in borate-glycol or borate-H2O electrolyte. The interface capacitance at the Al2O3-metal interface, CI, which is in series with the capacitance CD due to the Al2O3 dielectric, is determined from plots of 1/CM versus insulator thickness. CI is not fixed for a given metal-insulator interface but depends on the vacuum system used to deposit the metal electrode. CI is nearly temperature independent. When CI is taken into account the dielectric constant of Al2O3 determined from capacitance measurements is ˜8.3 at 295 K. The dielectric constant does not depend on anodizing electrolyte, insulator thickness, metal electrode, deposition conditions for the metal electrode or measurement frequency. By contrast, GM of Al-Al2O3-metal capacitors depends on both the deposition conditions of the metal and on the metal. For Al-Al2O3-Cu capacitors, GM is larger for capacitors with large values of 1/CI that result when Cu is evaporated in an oil-pumped vacuum system. For Al-Al2O3-Ag capacitors, GM does not depend on the Ag deposition conditions.

Origin of positive fixed charge at insulator/AlGaN interfaces and its control by AlGaN composition

NASA Astrophysics Data System (ADS)

Matys, M.; Stoklas, R.; Blaho, M.; Adamowicz, B.

2017-06-01

The key feature for the precise tuning of Vth in GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors is the control of the positive fixed charge (Qf) at the insulator/III-N interfaces, whose amount is often comparable to the negative surface polarization charge ( Qp o l -). In order to clarify the origin of Qf, we carried out a comprehensive capacitance-voltage (C-V) characterization of SiO2/AlxGa1-xN/GaN and SiN/AlxGa1-xN/GaN structures with Al composition (x) varying from 0.15 to 0.4. For both types of structures, we observed a significant Vth shift in C-V curves towards the positive gate voltage with increasing x. On the contrary, the Schottky gate structures exhibited Vth shift towards the more negative biases. From the numerical simulations of C-V curves using the Poisson's equation supported by the analytical calculations of Vth, we showed that the Vth shift in the examined MIS structures is due to a significant decrease in the positive Qf with rising x. Finally, we examined this result with respect to various hypotheses developed in the literature to explain the origin of the positive Qf at insulator/III-N interfaces.

Realization of synaptic learning and memory functions in Y2O3 based memristive device fabricated by dual ion beam sputtering

NASA Astrophysics Data System (ADS)

Das, Mangal; Kumar, Amitesh; Singh, Rohit; Than Htay, Myo; Mukherjee, Shaibal

2018-02-01

Single synaptic device with inherent learning and memory functions is demonstrated based on a forming-free amorphous Y2O3 (yttria) memristor fabricated by dual ion beam sputtering system. Synaptic functions such as nonlinear transmission characteristics, long-term plasticity, short-term plasticity and ‘learning behavior (LB)’ are achieved using a single synaptic device based on cost-effective metal-insulator-semiconductor (MIS) structure. An ‘LB’ function is demonstrated, for the first time in the literature, for a yttria based memristor, which bears a resemblance to certain memory functions of biological systems. The realization of key synaptic functions in a cost-effective MIS structure would promote much cheaper synapse for artificial neural network.

Noise characterization of enhancement-mode AlGaN graded barrier MIS-HEMT devices

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Saravana Kumar, R.; Mohankumar, N.

2017-12-01

This paper reports a systematic theoretical study on the microwave noise performance of graded AlGaN/GaN metal-insulator semiconductor high-electron mobility transistors (MIS-HEMTs) built on an Al2O3 substrate. The HfAlOx/AlGaN/GaN MIS-HEMT devices designed for this study show an outstanding small signal analog/RF and noise performance. The results on 1 μm gate length device show an enhancement mode operation with threshold voltage, VT = + 5.3 V, low drain leakage current, Ids,LL in the order of 1 × 10-9 A/mm along with high current gain cut-off frequency, fT of 17 GHz and maximum oscillation frequency fmax of 47 GHz at Vds = 10 V. The device Isbnd V and low-frequency noise estimation of the gate and drain noise spectral density and their correlation are evaluated using a Green's function method under different biasing conditions. The devices show a minimum noise figure (NFmin) of 1.053 dB in combination with equivalent noise resistance (Rn) of 23 Ω at 17 GHz, at Vgs = 6 V and Vds = 5 V which is relatively low and is suitable for broad-band low-noise amplifiers. This study shows that the graded AlGaN MIS-HEMT with HfAlOX gate insulator is appropriate for application requiring high-power and low-noise.

Nanostructured Anodic Multilayer Dielectric Stacked Metal-Insulator-Metal Capacitors.

PubMed

Karthik, R; Kannadassan, D; Baghini, Maryam Shojaei; Mallick, P S

2015-12-01

This paper presents the fabrication of Al2O3/TiO2/Al2O3 metal-insulator-metal (MIM) capacitor using anodization technique. High capacitance density of > 3.5 fF/μm2, low quadratic voltage coefficient of capacitance of < 115 ppm/V2 and a low leakage current density of 4.457 x 10(-11) A/cm2 at 3 V are achieved which are suitable for analog and mixed signal applications. We found that the anodization voltage played a major role in electrical and structural properties of the thin film. This work suggests that the anodization method can offer crystalline multilayer dielectric stack required for high performance MIM capacitor.

Control of Ga-oxide interlayer growth and Ga diffusion in SiO2/GaN stacks for high-quality GaN-based metal-oxide-semiconductor devices with improved gate dielectric reliability

NASA Astrophysics Data System (ADS)

Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Yamada, Hisashi; Takahashi, Tokio; Shimizu, Mitsuaki; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-01-01

A simple and feasible method for fabricating high-quality and highly reliable GaN-based metal-oxide-semiconductor (MOS) devices was developed. The direct chemical vapor deposition of SiO2 films on GaN substrates forming Ga-oxide interlayers was carried out to fabricate SiO2/GaO x /GaN stacked structures. Although well-behaved hysteresis-free GaN-MOS capacitors with extremely low interface state densities below 1010 cm-2 eV-1 were obtained by postdeposition annealing, Ga diffusion into overlying SiO2 layers severely degraded the dielectric breakdown characteristics. However, this problem was found to be solved by rapid thermal processing, leading to the superior performance of the GaN-MOS devices in terms of interface quality, insulating property, and gate dielectric reliability.

Electrical properties of MIS devices on CdZnTe/HgCdTe

NASA Astrophysics Data System (ADS)

Lee, Tae-Seok; Jeoung, Y. T.; Kim, Hyun Kyu; Kim, Jae Mook; Song, Jinhan; Ann, S. Y.; Lee, Ji Y.; Kim, Young Hun; Kim, Sun-Ung; Park, Mann-Jang; Lee, S. D.; Suh, Sang-Hee

1998-10-01

In this paper, we report the capacitance-voltage (C-V) properties of metal-insulator-semiconductor (MIS) devices on CdTe/HgCdTe by the metalorganic chemical vapor deposition (MOCVD) and CdZnTe/HgCdTe by thermal evaporation. In MOCVD, CdTe layers are directly grown on HgCdTe using the metal organic sources of DMCd and DiPTe. HgCdTe layers are converted to n-type and the carrier concentration, ND is low 1015 cm-3 after Hg-vacancy annealing at 260 degrees Celsius. In thermal evaporation, CdZnTe passivation layers were deposited on HgCdTe surfaces after the surfaces were etched with 0.5 - 2.0% bromine in methanol solution. To investigate the electrical properties of the MIS devices, the C-V measurement is conducted at 80 K and 1 MHz. C-V curve of MIS devices on CdTe/HgCdTe by MOCVD has shown nearly flat band condition and large hysteresis, which is inferred to result from many defects in CdTe layer induced during Hg-vacancy annealing process. A negative flat band voltage (VFB approximately equals -2 V) and a small hysteresis have been observed for MIS devices on CdZnTe/HgCdTe by thermal evaporation. It is inferred that the negative flat band voltage results from residual Te4+ on the surface after etching with bromine in methanol solution.

Insulator Charging in RF MEMS Capacitive Switches

DTIC Science & Technology

2005-06-01

and Simulations,” Journal of Microelectromechanical Systems, 8: 208-217 (June 1999). 5. Neaman , Donald. Semiconductor Physics & Devices. Boston...227-230 (2001). 5. Sze, S.M. Semiconductor Devices: Physics and Technology. New York: Wiley, 1985. 6. Neaman , Donald A. Semiconductor Physics...Radiation Response of Hafnium-Silicate Capacitors,” IEEE Transactions on Nuclear Science, 49: 3191-3196 (December 2002). 3. Neaman , D.A

Low temperature growth and electrical characterization of insulators for GaAs MISFETS

NASA Technical Reports Server (NTRS)

Borrego, J. M.; Ghandhi, S. K.

1981-01-01

Progress in the low temperature growth of oxides and layers on GaAs and the detailed electrical characterization of these oxides is reported. A plasma anodization system was designed, assembled, and put into operation. A measurement system was assembled for determining capacitance and conductance as a function of gate voltage for frequencies in the range from 1 Hz to 1 MHz. Initial measurements were carried out in Si-SiO2 capacitors in order to test the system and in GaAs MIS capacitors abricated using liquid anodization.

Electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP

NASA Astrophysics Data System (ADS)

Ferrandis, Philippe; Billaud, Mathilde; Duvernay, Julien; Martin, Mickael; Arnoult, Alexandre; Grampeix, Helen; Cassé, Mikael; Boutry, Hervé; Baron, Thierry; Vinet, Maud; Reimbold, Gilles

2018-04-01

To overcome the Fermi-level pinning in III-V metal-oxide-semiconductor capacitors, attention is usually focused on the choice of dielectric and surface chemical treatments prior to oxide deposition. In this work, we examined the influence of the III-V material surface cleaning and the semiconductor growth technique on the electrical properties of metal/Al2O3/In0.53Ga0.47As capacitors grown on InP(100) substrates. By means of the capacitance-voltage measurements, we demonstrated that samples do not have the same total oxide charge density depending on the cleaning solution used [(NH4)2S or NH4OH] prior to oxide deposition. The determination of the interface trap density revealed that a Fermi-level pinning occurs for samples grown by metalorganic chemical vapor deposition but not for similar samples grown by molecular beam epitaxy. Deep level transient spectroscopy analysis explained the Fermi-level pinning by an additional signal for samples grown by metalorganic chemical vapor deposition, attributed to the tunneling effect of carriers trapped in oxide toward interface states. This work emphasizes that the choice of appropriate oxide and cleaning treatment is not enough to prevent a Fermi-level pinning in III-V metal-oxide-semiconductor capacitors. The semiconductor growth technique needs to be taken into account because it impacts the trapping properties of the oxide.

Study and modeling of the transport mechanism in a Schottky diode on the basis of a GaAs semiinsulator

NASA Astrophysics Data System (ADS)

Resfa, A.; Smahi, Bourzig Y.; Menezla, Brahimi R.

2011-12-01

The current through a metal—semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of the semiconductor carriers in metal, thermionic emission-diffusion (TED) of carriers through a Schottky gate, and a mechanical quantum that pierces a tunnel through the gate. The system was solved by using a coupled Poisson—Boltzmann algorithm. Schottky BH is defined as the difference in energy between the Fermi level and the metal band carrier majority of the metal—semiconductor junction to the semiconductor contacts. The insulating layer converts the MS device in an MIS device and has a strong influence on its current—voltage (I—V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behaviour of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase in the process of thermionic electrons and holes, which will in turn act on the I—V characteristic of the diode, and an overflow maximum value [NT = 3 × 1020] is obtained. The I—V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.

Comparison of Multilayer Dielectric Thin Films for Future Metal-Insulator-Metal Capacitors: Al2O3/HfO2/Al2O3 versus SiO2/HfO2/SiO2

NASA Astrophysics Data System (ADS)

Park, Sang-Uk; Kwon, Hyuk-Min; Han, In-Shik; Jung, Yi-Jung; Kwak, Ho-Young; Choi, Woon-Il; Ha, Man-Lyun; Lee, Ju-Il; Kang, Chang-Yong; Lee, Byoung-Hun; Jammy, Raj; Lee, Hi-Deok

2011-10-01

In this paper, two kinds of multilayered metal-insulator-metal (MIM) capacitors using Al2O3/HfO2/Al2O3 (AHA) and SiO2/HfO2/SiO2 (SHS) were fabricated and characterized for radio frequency (RF) and analog mixed signal (AMS) applications. The experimental results indicate that the AHA MIM capacitor (8.0 fF/µm2) is able to provide a higher capacitance density than the SHS MIM capacitor (5.1 fF/µm2), while maintaining a low leakage current of about 50 nA/cm2 at 1 V. The quadratic voltage coefficient of capacitance, α gradually decreases as a function of stress time under constant voltage stress (CVS). The parameter variation of SHS MIM capacitors is smaller than that of AHA MIM capacitors. The effects of CVS on voltage linearity and time-dependent dielectric breakdown (TDDB) characteristics were also investigated.

Radiation hardening of metal-oxide semi-conductor (MOS) devices by boron

NASA Technical Reports Server (NTRS)

Danchenko, V.

1974-01-01

Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.

Ionic behavior of organic-inorganic metal halide perovskite based metal-oxide-semiconductor capacitors.

PubMed

Wang, Yucheng; Zhang, Yuming; Pang, Tiqiang; Xu, Jie; Hu, Ziyang; Zhu, Yuejin; Tang, Xiaoyan; Luan, Suzhen; Jia, Renxu

2017-05-24

Organic-inorganic metal halide perovskites are promising semiconductors for optoelectronic applications. Despite the achievements in device performance, the electrical properties of perovskites have stagnated. Ion migration is speculated to be the main contributing factor for the many unusual electrical phenomena in perovskite-based devices. Here, to understand the intrinsic electrical behavior of perovskites, we constructed metal-oxide-semiconductor (MOS) capacitors based on perovskite films and performed capacitance-voltage (C-V) and current-voltage (I-V) measurements of the capacitors. The results provide direct evidence for the mixed ionic-electronic transport behavior within perovskite films. In the dark, there is electrical hysteresis in both the C-V and I-V curves because the mobile negative ions take part in charge transport despite frequency modulation. However, under illumination, the large amount of photoexcited free carriers screens the influence of the mobile ions with a low concentration, which is responsible for the normal C-V properties. Validation of ion migration for the gate-control ability of MOS capacitors is also helpful for the investigation of perovskite MOS transistors and other gate-control photovoltaic devices.

Photoconductive detector of circularly polarized radiation based on a MIS structure with a CoPt layer

NASA Astrophysics Data System (ADS)

Kudrin, A. V.; Dorokhin, M. V.; Zdoroveishchev, A. V.; Demina, P. B.; Vikhrova, O. V.; Kalent'eva, I. L.; Ved', M. V.

2017-11-01

A photoconductive detector of circularly polarized radiation based on the metal-insulator-semiconductor structure of CoPt/(Al2O3/SiO2/Al2O3)/InGaAs/GaAs is created. The efficiency of detection of circularly polarized radiation is 0.75% at room temperature. The operation of the detector is based on the manifestation of the effect of magnetic circular dichroism in the CoPt layer, that is, the dependence of the CoPt transmission coefficient on the sign of the circular polarization of light and magnetization.

Novel Approach to Evaluation of Charging on Semiconductor Surface by Noncontact, Electrode-Free Capacitance/Voltage Measurement

NASA Astrophysics Data System (ADS)

Hirae, Sadao; Kohno, Motohiro; Okada, Hiroshi; Matsubara, Hideaki; Nakatani, Ikuyoshi; Kusuda, Tatsufumi; Sakai, Takamasa

1994-04-01

This paper describes a novel approach to the quantitative characterization of semiconductor surface charging caused by plasma exposures and ion implantations. The problems in conventional evaluation of charging are also discussed. Following the discussions above, the necessity of unified criteria is suggested for efficient development of systems or processes without charging damage. Hence, the charging saturation voltage between a top oxide surface and substrate, V s, and the charging density per unit area per second, ρ0, should be taken as criteria of charging behavior, which effectively represent the charging characteristics of both processes. The unified criteria can be obtained from the exposure time dependence of a net charging density on the thick field oxide. In order to determine V s and ρ0, the analysis using the C-V curve measured in a noncontact method with the metal-air-insulator-semiconductor (MAIS) technique is employed. The total space-charge density in oxide and its centroid can be determined at the same time by analyzing the flat-band voltage (V fb) of the MAIS capacitor as a function of the air gap. The net charge density can be obtained by analyzing the difference between the total space-charge density in oxide before and after charging. Finally, it is shown that charge damage of the large area metal-oxide-semiconductor (MOS) capacitor can be estimated from both V s and ρ0 which are obtained from results for a thick field oxide implanted with As+ and exposed to oxygen plasma.

Effect of atomic layer deposition temperature on current conduction in Al{sub 2}O{sub 3} films formed using H{sub 2}O oxidant

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hiraiwa, Atsushi, E-mail: hiraiwa@aoni.waseda.jp, E-mail: qs4a-hriw@asahi-net.or.jp; Matsumura, Daisuke; Kawarada, Hiroshi, E-mail: kawarada@waseda.jp

To develop high-performance, high-reliability gate insulation and surface passivation technologies for wide-bandgap semiconductor devices, the effect of atomic layer deposition (ALD) temperature on current conduction in Al{sub 2}O{sub 3} films is investigated based on the recently proposed space-charge-controlled field emission model. Leakage current measurement shows that Al{sub 2}O{sub 3} metal-insulator-semiconductor capacitors formed on the Si substrates underperform thermally grown SiO{sub 2} capacitors at the same average field. However, using equivalent oxide field as a more practical measure, the Al{sub 2}O{sub 3} capacitors are found to outperform the SiO{sub 2} capacitors in the cases where the capacitors are negatively biased andmore » the gate material is adequately selected to reduce virtual dipoles at the gate/Al{sub 2}O{sub 3} interface. The Al{sub 2}O{sub 3} electron affinity increases with the increasing ALD temperature, but the gate-side virtual dipoles are not affected. Therefore, the leakage current of negatively biased Al{sub 2}O{sub 3} capacitors is approximately independent of the ALD temperature because of the compensation of the opposite effects of increased electron affinity and permittivity in Al{sub 2}O{sub 3}. By contrast, the substrate-side sheet of charge increases with increasing ALD temperature above 210 °C and hence enhances the current of positively biased Al{sub 2}O{sub 3} capacitors more significantly at high temperatures. Additionally, an anomalous oscillatory shift of the current-voltage characteristics with ALD temperature was observed in positively biased capacitors formed by low-temperature (≤210 °C) ALD. This shift is caused by dipoles at the Al{sub 2}O{sub 3}/underlying SiO{sub 2} interface. Although they have a minimal positive-bias leakage current, the low-temperature-grown Al{sub 2}O{sub 3} films cause the so-called blisters problem when heated above 400 °C. Therefore, because of the absence of blistering, a 450 °C ALD process is presently the most promising technology for growing high-reliability Al{sub 2}O{sub 3} films.« less

Admittance of MIS-Structures Based on HgCdTe with a Double-Layer CdTe/Al2O3 Insulator

NASA Astrophysics Data System (ADS)

Dzyadukh, S. M.; Voitsekhovskii, A. V.; Nesmelov, S. N.; Sidorov, G. Yu.; Varavin, V. S.; Vasil'ev, V. V.; Dvoretsky, S. A.; Mikhailov, N. N.; Yakushev, M. V.

2018-03-01

Admittance of MIS structures based on n( p)- Hg1-xCdxTe (at x from 0.22 to 0.40) with SiO2/Si3N4, Al2O3, and CdTe/Al2O3 insulators is studied experimentally at 77 K. Growth of an intermediate CdTe layer during epitaxy results in the almost complete disappearance of the hysteresis of electrophysical characteristics of MIS structures based on graded-gap n-HgCdTe for a small range of the voltage variation. For a wide range of the voltage variation, the hysteresis of the capacitance-voltage characteristics appears for MIS structures based on n-HgCdTe with the CdTe/Al2O3 insulator. However, the hysteresis mechanism differs from that in case of a single-layer Al2O3 insulator. For MIS structures based on p-HgCdTe, introduction of an additional CdTe layer does not lead to a significant decrease of the hysteresis phenomena, which may be due to the degradation of the interface properties when mercury leaves the film as a result of low-temperature annealing changing the conductivity type of the semiconductor.

Screening-Engineered Field-Effect Solar Cells

DTIC Science & Technology

2012-01-01

virtually any semiconductor, including the promising but hard-to- dope metal oxides, sulfides, and phosphides.3 Prototype SFPV devices have been...MIS interface. Unfortu- nately, MIS cells, though sporting impressive efficiencies,4−6 typically have short operating lifetimes due to surface state...instability at the MIS interface.7 Methods aimed at direct field- effect “ doping ” of semiconductors, in which the voltage is externally applied to a gate

Determination of Insulator-to-Semiconductor Transition in Sol-Gel Oxide Semiconductors Using Derivative Spectroscopy.

PubMed

Lee, Woobin; Choi, Seungbeom; Kim, Kyung Tae; Kang, Jingu; Park, Sung Kyu; Kim, Yong-Hoon

2015-12-23

We report a derivative spectroscopic method for determining insulator-to-semiconductor transition during sol-gel metal-oxide semiconductor formation. When an as-spun sol-gel precursor film is photochemically activated and changes to semiconducting state, the light absorption characteristics of the metal-oxide film is considerable changed particularly in the ultraviolet region. As a result, a peak is generated in the first-order derivatives of light absorption ( A' ) vs. wavelength (λ) plots, and by tracing the peak center shift and peak intensity, transition from insulating-to-semiconducting state of the film can be monitored. The peak generation and peak center shift are described based on photon-energy-dependent absorption coefficient of metal-oxide films. We discuss detailed analysis method for metal-oxide semiconductor films and its application in thin-film transistor fabrication. We believe this derivative spectroscopy based determination can be beneficial for a non-destructive and a rapid monitoring of the insulator-to-semiconductor transition in sol-gel oxide semiconductor formation.

Amorphous silicon Schottky barrier solar cells incorporating a thin insulating layer and a thin doped layer

DOEpatents

Carlson, David E.

1980-01-01

Amorphous silicon Schottky barrier solar cells which incorporate a thin insulating layer and a thin doped layer adjacent to the junction forming metal layer exhibit increased open circuit voltages compared to standard rectifying junction metal devices, i.e., Schottky barrier devices, and rectifying junction metal insulating silicon devices, i.e., MIS devices.

Influence of the Compositional Grading on Concentration of Majority Charge Carriers in Near-Surface Layers of n(p)-HgCdTe Grown by Molecular Beam Epitaxy

NASA Astrophysics Data System (ADS)

Voitsekhovskii, A. V.; Nesmelov, S. N.; Dzyadukh, S. M.

2018-02-01

The capacitive characteristics of metal-insulator-semiconductor (MIS) structures based on the compositionally graded Hg1-xCdxTe created by molecular beam epitaxy have been experimentally investigated in a wide temperature range (8-77 K). A program has been developed for numerical simulation of ideal capacitance-voltage (C-V) characteristics in the low-frequency and high-frequency approximations. The concentrations of the majority carriers in the near-surface semiconductor layer are determined from the values of the capacitances in the minima of low-frequency C-V curves. For MIS structures based on p-Hg1-xCdxTe, the effect of the presence of the compositionally graded layer on the hole concentration in the near-surface semiconductor layer, determined from capacitive measurements, has not been established. Perhaps this is due to the fact that the concentration of holes in the near-surface layer largely depends on the type of dielectric coating and the regimes of its application. For MIS structures based on n-Hg1-x Cd x Te (x = 0.22-0.23) without a graded-gap layer, the electron concentration determined by the proposed method is close to the average concentration determined by the Hall measurements. The electron concentration in the near-surface semiconductor layer of the compositionally graded n-Hg1-x Cd x Te (x = 0.22-0.23) found from the minimum capacitance value is much higher than the average electron concentration determined by the Hall measurements. The results are qualitatively explained by the creation of additional intrinsic donor-type defects in the near-surface compositionally graded layer of n-Hg1-x Cd x Te.

Capacitors Would Help Protect Against Hypervelocity Impacts

NASA Technical Reports Server (NTRS)

Edwards, David; Hubbs, Whitney; Hovater, Mary

2007-01-01

A proposal investigates alternatives to the present bumper method of protecting spacecraft against impacts of meteoroids and orbital debris. The proposed method is based on a British high-voltage-capacitance technique for protecting armored vehicles against shaped-charge warheads. A shield, according to the proposal, would include a bare metal outer layer separated by a gap from an inner metal layer covered with an electrically insulating material. The metal layers would constitute electrodes of a capacitor. A bias potential would be applied between the metal layers. A particle impinging at hypervelocity on the outer metal layer would break apart into a debris cloud that would penetrate the electrical insulation on the inner metal layer. The cloud would form a path along which electric current could flow between the metal layers, thereby causing the capacitor to discharge. With proper design, the discharge current would be large enough to vaporize the particles in the debris cloud to prevent penetration of the spacecraft. The shield design can be mass optimized to be competitive with existing bumper designs. Parametric studies were proposed to determine optimum correction between bias voltage, impacting particle velocity, gap space, and insulating material required to prevent spacecraft penetration.

Photoisomerization-induced manipulation of single-electron tunneling for novel Si-based optical memory.

PubMed

Hayakawa, Ryoma; Higashiguchi, Kenji; Matsuda, Kenji; Chikyow, Toyohiro; Wakayama, Yutaka

2013-11-13

We demonstrated optical manipulation of single-electron tunneling (SET) by photoisomerization of diarylethene molecules in a metal-insulator-semiconductor (MIS) structure. Stress is placed on the fact that device operation is realized in the practical device configuration of MIS structure and that it is not achieved in structures based on nanogap electrodes and scanning probe techniques. Namely, this is a basic memory device configuration that has the potential for large-scale integration. In our device, the threshold voltage of SET was clearly modulated as a reversible change in the molecular orbital induced by photoisomerization, indicating that diarylethene molecules worked as optically controllable quantum dots. These findings will allow the integration of photonic functionality into current Si-based memory devices, which is a unique feature of organic molecules that is unobtainable with inorganic materials. Our proposed device therefore has enormous potential for providing a breakthrough in Si technology.

Metal-doped graphene layers composed with boron nitride-graphene as an insulator: a nano-capacitor.

PubMed

Monajjemi, Majid

2014-11-01

A model of a nanoscale dielectric capacitor composed of a few dopants has been investigated in this study. This capacitor includes metallic graphene layers which are separated by an insulating medium containing a few h-BN layers. It has been observed that the elements from group IIIA of the periodic table are more suitable as dopants for hetero-structures of the {metallic graphene/hBN/metallic graphene} capacitors compared to those from groups IA or IIA. In this study, we have specifically focused on the dielectric properties of different graphene/h-BN/graphene including their hetero-structure counterparts, i.e., Boron-graphene/h-BN/Boron-graphene, Al-graphene/h-BN/Al-graphene, Mg-graphene/h-BN/Mg-graphene, and Be-graphene/h-BN/Be-graphene stacks for monolayer form of dielectrics. Moreover, we studied the multi dielectric properties of different (h-BN)n/graphene hetero-structures of Boron-graphene/(h-BN)n/Boron-graphene.

Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

NASA Astrophysics Data System (ADS)

Singh, Anil; Agarwal, Alpana

2016-10-01

A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

Mechanism of leakage of ion-implantation isolated AlGaN/GaN MIS-high electron mobility transistors on Si substrate

NASA Astrophysics Data System (ADS)

Zhang, Zhili; Song, Liang; Li, Weiyi; Fu, Kai; Yu, Guohao; Zhang, Xiaodong; Fan, Yaming; Deng, Xuguang; Li, Shuiming; Sun, Shichuang; Li, Xiajun; Yuan, Jie; Sun, Qian; Dong, Zhihua; Cai, Yong; Zhang, Baoshun

2017-08-01

In this paper, we systematically investigated the leakage mechanism of the ion-implantation isolated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) on Si substrate. By means of combined DC tests at different temperatures and electric field dependence, we demonstrated the following original results: (1) It is proved that gate leakage is the main contribution to OFF-state leakage of ion-implantation isolated AlGaN/GaN MIS-HEMTs, and the gate leakage path is a series connection of the gate dielectric Si3N4 and Si3N4-GaN interface. (2) The dominant mechanisms of the leakage current through LPCVD-Si3N4 gate dielectric and Si3N4-GaN interface are identified to be Frenkel-Poole emission and two-dimensional variable range hopping (2D-VRH), respectively. (3) A certain temperature annealing could reduce the density of the interface state that produced by ion implantation, and consequently suppress the interface leakage transport, which results in a decrease in OFF-state leakage current of ion-implantation isolated AlGaN/GaN MIS-HEMTs.

Temperature-Dependent Electrical Properties and Carrier Transport Mechanisms of TMAH-Treated Ni/Au/Al2O3/GaN MIS Diode

NASA Astrophysics Data System (ADS)

Reddy, M. Siva Pratap; Puneetha, Peddathimula; Reddy, V. Rajagopal; Lee, Jung-Hee; Jeong, Seong-Hoon; Park, Chinho

2016-11-01

The temperature-dependent electrical properties and carrier transport mechanisms of tetramethylammonium hydroxide (TMAH)-treated Ni/Au/Al2O3/GaN metal-insulator-semiconductor (MIS) diodes have been investigated by current-voltage ( I- V) and capacitance-voltage ( C- V) measurements. The experimental results reveal that the barrier height ( I- V) increases whereas the ideality factor decreases with increasing temperature. The TMAH-treated Ni/Au/Al2O3/GaN MIS diode showed nonideal behaviors which indicate the presence of a nonuniform distribution of interface states ( N SS) and effect of series resistance ( R S). The obtained R S and N SS were found to decrease with increasing temperature. Furthermore, it was found that different transport mechanisms dominated in the TMAH-treated Ni/Au/Al2O3/GaN MIS diode. At 150 K to 250 K, Poole-Frenkel emission (PFE) was found to be responsible for the reverse leakage, while Schottky emission (SE) was the dominant mechanism at high electric fields in the temperature range from 300 K to 400 K. Feasible energy band diagrams and possible carrier transport mechanisms for the TMAH-treated Ni/Au/Al2O3/GaN MIS diode are discussed based on PFE and SE.

Multi-layer MOS capacitor based polarization insensitive electro-optic intensity modulator.

PubMed

Qiu, Xiaoming; Ruan, Xiaoke; Li, Yanping; Zhang, Fan

2018-05-28

In this study, a multi-layer metal-oxide-semiconductor capacitor (MLMOSC) polarization insensitive modulator is proposed. The design is validated by numerical simulation with commercial software LUMERICAL SOLUTION. Based on the epsilon-near-zero (ENZ) effect of indium tin oxide (ITO), the device manages to uniformly modulate both the transverse electric (TE) and the transverse magnetic (TM) modes. With a 20μm-long double-layer metal-oxide-semiconductor capacitor (DLMOSC) polarization insensitive modulator, in which two metal-oxide-semiconductor (MOS) structures are formed by the n-doped Si/HfO 2 /ITO/HfO 2 / n-doped Si stack, the extinction ratios (ERs) of both the TE and the TM modes can be over 20dB. The polarization dependent losses of the device can be as low as 0.05dB for the "OFF" state and 0.004dB for the "ON" state. Within 1dB polarization dependent loss, the device can operate with over 20dB ERs at the S, C, and L bands. The polarization insensitive modulator offers various merits including ultra-compact size, broadband spectrum, and complementary metal oxide semiconductor (CMOS) compatibility.

Testing and failure analysis to improve screening techniques for hermetically sealed metallized film capacitors for low energy applications

NASA Technical Reports Server (NTRS)

1982-01-01

Effective screening techniques are evaluated for detecting insulation resistance degradation and failure in hermetically sealed metallized film capacitors used in applications where low capacitor voltage and energy levels are common to the circuitry. A special test and monitoring system capable of rapidly scanning all test capacitors and recording faults and/or failures is examined. Tests include temperature cycling and storage as well as low, medium, and high voltage life tests. Polysulfone film capacitors are more heat stable and reliable than polycarbonate film units.

Leakage conduction behavior in electron-beam-cured nanoporous silicate films

NASA Astrophysics Data System (ADS)

Liu, Po-Tsun; Tsai, T. M.; Chang, T. C.

2005-05-01

This letter explores the application of electron-beam curing on nanoporous silicate films. The electrical conduction mechanism for the nanoporous silicate film cured by electron-beam radiation has been studied with metal-insulator-semiconductor capacitors. Electrical analyses over a varying temperature range from room temperature to 150°C provide evidence for space-charge-limited conduction in the electron-beam-cured thin film, while Schottky-emission-type leaky behavior is seen in the counterpart typically cured by a thermal furnace. A physical model consistent with electrical analyses is also proposed to deduce the origin of conduction behavior in the nanoporous silicate thin film.

Effects of ultrathin oxides in conducting MIS structures on GaAs

NASA Technical Reports Server (NTRS)

Childs, R. B.; Ruths, J. M.; Sullivan, T. E.; Fonash, S. J.

1978-01-01

Schottky barrier-type GaAs baseline devices (semiconductor surface etched and then immediately metalized) and GaAs conducting metal oxide-semiconductor devices are fabricated and characterized. The baseline surfaces (no purposeful oxide) are prepared by a basic or an acidic etch, while the surface for the MIS devices are prepared by oxidizing after the etch step. The metallizations used are thin-film Au, Ag, Pd, and Al. It is shown that the introduction of purposeful oxide into these Schottky barrier-type structures examined on n-type GaAs modifies the barrier formation, and that thin interfacial layers can modify barrier formation through trapping and perhaps chemical reactions. For Au- and Pd-devices, enhanced photovoltaic performance of the MIS configuration is due to increased barrier height.

Impacts of oxidants in atomic layer deposition method on Al2O3/GaN interface properties

NASA Astrophysics Data System (ADS)

Taoka, Noriyuki; Kubo, Toshiharu; Yamada, Toshikazu; Egawa, Takashi; Shimizu, Mitsuaki

2018-01-01

The electrical interface properties of GaN metal-oxide-semiconductor (MOS) capacitors with an Al2O3 gate insulator formed by atomic layer deposition method using three kinds of oxidants were investigated by the capacitance-voltage technique, Terman method, and conductance method. We found that O3 and the alternate supply of H2O and O3 (AS-HO) are effective for reducing the interface trap density (D it) at the energy range of 0.15 to 0.30 eV taking from the conduction band minimum. On the other hand, we found that surface potential fluctuation (σs) induced by interface charges for the AS-HO oxidant is much larger than that for a Si MOS capacitor with a SiO2 layer formed by chemical vapor deposition despite the small D it values for the AS-HO oxidant compared with the Si MOS capacitor. This means that the total charged center density including the fixed charge density, charged slow trap density, and charged interface trap density for the GaN MOS capacitor is higher than that for the Si MOS capacitor. Therefore, σs has to be reduced to improve the performances and reliability of GaN devices with the Al2O3/GaN interfaces.

Luminance compensation for AMOLED displays using integrated MIS sensors

NASA Astrophysics Data System (ADS)

Vygranenko, Yuri; Fernandes, Miguel; Louro, Paula; Vieira, Manuela

2017-05-01

Active-matrix organic light-emitting diodes (AMOLEDs) are ideal for future TV applications due to their ability to faithfully reproduce real images. However, pixel luminance can be affected by instability of driver TFTs and aging effect in OLEDs. This paper reports on a pixel driver utilizing a metal-insulator-semiconductor (MIS) sensor for luminance control of the OLED element. In the proposed pixel architecture for bottom-emission AMOLEDs, the embedded MIS sensor shares the same layer stack with back-channel etched a Si:H TFTs to maintain the fabrication simplicity. The pixel design for a large-area HD display is presented. The external electronics performs image processing to modify incoming video using correction parameters for each pixel in the backplane, and also sensor data processing to update the correction parameters. The luminance adjusting algorithm is based on realistic models for pixel circuit elements to predict the relation between the programming voltage and OLED luminance. SPICE modeling of the sensing part of the backplane is performed to demonstrate its feasibility. Details on the pixel circuit functionality including the sensing and programming operations are also discussed.

High-temperature properties of ceramic fibers and insulations for thermal protection of atmospheric entry and hypersonic cruise vehicles

NASA Technical Reports Server (NTRS)

Kourtides, Demetrius A.; Pitts, William C.; Araujo, Myrian; Zimmerman, R. S.

1988-01-01

Multilayer insulations (MIs) which will operate in the 500 to 1000 C temperature range are being considered for possible applications on aerospace vehicles subject to convective and radiative heating during atmospheric entry. The insulations described consist of ceramic fibers, insulations, and metal foils quilted together with ceramic thread. As these types of insulations have highly anisotropic properties, the total heat transfer characteristics must be determined. Data are presented on the thermal diffusivity and thermal conductivity of four types of MIs and are compared to the baseline Advanced Flexible Reusable Surface Insulation currently used on the Space Shuttle Orbiter. In addition, the high temperature properties of the fibers used in these MIs are discussed. The fibers investigated included silica and three types of aluminoborosilicate (ABS). Static tension tests were performed at temperatures up to 1200 C and the ultimate strain, tensile strength, and tensile modulus of single fibers were determined.

High temperature properties of ceramic fibers and insulations for thermal protection of atmospheric entry and hypersonic cruise vehicles

NASA Technical Reports Server (NTRS)

Kourtides, Demetrius A.; Pitts, William C.; Araujo, Myrian; Zimmerman, R. S.

1988-01-01

Multilayer insulations (MIs) which will operate in the 500 to 1000 C temperature range are being considered for possible applications on aerospace vehicles subject to convective and radiative heating during atmospheric entry. The insulations described consist of ceramic fibers, insulations, and metal foils quilted together with ceramic thread. As these types of insulations have highly anisotropic properties, the total heat transfer characteristics must be determined. Data are presented on the thermal diffusivity and thermal conductivity of four types of MIs and are compared to the baseline Advanced Flexible Reusable Surface Insulation currently used on the Space Shuttle Orbiter. In addition, the high temperature properties of the fibers used in these MIs are discussed. The fibers investigated included silica and three types of aluminoborosilicate (ABS). Static tension tests were performed at temperatures up to 1200 C and the ultimate strain, tensile strength, and tensile modulus of single fibers were determined.

Tungsten polyoxometalate molecules as active nodes for dynamic carrier exchange in hybrid molecular/semiconductor capacitors

NASA Astrophysics Data System (ADS)

Balliou, A.; Douvas, A. M.; Normand, P.; Tsikritzis, D.; Kennou, S.; Argitis, P.; Glezos, N.

2014-10-01

In this work we study the utilization of molecular transition metal oxides known as polyoxometalates (POMs), in particular the Keggin structure anions of the formula PW12O403-, as active nodes for potential switching and/or fast writing memory applications. The active molecules are being integrated in hybrid Metal-Insulator/POM molecules-Semiconductor capacitors, which serve as prototypes allowing investigation of critical performance characteristics towards the design of more sophisticated devices. The charging ability as well as the electronic structure of the molecular layer is probed by means of electrical characterization, namely, capacitance-voltage and current-voltage measurements, as well as transient capacitance measurements, C (t), under step voltage polarization. It is argued that the transient current peaks observed are manifestations of dynamic carrier exchange between the gate electrode and specific molecular levels, while the transient C (t) curves under conditions of molecular charging can supply information for the rate of change of the charge that is being trapped and de-trapped within the molecular layer. Structural characterization via surface and cross sectional scanning electron microscopy as well as atomic force microscopy, spectroscopic ellipsometry, UV and Fourier-transform IR spectroscopies, UPS, and XPS contribute to the extraction of accurate electronic structure characteristics and open the path for the design of new devices with on-demand tuning of their interfacial properties via the controlled preparation of the POM layer.

Low leakage Ru-strontium titanate-Ru metal-insulator-metal capacitors for sub-20 nm technology node in dynamic random access memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Popovici, M., E-mail: Mihaela.Ioana.Popovici@imec.be; Swerts, J.; Redolfi, A.

2014-02-24

Improved metal-insulator-metal capacitor (MIMCAP) stacks with strontium titanate (STO) as dielectric sandwiched between Ru as top and bottom electrode are shown. The Ru/STO/Ru stack demonstrates clearly its potential to reach sub-20 nm technology nodes for dynamic random access memory. Downscaling of the equivalent oxide thickness, leakage current density (J{sub g}) of the MIMCAPs, and physical thickness of the STO have been realized by control of the Sr/Ti ratio and grain size using a heterogeneous TiO{sub 2}/STO based nanolaminate stack deposition and a two-step crystallization anneal. Replacement of TiN with Ru as both top and bottom electrodes reduces the amount of electricallymore » active defects and is essential to achieve a low leakage current in the MIM capacitor.« less

The Research Laboratory of Electronics Progress Report Number 133, January 1-December 1990

DTIC Science & Technology

1990-12-31

4 6 Chapter 7 High-Frequency InAlAs/InGaAs Metal -Insulator-Doped Semiconductor...Epitaxy of Compound Semiconductors Chapter 7 High-Frequency InAlAs/InGaAs Metal -Insulator- Doped Semiconductor Field-Effect Transistors (MIDFETs) for...aligned silicided NMOS posed of refractory metals to allow a subsequentdevice fabrication. We have used cobalt deposi- high temperature anneal. This

All-semiconductor metamaterial-based optical circuit board at the microscale

DOE Office of Scientific and Technical Information (OSTI.GOV)

Min, Li; Huang, Lirong, E-mail: lrhuang@hust.edu.cn

2015-07-07

The newly introduced metamaterial-based optical circuit, an analogue of electronic circuit, is becoming a forefront topic in the fields of electronics, optics, plasmonics, and metamaterials. However, metals, as the commonly used plasmonic elements in an optical circuit, suffer from large losses at the visible and infrared wavelengths. We propose here a low-loss, all-semiconductor metamaterial-based optical circuit board at the microscale by using interleaved intrinsic GaAs and doped GaAs, and present the detailed design process for various lumped optical circuit elements, including lumped optical inductors, optical capacitors, optical conductors, and optical insulators. By properly combining these optical circuit elements and arrangingmore » anisotropic optical connectors, we obtain a subwavelength optical filter, which can always hold band-stop filtering function for various polarization states of the incident electromagnetic wave. All-semiconductor optical circuits may provide a new opportunity in developing low-power and ultrafast components and devices for optical information processing.« less

Liquid Drop Actuation by Photoelectrowetting

NASA Astrophysics Data System (ADS)

Palma, Cesar

In electrowetting an electric potential is applied between a droplet of electrolyte and a conductor separated by an insulator. The repulsion of like charges deforms and spreads the droplet until capillary and electric forces are in equilibrium. Photoelectrowetting is a light-triggered version of electrowetting where the conductor is replaced by a moderately-doped semiconductor. The electrolyte-insulator-semiconductor stack resembles a metal-insulator-semiconductor capacitor, which has the special property that the amount of charge that can be injected into it increases when exposed to light. Thus in photoelectrowetting the exposure of light spreads the droplet further than in unilluminated conditions. In this thesis a scheme is presented for moving drops on a surface using photoelectrowetting. In order to understand photoelectrowetting I conducted a study of electrowetting with semiconductors. Devices were constructed using moderately-doped p-type silicon wafers (Na = 8.6 x 1014 cm-3) coated with a bilayer composed of thermal oxide (100 nm) and teflon (265 nm). Electric biases (< 40 V) were applied between droplets of electrolyte (10 microliter, 10 mM NaCl) and the silicon wafer, resulting in deformations of the droplet. These changes were quantified with contact angle measurements which varied from 120° at zero bias to 90° at 40V depending on the conditions of the experiment. Three regimes were observed depending on the polarity of the bias and above-bandgap illumination impinging on the droplet, corresponding to the charge regimes of an MIS capacitor: accumulation, inversion and deep-depletion. I present a model for these wetting changes based on a balance of capillary and electrostatic forces. After accounting for various non-ideal effects, I find that the model agrees with the data. I demonstrate that it is essential to account for interface traps in our devices (1.8 x 1011 cm-2) in the deep-depletion regime, leading to a 33% (4?) correction to the prediction at 40V. I elucidate the nature of the photoelectrowetting effect and find that contrary to reports in the literature the transition is not reversible by light alone. In the next phase of my thesis, I demonstrate how photoelectrowetting triggered with a light beam on one side moves the droplet along a surface. Comparable with traditional electrowetting-based devices, I achieve speeds of up to 12 mm/s with 10 microliter drops of electrolyte (1% w/w NaCl) with a surfactant (5 mM NaCl) using an oscillating electric potential composed of an AC bias of magnitude 32.5 Vpp and a DC offset of -7 V cycled at a frequency of 15 kHz and a laser intensity of 40 mW/cm2 (lambda = 660nm). I measure the speed for varying magnitude and frequency of the bias, laser intensity, droplet size and viscosity. The optimal cycling frequency is set by competing effects: on the low frequency side (< 15 kHz) the speed is limited by migration of carriers from the illuminated to the non-illuminated regions under the drop, and on the high frequency side (> 15 kHz) the speed is limited by the laser intensity. I present a model for the speed incorporating these effects that compares favorably with experiment. I present results of simulations of minority charge carrier concentrations in depletion regions. These exhibit self-similarity in space and time. The front of the concentrations follows a power law in time with an exponent that depends on the dopant concentration. Predictions from the power laws compare favorably with experiment.

Ordered porous mesostructured materials from nanoparticle-block copolymer self-assembly

DOEpatents

Warren, Scott; Wiesner, Ulrich; DiSalvo, Jr., Francis J

2013-10-29

The invention provides mesostructured materials and methods of preparing mesostructured materials including metal-rich mesostructured nanoparticle-block copolymer hybrids, porous metal-nonmetal nanocomposite mesostructures, and ordered metal mesostructures with uniform pores. The nanoparticles can be metal, metal alloy, metal mixture, intermetallic, metal-carbon, metal-ceramic, semiconductor-carbon, semiconductor-ceramic, insulator-carbon or insulator-ceramic nanoparticles, or combinations thereof. A block copolymer/ligand-stabilized nanoparticle solution is cast, resulting in the formation of a metal-rich (or semiconductor-rich or insulator-rich) mesostructured nanoparticle-block copolymer hybrid. The hybrid is heated to an elevated temperature, resulting in the formation of an ordered porous nanocomposite mesostructure. A nonmetal component (e.g., carbon or ceramic) is then removed to produce an ordered mesostructure with ordered and large uniform pores.

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Role of direct electron-phonon coupling across metal-semiconductor interfaces in thermal transport via molecular dynamics.

PubMed

Lin, Keng-Hua; Strachan, Alejandro

2015-07-21

Motivated by significant interest in metal-semiconductor and metal-insulator interfaces and superlattices for energy conversion applications, we developed a molecular dynamics-based model that captures the thermal transport role of conduction electrons in metals and heat transport across these types of interface. Key features of our model, denoted eleDID (electronic version of dynamics with implicit degrees of freedom), are the natural description of interfaces and free surfaces and the ability to control the spatial extent of electron-phonon (e-ph) coupling. Non-local e-ph coupling enables the energy of conduction electrons to be transferred directly to the semiconductor/insulator phonons (as opposed to having to first couple to the phonons in the metal). We characterize the effect of the spatial e-ph coupling range on interface resistance by simulating heat transport through a metal-semiconductor interface to mimic the conditions of ultrafast laser heating experiments. Direct energy transfer from the conduction electrons to the semiconductor phonons not only decreases interfacial resistance but also increases the ballistic transport behavior in the semiconductor layer. These results provide new insight for experiments designed to characterize e-ph coupling and thermal transport at the metal-semiconductor/insulator interfaces.

Waveguide embedded plasmon laser with multiplexing and electrical modulation

DOEpatents

Ma, Ren-min; Zhang, Xiang

2017-08-29

This disclosure provides systems, methods, and apparatus related to nanometer scale lasers. In one aspect, a device includes a substrate, a line of metal disposed on the substrate, an insulating material disposed on the line of metal, and a line of semiconductor material disposed on the substrate and the insulating material. The line of semiconductor material overlaying the line of metal, disposed on the insulating material, forms a plasmonic cavity.

Unstable behaviour of normally-off GaN E-HEMT under short-circuit

NASA Astrophysics Data System (ADS)

Martínez, P. J.; Maset, E.; Sanchis-Kilders, E.; Esteve, V.; Jordán, J.; Bta Ejea, J.; Ferreres, A.

2018-04-01

The short-circuit capability of power switching devices plays an important role in fault detection and the protection of power circuits. In this work, an experimental study on the short-circuit (SC) capability of commercial 600 V Gallium Nitride enhancement-mode high-electron-mobility transistors (E-HEMT) is presented. A different failure mechanism has been identified for commercial p-doped GaN gate (p-GaN) HEMT and metal-insulator-semiconductor (MIS) HEMT. In addition to the well known thermal breakdown, a premature breakdown is shown on both GaN HEMTs, triggered by hot electron trapping at the surface, which demonstrates that current commercial GaN HEMTs has requirements for improving their SC ruggedness.

Interface properties of MIS structures based on hetero-epitaxial graded-gap Hg1-xCdxTe with CdTe interlayer created in situ during MBE growth

NASA Astrophysics Data System (ADS)

Voitsekhovskii, Alexander V.; Nesmelov, Sergey N.; Dzyadukh, Stanislav M.; Varavin, Vasily S.; Dvoretsky, Sergey A.; Mikhailov, Nikolay N.; Yakushev, Maksim V.; Sidorov, Georgy Yu.

2017-11-01

Heterostructures based on n-Hg1-xCdxTe (x = 0.23-0.40) with near-surface graded-gap layers were grown by molecular beam epitaxy on Si (013) substrates. At 77 K, the admittance of the In/Al2O3/Hg1-xCdxTe metal-insulator-semiconductor (MIS) structures with grown in situ CdTe intermediate layer and without such a layer was investigated. It has been established that MIS structures of In/Al2O3/Hg1-xCdxTe with an interlayer of in situ grown CdTe are characterized by the electrical strength of the dielectric and the qualitative interface. The hysteresis of the capacitive characteristics is practically absent within a small range of variation in the bias voltage. The density of fast surface states at the minimum does not exceed 2.2 × 1010 eV-1 cm-2. MIS structures of In/Al2O3/Hg1-xCdxTe without an intermediate layer of CdTe have significantly higher densities of fast and slow surface states, as well as lower values of the differential resistance of the space-charge region in the regime of strong inversion.

Nanostructured bilayer anodic TiO2/Al2O3 metal-insulator-metal capacitor.

PubMed

Karthik, R; Kannadassan, D; Baghini, Maryam Shojaei; Mallick, P S

2013-10-01

This paper presents the fabrication of high performance bilayer TiO2/Al2O3 Metal-Insulator-Metal capacitor using anodization technique. A high capacitance density of 7 fF/microm2, low quadratic voltage coefficient of capacitance of 150 ppm/V2 and a low leakage current density of 9.1 nA/cm2 at 3 V are achieved which are suitable for Analog and Mixed signal applications. The influence of anodization voltage on structural and electrical properties of dielectric stack is studied in detail. At higher anodization voltages, we have observed the transformation of amorphous to crystalline state of TiO2/Al2O3 and improvement of electrical properties.

Abrupt Depletion Layer Approximation for the Metal Insulator Semiconductor Diode.

ERIC Educational Resources Information Center

Jones, Kenneth

1979-01-01

Determines the excess surface change carrier density, surface potential, and relative capacitance of a metal insulator semiconductor diode as a function of the gate voltage, using the precise questions and the equations derived with the abrupt depletion layer approximation. (Author/GA)

Comprehensive electrical analysis of metal/Al2O3/O-terminated diamond capacitance

NASA Astrophysics Data System (ADS)

Pham, T. T.; Maréchal, A.; Muret, P.; Eon, D.; Gheeraert, E.; Rouger, N.; Pernot, J.

2018-04-01

Metal oxide semiconductor capacitors were fabricated using p - type oxygen-terminated (001) diamond and Al2O3 deposited by atomic layer deposition at two different temperatures 250 °C and 380 °C. Current voltage I(V), capacitance voltage C(V), and capacitance frequency C(f) measurements were performed and analyzed for frequencies ranging from 1 Hz to 1 MHz and temperatures from 160 K to 360 K. A complete model for the Metal-Oxide-Semiconductor Capacitors electrostatics, leakage current mechanisms through the oxide into the semiconductor and small a.c. signal equivalent circuit of the device is proposed and discussed. Interface states densities are then evaluated in the range of 1012eV-1cm-2 . The strong Fermi level pinning is demonstrated to be induced by the combined effects of the leakage current through the oxide and the presence of diamond/oxide interface states.

The effects of layering in ferroelectric Si-doped HfO{sub 2} thin films

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lomenzo, Patrick D.; Nishida, Toshikazu, E-mail: nishida@ufl.edu; Takmeel, Qanit

2014-08-18

Atomic layer deposited Si-doped HfO{sub 2} thin films approximately 10 nm thick are deposited with various Si-dopant concentrations and distributions. The ferroelectric behavior of the HfO{sub 2} thin films are shown to be dependent on both the Si mol. % and the distribution of Si-dopants. Metal-ferroelectric-insulator-semiconductor capacitors are shown to exhibit a tunable remanent polarization through the adjustment of the Si-dopant distribution at a constant Si concentration. Inhomogeneous layering of Si-dopants within the thin films effectively lowers the remanent polarization. A pinched hysteresis loop is observed for higher Si-dopant concentrations and found to be dependent on the Si layering distribution.

Atomic layer deposition of ZrO2 on W for metal-insulator-metal capacitor application

NASA Astrophysics Data System (ADS)

Lee, Sang-Yun; Kim, Hyoungsub; McIntyre, Paul C.; Saraswat, Krishna C.; Byun, Jeong-Soo

2003-04-01

A metal-insulator-metal (MIM) capacitor using ZrO2 on tungsten (W) metal bottom electrode was demonstrated and characterized in this letter. Both ZrO2 and W metal were synthesized by an atomic layer deposition (ALD) method. High-quality 110˜115 Å ZrO2 films were grown uniformly on ALD W using ZrCl4 and H2O precursors at 300 °C, and polycrystalline ZrO2 in the ALD regime could be obtained. A 13˜14-Å-thick interfacial layer between ZrO2 and W was observed after fabrication, and it was identified as WOx through angle-resolved x-ray photoelectron spectroscopy analysis with wet chemical etching. The apparent equivalent oxide thickness was 20˜21 Å. An effective dielectric constant of 22˜25 including an interfacial WOx layer was obtained by measuring capacitance and thickness of MIM capacitors with Pt top electrodes. High capacitance per area (16˜17 fF/μm2) and low leakage current (10-7 A/cm2 at ±1 V) were achieved.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

NASA Astrophysics Data System (ADS)

Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

2017-03-01

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

Electrical and optical properties of diketopyrrolopyrrole-based copolymer interfaces in thin film devices.

PubMed

Adil, Danish; Kanimozhi, Catherine; Ukah, Ndubuisi; Paudel, Keshab; Patil, Satish; Guha, Suchi

2011-05-01

Two donor-acceptor diketopyrrolopyrrole (DPP)-based copolymers (PDPP-BBT and TDPP-BBT) have been synthesized for their application in organic devices such as metal-insulator semiconductor (MIS) diodes and field-effect transistors (FETs). The semiconductor-dielectric interface was characterized by capacitance-voltage and conductance-voltage methods. These measurements yield an interface trap density of 4.2 × 10(12) eV⁻¹ cm⁻² in TDPP-BBT and 3.5 × 10¹² eV⁻¹ cm⁻² in PDPP-BBT at the flat-band voltage. The FETs based on these spincoated DPP copolymers display p-channel behavior with hole mobilities of the order 10⁻³ cm²/(Vs). Light scattering studies from PDPP-BBT FETs show almost no change in the Raman spectrum after the devices are allowed to operate at a gate voltage, indicating that the FETs suffer minimal damage due to the metal-polymer contact or the application of an electric field. As a comparison Raman intensity profile from the channel-Au contact layer in pentacene FETs are presented, which show a distinct change before and after biasing.

Direct Fabrication of Inkjet-Printed Dielectric Film for Metal-Insulator-Metal Capacitors

NASA Astrophysics Data System (ADS)

Cho, Cheng-Lin; Kao, Hsuan-ling; Wu, Yung-Hsien; Chang, Li-Chun; Cheng, Chun-Hu

2018-01-01

In this study, an inkjet-printed dielectric film that used a polymer-based SU-8 ink was fabricated for use in a metal-insulator-metal (MIM) capacitor. Thermal treatment of the inkjet-printed SU-8 polymer film affected its surface morphology, chemical structure, and surface wettability. A 20-min soft-bake at 60°C was applied to eliminate inkjet-printed bubbles and ripples. The ultraviolet-exposed SU-8 polymer film was crosslinked at temperatures between 120°C and 220°C and became disordered at 270°C, demonstrated using Fourier-transform infrared spectroscopy. A maximum SU-8 polymer film hard-bake temperature of 120°C was identified, and a printing process was subsequently employed because the appropriate water contact angle of the printed film was 79°. Under the appropriate inkjet printing conditions, the two-transmission-line method was used to extract the dielectric and electrical properties of the SU-8 polymer film, and the electrical behavior of the fabricated MIM capacitor was also characterized.

Tuning the Schottky rectification in graphene-hexagonal boron nitride-molybdenum disulfide heterostructure.

PubMed

Liu, Biao; Zhao, Yu-Qing; Yu, Zhuo-Liang; Wang, Lin-Zhi; Cai, Meng-Qiu

2018-03-01

It was still a great challenge to design high performance of rectification characteristic for the rectifier diode. Lately, a new approach was proposed experimentally to tune the Schottky barrier height (SBH) by inserting an ultrathin insulated tunneling layer to form metal-insulator-semiconductor (MIS) heterostructures. However, the electronic properties touching off the high performance of these heterostructures and the possibility of designing more efficient applications for the rectifier diode were not presently clear. In this paper, the structural, electronic and interfacial properties of the novel MIS diode with the graphene/hexagonal boron nitride/monolayer molybdenum disulfide (GBM) heterostructure had been investigated by first-principle calculations. The calculated results showed that the intrinsic properties of graphene and MoS 2 were preserved due to the weak van der Waals contact. The height of interfacial Schottky barrier can be tuned by the different thickness of hBN layers. In addition, the GBM Schottky diode showed more excellent rectification characteristic than that of GM Schottky diode due to the interfacial band bending caused by the epitaxial electric field. Based on the electronic band structure, we analyzed the relationship between the electronic structure and the nature of the Schottky rectifier, and revealed the potential of utilizing GBM Schottky diode for the higher rectification characteristic devices. Copyright © 2017 Elsevier Inc. All rights reserved.

Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

PubMed

Ha, Mingjing; Zhang, Wei; Braga, Daniele; Renn, Michael J; Kim, Chris H; Frisbie, C Daniel

2013-12-26

In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

Interface Si donor control to improve dynamic performance of AlGaN/GaN MIS-HEMTs

NASA Astrophysics Data System (ADS)

Song, Liang; Fu, Kai; Zhang, Zhili; Sun, Shichuang; Li, Weiyi; Yu, Guohao; Hao, Ronghui; Fan, Yaming; Shi, Wenhua; Cai, Yong; Zhang, Baoshun

2017-12-01

In this letter, we have studied the performance of AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with different interface Si donor incorporation which is tuned during the deposition process of LPCVD-SiNx which is adopted as gate dielectric and passivation layer. Current collapse of the MIS-HEMTs without field plate is suppressed more effectively by increasing the SiH2Cl2/NH3 flow ratio and the normalized dynamic on-resistance (RON) is reduced two orders magnitude after off-state VDS stress of 600 V for 10 ms. Through interface characterization, we have found that the interface deep-level traps distribution with high Si donor incorporation by increasing the SiH2Cl2/NH3 flow ratio is lowered. It's indicated that the Si donors are most likely to fill and screen the deep-level traps at the interface resulting in the suppression of slow trapping process and the virtual gate effect. Although the Si donor incorporation brings about the increase of gate leakage current (IGS), no clear degradation of breakdown voltage can be seen by choosing appropriate SiH2Cl2/NH3 flow ratio.

Metal-insulator-semiconductor heterostructures for plasmonic hot-carrier optoelectronics.

PubMed

García de Arquer, F Pelayo; Konstantatos, Gerasimos

2015-06-01

Plasmonic hot-electron devices are attractive candidates for light-energy harvesting and photodetection applications. For solid state devices, the most compact and straightforward architecture is the metal-semiconductor Schottky junction. However convenient, this structure introduces limitations such as the elevated dark current associated to thermionic emission, or constraints for device design due to the finite choice of materials. In this work we theoretically consider the metal-insulator-semiconductor heterojunction as a candidate for plasmonic hot-carrier photodetection and solar cells. The presence of the insulating layer can significantly reduce the dark current, resulting in increased device performance with predicted solar power conversion efficiencies up to 9%. For photodetection, the sensitivity can be extended well into the infrared by a judicious choice of the insulating layer, with up to 300-fold expected enhancement in detectivity.

Quantum spin liquids and the metal-insulator transition in doped semiconductors.

PubMed

Potter, Andrew C; Barkeshli, Maissam; McGreevy, John; Senthil, T

2012-08-17

We describe a new possible route to the metal-insulator transition in doped semiconductors such as Si:P or Si:B. We explore the possibility that the loss of metallic transport occurs through Mott localization of electrons into a quantum spin liquid state with diffusive charge neutral "spinon" excitations. Such a quantum spin liquid state can appear as an intermediate phase between the metal and the Anderson-Mott insulator. An immediate testable consequence is the presence of metallic thermal conductivity at low temperature in the electrical insulator near the metal-insulator transition. Further, we show that though the transition is second order, the zero temperature residual electrical conductivity will jump as the transition is approached from the metallic side. However, the electrical conductivity will have a nonmonotonic temperature dependence that may complicate the extrapolation to zero temperature. Signatures in other experiments and some comparisons with existing data are made.

Evaluation of the density of the charge trapped in organic ferroelectric capacitors based on the Mott-Schottky model

NASA Astrophysics Data System (ADS)

Kim, Won-Ho; Kwon, Jin-Hyuk; Park, Gyeong-Tae; Kim, Jae-Hyun; Bae, Jin-Hyuk; Zhang, Xue; Park, Jaehoon

2014-09-01

Organic ferroelectric capacitors were fabricated using pentacene and poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as an organic semiconductor and a ferroelectric material, respectively. A paraelectric poly(vinyl cinnamate) layer was adopted as an interlayer between the PVDF-TrFE layer and the bottom electrode. The paraelectric interlayer induced a depolarization field opposite to the direction of the polarization formed in the ferroelectric PVDF-TrFE insulator, thereby suppressing spontaneous polarization. As a result, the Mott-Schottky model could be used to evaluate, from the extracted flat-band voltages, the density of the charge trapped in the organic ferroelectric capacitors.

Positron studies of metal-oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Au, H. L.; Asoka-Kumar, P.; Nielsen, B.; Lynn, K. G.

1993-03-01

Positron annihilation spectroscopy provides a new probe to study the properties of interface traps in metal-oxide semiconductors (MOS). Using positrons, we have examined the behavior of the interface traps as a function of gate bias. We propose a simple model to explain the positron annihilation spectra from the interface region of a MOS capacitor.

MOSFET and MOS capacitor responses to ionizing radiation

NASA Technical Reports Server (NTRS)

Benedetto, J. M.; Boesch, H. E., Jr.

1984-01-01

The ionizing radiation responses of metal oxide semiconductor (MOS) field-effect transistors (FETs) and MOS capacitors are compared. It is shown that the radiation-induced threshold voltage shift correlates closely with the shift in the MOS capacitor inversion voltage. The radiation-induced interface-state density of the MOSFETs and MOS capacitors was determined by several techniques. It is shown that the presence of 'slow' states can interfere with the interface-state measurements.

Magnetocapacitance and the physics of solid state interfaces

NASA Astrophysics Data System (ADS)

Hebard, Arthur

2008-10-01

When Herbert Kroemer stated in his Nobel address [1] that ``the interface is the device,'' he was implicitly acknowledging the importance of understanding the physics of interfaces. If interfaces are to have character traits, then ``impedance'' (or complex capacitance) would be a commonly used descriptor. In this talk I will discuss the use of magnetic fields to probe the ``character'' of a variety of interfaces including planar capacitor structures with magnetic electrodes, simple metal/semiconductor contacts (Schottky barriers) and the interface-dominated competition on microscopic length scales between ferromagnetic metallic and charge-ordered insulating phases in complex oxides. I will show that seeking experimental answers to surprisingly simple questions often leads to striking results that seriously challenge theoretical understanding. Perhaps Herbert Kroemer should have said, ``the interface is the device with a magnetic personality that continually surprises.'' [3pt] [1] Herbert Kroemer, ``Quasielectric fields and band offsets: teaching electron s new tricks,'' Nobel Lecture, December 8, 2000:

Comparative study on nitridation and oxidation plasma interface treatment for AlGaN/GaN MIS-HEMTs with AlN gate dielectric

NASA Astrophysics Data System (ADS)

Zhu, Jie-Jie; Ma, Xiao-Hua; Hou, Bin; Chen, Li-Xiang; Zhu, Qing; Hao, Yue

2017-02-01

This paper demonstrated the comparative study on interface engineering of AlN/AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) by using plasma interface pre-treatment in various ambient gases. The 15 nm AlN gate dielectric grown by plasma-enhanced atomic layer deposition significantly suppressed the gate leakage current by about two orders of magnitude and increased the peak field-effect mobility by more than 50%. NH3/N2 nitridation plasma treatment (NPT) was used to remove the 3 nm poor-quality interfacial oxide layer and N2O/N2 oxidation plasma treatment (OPT) to improve the quality of interfacial layer, both resulting in improved dielectric/barrier interface quality, positive threshold voltage (V th) shift larger than 0.9 V, and negligible dispersion. In comparison, however, NPT led to further decrease in interface charges by 3.38 × 1012 cm-2 and an extra positive V th shift of 1.3 V. Analysis with fat field-effect transistors showed that NPT resulted in better sub-threshold characteristics and transconductance linearity for MIS-HEMTs compared with OPT. The comparative study suggested that direct removing the poor interfacial oxide layer by nitridation plasma was superior to improving the quality of interfacial layer by oxidation plasma for the interface engineering of GaN-based MIS-HEMTs.

All-Graphene Planar Self-Switching MISFEDs, Metal-Insulator-Semiconductor Field-Effect Diodes

PubMed Central

Al-Dirini, Feras; Hossain, Faruque M.; Nirmalathas, Ampalavanapillai; Skafidas, Efstratios

2014-01-01

Graphene normally behaves as a semimetal because it lacks a bandgap, but when it is patterned into nanoribbons a bandgap can be introduced. By varying the width of these nanoribbons this band gap can be tuned from semiconducting to metallic. This property allows metallic and semiconducting regions within a single Graphene monolayer, which can be used in realising two-dimensional (2D) planar Metal-Insulator-Semiconductor field effect devices. Based on this concept, we present a new class of nano-scale planar devices named Graphene Self-Switching MISFEDs (Metal-Insulator-Semiconductor Field-Effect Diodes), in which Graphene is used as the metal and the semiconductor concurrently. The presented devices exhibit excellent current-voltage characteristics while occupying an ultra-small area with sub-10 nm dimensions and an ultimate thinness of a single atom. Quantum mechanical simulation results, based on the Extended Huckel method and Nonequilibrium Green's Function Formalism, show that a Graphene Self-Switching MISFED with a channel as short as 5 nm can achieve forward-to-reverse current rectification ratios exceeding 5000. PMID:24496307

Insulator charging limits direct current across tunneling metal-insulator-semiconductor junctions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vilan, Ayelet

Molecular electronics studies how the molecular nature affects the probability of charge carriers to tunnel through the molecules. Nevertheless, transport is also critically affected by the contacts to the molecules, an aspect that is often overlooked. Specifically, the limited ability of non-metallic contacts to maintain the required charge balance across the fairly insulating molecule often have dramatic effects. This paper shows that in the case of lead/organic monolayer-silicon junctions, a charge balance is responsible for an unusual current scaling, with the junction diameter (perimeter), rather than its area. This is attributed to the balance between the 2D charging at themore » metal/insulator interface and the 3D charging of the semiconductor space-charge region. A derivative method is developed to quantify transport across tunneling metal-insulator-semiconductor junctions; this enables separating the tunneling barrier from the space-charge barrier for a given current-voltage curve, without complementary measurements. The paper provides practical tools to analyze specific molecular junctions compatible with existing silicon technology, and demonstrates the importance of contacts' physics in modeling charge transport across molecular junctions.« less

Physical aspects of colossal dielectric constant material CaCu3Ti4O12 thin films

NASA Astrophysics Data System (ADS)

Deng, Guochu; He, Zhangbin; Muralt, Paul

2009-04-01

The underlying physical mechanism of the so-called colossal dielectric constant phenomenon in CaCu3Ti4O12 (CCTO) thin films were investigated by using semiconductor theories and methods. The semiconductivity of CCTO thin films originated from the acceptor defect at a level ˜90 meV higher than valence band. Two contact types, metal-semiconductor and metal-insulator-semiconductor junctions, were observed and their barrier heights, and impurity concentrations were theoretically calculated. Accordingly, the Schottky barrier height of metal-semiconductor contact is about 0.8 eV, and the diffusion barrier height of metal-insulator-semiconductor contact is about 0.4-0.7 eV. The defect concentrations of both samples are quite similar, of the magnitude of 1019 cm-3, indicating an inherent feature of high defect concentration.

Enhanced performance of ferroelectric-based all organic transistors and capacitors through choice of solvent

NASA Astrophysics Data System (ADS)

Knotts, Grant; Bhaumik, Anagh; Ghosh, Kartik; Guha, Suchismita

2014-03-01

We examine the role of solvents in the performance of pentacene devices using the ferroelectric copolymer poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFe) as a gate insulating layer. High dipole moment solvents such as dimethyl sulfoxide used to dissolve the copolymer for spin casting increase the charge carrier mobility in field-effect transistors by nearly an order of magnitude as compared to lower dipole moment solvents. The polarization in Al/PVDF-TrFe/Au metal-ferroelectric-metal devices is also investigated. An increase in remnant polarization of ~ 20% is observed in the sample using dimethyl sulfoxide as the ferroelectric solvent. Interestingly, at low applied electric fields of ~ 100 MV/m a remnant polarization is seen in the high dipole moment device that is nearly 3.5 times larger than the value observed in the lower dipole moment samples, suggesting that the degree of dipolar order is higher at low operating voltages for the high dipole moment device. Detailed analysis of the capacitance characteristics of metal-insulator-semiconductor structure is performed. The density of interface trap states is nearly an order of magnitude lower for the high dipole moment device. This work was supported by National Science Foundation under Grant No. ECCS-1305642.

Inelastic tunnel diodes

NASA Technical Reports Server (NTRS)

Anderson, L. M. (Inventor)

1984-01-01

Power is extracted from plasmons, photons, or other guided electromagnetic waves at infrared to midultraviolet frequencies by inelastic tunneling in metal-insulator-semiconductor-metal diodes. Inelastic tunneling produces power by absorbing plasmons to pump electrons to higher potential. Specifically, an electron from a semiconductor layer absorbs a plasmon and simultaneously tunnels across an insulator into metal layer which is at higher potential. The diode voltage determines the fraction of energy extracted from the plasmons; any excess is lost to heat.

Determination of the density of surface states at the semiconductor-insulator interface in a metal-insulator-semiconductor structure

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gulyamov, G., E-mail: Gulyamov1949@rambler.ru; Sharibaev, N. U.

2011-02-15

The temporal dependence of thermal generation of electrons from occupied surface states at the semiconductor-insulator interface in a metal-insulator-semiconductor structure is studied. It is established that, at low temperatures, the derivative of the probability of depopulation of occupied surface states with respect to energy is represented by the Dirac {delta} function. It is shown that the density of states of a finite number of discrete energy levels under high-temperature measurements manifests itself as a continuous spectrum, whereas this spectrum appears discrete at low temperatures. A method for processing the continuous spectrum of the density of surface states is suggested thatmore » method makes it possible to determine the discrete energy spectrum. The obtained results may be conducive to an increase in resolution of the method of non-stationary spectroscopy of surface states.« less

Low-threshold voltage ultraviolet light-emitting diodes based on (Al,Ga)N metal-insulator-semiconductor structures

NASA Astrophysics Data System (ADS)

Liang, Yu-Han; Towe, Elias

2017-12-01

Al-rich III-nitride-based deep-ultraviolet (UV) (275-320 nm) light-emitting diodes are plagued with a low emission efficiency and high turn-on voltages. We report Al-rich (Al,Ga)N metal-insulator-semiconductor UV light-emitting Schottky diodes with low turn-on voltages of <3 V, which are about half those of typical (Al,Ga)N p-i-n diodes. Our devices use a thin AlN film as the insulator and an n-type Al0.58Ga0.42N film as the semiconductor. To improve the efficiency, we inserted a GaN quantum-well structure between the AlN insulator and the n-type Al x Ga1- x N semiconductor. The benefits of the quantum-well structure include the potential to tune the emission wavelength and the capability to confine carriers for more efficient radiative recombination.

Atomic-layer-deposited Al2O3-HfO2-Al2O3 dielectrics for metal-insulator-metal capacitor applications

NASA Astrophysics Data System (ADS)

Ding, Shi-Jin; Zhu, Chunxiang; Li, Ming-Fu; Zhang, David Wei

2005-08-01

Atomic-layer-deposited Al2O3-HfO2-Al2O3 dielectrics have been investigated to replace conventional silicon oxide and nitride for radio frequency and analog metal-insulator-metal capacitors applications. In the case of 1-nm-Al2O3, sufficiently good electrical performances are achieved, including a high dielectric constant of ˜17, a small dissipation factor of 0.018 at 100kHz, an extremely low leakage current of 7.8×10-9A/cm2 at 1MV/cm and 125°C, perfect voltage coefficients of capacitance (74ppm/V2 and 10ppm/V). The quadratic voltage coefficient of capacitance decreases with the applied frequency due to the change of relaxation time with different carrier mobility in insulator, and correlates with the dielectric composition and thickness, which is of intrinsic property owing to electric field polarization. Furthermore, the conduction mechanism of the AHA dielectrics is also discussed, indicating the Schottky emission dominated at room temperature.

Anomalous high capacitance in a coaxial single nanowire capacitor.

PubMed

Liu, Zheng; Zhan, Yongjie; Shi, Gang; Moldovan, Simona; Gharbi, Mohamed; Song, Li; Ma, Lulu; Gao, Wei; Huang, Jiaqi; Vajtai, Robert; Banhart, Florian; Sharma, Pradeep; Lou, Jun; Ajayan, Pulickel M

2012-06-06

Building entire multiple-component devices on single nanowires is a promising strategy for miniaturizing electronic applications. Here we demonstrate a single nanowire capacitor with a coaxial asymmetric Cu-Cu(2)O-C structure, fabricated using a two-step chemical reaction and vapour deposition method. The capacitance measured from a single nanowire device corresponds to ~140 μF cm(-2), exceeding previous reported values for metal-insulator-metal micro-capacitors and is more than one order of magnitude higher than what is predicted by classical electrostatics. Quantum mechanical calculations indicate that this unusually high capacitance may be attributed to a negative quantum capacitance of the dielectric-metal interface, enhanced significantly at the nanoscale.

Electrical characteristics and interface properties of ALD-HfO2/AlGaN/GaN MIS-HEMTs fabricated with post-deposition annealing

NASA Astrophysics Data System (ADS)

Kubo, Toshiharu; Egawa, Takashi

2017-12-01

HfO2/AlGaN/GaN metal-insulator-semiconductor (MIS)-type high electron mobility transistors (HEMTs) on Si substrates were fabricated by atomic layer deposition of HfO2 layers and post-deposition annealing (PDA). The current-voltage characteristics of the MIS-HEMTs with as-deposited HfO2 layers showed a low gate leakage current (I g) despite the relatively low band gap of HfO2, and a dynamic threshold voltage shift (ΔV th) was observed. After PDA above 500 °C, ΔV th was reduced from 2.9 to 0.7 V with an increase in I g from 2.2 × 10-7 to 4.8 × 10-2 mA mm-1. Effects of the PDA on the HfO2 layer and the HfO2/AlGaN interface were investigated by x-ray photoelectron spectroscopy (XPS) using synchrotron radiation. XPS data showed that oxygen vacancies exist in the as-deposited HfO2 layers and they disappeared with an increase in the PDA temperature. These results indicate that the deep electron traps that cause ΔV th are related to the oxygen vacancies in the HfO2 layers.

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

Subthreshold characteristics of pentacene field-effect transistors influenced by grain boundaries

NASA Astrophysics Data System (ADS)

Park, Jaehoon; Jeong, Ye-Sul; Park, Kun-Sik; Do, Lee-Mi; Bae, Jin-Hyuk; Sun Choi, Jong; Pearson, Christopher; Petty, Michael

2012-05-01

Grain boundaries in polycrystalline pentacene films significantly affect the electrical characteristics of pentacene field-effect transistors (FETs). Upon reversal of the gate voltage sweep direction, pentacene FETs exhibited hysteretic behaviours in the subthreshold region, which was more pronounced for the FET having smaller pentacene grains. No shift in the flat-band voltage of the metal-insulator-semiconductor capacitor elucidates that the observed hysteresis was mainly caused by the influence of localized trap states existing at pentacene grain boundaries. From the results of continuous on/off switching operation of the pentacene FETs, hole depletion during the off period is found to be limited by pentacene grain boundaries. It is suggested that the polycrystalline nature of a pentacene film plays an important role on the dynamic characteristics of pentacene FETs.

Characterization of Interface State in Silicon Carbide Metal Oxide Semiconductor Capacitors

NASA Astrophysics Data System (ADS)

Kao, Wei-Chieh

Silicon carbide (SiC) has always been considered as an excellent material for high temperature and high power devices. Since SiC is the only compound semiconductor whose native oxide is silicon dioxide (SiO2), it puts SiC in a unique position. Although SiC metal oxide semiconductor (MOS) technology has made significant progress in recent years, there are still a number of issues to be overcome before more commercial SiC devices can enter the market. The prevailing issues surrounding SiC MOSFET devices are the low channel mobility, the low quality of the oxide layer and the high interface state density at the SiC/SiO2 interface. Consequently, there is a need for research to be performed in order to have a better understanding of the factors causing the poor SiC/SiO2 interface properties. In this work, we investigated the generation lifetime in SiC materials by using the pulsed metal oxide semiconductor (MOS) capacitor method and measured the interface state density distribution at the SiC/SiO2 interface by using the conductance measurement and the high-low frequency capacitance technique. These measurement techniques have been performed on n-type and p-type SiC MOS capacitors. In the course of our investigation, we observed fast interface states at semiconductor-dielectric interfaces in SiC MOS capacitors that underwent three different interface passivation processes, such states were detected in the nitrided samples but not observed in PSG-passivated samples. This result indicate that the lack of fast states at PSG-passivated interface is one of the main reasons for higher channel mobility in PSG MOSFETs. In addition, the effect of mobile ions in the oxide on the response time of interface states has been investigated. In the last chapter we propose additional methods of investigation that can help elucidate the origin of the particular interface states, enabling a more complete understanding of the SiC/SiO2 material system.

Nitride passivation reduces interfacial traps in atomic-layer-deposited Al2O3/GaAs (001) metal-oxide-semiconductor capacitors using atmospheric metal-organic chemical vapor deposition

NASA Astrophysics Data System (ADS)

Aoki, T.; Fukuhara, N.; Osada, T.; Sazawa, H.; Hata, M.; Inoue, T.

2014-07-01

Using an atmospheric metal-organic chemical vapor deposition system, we passivated GaAs with AlN prior to atomic layer deposition of Al2O3. This AlN passivation incorporated nitrogen at the Al2O3/GaAs interface, improving the capacitance-voltage (C-V) characteristics of the resultant metal-oxide-semiconductor capacitors (MOSCAPs). The C-V curves of these devices showed a remarkable reduction in the frequency dispersion of the accumulation capacitance. Using the conductance method at various temperatures, we extracted the interfacial density of states (Dit). The Dit was reduced over the entire GaAs band gap. In particular, these devices exhibited Dit around the midgap of less than 4 × 1012 cm-2eV-1, showing that AlN passivation effectively reduced interfacial traps in the MOS structure.

Silicon chip with capacitors and transistors for interfacing organotypic brain slice of rat hippocampus.

PubMed

Hutzler, Michael; Fromherz, Peter

2004-04-01

Probing projections between brain areas and their modulation by synaptic potentiation requires dense arrays of contacts for noninvasive electrical stimulation and recording. Semiconductor technology is able to provide planar arrays with high spatial resolution to be used with planar neuronal structures such as organotypic brain slices. To address basic methodical issues we developed a silicon chip with simple arrays of insulated capacitors and field-effect transistors for stimulation of neuronal activity and recording of evoked field potentials. Brain slices from rat hippocampus were cultured on that substrate. We achieved local stimulation of the CA3 region by applying defined voltage pulses to the chip capacitors. Recording of resulting local field potentials in the CA1 region was accomplished with transistors. The relationship between stimulation and recording was rationalized by a sheet conductor model. By combining a row of capacitors with a row of transistors we determined a simple stimulus-response matrix from CA3 to CA1. Possible contributions of inhomogeneities of synaptic projection, of tissue structure and of neuroelectronic interfacing were considered. The study provides the basis for a development of semiconductor chips with high spatial resolution that are required for long-term studies of topographic mapping.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moghadam, Reza M.; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to low-power field-effect devices that can be used for logic or memory. Essential to realizing such field-effect devices is the development of ferroelectric metal-oxide-semiconductor (MOS) capacitors, in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel. Here we demonstrate that ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x= 0.7) that has been epitaxially grown on Ge. We find that themore » ferroelectric properties of SrZrxTi1-xO3 are exceptionally robust, as gate layers as thin as 5 nm give rise to hysteretic capacitance-voltage characteristics that are 2 V in width. The development of ferroelectric MOS capacitors with gate thicknesses that are technologically relevant opens a pathway to realize scalable ferroelectric field-effect devices.« less

Numerical investigation of metal-semiconductor-insulator-semiconductor passivated hole contacts based on atomic layer deposited AlO x

NASA Astrophysics Data System (ADS)

Ke, Cangming; Xin, Zheng; Ling, Zhi Peng; Aberle, Armin G.; Stangl, Rolf

2017-08-01

Excellent c-Si tunnel layer surface passivation has been obtained recently in our lab, using atomic layer deposited aluminium oxide (ALD AlO x ) in the tunnel layer regime of 0.9 to 1.5 nm, investigated to be applied for contact passivation. Using the correspondingly measured interface properties, this paper compares the theoretical collection efficiency of a conventional metal-semiconductor (MS) contact on diffused p+ Si to a metal-semiconductor-insulator-semiconductor (MSIS) contact on diffused p+ Si or on undoped n-type c-Si. The influences of (1) the tunnel layer passivation quality at the tunnel oxide interface (Q f and D it), (2) the tunnel layer thickness and the electron and hole tunnelling mass, (3) the tunnel oxide material, and (4) the semiconductor capping layer material properties are investigated numerically by evaluation of solar cell efficiency, open-circuit voltage, and fill factor.

Charge-flow structures as polymeric early-warning fire alarm devices. M.S. Thesis; [metal oxide semiconductors

NASA Technical Reports Server (NTRS)

Sechen, C. M.; Senturia, S. D.

1977-01-01

The charge-flow transistor (CFT) and its applications for fire detection and gas sensing were investigated. The utility of various thin film polymers as possible sensing materials was determined. One polymer, PAPA, showed promise as a relative humidity sensor; two others, PFI and PSB, were found to be particularly suitable for fire detection. The behavior of the charge-flow capacitor, which is basically a parallel-plate capacitor with a polymer-filled gap in the metallic tip electrode, was successfully modeled as an RC transmission line. Prototype charge-flow transistors were fabricated and tested. The effective threshold voltage of this metal oxide semiconductor was found to be dependent on whether surface or bulk conduction in the thin film was dominant. Fire tests with a PFI-coated CFT indicate good sensitivity to smouldering fires.

EUO-Based Multifunctional Heterostructures

DTIC Science & Technology

2015-06-06

magnetoresistance and the metal -insulator transition resistance ratios of doped EuO by interfacing this semiconductor with niobium; the observed effect is...general and may be applied to any metal /semiconductor interface where the semiconductor shows large Zeeman splitting under magnetic field, (2...understanding the changes in electronic structure and Fermi-surface reconstruction that occur as doped EuO progresses through the ferromagnetic metal

Leakage current and charging/discharging processes in barrier-type anodic alumina thin films for use in metal-insulator-metal capacitors

NASA Astrophysics Data System (ADS)

Hourdakis, E.; Koutsoureli, M.; Papaioannou, G.; Nassiopoulou, A. G.

2018-06-01

Barrier-type anodic alumina thin films are interesting for use in high capacitance density metal-insulator-metal capacitors due to their excellent dielectric properties at small thickness. This thickness is easily controlled by the anodization voltage. In previous papers we studied the main parameters of interest of the Al/barrier-type anodic alumina/Al structure for use in RF applications and showed the great potential of barrier-type anodic alumina in this respect. In this paper, we investigated in detail charging/discharging processes and leakage current of the above dielectric material. Two different sets of metal-insulator-metal capacitors were studied, namely, with the top Al electrode being either e-gun deposited or sputtered. The dielectric constant of the barrier-type anodic alumina was found at 9.3. Low leakage current was observed in all samples studied. Furthermore, depending on the film thickness, field emission following the Fowler-Nordheim mechanism was observed above an applied electric field. Charging of the anodic dielectric was observed, occurring in the bulk of the anodic layer. The stored charge was of the order of few μC/cm2 and the calculated trap density ˜2 × 1018 states/cm3, the most probable origin of charge traps being, in our opinion, positive electrolyte ions trapped in the dielectric during anodization. We do not think that oxygen vacancies play an important role, since their existence would have a more important impact on the leakage current characteristics, such as resistive memory effects or significant changes during annealing, which were not observed. Finally, discharging characteristic times as high as 5 × 109 s were measured.

Scalable ferroelectric MOS capacitors comprised of single crystalline SrZrxTi1-xO3 on Ge.

NASA Astrophysics Data System (ADS)

Moghadam, Reza; Xiao, Z.-Y.; Ahmadi-Majlan, K.; Grimley, E.; Ong, P. V.; Lebeau, J. M.; Chambers, S. A.; Hong, X.; Sushko, P.; Ngai, J. H.

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, ferroelectric materials integrated on semiconductors could lead to field-effect devices that require very little power to operate, or that possess both logic and memory functionalities. The development of metal-oxide-semiconductor (MOS) capacitors in which the polarization of a ferroelectric gate is coupled to the surface potential of a semiconducting channel is essential in order to realize such field-effect devices. Here we demonstrate that scalable, ferroelectric MOS capacitors can be realized using single crystalline SrZrxTi1-xO3 (x = 0.7) that has been epitaxially grown on Ge. Single crystalline SrZrxTi1-xO3 exhibits characteristics that are ideal for a ferroelectric gate material, namely, a type-I band offset with respect to Ge, large coercive fields and polarization that can be enhanced with electric field. The latter characteristic stems from the relaxor nature of SrZrxTi1-xO3. These properties enable MOS capacitors with 5 nm thick SrZrxTi1-xO3 layers to exhibit a nearly 2 V wide hysteretic window in the capacitance-voltage characteristics. The realization of ferroelectric MOS capacitors with technologically relevant gate thicknesses opens the pathway to practical field effect devices. NSF DMR 1508530.

High power density capacitor and method of fabrication

DOEpatents

Tuncer, Enis

2012-11-20

A ductile preform for making a drawn capacitor includes a plurality of electrically insulating, ductile insulator plates and a plurality of electrically conductive, ductile capacitor plates. Each insulator plate is stacked vertically on a respective capacitor plate and each capacitor plate is stacked on a corresponding insulator plate in alignment with only one edge so that other edges are not in alignment and so that each insulator plate extends beyond the other edges. One or more electrically insulating, ductile spacers are disposed in horizontal alignment with each capacitor plate along the other edges and the pattern is repeated so that alternating capacitor plates are stacked on alternating opposite edges of the insulator plates. A final insulator plate is positioned at an extremity of the preform. The preform may then be drawn to fuse the components and decrease the dimensions of the preform that are perpendicular to the direction of the draw.

A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires

NASA Astrophysics Data System (ADS)

Saranti, Konstantina; Alotaibi, Sultan; Paul, Shashi

2016-06-01

The work described in this paper focuses on the utilisation of silicon nanowires as the information storage element in flash-type memory devices. Silicon nanostructures have attracted attention due to interesting electrical and optical properties, and their potential integration into electronic devices. A detailed investigation of the suitability of silicon nanowires as the charge storage medium in two-terminal non-volatile memory devices are presented in this report. The deposition of the silicon nanostructures was carried out at low temperatures (less than 400 °C) using a previously developed a novel method within our research group. Two-terminal non-volatile (2TNV) memory devices and metal-insulator-semiconductor (MIS) structures containing the silicon nanowires were fabricated and an in-depth study of their characteristics was carried out using current-voltage and capacitance techniques.

Hydrogen gas sensors using a thin Ta2O5 dielectric film

NASA Astrophysics Data System (ADS)

Kim, Seongjeen

2014-12-01

A capacitive-type hydrogen gas sensor with a MIS (metal-insulator-semiconductor) structure was investigated for high-temperature applications. In this work, a tantalum oxide (Ta2O5) layer of tens of nanometers in thickness formed by oxidizing tantalum film in rapid thermal processing (RTP) was exploited with the purpose of sensitivity improvement. Silicon carbide (SiC), which is good even at high temperatures over 500 °C, was used as the substrate. We fabricated sensors composed of Pd/Ta2O5/SiC, and the dependences of the capacitance response properties and the I-V characteristics on the hydrogen concentration were analyzed from the temperature range of room temperature to 500 °C. As a result, our hydrogen sensor showed promising performance with respect to the sensitivity and the adaptability at high temperature.

Silicon Carbide-Based Hydrogen Gas Sensors for High-Temperature Applications

PubMed Central

Kim, Seongjeen; Choi, Jehoon; Jung, Minsoo; Joo, Sungjae; Kim, Sangchoel

2013-01-01

We investigated SiC-based hydrogen gas sensors with metal-insulator-semiconductor (MIS) structure for high temperature process monitoring and leak detection applications in fields such as the automotive, chemical and petroleum industries. In this work, a thin tantalum oxide (Ta2O5) layer was exploited with the purpose of sensitivity improvement, because tantalum oxide has good stability at high temperature with high permeability for hydrogen gas. Silicon carbide (SiC) was used as a substrate for high-temperature applications. We fabricated Pd/Ta2O5/SiC-based hydrogen gas sensors, and the dependence of their I-V characteristics and capacitance response properties on hydrogen concentrations were analyzed in the temperature range from room temperature to 500 °C. According to the results, our sensor shows promising performance for hydrogen gas detection at high temperatures. PMID:24113685

Silicon carbide-based hydrogen gas sensors for high-temperature applications.

PubMed

Kim, Seongjeen; Choi, Jehoon; Jung, Minsoo; Joo, Sungjae; Kim, Sangchoel

2013-10-09

We investigated SiC-based hydrogen gas sensors with metal-insulator-semiconductor (MIS) structure for high temperature process monitoring and leak detection applications in fields such as the automotive, chemical and petroleum industries. In this work, a thin tantalum oxide (Ta2O5) layer was exploited with the purpose of sensitivity improvement, because tantalum oxide has good stability at high temperature with high permeability for hydrogen gas. Silicon carbide (SiC) was used as a substrate for high-temperature applications. We fabricated Pd/Ta2O5/SiC-based hydrogen gas sensors, and the dependence of their I-V characteristics and capacitance response properties on hydrogen concentrations were analyzed in the temperature range from room temperature to 500 °C. According to the results, our sensor shows promising performance for hydrogen gas detection at high temperatures.

Oxide Structure Dependence of SiO2/SiOx/3C-SiC/n-Type Si Nonvolatile Resistive Memory on Memory Operation Characteristics

NASA Astrophysics Data System (ADS)

Yamaguchi, Yuichiro; Shouji, Masatsugu; Suda, Yoshiyuki

2012-11-01

We have investigated the dependence of the oxide layer structure of our previously proposed metal/SiO2/SiOx/3C-SiC/n-Si/metal metal-insulator-semiconductor (MIS) resistive memory device on the memory operation characteristics. The current-voltage (I-V) measurement and X-ray photoemission spectroscopy results suggest that SiOx defect states mainly caused by the oxidation of 3C-SiC at temperatures below 1000 °C are related to the hysteresis memory behavior in the I-V curve. By restricting the SiOx interface region, the number of switching cycles and the on/off current ratio are more enhanced. Compared with a memory device formed by one-step or two-step oxidation of 3C-SiC, a memory device formed by one-step oxidation of Si/3C-SiC exhibits a more restrictive SiOx interface with a more definitive SiO2 layer and higher memory performances for both the endurance switching cycle and on/off current ratio.

Effect of sulfur passivation on the InP surface prior to plasma-enhanced chemical vapor deposition of SiNx

NASA Astrophysics Data System (ADS)

Tang, Hengjing; Wu, Xiaoli; Xu, Qinfei; Liu, Hongyang; Zhang, Kefeng; Wang, Yang; He, Xiangrong; Li, Xue; Gong, Hai Mei

2008-03-01

The fabrication of Au/SiNx/InP metal-insulator-semiconductor (MIS) diodes has been achieved by depositing a layer of SiNx on the (NH4)2Sx-treated n-InP. The SiNx layer was deposited at 200 °C using plasma-enhanced chemical vapor deposition (PECVD). The effect of passivation on the InP surface before and after annealing was evaluated by current-voltage (I-V) and capacitance-voltage (C-V) measurements, and Auger electron spectroscopy (AES) analysis was used to investigate the depth profiles of several atoms. The results indicate that the SiNx passivation layer exhibits good insulative characteristics. The annealing process causes distinct inter-diffusion in the SiNx/InP interface and contributes to the decrease of the fixed charge density and minimum interface state density, which are 1.96 × 1012 cm-2 and 7.41 × 1011 cm-2 eV-1, respectively. A 256 × 1 InP/InGaAs/InP heterojunction photodiode, fabricated with sulfidation and SiNx passivation layer, has good response uniformity.

Design and characterization of a single channel two-liquid capacitor and its application to hyperelastic strain sensing.

PubMed

Liu, Shanliangzi; Sun, Xiaoda; Hildreth, Owen J; Rykaczewski, Konrad

2015-03-07

Room temperature liquid-metal microfluidic devices are attractive systems for hyperelastic strain sensing. These liquid-phase electronics are intrinsically soft and retain their functionality even when stretched to several times their original length. Currently two types of liquid metal-based strain sensors exist for in-plane measurements: single-microchannel resistive and two-microchannel capacitive devices. With a winding serpentine channel geometry, these sensors typically have a footprint of about a square centimeter. This large footprint of an individual device limits the number of sensors that can be embedded into, for example, electronic fabric or skin. In this work we introduce an alternative capacitor design consisting of two liquid metal electrodes separated by a liquid dielectric material within a single straight channel. Using a liquid insulator instead of a solid elastomer enables us to tailor the system's capacitance by selecting high or low dielectric constant liquids. We quantify the effects of the electrode geometry including the diameter, spacing, and meniscus shape as well as the dielectric constant of the insulating liquid on the overall system's capacitance. We also develop a procedure for fabricating the two-liquid capacitor within a single straight polydiemethylsiloxane channel and demonstrate that this device can have about 25 times higher capacitance per sensor's base area when compared to two-channel liquid metal capacitors. Lastly, we characterize the response of this compact device to strain and identify operational issues arising from complex hydrodynamics near liquid-liquid and liquid-elastomer interfaces.

Thermally tunable VO2-SiO2 nanocomposite thin-film capacitors

NASA Astrophysics Data System (ADS)

Sun, Yifei; Narayanachari, K. V. L. V.; Wan, Chenghao; Sun, Xing; Wang, Haiyan; Cooley, Kayla A.; Mohney, Suzanne E.; White, Doug; Duwel, Amy; Kats, Mikhail A.; Ramanathan, Shriram

2018-03-01

We present a study of co-sputtered VO2-SiO2 nanocomposite dielectric thin-film media possessing continuous temperature tunability of the dielectric constant. The smooth thermal tunability is a result of the insulator-metal transition in the VO2 inclusions dispersed within an insulating matrix. We present a detailed comparison of the dielectric characteristics of this nanocomposite with those of a VO2 control layer and of VO2/SiO2 laminate multilayers of comparable overall thickness. We demonstrated a nanocomposite capacitor that has a thermal capacitance tunability of ˜60% between 25 °C and 100 °C at 1 MHz, with low leakage current. Such thermally tunable capacitors could find potential use in applications such as sensing, thermal cloaks, and phase-change energy storage devices.

The effect of processing conditions on the GaAs/plasma-grown insulator interface

NASA Technical Reports Server (NTRS)

Hshieh, F. I.; Borrego, J. M.; Ghandhi, S. K.

1986-01-01

The effect of processing conditions on the interface state density was evaluated from C-V measurements on metal-oxide-semiconductor capacitors. The optimum processing conditions for the minimum surface state density was found to be related to the postoxidation annealing temperature and time, and was independent of chemical treatments prior to oxidation. Annealing at the optimum condition (i.e., at 350 C for 1 h in either nitrogen or hydrogen gas, with or without an aluminum pattern on the oxide) reduces the fast surface state density by about one order of magnitude. By using a nitrogen/oxygen plasma, the static dielectric constant of the oxide decreased as the N/O ratio was increased, and nitrogen was incorporated into the oxide. In addition, the fast surface state density was reduced as a result of this nitridation process.

Improved reliability from a plasma-assisted metal-insulator-metal capacitor comprising a high-k HfO2 film on a flexible polyimide substrate.

PubMed

Meena, Jagan Singh; Chu, Min-Ching; Kuo, Shiao-Wei; Chang, Feng-Chih; Ko, Fu-Hsiang

2010-03-20

We have used a sol-gel spin-coating process to fabricate a new metal-insulator-metal (MIM) capacitor comprising a 10 nm-thick high-k thin dielectric HfO(2) film on a flexible polyimide (PI) substrate. The surface morphology of this HfO(2) film was investigated using atomic force microscopy and scanning electron microscopy, which confirmed that continuous and crack-free film growth had occurred on the film surface. After oxygen (O(2)) plasma pretreatment and subsequent annealing at 250 degrees C, the film on the PI substrate exhibited a low leakage current density of 3.64 x 10(-9) A cm(-2) at 5 V and a maximum capacitance density of 10.35 fF microm(-2) at 1 MHz. The as-deposited sol-gel film was completely oxidized when employing O(2) plasma at a relatively low temperature (ca. 250 degrees C), thereby enhancing the electrical performance. We employed X-ray photoelectron spectroscopy (XPS) at both high and low resolution to examine the chemical composition of the film subjected to various treatment conditions. The shift of the XPS peaks towards higher binding energy, revealed that O(2) plasma treatment was the most effective process for the complete oxidation of hafnium atoms at low temperature. A study of the insulator properties indicated the excellent bendability of our MIM capacitor; the flexible PI substrate could be bent up to 10(5) times and folded to near 360 degrees without any deterioration in its electrical performance.

Processing of insulators and semiconductors

DOEpatents

Quick, Nathaniel R.; Joshi, Pooran C.; Duty, Chad Edward; Jellison, Jr., Gerald Earle; Angelini, Joseph Attilio

2015-06-16

A method is disclosed for processing an insulator material or a semiconductor material. The method includes pulsing a plasma lamp onto the material to diffuse a doping substance into the material, to activate the doping substance in the material or to metallize a large area region of the material. The method may further include pulsing a laser onto a selected region of the material to diffuse a doping substance into the material, to activate the doping substance in the material or to metallize a selected region of the material.

Enhanced adhesion of films to semiconductors or metals by high energy bombardment

NASA Technical Reports Server (NTRS)

Tombrello, Thomas A. (Inventor); Qiu, Yuanxun (Inventor); Mendenhall, Marcus H. (Inventor)

1985-01-01

Films (12) of a metal such as gold or other non-insulator materials are firmly bonded to other non-insulators such as semiconductor substrates (10), suitably silicon or gallium arsenide by irradiating the interface with high energy ions. The process results in improved adhesion without excessive doping and provides a low resistance contact to the semiconductor. Thick layers can be bonded by depositing or doping the interfacial surfaces with fissionable elements or alpha emitters. The process can be utilized to apply very small, low resistance electrodes (78) to light-emitting solid state laser diodes (60) to form a laser device 70.

Fabrication and evaluation of dispersed-Ag nanoparticles-in-polyimide thin films

NASA Astrophysics Data System (ADS)

Sonehara, Makoto; Watanabe, Yuki; Yamaguchi, Sota; Kato, Takanori; Yoshisaku, Yasuaki; Sato, Toshiro; Itoh, Eiji

2017-10-01

A thin-film common-mode filter (TF-CMF) for cell phones in the UHF band was fabricated and evaluated. The TF-CMF consisted of multiple metal-insulator-metal (MIM) capacitors and inductors. The sizes of the 0.70-1.0 GHz band-type and 1.8-2.0 GHz band-type TF-CMFs are 1,140 × 1,260 × 10.5 µm3, and 1,060 × 1,060 × 10.5 µm3, respectively. The footprint in both types of TF-CMFs is over 1 mm2. In order to miniaturize the TF-CMF, we proposed to change a polyimide-only to a polyimide with dispersed Ag nanoparticles with high permittivity in the insulator layer for the MIM capacitor of the TF-CMF. A polyimide (\\text{polyimide precursor}:\\text{toluene with dispersed Ag nanoparticles} = 100:1) thin film with dispersed high-density Ag nanoparticles has a relative permittivity of about 8, which is twice as high as that of the polyimide-only thin film. If the capacitance and distance between electrodes are the same, then the capacitor footprint may be halved.

Physicochemical assessment criteria for high-voltage pulse capacitors

NASA Astrophysics Data System (ADS)

Darian, L. A.; Lam, L. Kh.

2016-12-01

In the paper, the applicability of decomposition products of internal insulation of high-voltage pulse capacitors is considered (aging is the reason for decomposition products of internal insulation). Decomposition products of internal insulation of high-voltage pulse capacitors can be used to evaluate their quality when in operation and in service. There have been three generations of markers of aging of insulation as in the case with power transformers. The area of applicability of markers of aging of insulation for power transformers has been studied and the area can be extended to high-voltage pulse capacitors. The research reveals that there is a correlation between the components and quantities of markers of aging of the first generation (gaseous decomposition products of insulation) dissolved in insulating liquid and the remaining life of high-voltage pulse capacitors. The application of markers of aging to evaluate the remaining service life of high-voltage pulse capacitor is a promising direction of research, because the design of high-voltage pulse capacitors keeps stability of markers of aging of insulation in high-voltage pulse capacitors. It is necessary to continue gathering statistical data concerning development of markers of aging of the first generation. One should also carry out research aimed at estimation of the remaining life of capacitors using markers of the second and the third generation.

Phase modulation in horizontal metal-insulator-silicon-insulator-metal plasmonic waveguides.

PubMed

Zhu, Shiyang; Lo, G Q; Kwong, D L

2013-04-08

An extremely compact Si phase modulator is proposed and validated, which relies on effective modulation of the real part of modal index of horizontal metal-insulator-Si-insulator-metal plasmonic waveguides by a voltage applied between the metal cover and the Si core. Proof-of-concept devices are fabricated on silicon-on-insulator substrates using standard complementary metal-oxide-semiconductor technology using copper as the metal and thermal silicon dioxide as the insulator. A modulator with a 1-μm-long phase shifter inserted in an asymmetric Si Mach-Zehnder interferometer exhibits 9-dB extinction ratio under a 6-V/10-kHz voltage swing. Numerical simulations suggest that high speed and low driving voltage could be achieved by shortening the distance between the Si core and the n(+)-contact and by using a high-κ dielectric as the insulator, respectively.

Electrical characterization and modelization of CaCu3Ti4O12 polycrystalline ceramics

NASA Astrophysics Data System (ADS)

Cheballah, Chafe; Valdez-Nava, Zarel; Laudebat, Lionel; Guillemet-Fritsch, Sophie; Lebey, Thierry

2015-06-01

Since the observation almost 15 years ago of the so-called "colossal" dielectric permittivity behavior in CaCu3Ti4O12 (CCTO) ceramics, several works have been undertaken to understand its physical origin interfacial polarization being the most likelihood. In this paper, (C-V) measurements, commonly used on semiconducting materials have been used to characterize CCTO samples. Their results may be described by a head-to-tail double metal-insulating-semiconductor (MIS) structure. A comparison between experimental and numerical simulation results of such a structure shows a good agreement, whatever the frequency range. Furthermore, this model explains the non-symmetrical behavior of the electrical response of this material, a property still not taken into account by today's commonly known models. Contribution to the topical issue "Electrical Engineering Symposium (SGE 2014) - Elected submissions", edited by Adel Razek

Noncontact Measurement of Doping Profile for Bare Silicon

NASA Astrophysics Data System (ADS)

Kohno, Motohiro; Matsubara, Hideaki; Okada, Hiroshi; Hirae, Sadao; Sakai, Takamasa

1998-10-01

In this study, we evaluate the doping concentrations of bare silicon wafers by noncontact capacitance voltage (C V) measurements. The metal-air-insulator-semiconductor (MAIS) method enables the measurement of C V characteristics of silicon wafers without oxidation and electrode preparation. This method has the advantage that a doping profile close to the wafer surface can be obtained. In our experiment, epitaxial silicon wafers were used to compare the MAIS method with the conventional MIS method. The experimental results obtained from the two methods showed good agreement. Then, doping profiles of boron-doped Czochralski (CZ) wafers were measured by the MAIS method. The result indicated a significant reduction of the doping concentration near the wafer surface. This observation is attributed to the well-known deactivation of boron with atomic hydrogen which permeated the silicon bulk during the polishing process. This deactivation was recovered by annealing in air at 180°C for 120 min.

Annealing effects on capacitance-voltage characteristics of a-Si/SiN(x) multilayer prepared using hot-wire chemical vapour deposition.

PubMed

Panchal, A K; Rai, D K; Solanki, C S

2011-04-01

Post-deposition annealing of a-Si/SiN(x) multilayer films at different temperature shows varying shift in high frequency (1 MHz) capacitance-voltage (HFCV) characteristics. Various a-Si/SiN(x) multilayer films were deposited using hot wire chemical vapor deposition (HWCVD) and annealed in the temperature range of 800 to 900 degrees C to precipitate Si quantum dots (Si-QD) in a-Si layers. HFCV measurements of the as-deposited and annealed films in metal-insulator-semiconductor (MIS) structures show hysterisis in C-V curves. The hysteresis in the as-deposited films and annealed films is attributed to charge trapping in Si-dangling bonds in a-Si layer and in Si-QD respectively. The charge trapping density in Si-QD increases with temperature while the interface defects density (D(it)) remains constant.

Ferroelectric switching of poly(vinylidene difluoride-trifluoroethylene) in metal-ferroelectric-semiconductor non-volatile memories with an amorphous oxide semiconductor

NASA Astrophysics Data System (ADS)

Gelinck, G. H.; van Breemen, A. J. J. M.; Cobb, B.

2015-03-01

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Current-induced switching in a magnetic insulator

NASA Astrophysics Data System (ADS)

Avci, Can Onur; Quindeau, Andy; Pai, Chi-Feng; Mann, Maxwell; Caretta, Lucas; Tang, Astera S.; Onbasli, Mehmet C.; Ross, Caroline A.; Beach, Geoffrey S. D.

2017-03-01

The spin Hall effect in heavy metals converts charge current into pure spin current, which can be injected into an adjacent ferromagnet to exert a torque. This spin-orbit torque (SOT) has been widely used to manipulate the magnetization in metallic ferromagnets. In the case of magnetic insulators (MIs), although charge currents cannot flow, spin currents can propagate, but current-induced control of the magnetization in a MI has so far remained elusive. Here we demonstrate spin-current-induced switching of a perpendicularly magnetized thulium iron garnet film driven by charge current in a Pt overlayer. We estimate a relatively large spin-mixing conductance and damping-like SOT through spin Hall magnetoresistance and harmonic Hall measurements, respectively, indicating considerable spin transparency at the Pt/MI interface. We show that spin currents injected across this interface lead to deterministic magnetization reversal at low current densities, paving the road towards ultralow-dissipation spintronic devices based on MIs.

Electric-field driven insulator-metal transition and tunable magnetoresistance in ZnO thin film

NASA Astrophysics Data System (ADS)

Zhang, Le; Chen, Shanshan; Chen, Xiangyang; Ye, Zhizhen; Zhu, Liping

2018-04-01

Electrical control of the multistate phase in semiconductors offers the promise of nonvolatile functionality in the future semiconductor spintronics. Here, by applying an external electric field, we have observed a gate-induced insulator-metal transition (MIT) with the temperature dependence of resistivity in ZnO thin films. Due to a high-density carrier accumulation, we have shown the ability to inverse change magnetoresistance in ZnO by ionic liquid gating from 10% to -2.5%. The evolution of photoluminescence under gate voltage was also consistent with the MIT, which is due to the reduction of dislocation. Our in-situ gate-controlled photoluminescence, insulator-metal transition, and the conversion of magnetoresistance open up opportunities in searching for quantum materials and ZnO based photoelectric devices.

Theoretical and experimental investigations of superconductivity. Amorphous semiconductors, superconductivity and magnetism

NASA Technical Reports Server (NTRS)

Cohen, M. H.

1973-01-01

The research activities from 1 March 1963 to 28 February 1973 are summarized. Major lectures are listed along with publications on superconductivity, superfluidity, electronic structures and Fermi surfaces of metals, optical spectra of solids, electronic structure of insulators and semiconductors, theory of magnetic metals, physics of surfaces, structures of metals, and molecular physics.

Physicochemical assessment criteria for high-voltage pulse capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Darian, L. A., E-mail: LDarian@rambler.ru; Lam, L. Kh.

In the paper, the applicability of decomposition products of internal insulation of high-voltage pulse capacitors is considered (aging is the reason for decomposition products of internal insulation). Decomposition products of internal insulation of high-voltage pulse capacitors can be used to evaluate their quality when in operation and in service. There have been three generations of markers of aging of insulation as in the case with power transformers. The area of applicability of markers of aging of insulation for power transformers has been studied and the area can be extended to high-voltage pulse capacitors. The research reveals that there is amore » correlation between the components and quantities of markers of aging of the first generation (gaseous decomposition products of insulation) dissolved in insulating liquid and the remaining life of high-voltage pulse capacitors. The application of markers of aging to evaluate the remaining service life of high-voltage pulse capacitor is a promising direction of research, because the design of high-voltage pulse capacitors keeps stability of markers of aging of insulation in high-voltage pulse capacitors. It is necessary to continue gathering statistical data concerning development of markers of aging of the first generation. One should also carry out research aimed at estimation of the remaining life of capacitors using markers of the second and the third generation.« less

The Significance of Breakdown Voltages for Quality Assurance of Low-Voltage BME Ceramic Capacitors

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander A.

2014-01-01

Application of thin dielectric, base metal electrode (BME) ceramic capacitors for high-reliability applications requires development of testing procedures that can assure high quality and reliability of the parts. In this work, distributions of breakdown voltages (VBR) in variety of low-voltage BME multilayer ceramic capacitors (MLCCs) have been measured and analyzed. It has been shown that analysis of the distributions can indicate the proportion of defective parts in the lot and significance of the defects. Variations of the distributions after solder dip testing allow for an assessment of the robustness of capacitors to soldering-related stresses. The drawbacks of the existing screening and qualification methods to reveal defects in high-value, low-voltage MLCCs and the importance of VBR measurements are discussed. Analysis has shown that due to a larger concentration of oxygen vacancies, defect-related degradation of the insulation resistance (IR) and failures are more likely in BME compared to the precious metal electrode (PME) capacitors.

Fabrication of PVDF-TrFE based bilayered PbTiO3/PVDF-TrFE films capacitor

NASA Astrophysics Data System (ADS)

Nurbaya, Z.; Wahid, M. H.; Rozana, M. D.; Annuar, I.; Alrokayan, S. A. H.; Khan, H. A.; Rusop, M.

2016-07-01

Development of high performance capacitor is reaching towards new generation where the ferroelectric materials take places as the active dielectric layer. The motivation of this study is to produce high capacitance device with long life cycle. This was configured by preparing bilayered films where lead titanate as an active dielectric layer and stacked with the top dielectric layer, poly(vinyledenefluoride-trifluoroethylene). Both of them are being referred that have one in common which is ferroelectric behavior. Therefore the combination of ceramic and polymer ferroelectric material could perform optimum dielectric characteristic for capacitor applications. The fabrication was done by simple sol-gel spin coating method that being varied at spinning speed property for polymer layers, whereas maintaining the ceramic layer. The characterization of PVDF-TrFE/PbTiO3 was performed according to metal-insulator-metal stacked capacitor measurement which includes structural, dielectric, and ferroelectric measurement.

Fabrication and Testing of Polyvinylidene Fluoride Capacitors

NASA Technical Reports Server (NTRS)

Buritz, R. S.

1980-01-01

High energy density capacitors made from metallized polyvinylidene fluoride film were built and tested. Terminations of aluminum-babbitt, tin-babbitt, and all-babbitt were evaluated. All-babbit terminations appeared to be better. The 0.1 microfarad and 2 microfarad capacitors were made of 6 micrometer material. Capacitance, dissipation factor, and insulation resistance measurements were made over the ranges -55 C to 125 C and 10 Hz to 100 kHz. Twelve of forty-one 0.1 microfarad capacitors survived a 5000 hour dc plus ac life test. Under the same conditions, the 2 microfarad capacitors exhibited overheating because of excessive power loss. Some failures occurred after low temperature exposures for 48 hours. No failures were caused by vibration or temperature cycling.

Measurement of Ferroelectric Films in MFM and MFIS Structures

NASA Astrophysics Data System (ADS)

Anderson, Jackson D.

For many years ferroelectric memory has been used in applications requiring low power, yet mainstream adoption has been stifled due to integration and scaling issues. With the renewed interest in these devices due to the recent discovery of ferroelectricity in HfO2, it is imperative that the properties of these films are well understood. To aid that end, a ferroelectric analysis package has been developed and released on GitHub and PyPI under a creative commons non-commercial share-alike license. This package contains functions for visualization and analysis of data from polarization, leakage current, and FORC measurements as well as basic modeling capability. Functionality is verified via the analysis of lead zirconate titanate (PZT) capacitors, where a multi-domain simulation based on an experimental Preisach density shows decent agreement despite measurement noise. The package is then used in the analysis of ferroelectric HfO2 films deposited in metal-ferroelectric-metal (MFM) and metal-ferroelectric-insulator-semiconductor (MFIS) stacks. 13.5 nm HfO2 films deposited on a semiconductor surface are shown to have a coercive voltage of 2.5 V, rather than the 1.9 V of the film in an MFM stack. This value further increases to 3-5 V when a lightly doped semiconductor depletion and inversion capacitance is added to the stack. The magnitude of this change is more than can be accounted for from the 10% voltage drop across the interfacial oxide layer, indicating that the modified surface properties are impacting the formation of the ferroelectric phase during anneal. In light of this, care should be taken to map out ferroelectric HfO2 properties using the particular physical stack that will be used, rather than using an MFM stack as a proxy.

Electrical characterization of MIM capacitor comprises an adamantane film at room temperature

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tiwari, Rajanish N., E-mail: rajanisht@gmail.com; Toyota Technological Institute, 2-12-1Hisakata, Tempaku-Ku, Nagoya 468-8511; Yoshimura, Masamichi

2016-06-15

We fabricated a new metal-insulator-metal capacitor at room temperature, comprising a ∼90 nm thin low–k adamantane film on a Si substrate. The surface morphology of deposited organic film was investigated by using scanning electron microscopy and Raman spectroscopy, which is confirmed that the adamantane thin film was uniformly distributed on the Si surface. The adamantane film exhibits a low leakage current density of 7.4 x 10{sup −7} A/cm{sup 2} at 13.5 V, better capacitance density of 2.14 fF/μm{sup 2} at 100 KHz.

Fabrication of lateral electrodes on semiconductor nanowires through structurally matched insulation for functional optoelectronics.

PubMed

Sheng, Yun; Sun, Huabin; Wang, Jianyu; Gao, Fan; Wang, Junzhuan; Pan, Lijia; Pu, Lin; Zheng, Youdou; Shi, Yi

2013-01-18

A strategy of using structurally matched alumina insulation to produce lateral electrodes on semiconductor nanowires is presented. Nanowires in the architecture are structurally matched with alumina insulation using selective anodic oxidation. Lateral electrodes are fabricated by directly evaporating metallic atoms onto the opposite sides of the nanowires. The integrated architecture with lateral electrodes propels carriers to transport them across nanowires and is crucially beneficial to the injection/extraction in optoelectronics. The matched architecture and the insulating properties of the alumina layer are investigated experimentally. ZnO nanowires are functionalized into an ultraviolet photodiode as an example. The present strategy successfully implements an advantageous architecture and is significant in developing diverse semiconductor nanowires in optoelectronic applications.

Nitride passivation reduces interfacial traps in atomic-layer-deposited Al{sub 2}O{sub 3}/GaAs (001) metal-oxide-semiconductor capacitors using atmospheric metal-organic chemical vapor deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Aoki, T., E-mail: aokit@sc.sumitomo-chem.co.jp; Fukuhara, N.; Osada, T.

2014-07-21

Using an atmospheric metal-organic chemical vapor deposition system, we passivated GaAs with AlN prior to atomic layer deposition of Al{sub 2}O{sub 3}. This AlN passivation incorporated nitrogen at the Al{sub 2}O{sub 3}/GaAs interface, improving the capacitance-voltage (C–V) characteristics of the resultant metal-oxide-semiconductor capacitors (MOSCAPs). The C–V curves of these devices showed a remarkable reduction in the frequency dispersion of the accumulation capacitance. Using the conductance method at various temperatures, we extracted the interfacial density of states (D{sub it}). The D{sub it} was reduced over the entire GaAs band gap. In particular, these devices exhibited D{sub it} around the midgap ofmore » less than 4 × 10{sup 12} cm{sup −2}eV{sup −1}, showing that AlN passivation effectively reduced interfacial traps in the MOS structure.« less

Temperature-dependent degradation mechanisms of threshold voltage in La2O3-gated n-channel metal-oxide-semiconductor field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Ming-Tsong; Hsu, De-Cheng; Juan, Pi-Chun; Wang, Y. L.; Lee, Joseph Ya-min

2010-09-01

Metal-oxide-semiconductor capacitors and n-channel metal-oxide-semiconductor field-effect transistors with La2O3 gate dielectric were fabricated. The positive bias temperature instability was studied. The degradation of threshold voltage (ΔVT) showed an exponential dependence on the stress time in the temperature range from 25 to 75 °C. The degradation of subthreshold slope (ΔS) and gate leakage (IG) with stress voltage was also measured. The degradation of VT is attributed to the oxide trap charges Qot. The extracted activation energy of 0.2 eV is related to a degradation dominated by the release of atomic hydrogen in La2O3 thin films.

Formation of atomically ordered and chemically selective Si-O-Ti monolayer on Si0.5Ge0.5(110) for a MIS structure via H2O2(g) functionalization.

PubMed

Park, Sang Wook; Choi, Jong Youn; Siddiqui, Shariq; Sahu, Bhagawan; Galatage, Rohit; Yoshida, Naomi; Kachian, Jessica; Kummel, Andrew C

2017-02-07

Si 0.5 Ge 0.5 (110) surfaces were passivated and functionalized using atomic H, hydrogen peroxide (H 2 O 2 ), and either tetrakis(dimethylamino)titanium (TDMAT) or titanium tetrachloride (TiCl 4 ) and studied in situ with multiple spectroscopic techniques. To passivate the dangling bonds, atomic H and H 2 O 2 (g) were utilized and scanning tunneling spectroscopy (STS) demonstrated unpinning of the surface Fermi level. The H 2 O 2 (g) could also be used to functionalize the surface for metal atomic layer deposition. After subsequent TDMAT or TiCl 4 dosing followed by a post-deposition annealing, scanning tunneling microscopy demonstrated that a thermally stable and well-ordered monolayer of TiO x was deposited on Si 0.5 Ge 0.5 (110), and X-ray photoelectron spectroscopy verified that the interfaces only contained Si-O-Ti bonds and a complete absence of GeO x . STS measurements confirmed a TiO x monolayer without mid-gap and conduction band edge states, which should be an ideal ultrathin insulating layer in a metal-insulator-semiconductor structure. Regardless of the Ti precursors, the final Ti density and electronic structure were identical since the Ti bonding is limited by the high coordination of Ti to O.

Comparative studies of Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors with HfSiON dielectric and TaN metal gate

NASA Astrophysics Data System (ADS)

Hu, Ai-Bin; Xu, Qiu-Xia

2010-05-01

Ge and Si p-channel metal-oxide-semiconductor field-effect-transistors (p-MOSFETs) with hafnium silicon oxynitride (HfSiON) gate dielectric and tantalum nitride (TaN) metal gate are fabricated. Self-isolated ring-type transistor structures with two masks are employed. W/TaN metal stacks are used as gate electrode and shadow masks of source/drain implantation separately. Capacitance-voltage curve hysteresis of Ge metal-oxide-semiconductor (MOS) capacitors may be caused by charge trapping centres in GeO2 (1 < x < 2). Effective hole mobilities of Ge and Si transistors are extracted by using a channel conductance method. The peak hole mobilities of Si and Ge transistors are 33.4 cm2/(V · s) and 81.0 cm2/(V · s), respectively. Ge transistor has a hole mobility 2.4 times higher than that of Si control sample.

Multimodal Responses of Self-Organized Circuitry in Electronically Phase Separated Materials

DOE PAGES

Herklotz, Andreas; Guo, Hangwen; Wong, Anthony T.; ...

2016-07-13

When confining an electronically phase we separated manganite film to the scale of its coexisting self-organized metallic and these insulating domains allows resistor-capacitor circuit-like responses while providing both electroresistive and magnetoresistive switching functionality.

Electrical hysteresis in p-GaN metal-oxide-semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

NASA Astrophysics Data System (ADS)

Zhang, Kexiong; Liao, Meiyong; Imura, Masataka; Nabatame, Toshihide; Ohi, Akihiko; Sumiya, Masatomo; Koide, Yasuo; Sang, Liwen

2016-12-01

The electrical hysteresis in current-voltage (I-V) and capacitance-voltage characteristics was observed in an atomic-layer-deposited Al2O3/p-GaN metal-oxide-semiconductor capacitor (PMOSCAP). The absolute minimum leakage currents of the PMOSCAP for forward and backward I-V scans occurred not at 0 V but at -4.4 and +4.4 V, respectively. A negative flat-band voltage shift of 5.5 V was acquired with a capacitance step from +4.4 to +6.1 V during the forward scan. Mg surface accumulation on p-GaN was demonstrated to induce an Mg-Ga-Al-O oxidized layer with a trap density on the order of 1013 cm-2. The electrical hysteresis is attributed to the hole trapping and detrapping process in the traps of the Mg-Ga-Al-O layer via the Poole-Frenkel mechanism.

Low-temperature electron cyclotron resonance plasma-enhanced chemical-vapor deposition silicon dioxide as gate insulator for polycrystalline silicon thin-film transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Maiolo, L.; Pecora, A.; Fortunato, G.

2006-03-15

Silicon dioxide films have been deposited at temperatures below 270 deg. C in an electron cyclotron resonance (ECR) plasma reactor from O{sub 2}, SiH{sub 4}, and He gas mixture. Pinhole density analysis as a function of substrate temperature for different microwave powers was carried out. Films deposited at higher microwave power and at room temperature show defect densities (<7 pinhole/mm{sup 2}), ensuring low-temperature process integration on large area. From Fourier transform infrared analysis and thermal desorption spectrometry we also evaluated very low hydrogen content if compared to conventional rf-plasma-enhanced chemical-vapor-deposited (PECVD) SiO{sub 2} deposited at 350 deg. C. Electrical propertiesmore » have been measured in metal-oxide-semiconductor (MOS) capacitors, depositing SiO{sub 2} at RT as gate dielectric; breakdown electric fields >10 MV/cm and charge trapping at fields >6 MV/cm have been evaluated. From the study of interface quality in MOS capacitors, we found that even for low annealing temperature (200 deg. C), it is possible to considerably reduce the interface state density down to 5x10{sup 11} cm{sup -2} eV{sup -1}. To fully validate the ECR-PECVD silicon dioxide we fabricated polycrystalline silicon thin-film transistors using RT-deposited SiO{sub 2} as gate insulator. Different postdeposition thermal treatments have been studied and good device characteristics were obtained even for annealing temperature as low as 200 deg. C.« less

Efficiency of thermoelectric conversion in ferroelectric film capacitive structures

NASA Astrophysics Data System (ADS)

Volpyas, V. A.; Kozyrev, A. B.; Soldatenkov, O. I.; Tepina, E. R.

2012-06-01

Thermal heating/cooling conditions for metal-insulator-metal structures based on barium strontium titanate ferroelectric films are studied by numerical methods with the aim of their application in capacitive thermoelectric converters. A correlation between the thermal and capacitive properties of thin-film ferroelectric capacitors is considered. The time of the temperature response and the rate of variation of the capacitive properties of the metal-insulator-metal structures are determined by analyzing the dynamics of thermal processes. Thermophysical calculations are carried out that take into consideration the real electrical properties of barium strontium titanate ferroelectric films and allow estimation of thermal modulation parameters and the efficiency of capacitive thermoelectric converters on their basis.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Babadi, A. S., E-mail: aein.shiri-babadi@eit.lth.se; Lind, E.; Wernersson, L. E.

A qualitative analysis on capacitance-voltage and conductance data for high-κ/InAs capacitors is presented. Our measured data were evaluated with a full equivalent circuit model, including both majority and minority carriers, as well as interface and border traps, formulated for narrow band gap metal-oxide-semiconductor capacitors. By careful determination of interface trap densities, distribution of border traps across the oxide thickness, and taking into account the bulk semiconductor response, it is shown that the trap response has a strong effect on the measured capacitances. Due to the narrow bandgap of InAs, there can be a large surface concentration of electrons and holesmore » even in depletion, so a full charge treatment is necessary.« less

Capacitance-voltage measurement in memory devices using ferroelectric polymer

NASA Astrophysics Data System (ADS)

Nguyen, Chien A.; Lee, Pooi See

2006-01-01

Application of thin polymer film as storing mean for non-volatile memory devices is investigated. Capacitance-voltage (C-V) measurement of metal-ferroelectric-metal device using ferroelectric copolymer P(VDF-TrFE) as dielectric layer shows stable 'butter-fly' curve. The two peaks in C-V measurement corresponding to the largest capacitance are coincidental at the coercive voltages that give rise to zero polarization in the polarization hysteresis measurement. By comparing data of C-V and P-E measurement, a correlation between two types of hysteresis is established in which it reveals simultaneous electrical processes occurring inside the device. These processes are caused by the response of irreversible and reversible polarization to the applied electric field that can be used to present a memory window. The memory effect of ferroelectric copolymer is further demonstrated for fabricating polymeric non-volatile memory devices using metal-ferroelectric-insulator-semiconductor structure (MFIS). By applying different sweeping voltages at the gate, bidirectional flat-band voltage shift is observed in the ferroelectric capacitor. The asymmetrical shift after negative sweeping is resulted from charge accumulation at the surface of Si substrate caused by the dipole direction in the polymer layer. The effect is reversed for positive voltage sweeping.

Thin-film composite materials as a dielectric layer for flexible metal-insulator-metal capacitors.

PubMed

Tiwari, Jitendra N; Meena, Jagan Singh; Wu, Chung-Shu; Tiwari, Rajanish N; Chu, Min-Ching; Chang, Feng-Chih; Ko, Fu-Hsiang

2010-09-24

A new organic-organic nanoscale composite thin-film (NCTF) dielectric has been synthesized by solution deposition of 1-bromoadamantane and triblock copolymer (Pluronic P123, BASF, EO20-PO70-EO20), in which the precursor solution has been achieved with organic additives. We have used a sol-gel process to make a metal-insulator-metal capacitor (MIM) comprising a nanoscale (10 nm-thick) thin-film on a flexible polyimide (PI) substrate at room temperature. Scanning electron microscope and atomic force microscope revealed that the deposited NCTFs were crack-free, uniform, highly resistant to moisture absorption, and well adhered on the Au-Cr/PI. The electrical properties of 1-bromoadamantane-P123 NCTF were characterized by dielectric constant, capacitance, and leakage current measurements. The 1-bromoadamantane-P123 NCTF on the PI substrate showed a low leakage current density of 5.5 x 10(-11) A cm(-2) and good capacitance of 2.4 fF at 1 MHz. In addition, the calculated dielectric constant of 1-bromoadamantane-P123 NCTF was 1.9, making them suitable candidates for use in future flexible electronic devices as a stable intermetal dielectric. The electrical insulating properties of 1-bromoadamantane-P123 NCTF have been improved due to the optimized dipole moments of the van der Waals interactions.

Nanoscale semiconductor-insulator-metal core/shell heterostructures: facile synthesis and light emission.

PubMed

Li, Gong Ping; Chen, Rui; Guo, Dong Lai; Wong, Lai Mun; Wang, Shi Jie; Sun, Han Dong; Wu, Tom

2011-08-01

Controllably constructing hierarchical nanostructures with distinct components and designed architectures is an important theme of research in nanoscience, entailing novel but reliable approaches of bottom-up synthesis. Here, we report a facile method to reproducibly create semiconductor-insulator-metal core/shell nanostructures, which involves first coating uniform MgO shells onto metal oxide nanostructures in solution and then decorating them with Au nanoparticles. The semiconductor nanowire core can be almost any material and, herein, ZnO, SnO(2) and In(2)O(3) are used as examples. We also show that linear chains of short ZnO nanorods embedded in MgO nanotubes and porous MgO nanotubes can be obtained by taking advantage of the reduced thermal stability of the ZnO core. Furthermore, after MgO shell-coating and the appropriate annealing treatment, the intensity of the ZnO near-band-edge UV emission becomes much stronger, showing a 25-fold enhancement. The intensity ratio of the UV/visible emission can be increased further by decorating the surface of the ZnO/MgO nanowires with high-density plasmonic Au nanoparticles. These heterostructured semiconductor-insulator-metal nanowires with tailored morphologies and enhanced functionalities have great potential for use as nanoscale building blocks in photonic and electronic applications. This journal is © The Royal Society of Chemistry 2011

Berry phase mechanism of the anomalous Hall effect in a disordered two-dimensional magnetic semiconductor structure.

DOE PAGES

Oveshnikov, L. N.; Kulbachinskii, V. A.; Davydov, A. B.; ...

2015-11-24

In this study, the anomalous Hall effect (AHE) arises from the interplay of spin-orbit interactions and ferromagnetic order and is a potentially useful probe of electron spin polarization, especially in nanoscale systems where direct measurement is not feasible. While AHE is rather well-understood in metallic ferromagnets, much less is known about the relevance of different physical mechanisms governing AHE in insulators. As ferromagnetic insulators, but not metals, lend themselves to gatecontrol of electron spin polarization, understanding AHE in the insulating state is valuable from the point of view of spintronic applications. Among the mechanisms proposed in the literature for AHEmore » in insulators, the one related to a geometric (Berry) phase effect has been elusive in past studies. The recent discovery of quantized AHE in magnetically doped topological insulators - essentially a Berry phase effect - provides strong additional motivation to undertake more careful search for geometric phase effects in AHE in the magnetic semiconductors. Here we report our experiments on the temperature and magnetic field dependences of AHE in insulating, strongly-disordered two-dimensional Mn delta-doped semiconductor heterostructures in the hopping regime. In particular, it is shown that at sufficiently low temperatures, the mechanism of AHE related to the Berry phase is favoured.« less

Berry phase mechanism of the anomalous Hall effect in a disordered two-dimensional magnetic semiconductor structure

PubMed Central

Oveshnikov, L. N.; Kulbachinskii, V. A.; Davydov, A. B.; Aronzon, B. A.; Rozhansky, I. V.; Averkiev, N. S.; Kugel, K. I.; Tripathi, V.

2015-01-01

The anomalous Hall effect (AHE) arises from the interplay of spin-orbit interactions and ferromagnetic order and is a potentially useful probe of electron spin polarization, especially in nanoscale systems where direct measurement is not feasible. While AHE is rather well-understood in metallic ferromagnets, much less is known about the relevance of different physical mechanisms governing AHE in insulators. As ferromagnetic insulators, but not metals, lend themselves to gate-control of electron spin polarization, understanding AHE in the insulating state is valuable from the point of view of spintronic applications. Among the mechanisms proposed in the literature for AHE in insulators, the one related to a geometric (Berry) phase effect has been elusive in past studies. The recent discovery of quantized AHE in magnetically doped topological insulators - essentially a Berry phase effect - provides strong additional motivation to undertake more careful search for geometric phase effects in AHE in the magnetic semiconductors. Here we report our experiments on the temperature and magnetic field dependences of AHE in insulating, strongly-disordered two-dimensional Mn delta-doped semiconductor heterostructures in the hopping regime. In particular, it is shown that at sufficiently low temperatures, the mechanism of AHE related to the Berry phase is favoured. PMID:26596472

Coulomb Blockade Plasmonic Switch.

PubMed

Xiang, Dao; Wu, Jian; Gordon, Reuven

2017-04-12

Tunnel resistance can be modulated with bias via the Coulomb blockade effect, which gives a highly nonlinear response current. Here we investigate the optical response of a metal-insulator-nanoparticle-insulator-metal structure and show switching of a plasmonic gap from insulator to conductor via Coulomb blockade. By introducing a sufficiently large charging energy in the tunnelling gap, the Coulomb blockade allows for a conductor (tunneling) to insulator (capacitor) transition. The tunnelling electrons can be delocalized over the nanocapacitor again when a high energy penalty is added with bias. We demonstrate that this has a huge impact on the plasmonic resonance of a 0.51 nm tunneling gap with ∼70% change in normalized optical loss. Because this structure has a tiny capacitance, there is potential to harness the effect for high-speed switching.

Efficient Carrier-to-Exciton Conversion in Field Emission Tunnel Diodes Based on MIS-Type van der Waals Heterostack.

PubMed

Wang, Shunfeng; Wang, Junyong; Zhao, Weijie; Giustiniano, Francesco; Chu, Leiqiang; Verzhbitskiy, Ivan; Zhou Yong, Justin; Eda, Goki

2017-08-09

We report on efficient carrier-to-exciton conversion and planar electroluminescence from tunnel diodes based on a metal-insulator-semiconductor (MIS) van der Waals heterostack consisting of few-layer graphene (FLG), hexagonal boron nitride (hBN), and monolayer tungsten disulfide (WS 2 ). These devices exhibit excitonic electroluminescence with extremely low threshold current density of a few pA·μm -2 , which is several orders of magnitude lower compared to the previously reported values for the best planar EL devices. Using a reference dye, we estimate the EL quantum efficiency to be ∼1% at low current density limit, which is of the same order of magnitude as photoluminescence quantum yield at the equivalent excitation rate. Our observations reveal that the efficiency of our devices is not limited by carrier-to-exciton conversion efficiency but by the inherent exciton-to-photon yield of the material. The device characteristics indicate that the light emission is triggered by injection of hot minority carriers (holes) to n-doped WS 2 by Fowler-Nordheim tunneling and that hBN serves as an efficient hole-transport and electron-blocking layer. Our findings offer insight into the intelligent design of van der Waals heterostructures and avenues for realizing efficient excitonic devices.

Characterization of high-{kappa} LaLuO{sub 3} thin film grown on AlGaN/GaN heterostructure by molecular beam deposition

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yang Shu; Huang Sen; Chen Hongwei

2011-10-31

We report the study of high-dielectric-constant (high-{kappa}) dielectric LaLuO{sub 3} (LLO) thin film that is grown on AlGaN/GaN heterostructure by molecular beam deposition (MBD). The physical properties of LLO on AlGaN/GaN heterostrucure have been investigated with atomic force microscopy, x-ray photoelectron spectroscopy, and TEM. It is revealed that the MBD-grown 16 nm-thick LLO film is polycrystalline with a thin ({approx}2 nm) amorphous transition layer at the LLO/GaN interface. The bandgap of LLO is derived as 5.3 {+-} 0.04 eV from O1s energy loss spectrum. Capacitance-voltage (C-V) characteristics of a Ni-Au/LLO/III-nitride metal-insulator-semiconductor diode exhibit small frequency dispersion (<2%) and reveal amore » high effective dielectric constant of {approx}28 for the LLO film. The LLO layer is shown to be effective in suppressing the reverse and forward leakage current in the MIS diode. In particular, the MIS diode forward current is reduced by 7 orders of magnitude at a forward bias of 1 V compared to a conventional Ni-Au/III-nitride Schottky diode.« less

Insulators obtained by electron cyclotron resonance plasmas on Si or GaAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Diniz, J.A.; Doi, I.; Swart, J.W

2003-03-15

Silicon oxynitride (SiO{sub x}N{sub y}) and nitride (SiN{sub x}) insulators have been deposited or grown (with or without silane in the gas mixture, respectively) by electron cyclotron resonance (ECR) plasmas on Si and/or GaAs substrates at room temperature (20 deg. C) and low pressures (up to 10 mTorr). Chemical bonding characteristics of the SiO{sub x}N{sub y} and SiN{sub x} films were evaluated using Fourier transform infrared spectrometry (FTIR). The profile measurements determined the film thickness, the deposition (or oxidation) rate and the etch rates in buffered HF (BHF). The refractive indexes and the thicknesses were determined by ellipsometry. The effectivemore » interface charge densities were determined by capacitance-voltage (C-V) measurements. With these processes and analyses, different films were obtained and optimized. Suitable gate insulators for metal-insulator-semiconductor (MIS) devices with low interface charge densities were developed: (a) SiN{sub x} films deposited by ECR-chemical vapor deposition (ECR-PECVD) on GaAs substrates; (b) SiO{sub x}N{sub y} insulators obtained by low-energy molecular nitrogen ion ({sup 28}N{sub 2}{sup +}) implantation (energy of 5 keV and dose of 1x10{sup 15}/cm{sup 2}) in Si substrates prior to high-density O{sub 2} ECR plasma oxidation; and (c) SiO{sub x}N{sub y} insulators grown (without silane in the gas mixture) by O{sub 2}/N{sub 2}/Ar ECR plasma 'oxynitridation'. Furthermore, some SiN{sub x} films also present very good masking characteristics for local oxidation of silicon process.« less

Electrode influence on the number of oxygen vacancies at the gate/high-κ dielectric interface in nanoscale MIM capacitors

NASA Astrophysics Data System (ADS)

Stojanovska-Georgievska, Lihnida

2015-02-01

In this paper, a particular attention has been paid in determining the impact of the type of top electrode (the gate), on the overall characteristics of the examined metal-insulator-metal structures, that contain doped Ta2O5:Hf high-κ dielectric as an insulator. For that purpose MIM capacitors with different metal gates (conventional Al and also W, Au, Pt, Mo, TiN, Ta) were formed. The results obtained, consider both the influence of metal work function and oxygen affinity, as possible reasons for increasing of number of oxygen vacancies at the gate/dielectric interface. Here we use capacitance-voltage alteration (C-V measurements) under constant current stress (CCS) conditions as characterization technique. The measurements show grater creation of positive oxygen vacancies in the case of metal electrodes with high work function, like Au and Pt, for almost one order of magnitude. It is also indicative that these metals have also the lowest values of heat of oxygen formation, which also favors the creation of oxygen vacancies. All results are discussed taking into consideration the nanoscale thickness of the dielectric layer (of the order of 8 nm), implicating the stronger effect of interface properties on the overall behavior rather than the one originating from the bulk of material.

Absorption Voltages and Insulation Resistance in Ceramic Capacitors with Cracks

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander

2016-01-01

Time dependence of absorption voltages (Vabs) in different types of low-voltage X5R and X7R ceramic capacitors was monitored for a maximum duration of hundred hours after polarization. To evaluate the effect of mechanical defects on Vabs, cracks in the dielectric were introduced either mechanically or by thermal shock. The maximum absorption voltage, time to roll-off, and the rate of voltage decrease are shown to depend on the crack-related leakage currents and insulation resistance in the parts. A simple model that is based on the Dow equivalent circuit for capacitors with absorption has been developed to assess the insulation resistance of capacitors. Standard measurements of the insulation resistance, contrary to the measurements based on Vabs, are not sensitive to the presence of mechanical defects and fail to reveal capacitors with cracks. Index Terms: Ceramic capacitor, insulation resistance, dielectric absorption, cracking.

Voltage-Dependent Charge Storage in Cladded Zn0.56Cd0.44Se Quantum Dot MOS Capacitors for Multibit Memory Applications

NASA Astrophysics Data System (ADS)

Khan, J.; Lingalugari, M.; Al-Amoody, F.; Jain, F.

2013-11-01

As conventional memories approach scaling limitations, new storage methods must be utilized to increase Si yield and produce higher on-chip memory density. Use of II-VI Zn0.56Cd0.44Se quantum dots (QDs) is compatible with epitaxial gate insulators such as ZnS-ZnMgS. Voltage-dependent charging effects in cladded Zn0.56Cd0.44Se QDs are presented in a conventional metal-oxide-semiconductor capacitor structure. Charge storage capabilities in Si and ZnMgS QDs have been reported by various researchers; this work is focused on II-VI material Zn0.56Cd0.44Se QDs nucleated using photoassisted microwave plasma metalorganic chemical vapor deposition. Using capacitance-voltage hysteresis characterization, the multistep charging and discharging capabilities of the QDs at room temperature are presented. Three charging states are presented within a 10 V charging voltage range. These characteristics exemplify discrete charge states in the QD layer, perfect for multibit, QD-functionalized high-density memory applications. Multiple charge states with low operating voltage provide device characteristics that can be used for multibit storage by allowing varying charges to be stored in a QD layer based on the applied "write" voltage.

A study to investigate the chemical stability of gallium phosphate oxide/gallium arsenide phosphide

NASA Technical Reports Server (NTRS)

Kuhlman, G. J.

1979-01-01

The elemental composition with depth into the oxide films was examined using secondary ion mass spectrometry. Results indicate that the layers are arsenic-deficient through the bulk of the oxide and arsenic-rich near both the oxide surface and the oxide-semiconductor interface region. Phosphorus is incorporated into the oxide in an approximately uniform manner. The MIS capacitor structures exhibited deep-depletion characteristics and hysteresis indicative of electron trapping at the oxide-semiconductor interface. Post-oxidation annealing of the films in argon or nitrogen generally results in slightly increased dielectric leakage currents and decreased C-V hysteresis effects, and is associated with arsenic loss at the oxide surface. The results of bias-temperature stress experiments indicate that the major instability effects are due to changes in the electron trapping behavior. No changes were observed in the elemental profiles following electrical stressing, indicating that the grown films are chemically stable under device operating conditions.

Interfacial engineering of metal-insulator-semiconductor junctions for efficient and stable photoelectrochemical water oxidation

PubMed Central

Digdaya, Ibadillah A.; Adhyaksa, Gede W. P.; Trześniewski, Bartek J.; Garnett, Erik C.; Smith, Wilson A.

2017-01-01

Solar-assisted water splitting can potentially provide an efficient route for large-scale renewable energy conversion and storage. It is essential for such a system to provide a sufficiently high photocurrent and photovoltage to drive the water oxidation reaction. Here we demonstrate a photoanode that is capable of achieving a high photovoltage by engineering the interfacial energetics of metal–insulator–semiconductor junctions. We evaluate the importance of using two metals to decouple the functionalities for a Schottky contact and a highly efficient catalyst. We also illustrate the improvement of the photovoltage upon incidental oxidation of the metallic surface layer in KOH solution. Additionally, we analyse the role of the thin insulating layer to the pinning and depinning of Fermi level that is responsible to the resulting photovoltage. Finally, we report the advantage of using dual metal overlayers as a simple protection route for highly efficient metal–insulator–semiconductor photoanodes by showing over 200 h of operational stability. PMID:28660883

Room-temperature ductile inorganic semiconductor.

PubMed

Shi, Xun; Chen, Hongyi; Hao, Feng; Liu, Ruiheng; Wang, Tuo; Qiu, Pengfei; Burkhardt, Ulrich; Grin, Yuri; Chen, Lidong

2018-05-01

Ductility is common in metals and metal-based alloys, but is rarely observed in inorganic semiconductors and ceramic insulators. In particular, room-temperature ductile inorganic semiconductors were not known until now. Here, we report an inorganic α-Ag 2 S semiconductor that exhibits extraordinary metal-like ductility with high plastic deformation strains at room temperature. Analysis of the chemical bonding reveals systems of planes with relatively weak atomic interactions in the crystal structure. In combination with irregularly distributed silver-silver and sulfur-silver bonds due to the silver diffusion, they suppress the cleavage of the material, and thus result in unprecedented ductility. This work opens up the possibility of searching for ductile inorganic semiconductors/ceramics for flexible electronic devices.

Room-temperature ductile inorganic semiconductor

NASA Astrophysics Data System (ADS)

Shi, Xun; Chen, Hongyi; Hao, Feng; Liu, Ruiheng; Wang, Tuo; Qiu, Pengfei; Burkhardt, Ulrich; Grin, Yuri; Chen, Lidong

2018-05-01

Ductility is common in metals and metal-based alloys, but is rarely observed in inorganic semiconductors and ceramic insulators. In particular, room-temperature ductile inorganic semiconductors were not known until now. Here, we report an inorganic α-Ag2S semiconductor that exhibits extraordinary metal-like ductility with high plastic deformation strains at room temperature. Analysis of the chemical bonding reveals systems of planes with relatively weak atomic interactions in the crystal structure. In combination with irregularly distributed silver-silver and sulfur-silver bonds due to the silver diffusion, they suppress the cleavage of the material, and thus result in unprecedented ductility. This work opens up the possibility of searching for ductile inorganic semiconductors/ceramics for flexible electronic devices.

Fabrication of PVDF-TrFE based bilayered PbTiO{sub 3}/PVDF-TrFE films capacitor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nurbaya, Z., E-mail: nurbayazainal@gmail.com; Razak School of Engineering and Advanced Technology, Universiti Teknologi Malaysia, 54100 Kuala Lumpur; Wahid, M. H.

2016-07-06

Development of high performance capacitor is reaching towards new generation where the ferroelectric materials take places as the active dielectric layer. The motivation of this study is to produce high capacitance device with long life cycle. This was configured by preparing bilayered films where lead titanate as an active dielectric layer and stacked with the top dielectric layer, poly(vinyledenefluoride-trifluoroethylene). Both of them are being referred that have one in common which is ferroelectric behavior. Therefore the combination of ceramic and polymer ferroelectric material could perform optimum dielectric characteristic for capacitor applications. The fabrication was done by simple sol-gel spin coatingmore » method that being varied at spinning speed property for polymer layers, whereas maintaining the ceramic layer. The characterization of PVDF-TrFE/PbTiO3 was performed according to metal-insulator-metal stacked capacitor measurement which includes structural, dielectric, and ferroelectric measurement.« less

Thin-film solar cell fabricated on a flexible metallic substrate

DOEpatents

Tuttle, John R.; Noufi, Rommel; Hasoon, Falah S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Thin-Film Solar Cell Fabricated on a Flexible Metallic Substrate

DOEpatents

Tuttle, J. R.; Noufi, R.; Hasoon, F. S.

2006-05-30

A thin-film solar cell (10) is provided. The thin-film solar cell (10) comprises a flexible metallic substrate (12) having a first surface and a second surface. A back metal contact layer (16) is deposited on the first surface of the flexible metallic substrate (12). A semiconductor absorber layer (14) is deposited on the back metal contact. A photoactive film deposited on the semiconductor absorber layer (14) forms a heterojunction structure and a grid contact (24) deposited on the heterjunction structure. The flexible metal substrate (12) can be constructed of either aluminium or stainless steel. Furthermore, a method of constructing a solar cell is provided. The method comprises providing an aluminum substrate (12), depositing a semiconductor absorber layer (14) on the aluminum substrate (12), and insulating the aluminum substrate (12) from the semiconductor absorber layer (14) to inhibit reaction between the aluminum substrate (12) and the semiconductor absorber layer (14).

Nanoscale semiconductor-insulator-metal core/shell heterostructures: facile synthesis and light emission

NASA Astrophysics Data System (ADS)

Li, Gong Ping; Chen, Rui; Guo, Dong Lai; Wong, Lai Mun; Wang, Shi Jie; Sun, Han Dong; Wu, Tom

2011-08-01

Controllably constructing hierarchical nanostructures with distinct components and designed architectures is an important theme of research in nanoscience, entailing novel but reliable approaches of bottom-up synthesis. Here, we report a facile method to reproducibly create semiconductor-insulator-metal core/shell nanostructures, which involves first coating uniform MgO shells onto metal oxide nanostructures in solution and then decorating them with Au nanoparticles. The semiconductor nanowire core can be almost any material and, herein, ZnO, SnO2 and In2O3 are used as examples. We also show that linear chains of short ZnO nanorods embedded in MgO nanotubes and porous MgO nanotubes can be obtained by taking advantage of the reduced thermal stability of the ZnO core. Furthermore, after MgO shell-coating and the appropriate annealing treatment, the intensity of the ZnO near-band-edge UV emission becomes much stronger, showing a 25-fold enhancement. The intensity ratio of the UV/visible emission can be increased further by decorating the surface of the ZnO/MgO nanowires with high-density plasmonic Au nanoparticles. These heterostructured semiconductor-insulator-metal nanowires with tailored morphologies and enhanced functionalities have great potential for use as nanoscale building blocks in photonic and electronic applications.Controllably constructing hierarchical nanostructures with distinct components and designed architectures is an important theme of research in nanoscience, entailing novel but reliable approaches of bottom-up synthesis. Here, we report a facile method to reproducibly create semiconductor-insulator-metal core/shell nanostructures, which involves first coating uniform MgO shells onto metal oxide nanostructures in solution and then decorating them with Au nanoparticles. The semiconductor nanowire core can be almost any material and, herein, ZnO, SnO2 and In2O3 are used as examples. We also show that linear chains of short ZnO nanorods embedded in MgO nanotubes and porous MgO nanotubes can be obtained by taking advantage of the reduced thermal stability of the ZnO core. Furthermore, after MgO shell-coating and the appropriate annealing treatment, the intensity of the ZnO near-band-edge UV emission becomes much stronger, showing a 25-fold enhancement. The intensity ratio of the UV/visible emission can be increased further by decorating the surface of the ZnO/MgO nanowires with high-density plasmonic Au nanoparticles. These heterostructured semiconductor-insulator-metal nanowires with tailored morphologies and enhanced functionalities have great potential for use as nanoscale building blocks in photonic and electronic applications. Electronic supplementary information (ESI) available: Representative SEM and TEM images of 700 °C annealed ZnO/MgO core/shell NWs, a TEM image of an individual MgO nanocrystal inside the MgO NTs and SEM images of SnO2 NP chains embedded in MgO NTs and comb-shaped MgO hollow nanostructures. See DOI: 10.1039/c1nr10352k

Synchrotron radiation x-ray photoelectron spectroscopy study on the interface chemistry of high-k PrxAl2-xO3 (x=0-2) dielectrics on TiN for dynamic random access memory applications

NASA Astrophysics Data System (ADS)

Schroeder, T.; Lupina, G.; Sohal, R.; Lippert, G.; Wenger, Ch.; Seifarth, O.; Tallarida, M.; Schmeisser, D.

2007-07-01

Engineered dielectrics combined with compatible metal electrodes are important materials science approaches to scale three-dimensional trench dynamic random access memory (DRAM) cells. Highly insulating dielectrics with high dielectric constants were engineered in this study on TiN metal electrodes by partly substituting Al in the wide band gap insulator Al2O3 by Pr cations. High quality PrAlO3 metal-insulator-metal capacitors were processed with a dielectric constant of 19, three times higher than in the case of Al2O3 reference cells. As a parasitic low dielectric constant interface layer between PrAlO3 and TiN limits the total performance gain, a systematic nondestructive synchrotron x-ray photoelectron spectroscopy study on the interface chemistry of PrxAl2-xO3 (x =0-2) dielectrics on TiN layers was applied to unveil its chemical origin. The interface layer results from the decreasing chemical reactivity of PrxAl2-xO3 dielectrics with increasing Pr content x to reduce native Ti oxide compounds present on unprotected TiN films. Accordingly, PrAlO3 based DRAM capacitors require strict control of the surface chemistry of the TiN electrode, a parameter furthermore of importance to engineer the band offsets of PrxAl2-xO3/TiN heterojunctions.

Ferroelectricity in epitaxial Y-doped HfO2 thin film integrated on Si substrate

NASA Astrophysics Data System (ADS)

Lee, K.; Lee, T. Y.; Yang, S. M.; Lee, D. H.; Park, J.; Chae, S. C.

2018-05-01

We report on the ferroelectricity of a Y-doped HfO2 thin film epitaxially grown on Si substrate, with an yttria-stabilized zirconia buffer layer pre-deposited on the substrate. Piezoresponse force microscopy results show the ferroelectric domain pattern, implying the existence of ferroelectricity in the epitaxial HfO2 film. The epitaxially stabilized HfO2 film in the form of a metal-ferroelectric-insulator-semiconductor structure exhibits ferroelectric hysteresis with a clear ferroelectric switching current in polarization-voltage measurements. The HfO2 thin film also demonstrates ferroelectric retention comparable to that of current perovskite-based metal-ferroelectric-insulator-semiconductor structures.

Frequency jumps in single chip microwave LC oscillators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gualco, Gabriele; Grisi, Marco; Boero, Giovanni, E-mail: giovanni.boero@epfl.ch

2014-12-15

We report on the experimental observation of oscillation frequency jumps in microwave LC oscillators fabricated using standard complementary metal-oxide-semiconductor technologies. The LC oscillators, operating at a frequency of about 20 GHz, consist of a single turn planar coil, a metal-oxide-metal capacitor, and two cross-coupled metal-oxide-semiconductor field effect transistors used as negative resistance network. At 300 K as well as at 77 K, the oscillation frequency is a continuous function of the oscillator bias voltage. At 4 K, frequency jumps as large as 30 MHz are experimentally observed. This behavior is tentatively attributed to the emission and capture of single electrons from defects andmore » dopant atoms.« less

Miniaturized Metal (Metal Alloy)/PdO(x)/SiC Hydrogen and Hydrocarbon Gas Sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO(x)). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600 C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sided sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

LC and ferromagnetic resonance in soft/hard magnetic microwires

NASA Astrophysics Data System (ADS)

Tian, Bin; Vazquez, Manuel

2015-12-01

The magnetic behavior of soft/hard biphase microwires is introduced here. The microwires consist of a Co59.1Fe14.8Si10.2B15.9 soft magnetic nucleus and a Co90Ni10 hard outer shell separated by an intermediate insulating Pyrex glass microtube. By comparing the resistance spectrums of welding the ends of metallic core (CC) or welding the metallic core and outer shell (CS) to the connector, it is found that one of the two peaks in the resistance spectrum is because the LC resonance depends on the inductor and capacitors in which one is the capacitor between the metallic core and outer shell, and the other is between the outer shell and connector. Correspondingly, another peak is for the ferromagnetic resonance of metallic core. After changing the capacitance of the capacitors, the frequency of LC resonance moves to high frequency band, and furthermore, the peak of LC resonance in the resistance spectrum disappeared. These magnetostatically coupled biphase systems are thought to be of large potential interest as sensing elements in sensor devices.

Novel Dry-Type Glucose Sensor Based on a Metal-Oxide-Semiconductor Capacitor Structure with Horseradish Peroxidase + Glucose Oxidase Catalyzing Layer

NASA Astrophysics Data System (ADS)

Lin, Jing-Jenn; Wu, You-Lin; Hsu, Po-Yen

2007-10-01

In this paper, we present a novel dry-type glucose sensor based on a metal-oxide-semiconductor capacitor (MOSC) structure using SiO2 as a gate dielectric in conjunction with a horseradish peroxidase (HRP) + glucose oxidase (GOD) catalyzing layer. The tested glucose solution was dropped directly onto the window opened on the SiO2 layer, with a coating of HRP + GOD catalyzing layer on top of the gate dielectric. From the capacitance-voltage (C-V) characteristics of the sensor, we found that the glucose solution can induce an inversion layer on the silicon surface causing a gate leakage current flowing along the SiO2 surface. The gate current changes Δ I before and after the drop of glucose solution exhibits a near-linear relationship with increasing glucose concentration. The Δ I sensitivity is about 1.76 nA cm-2 M-1, and the current is quite stable 20 min after the drop of the glucose solution is tested.

Comparative Study of HfTa-based gate-dielectric Ge metal-oxide-semiconductor capacitors with and without AlON interlayer

NASA Astrophysics Data System (ADS)

Xu, J. P.; Zhang, X. F.; Li, C. X.; Chan, C. L.; Lai, P. T.

2010-04-01

The electrical properties and high-field reliability of HfTa-based gate-dielectric metal-oxide-semiconductor (MOS) devices with and without AlON interlayer on Ge substrate are investigated. Experimental results show that the MOS capacitor with HfTaON/AlON stack gate dielectric exhibits low interface-state/oxide-charge densities, low gate leakage, small capacitance equivalent thickness (˜1.1 nm), and high dielectric constant (˜20). All of these should be attributed to the blocking role of the ultrathin AlON interlayer against interdiffusions of Ge, Hf, and Ta and penetration of O into the Ge substrate, with the latter effectively suppressing the unintentional formation of unstable poor-quality low- k GeO x and giving a superior AlON/Ge interface. Moreover, incorporation of N into both the interlayer and high- k dielectric further improves the device reliability under high-field stress through the formation of strong N-related bonds.

Improved interfacial and electrical properties of GaAs metal-oxide-semiconductor capacitors with HfTiON as gate dielectric and TaON as passivation interlayer

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Zhu, S. Y.; Huang, Y.; Lai, P. T.

2013-08-01

The interfacial and electrical properties of sputtered HfTiON on sulfur-passivated GaAs with or without TaON as interfacial passivation layer (IPL) are investigated. Experimental results show that the GaAs metal-oxide-semiconductor capacitor with HfTiON/TaON stacked gate dielectric annealed at 600 °C exhibits low interface-state density (1.0 × 1012 cm-2 eV-1), small gate leakage current (7.3 × 10-5 A cm-2 at Vg = Vfb + 1 V), small capacitance equivalent thickness (1.65 nm), and large equivalent dielectric constant (26.2). The involved mechanisms lie in the fact that the TaON IPL can effectively block the diffusions of Hf, Ti, and O towards GaAs surface and suppress the formation of interfacial As-As bonds, Ga-/As-oxides, thus unpinning the Femi level at the TaON/GaAs interface and improving the interface quality and electrical properties of the device.

Passivation of oxide traps and interface states in GaAs metal-oxide-semiconductor capacitor by LaTaON passivation layer and fluorine incorporation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Liu, L. N.; Choi, H. W.; Lai, P. T., E-mail: laip@eee.hku.hk

2015-11-23

GaAs metal-oxide-semiconductor capacitor with TaYON/LaTaON gate-oxide stack and fluorine-plasma treatment is fabricated and compared with its counterparts without the LaTaON passivation interlayer or the fluorine treatment. Experimental results show that the sample exhibits better characteristics: low interface-state density (8 × 10{sup 11 }cm{sup −2}/eV), small flatband voltage (0.69 V), good capacitance-voltage behavior, small frequency dispersion, and small gate leakage current (6.35 × 10{sup −6} A/cm{sup 2} at V{sub fb} + 1 V). These should be attributed to the suppressed growth of unstable Ga and As oxides on the GaAs surface during gate-oxide annealing by the LaTaON interlayer and fluorine incorporation, and the passivating effects of fluorine atoms on the acceptor-likemore » interface and near-interface traps.« less

Combinatorial Investigation of ZrO2-Based Dielectric Materials for Dynamic Random-Access Memory Capacitors

NASA Astrophysics Data System (ADS)

Kiyota, Yuji; Itaka, Kenji; Iwashita, Yuta; Adachi, Tetsuya; Chikyow, Toyohiro; Ogura, Atsushi

2011-06-01

We investigated zirconia (ZrO2)-based material libraries in search of new dielectric materials for dynamic random-access memory (DRAM) by combinatorial-pulsed laser deposition (combi-PLD). We found that the substitution of yttrium (Y) to Zr sites in the ZrO2 system suppressed the leakage current effectively. The metal-insulator-metal (MIM) capacitor property of this system showed a leakage current density of less than 5×10-7 A/cm2 and the dielectric constant was 20. Moreover, the addition of titanium (Ti) or tantalum (Ta) to this system caused the dielectric constant to increase to ˜25 within the allowed leakage level of 5×10-7 A/cm2. Therefore, Zr-Y-Ti-O and Zr-Y-Ta-O systems have good potentials for use as new materials with high dielectric constants of DRAM capacitors instead of silicon dioxides (SiO2).

The optical characterization of organometallic complex thin films by spectroscopic ellipsometry and photovoltaic diode application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Özaydın, C.; Güllü, Ö., E-mail: omergullu@gmail.com; Pakma, O.

2016-05-15

Highlights: • Optical properties and thickness of the A novel organometallic complex (OMC) film were investigated by spectroscopic ellipsometry (SE). • Au/OMC/n-Si metal/interlayer/semiconductor (MIS) diode has been fabricated • This paper presents the I–V analysis of Au/OMC/n-Si MIS diode. • Current–voltage and photovoltaic properties of the diode were investigated. - Abstract: In this work, organometallic complex (OMC) films have been deposited onto glass or silicon substrates by spin coating technique and their photovoltaic application potential has been investigated. Optical properties and thickness of the film have been investigated by spectroscopic ellipsometry (SE). Also, transmittance spectrum has been taken by UV/vismore » spectrophotometer. The optical method has been used to determine the band gap value of the films. Also, Au/OMC/n-Si metal/interlayer/semiconductor (MIS) diode has been fabricated. Current–voltage and photovoltaic properties of the structure were investigated. The ideality factor (n) and barrier height (Φ{sub b}) values of the diode were found to be 2.89 and 0.79 eV, respectively. The device shows photovoltaic behavior with a maximum open-circuit voltage of 396 mV and a short circuit current of 33.8 μA under 300 W light.« less

Investigation of the sensitivity of MIS-sensor to thermal decomposition products of cables insulation

NASA Astrophysics Data System (ADS)

Filipchuk, D. V.; Litvinov, A. V.; Etrekova, M. O.; Nozdrya, D. A.

2017-12-01

Sensitivity of the MIS-sensor to products of thermal decomposition of insulation and jacket of the most common types of cables is investigated. It is shown that hydrogen is evolved under heating the insulation to temperatures not exceeding 250 °C. Registration of the evolved hydrogen by the MIS-sensor can be used for detection of fires at an early stage.

Ceramic Processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

EWSUK,KEVIN G.

1999-11-24

Ceramics represent a unique class of materials that are distinguished from common metals and plastics by their: (1) high hardness, stiffness, and good wear properties (i.e., abrasion resistance); (2) ability to withstand high temperatures (i.e., refractoriness); (3) chemical durability; and (4) electrical properties that allow them to be electrical insulators, semiconductors, or ionic conductors. Ceramics can be broken down into two general categories, traditional and advanced ceramics. Traditional ceramics include common household products such as clay pots, tiles, pipe, and bricks, porcelain china, sinks, and electrical insulators, and thermally insulating refractory bricks for ovens and fireplaces. Advanced ceramics, also referredmore » to as ''high-tech'' ceramics, include products such as spark plug bodies, piston rings, catalyst supports, and water pump seals for automobiles, thermally insulating tiles for the space shuttle, sodium vapor lamp tubes in streetlights, and the capacitors, resistors, transducers, and varistors in the solid-state electronics we use daily. The major differences between traditional and advanced ceramics are in the processing tolerances and cost. Traditional ceramics are manufactured with inexpensive raw materials, are relatively tolerant of minor process deviations, and are relatively inexpensive. Advanced ceramics are typically made with more refined raw materials and processing to optimize a given property or combination of properties (e.g., mechanical, electrical, dielectric, optical, thermal, physical, and/or magnetic) for a given application. Advanced ceramics generally have improved performance and reliability over traditional ceramics, but are typically more expensive. Additionally, advanced ceramics are typically more sensitive to the chemical and physical defects present in the starting raw materials, or those that are introduced during manufacturing.« less

Monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Barfknecht, Andrew T. (Inventor); Garcia, Graham A. (Inventor); Russell, Stephen D. (Inventor); Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Barrier height enhancement of metal/semiconductor contact by an enzyme biofilm interlayer

NASA Astrophysics Data System (ADS)

Ocak, Yusuf Selim; Gul Guven, Reyhan; Tombak, Ahmet; Kilicoglu, Tahsin; Guven, Kemal; Dogru, Mehmet

2013-06-01

A metal/interlayer/semiconductor (Al/enzyme/p-Si) MIS device was fabricated using α-amylase enzyme as a thin biofilm interlayer. It was observed that the device showed an excellent rectifying behavior and the barrier height value of 0.78 eV for Al/α-amylase/p-Si was meaningfully larger than the one of 0.58 eV for conventional Al/p-Si metal/semiconductor (MS) contact. Enhancement of the interfacial potential barrier of Al/p-Si MS diode was realized using enzyme interlayer by influencing the space charge region of Si semiconductor. The electrical properties of the structure were executed by the help of current-voltage and capacitance-voltage measurements. The photovoltaic properties of the structure were executed under a solar simulator with AM1.5 global filter between 40 and 100 mW/cm2 illumination conditions. It was also reported that the α-amylase enzyme produced from Bacillus licheniformis had a 3.65 eV band gap value obtained from optical method.

Optoelectronic Fibers via Selective Amplification of In-Fiber Capillary Instabilities.

PubMed

Wei, Lei; Hou, Chong; Levy, Etgar; Lestoquoy, Guillaume; Gumennik, Alexander; Abouraddy, Ayman F; Joannopoulos, John D; Fink, Yoel

2017-01-01

Thermally drawn metal-insulator-semiconductor fibers provide a scalable path to functional fibers. Here, a ladder-like metal-semiconductor-metal photodetecting device is formed inside a single silica fiber in a controllable and scalable manner, achieving a high density of optoelectronic components over the entire fiber length and operating at a bandwidth of 470 kHz, orders of magnitude larger than any other drawn fiber device. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Dielectric response of crystalline tris(acetylacetonato)cobalt(III) films grown on Si substrate for low- k dielectric applications

NASA Astrophysics Data System (ADS)

Dakhel, A. A.; Ali-Mohamed, A. Y.

2008-01-01

Thin films of the complex tris(acetylacetonato)cobalt(III) [abb. Co(acac) 3] were deposited in vacuum on glass and p-Si substrates for optical and dielectric studies. The samples were characterised by X-ray diffraction and fluorescence methods as well as optical absorption spectroscopy. The prepared films show a polycrystalline of monoclinic P2 1/ c structure. The optical absorption spectrum of the prepared film was not exactly fit to that of the molecular one. The energy of the optical absorption onset of the Co(acac) 3 film was calculated by using usual solid-state methods. For electrical measurements on the complex as insulator, samples in the form of metal-insulator-semiconductor (MIS) structure were prepared and characterised by measurement of the capacitance as a function of gate voltage at 1 MHz. The frequency dependence of the complex dielectric constant of the complex was studied in the frequency range (1-1000 kHz) in the temperature range (294-323 K). The experimental results were analysed in the framework of Debye single relaxation model. Generally, the present study shows that a film of complex Co(acac) 3 grown on Si substrate is a promising candidate for low- k dielectric applications, it displays low- k value around 1.7 at high frequencies.

Electrical characteristics and thermal stability of n+ polycrystalline- Si/ZrO2/SiO2/Si metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lim, Kwan-Yong; Park, Dae-Gyu; Cho, Heung-Jae; Kim, Joong-Jung; Yang, Jun-Mo; Ii, Choi-Sang; Yeo, In-Seok; Park, Jin Won

2002-01-01

We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50-140 Å)/SiO2(7 Å)/p-Si metal-oxide-semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance-voltage hysteresis as small as ˜12 mV with the flatband voltage of -0.5 V and the interface trap density of ˜5×1010cm-2 eV-1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (<50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min.

Transport Physics in Thin-Film Oxides: From Capacitors to Memristors1

NASA Astrophysics Data System (ADS)

Tierney, Brian; Hjalmarson, Harold; McLain, Michael; Hughart, David; Marinella, Matthew; Mamaluy, Denis; Gao, Xujiao

A physics-based model of transport mechanisms in metal-insulator-metal (M-I-M) systems is developed to explain transport through the metal-oxide interfaces and in the bulk of the insulating oxide. Interface tunneling, such as that between the metal to the conduction band or bound defect states, is accounted for by a WKB model. Our model also incorporates the evolution of the associated oxide defect chemistry. Continuum calculations are performed for both Ta2O5 M-I-M capacitors and TaOx-Based M-I-M memristors, as both devices are structurally similar and can be characterized by a common set of transport mechanisms. However, due to the electroforming process for which memristors are subjected, different transport mechanisms dominate for each type of device. Also, the effects of pulsed ionizing radiation from an external source are included in the model. It is shown that such radiation can be used to probe whether the M-I-M system is in a capacitive or memristive state. 1Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE-AC04-94AL85000.

Hg-Based Epitaxial Materials for Topological Insulators

DTIC Science & Technology

2014-07-01

Research Laboratory for investigation of properties. 15. SUBJECT TERMS EOARD, topological insulator , diluted magnetic ...topological superconductors and spintronics to quantum computation (e.g. see C.L.Kane and J.E.Moore "Topological Insulators " Physics World (2011) 24...tetradymite semiconductors Bi2Te3, Bi2Se3, and Sb2Te3 which form magnetically ordered insulators when doped with transition metal elements Cr or Fe (Rui Yu et

Investigation of embedded perovskite nanoparticles for enhanced capacitor permittivities.

PubMed

Krause, Andreas; Weber, Walter M; Pohl, Darius; Rellinghaus, Bernd; Verheijen, Marcel; Mikolajick, Thomas

2014-11-26

Growth experiments show significant differences in the crystallization of ultrathin CaTiO3 layers on polycrystalline Pt surfaces. While the deposition of ultrathin layers below crystallization temperature inhibits the full layer crystallization, local epitaxial growth of CaTiO3 crystals on top of specific oriented Pt crystals occurs. The result is a formation of crystals embedded in an amorphous matrix. An epitaxial alignment of the cubic CaTiO3 ⟨111⟩ direction on top of the underlying Pt {111} surface has been observed. A reduced forming energy is attributed to an interplay of surface energies at the {111} interface of both materials and CaTiO3 nanocrystallites facets. The preferential texturing of CaTiO3 layers on top of Pt has been used in the preparation of ultrathin metal-insulator-metal capacitors with 5-30 nm oxide thickness. The effective CaTiO3 permittivity in the capacitor stack increases to 55 compared to capacitors with amorphous layers and a permittivity of 28. The isolated CaTiO3 crystals exhibit a passivation of the CaTiO3 grain surfaces by the surrounding amorphous matrix, which keeps the capacitor leakage current at ideally low values comparable for those of amorphous thin film capacitors.

Surface Passivation for 3-5 Semiconductor Processing: Stable Gallium Sulphide Films by MOCVD

NASA Technical Reports Server (NTRS)

Macinnes, Andrew N.; Jenkins, Phillip P.; Power, Michael B.; Kang, Soon; Barron, Andrew R.; Hepp, Aloysius F.; Tabib-Azar, Massood

1994-01-01

Gallium sulphide (GaS) has been deposited on GaAs to form stable, insulating, passivating layers. Spectrally resolved photoluminescence and surface recombination velocity measurements indicate that the GaS itself can contribute a significant fraction of the photoluminescence in GaS/GaAs structures. Determination of surface recombination velocity by photoluminescence is therefore difficult. By using C-V analysis of metal-insulator-semiconductor structures, passivation of the GaAs with GaS films is quantified.

Capacitance-voltage analysis of electrical properties for WSe2 field effect transistors with high-k encapsulation layer

NASA Astrophysics Data System (ADS)

Ko, Seung-Pil; Shin, Jong Mok; Jang, Ho Kyun; You, Min Youl; Jin, Jun-Eon; Choi, Miri; Cho, Jiung; Kim, Gyu-Tae

2018-02-01

Doping effects in devices based on two-dimensional (2D) materials have been widely studied. However, detailed analysis and the mechanism of the doping effect caused by encapsulation layers has not been sufficiently explored. In this work, we present experimental studies on the n-doping effect in WSe2 field effect transistors (FETs) with a high-k encapsulation layer (Al2O3) grown by atomic layer deposition. In addition, we demonstrate the mechanism and origin of the doping effect. After encapsulation of the Al2O3 layer, the threshold voltage of the WSe2 FET negatively shifted with the increase of the on-current. The capacitance-voltage measurements of the metal insulator semiconductor (MIS) structure proved the presence of the positive fixed charges within the Al2O3 layer. The flat-band voltage of the MIS structure of Au/Al2O3/SiO2/Si was shifted toward the negative direction on account of the positive fixed charges in the Al2O3 layer. Our results clearly revealed that the fixed charges in the Al2O3 encapsulation layer modulated the Fermi energy level via the field effect. Moreover, these results possibly provide fundamental ideas and guidelines to design 2D materials FETs with high-performance and reliability.

Limitations of threshold voltage engineering of AlGaN/GaN heterostructures by dielectric interface charge density and manipulation by oxygen plasma surface treatments

NASA Astrophysics Data System (ADS)

Lükens, G.; Yacoub, H.; Kalisch, H.; Vescan, A.

2016-05-01

The interface charge density between the gate dielectric and an AlGaN/GaN heterostructure has a significant impact on the absolute value and stability of the threshold voltage Vth of metal-insulator-semiconductor (MIS) heterostructure field effect transistor. It is shown that a dry-etching step (as typically necessary for normally off devices engineered by gate-recessing) before the Al2O3 gate dielectric deposition introduces a high positive interface charge density. Its origin is most likely donor-type trap states shifting Vth to large negative values, which is detrimental for normally off devices. We investigate the influence of oxygen plasma annealing techniques of the dry-etched AlGaN/GaN surface by capacitance-voltage measurements and demonstrate that the positive interface charge density can be effectively compensated. Furthermore, only a low Vth hysteresis is observable making this approach suitable for threshold voltage engineering. Analysis of the electrostatics in the investigated MIS structures reveals that the maximum Vth shift to positive voltages achievable is fundamentally limited by the onset of accumulation of holes at the dielectric/barrier interface. In the case of the Al2O3/Al0.26Ga0.74N/GaN material system, this maximum threshold voltage shift is limited to 2.3 V.

Unified computational model of transport in metal-insulating oxide-metal systems

NASA Astrophysics Data System (ADS)

Tierney, B. D.; Hjalmarson, H. P.; Jacobs-Gedrim, R. B.; Agarwal, Sapan; James, C. D.; Marinella, M. J.

2018-04-01

A unified physics-based model of electron transport in metal-insulator-metal (MIM) systems is presented. In this model, transport through metal-oxide interfaces occurs by electron tunneling between the metal electrodes and oxide defect states. Transport in the oxide bulk is dominated by hopping, modeled as a series of tunneling events that alter the electron occupancy of defect states. Electron transport in the oxide conduction band is treated by the drift-diffusion formalism and defect chemistry reactions link all the various transport mechanisms. It is shown that the current-limiting effect of the interface band offsets is a function of the defect vacancy concentration. These results provide insight into the underlying physical mechanisms of leakage currents in oxide-based capacitors and steady-state electron transport in resistive random access memory (ReRAM) MIM devices. Finally, an explanation of ReRAM bipolar switching behavior based on these results is proposed.

A silicon-on-insulator complementary-metal-oxide-semiconductor compatible flexible electronics technology

NASA Astrophysics Data System (ADS)

Tu, Hongen; Xu, Yong

2012-07-01

This paper reports a simple flexible electronics technology that is compatible with silicon-on-insulator (SOI) complementary-metal-oxide-semiconductor (CMOS) processes. Compared with existing technologies such as direct fabrication on flexible substrates and transfer printing, the main advantage of this technology is its post-SOI-CMOS compatibility. Consequently, high-performance and high-density CMOS circuits can be first fabricated on SOI wafers using commercial foundry and then be integrated into flexible substrates. The yield is also improved by eliminating the transfer printing step. Furthermore, this technology allows the integration of various sensors and microfluidic devices. To prove the concept of this technology, flexible MOSFETs have been demonstrated.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Fabrication of solid-state secondary battery using semiconductors and evaluation of its charge/discharge characteristics

NASA Astrophysics Data System (ADS)

Sasaki, Atsuya; Sasaki, Akito; Hirabayashi, Hideaki; Saito, Shuichi; Aoki, Katsuaki; Kataoka, Yoshinori; Suzuki, Koji; Yabuhara, Hidehiko; Ito, Takahiro; Takagi, Shigeyuki

2018-04-01

Li-ion batteries have attracted interest for use as storage batteries. However, the risk of fire has not yet been resolved. Although solid Li-ion batteries are possible alternatives, their performance characteristics are unsatisfactory. Recently, research on utilizing the accumulation of carriers at the trap levels of semiconductors has been performed. However, the detailed charge/discharge characteristics and principles have not been reported. In this report, we attempted to form new n-type oxide semiconductor/insulator/p-type oxide semiconductor structures. The battery characteristics of these structures were evaluated by charge/discharge measurements. The obtained results clearly indicated the characteristics of rechargeable batteries. Furthermore, the fabricated structure accumulated an approximately 5000 times larger number of carriers than a parallel plate capacitor. Additionally, by constructing circuit models based on the experimental results, the charge/discharge mechanisms were considered. This is the first detailed experimental report on a rechargeable battery that operates without the double injection of ions and electrons.

Superconductivity in CVD diamond films.

PubMed

Takano, Yoshihiko

2009-06-24

A beautiful jewel of diamond is insulator. However, boron doping can induce semiconductive, metallic and superconducting properties in diamond. When the boron concentration is tuned over 3 × 10(20) cm(-3), diamonds enter the metallic region and show superconductivity at low temperatures. The metal-insulator transition and superconductivity are analyzed using ARPES, XAS, NMR, IXS, transport and magnetic measurements and so on. This review elucidates the physical properties and mechanism of diamond superconductor as a special superconductivity that occurs in semiconductors.

Characterization and Modeling Analysis for Metal-Semiconductor-Metal GaAs Diodes with Pd/SiO2 Mixture Electrode

PubMed Central

Tan, Shih-Wei; Lai, Shih-Wen

2012-01-01

Characterization and modeling of metal-semiconductor-metal (MSM) GaAs diodes using to evaporate SiO2 and Pd simultaneously as a mixture electrode (called M-MSM diodes) compared with similar to evaporate Pd as the electrode (called Pd-MSM diodes) were reported. The barrier height (φ b) and the Richardson constant (A*) were carried out for the thermionic-emission process to describe well the current transport for Pd-MSM diodes in the consideration of the carrier over the metal-semiconductor barrier. In addition, in the consideration of the carrier over both the metal-semiconductor barrier and the insulator-semiconductor barrier simultaneously, thus the thermionic-emission process can be used to describe well the current transport for M-MSM diodes. Furthermore, in the higher applied voltage, the carrier recombination will be taken into discussion. Besides, a composite-current (CC) model is developed to evidence the concepts. Our calculated results are in good agreement with the experimental ones. PMID:23226352

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Hunter, Gary W. (Inventor); Xu, Jennifer C. (Inventor); Lukco, Dorothy (Inventor)

2011-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x ). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

Miniaturized metal (metal alloy)/ PdO.sub.x/SiC hydrogen and hydrocarbon gas sensors

NASA Technical Reports Server (NTRS)

Xu, Jennifer C. (Inventor); Hunter, Gary W. (Inventor); Lukco, Dorothy (Inventor)

2008-01-01

A miniaturized Schottky diode hydrogen and hydrocarbon sensor and the method of making same is disclosed and claimed. The sensor comprises a catalytic metal layer, such as palladium, a silicon carbide substrate layer and a thin barrier layer in between the catalytic and substrate layers made of palladium oxide (PdO.sub.x). This highly stable device provides sensitive gas detection at temperatures ranging from at least 450 to 600.degree. C. The barrier layer prevents reactions between the catalytic metal layer and the substrate layer. Conventional semiconductor fabrication techniques are used to fabricate the small-sized sensors. The use of a thicker palladium oxide barrier layer for other semiconductor structures such as a capacitor and transistor structures is also disclosed.

MOSFET Electric-Charge Sensor

NASA Technical Reports Server (NTRS)

Robinson, Paul A., Jr.

1988-01-01

Charged-particle probe compact and consumes little power. Proposed modification enables metal oxide/semiconductor field-effect transistor (MOSFET) to act as detector of static electric charges or energetic charged particles. Thickened gate insulation acts as control structure. During measurements metal gate allowed to "float" to potential of charge accumulated in insulation. Stack of modified MOSFET'S constitutes detector of energetic charged particles. Each gate "floats" to potential induced by charged-particle beam penetrating its layer.

Lateral amorphous selenium metal-insulator-semiconductor-insulator-metal photodetectors using ultrathin dielectric blocking layers for dark current suppression

NASA Astrophysics Data System (ADS)

Chang, Cheng-Yi; Pan, Fu-Ming; Lin, Jian-Siang; Yu, Tung-Yuan; Li, Yi-Ming; Chen, Chieh-Yang

2016-12-01

We fabricated amorphous selenium (a-Se) photodetectors with a lateral metal-insulator-semiconductor-insulator-metal (MISIM) device structure. Thermal aluminum oxide, plasma-enhanced chemical vapor deposited silicon nitride, and thermal atomic layer deposited (ALD) aluminum oxide and hafnium oxide (ALD-HfO2) were used as the electron and hole blocking layers of the MISIM photodetectors for dark current suppression. A reduction in the dark current by three orders of magnitude can be achieved at electric fields between 10 and 30 V/μm. The effective dark current suppression is primarily ascribed to electric field lowering in the dielectric layers as a result of charge trapping in deep levels. Photogenerated carriers in the a-Se layer can be transported across the blocking layers to the Al electrodes via Fowler-Nordheim tunneling because a high electric field develops in the ultrathin dielectric layers under illumination. Since the a-Se MISIM photodetectors have a very low dark current without significant degradation in the photoresponse, the signal contrast is greatly improved. The MISIM photodetector with the ALD-HfO2 blocking layer has an optimal signal contrast more than 500 times the contrast of the photodetector without a blocking layer at 15 V/μm.

Positron annihilation studies in the field induced depletion regions of metal-oxide-semiconductor structures

NASA Astrophysics Data System (ADS)

Asoka-Kumar, P.; Leung, T. C.; Lynn, K. G.; Nielsen, B.; Forcier, M. P.; Weinberg, Z. A.; Rubloff, G. W.

1992-06-01

The centroid shifts of positron annihilation spectra are reported from the depletion regions of metal-oxide-semiconductor (MOS) capacitors at room temperature and at 35 K. The centroid shift measurement can be explained using the variation of the electric field strength and depletion layer thickness as a function of the applied gate bias. An estimate for the relevant MOS quantities is obtained by fitting the centroid shift versus beam energy data with a steady-state diffusion-annihilation equation and a derivative-gaussian positron implantation profile. Inadequacy of the present analysis scheme is evident from the derived quantities and alternate methods are required for better predictions.

Increased Multilayer Fabrication and RF Characterization of a High-Density Stacked MIM Capacitor Based on Selective Etching

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tseng, VFG; Xie, HK

2014-07-01

This paper presents the fabrication and characterization of a high-density multilayer stacked metal-insulator-metal (MIM) capacitor based on a novel process of depositing the MIM multilayer on pillars followed by polishing and selective etching steps to form a stacked capacitor with merely three photolithography steps. In this paper, the pillars were made of glass to prevent substrate loss, whereas an oxide-nitride-oxide dielectric was employed for lower leakage, better voltage/frequency linearity, and better stress compensation. MIM capacitors with six dielectric layers were successfully fabricated, yielding capacitance density of 3.8 fF/mu m(2), maximum capacitance of 2.47 nF, and linear and quadratic voltage coefficientsmore » of capacitance below 21.2 ppm/V and 2.31 ppm/V-2. The impedance was measured from 40 Hz to 3 GHz, and characterized by an analytically derived equivalent circuit model to verify the radio frequency applicability. The multilayer stacking-induced plate resistance mismatch and its effect on the equivalent series resistance (ESR) and effective capacitance was also investigated, which can be counteracted by a corrected metal thickness design. A low ESR of 800 m Omega was achieved, whereas the self-resonance frequency was >760 MHz, successfully demonstrating the feasibility of this method to scale up capacitance densities for high-quality-factor, high-frequency, and large-value MIM capacitors.« less

Schottky Barrier Height Engineering for Electrical Contacts of Multilayered MoS2 Transistors with Reduction of Metal-Induced Gap States.

PubMed

Kim, Gwang-Sik; Kim, Seung-Hwan; Park, June; Han, Kyu Hyun; Kim, Jiyoung; Yu, Hyun-Yong

2018-06-06

The difficulty in Schottky barrier height (SBH) control arising from Fermi-level pinning (FLP) at electrical contacts is a bottleneck in designing high-performance nanoscale electronics and optoelectronics based on molybdenum disulfide (MoS 2 ). For electrical contacts of multilayered MoS 2 , the Fermi level on the metal side is strongly pinned near the conduction-band edge of MoS 2 , which makes most MoS 2 -channel field-effect transistors (MoS 2 FETs) exhibit n-type transfer characteristics regardless of their source/drain (S/D) contact metals. In this work, SBH engineering is conducted to control the SBH of electrical top contacts of multilayered MoS 2 by introducing a metal-interlayer-semiconductor (MIS) structure which induces the Fermi-level unpinning by a reduction of metal-induced gap states (MIGS). An ultrathin titanium dioxide (TiO 2 ) interlayer is inserted between the metal contact and the multilayered MoS 2 to alleviate FLP and tune the SBH at the S/D contacts of multilayered MoS 2 FETs. A significant alleviation of FLP is demonstrated as MIS structures with 1 nm thick TiO 2 interlayers are introduced into the S/D contacts. Consequently, the pinning factor ( S) increases from 0.02 for metal-semiconductor (MS) contacts to 0.24 for MIS contacts, and the controllable SBH range is widened from 37 meV (50-87 meV) to 344 meV (107-451 meV). Furthermore, the Fermi-level unpinning effect is reinforced as the interlayer becomes thicker. This work widens the scope for modifying electrical characteristics of contacts by providing a platform to control the SBH through a simple process as well as understanding of the FLP at the electrical top contacts of multilayered MoS 2 .

Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

NASA Technical Reports Server (NTRS)

Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Russell, Stephen D. (Inventor); Garcia, Graham A. (Inventor); Barfknecht, Andrew T. (Inventor); Clayton, Stanley R. (Inventor)

2000-01-01

A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

Electrically insulating films deposited on V-4%Cr-4%Ti by reactive CVD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, J.H.

1998-04-01

In the design of liquid-metal blankets for magnetic fusion reactors, corrosion resistance of structural materials and the magnetohydrodynamic forces and their influence on thermal hydraulics and corrosion are major concerns. Electrically insulating CaO films deposited on V-4%Cr-4%Ti exhibit high-ohmic insulator behavior even though a small amount of vanadium from the alloy become incorporated into the film. However, when vanadium concentration in the film is > 15 wt.%, the film becomes conductive. When the vanadium concentration is high in localized areas, a calcium vanadate phase that exhibits semiconductor behavior can form. The objective of this study is to evaluate electrically insulatingmore » films that were deposited on V-4%Cr-4%Ti by a reactive chemical vapor deposition (CVD) method. To this end, CaO and Ca-V-O coatings were produced on vanadium alloys by CVD and by a metallic-vapor process to investigate the electrical resistance of the coatings. The authors found that the Ca-V-O films exhibited insulator behavior when the ratio of calcium concentration to vanadium concentration R in the film > 0.9, and semiconductor or conductor behavior when R < 0.8. However, in some cases, semiconductor behavior was observed when CaO-coated samples with R > 0.98 were exposed in liquid lithium. Based on these studies, they conclude that semiconductor behavior occurs if a conductive calcium vanadate phase is present in localized regions in the CaO coating.« less

Prediction of weak topological insulators in layered semiconductors.

PubMed

Yan, Binghai; Müchler, Lukas; Felser, Claudia

2012-09-14

We report the discovery of weak topological insulators by ab initio calculations in a honeycomb lattice. We propose a structure with an odd number of layers in the primitive unit cell as a prerequisite for forming weak topological insulators. Here, the single-layered KHgSb is the most suitable candidate for its large bulk energy gap of 0.24 eV. Its side surface hosts metallic surface states, forming two anisotropic Dirac cones. Although the stacking of even-layered structures leads to trivial insulators, the structures can host a quantum spin Hall layer with a large bulk gap, if an additional single layer exists as a stacking fault in the crystal. The reported honeycomb compounds can serve as prototypes to aid in the finding of new weak topological insulators in layered small-gap semiconductors.

Absorption Voltages and Insulation Resistance in Ceramic Capacitors with Cracks

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander

2014-01-01

Time dependence of absorption voltages (V(sub abs)) in different types of low-voltage X5R and X7R ceramic capacitors was monitored for a maximum duration of hundred hours after polarization. To evaluate the effect of mechanical defects on V(sub abs)), cracks in the dielectric were introduced either mechanically or by thermal shock. The maximum absorption voltage, time to roll-off, and the rate of voltage decrease are shown to depend on the crack-related leakage currents and insulation resistance in the parts. A simple model that is based on the Dow equivalent circuit for capacitors with absorption has been developed to assess the insulation resistance of capacitors. Standard measurements of the insulation resistance, contrary to the measurements based on V(sub abs)), are not sensitive to the presence of mechanical defects and fail to reveal capacitors with cracks.

Printing Semiconductor-Insulator Polymer Bilayers for High-Performance Coplanar Field-Effect Transistors.

PubMed

Bu, Laju; Hu, Mengxing; Lu, Wanlong; Wang, Ziyu; Lu, Guanghao

2018-01-01

Source-semiconductor-drain coplanar transistors with an organic semiconductor layer located within the same plane of source/drain electrodes are attractive for next-generation electronics, because they could be used to reduce material consumption, minimize parasitic leakage current, avoid cross-talk among different devices, and simplify the fabrication process of circuits. Here, a one-step, drop-casting-like printing method to realize a coplanar transistor using a model semiconductor/insulator [poly(3-hexylthiophene) (P3HT)/polystyrene (PS)] blend is developed. By manipulating the solution dewetting dynamics on the metal electrode and SiO 2 dielectric, the solution within the channel region is selectively confined, and thus make the top surface of source/drain electrodes completely free of polymers. Subsequently, during solvent evaporation, vertical phase separation between P3HT and PS leads to a semiconductor-insulator bilayer structure, contributing to an improved transistor performance. Moreover, this coplanar transistor with semiconductor-insulator bilayer structure is an ideal system for injecting charges into the insulator via gate-stress, and the thus-formed PS electret layer acts as a "nonuniform floating gate" to tune the threshold voltage and effective mobility of the transistors. Effective field-effect mobility higher than 1 cm 2 V -1 s -1 with an on/off ratio > 10 7 is realized, and the performances are comparable to those of commercial amorphous silicon transistors. This coplanar transistor simplifies the fabrication process of corresponding circuits. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Influence of CO annealing in metal-oxide-semiconductor capacitors with SiO2 films thermally grown on Si and on SiC

NASA Astrophysics Data System (ADS)

Pitthan, E.; dos Reis, R.; Corrêa, S. A.; Schmeisser, D.; Boudinov, H. I.; Stedile, F. C.

2016-01-01

Understanding the influence of SiC reaction with CO, a by-product of SiC thermal oxidation, is a key point to elucidate the origin of electrical defects in SiC metal-oxide-semiconductor (MOS) devices. In this work, the effects on electrical, structural, and chemical properties of SiO2/Si and SiO2/SiC structures submitted to CO annealing were investigated. It was observed that long annealing times resulted in the incorporation of carbon from CO in the Si substrate, followed by deterioration of the SiO2/Si interface, and its crystallization as SiC. Besides, this incorporated carbon remained in the Si surface (previous SiO2/Si region) after removal of the silicon dioxide film by HF etching. In the SiC case, an even more defective surface region was observed due to the CO interaction. All MOS capacitors formed using both semiconductor materials presented higher leakage current and generation of positive effective charge after CO annealings. Such results suggest that the negative fixed charge, typically observed in SiO2/SiC structures, is not originated from the interaction of the CO by-product, formed during SiC oxidation, with the SiO2/SiC interfacial region.

A comprehensive study of charge trapping in organic field-effect devices with promising semiconductors and different contact metals by displacement current measurements

NASA Astrophysics Data System (ADS)

Bisoyi, Sibani; Rödel, Reinhold; Zschieschang, Ute; Kang, Myeong Jin; Takimiya, Kazuo; Klauk, Hagen; Tiwari, Shree Prakash

2016-02-01

A systematic and comprehensive study on the charge-carrier injection and trapping behavior was performed using displacement current measurements in long-channel capacitors based on four promising small-molecule organic semiconductors (pentacene, DNTT, C10-DNTT and DPh-DNTT). In thin-film transistors, these semiconductors showed charge-carrier mobilities ranging from 1.0 to 7.8 cm2 V-1 s-1. The number of charges injected into and extracted from the semiconductor and the density of charges trapped in the device during each measurement were calculated from the displacement current characteristics and it was found that the density of trapped charges is very similar in all devices and of the order 1012 cm-2, despite the fact that the four semiconductors show significantly different charge-carrier mobilities. The choice of the contact metal (Au, Ag, Cu, Pd) was also found to have no significant effect on the trapping behavior.

Spark gap device for precise switching

DOEpatents

Boettcher, Gordon E.

1984-01-01

A spark gap device for precise switching of an energy storage capacitor into an exploding bridge wire load is disclosed. Niobium electrodes having a melting point of 2,415 degrees centrigrade are spaced apart by an insulating cylinder to define a spark gap. The electrodes are supported by conductive end caps which, together with the insulating cylinder, form a hermetically sealed chamber filled with an inert, ionizable gas, such as pure xenon. A quantity of solid radioactive carbon-14 within the chamber adjacent the spark gap serves as a radiation stabilizer. The sides of the electrodes and the inner wall of the insulating cylinder are spaced apart a sufficient distance to prevent unwanted breakdown initiation. A conductive sleeve may envelop the outside of the insulating member from the midpoint of the spark gap to the cap adjacent the cathode. The outer metallic surfaces of the device may be coated with a hydrogen-impermeable coating to lengthen the shelf life and operating life of the device. The device breaks down at about 1,700 volts for input voltage rates up to 570 volts/millisecond and allows peak discharge currents of up to 3,000 amperes from a 0.3 microfarad energy storage capacitor for more than 1,000 operations.

A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

DTIC Science & Technology

2014-01-01

ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

Single-crystal-like GdNdO{sub x} thin films on silicon substrates by magnetron sputtering and high-temperature annealing for crystal seed layer application

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Ziwei; Xiao, Lei; Liang, Renrong, E-mail: wang-j@tsinghua.edu.cn, E-mail: liangrr@tsinghua.edu.cn

2016-06-15

Single-crystal-like rare earth oxide thin films on silicon (Si) substrates were fabricated by magnetron sputtering and high-temperature annealing processes. A 30-nm-thick high-quality GdNdO{sub x} (GNO) film was deposited using a high-temperature sputtering process at 500°C. A Gd{sub 2}O{sub 3} and Nd{sub 2}O{sub 3} mixture was used as the sputtering target, in which the proportions of Gd{sub 2}O{sub 3} and Nd{sub 2}O{sub 3} were controlled to make the GNO’s lattice parameter match that of the Si substrate. To further improve the quality of the GNO film, a post-deposition annealing process was performed at a temperature of 1000°C. The GNO films exhibitedmore » a strong preferred orientation on the Si substrate. In addition, an Al/GNO/Si capacitor was fabricated to evaluate the dielectric constant and leakage current of the GNO films. It was determined that the single-crystal-like GNO films on the Si substrates have potential for use as an insulator layer for semiconductor-on-insulator and semiconductor/insulator multilayer applications.« less

Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer

NASA Astrophysics Data System (ADS)

Ji, F.; Xu, J. P.; Liu, J. G.; Li, C. X.; Lai, P. T.

2011-05-01

TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N2 to suppress the growth of unstable GeOx at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3×1011 cm-2 eV), small gate leakage current (8.6×10-4 A cm-2 at Vg-Vfb=1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet-N2 anneal can significantly suppress the growth of unstable low-k GeOx.

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

NASA Astrophysics Data System (ADS)

Wang, L. S.; Xu, J. P.; Liu, L.; Lu, H. H.; Lai, P. T.; Tang, W. M.

2015-03-01

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm-2 eV-1 at midgap), smaller gate leakage current (9.5 × 10-5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

High quality HfO{sub 2}/p-GaSb(001) metal-oxide-semiconductor capacitors with 0.8 nm equivalent oxide thickness

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, Michael; Datta, Suman, E-mail: sdatta@engr.psu.edu; Bruce Rayner, G.

2014-12-01

We investigate in-situ cleaning of GaSb surfaces and its effect on the electrical performance of p-type GaSb metal-oxide-semiconductor capacitor (MOSCAP) using a remote hydrogen plasma. Ultrathin HfO{sub 2} films grown by atomic layer deposition were used as a high permittivity gate dielectric. Compared to conventional ex-situ chemical cleaning methods, the in-situ GaSb surface treatment resulted in a drastic improvement in the impedance characteristics of the MOSCAPs, directly evidencing a much lower interface trap density and enhanced Fermi level movement efficiency. We demonstrate that by using a combination of ex-situ and in-situ surface cleaning steps, aggressively scaled HfO{sub 2}/p-GaSb MOSCAP structuresmore » with a low equivalent oxide thickness of 0.8 nm and efficient gate modulation of the surface potential are achieved, allowing to push the Fermi level far away from the valence band edge high up into the band gap of GaSb.« less

Measurement of n-type Dry Thermally Oxidized 6H-SiC Metal-oxide Semiconductor Diodes by Quasistatic and High-Frequency Capacitance Versus Voltage and Capacitance Transient Techniques

NASA Technical Reports Server (NTRS)

Neudeck, P.; Kang, S.; Petit, J.; Tabib-Azar, M.

1994-01-01

Dry-oxidized n-type 6H-SiC metal-oxide-semiconductor capacitors are investigated using quasistatic capacitance versus voltage (C-V), high-frequency C-V, and pulsed high-frequency capacitance transient (C-t) analysis over the temperature range from 297 to 573 K. The quasistatic C - V characteristics presented are the first reported for 6H-SiC MOS capacitors, and exhibit startling nonidealities due to nonequilibrium conditions that arise from the fact that the recombination/generation process in 6H-SiC is extraordinarily slow even at the highest measurement temperature employed. The high-frequency dark C-V characteristics all showed deep depletion with no observable hysteresis. The recovery of the high-frequency capacitance from deep depletion to inversion was used to characterize the minority-carrier generation process as a function of temperature. Zerbst analysis conducted on the resulting C-t transients, which were longer than 1000 s at 573 K, showed a generation lifetime thermal activation energy of 0.49 eV.

Ion-sculpting of nanopores in amorphous metals, semiconductors, and insulators

DOE Office of Scientific and Technical Information (OSTI.GOV)

George, H. Bola; Madi, Charbel S.; Aziz, Michael J.

2010-06-28

We report the closure of nanopores to single-digit nanometer dimensions by ion sculpting in a range of amorphous materials including insulators (SiO{sub 2} and SiN), semiconductors (a-Si), and metallic glasses (Pd{sub 80}Si{sub 20})--the building blocks of a single-digit nanometer electronic device. Ion irradiation of nanopores in crystalline materials (Pt and Ag) does not cause nanopore closure. Ion irradiation of c-Si pores below 100 deg. C and above 600 deg. C, straddling the amorphous-crystalline dynamic transition temperature, yields closure at the lower temperature but no mass transport at the higher temperature. Ion beam nanosculpting appears to be restricted to materials thatmore » either are or become amorphous during ion irradiation.« less

Planar heterostructures of single-layer transition metal dichalcogenides: Composite structures, Schottky junctions, tunneling barriers, and half metals

NASA Astrophysics Data System (ADS)

Aras, Mehmet; Kılıç, ćetin; Ciraci, S.

2017-02-01

Planar composite structures formed from the stripes of transition metal dichalcogenides joined commensurately along their zigzag or armchair edges can attain different states in a two-dimensional (2D), single-layer, such as a half metal, 2D or one-dimensional (1D) nonmagnetic metal and semiconductor. Widening of stripes induces metal-insulator transition through the confinements of electronic states to adjacent stripes, that results in the metal-semiconductor junction with a well-defined band lineup. Linear bending of the band edges of the semiconductor to form a Schottky barrier at the boundary between the metal and semiconductor is revealed. Unexpectedly, strictly 1D metallic states develop in a 2D system along the boundaries between stripes, which pins the Fermi level. Through the δ doping of a narrow metallic stripe one attains a nanowire in the 2D semiconducting sheet or narrow band semiconductor. A diverse combination of constituent stripes in either periodically repeating or finite-size heterostructures can acquire critical fundamental features and offer device capacities, such as Schottky junctions, nanocapacitors, resonant tunneling double barriers, and spin valves. These predictions are obtained from first-principles calculations performed in the framework of density functional theory.

Nonstoichiometric Solution-Processed BaTiO₃ Film for Gate Insulator Applications.

PubMed

Lau, Joyce; Kim, Sangsub; Kim, Hyunki; Koo, Kwangjun; Lee, Jaeseob; Kim, Sangsoo; Choi, Byoungdeog

2018-09-01

Solution processed barium titanate (BTO) was used to fabricate an Al/BaTiO3/p-Si metal-insulator-semiconductor (MIS) structure, which was used as a gate insulator. Changes in the electrical characteristics of the film were investigated as a function of the film thickness and post deposition annealing conditions. Our results showed that a thickness of 5 layers and an annealing temperature of 650 °C produced the highest electrical performance. BaxTi1-xO3 was altered at x = 0.10, 0.30, 0.50, 0.70, 0.90, and 1.0 to investigate changes in the electrical properties as a function of composition. The highest dielectric constant of 87 was obtained for x = 0.10, while the leakage current density was suppressed as Ba content increased. The lowest leakage current density was 1.34×10-10 A/cm2, which was observed at x = 0.90. The leakage current was related to the resistivity of the film, the interface states, and grain densification. Space charge limited current (SCLC) was the dominant leakage mechanism in BTO films based on leakage current analysis. Although a Ba content of x = 0.90 had the highest trap density, the traps were mainly composed of Ti-vacancies, which acted as strong electron traps and affected the film resistivity. A secondary phase, Ba2TiO4, which was observed in cases of excess Ba, acted as a grain refiner and provided faster densification of the film during the thermal process. The absence of a secondary phase in BaO (x = 1.0) led to the formation of many interface states and degradation in the electrical properties. Overall, the insulator properties of BTO were improved when the composition ratio was x = 0.90.

Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies

DOEpatents

Blewer, Robert S.; Gullinger, Terry R.; Kelly, Michael J.; Tsao, Sylvia S.

1991-01-01

A method of forming a multiple level porous silicon substrate for semiconductor integrated circuits including anodizing non-porous silicon layers of a multi-layer silicon substrate to form multiple levels of porous silicon. At least one porous silicon layer is then oxidized to form an insulating layer and at least one other layer of porous silicon beneath the insulating layer is metallized to form a buried conductive layer. Preferably the insulating layer and conductive layer are separated by an anodization barrier formed of non-porous silicon. By etching through the anodization barrier and subsequently forming a metallized conductive layer, a fully or partially insulated buried conductor may be fabricated under single crystal silicon.

Novel growth techniques of group-IV based semiconductors on insulator for next-generation electronics

NASA Astrophysics Data System (ADS)

Miyao, Masanobu; Sadoh, Taizoh

2017-05-01

Recent progress in the crystal growth of group-IV-based semiconductor-on-insulators is reviewed from physical and technological viewpoints. Liquid-phase growth based on SiGe-mixing-triggered rapid-melting growth enables formation of hybrid (100) (110) (111)-orientation Ge-on-insulator (GOI) structures, which show defect-free GOI with very high carrier mobility (˜1040 cm2 V-1 s-1). Additionally, SiGe mixed-crystals with laterally uniform composition were obtained by eliminating segregation phenomena during the melt-back process. Low-temperature solid-phase growth has been explored by combining this process with ion-beam irradiation, additional doping of group-IV elements, metal induced lateral crystallization with/without electric field, and metal-induced layer exchange crystallization. These efforts have enabled crystal growth on insulators below 400 °C, achieving high carrier mobility (160-320 cm2 V-1 s-1). Moreover, orientation-controlled SiGe and Ge films on insulators have been obtained below the softening temperatures of conventional plastic films (˜300 °C). Detailed characterization provides an understanding of physical phenomena behind these crystal growth techniques. Applying these methods when fabricating next-generation electronics is also discussed.

Highly-Sensitive Thin Film THz Detector Based on Edge Metal-Semiconductor-Metal Junction.

PubMed

Jeon, Youngeun; Jung, Sungchul; Jin, Hanbyul; Mo, Kyuhyung; Kim, Kyung Rok; Park, Wook-Ki; Han, Seong-Tae; Park, Kibog

2017-12-04

Terahertz (THz) detectors have been extensively studied for various applications such as security, wireless communication, and medical imaging. In case of metal-insulator-metal (MIM) tunnel junction THz detector, a small junction area is desirable because the detector response time can be shortened by reducing it. An edge metal-semiconductor-metal (EMSM) junction has been developed with a small junction area controlled precisely by the thicknesses of metal and semiconductor films. The voltage response of the EMSM THz detector shows the clear dependence on the polarization angle of incident THz wave and the responsivity is found to be very high (~2,169 V/W) at 0.4 THz without any antenna and signal amplifier. The EMSM junction structure can be a new and efficient way of fabricating the nonlinear device THz detector with high cut-off frequency relying on extremely small junction area.

Drain current enhancement induced by hole injection from gate of 600-V-class normally off gate injection transistor under high temperature conditions up to 200 °C

NASA Astrophysics Data System (ADS)

Ishii, Hajime; Ueno, Hiroaki; Ueda, Tetsuzo; Endoh, Tetsuo

2018-06-01

In this paper, the current–voltage (I–V) characteristics of a 600-V-class normally off GaN gate injection transistor (GIT) from 25 to 200 °C are analyzed, and it is revealed that the drain current of the GIT increases during high-temperature operation. It is found that the maximum drain current (I dmax) of the GIT is 86% higher than that of a conventional 600-V-class normally off GaN metal insulator semiconductor hetero-FET (MIS-HFET) at 150 °C, whereas the GIT obtains 56% I dmax even at 200 °C. Moreover, the mechanism of the drain current increase of the GIT is clarified by examining the relationship between the temperature dependence of the I–V characteristics of the GIT and the gate hole injection effect determined from the shift of the second transconductance (g m) peak of the g m–V g characteristic. From the above, the GIT is a promising device with enough drivability for future power switching applications even under high-temperature conditions.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gelinck, G. H., E-mail: Gerwin.Gelinck@tno.nl; Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven; Breemen, A. J. J. M. van

Ferroelectric polarization switching of poly(vinylidene difluoride-trifluoroethylene) is investigated in different thin-film device structures, ranging from simple capacitors to dual-gate thin-film transistors (TFT). Indium gallium zinc oxide, a high mobility amorphous oxide material, is used as semiconductor. We find that the ferroelectric can be polarized in both directions in the metal-ferroelectric-semiconductor (MFS) structure and in the dual-gate TFT under certain biasing conditions, but not in the single-gate thin-film transistors. These results disprove the common belief that MFS structures serve as a good model system for ferroelectric polarization switching in thin-film transistors.

Trap density of GeNx/Ge interface fabricated by electron-cyclotron-resonance plasma nitridation

NASA Astrophysics Data System (ADS)

Fukuda, Yukio; Otani, Yohei; Toyota, Hiroshi; Ono, Toshiro

2011-07-01

We have investigated GeNx/Ge interface properties using Si3N4(7 nm)/GeNx(2 nm)/Ge metal-insulator-semiconductor structures fabricated by the plasma nitridation of Ge substrates using an electron-cyclotron-resonance-generated nitrogen plasma. The interface trap density (Dit) measured by the conductance method is found to be distributed symmetrically in the Ge band gap with a minimum Dit value lower than 3 × 1011 cm-2eV-1 near the midgap. This result may lead to the development of processes for the fabrication of p- and n-Ge Schottky-barrier (SB) source/drain metal-insulator-semiconductor field-effect transistors using chemically and thermally robust GeNx dielectrics as interlayers for SB source/drain contacts and high-κ gate dielectrics.

Carbon kagome lattice and orbital-frustration-induced metal-insulator transition for optoelectronics.

PubMed

Chen, Yuanping; Sun, Y Y; Wang, H; West, D; Xie, Yuee; Zhong, J; Meunier, V; Cohen, Marvin L; Zhang, S B

2014-08-22

A three-dimensional elemental carbon kagome lattice, made of only fourfold-coordinated carbon atoms, is proposed based on first-principles calculations. Despite the existence of 60° bond angles in the triangle rings, widely perceived to be energetically unfavorable, the carbon kagome lattice is found to display exceptional stability comparable to that of C(60). The system allows us to study the effects of triangular frustration on the electronic properties of realistic solids, and it demonstrates a metal-insulator transition from that of graphene to a direct gap semiconductor in the visible blue region. By minimizing s-p orbital hybridization, which is an intrinsic property of carbon, not only the band edge states become nearly purely frustrated p states, but also the band structure is qualitatively different from any known bulk elemental semiconductors. For example, the optical properties are similar to those of direct-gap semiconductors GaN and ZnO, whereas the effective masses are comparable to or smaller than those of Si.

MOS Circuitry Would Detect Low-Energy Charged Particles

NASA Technical Reports Server (NTRS)

Sinha, Mahadeva; Wadsworth, Mark

2003-01-01

Metal oxide semiconductor (MOS) circuits for measuring spatially varying intensities of beams of low-energy charged particles have been developed. These circuits are intended especially for use in measuring fluxes of ions with spatial resolution along the focal planes of mass spectrometers. Unlike prior mass spectrometer focal-plane detectors, these MOS circuits would not be based on ion-induced generation of electrons, and photons; instead, they would be based on direct detection of the electric charges of the ions. Hence, there would be no need for microchannel plates (for ion-to-electron conversion), phosphors (for electron-to-photon conversion), and photodetectors (for final detection) -- components that degrade spatial resolution and contribute to complexity and size. The developmental circuits are based on linear arrays of charge-coupled devices (CCDs) with associated readout circuitry (see figure). They resemble linear CCD photodetector arrays, except that instead of a photodetector, each pixel contains a capacitive charge sensor. The capacitor in each sensor comprises two electrodes (typically made of aluminum) separated by a layer of insulating material. The exposed electrode captures ions and accumulates their electric charges during signal-integration periods.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawase, Kazumasa; Uehara, Yasushi; Teramoto, Akinobu

Silicon dioxide (SiO{sub 2}) films formed by chemical vapor deposition (CVD) were treated with oxygen radical oxidation using Ar/O{sub 2} plasma excited by microwave. The mass density depth profiles, carrier trap densities, and current-voltage characteristics of the radical-oxidized CVD-SiO{sub 2} films were investigated. The mass density depth profiles were estimated with x ray reflectivity measurement using synchrotron radiation of SPring-8. The carrier trap densities were estimated with x ray photoelectron spectroscopy time-dependent measurement. The mass densities of the radical-oxidized CVD-SiO{sub 2} films were increased near the SiO{sub 2} surface. The densities of the carrier trap centers in these films weremore » decreased. The leakage currents of the metal-oxide-semiconductor capacitors fabricated by using these films were reduced. It is probable that the insulation properties of the CVD-SiO{sub 2} film are improved by the increase in the mass density and the decrease in the carrier trap density caused by the restoration of the Si-O network with the radical oxidation.« less

Low-voltage operation of Si-based ferroelectric field effect transistors using organic ferroelectrics, poly(vinylidene fluoride-trifluoroethylene), as a gate dielectric

NASA Astrophysics Data System (ADS)

Miyata, Yusuke; Yoshimura, Takeshi; Ashida, Atsushi; Fujimura, Norifumi

2016-04-01

Si-based metal-ferroelectric-semiconductor (MFS) capacitors have been fabricated using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as a ferroelectric gate. The pinhole-free P(VDF-TrFE) thin films with high resistivity were able to be prepared by spin-coating directly onto hydrogen-terminated Si. The capacitance-voltage (C-V) characteristics of the ferroelectric gate field effect transistor (FeFET) using this MFS structure clearly show butterfly-shaped hysteresis originating from the ferroelectricity, indicating carrier modulation on the Si surface at gate voltages below 2 V. The drain current-gate voltage (I D-V G) characteristics also show counterclockwise hysteresis at gate voltages below 5 V. This is the first report on the low-voltage operation of a Si-based FeFET using P(VDF-TrFE) as a gate dielectric. This organic gate FeFET without any insulator layer at the ferroelectric/Si interface should be one of the promising devices for overcoming the critical issues of the FeFET, such as depolarization field and a decrease in the gate voltage.

Silicon device performance measurements to support temperature range enhancement

NASA Technical Reports Server (NTRS)

Bromstead, James; Weir, Bennett; Johnson, R. Wayne; Askew, Ray

1992-01-01

Testing of the metal oxide semiconductor (MOS)-controlled thyristor (MCT) has uncovered a failure mechanism at elevated temperature. The failure appears to be due to breakdown of the gate oxide. Further testing is underway to verify the failure mode. Higher current level inverters were built to demonstrate 200 C operation of the N-MOSFET's and insulated-gate-bipolar transistors (IGBT's) and for life testing. One MOSFET failed early in testing. The origin of this failure is being studied. No IGBT's have failed. A prototype 28-to-42 V converter was built and is being tested at room temperature. The control loop is being finalized. Temperature stable, high value (10 micro-F) capacitors appear to be the limiting factor in the design at this time. In this application, the efficiency will be lower for the IGBT version due to the large V sub(cesat) (3.5-4 V) compared to the input voltage of 28 V. The MOSFET version should have higher efficiency; however, the MOSFET does not appear to be as robust at 200 C. Both versions are built for comparison.

A novel technique to measure interface trap density in a GaAs MOS capacitor using time-varying magnetic fields

DOE Office of Scientific and Technical Information (OSTI.GOV)

Choudhury, Aditya N. Roy, E-mail: aditya@physics.iisc.ernet.in; Venkataraman, V.

Interface trap density (D{sub it}) in a GaAs metal-oxide-semiconductor (MOS) capacitor can be measured electrically by measuring its impedance, i.e. by exciting it with a small signal voltage source and measuring the resulting current through the circuit. We propose a new method of measuring D{sub it} where the MOS capacitor is subjected to a (time-varying) magnetic field instead, which produces an effect equivalent to a (time-varying) voltage drop across the sample. This happens because the electron chemical potential of GaAs changes with a change in an externally applied magnetic field (unlike that of the gate metal); this is not themore » voltage induced by Faraday’s law of electromagnetic induction. So, by measuring the current through the MOS, D{sub it} can be found similarly. Energy band diagrams and equivalent circuits of a MOS capacitor are drawn in the presence of a magnetic field, and analyzed. The way in which a magnetic field affects a MOS structure is shown to be fundamentally different compared to an electrical voltage source.« less

The effect of surface conditions on the work function of insulators and semiconductors

NASA Technical Reports Server (NTRS)

George, A.

1973-01-01

Ionization energies of organic semiconductors were determined using single crystals of the material. The theory of the method is essentially that of Millikan's oil drop experiment. The technique employed in the experiment is based on the electrostatic method of balancing a charged particle in an electric field against the force of gravity for different excitation energies above the threshold value, and from an estimate of the balancing voltages, read off the ionization energy from the intercept of the energy axis in a plot wavelength corresponding to the balancing potential for the incident radiation of wavelength. In the modified technique which is adopted in the present experimental investigation, a small single crystal is suspended by a fine quartz fiber between two vertical capacitor plates to which a suitable high voltage is applied.

Enhanced Performance of Gate-First p-Channel Metal-Insulator-Semiconductor Field-Effect Transistors with Polycrystalline Silicon/TiN/HfSiON Stacks Fabricated by Physical Vapor Deposition Based In situ Method

NASA Astrophysics Data System (ADS)

Kitano, Naomu; Horie, Shinya; Arimura, Hiroaki; Kawahara, Takaaki; Sakashita, Shinsuke; Nishida, Yukio; Yugami, Jiro; Minami, Takashi; Kosuda, Motomu; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2007-12-01

We demonstrated the use of an in situ metal/high-k fabrication method for improving the performance of metal-insulator-semiconductor field-effect transistors (MISFETs). Gate-first pMISFETs with polycrystalline silicon (poly-Si)/TiN/HfSiON stacks were fabricated by techniques based on low-damage physical vapor deposition, in which high-quality HfSiON dielectrics were formed by the interface reaction between an ultrathin metal-Hf layer (0.5 nm thick) and a SiO2 underlayer, and TiN electrodes were continuously deposited on the gate dielectrics without exposure to air. Gate-first pMISFETs with high carrier mobility and a low threshold voltage (Vth) were realized by reducing the carbon impurity in the gate stacks and improving the Vth stability against thermal treatment. As a result, we obtained superior current drivability (Ion = 350 μA/μm at Ioff = 200 pA/μm), which corresponds to a 13% improvement over that of conventional chemical vapor deposition-based metal/high-k devices.

Electrostatically assisted fabrication of silver-dielectric core/shell nanoparticles thin film capacitor with uniform metal nanoparticle distribution and controlled spacing.

PubMed

Li, Xue; Niitsoo, Olivia; Couzis, Alexander

2016-03-01

An electrostatically-assisted strategy for fabrication of thin film composite capacitors with controllable dielectric constant (k) has been developed. The capacitor is composed of metal-dielectric core/shell nanoparticle (silver/silica, Ag@SiO2) multilayer films, and a backfilling polymer. Compared with the simple metal particle-polymer mixtures where the metal nanoparticles (NP) are randomly dispersed in the polymer matrix, the metal volume fraction in our capacitor was significantly increased, owing to the densely packed NP multilayers formed by the electrostatically assisted assembly process. Moreover, the insulating layer of silica shell provides a potential barrier that reduces the tunneling current between neighboring Ag cores, endowing the core/shell nanocomposites with a stable and relatively high dielectric constant (k) and low dielectric loss (D). Our work also shows that the thickness of the SiO2 shell plays a dominant role in controlling the dielectric properties of the nanocomposites. Control over metal NP separation distance was realized not only by variation the shell thickness of the core/shell NPs but also by introducing a high k nanoparticle, barium strontium titanate (BST) of relatively smaller size (∼8nm) compared to 80-160nm of the core/shell Ag@SiO2 NPs. The BST assemble between the Ag@SiO2 and fill the void space between the closely packed core/shell NPs leading to significant enhancement of the dielectric constant. This electrostatically assisted assembly method is promising for generating multilayer films of a large variety of NPs over large areas at low cost. Copyright © 2015 Elsevier Inc. All rights reserved.

Spark gap device for precise switching

DOEpatents

Boettcher, G.E.

1984-10-02

A spark gap device for precise switching of an energy storage capacitor into an exploding bridge wire load is disclosed. Niobium electrodes having a melting point of 2,415 degrees centigrade are spaced apart by an insulating cylinder to define a spark gap. The electrodes are supported by conductive end caps which, together with the insulating cylinder, form a hermetically sealed chamber filled with an inert, ionizable gas, such as pure xenon. A quantity of solid radioactive carbon-14 within the chamber adjacent the spark gap serves as a radiation stabilizer. The sides of the electrodes and the inner wall of the insulating cylinder are spaced apart a sufficient distance to prevent unwanted breakdown initiation. A conductive sleeve may envelop the outside of the insulating member from the midpoint of the spark gap to the cap adjacent the cathode. The outer metallic surfaces of the device may be coated with a hydrogen-impermeable coating to lengthen the shelf life and operating life of the device. The device breaks down at about 1,700 volts for input voltage rates up to 570 volts/millisecond and allows peak discharge currents of up to 3,000 amperes from a 0.3 microfarad energy storage capacitor for more than 1,000 operations. 3 figs.

Thermoelectricity in correlated narrow-gap semiconductors

NASA Astrophysics Data System (ADS)

Tomczak, Jan M.

2018-05-01

We review many-body effects, their microscopic origin, as well as their impact on thermoelectricity in correlated narrow-gap semiconductors. Members of this class—such as FeSi and FeSb2—display an unusual temperature dependence in various observables: insulating with large thermopowers at low temperatures, they turn bad metals at temperatures much smaller than the size of their gaps. This insulator-to-metal crossover is accompanied by spectral weight-transfers over large energies in the optical conductivity and by a gradual transition from activated to Curie–Weiss-like behaviour in the magnetic susceptibility. We show a retrospective of the understanding of these phenomena, discuss the relation to heavy-fermion Kondo insulators—such as Ce3Bi4Pt3 for which we present new results—and propose a general classification of paramagnetic insulators. From the latter, FeSi emerges as an orbital-selective Kondo insulator. Focussing on intermetallics such as silicides, antimonides, skutterudites, and Heusler compounds we showcase successes and challenges for the realistic simulation of transport properties in the presence of electronic correlations. Further, we explore new avenues in which electronic correlations may contribute to the improvement of thermoelectric performance.

Thin-film decoupling capacitors for multi-chip modules

NASA Astrophysics Data System (ADS)

Dimos, D.; Lockwood, S. J.; Schwartz, R. W.; Rogers, M. S.

Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multi-chip modules. These thin-film decoupling capacitors are intended to replace multi-layer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved high-speed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants ((var epsilon) greater than or equal to 900), low dielectric losses (tan(delta) = 0.01), excellent insulation resistances (rho greater than 10(exp 13) (Omega)-cm at 125 C), and good breakdown field strengths (E(sub B) = 900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 micron thick, which results in a large capacitance/area (8-9 nF/sq mm). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components.

Space-charge Effect on Electroresistance in Metal-Ferroelectric-Metal capacitors

PubMed Central

Tian, Bo Bo; Liu, Yang; Chen, Liu Fang; Wang, Jian Lu; Sun, Shuo; Shen, Hong; Sun, Jing Lan; Yuan, Guo Liang; Fusil, Stéphane; Garcia, Vincent; Dkhil, Brahim; Meng, Xiang Jian; Chu, Jun Hao

2015-01-01

Resistive switching through electroresistance (ER) effect in metal-ferroelectric-metal (MFM) capacitors has attracted increasing interest due to its potential applications as memories and logic devices. However, the detailed electronic mechanisms resulting in large ER when polarisation switching occurs in the ferroelectric barrier are still not well understood. Here, ER effect up to 1000% at room temperature is demonstrated in C-MOS compatible MFM nanocapacitors with a 8.8 nm-thick poly(vinylidene fluoride) (PVDF) homopolymer ferroelectric, which is very promising for silicon industry integration. Most remarkably, using theory developed for metal-semiconductor rectifying contacts, we derive an analytical expression for the variation of interfacial barrier heights due to space-charge effect that can interpret the observed ER response. We extend this space-charge model, related to the release of trapped charges by defects, to MFM structures made of ferroelectric oxides. This space-charge model provides a simple and straightforward tool to understand recent unusual reports. Finally, this work suggests that defect-engineering could be an original and efficient route for tuning the space-charge effect and thus the ER performances in future electronic devices. PMID:26670138

Space-charge Effect on Electroresistance in Metal-Ferroelectric-Metal capacitors

NASA Astrophysics Data System (ADS)

Tian, Bo Bo; Liu, Yang; Chen, Liu Fang; Wang, Jian Lu; Sun, Shuo; Shen, Hong; Sun, Jing Lan; Yuan, Guo Liang; Fusil, Stéphane; Garcia, Vincent; Dkhil, Brahim; Meng, Xiang Jian; Chu, Jun Hao

2015-12-01

Resistive switching through electroresistance (ER) effect in metal-ferroelectric-metal (MFM) capacitors has attracted increasing interest due to its potential applications as memories and logic devices. However, the detailed electronic mechanisms resulting in large ER when polarisation switching occurs in the ferroelectric barrier are still not well understood. Here, ER effect up to 1000% at room temperature is demonstrated in C-MOS compatible MFM nanocapacitors with a 8.8 nm-thick poly(vinylidene fluoride) (PVDF) homopolymer ferroelectric, which is very promising for silicon industry integration. Most remarkably, using theory developed for metal-semiconductor rectifying contacts, we derive an analytical expression for the variation of interfacial barrier heights due to space-charge effect that can interpret the observed ER response. We extend this space-charge model, related to the release of trapped charges by defects, to MFM structures made of ferroelectric oxides. This space-charge model provides a simple and straightforward tool to understand recent unusual reports. Finally, this work suggests that defect-engineering could be an original and efficient route for tuning the space-charge effect and thus the ER performances in future electronic devices.

A new constituent of electrostatic energy in semiconductors. An attempt to reformulate electrostatic energy in matter

NASA Astrophysics Data System (ADS)

Sallese, Jean-Michel

2016-06-01

The concept of electric energy is revisited in detail for semiconductors. We come to the conclusion that the main relationship used to calculate the energy related to the penetration of the electric field in semiconductors is missing a fundamental term. For instance, spatial derivate of the electrostatic energy using the traditional formula fails at giving the correct electrostatic force between semiconductor based capacitor plates, and reveals unambiguously the existence of an extra contribution to the standard electrostatic free energy. The additional term is found to be related to the generation of space charge regions which are predicted when combining electrostatics with semiconductor physics laws, such as for accumulation and inversion layers. On the contrary, no such energy is needed when relying on electrostatics only, as for instance when adopting the so-called full depletion approximation. The same holds for neutral and charged insulators that are still consistent with the customary definition, but these two examples are in fact singular cases. In semiconductors for instance, this additional energy can largely exceed the energy gained by the dipoles, thus becoming the dominant term. This unexpected result clearly asks for a generalization of electrostatic energy in matter in order to reconcile basic concepts of electrostatic energy in the framework of classical physics.

Charge dissipative dielectric for cryogenic devices

NASA Technical Reports Server (NTRS)

Cantor, Robin Harold (Inventor); Hall, John Addison (Inventor)

2007-01-01

A Superconducting Quantum Interference Device (SQUID) is disclosed comprising a pair of resistively shunted Josephson junctions connected in parallel within a superconducting loop and biased by an external direct current (dc) source. The SQUID comprises a semiconductor substrate and at least one superconducting layer. The metal layer(s) are separated by or covered with a semiconductor material layer having the properties of a conductor at room temperature and the properties of an insulator at operating temperatures (generally less than 100 Kelvins). The properties of the semiconductor material layer greatly reduces the risk of electrostatic discharge that can damage the device during normal handling of the device at room temperature, while still providing the insulating properties desired to allow normal functioning of the device at its operating temperature. A method of manufacturing the SQUID device is also disclosed.

Plasmon and exciton superconductivity mechanisms in layered structures

NASA Technical Reports Server (NTRS)

Gabovich, A. M.; Pashitskiy, E. A.; Uvarova, S. K.

1977-01-01

Plasmon and exciton superconductivity mechanisms are discussed. Superconductivity in a three layer metal semiconductor metal and insulator semimetal insulator sandwich structure was described in terms of the temperature dependent Green function of the longitudinal (Coulomb) field. The dependences of the superconducting transition temperature on structure parameters were obtained. In a semiconducting film, as a result of interactions of degenerate free carriers with excitons, superconductivity exists only in a certain range of parameter values, and the corresponding critical temperature is much lower than in the plasmon mechanism of superconductivity.

Device Performance and Reliability Improvements of AlGaBN/GaN/Si MOSFET

DTIC Science & Technology

2016-02-04

Metal insulator semiconductor AlGaN /GaN high electron mobility transistors (MISHEMTs) are promising for power device applications due to a lower leakage...current than the conventional Schottky AlGaN/GaN HEMTs.1–3 Among a large number of insulator materials, an Al2O3 dielectric layer, deposited by...atomic layer deposition (ALD), is often employed as the gate insulator because of a large band gap (and the resultant high conduction band offset on

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Electronic Materials and Processing: Proceedings of the First Electronic Materials and Processing Congress Held in Conjunction with the 1988 World Materials Congress, Chicago, Illinois, USA, 24-30 September 1988

DTIC Science & Technology

1988-01-01

usually be traced to a combination of new semiconductors one on top of the other, then concepts, materials, and device principles, the process is called...example, growth techniques. New combinations of compound semiconductors such as GaAs have an materials called heterostructures can be made intrinsically...of combinations of metals, have direct energy band gaps that facilitate semiconductor, and insulators. Quantum the efficient recombination of

Neutral beam and ICP etching of HKMG MOS capacitors: Observations and a plasma-induced damage model

NASA Astrophysics Data System (ADS)

Kuo, Tai-Chen; Shih, Tzu-Lang; Su, Yin-Hsien; Lee, Wen-Hsi; Current, Michael Ira; Samukawa, Seiji

2018-04-01

In this study, TiN/HfO2/Si metal-oxide-semiconductor (MOS) capacitors were etched by a neutral beam etching technique under two contrasting conditions. The configurations of neutral beam etching technique were specially designed to demonstrate a "damage-free" condition or to approximate "reactive-ion-etching-like" conditions to verify the effect of plasma-induced damage on electrical characteristics of MOS capacitors. The results show that by neutral beam etching (NBE), the interface state density (Dit) and the oxide trapped charge (Qot) were lower than routine plasma etching. Furthermore, the decrease in capacitor size does not lead to an increase in leakage current density, indicating less plasma induced side-wall damage. We present a plasma-induced gate stack damage model which we demonstrate by using these two different etching configurations. These results show that NBE is effective in preventing plasma-induced damage at the high-k/Si interface and on the high-k oxide sidewall and thus improve the electrical performance of the gate structure.

Metal-oxide-metal point contact junction detectors. [detection mechanism and mechanical stability

NASA Technical Reports Server (NTRS)

Baird, J.; Havemann, R. H.; Fults, R. D.

1973-01-01

The detection mechanism(s) and design of a mechanically stable metal-oxide-metal point contact junction detector are considered. A prototype for a mechanically stable device has been constructed and tested. A technique has been developed which accurately predicts microwave video detector and heterodyne mixer SIM (semiconductor-insulator-metal) diode performance from low dc frequency volt-ampere curves. The difference in contact potential between the two metals and geometrically induced rectification constitute the detection mechanisms.

Electrical characteristics and thermal stability of HfO{sub 2} metal-oxide-semiconductor capacitors fabricated on clean reconstructed GaSb surfaces

DOE Office of Scientific and Technical Information (OSTI.GOV)

Miyata, Noriyuki, E-mail: nori.miyata@aist.go.jp; Mori, Takahiro; Yasuda, Tetsuji

2014-06-09

HfO{sub 2}/GaSb interfaces fabricated by high-vacuum HfO{sub 2} deposition on clean reconstructed GaSb surfaces were examined to explore a thermally stable GaSb metal-oxide-semiconductor structure with low interface-state density (D{sub it}). Interface Sb-O bonds were electrically and thermally unstable, and post-metallization annealing at temperatures higher than 200 °C was required to stabilize the HfO{sub 2}/GaSb interfaces. However, the annealing led to large D{sub it} in the upper-half band gap. We propose that the decomposition products that are associated with elemental Sb atoms act as interface states, since a clear correlation between the D{sub it} and the Sb coverage on the initial GaSbmore » surfaces was observed.« less

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

NASA Technical Reports Server (NTRS)

Rafferty, Connor S.; Biegel, Bryan A.; Yu, Zhi-Ping; Ancona, Mario G.; Bude, J.; Dutton, Robert W.; Saini, Subhash (Technical Monitor)

1998-01-01

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Hysteresis in Lanthanide Aluminum Oxides Observed by Fast Pulse CV Measurement

PubMed Central

Zhao, Chun; Zhao, Ce Zhou; Lu, Qifeng; Yan, Xiaoyi; Taylor, Stephen; Chalker, Paul R.

2014-01-01

Oxide materials with large dielectric constants (so-called high-k dielectrics) have attracted much attention due to their potential use as gate dielectrics in Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). A novel characterization (pulse capacitance-voltage) method was proposed in detail. The pulse capacitance-voltage technique was employed to characterize oxide traps of high-k dielectrics based on the Metal Oxide Semiconductor (MOS) capacitor structure. The variation of flat-band voltages of the MOS structure was observed and discussed accordingly. Some interesting trapping/detrapping results related to the lanthanide aluminum oxide traps were identified for possible application in Flash memory technology. After understanding the trapping/detrapping mechanism of the high-k oxides, a solid foundation was prepared for further exploration into charge-trapping non-volatile memory in the future. PMID:28788225

Characterizing the Performance of the Wheel Electrostatic Spectrometer

NASA Technical Reports Server (NTRS)

Johansen, Michael R.; Mackey, P. J.; Holbert, E.; Calle, C. I.; Clements, J. S.

2013-01-01

Insulators need to be discharged after each wheel revolution. Sensor responses repeatable within one standard deviation in the noise of the signal. Insulators may not need to be cleaned after each revolution. Parent Technology- Mars Environmental Compatibility Assessment/Electrometer Electrostatic sensors with dissimilar cover insulators Protruding insulators tribocharge against regolith simulant Developed for use on the scoop for the 2001 Mars Odyssey lander Wheel Electrostatic Spectrometer Embedded electrostatic sensors in prototype Martian rover wheel If successful, this technology will enable constant electrostatic testing on Mars Air ionizing fan used to neutralize the surface charge on cover insulators . WES rolled on JSClA lunar simulant Control experiment -Static elimination not conducted between trials -Capacitor discharged after each experiment Charge neutralization experiment -Static elimination conducted between trials -Capacitor discharged after each experiment. Air ionizing fan used on insulators after each wheel revolution Capacitor discharged after each trial Care was taken to roll WES with same speed/pressure Error bars represent one standard deviation in the noise of e ach sensor

Electro-plasmonic 2 × 2 channel-routing switch arranged on a thin-Si-doped metal/insulator/semiconductor/metal structure.

PubMed

Moazzam, Mostafa Keshavarz; Kaatuzian, Hassan

2016-01-20

Plasmonics as a new field of chip-scale technology is the interesting substrate of this study to propose and numerically investigate a metal/insulator/semiconductor/metal (MISM)-structure 2×2 plasmonic routing switch. As a planar subwavelength arrangement, the presented design has two npn-doped side-coupled dual waveguides whose duty is to route the propagating surface plasmon polaritons through the device. Relying on the MISM structure, which has a MOS-like thin-film arrangement of typically 45 nm doped silicon covered by a layer of 8 nm thick HfO(2) gate insulator, the routing configuration is electrically addressed based on the carrier-induced plasma dispersion effects as an external electro-plasmonic switching control. Finite-element-method-conducted electromagnetic simulations are employed to evaluate the switch optical response at telecom wavelength of λ=1550  nm, due to which the balanced operation measure of extinction ratios larger than 10 dB and insertion losses of around -1.8  dB are obtained for both channels of CROSS and STRAIGHT. Compared with other photonic and plasmonic switching counterparts, this configuration, besides its potential for CMOS compatibility, can be utilized as a high-speed compact building block to sustain higher-speed, more miniaturized, and less consuming electro-optic routing/switching protocols toward complicated optical integrated circuits and systems.

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG in the form of PVD TaN was investigated along with high-k blocking dielectric. The material properties of TaN metal and high-k / low-k dielectric engineering were systematically studied. And the resulting memory structures exhibit excellent memory characteristics and scalability of the metal FG down to ˜1nm, which is promising in order to reduce the unwanted FG-FG interferences. In the later part of the study, the thermal stability of the combined stack was examined and various approaches to improve the stability and understand the cause of instability were explored. The performance of the high-k IPD metal FG memory structure was observed to degrade with higher annealing conditions and the deteriorated behavior was attributed to the leakage instability of the high-k /TaN capacitor. While the degradation is pronounced in both MIM and MIS capacitors, a higher leakage increment was seen in MIM, which was attributed to the higher degree of dielectric crystallization. In an attempt to improve the thermal stability, the trade-off in using amorphous interlayers to reduce the enhanced dielectric crystallization on metal was highlighted. Also, the effect of oxygen vacancies and grain growth on the dielectric leakage was studied through a multi-deposition-multi-anneal technique. Multi step deposition and annealing in a more electronegative ambient was observed to have a positive impact on the dielectric performance.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Song, Yongli; Wang, Xianjie; Sui, Yu

Here in this article, we investigated the dielectric properties of (In + Nb) co-doped rutile TiO 2 single crystal and polycrystalline ceramics. Both of them showed colossal, up to 10 4, dielectric permittivity at room temperature. The single crystal sample showed one dielectric relaxation process with a large dielectric loss. The voltage-dependence of dielectric permittivity and the impedance spectrum suggest that the high dielectric permittivity of single crystal originated from the surface barrier layer capacitor (SBLC). The impedance spectroscopy at different temperature confirmed that the (In+Nb) co-doped rutile TiO 2 polycrystalline ceramic had semiconductor grains and insulating grain boundaries, andmore » that the activation energies were calculated to be 0.052 eV and 0.35 eV for grain and grain boundary, respectively. The dielectric behavior and impedance spectrum of the polycrystalline ceramic sample indicated that the internal barrier layer capacitor (IBLC) mode made a major contribution to the high ceramic dielectric permittivity, instead of the electron-pinned defect-dipoles.« less

Opening of K+ channels by capacitive stimulation from silicon chip

NASA Astrophysics Data System (ADS)

Ulbrich, M. H.; Fromherz, P.

2005-10-01

The development of stable neuroelectronic systems requires a stimulation of nerve cells from semiconductor devices without electrochemical effects at the electrolyte/solid interface and without damage of the cell membrane. The interaction must rely on a reversible opening of voltage-gated ion channels by capacitive coupling. In a proof-of-principle experiment, we demonstrate that Kv1.3 potassium channels expressed in HEK293 cells can be opened from an electrolyte/oxide/silicon (EOS) capacitor. A sufficient strength of electrical coupling is achieved by insulating silicon with a thin film of TiO2 to achieve a high capacitance and by removing NaCl from the electrolyte to enhance the resistance of the cell-chip contact. When a decaying voltage ramp is applied to the EOS capacitor, an outward current through the attached cell membrane is observed that is specific for Kv1.3 channels. An open probability up to fifty percent is estimated by comparison with a numerical simulation of the cell-chip contact.

Radio Relays Improve Wireless Products

NASA Technical Reports Server (NTRS)

2009-01-01

Signal Hill, California-based XCOM Wireless Inc. developed radio frequency micromachine (RF MEMS) relays with a Phase II Small Business Innovation Research (SBIR) contract through NASA?s Jet Propulsion Laboratory. In order to improve satellite communication systems, XCOM produced wireless RF MEMS relays and tunable capacitors that use metal-to-metal contact and have the potential to outperform most semiconductor technologies while using less power. These relays are used in high-frequency test equipment and instrumentation, where increased speed can mean significant cost savings. Applications now also include mainstream wireless applications and greatly improved tactical radios.

Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

NASA Astrophysics Data System (ADS)

Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

2007-09-01

Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

The use of charge extraction by linearly increasing voltage in polar organic light-emitting diodes

NASA Astrophysics Data System (ADS)

Züfle, Simon; Altazin, Stéphane; Hofmann, Alexander; Jäger, Lars; Neukom, Martin T.; Schmidt, Tobias D.; Brütting, Wolfgang; Ruhstaller, Beat

2017-05-01

We demonstrate the application of the CELIV (charge carrier extraction by linearly increasing voltage) technique to bilayer organic light-emitting devices (OLEDs) in order to selectively determine the hole mobility in N,N0-bis(1-naphthyl)-N,N0-diphenyl-1,10-biphenyl-4,40-diamine (α-NPD). In the CELIV technique, mobile charges in the active layer are extracted by applying a negative voltage ramp, leading to a peak superimposed to the measured displacement current whose temporal position is related to the charge carrier mobility. In fully operating devices, however, bipolar carrier transport and recombination complicate the analysis of CELIV transients as well as the assignment of the extracted mobility value to one charge carrier species. This has motivated a new approach of fabricating dedicated metal-insulator-semiconductor (MIS) devices, where the extraction current contains signatures of only one charge carrier type. In this work, we show that the MIS-CELIV concept can be employed in bilayer polar OLEDs as well, which are easy to fabricate using most common electron transport layers (ETLs), like Tris-(8-hydroxyquinoline)aluminum (Alq3). Due to the macroscopic polarization of the ETL, holes are already injected into the hole transport layer below the built-in voltage and accumulate at the internal interface with the ETL. This way, by a standard CELIV experiment only holes will be extracted, allowing us to determine their mobility. The approach can be established as a powerful way of selectively measuring charge mobilities in new materials in a standard device configuration.

Power electronics cooling apparatus

DOEpatents

Sanger, Philip Albert; Lindberg, Frank A.; Garcen, Walter

2000-01-01

A semiconductor cooling arrangement wherein a semiconductor is affixed to a thermally and electrically conducting carrier such as by brazing. The coefficient of thermal expansion of the semiconductor and carrier are closely matched to one another so that during operation they will not be overstressed mechanically due to thermal cycling. Electrical connection is made to the semiconductor and carrier, and a porous metal heat exchanger is thermally connected to the carrier. The heat exchanger is positioned within an electrically insulating cooling assembly having cooling oil flowing therethrough. The arrangement is particularly well adapted for the cooling of high power switching elements in a power bridge.

Synthesis, interface (Au/M2Pc2/p-Si), electrochemical and electrocatalytic properties of novel ball-type phthalocyanines.

PubMed

Şengül, Abdurrahman; Doğan, H Zekeriya; Altındal, Ahmet; Özkaya, Ali Rıza; Salih, Bekir; Bekaroğlu, Özer

2012-07-07

The phthalodinitrile derivative (3) was prepared by the reaction of 4,4'-(octahydro-4,7-methano-5H-inden-5-ylidene)bisphenol (1) and 4-nitrophthalonitrile (2) with dry DMF as the solvent in the presence of the base K(2)CO(3) by the method of nucleophilic substitution of an activated nitro group in an aromatic ring. The template reaction of 3 with the corresponding metal salts gave the novel bi-nuclear ball-type metallophthalocyanines, MPcs {M = Co (4), Cu (5), Zn (6)}. Newly synthesized compounds were characterized by elemental analysis, UV-vis, FT-IR (ATR), MALDI-TOF mass and (1)H-NMR spectroscopy techniques. The electronic spectra exhibit an intense π→π* transition of characteristic Q and B bands of the Pc core. The dielectric properties and interface between the spin coated films of 4-6 and a p-type silicon substrate have been studied by fabricating metal-insulator-semiconductor capacitors. The results indicated that the frequency dependence of the dielectric permittivity, ε'(ω), exhibits non-Debye type relaxation for all the temperatures investigated. The ac conductivity results indicated that the conduction mechanism can be explained by a hopping model at low temperatures (<430 K) and a free band conduction mechanism at high temperatures (≥430 K). The density of interface state calculations on these novel compounds showed that the combination of Au/4/p-Si is a promising structure with a high dielectric constant and a low interface trap density suitable for metal-oxide-semiconductor devices. The electrochemical properties of the Pc complexes were examined by cyclic voltammetry, differential voltammetry and controlled potential coulometry on platinum in non-aqueous media. The complexes showed ring-based and/or metal-based mixed-valence behaviours as a result of the remarkable interaction between the two Pc rings and/or metal centres. The mixed-valence splitting values for the complexes suggested that the mixed valence species are considerably stable. The Vulcan XC-72(VC)/Nafion(Nf)/4 modified glassy carbon electrode showed much a higher catalytic performance towards oxygen reduction than those of VC/Nf/5 and VC/Nf/6 modified ones.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lutzer, B.; Simsek, S.; Zimmermann, C.

In order to improve the electrical behaviour of metal-insulator-metal capacitors with ZrO{sub 2} insulator grown by Atomic Layer Deposition, the influence of the insertion of interfacial Cr layers between Pt electrodes and the zirconia is investigated. An improvement of the α-voltage coefficient of capacitance as low as 567 ppm/V{sup 2} is achieved for a single layer of Cr while maintaining a high capacitance density of 10.7 fF/μm{sup 2} and a leakage current of less than 1.2 × 10{sup −8} A/cm{sup 2} at +1 V. The role of the interface is discussed by means of X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy showing themore » formation of Zr stabilized chromia oxide phase with a dielectric constant of 16.« less

Global Phase Diagram of a Three-Dimensional Dirty Topological Superconductor

NASA Astrophysics Data System (ADS)

Roy, Bitan; Alavirad, Yahya; Sau, Jay D.

2017-06-01

We investigate the phase diagram of a three-dimensional, time-reversal symmetric topological superconductor in the presence of charge impurities and random s -wave pairing. Combining complimentary field theoretic and numerical methods, we show that the quantum phase transition between two topologically distinct paired states (or thermal insulators), described by thermal Dirac semimetal, remains unaffected in the presence of sufficiently weak generic randomness. At stronger disorder, however, these two phases are separated by an intervening thermal metallic phase of diffusive Majorana fermions. We show that across the insulator-insulator and metal-insulator transitions, normalized thermal conductance displays single parameter scaling, allowing us to numerically extract the critical exponents across them. The pertinence of our study in strong spin-orbit coupled, three-dimensional doped narrow gap semiconductors, such as CuxBi2Se3 , is discussed.

Quantum Dots Based Rad-Hard Computing and Sensors

NASA Technical Reports Server (NTRS)

Fijany, A.; Klimeck, G.; Leon, R.; Qiu, Y.; Toomarian, N.

2001-01-01

Quantum Dots (QDs) are solid-state structures made of semiconductors or metals that confine a small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well-conducting region. Thus, they can be viewed as artificial atoms. They therefore represent the ultimate limit of the semiconductor device scaling. Additional information is contained in the original extended abstract.

Amorphous metallizations for high-temperature semiconductor device applications

NASA Technical Reports Server (NTRS)

Wiley, J. D.; Perepezko, J. H.; Nordman, J. E.; Kang-Jin, G.

1981-01-01

The initial results of work on a class of semiconductor metallizations which appear to hold promise as primary metallizations and diffusion barriers for high temperature device applications are presented. These metallizations consist of sputter-deposited films of high T sub g amorphous-metal alloys which (primarily because of the absence of grain boundaries) exhibit exceptionally good corrosion-resistance and low diffusion coefficients. Amorphous films of the alloys Ni-Nb, Ni-Mo, W-Si, and Mo-Si were deposited on Si, GaAs, GaP, and various insulating substrates. The films adhere extremely well to the substrates and remain amorphous during thermal cycling to at least 500 C. Rutherford backscattering and Auger electron spectroscopy measurements indicate atomic diffussivities in the 10 to the -19th power sq cm/S range at 450 C.

Origin of flatband voltage shift and unusual minority carrier generation in thermally grown GeO2/Ge metal-oxide-semiconductor devices

NASA Astrophysics Data System (ADS)

Hosoi, Takuji; Kutsuki, Katsuhiro; Okamoto, Gaku; Saito, Marina; Shimura, Takayoshi; Watanabe, Heiji

2009-05-01

Improvement in electrical properties of thermally grown GeO2/Ge metal-oxide-semiconductor (MOS) capacitors, such as significantly reduced flatband voltage (VFB) shift, small hysteresis, and minimized minority carrier response in capacitance-voltage (C-V) characteristics, has been demonstrated by in situ low temperature vacuum annealing prior to gate electrode deposition. Thermal desorption analysis has revealed that not only water but also hydrocarbons are easily infiltrated into GeO2 layers during air exposure and desorbed at around 300 °C, indicating that organic molecules within GeO2/Ge MOS structures are possible origins of electrical defects. The inversion capacitance, indicative of minority carrier generation, increases with air exposure time for Au/GeO2/Ge MOS capacitors, while maintaining an interface state density (Dit) of about a few 1011 cm-2 eV-1. Unusual increase in inversion capacitance was found to be suppressed by Al2O3 capping (Au/Al2O3/GeO2/Ge structures). This suggests that electrical defects induced outside the Au electrode by infiltrated molecules may enhance the minority carrier generation, and thus acting as a minority carrier source just like MOS field-effect transistors.

Electroactive Nanoporous Metal Oxides and Chalcogenides by Chemical Design

PubMed Central

2017-01-01

The archetypal silica- and aluminosilicate-based zeolite-type materials are renowned for wide-ranging applications in heterogeneous catalysis, gas-separation and ion-exchange. Their compositional space can be expanded to include nanoporous metal chalcogenides, exemplified by germanium and tin sulfides and selenides. By comparison with the properties of bulk metal dichalcogenides and their 2D derivatives, these open-framework analogues may be viewed as three-dimensional semiconductors filled with nanometer voids. Applications exist in a range of molecule size and shape discriminating devices. However, what is the electronic structure of nanoporous metal chalcogenides? Herein, materials modeling is used to describe the properties of a homologous series of nanoporous metal chalcogenides denoted np-MX2, where M = Si, Ge, Sn, Pb, and X = O, S, Se, Te, with Sodalite, LTA and aluminum chromium phosphate-1 structure types. Depending on the choice of metal and anion their properties can be tuned from insulators to semiconductors to metals with additional modification achieved through doping, solid solutions, and inclusion (with fullerene, quantum dots, and hole transport materials). These systems form the basis of a new branch of semiconductor nanochemistry in three dimensions. PMID:28572706

Direct cooled power electronics substrate

DOEpatents

Wiles, Randy H [Powell, TN; Wereszczak, Andrew A [Oak Ridge, TN; Ayers, Curtis W [Kingston, TN; Lowe, Kirk T [Knoxville, TN

2010-09-14

The disclosure describes directly cooling a three-dimensional, direct metallization (DM) layer in a power electronics device. To enable sufficient cooling, coolant flow channels are formed within the ceramic substrate. The direct metallization layer (typically copper) may be bonded to the ceramic substrate, and semiconductor chips (such as IGBT and diodes) may be soldered or sintered onto the direct metallization layer to form a power electronics module. Multiple modules may be attached to cooling headers that provide in-flow and out-flow of coolant through the channels in the ceramic substrate. The modules and cooling header assembly are preferably sized to fit inside the core of a toroidal shaped capacitor.

In-situ SiN{sub x}/InN structures for InN field-effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zervos, Ch., E-mail: hzervos@physics.uoc.gr; Georgakilas, A.; Department of Physics, University of Crete, P.O. Box 2208, GR-71003 Heraklion, Crete

Critical aspects of InN channel field-effect transistors (FETs) have been investigated. SiN{sub x} dielectric layers were deposited in-situ, in the molecular beam epitaxy system, on the surface of 2 nm InN layers grown on GaN (0001) buffer layers. Metal-insulator-semiconductor Ni/SiN{sub x}/InN capacitors were analyzed by capacitance-voltage (C-V) and current-voltage measurements and were used as gates in InN FET transistors (MISFETs). Comparison of the experimental C-V results with self-consistent Schrödinger-Poisson calculations indicates the presence of a positive charge at the SiN{sub x}/InN interface of Q{sub if} ≈ 4.4 – 4.8 × 10{sup 13 }cm{sup −2}, assuming complete InN strain relaxation. Operation of InN MISFETs was demonstrated, but their performancemore » was limited by a catastrophic breakdown at drain-source voltages above 2.5–3.0 V, the low electron mobility, and high series resistances of the structures.« less

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, Arthur W.; Ellingboe, Albert R.

1998-01-01

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18-0.35 mm or less.

Helicon wave excitation to produce energetic electrons for manufacturing semiconductors

DOEpatents

Molvik, A.W.; Ellingboe, A.R.

1998-10-20

A helicon plasma source is controlled by varying the axial magnetic field or rf power controlling the formation of the helicon wave. An energetic electron current is carried on the wave when the magnetic field is 90 G; but there is minimal energetic electron current when the magnetic field is 100 G in one particular plasma source. Similar performance can be expected from other helicon sources by properly adjusting the magnetic field and power to the particular geometry. This control for adjusting the production of energetic electrons can be used in the semiconductor and thin-film manufacture process. By applying energetic electrons to the insulator layer, such as silicon oxide, etching ions are attracted to the insulator layer and bombard the insulator layer at higher energy than areas that have not accumulated the energetic electrons. Thus, silicon and metal layers, which can neutralize the energetic electron currents will etch at a slower or non-existent rate. This procedure is especially advantageous in the multilayer semiconductor manufacturing because trenches can be formed that are in the range of 0.18--0.35 mm or less. 16 figs.

Nanostructure multilayer dielectric materials for capacitors and insulators

DOEpatents

Barbee, Jr., Troy W.; Johnson, Gary W.

1998-04-21

A capacitor is formed of at least two metal conductors having a multilayer dielectric and opposite dielectric-conductor interface layers in between. The multilayer dielectric includes many alternating layers of amorphous zirconium oxide (ZrO.sub.2) and alumina (Al.sub.2 O.sub.3). The dielectric-conductor interface layers are engineered for increased voltage breakdown and extended service life. The local interfacial work function is increased to reduce charge injection and thus increase breakdown voltage. Proper material choices can prevent electrochemical reactions and diffusion between the conductor and dielectric. Physical vapor deposition is used to deposit the zirconium oxide (ZrO.sub.2) and alumina (Al.sub.2 O.sub.3) in alternating layers to form a nano-laminate.

Unexpected significant increase in bulk conductivity of a dielectric arising from charge injection

NASA Astrophysics Data System (ADS)

Wang, Jian-Jun; Bayer, Thorsten J. M.; Wang, Rui; Carter, Jared J.; Randall, Clive A.; Chen, Long-Qing

2017-06-01

Charge injection is a common phenomenon in heterostructures or devices containing metal-insulator interfaces under a voltage bias ranging from dielectric capacitors to electroluminescent and lasing devices. It is generally believed that charge injection only significantly increases the conductivity near the interfacial region or in capacitors with very thin dielectric layers. In this work, the impact of charge injection on bulk conductivity of a 0.5 mm thick Fe-doped SrTiO3 single crystal is investigated with a combination of experimental impedance measurements and computational modelling. It is found that the interfacial charge injection may increase the predicted bulk conductivity of a dielectric by more than one order of magnitude as a consequence of Schottky barrier height lowering.

Nanostructure multilayer dielectric materials for capacitors and insulators

DOEpatents

Barbee, T.W. Jr.; Johnson, G.W.

1998-04-21

A capacitor is formed of at least two metal conductors having a multilayer dielectric and opposite dielectric-conductor interface layers in between. The multilayer dielectric includes many alternating layers of amorphous zirconium oxide (ZrO{sub 2}) and alumina (Al{sub 2}O{sub 3}). The dielectric-conductor interface layers are engineered for increased voltage breakdown and extended service life. The local interfacial work function is increased to reduce charge injection and thus increase breakdown voltage. Proper material choices can prevent electrochemical reactions and diffusion between the conductor and dielectric. Physical vapor deposition is used to deposit the zirconium oxide (ZrO{sub 2}) and alumina (Al{sub 2}O{sub 3}) in alternating layers to form a nano-laminate. 1 fig.

Andreev Reflection in an s-Type Superconductor Proximized 3D Topological Insulator.

PubMed

Tikhonov, E S; Shovkun, D V; Snelder, M; Stehno, M P; Huang, Y; Golden, M S; Golubov, A A; Brinkman, A; Khrapai, V S

2016-09-30

We investigate transport and shot noise in lateral normal-metal-3D topological-insulator-superconductor contacts, where the 3D topological insulator (TI) is based on Bi. In the normal state, the devices are in the elastic diffusive transport regime, as demonstrated by a nearly universal value of the shot noise Fano factor F_{N}≈1/3 in magnetic field and in a reference normal-metal contact. In the absence of magnetic field, we identify the Andreev reflection (AR) regime, which gives rise to the effective charge doubling in shot noise measurements. Surprisingly, the Fano factor F_{AR}≈0.22±0.02 is considerably reduced in the AR regime compared to F_{N}, in contrast to previous AR experiments in normal metals and semiconductors. We suggest that this effect is related to a finite thermal conduction of the proximized, superconducting TI owing to a residual density of states at low energies.

Characterization of 720 and 940 MHz Oscillators with Chip Antenna for Wireless Sensors from Room Temperature to 200 and 250 deg C

NASA Technical Reports Server (NTRS)

Scardelletti, Maximilian C.; Ponchak, George E.

2011-01-01

Oscillators that operate at 720 and 940 MHz and characterized over a temperature range of 25 C to 200 C and 250 C, respectively, are presented. The oscillators are designed on alumina substrates with typical integrated circuit fabrication techniques. Cree SiC MESFETs, thin film metal-insulator-metal capacitors and spiral inductors, and Johanson miniature chip antennas make-up the circuits. The output power and phase noise are presented as a function of temperature and frequency. Index Terms MESFETS, chip antennas, oscillators SiC alumina.

Deposition of thin insulation layers from the gas phase

NASA Technical Reports Server (NTRS)

Behn, R.; Hagedorn, H.; Kammermaier, J.; Kobale, M.; Packonik, H.; Ristow, D.; Seebacher, G.

1981-01-01

The continuous deposition of thin organic dielectric films on metallized carrier foils by glow discharge in monomeric gases is described. Depending on the applied monomers, the films had a dissipation factor of .001 to .003 (1 kHz), a relative permittivity of 2.3 to 2.5 and a resistivity of about 10 to the 17th power omega cm. Additionally, they proved to have a high mechanical homogeneity. Self-healing rolled capacitors with a very high capacitance per volume and of consistently high quality were fabricated from the metallized carrier foils covered with the dielectric film.

Ceramic capacitor insulation resistance failures accelerated by low voltage

NASA Technical Reports Server (NTRS)

Brennan, T. F.

1978-01-01

Ceramic capacitors failed insulation resistance testing at less than one-tenth their rated voltage. Many failures recovered as the voltage was increased. Comprehensive failure analysis techniques, some of which are unprecedented, were used to examine these failures. It was determined that there was more than one failure mechanism, and the results indicate a need for special additional screening.

Characteristics of Superjunction Lateral-Double-Diffusion Metal Oxide Semiconductor Field Effect Transistor and Degradation after Electrical Stress

NASA Astrophysics Data System (ADS)

Lin, Jyh‑Ling; Lin, Ming‑Jang; Lin, Li‑Jheng

2006-04-01

The superjunction lateral double diffusion metal oxide semiconductor field effect has recently received considerable attention. Introducing heavily doped p-type strips to the n-type drift region increases the horizontal depletion capability. Consequently, the doping concentration of the drift region is higher and the conduction resistance is lower than those of conventional lateral-double-diffusion metal oxide semiconductor field effect transistors (LDMOSFETs). These characteristics may increase breakdown voltage (\\mathit{BV}) and reduce specific on-resistance (Ron,sp). In this study, we focus on the electrical characteristics of conventional LDMOSFETs on silicon bulk, silicon-on-insulator (SOI) LDMOSFETs and superjunction LDMOSFETs after bias stress. Additionally, the \\mathit{BV} and Ron,sp of superjunction LDMOSFETs with different N/P drift region widths and different dosages are discussed. Simulation tools, including two-dimensional (2-D) TSPREM-4/MEDICI and three-dimensional (3-D) DAVINCI, were employed to determine the device characteristics.

Fabrication of Hydrogenated Diamond Metal-Insulator-Semiconductor Field-Effect Transistors.

PubMed

Liu, Jiangwei; Koide, Yasuo

2017-01-01

Diamond is regarded as a promising material for fabrication of high-power and high-frequency electronic devices due to its remarkable intrinsic properties, such as wide band gap energy, high carrier mobility, and high breakdown field. Meanwhile, since diamond has good biocompatibility, long-term durability, good chemical inertness, and a large electron-chemical potential window, it is a suitable candidate for the fabrication of biosensors. Here, we demonstrate the fabrication of hydrogenated diamond (H-diamond) based metal-insulator-semiconductor field-effect transistors (MISFETs). The fabrication is based on the combination of laser lithography, dry-etching, atomic layer deposition (ALD), sputtering deposition (SD), electrode evaporation, and lift-off techniques. The gate insulator is high-k HfO 2 with a SD/ALD bilayer structure. The thin ALD-HfO 2 film (4.0 nm) acts as a buffer layer to prevent the hydrogen surface of the H-diamond from plasma discharge damage during the SD-HfO 2 deposition. The growth of H-diamond epitaxial layer, fabrication of H-diamond MISFETs, and electrical property measurements for the MISFETs is demonstrated. This chapter explains the fabrication of H-diamond FET based biosensors.

Thin film three-dimensional topological insulator metal-oxide-semiconductor field-effect-transistors: A candidate for sub-10 nm devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Akhavan, N. D., E-mail: nima.dehdashti@uwa.edu.au; Jolley, G.; Umana-Membreno, G. A.

2014-08-28

Three-dimensional (3D) topological insulators (TI) are a new state of quantum matter in which surface states reside in the bulk insulating energy bandgap and are protected by time-reversal symmetry. It is possible to create an energy bandgap as a consequence of the interaction between the conduction band and valence band surface states from the opposite surfaces of a TI thin film, and the width of the bandgap can be controlled by the thin film thickness. The formation of an energy bandgap raises the possibility of thin-film TI-based metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, we explore the performance of MOSFETs basedmore » on thin film 3D-TI structures by employing quantum ballistic transport simulations using the effective continuous Hamiltonian with fitting parameters extracted from ab-initio calculations. We demonstrate that thin film transistors based on a 3D-TI structure provide similar electrical characteristics compared to a Si-MOSFET for gate lengths down to 10 nm. Thus, such a device can be a potential candidate to replace Si-based MOSFETs in the sub-10 nm regime.« less

Interfacial varactor characteristics of ferroelectric thin films on high-resistivity Si substrate

NASA Astrophysics Data System (ADS)

Lan, Wen-An; Wang, Tsan-Chun; Huang, Ling-Hui; Wu, Tai-Bor

2006-07-01

Ferroelectric Ba(Zr0.25Ti0.75)O3 (BZT) thin films were deposited on high-resistivity Si substrate without or with inserting a high-k buffer layer of Ta2O5. The varactor characteristics of the BZT capacitors in metal-oxide-semiconductor structure were studied. At low frequency (1MHz ), the capacitors exhibit a negatively tunable characteristic, i.e., [C(V)-C(0)]/C(0)<0, against dc bias V, but opposite tunable characteristics were found at microwave frequencies (>1GHz). The change of voltage-dependent characteristic is attributed to the effect of low-resistivity interface induced by charged defects formed from interfacial oxidation of Si in screening the microwave from penetrating into the bulk of Si.

Effects of Post-Deposition Annealing on ZrO2/n-GaN MOS Capacitors with H2O and O3 as the Oxidizers

NASA Astrophysics Data System (ADS)

Zheng, Meijuan; Zhang, Guozhen; Wang, Xiao; Wan, Jiaxian; Wu, Hao; Liu, Chang

2017-04-01

GaN-based metal-oxide-semiconductor capacitors with ZrO2 as the dielectric layer have been prepared by atomic layer deposition. The accumulation and depletion regions can be clearly distinguished when the voltage was swept from -4 to 4 V. Post-annealing results suggested that the capacitance in accumulation region went up gradually as the annealing temperature increased from 300 to 500 °C. A minimum leakage current density of 3 × 10-9 A/cm2 at 1 V was obtained when O3 was used for the growth of ZrO2. Leakage analysis revealed that Schottky emission and Fowler-Nordheim tunneling were the main leakage mechanisms.

Collaborative research in tunneling and field emission pumped surface wave local oscillators and amplifiers for infrared and submillimeter wavelengths under director's discretionary fund

NASA Technical Reports Server (NTRS)

Gustafson, T. K.

1982-01-01

Progress is reported in work towards the development of surface wave sources for the infrared and sub-millimeter portion of the spectrum to be based upon electron pumping by tunneling electrons in metal-barrier-metal or metal-barrier-semiconductor devices. Tunneling phenomena and the coupling of radiation to tunnel junctions were studied. The propagation characteristics of surface electro-magnetic modes in metal-insulator-p(++) semiconductor structures as a function of frequency were calculated. A model for the gain process based upon Tucker's formalism was developed and used to estimate what low frequency gain might be expected from such structures. The question of gain was addressed from a more fundamental viewpoint using the method of Lasher and Stern.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, Bao; Liu, Wen-Jun; Wei, Lei

Excellent voltage linearity of metal-insulator-metal (MIM) capacitors is highly required for next generation radio frequency integration circuits. In this work, employing atomic layer deposition technique, we demonstrated how the voltage linearity of MIM capacitors was modulated by adding different thickness of SiO{sub 2} layer to the nano-stack of Al{sub 2}O{sub 3}/ZrO{sub 2}. It was found that the quadratic voltage coefficient of capacitance (α) can be effectively reduced from 1279 to −75 ppm/V{sup 2} with increasing the thickness of SiO{sub 2} from zero to 4 nm, which is more powerful than increasing the thickness of ZrO{sub 2} in the Al{sub 2}O{sub 3}/ZrO{sub 2}more » stack. This is attributed to counteraction between the positive α for Al{sub 2}O{sub 3}/ZrO{sub 2} and the negative one for SiO{sub 2} in the MIM capacitors with Al{sub 2}O{sub 3}/ZrO{sub 2}/SiO{sub 2} stacks. Interestingly, voltage-polarity dependent conduction behaviors in the MIM capacitors were observed. For electron bottom-injection, the addition of SiO{sub 2} obviously suppressed the leakage current; however, it abnormally increased the leakage current for electron top-injection. These are ascribed to the co-existence of shallow and deep traps in ZrO{sub 2}, and the former is in favor of the field-assisted tunnelling conduction and the latter contributes to the trap-assisted tunnelling process. The above findings will be beneficial to device design and process optimization for high performance MIM capacitors.« less

Damage free Ar ion plasma surface treatment on In{sub 0.53}Ga{sub 0.47}As-on-silicon metal-oxide-semiconductor device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koh, Donghyi; Shin, Seung Heon; Ahn, Jaehyun

2015-11-02

In this paper, we investigated the effect of in-situ Ar ion plasma surface pre-treatment in order to improve the interface properties of In{sub 0.53}Ga{sub 0.47}As for high-κ top-gate oxide deposition. X-ray photoelectron spectroscopy (XPS) and metal-oxide-semiconductor capacitors (MOSCAPs) demonstrate that Ar ion treatment removes the native oxide on In{sub 0.53}Ga{sub 0.47}As. The XPS spectra of Ar treated In{sub 0.53}Ga{sub 0.47}As show a decrease in the AsO{sub x} and GaO{sub x} signal intensities, and the MOSCAPs show higher accumulation capacitance (C{sub acc}), along with reduced frequency dispersion. In addition, Ar treatment is found to suppress the interface trap density (D{sub it}),more » which thereby led to a reduction in the threshold voltage (V{sub th}) degradation during constant voltage stress and relaxation. These results outline the potential of surface treatment for III-V channel metal-oxide-semiconductor devices and application to non-planar device process.« less

An Ultrathin Single Crystalline Relaxor Ferroelectric Integrated on a High Mobility Semiconductor.

PubMed

Moghadam, Reza M; Xiao, Zhiyong; Ahmadi-Majlan, Kamyar; Grimley, Everett D; Bowden, Mark; Ong, Phuong-Vu; Chambers, Scott A; Lebeau, James M; Hong, Xia; Sushko, Peter V; Ngai, Joseph H

2017-10-11

The epitaxial growth of multifunctional oxides on semiconductors has opened a pathway to introduce new functionalities to semiconductor device technologies. In particular, the integration of gate materials that enable nonvolatile or hysteretic functionality in field-effect transistors could lead to device technologies that consume less power or allow for novel modalities in computing. Here we present electrical characterization of ultrathin single crystalline SrZr x Ti 1-x O 3 (x = 0.7) films epitaxially grown on a high mobility semiconductor, Ge. Epitaxial films of SrZr x Ti 1-x O 3 exhibit relaxor behavior, characterized by a hysteretic polarization that can modulate the surface potential of Ge. We find that gate layers as thin as 5 nm corresponding to an equivalent-oxide thickness of just 1.0 nm exhibit a ∼2 V hysteretic window in the capacitance-voltage characteristics. The development of hysteretic metal-oxide-semiconductor capacitors with nanoscale gate thicknesses opens new vistas for nanoelectronic devices.

Internal Photoemission at Interaces of ALD TaiOx Insulating Layers Deposited on Si, InP and In0.53Ga0.47As

NASA Astrophysics Data System (ADS)

Chou, H. Y.; Afanas'ev, V. V.; Thoan, N. H.; Adelmann, C.; Lin, H. C.; Houssa, M.; Stesmans, A.

2012-12-01

Electrical analysis of interfaces of (100)Si, (100)InP, and (100)In0.53Ga0.47As with TaSiOx (Ta/Si≈1) films atomic-layer deposited using SiCl4, TaCl5, and H2O precursors suggests Ta silicate as a good insulating and surface passivating layer on all three semiconductors. However, when a positive voltage is applied to the top metal electrode in a metal/ TaSiOx /semiconductor configuration, considerable hysteresis of the capacitance-voltage curves, both at 300 and 77 K, is universally observed indicating electron injection and trapping in the insulator. To shed some light on the origin of this charge instability, we analyzed interface band alignment of the studied interfaces using the spectroscopies of internal photoemission and photoconductivity measurements. The latter reveals that independently of the semiconductor substrate material, TaSiOx layers exhibit a bandgap of only 4.5±0.1 eV, typical for a Ta2O5 network. The density of electron states associated with this narrow-gap network may account for the enhanced electron injection and trapping. Furthermore, while a sufficiently high energy barrier for electrons between Si and TaSiOx (3.1±0.1 eV) is found, much lower IPE thresholds are encountered at the (100)InP/TaSiOx and (100) In0.53Ga0.47As/TaSiOx interfaces, i.e., 2.4 and 2.0 eV, respectively. The lower barrier may be related by the formation of narrow-gap In-rich interlayers between AIIIBV semiconductors and TaSiOx.

Internal Photoemission at Interfaces of ALD TaSiOx Insulating Layers Deposited on Si, InP and In0.53Ga0.47As

NASA Astrophysics Data System (ADS)

Y Chou, H.; Afanas'ev, V. V.; Thoan, N. H.; Adelmann, C.; Lin, H. C.; Houssa, M.; Stesmans, A.

2012-10-01

Electrical analysis of interfaces of (100)Si, (100)InP, and (100)In0.53Ga0.47As with TaSiOx (Ta/Si≈1) films atomic-layer deposited using SiCl4, TaCl5, and H2O precursors suggests Ta silicate as a good insulating and surface passivating layer on all three semiconductors. However, when a positive voltage is applied to the top metal electrode in a metal/ TaSiOx /semiconductor configuration, considerable hysteresis of the capacitance-voltage curves, both at 300 and 77 K, is universally observed indicating electron injection and trapping in the insulator. To shed some light on the origin of this charge instability, we analyzed interface band alignment of the studied interfaces using the spectroscopies of internal photoemission and photoconductivity measurements. The latter reveals that independently of the semiconductor substrate material, TaSiOx layers exhibit a bandgap of only 4.5±0.1 eV, typical for a Ta2O5 network. The density of electron states associated with this narrow-gap network may account for the enhanced electron injection and trapping. Furthermore, while a sufficiently high energy barrier for electrons between Si and TaSiOx (3.1±0.1 eV) is found, much lower IPE thresholds are encountered at the (100)InP/TaSiOx and (100) In0.53Ga0.47As/TaSiOx interfaces, i.e., 2.4 and 2.0 eV, respectively. The lower barrier may be related by the formation of narrow-gap In-rich interlayers between AIIIBV semiconductors and TaSiOx.

Sulfur as a surface passivation for InP

NASA Technical Reports Server (NTRS)

Iyer, R.; Chang, R. R.; Lile, D. L.

1988-01-01

The use of liquid and gas phase sulfur pretreatment of the surface of InP as a way to form a near-ideal passivated surface prior to chemical vapor deposition of SiO2 was investigated. Results of high-frequency and quasi-static capacitance-voltage measurements, as well as enhancement mode insulated gate field-effect transistor (FET) transductance and drain current stability studies, all support the efficacy of this approach for metal-insulator-semiconductor application of this semiconductor. In particular, surface state values in the range of 10 to the 10th to a few 10 to the 11th/sq cm per eV and enhancement mode FET drain current drifts of less than 5 percent over a 12 h test period were measured.

Improving yield and performance in ZnO thin-film transistors made using selective area deposition.

PubMed

Nelson, Shelby F; Ellinger, Carolyn R; Levy, David H

2015-02-04

We describe improvements in both yield and performance for thin-film transistors (TFTs) fabricated by spatial atomic layer deposition (SALD). These improvements are shown to be critical in forming high-quality devices using selective area deposition (SAD) as the patterning method. Selective area deposition occurs when the precursors for the deposition are prevented from reacting with some areas of the substrate surface. Controlling individual layer quality and the interfaces between layers is essential for obtaining good-quality thin-film transistors and capacitors. The integrity of the gate insulator layer is particularly critical, and we describe a method for forming a multilayer dielectric using an oxygen plasma treatment between layers that improves crossover yield. We also describe a method to achieve improved mobility at the important interface between the semiconductor and the gate insulator by, conversely, avoiding oxygen plasma treatment. Integration of the best designs results in wide design flexibility, transistors with mobility above 15 cm(2)/(V s), and good yield of circuits.

Method of making silicon on insalator material using oxygen implantation

DOEpatents

Hite, Larry R.; Houston, Ted; Matloubian, Mishel

1989-01-01

The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Stoichiometric and Oxygen-Deficient VO2 as Versatile Hole Injection Electrode for Organic Semiconductors.

PubMed

Fu, Keke; Wang, Rongbin; Katase, Takayoshi; Ohta, Hiromichi; Koch, Norbert; Duhm, Steffen

2018-03-28

Using photoemission spectroscopy, we show that the surface electronic structure of VO 2 is determined by the temperature-dependent metal-insulator phase transition and the density of oxygen vacancies, which depends on the temperature and ultrahigh vacuum (UHV) conditions. The atomically clean and stoichiometric VO 2 surface is insulating at room temperature and features an ultrahigh work function of up to 6.7 eV. Heating in UHV just above the phase transition temperature induces the expected metallic phase, which goes in hand with the formation of oxygen defects (up to 6% in this study), but a high work function >6 eV is maintained. To demonstrate the suitability of VO 2 as hole injection contact for organic semiconductors, we investigated the energy-level alignment with the prototypical organic hole transport material N, N'-di(1-naphthyl)- N, N'-diphenyl-(1,1'-biphenyl)-4,4'-diamine (NPB). Evidence for strong Fermi-level pinning and the associated energy-level bending in NPB is found, rendering an Ohmic contact for holes.

Multilayer graphene on insulator formed by Co-induced layer exchange

NASA Astrophysics Data System (ADS)

Murata, Hiromasa; Toko, Kaoru; Suemasu, Takashi

2017-05-01

The direct synthesis of multilayer graphene (MLG) on arbitrary substrates is essential for incorporating carbon wirings and heat spreaders into electronic devices. Here, we applied the metal-induced layer exchange (MILE) technique, developed for group-IV semiconductors, to a sputtered amorphous carbon (a-C) thin film using Co as a catalyst. MLG was formed on a SiO2 substrate at 800 °C for 10 min; however, it disappeared during wet etching for removing Co. This behavior was attributed to the small contact area between MLG and SiO2 caused by the deformation of the Co layer during annealing. By preparing the Co layer at 200 °C, its thermal stability was improved, resulting in the synthesis of MLG on the substrate through MILE. Raman measurements indicated good crystal quality of the MLG compared with that obtained by conventional metal-induced solid-phase crystallization. MILE was thus proven to be useful not only for group-IV semiconductors but also for carbon materials on insulators.

Ultrathin body GaSb-on-insulator p-channel metal-oxide-semiconductor field-effect transistors on Si fabricated by direct wafer bonding

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yokoyama, Masafumi, E-mail: yokoyama@mosfet.t.u-tokyo.ac.jp; Takenaka, Mitsuru; Takagi, Shinichi

2015-02-16

We have realized ultrathin body GaSb-on-insulator (GaSb-OI) on Si wafers by direct wafer bonding technology using atomic-layer deposition (ALD) Al{sub 2}O{sub 3} and have demonstrated GaSb-OI p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Si. A 23-nm-thick GaSb-OI p-MOSFET exhibits the peak effective mobility of ∼76 cm{sup 2}/V s. We have found that the effective hole mobility of the thin-body GaSb-OI p-MOSFETs decreases with a decrease in the GaSb-OI thickness or with an increase in Al{sub 2}O{sub 3} ALD temperature. The InAs passivation of GaSb-OI MOS interfaces can enhance the peak effective mobility up to 159 cm{sup 2}/V s for GaSb-OI p-MOSFETs with themore » 20-nm-thick GaSb layer.« less

Quasi-Two-Dimensional h-BN/β-Ga2O3 Heterostructure Metal-Insulator-Semiconductor Field-Effect Transistor.

PubMed

Kim, Janghyuk; Mastro, Michael A; Tadjer, Marko J; Kim, Jihyun

2017-06-28

β-gallium oxide (β-Ga 2 O 3 ) and hexagonal boron nitride (h-BN) heterostructure-based quasi-two-dimensional metal-insulator-semiconductor field-effect transistors (MISFETs) were demonstrated by integrating mechanical exfoliation of (quasi)-two-dimensional materials with a dry transfer process, wherein nanothin flakes of β-Ga 2 O 3 and h-BN were utilized as the channel and gate dielectric, respectively, of the MISFET. The h-BN dielectric, which has an extraordinarily flat and clean surface, provides a minimal density of charged impurities on the interface between β-Ga 2 O 3 and h-BN, resulting in superior device performances (maximum transconductance, on/off ratio, subthreshold swing, and threshold voltage) compared to those of the conventional back-gated configurations. Also, double-gating of the fabricated device was demonstrated by biasing both top and bottom gates, achieving the modulation of the threshold voltage. This heterostructured wide-band-gap nanodevice shows a new route toward stable and high-power nanoelectronic devices.

A field-shaping multi-well avalanche detector for direct conversion amorphous selenium

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goldan, A. H.; Zhao, W.

2013-01-15

Purpose: A practical detector structure is proposed to achieve stable avalanche multiplication gain in direct-conversion amorphous selenium radiation detectors. Methods: The detector structure is referred to as a field-shaping multi-well avalanche detector. Stable avalanche multiplication gain is achieved by eliminating field hot spots using high-density avalanche wells with insulated walls and field-shaping inside each well. Results: The authors demonstrate the impact of high-density insulated wells and field-shaping to eliminate the formation of both field hot spots in the avalanche region and high fields at the metal-semiconductor interface. Results show a semi-Gaussian field distribution inside each well using the field-shaping electrodes,more » and the electric field at the metal-semiconductor interface can be one order-of-magnitude lower than the peak value where avalanche occurs. Conclusions: This is the first attempt to design a practical direct-conversion amorphous selenium detector with avalanche gain.« less

Electrical response of Pt/Ru/PbZr0.52Ti0.48O3/Pt capacitor as function of lead precursor excess

NASA Astrophysics Data System (ADS)

Gueye, Ibrahima; Le Rhun, Gwenael; Renault, Olivier; Defay, Emmanuel; Barrett, Nicholas

2017-11-01

We investigated the influence of the surface microstructure and chemistry of sol-gel grown PbZr0.52Ti0.48O3 (PZT) on the electrical performance of PZT-based metal-insulator-metal (MIM) capacitors as a function of Pb precursor excess. Using surface-sensitive, quantitative X-ray photoelectron spectroscopy and scanning electron microscopy, we confirm the presence of ZrOx surface phase. Low Pb excess gives rise to a discontinuous layer of ZrOx on a (100) textured PZT film with a wide band gap reducing the capacitance of PZT-based MIMs whereas the breakdown field is enhanced. At high Pb excess, the nanostructures disappear while the PZT grain size increases and the film texture becomes (111). Concomitantly, the capacitance density is enhanced by 8.7%, and both the loss tangent and breakdown field are reduced by 20 and 25%, respectively. The role of the low permittivity, dielectric interface layer on capacitance and breakdown is discussed.

MEMS fabrication and frequency sweep for suspending beam and plate electrode in electrostatic capacitor

NASA Astrophysics Data System (ADS)

Zhu, Jianxiong; Song, Weixing

2018-01-01

We report a MEMS fabrication and frequency sweep for a high-order mode suspending beam and plate layer in electrostatic micro-gap semiconductor capacitor. This suspended beam and plate was designed with silicon oxide (SiO2) film which was fabricated using bulk silicon micromachining technology on both side of a silicon substrate. The designed semiconductor capacitors were driven by a bias direct current (DC) and a sweep frequency alternative current (AC) in a room temperature for an electrical response test. Finite element calculating software was used to evaluate the deformation mode around its high-order response frequency. Compared a single capacitor with a high-order response frequency (0.42 MHz) and a 1 × 2 array parallel capacitor, we found that the 1 × 2 array parallel capacitor had a broader high-order response range. And it concluded that a DC bias voltage can be used to modulate a high-order response frequency for both a single and 1 × 2 array parallel capacitors.

Solid-state pulse modulator using Marx generator for a medical linac electron-gun

NASA Astrophysics Data System (ADS)

Lim, Heuijin; Hyeok Jeong, Dong; Lee, Manwoo; Lee, Mujin; Yi, Jungyu; Yang, Kwangmo; Ro, Sung Chae

2016-04-01

A medical linac is used for the cancer treatment and consists of an accelerating column, waveguide components, a magnetron, an electron-gun, a pulse modulator, and an irradiation system. The pulse modulator based on hydrogen thyratron-switched pulse-forming network is commonly used in linac. As the improvement of the high power semiconductors in switching speed, voltage rating, and current rating, an insulated gate bipolar transistor has become the more popular device used for pulsed power systems. We propose a solid-state pulse modulator to generator high voltage by multi-stacked storage-switch stages based on the Marx generator. The advantage of our modulator comes from the use of two semiconductors to control charging and discharging of the storage capacitor at each stage and it allows to generate the pulse with various amplitudes, widths, and shapes. In addition, a gate driver for two semiconductors is designed to reduce the control channels and to protect the circuits. It is developed for providing the pulsed power to a medical linac electron-gun that requires 25 kV and 1 A as the first application. In order to improve the power efficiency and achieve the compactness modulator, a capacitor charging power supply, a Marx pulse generator, and an electron-gun heater isolated transformer are constructed and integrated. This technology is also being developed to extend the high power pulsed system with > 1 MW and also other applications such as a plasma immersed ion implantation and a micro pulse electrostatic precipitator which especially require variable pulse shape and high repetition rate > 1 kHz. The paper describes the design features and the construction of this solid-state pulse modulator. Also shown are the performance results into the linac electron-gun.

Anomalous Temperature Dependence in Metal-Black Phosphorus Contact.

PubMed

Li, Xuefei; Grassi, Roberto; Li, Sichao; Li, Tiaoyang; Xiong, Xiong; Low, Tony; Wu, Yanqing

2018-01-10

Metal-semiconductor contact has been the performance limiting problem for electronic devices and also dictates the scaling potential for future generation devices based on novel channel materials. Two-dimensional semiconductors beyond graphene, particularly few layer black phosphorus, have attracted much attention due to their exceptional electronic properties such as anisotropy and high mobility. However, due to its ultrathin body nature, few layer black phosphorus-metal contact behaves differently than conventional Schottky barrier (SB) junctions, and the mechanisms of its carrier transport across such a barrier remain elusive. In this work, we examine the transport characteristic of metal-black phosphorus contact under varying temperature. We elucidated the origin of apparent negative SB heights extracted from classical thermionic emission model and also the phenomenon of metal-insulator transition observed in the current-temperature transistor characteristic. In essence, we found that the SB height can be modulated by the back-gate voltage, which beyond a certain critical point becomes so low that the injected carrier can no longer be described by the conventional thermionic emission theory. The transition from transport dominated by a Maxwell-Boltzmann distribution for the high energy tail states, to that of a Fermi distribution by low energy Fermi sea electrons, is the physical origin of the observed metal-insulator transition. We identified two distinctive tunneling limited transport regimes in the contact: vertical and longitudinal tunneling.

Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides

NASA Astrophysics Data System (ADS)

Jiao, C.; Ahyi, A. C.; Dhar, S.; Morisette, D.; Myers-Ward, R.

2017-04-01

We report results on the interface trap density ( D it) of 4H- and 6H-SiC metal-oxide-semiconductor (MOS) capacitors with different interface chemistries. In addition to pure dry oxidation, we studied interfaces formed by annealing thermal oxides in NO or POCl3. The D it profiles, determined by the C- ψ s method, show that, although the as-oxidized 4H-SiC/SiO2 interface has a much higher D it profile than 6H-SiC/SiO2, after postoxidation annealing (POA), both polytypes maintain comparable D it near the conduction band edge for the gate oxides incorporated with nitrogen or phosphorus. Unlike most conventional C- V- or G- ω-based methods, the C- ψ s method is not limited by the maximum probe frequency, therefore taking into account the "fast traps" detected in previous work on 4H-SiC. The results indicate that such fast traps exist near the band edge of 6H-SiC also. For both polytypes, we show that the total interface trap density ( N it) integrated from the C- ψ s method is several times that obtained from the high-low method. The results suggest that the detected fast traps have a detrimental effect on electron transport in metal-oxide-semiconductor field-effect transistor (MOSFET) channels.

Origin of colossal dielectric permittivity of rutile Ti 0.9In 0.05Nb 0.05O 2: single crystal and polycrystalline

DOE PAGES

Song, Yongli; Wang, Xianjie; Sui, Yu; ...

2016-02-12

Here in this article, we investigated the dielectric properties of (In + Nb) co-doped rutile TiO 2 single crystal and polycrystalline ceramics. Both of them showed colossal, up to 10 4, dielectric permittivity at room temperature. The single crystal sample showed one dielectric relaxation process with a large dielectric loss. The voltage-dependence of dielectric permittivity and the impedance spectrum suggest that the high dielectric permittivity of single crystal originated from the surface barrier layer capacitor (SBLC). The impedance spectroscopy at different temperature confirmed that the (In+Nb) co-doped rutile TiO 2 polycrystalline ceramic had semiconductor grains and insulating grain boundaries, andmore » that the activation energies were calculated to be 0.052 eV and 0.35 eV for grain and grain boundary, respectively. The dielectric behavior and impedance spectrum of the polycrystalline ceramic sample indicated that the internal barrier layer capacitor (IBLC) mode made a major contribution to the high ceramic dielectric permittivity, instead of the electron-pinned defect-dipoles.« less

Origin of colossal dielectric permittivity of rutile Ti0.9In0.05Nb0.05O2: single crystal and polycrystalline

PubMed Central

Song, Yongli; Wang, Xianjie; Sui, Yu; Liu, Ziyi; Zhang, Yu; Zhan, Hongsheng; Song, Bingqian; Liu, Zhiguo; Lv, Zhe; Tao, Lei; Tang, Jinke

2016-01-01

In this paper, we investigated the dielectric properties of (In + Nb) co-doped rutile TiO2 single crystal and polycrystalline ceramics. Both of them showed colossal, up to 104, dielectric permittivity at room temperature. The single crystal sample showed one dielectric relaxation process with a large dielectric loss. The voltage-dependence of dielectric permittivity and the impedance spectrum suggest that the high dielectric permittivity of single crystal originated from the surface barrier layer capacitor (SBLC). The impedance spectroscopy at different temperature confirmed that the (In + Nb) co-doped rutile TiO2 polycrystalline ceramic had semiconductor grains and insulating grain boundaries, and that the activation energies were calculated to be 0.052 eV and 0.35 eV for grain and grain boundary, respectively. The dielectric behavior and impedance spectrum of the polycrystalline ceramic sample indicated that the internal barrier layer capacitor (IBLC) mode made a major contribution to the high ceramic dielectric permittivity, instead of the electron-pinned defect-dipoles. PMID:26869187

Origin of colossal dielectric permittivity of rutile Ti0.9In0.05Nb0.05O2: single crystal and polycrystalline

NASA Astrophysics Data System (ADS)

Song, Yongli; Wang, Xianjie; Sui, Yu; Liu, Ziyi; Zhang, Yu; Zhan, Hongsheng; Song, Bingqian; Liu, Zhiguo; Lv, Zhe; Tao, Lei; Tang, Jinke

2016-02-01

In this paper, we investigated the dielectric properties of (In + Nb) co-doped rutile TiO2 single crystal and polycrystalline ceramics. Both of them showed colossal, up to 104, dielectric permittivity at room temperature. The single crystal sample showed one dielectric relaxation process with a large dielectric loss. The voltage-dependence of dielectric permittivity and the impedance spectrum suggest that the high dielectric permittivity of single crystal originated from the surface barrier layer capacitor (SBLC). The impedance spectroscopy at different temperature confirmed that the (In + Nb) co-doped rutile TiO2 polycrystalline ceramic had semiconductor grains and insulating grain boundaries, and that the activation energies were calculated to be 0.052 eV and 0.35 eV for grain and grain boundary, respectively. The dielectric behavior and impedance spectrum of the polycrystalline ceramic sample indicated that the internal barrier layer capacitor (IBLC) mode made a major contribution to the high ceramic dielectric permittivity, instead of the electron-pinned defect-dipoles.

Origin of colossal dielectric permittivity of rutile Ti₀.₉In₀.₀₅Nb₀.₀₅O₂: single crystal and polycrystalline.

PubMed

Song, Yongli; Wang, Xianjie; Sui, Yu; Liu, Ziyi; Zhang, Yu; Zhan, Hongsheng; Song, Bingqian; Liu, Zhiguo; Lv, Zhe; Tao, Lei; Tang, Jinke

2016-02-12

In this paper, we investigated the dielectric properties of (In + Nb) co-doped rutile TiO2 single crystal and polycrystalline ceramics. Both of them showed colossal, up to 10(4), dielectric permittivity at room temperature. The single crystal sample showed one dielectric relaxation process with a large dielectric loss. The voltage-dependence of dielectric permittivity and the impedance spectrum suggest that the high dielectric permittivity of single crystal originated from the surface barrier layer capacitor (SBLC). The impedance spectroscopy at different temperature confirmed that the (In + Nb) co-doped rutile TiO2 polycrystalline ceramic had semiconductor grains and insulating grain boundaries, and that the activation energies were calculated to be 0.052 eV and 0.35 eV for grain and grain boundary, respectively. The dielectric behavior and impedance spectrum of the polycrystalline ceramic sample indicated that the internal barrier layer capacitor (IBLC) mode made a major contribution to the high ceramic dielectric permittivity, instead of the electron-pinned defect-dipoles.

Capacitor blocks for linear transformer driver stages.

PubMed

Kovalchuk, B M; Kharlov, A V; Kumpyak, E V; Smorudov, G V; Zherlitsyn, A A

2014-01-01

In the Linear Transformer Driver (LTD) technology, the low inductance energy storage components and switches are directly incorporated into the individual cavities (named stages) to generate a fast output voltage pulse, which is added along a vacuum coaxial line like in an inductive voltage adder. LTD stages with air insulation were recently developed, where air is used both as insulation in a primary side of the stages and as working gas in the LTD spark gap switches. A custom designed unit, referred to as a capacitor block, was developed for use as a main structural element of the transformer stages. The capacitor block incorporates two capacitors GA 35426 (40 nF, 100 kV) and multichannel multigap gas switch. Several modifications of the capacitor blocks were developed and tested on the life time and self breakdown probability. Blocks were tested both as separate units and in an assembly of capacitive module, consisting of five capacitor blocks. This paper presents detailed design of capacitor blocks, description of operation regimes, numerical simulation of electric field in the switches, and test results.

Resistivity behavior of optimized PbTiO3 thin films prepared by spin coating method

NASA Astrophysics Data System (ADS)

Nurbaya, Z.; Wahid, M. H.; Rozana, M. D.; Alrokayan, S. A. H.; Khan, H. A.; Rusop, M.

2018-05-01

Th is study presents the resistivity behavior of PbTiO3 thin films which were prepared towards metal-insulator-metal capacitor device fabrication. The PbTiO3 thin films were prepared through sol-gel spin coating method that involved various deposition parameters that is (1) different molar concentration of PbTiO3 solutions, (2) various additional PbAc-content in PbTiO3 solutions, and (3) various annealing temperature on PbTiO3 thin films. Hence, an electrical measurement of current versus voltage was done to determine the resistivity behavior of PbTiO3 thin films.

In-Plane Impedance Spectroscopy measurements in Vanadium Dioxide thin films

NASA Astrophysics Data System (ADS)

Ramirez, Juan; Patino, Edgar; Schmidt, Rainer; Sharoni, Amos; Gomez, Maria; Schuller, Ivan

2012-02-01

In plane Impedance Spectroscopy measurements have been done in Vanadium Dioxide thin films in the range of 100 Hz to 1 MHz. Our measurements allows distinguishing between the resistive and capacitive response of the Vanadium Dioxide films across the metal-insulator transition. A non ideal RC behavior was found in our thin films from room temperature up to 334 K. Around the MIT, an increase of the total capacitance is observed. A capacitor-network model is able to reproduce the capacitance changes across the MIT. Above the MIT, the system behaves like a metal as expected, and a modified equivalent circuit is necessary to describe the impedance data adequately.

A Compact Operational Amplifier with Load-Insensitive Stability Compensation for High-Precision Transducer Interface.

PubMed

Yu, Zhanghao; Yang, Xi; Chung, SungWon

2018-01-29

High-resolution electronic interface circuits for transducers with nonlinear capacitive impedance need an operational amplifier, which is stable for a wide range of load capacitance. Such operational amplifier in a conventional design requires a large area for compensation capacitors, increasing costs and limiting applications. In order to address this problem, we present a gain-boosted two-stage operational amplifier, whose frequency response compensation capacitor size is insensitive to the load capacitance and also orders of magnitude smaller compared to the conventional Miller-compensation capacitor that often dominates chip area. By exploiting pole-zero cancellation between a gain-boosting stage and the main amplifier stage, the compensation capacitor of the proposed operational amplifier becomes less dependent of load capacitance, so that it can also operate with a wide range of load capacitance. A prototype operational amplifier designed in 0.13-μm complementary metal-oxide-semiconductor (CMOS) with a 400-fF compensation capacitor occupies 900- μ m 2 chip area and achieves 0.022-2.78-MHz unity gain bandwidth and over 65 ∘ phase margin with a load capacitance of 0.1-15 nF. The prototype amplifier consumes 7.6 μ W from a single 1.0-V supply. For a given compensation capacitor size and a chip area, the prototype design demonstrates the best reported performance trade-off on unity gain bandwidth, maximum stable load capacitance, and power consumption.

Deposition Of Cubic BN On Diamond Interlayers

NASA Technical Reports Server (NTRS)

Ong, Tiong P.; Shing, Yuh-Han

1994-01-01

Thin films of polycrystalline, pure, cubic boron nitride (c-BN) formed on various substrates, according to proposal, by chemical vapor deposition onto interlayers of polycrystalline diamond. Substrate materials include metals, semiconductors, and insulators. Typical substrates include metal-cutting tools: polycrystalline c-BN coats advantageous for cutting ferrous materials and for use in highly oxidizing environments-applications in which diamond coats tend to dissolve in iron or be oxidized, respectively.

Effects of Post-Deposition Annealing on ZrO2/n-GaN MOS Capacitors with H2O and O3 as the Oxidizers.

PubMed

Zheng, Meijuan; Zhang, Guozhen; Wang, Xiao; Wan, Jiaxian; Wu, Hao; Liu, Chang

2017-12-01

GaN-based metal-oxide-semiconductor capacitors with ZrO 2 as the dielectric layer have been prepared by atomic layer deposition. The accumulation and depletion regions can be clearly distinguished when the voltage was swept from -4 to 4 V. Post-annealing results suggested that the capacitance in accumulation region went up gradually as the annealing temperature increased from 300 to 500 °C. A minimum leakage current density of 3 × 10 -9  A/cm 2 at 1 V was obtained when O 3 was used for the growth of ZrO 2 . Leakage analysis revealed that Schottky emission and Fowler-Nordheim tunneling were the main leakage mechanisms.

Highly scaled equivalent oxide thickness of 0.66 nm for TiN/HfO2/GaSb MOS capacitors by using plasma-enhanced atomic layer deposition

NASA Astrophysics Data System (ADS)

Tsai, Ming-Li; Wang, Shin-Yuan; Chien, Chao-Hsin

2017-08-01

Through in situ hydrogen plasma treatment (HPT) and plasma-enhanced atomic-layer-deposited TiN (PEALD-TiN) layer capping, we successfully fabricated TiN/HfO2/GaSb metal-oxide-semiconductor capacitors with an ultrathin equivalent oxide thickness of 0.66 nm and a low density of states of approximately 2 × 1012 cm-2 eV-1 near the valence band edge. After in situ HPT, a native oxide-free surface was obtained through efficient etching. Moreover, the use of the in situ PEALD-TiN layer precluded high-κ dielectric damage that would have been caused by conventional sputtering, thereby yielding a superior high-κ dielectric and low gate leakage current.

New technique for heterogeneous vapor-phase synthesis of nanostructured metal layers from low-dimensional volatile metal complexes

NASA Astrophysics Data System (ADS)

Badalyan, A. M.; Bakhturova, L. F.; Kaichev, V. V.; Polyakov, O. V.; Pchelyakov, O. P.; Smirnov, G. I.

2011-09-01

A new technique for depositing thin nanostructured layers on semiconductor and insulating substrates that is based on heterogeneous gas-phase synthesis from low-dimensional volatile metal complexes is suggested and tried out. Thin nanostructured copper layers are deposited on silicon and quartz substrates from low-dimensional formate complexes using a combined synthesis-mass transport process. It is found that copper in layers thus deposited is largely in a metal state (Cu0) and has the form of closely packed nanograins with a characteristic structure.

Role of the dielectric for the charging dynamics of the dielectric/barrier interface in AlGaN/GaN based metal-insulator-semiconductor structures under forward gate bias stress

NASA Astrophysics Data System (ADS)

Lagger, P.; Steinschifter, P.; Reiner, M.; Stadtmüller, M.; Denifl, G.; Naumann, A.; Müller, J.; Wilde, L.; Sundqvist, J.; Pogany, D.; Ostermaier, C.

2014-07-01

The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔVth, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness tD and barrier thickness tB, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔNit, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. The scaling behavior of ΔNit is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends.

PubMed

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-08-02

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed.

Inkjet-Printed Organic Transistors Based on Organic Semiconductor/Insulating Polymer Blends

PubMed Central

Kwon, Yoon-Jung; Park, Yeong Don; Lee, Wi Hyoung

2016-01-01

Recent advances in inkjet-printed organic field-effect transistors (OFETs) based on organic semiconductor/insulating polymer blends are reviewed in this article. Organic semiconductor/insulating polymer blends are attractive ink candidates for enhancing the jetting properties, inducing uniform film morphologies, and/or controlling crystallization behaviors of organic semiconductors. Representative studies using soluble acene/insulating polymer blends as an inkjet-printed active layer in OFETs are introduced with special attention paid to the phase separation characteristics of such blended films. In addition, inkjet-printed semiconducting/insulating polymer blends for fabricating high performance printed OFETs are reviewed. PMID:28773772

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

Defect-free high Sn-content GeSn on insulator grown by rapid melting growth.

PubMed

Liu, Zhi; Cong, Hui; Yang, Fan; Li, Chuanbo; Zheng, Jun; Xue, Chunlai; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2016-12-12

GeSn is an attractive semiconductor material for Si-based photonics. However, large lattice mismatch between GeSn and Si and the low solubility of Sn in Ge limit its development. In order to obtain high Sn-content GeSn on Si, it is normally grown at low temperature, which would lead to inevitable dislocations. Here, we reported a single-crystal defect-free graded GeSn on insulator (GSOI) stripes laterally grown by rapid melting growth (RMG). The Sn-content reaches to 14.2% at the end of the GSOI stripe. Transmission electron microscopy observation shows the GSOI stripe without stacking fault and dislocations. P-channel pseudo metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor-metal (MSM) Schottky junction photodetectors were fabricated on these GSOIs. Good transistor performance with a low field peak hole mobility of 402 cm 2 /Vs is obtained, which indicates a high-quality of this GSOI structure. Strong near-infrared and short-wave infrared optical absorption of the MSM photodetectors at 1550 nm and 2000 nm were observed. Owing to high Sn-content and defect-free, responsivity of 236 mA/W@-1.5 V is achieved at 1550 nm wavelength. In addition, responsivity reaches 154 mA/W@-1.5 V at 2000 nm with the optical absorption layer only 200 nm-thick, which is the highest value reported for GeSn junction photodetectors until now.

Defect-free high Sn-content GeSn on insulator grown by rapid melting growth

PubMed Central

Liu, Zhi; Cong, Hui; Yang, Fan; Li, Chuanbo; Zheng, Jun; Xue, Chunlai; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2016-01-01

GeSn is an attractive semiconductor material for Si-based photonics. However, large lattice mismatch between GeSn and Si and the low solubility of Sn in Ge limit its development. In order to obtain high Sn-content GeSn on Si, it is normally grown at low temperature, which would lead to inevitable dislocations. Here, we reported a single-crystal defect-free graded GeSn on insulator (GSOI) stripes laterally grown by rapid melting growth (RMG). The Sn-content reaches to 14.2% at the end of the GSOI stripe. Transmission electron microscopy observation shows the GSOI stripe without stacking fault and dislocations. P-channel pseudo metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor-metal (MSM) Schottky junction photodetectors were fabricated on these GSOIs. Good transistor performance with a low field peak hole mobility of 402 cm2/Vs is obtained, which indicates a high-quality of this GSOI structure. Strong near-infrared and short-wave infrared optical absorption of the MSM photodetectors at 1550 nm and 2000 nm were observed. Owing to high Sn-content and defect-free, responsivity of 236 mA/W@-1.5 V is achieved at 1550 nm wavelength. In addition, responsivity reaches 154 mA/W@-1.5 V at 2000 nm with the optical absorption layer only 200 nm-thick, which is the highest value reported for GeSn junction photodetectors until now. PMID:27941825

Defect-free high Sn-content GeSn on insulator grown by rapid melting growth

NASA Astrophysics Data System (ADS)

Liu, Zhi; Cong, Hui; Yang, Fan; Li, Chuanbo; Zheng, Jun; Xue, Chunlai; Zuo, Yuhua; Cheng, Buwen; Wang, Qiming

2016-12-01

GeSn is an attractive semiconductor material for Si-based photonics. However, large lattice mismatch between GeSn and Si and the low solubility of Sn in Ge limit its development. In order to obtain high Sn-content GeSn on Si, it is normally grown at low temperature, which would lead to inevitable dislocations. Here, we reported a single-crystal defect-free graded GeSn on insulator (GSOI) stripes laterally grown by rapid melting growth (RMG). The Sn-content reaches to 14.2% at the end of the GSOI stripe. Transmission electron microscopy observation shows the GSOI stripe without stacking fault and dislocations. P-channel pseudo metal-oxide-semiconductor field effect transistors (MOSFETs) and metal-semiconductor-metal (MSM) Schottky junction photodetectors were fabricated on these GSOIs. Good transistor performance with a low field peak hole mobility of 402 cm2/Vs is obtained, which indicates a high-quality of this GSOI structure. Strong near-infrared and short-wave infrared optical absorption of the MSM photodetectors at 1550 nm and 2000 nm were observed. Owing to high Sn-content and defect-free, responsivity of 236 mA/W@-1.5 V is achieved at 1550 nm wavelength. In addition, responsivity reaches 154 mA/W@-1.5 V at 2000 nm with the optical absorption layer only 200 nm-thick, which is the highest value reported for GeSn junction photodetectors until now.

Bilayer insulator tunnel barriers for graphene-based vertical hot-electron transistors

NASA Astrophysics Data System (ADS)

Vaziri, S.; Belete, M.; Dentoni Litta, E.; Smith, A. D.; Lupina, G.; Lemme, M. C.; Östling, M.

2015-07-01

Vertical graphene-based device concepts that rely on quantum mechanical tunneling are intensely being discussed in the literature for applications in electronics and optoelectronics. In this work, the carrier transport mechanisms in semiconductor-insulator-graphene (SIG) capacitors are investigated with respect to their suitability as electron emitters in vertical graphene base transistors (GBTs). Several dielectric materials as tunnel barriers are compared, including dielectric double layers. Using bilayer dielectrics, we experimentally demonstrate significant improvements in the electron injection current by promoting Fowler-Nordheim tunneling (FNT) and step tunneling (ST) while suppressing defect mediated carrier transport. High injected tunneling current densities approaching 103 A cm-2 (limited by series resistance), and excellent current-voltage nonlinearity and asymmetry are achieved using a 1 nm thick high quality dielectric, thulium silicate (TmSiO), as the first insulator layer, and titanium dioxide (TiO2) as a high electron affinity second layer insulator. We also confirm the feasibility and effectiveness of our approach in a full GBT structure which shows dramatic improvement in the collector on-state current density with respect to the previously reported GBTs. The device design and the fabrication scheme have been selected with future CMOS process compatibility in mind. This work proposes a bilayer tunnel barrier approach as a promising candidate to be used in high performance vertical graphene-based tunneling devices.

Criticality of Low-Energy Protons in Single-Event Effects Testing of Highly-Scaled Technologies

NASA Technical Reports Server (NTRS)

Pellish, Jonathan Allen; Marshall, Paul W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element.

PubMed

Pauls, Greg; Kalkur, Thottam S

2007-06-01

Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter.

Silicon Carbide-Based Hydrogen and Hydrocarbon Gas Detection

NASA Technical Reports Server (NTRS)

Hunter, Gary W.; Neudeck, Philip G.; Chen, Liang-Yu; Knight, D.; Liu, C. C.; Wu, Q. H.R

1995-01-01

Hydrogen and hydrocarbon detection in aeronautical applications is important for reasons of safety and emissions control. The use of silicon carbide as a semiconductor in a metal-semiconductor or metal-insulator-semiconductor structure opens opportunities to measure hydrogen and hydrocarbons in high temperature environments beyond the capabilities of silicon-based devices. The purpose of this paper is to explore the response and stability of Pd-SiC Schottky diodes as gas sensors in the temperature range from 100 to 400 C. The effect of heat treating on the diode properties as measured at 100 C is explored. Subsequent operation at 400 C demonstrates the diodes' sensitivity to hydrogen and hydrocarbons. It is concluded that the Pd-SiC Schottky diode has potential as a hydrogen and hydrocarbon sensor over a wide range of temperatures but further studies are necessary to determine the diodes' long term stability.

Highly uniform and reliable resistive switching characteristics of a Ni/WOx/p+-Si memory device

NASA Astrophysics Data System (ADS)

Kim, Tae-Hyeon; Kim, Sungjun; Kim, Hyungjin; Kim, Min-Hwi; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

2018-02-01

In this paper, we investigate the resistive switching behavior of a bipolar resistive random-access memory (RRAM) in a Ni/WOx/p+-Si RRAM with CMOS compatibility. Highly unifrom and reliable bipolar resistive switching characteristics are observed by a DC voltage sweeping and its switching mechanism can be explained by SCLC model. As a result, the possibility of metal-insulator-silicon (MIS) structural WOx-based RRAM's application to Si-based 1D (diode)-1R (RRAM) or 1T (transistor)-1R (RRAM) structure is demonstrated.

Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

PubMed

Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

2013-03-25

n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

FAST TRACK COMMUNICATION: Deposition temperature effect on electrical properties and interface of high-k ZrO2 capacitor

NASA Astrophysics Data System (ADS)

Kim, Joo-Hyung; Ignatova, Velislava A.; Heitmann, Johannes; Oberbeck, Lars

2008-09-01

The electrical characteristics, i.e. leakage current and capacitance, of ZrO2 based metal-insulator-metal structures, grown at 225, 250 and 275 °C by atomic layer deposition, were studied. The lowest leakage current was obtained at 250 °C deposition temperature, while the highest dielectric constant (k ~ 43) was measured for the samples grown at 275 °C, most probably due to the formation of tetragonal/cubic phases in the ZrO2 layer. We have shown that the main leakage current of these ZrO2 capacitors is governed by the Poole-Frenkel conduction mechanism. It was observed by x-ray photoelectron spectroscopy depth profiling that at 275 °C deposition temperature the oxygen content at and beyond the ZrO2/TiN interface is higher than at lower deposition temperatures, most probably due to oxygen inter-diffusion towards the electrode layer, forming a mixed TiN-TiOxNy interface layer. At and above 275 °C the ZrO2 layer changes its structure and becomes crystalline as proven by XRD analysis.

Role of copper in time dependent dielectric breakdown of porous organo-silicate glass low-k materials

NASA Astrophysics Data System (ADS)

Zhao, Larry; Pantouvaki, Marianna; Croes, Kristof; Tőkei, Zsolt; Barbarin, Yohan; Wilson, Christopher J.; Baklanov, Mikhail R.; Beyer, Gerald P.; Claeys, Cor

2011-11-01

The role of copper in time dependent dielectric breakdown (TDDB) of a porous low-k dielectric with TaN/Ta barrier was investigated on a metal-insulator-metal capacitor configuration where Cu ions can drift into the low-k film by applying a positive potential on the top while they are not permitted to enter the low-k dielectric if a negative potential is applied on the top. No difference in TDDB performance was observed between the positive and negative bias conditions, suggesting that Cu cannot penetrate TaN/Ta barrier to play a critical role in the TDDB of porous low-k material.

A charge inverter for III-nitride light-emitting diodes

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhang, Zi-Hui, E-mail: zh.zhang@hebut.edu.cn, E-mail: wbi@hebut.edu.cn, E-mail: volkan@stanfordalumni.org, E-mail: sunxw@sustc.edu.cn; Zhang, Yonghui; Bi, Wengang, E-mail: zh.zhang@hebut.edu.cn, E-mail: wbi@hebut.edu.cn, E-mail: volkan@stanfordalumni.org, E-mail: sunxw@sustc.edu.cn

In this work, we propose a charge inverter that substantially increases the hole injection efficiency for InGaN/GaN light-emitting diodes (LEDs). The charge inverter consists of a metal/electrode, an insulator, and a semiconductor, making an Electrode-Insulator-Semiconductor (EIS) structure, which is formed by depositing an extremely thin SiO{sub 2} insulator layer on the p{sup +}-GaN surface of a LED structure before growing the p-electrode. When the LED is forward-biased, a weak inversion layer can be obtained at the interface between the p{sup +}-GaN and SiO{sub 2} insulator. The weak inversion region can shorten the carrier tunnel distance. Meanwhile, the smaller dielectric constantmore » of the thin SiO{sub 2} layer increases the local electric field within the tunnel region, and this is effective in promoting the hole transport from the p-electrode into the p{sup +}-GaN layer. Due to the improved hole injection, the external quantum efficiency is increased by 20% at 20 mA for the 350 × 350 μm{sup 2} LED chip. Thus, the proposed EIS holds great promise for high efficiency LEDs.« less

Charge trapping and current-conduction mechanisms of metal-oxide-semiconductor capacitors with La xTa y dual-doped HfON dielectrics

NASA Astrophysics Data System (ADS)

Cheng, Chin-Lung; Horng, Jeng-Haur; Chang-Liao, Kuei-Shu; Jeng, Jin-Tsong; Tsai, Hung-Yang

2010-10-01

Charge trapping and related current-conduction mechanisms in metal-oxide-semiconductor (MOS) capacitors with La xTa y dual-doped HfON dielectrics have been investigated under various post-deposition annealing (PDA). The results indicate that by La xTa y incorporation into HfON dielectric enhances electrical and reliability characteristics, including equivalent-oxide-thickness (EOT), stress-induced leakage current (SILC), and trap energy level. The mechanisms related to larger positive charge generation in the gate dielectric bulk can be attributed to La xTa y dual-doped HfON dielectric. The results of C- V measurement indicate that more negative charges are induced with increasing PDA temperature for the La xTa y dual-doped HfON dielectric. The charge current transport mechanisms through various dielectrics have been analyzed with current-voltage ( I- V) measurements under various temperatures. The current-conduction mechanisms of HfLaTaON dielectric at the low-, medium-, and high-electrical fields were dominated by Schottky emission (SE), Frenkel-Poole emission (F-P), and Fowler-Nordheim (F-N), respectively. A low trap energy level ( Φ trap) involved in Frenkel-Pool conduction in an HfLaTaON dielectric was estimated to be around 0.142 eV. Although a larger amount of positive charges generated in the HfLaTaON dielectric was obtained, the Φ trap of these positive charges in the HfLaTaON dielectric are shallow compared with HfON dielectric.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Positron beam studies of solids and surfaces: A summary

NASA Astrophysics Data System (ADS)

Coleman, P. G.

2006-02-01

A personal overview is given of the advances in positron beam studies of solids and surfaces presented at the 10th International Workshop on Positron Beams, held in Doha, Qatar, in March 2005. Solids studied include semiconductors, metals, alloys and insulators, as well as biophysical systems. Surface studies focussed on positron annihilation-induced Auger electron spectroscopy (PAES), but interesting applications of positron-surface interactions in fields as diverse as semiconductor technology and studies of the interstellar medium serve to illustrate once again the breadth of scientific endeavour covered by slow positron beam investigations.

n/a

NASA Image and Video Library

2003-06-10

Cadmium selenium Quantum Dots (QDs) are metal nanoparticles that fluoresce in a variety of colors determined by their size. QDs are solid state structures made of semiconductors or metals that confine a countable, small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well conducted region. Coupling QDs with antibodies can be used to make spectrally multiplexed immunoassays that test for a number of microbial contaminants using a single test.

SOI metal-oxide-semiconductor field-effect transistor photon detector based on single-hole counting.

PubMed

Du, Wei; Inokawa, Hiroshi; Satoh, Hiroaki; Ono, Atsushi

2011-08-01

In this Letter, a scaled-down silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is characterized as a photon detector, where photogenerated individual holes are trapped below the negatively biased gate and modulate stepwise the electron current flowing in the bottom channel induced by the positive substrate bias. The output waveforms exhibit clear separation of current levels corresponding to different numbers of trapped holes. Considering this capability of single-hole counting, a small dark count of less than 0.02 s(-1) at room temperature, and low operation voltage of 1 V, SOI MOSFET could be a unique photon-number-resolving detector if the small quantum efficiency were improved. © 2011 Optical Society of America

Electronic Transport Behaviors due to Charge Density Waves in Ni-Nb-Zr-H Glassy Alloys

NASA Astrophysics Data System (ADS)

Fukuhara, Mikio; Umemori, Yoshimasa

2013-11-01

The amorphous Ni-Nb-Zr-H glassy alloy containing subnanometer-sized icosahedral Zr5 Nb5Ni3 clusters exhibited four types of electronic phenomena: a metal/insulator transition, an electric current-induced voltage oscillation (Coulomb oscillation), giant capacitor behavior and an electron avalanche with superior resistivity. These findings could be excluded by charge density waves that the low-dimensional component of clusters, in which the atoms are lined up in chains along the [130] direction, plays important roles in various electron transport phenomena.

Effect of forming gas annealing on the degradation properties of Ge-based MOS stacks

NASA Astrophysics Data System (ADS)

Aguirre, F.; Pazos, S.; Palumbo, F. R. M.; Fadida, S.; Winter, R.; Eizenberg, M.

2018-04-01

The influence of forming gas annealing on the degradation at a constant stress voltage of multi-layered germanium-based Metal-Oxide-Semiconductor capacitors (p-Ge/GeOx/Al2O3/High-K/Metal Gate) has been analyzed in terms of the C-V hysteresis and flat band voltage as a function of both negative and positive stress fields. Significant differences were found for the case of negative voltage stress between the annealed and non-annealed samples, independently of the stressing time. It was found that the hole trapping effect decreases in the case of the forming gas annealed samples, indicating strong passivation of defects with energies close to the valence band existing in the oxide-semiconductor interface during the forming gas annealing. Finally, a comparison between the degradation dynamics of Germanium and III-V (n-InGaAs) MOS stacks is presented to summarize the main challenges in the integration of reliable Ge-III-V hybrid devices.

Commercially developed mixed-signal CMOS process features for application in advanced ROICs in 0.18μm technology node

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Hurwitz, Paul; Mann, Richard; Qamar, Yasir; Chaudhry, Samir; Zwingman, Robert; Howard, David; Racanelli, Marco

2012-06-01

Increasingly complex specifications for next-generation focal plane arrays (FPAs) require smaller pixels, larger array sizes, reduced power consumption and lower cost. We have previously reported on the favorable features available in the commercially available TowerJazz CA18 0.18μm mixed-signal CMOS technology platform for advanced read-out integrated circuit (ROIC) applications. In his paper, new devices in development for commercial purposes and which may have applications in advanced ROICs are reported. First, results of buried-channel 3.3V field effect transistors (FETs) are detailed. The buried-channel pFETs show flicker (1/f) noise reductions of ~5X in comparison to surface-channel pFETs along with a significant reduction of the body constant parameter. The buried-channel nFETs show ~2X reduction of 1/f noise versus surface-channel nFETs. Additional reduced threshold voltage nFETs and pFETs are also described. Second, a high-density capacitor solution with a four-stacked linear (metal-insulator-metal) MIM capacitor having capacitance density of 8fF/μm2 is reported. Additional stacking with MOS capacitor in a 5V tolerant process results in >50fC/μm2 charge density. Finally, one-time programmable (OTP) and multi-time programmable (MTP) non-volatile memory options in the CA18 technology platform are outlined.

Impact of oxygen plasma postoxidation process on Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Lechaux, Y.; Fadjie-Djomkam, A. B.; Bollaert, S.; Wichmann, N.

2016-09-01

Capacitance-voltage (C-V) measurements and x-ray photoelectron spectroscopy (XPS) analysis were performed in order to investigate the effect of a oxygen (O2) plasma after oxide deposition on the Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor structure passivated with ammonia NH4OH solution. From C-V measurements, an improvement of charge control is observed using the O2 plasma postoxidation process on In0.53Ga0.47As, while the minimum of interface trap density remains at a good value lower than 1 × 1012 cm-2 eV-1. From XPS measurements, we found that NH4OH passivation removes drastically the Ga and As native oxides on the In0.53Ga0.47As surface and the O2 plasma postoxidation process enables the reduction of interface re-oxidation after post deposition annealing (PDA) of the oxide. The advanced hypothesis is the formation of interfacial barrier between Al2O3 and In0.53Ga0.47As which prevents the diffusion of oxygen species into the semiconductor surface during PDA.

Polypyrrole Porous Micro Humidity Sensor Integrated with a Ring Oscillator Circuit on Chip

PubMed Central

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm2. The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C. PMID:22163459

Polypyrrole porous micro humidity sensor integrated with a ring oscillator circuit on chip.

PubMed

Yang, Ming-Zhi; Dai, Ching-Liang; Lu, De-Hao

2010-01-01

This study presents the design and fabrication of a capacitive micro humidity sensor integrated with a five-stage ring oscillator circuit on chip using the complimentary metal oxide semiconductor (CMOS) process. The area of the humidity sensor chip is about 1 mm(2). The humidity sensor consists of a sensing capacitor and a sensing film. The sensing capacitor is constructed from spiral interdigital electrodes that can enhance the sensitivity of the sensor. The sensing film of the sensor is polypyrrole, which is prepared by the chemical polymerization method, and the film has a porous structure. The sensor needs a post-CMOS process to coat the sensing film. The post-CMOS process uses a wet etching to etch the sacrificial layers, and then the polypyrrole is coated on the sensing capacitor. The sensor generates a change in capacitance when the sensing film absorbs or desorbs vapor. The ring oscillator circuit converts the capacitance variation of the sensor into the oscillation frequency output. Experimental results show that the sensitivity of the humidity sensor is about 99 kHz/%RH at 25 °C.

Poole Frenkel current and Schottky emission in SiN gate dielectric in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistors

NASA Astrophysics Data System (ADS)

Hanna, Mina J.; Zhao, Han; Lee, Jack C.

2012-10-01

We analyze the anomalous I-V behavior in SiN prepared by plasma enhanced chemical vapor deposition for use as a gate insulator in AlGaN/GaN metal insulator semiconductor heterostructure filed effect transistors (HFETs). We observe leakage current across the dielectric with opposite polarity with respect to the applied electric field once the voltage sweep reaches a level below a determined threshold. This is observed as the absolute minimum of the leakage current does not occur at minimum voltage level (0 V) but occurs earlier in the sweep interval. Curve-fitting analysis suggests that the charge-transport mechanism in this region is Poole-Frenkel current, followed by Schottky emission due to band bending. Despite the current anomaly, the sample devices have shown a notable reduction of leakage current of over 2 to 6 order of magnitudes compared to the standard Schottky HFET. We show that higher pressures and higher silane concentrations produce better films manifesting less trapping. This conforms to our results that we reported in earlier publications. We found that higher chamber pressure achieves higher sheet carrier concentration that was found to be strongly dependent on the trapped space charge at the SiN/GaN interface. This would suggest that a lower chamber pressure induces more trap states into the SiN/GaN interface.

MIS diode structure in As/+/ implanted CdS

NASA Technical Reports Server (NTRS)

Hutchby, J. A.

1977-01-01

Structure made by As implantation of carefully prepared high-conductivity CdS surfaces followed by Pt deposition and 450 C anneal display rectifying, although substantially different, I-V characteristics in the dark and during illumination with subband-gap light. Structures prepared in the same way on an unimplanted portion of the substrate have similar I-V characteristics, except that the forward turnover voltage for an illuminated unimplanted diode is much smaller than that for an implanted diode. It is suggested that the charge conduction in both structures is dominated by hole and/or electron tunneling through a metal-semiconductor potential barrier. The tunneling processes appear to be quite sensitive to subband-gap illumination, which causes the dramatic decreases of turnover voltages and apparent series resistances. The difference in turnover voltage appears to be caused by interface states between the Pt electrode and the implanted layer, which suggests a MIS model.

Ultraviolet and visible range plasmonics in the topological insulator Bi1.5Sb0.5Te1.8Se1.2

NASA Astrophysics Data System (ADS)

Ou, Jun-Yu; So, Jin-Kyu; Adamo, Giorgio; Sulaev, Azat; Wang, Lan; Zheludev, Nikolay I.

2014-10-01

The development of metamaterials, data processing circuits and sensors for the visible and ultraviolet parts of the spectrum is hampered by the lack of low-loss media supporting plasmonic excitations. This has driven the intense search for plasmonic materials beyond noble metals. Here we show that the semiconductor Bi1.5Sb0.5Te1.8Se1.2, also known as a topological insulator, is also a good plasmonic material in the blue-ultraviolet range, in addition to the already-investigated terahertz frequency range. Metamaterials fabricated from Bi1.5Sb0.5Te1.8Se1.2 show plasmonic resonances from 350 to 550 nm, while surface gratings exhibit cathodoluminescent peaks from 230 to 1,050 nm. The observed plasmonic response is attributed to the combination of bulk charge carriers from interband transitions and surface charge carriers of the topological insulator. The importance of our result is in the identification of new mechanisms of negative permittivity in semiconductors where visible range plasmonics can be directly integrated with electronics.

Photoluminescence enhancement of monolayer tungsten disulfide in complicated plasmonic microstructures

NASA Astrophysics Data System (ADS)

Zhou, Yi; Hu, Xiaoyong; Gao, Wei; Song, Hanfa; Chu, Saisai; Yang, Hong; Gong, Qihuang

2018-06-01

Two-dimensional van der Waals materials are interesting for fundamental physics exploration and device applications because of their attractive physical properties. Here, we report a strategy to realize photoluminescence (PL) enhancement of two-dimensional transition-metal dichalcogenides (TMDCs) in the visible range using a plasmonic microstructure with patterned gold nanoantennas and a metal-insulator-semiconductor-insulator-metal structure. The PL intensity was enhanced by a factor of two under Y-polarization due to the increased radiative decay rate by the surface plasmon radiation channel in the gold nanoantennas and the decreased nonradiative decay rate by suppressing exciton quenching in the SiO2 isolation layer. The fluorescence lifetime of monolayer tungsten disulfide in this structure was shorter than that of a sample without patterned gold nanoantennas. Tailoring the light-matter interactions between two-dimensional TMDCs and plasmonic nanostructures may provide highly efficient optoelectronic devices such as TMDC-based light emitters.

MULTIPLE SPARK GAP SWITCH

DOEpatents

Schofield, A.E.

1958-07-22

A multiple spark gap switch of unique construction is described which will permit controlled, simultaneous discharge of several capacitors into a load. The switch construction includes a disc electrode with a plurality of protuberances of generally convex shape on one surface. A firing electrode is insulatingly supponted In each of the electrode protuberances and extends substantially to the apex thereof. Individual electrodes are disposed on an insulating plate parallel with the disc electrode to form a number of spark gaps with the protuberances. These electrodes are each connected to a separate charged capacitor and when a voltage ls applied simultaneously between the trigger electrodes and the dlsc electrode, each spark gap fires to connect its capacitor to the disc electrode and a subsequent load.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Yafyasov, A. M., E-mail: yafyasov@gmail.com; Bogevolnov, V. B.; Ryumtsev, E. I.

A semiconductor—organic-insulator system with spatially distributed charge is created with a uniquely low density of fast surface states (N{sub ss}) at the interface. A system with N{sub ss} ≈ 5 × 10{sup 10} cm{sup –2} is obtained for the example of n-Ge and the physical characteristics of the interface are measured for this system with liquid and metal field electrodes. For a system with an organic insulator, the range of variation of the surface potential from enrichment of the space-charge region of the semiconductor to the inversion state is first obtained without changing the mechanism of interaction between the adsorbedmore » layer and the semiconductor surface. The effect of enhanced polarization of the space-charge region of the semiconductor occurs due to a change in the spatial structure of mobile charge in the organic dielectric layer. The system developed in the study opens up technological opportunities for the formation of a new generation of electronic devices based on organic film structures and for experimental modeling of the electronic properties of biological membranes.« less

In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation.

PubMed

Amor, S; André, N; Kilchytska, V; Tounsi, F; Mezghani, B; Gérard, P; Ali, Z; Udrea, F; Flandre, D; Francis, L A

2017-05-05

In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

In-situ thermal annealing of on-membrane silicon-on-insulator semiconductor-based devices after high gamma dose irradiation

NASA Astrophysics Data System (ADS)

Amor, S.; André, N.; Kilchytska, V.; Tounsi, F.; Mezghani, B.; Gérard, P.; Ali, Z.; Udrea, F.; Flandre, D.; Francis, L. A.

2017-05-01

In this paper, we investigate the recovery of some semiconductor-based components, such as N/P-type field-effect transistors (FETs) and a complementary metal-oxide-semiconductor (CMOS) inverter, after being exposed to a high total dose of gamma ray radiation. The employed method consists mainly of a rapid, low power and in situ annealing mitigation technique by silicon-on-insulator micro-hotplates. Due to the ionizing effect of the gamma irradiation, the threshold voltages showed an average shift of -580 mV for N-channel transistors, and -360 mV for P-MOSFETs. A 4 min double-cycle annealing of components with a heater temperature up to 465 °C, corresponding to a maximum power of 38 mW, ensured partial recovery but was not sufficient for full recovery. The degradation was completely recovered after the use of a built-in high temperature annealing process, up to 975 °C for 8 min corresponding to a maximum power of 112 mW, which restored the normal operating characteristics for all devices after their irradiation.

Neural Implants, Packaging for Biocompatible Implants, and Improving Fabricated Capacitors

NASA Astrophysics Data System (ADS)

Agger, Elizabeth Rose

We have completed the circuit design and packaging procedure for an NIH-funded neural implant, called a MOTE (Microscale Optoelectronically Transduced Electrode). Neural recording implants for mice have greatly advanced neuroscience, but they are often damaging and limited in their recording location. This project will result in free-floating implants that cause less damage, provide rapid electronic recording, and increase range of recording across the cortex. A low-power silicon IC containing amplification and digitization sub-circuits is powered by a dual-function gallium arsenide photovoltaic and LED. Through thin film deposition, photolithography, and chemical and physical etching, the Molnar Group and the McEuen Group (Applied and Engineering Physics department) will package the IC and LED into a biocompatible implant approximately 100microm3. The IC and LED are complete and we have begun refining this packaging procedure in the Cornell NanoScale Science & Technology Facility. ICs with 3D time-resolved imaging capabilities can image microorganisms and other biological samples given proper packaging. A portable, flat, easily manufactured package would enable scientists to place biological samples on slides directly above the Molnar group's imaging chip. We have developed a packaging procedure using laser cutting, photolithography, epoxies, and metal deposition. Using a flip-chip method, we verified the process by aligning and adhering a sample chip to a holder wafer. In the CNF, we have worked on a long-term metal-insulator-metal (MIM) capacitor characterization project. Former Fellow and continuing CNF user Kwame Amponsah developed the original procedure for the capacitor fabrication, and another former fellow, Jonilyn Longenecker, revised the procedure and began the arduous process of characterization. MIM caps are useful to clean room users as testing devices to verify electronic characteristics of their active circuitry. This project's objective is to determine differences in current-voltage (IV) and capacitor-voltage (CV) relationships across variations in capacitor size and dielectric type. This effort requires an approximately 20-step process repeated for two-to-six varieties (dependent on temperature and thermal versus plasma options) of the following dielectrics: HfO2, SiO2, Al2O3, TaOx, and TiO2.

A robust low quiescent current power receiver for inductive power transmission in bio implants

NASA Astrophysics Data System (ADS)

Helalian, Hamid; Pasandi, Ghasem; Jafarabadi Ashtiani, Shahin

2017-05-01

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC-DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC-DC converter has variable conversion ratios and synchronous controller that lets the DC-DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0-10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%.

Cadmium Selenium Testing for Microbial Contaminants

NASA Technical Reports Server (NTRS)

2003-01-01

Cadmium selenium Quantum Dots (QDs) are metal nanoparticles that fluoresce in a variety of colors determined by their size. QDs are solid state structures made of semiconductors or metals that confine a countable, small number of electrons into a small space. The confinement of electrons is achieved by the placement of some insulating material(s) around a central, well conducted region. Coupling QDs with antibodies can be used to make spectrally multiplexed immunoassays that test for a number of microbial contaminants using a single test.

Study of the Physics of Insulating Films as Related to the Reliability of Metal-Oxide Semiconductor Devices

DTIC Science & Technology

1980-11-01

materials work and sample preparation of D.W. Dong; the technical assistance of F.L. Pesavento and J.A. Calise; the assistance in device fabrication...FILMS D.J. DiMaria R. Ghez D.W. Dong I.B.M. Thomas J. Watson Research Center Yorktown Heights, New York 10598 Technical Assistance of F.L. Pesavento and... Pesavento and J.A. Calise; the assistance with gate metallizations by the Silicon Facility and Central Scientific Services at the T.J. Watson

M-I-S solar cell - Theory and experimental results

NASA Technical Reports Server (NTRS)

Childs, R.; Fortuna, J.; Geneczko, J.; Fonash, S. J.

1976-01-01

The paper presents an operating-mode analysis of an MIS solar cell and discusses the advantages which can arise as a result of the use of transport control, field shaping (increased n factor), and zero bias barrier height modification. It is noted that for an n-type semiconductor, it is relatively easy to obtain an enhanced n factor using acceptor-like states without an increase in diode saturation current, the converse being true for p-type semiconductors. Several MIS configurations are examined: an acceptor-like, localized state configuration producing field shaping and no change in diode saturation current, and acceptor-like localized configurations producing field shaping, with a decrease of diode saturation current, in one case, and an increase in the other.

One-Dimensional Nanostructures and Devices of II–V Group Semiconductors

PubMed Central

2009-01-01

The II–V group semiconductors, with narrow band gaps, are important materials with many applications in infrared detectors, lasers, solar cells, ultrasonic multipliers, and Hall generators. Since the first report on trumpet-like Zn3P2nanowires, one-dimensional (1-D) nanostructures of II–V group semiconductors have attracted great research attention recently because these special 1-D nanostructures may find applications in fabricating new electronic and optoelectronic nanoscale devices. This article covers the 1-D II–V semiconducting nanostructures that have been synthesized till now, focusing on nanotubes, nanowires, nanobelts, and special nanostructures like heterostructured nanowires. Novel electronic and optoelectronic devices built on 1-D II–V semiconducting nanostructures will also be discussed, which include metal–insulator-semiconductor field-effect transistors, metal-semiconductor field-effect transistors, andp–nheterojunction photodiode. We intent to provide the readers a brief account of these exciting research activities. PMID:20596452

Block copolymer-templated chemistry on Si, Ge, InP, and GaAs surfaces.

PubMed

Aizawa, Masato; Buriak, Jillian M

2005-06-29

Patterning of semiconductor surfaces is an area of intense interest, not only for technological applications, such as molecular electronics, sensing, cellular recognition, and others, but also for fundamental understanding of surface reactivity, general control over surface properties, and development of new surface reactivity. In this communication, we describe the use of self-assembling block copolymers to direct semiconductor surface chemistry in a spatially defined manner, on the nanoscale. The proof-of-principle class of reactions evaluated here is galvanic displacement, in which a metal ion, M+, is reduced to M0 by the semiconductor, including Si, Ge, InP, and GaAs. The block copolymer chosen has a polypyridine block which binds to the metal ions and brings them into close proximity with the surface, at which point they undergo reaction; the pattern of resulting surface chemistry, therefore, mirrors the nanoscale structure of the parent block copolymer. This chemistry has the added advantage of forming metal nanostructures that result in an alloy or intermetallic at the interface, leading to strongly bound metal nanoparticles that may have interesting electronic properties. This approach has been shown to be very general, functioning on a variety of semiconductor substrates for both silver and gold deposition, and is being extended to organic and inorganic reactions on a variety of conducting, semiconducting, and insulating substrates.

Switchable diode effect in oxygen vacancy-modulated SrTiO3 single crystal

NASA Astrophysics Data System (ADS)

Pan, Xinqiang; Shuai, Yao; Wu, Chuangui; Luo, Wenbo; Sun, Xiangyu; Zeng, Huizhong; Bai, Xiaoyuan; Gong, Chaoguan; Jian, Ke; Zhang, Lu; Guo, Hongliang; Tian, Benlang; Zhang, Wanli

2017-09-01

SrTiO3 (STO) single crystal wafer was annealed in vacuum, and co-planar metal-insulator-metal structure of Pt/Ti/STO/Ti/Pt were formed by sputtering Pt/Ti electrodes onto the surface of STO after annealing. The forming-free resistive switching behavior with self-compliance property was observed in the sample. The sample showed switchable diode effect, which is explained by a simple model that redistribution of oxygen vacancies (OVs) under the external electric field results in the formation of n-n+ junction or n+-n junction (n donated n-type semiconductor; n+ donated heavily doped n-type semiconductor). The self-compliance property is also interpreted by the formation of n-n+/n+-n junction caused by the migration of the OVs under the electric field.

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

NASA Astrophysics Data System (ADS)

Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

2017-06-01

Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

Reusable fast opening switch

DOEpatents

Van Devender, J.P.; Emin, D.

1983-12-21

A reusable fast opening switch for transferring energy, in the form of a high power pulse, from an electromagnetic storage device such as an inductor into a load. The switch is efficient, compact, fast and reusable. The switch comprises a ferromagnetic semiconductor which undergoes a fast transition between conductive and metallic states at a critical temperature and which undergoes the transition without a phase change in its crystal structure. A semiconductor such as europium rich europhous oxide, which undergoes a conductor to insulator transition when it is joule heated from its conductor state, can be used to form the switch.

SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

NASA Astrophysics Data System (ADS)

Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

2018-06-01

Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

Observation of turnover of spontaneous polarization in ferroelectric layer of pentacene/poly-(vinylidene-trifluoroethylene) double-layer capacitor under photo illumination by optical second-harmonic generation measurement

NASA Astrophysics Data System (ADS)

Shi, Zhemin; Taguchi, Dai; Manaka, Takaaki; Iwamoto, Mitsumasa

2016-04-01

The details of turnover process of spontaneous polarization and associated carrier motions in indium-tin oxide/poly-(vinylidene-trifluoroethylene)/pentacene/Au capacitor were analyzed by coupling displacement current measurement (DCM) and electric-field-induced optical second-harmonic generation (EFISHG) measurement. A model was set up from DCM results to depict the relationship between electric field in semiconductor layer and applied external voltage, proving that photo illumination effect on the spontaneous polarization process lied in variation of semiconductor conductivity. The EFISHG measurement directly and selectively probed the electric field distribution in semiconductor layer, modifying the model and revealing detailed carrier behaviors involving photo illumination effect, dipole reversal, and interfacial charging in the device. A further decrease of DCM current in the low voltage region under illumination was found as the result of illumination effect, and the result was argued based on the changing of the total capacitance of the double-layer capacitors.

Is DNA a metal, semiconductor or insulator? A theoretical approach

NASA Astrophysics Data System (ADS)

Rey-Gonzalez, Rafael; Fonseca-Romero, Karen; Plazas, Carlos; Grupo de Óptica e Información Cuántica Team

Over the last years, scientific interest for designing and making low dimensional electronic devices with traditional or novel materials has been increased. These experimental and theoretical researches in electronic properties at molecular scale are looking for developing efficient devices able to carry out tasks which are currently done by silicon transistors and devices. Among the new materials DNA strands are highlighted, but the experimental results have been contradictories pointing to behaviors as conductor, semiconductor or insulator. To contribute to the understanding of the origin of the disparity of the measurements, we perform a numerical calculation of the electrical conductance of DNA segments, modeled as 1D disordered finite chains. The system is described into a Tight binding model with nearest neighbor interactions and a s orbital per site. Hydration effects are included as random variations of self-energies. The electronic current as a function of applied bias is calculated using Launder formalism, where the transmission probability is determined into the transfer matrix formalism. We find a conductor-to-semiconductor-to-insulator transition as a function of the three effects taken into account: chain size, intrinsic disorder, and hydration We thank Fundación para la Promoción de la Investigación y la Tecnología, Colombia, and Dirección de Investigación de Bogotá, Universidad Nacional de Colombia, for partial financial support.

Aluminum nitride insulating films for MOSFET devices

NASA Technical Reports Server (NTRS)

Lewicki, G. W.; Maserjian, J.

1972-01-01

Application of aluminum nitrides as electrical insulator for electric capacitors is discussed. Electrical properties of aluminum nitrides are analyzed and specific use with field effect transistors is defined. Operational limits of field effect transistors are developed.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Capacitor electrode stimulates nerve or muscle without oxidation-reduction reactions.

PubMed

Guyton, D L; Hambrecht, F T

1973-07-06

Porous tantalum disks, available as "slugs" from the capacitor industry, have large available surface area and a thin insulating coating of tantalum pentoxide. When implanted, they fill with extracellular fluid and operate as capacitor-stimulating electrodes having high capacitance per unit volume. Capable of stimulating excitable tissute without generating electrochemical by-products, these electrodes should provide a safer interface between neural prosthetic devices and human tissue.

Improvement of interfacial and electrical properties of Al2O3/ n-Ga0.47In0.53As for III-V impact ionization MOSFETs

NASA Astrophysics Data System (ADS)

Lechaux, Y.; Fadjie, A.; Bollaert, S.; Talbo, V.; Mateos, J.; González, T.; Vasallo, B. G.; Wichmann, N.

2015-10-01

In this work, Metal - Oxide - Semiconductor Capacitors (MOSCaps) based on Al2O3/ n-Ga0.47In0.53As interface have been studied. In order to have high MOSFETs performance, it is necessary to improve the semiconductor - oxide interface quality. It is observed that the (NH4)2S passivation shows lower interface trap density in the order of 6×1011cm-2.eV-1. Also, it is observed that O2 plasma densification after a passivation in a NH4OH solution improves the electrical behaviour of the charge control. Low interface trap density in the order of 1×1012cm-2.eV-1 was obtained for different treatments presented in this work.

Transition temperature from band to hopping direct current conduction in crystalline semiconductors with hydrogen-like impurities: Heat versus Coulomb attraction

NASA Astrophysics Data System (ADS)

Poklonski, N. A.; Vyrko, S. A.; Poklonskaya, O. N.; Zabrodskii, A. G.

2011-12-01

For nondegenerate bulk semiconductors, we have used the virial theorem to derive an expression for the temperature Tj of the transition from the regime of "free" motion of electrons in the c-band (or holes in the υ-band) to their hopping motion between donors (or acceptors). Distribution of impurities over the crystal was assumed to be of the Poisson type, while distribution of their energy levels was assumed to be of the Gaussian type. Our conception of the virial theorem implementation is that the transition from the band-like conduction to hopping conduction occurs when the average kinetic energy of an electron in the c-band (hole in the υ-band) is equal to the half of the absolute value of the average energy of the Coulomb interaction of an electron (hole) with the nearest neighbor ionized donor (acceptor). Calculations of Tj according to our model agree with experimental data for crystals of Ge, Si, diamond, etc. up to the concentrations of a hydrogen-like impurity, at which the phase insulator-metal transition (Mott transition) occurs. Under the temperature Th ≈ Tj /3, when the nearest neighbor hopping conduction via impurity atoms dominates, we obtained expressions for the electrostatic field screening length Λh in the Debye-Hückel approximation, taking into account a nonzero width of the impurity energy band. It is shown that the measurements of quasistatic capacitance of the semiconductor in a metal-insulator-semiconductor structure in the regime of the flat bands at the temperature Th allow to determine the concentration of doping impurity or its compensation ratio by knowing Λh.

2014 NEPP Tasks Update for Ceramic and Tantalum Capacitors

NASA Technical Reports Server (NTRS)

Teverovsky, Alexander A.

2014-01-01

Presentation describes recent development in research on MnO2, wet, and polymer tantalum capacitors. Low-voltage failures in multilayer ceramic capacitors and techniques to reveal precious metal electrode (PME) and base metal electrode (BME) capacitors with cracks are discussed. A voltage breakdown technique is suggested to select high quality low-voltage BME ceramic capacitors.

Nanoscale control of an interfacial metal-insulator transition at room temperature.

PubMed

Cen, C; Thiel, S; Hammerl, G; Schneider, C W; Andersen, K E; Hellberg, C S; Mannhart, J; Levy, J

2008-04-01

Experimental and theoretical investigations have demonstrated that a quasi-two-dimensional electron gas (q-2DEG) can form at the interface between two insulators: non-polar SrTiO3 and polar LaTiO3 (ref. 2), LaAlO3 (refs 3-5), KTaO3 (ref. 7) or LaVO3 (ref. 6). Electronically, the situation is analogous to the q-2DEGs formed in semiconductor heterostructures by modulation doping. LaAlO3/SrTiO3 heterostructures have recently been shown to exhibit a hysteretic electric-field-induced metal-insulator quantum phase transition for LaAlO3 thicknesses of 3 unit cells. Here, we report the creation and erasure of nanoscale conducting regions at the interface between two insulating oxides, LaAlO3 and SrTiO3. Using voltages applied by a conducting atomic force microscope (AFM) probe, the buried LaAlO3/SrTiO3 interface is locally and reversibly switched between insulating and conducting states. Persistent field effects are observed using the AFM probe as a gate. Patterning of conducting lines with widths of approximately 3 nm, as well as arrays of conducting islands with densities >10(14) inch(-2), is demonstrated. The patterned structures are stable for >24 h at room temperature.

Interface charge trapping induced flatband voltage shift during plasma-enhanced atomic layer deposition in through silicon via

NASA Astrophysics Data System (ADS)

Li, Yunlong; Suhard, Samuel; Van Huylenbroeck, Stefaan; Meersschaut, Johan; Van Besien, Els; Stucchi, Michele; Croes, Kristof; Beyer, Gerald; Beyne, Eric

2017-12-01

A Through Silicon Via (TSV) is a key component for 3D integrated circuit stacking technology, and the diameter of a TSV keeps scaling down to reduce the footprint in silicon. The TSV aspect ratio, defined as the TSV depth/diameter, tends to increase consequently. Starting from the aspect ratio of 10, to improve the TSV sidewall coverage and reduce the process thermal budget, the TSV dielectric liner deposition process has evolved from sub-atmospheric chemical vapour deposition to plasma-enhanced atomic layer deposition (PE-ALD). However, with this change, a strong negative shift in the flatband voltage is observed in the capacitance-voltage characteristic of the vertical metal-oxide-semiconductor (MOS) parasitic capacitor formed between the TSV copper metal and the p-Si substrate. And, no shift is present in planar MOS capacitors manufactured with the same PE-ALD oxide. By comparing the integration process of these two MOS capacitor structures, and by using Elastic Recoil Detection to study the elemental composition of our films, it is found that the origin of the negative flatband voltage shift is the positive charge trapping at the Si/SiO2 interface, due to the positive PE-ALD reactants confined to the narrow cavity of high aspect ratio TSVs. This interface charge trapping effect can be effectively mitigated by high temperature annealing. However, this is limited in the real process due to the high thermal budget. Further investigation on liner oxide process optimization is needed.

Advanced CMOS Radiation Effects Testing and Analysis

NASA Technical Reports Server (NTRS)

Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.;

The Use of Ion Implantation for Materials Processing.

DTIC Science & Technology

1980-10-06

consists of a series of sections, each section being an annular insulator (glass) and a shaped metal electrode (polished aluminum ) cemented together. A...depending on the ion species, semiconductor material, attached materials (such as aluminum leads), implantation energy, and dose; but some devices are...concentration of subsurface carbon. Appearing directly beneath the oxide layer, the C concentration first reaches a maximum of about five times the bulk

Development of the Field-Induced Electron Injection and Impact Ionization (F4I) Technique for Radiation Hardness Testing of MOS (Metal-Oxide-Semiconductor) Gate Insulators.

DTIC Science & Technology

1988-03-01

Applesoft language, a variant of floating-point BASIC that is supplied with the computer. As an intepreted language, Apple- soft BASIC executes fairly...fit with (VI , II ) array. I 8400 Sound bell and display warning when current limit exceeded. 8500-8510 Output HV pulse, read and display amplitude

Method for disclosing invisible physical properties in metal-ferroelectric-insulator-semiconductor gate stacks

NASA Astrophysics Data System (ADS)

Sakai, Shigeki; Zhang, Wei; Takahashi, Mitsue

2017-04-01

In metal-ferroelectric-insulator-semiconductor gate stacks of ferroelectric-gate field effect transistors (FeFETs), it is impossible to directly obtain curves of polarization versus electric field (P f-E f) in the ferroelectric layer. The P f-E f behavior is not simple, i.e. the P f-E f curves are hysteretic and nonlinear, and the hysteresis curve width depends on the electric field scan amplitude. Unless the P f-E f relation is known, the field E f strength cannot be solved when the voltage is applied between the gate meal and the semiconductor substrate, and thus P f-E f cannot be obtained after all. In this paper, the method for disclosing the relationships among the polarization peak-to-peak amplitude (2P mm_av), the electric field peak-to-peak amplitude (2E mm_av), and the memory window (E w) in units of the electric field is presented. To get P mm_av versus E mm_av, FeFETs with different ferroelectric-layer thicknesses should be prepared. Knowing such essential physical parameters is helpful and in many cases enough to quantitatively understand the behavior of FeFETs. The method is applied to three groups. The first one consists of SrBi2Ta2O9-based FeFETs. The second and third ones consist of Ca x Sr1-x Bi2Ta2O9-based FeFETs made by two kinds of annealing. The method can clearly differentiate the characters of the three groups. By applying the method, ferroelectric relationships among P mm_av, E mm_av, and E w are well classified in the three groups according to the difference of the material kinds and the annealing conditions. The method also evaluates equivalent oxide thickness (EOT) of a dual layer of a deposited high-k insulator and a thermally-grown SiO2-like interfacial layer (IL). The IL thickness calculated by the method is consistent with cross-sectional image of the FeFETs observed by a transmission electron microscope. The method successfully discloses individual characteristics of the ferroelectric and the insulator layers hidden in the gate stack of a FeFET.

Photoluminescent Au-Ge composite nanodots formation on SiO2 surface by ion induced dewetting

NASA Astrophysics Data System (ADS)

Datta, D. P.; Siva, V.; Singh, A.; Kanjilal, D.; Sahoo, P. K.

2017-09-01

Medium energy ion irradiation on a bilayer of Au and Ge on SiO2 is observed to result in gradual morphological evolution from an interconnected network to a nanodot array on the insulator surface. Structural and compositional analyses reveal composite nature of the nanodots, comprising of both Au and Ge. The growing nanostructures are found to be photoluminescent at room temperature where the emission intensity and wavelengths vary with morphology. The growth of such nanostructures can be understood in terms of dewetting of the metal layer under ion irradiation due to ion-induced melting along the ion tracks. The visible PL emission is found to be related with evolution of the Au-Ge nanodots. The study indicates a route towards single step synthesis of metal-semiconductor nanodots on insulator surface.

Study of the Physics of Insulating Films as Related to the Reliability of Metal-Oxide Semiconductor Devices

DTIC Science & Technology

1981-07-01

and Berglund (13,5). Pulsed electron flow is induced through the SiO 2 film by rf avalanche in the p-silicon surface depletion layer, and the rf voltage...were then evaporated through a shadow mask from an rf heated crucible in a vacuum chamber under 10 - 6 Torr pressure. Finally, a post-metallization...12.) P. Williams and J.E. Baker, Appl. Phys. Lett. 36, 842 (1980). 13.) H.H. Anderson, Appl. Phys. 18, 131 (1979). 14.) D.R. Young, D.J. DiMaria, W.R

Microwave-Assisted Size Control of Colloidal Nickel Nanocrystals for Colloidal Nanocrystals-Based Non-volatile Memory Devices

NASA Astrophysics Data System (ADS)

Yadav, Manoj; Velampati, Ravi Shankar R.; Mandal, D.; Sharma, Rohit

2018-03-01

Colloidal synthesis and size control of nickel (Ni) nanocrystals (NCs) below 10 nm are reported using a microwave synthesis method. The synthesised colloidal NCs have been characterized using x-ray diffraction, transmission electron microscopy (TEM) and dynamic light scattering (DLS). XRD analysis highlights the face centred cubic crystal structure of synthesised NCs. The size of NCs observed using TEM and DLS have a distribution between 2.6 nm and 10 nm. Furthermore, atomic force microscopy analysis of spin-coated NCs over a silicon dioxide surface has been carried out to identify an optimum spin condition that can be used for the fabrication of a metal oxide semiconductor (MOS) non-volatile memory (NVM) capacitor. Subsequently, the fabrication of a MOS NVM capacitor is reported to demonstrate the potential application of colloidal synthesized Ni NCs in NVM devices. We also report the capacitance-voltage (C-V) and capacitance-time (C-t) response of the fabricated MOS NVM capacitor. The C-V and C-t characteristics depict a large flat band voltage shift (V FB) and high retention time, respectively, which indicate that colloidal Ni NCs are excellent candidates for applications in next-generation NVM devices.

Origin of temperature dependent conduction of current from n-4H-SiC into silicon dioxide films at high electric fields

NASA Astrophysics Data System (ADS)

Xiang, An; Xu, Xingliang; Zhang, Lin; Li, Zhiqiang; Li, Juntao; Dai, Gang

2018-02-01

The conduction of current from n-4H-SiC into pyrogenic and dry oxidized films is studied. Anomalous current conduction was observed at a high electric field above 8 MV/cm for dry oxidized metal-oxide-semiconductor (MOS) capacitors, which cannot be interpreted in the framework of pure Fowler-Nordheim tunneling. The temperature-dependent current measurement and density of interface trap estimated from the hi-lo method for the SiO2/4H-SiC interface revealed that the combined current conduction of Fowler-Nordheim and Poole-Frenkel emission is responsible for the current conduction in both pyrogenic and dry oxidized MOS capacitors. Furthermore, the origin of temperature dependent current conduction is the Poole-Frenkel emission via the carbon pair defect trap level at 1.3 eV below the conduction band edge of SiO2. In addition, with the dry oxidized capacitors, the enhanced temperature dependent current above 8 MV/cm is attributed to the PF emission via a trap level at 1.47 eV below the conduction band edge of SiO2, which corresponds to another configuration of a carbon pair defect in SiO2 films.

Tunable Electron and Hole Injection Enabled by Atomically Thin Tunneling Layer for Improved Contact Resistance and Dual Channel Transport in MoS2/WSe2 van der Waals Heterostructure.

PubMed

Khan, Muhammad Atif; Rathi, Servin; Lee, Changhee; Lim, Dongsuk; Kim, Yunseob; Yun, Sun Jin; Youn, Doo Hyeb; Kim, Gil-Ho

2018-06-25

Two-dimensional (2D) materials based heterostructures provide a unique platform where interaction between stacked 2D layers can enhance the electrical and opto-electrical properties as well as give rise to interesting new phenomena. Here, operation of a van der Waals heterostructure device comprising of vertically stacked bi-layer MoS 2 and few layered WSe 2 has been demonstrated in which atomically thin MoS 2 layer has been employed as a tunneling layer to the underlying WSe 2 layer. In this way, simultaneous contacts to both MoS 2 and WSe 2 2D layers have been established by forming direct MS (metal semiconductor) to MoS 2 and tunneling based MIS (metal insulator semiconductor) contacts to WSe 2 , respectively. The use of MoS 2 as a dielectric tunneling layer results in improved contact resistance (80 kΩ-µm) for WSe 2 contact, which is attributed to reduction in effective Schottky barrier height and is also confirmed from the temperature dependent measurement. Further, this unique contact engineering and type II band alignment between MoS 2 and WSe 2 enables a selective and independent carrier transport across the respective layers. This contact engineered dual channel heterostructure exhibits an excellent gate control and both channel current and carrier types can be modulated by the vertical electric field of the gate electrode, which is also reflected in on/off ratio of 10 4 for both electrons (MoS 2 ) and holes (WSe 2 ) channels. Moreover, the charge transfer at the heterointerface is studied quantitatively from the shift in the threshold voltage of the pristine MoS 2 and heterostructure device, which agrees with the carrier recombination induced optical quenching as observed in the Raman spectra of the pristine and heterostructure layers. This observation of dual channel ambipolar transport enabled by the hybrid tunneling contacts and strong interlayer coupling can be utilized for high performance opto-electrical devices and applications.

Temperature dependence of frequency dispersion in III–V metal-oxide-semiconductor C-V and the capture/emission process of border traps

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vais, Abhitosh, E-mail: Abhitosh.Vais@imec.be; Martens, Koen; DeMeyer, Kristin

2015-08-03

This paper presents a detailed investigation of the temperature dependence of frequency dispersion observed in capacitance-voltage (C-V) measurements of III-V metal-oxide-semiconductor (MOS) devices. The dispersion in the accumulation region of the capacitance data is found to change from 4%–9% (per decade frequency) to ∼0% when the temperature is reduced from 300 K to 4 K in a wide range of MOS capacitors with different gate dielectrics and III-V substrates. We show that such significant temperature dependence of C-V frequency dispersion cannot be due to the temperature dependence of channel electrostatics, i.e., carrier density and surface potential. We also show that the temperaturemore » dependence of frequency dispersion, and hence, the capture/emission process of border traps can be modeled by a combination of tunneling and a “temperature-activated” process described by a non-radiative multi-phonon model, instead of a widely believed single-step elastic tunneling process.« less

Future Development of Dense Ferroelectric Memories for Space Applications

NASA Technical Reports Server (NTRS)

Philpy, Stephen C.; Derbenwick, Gary F.

2001-01-01

The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.

Presence of Peierls pairing and absence of insulator-to-metal transition in VO2 (A): a structure-property relationship study.

PubMed

Popuri, S R; Artemenko, A; Decourt, R; Villesuzanne, A; Pollet, M

2017-03-01

Layered vanadium oxides have been extensively explored due to their interesting metal-insulator transitions and energy conversion/storage applications. In the present study, we have successfully synthesized VO 2 (A) polymorph powder samples by a single-step hydrothermal synthesis process and consolidated them using spark plasma sintering. The structural and electronic properties of VO 2 (A) are measured over a large temperature range from liquid helium, across the structural transition (400-440 K) and up to 500 K. The structural analysis around this transition reveals an antiferrodistorsive to partially ferrodistorsive ordering upon cooling. It is followed by a progressive antiferromagnetic spin pairing which fully settles at about 150 K. The transport measurements show that, in contrast to the rutile archetype VO 2 (R/M1), the structural transition comes with a transition from semiconductor to band-type insulator. Under these circumstances, we propose a scenario with a high temperature antiferrodistorsive paramagnetic semiconducting phase, followed by an intermediate regime with a partially ferrodistorsive paramagnetic semiconducting phase, and finally a low temperature partially ferrodistorsive antiferromagnetic band insulator phase with a possible V-V Peierls-type pairing.

Charge and spin diffusion on the metallic side of the metal-insulator transition: A self-consistent approach

NASA Astrophysics Data System (ADS)

Wellens, Thomas; Jalabert, Rodolfo A.

2016-10-01

We develop a self-consistent theory describing the spin and spatial electron diffusion in the impurity band of doped semiconductors under the effect of a weak spin-orbit coupling. The resulting low-temperature spin-relaxation time and diffusion coefficient are calculated within different schemes of the self-consistent framework. The simplest of these schemes qualitatively reproduces previous phenomenological developments, while more elaborate calculations provide corrections that approach the values obtained in numerical simulations. The results are universal for zinc-blende semiconductors with electron conductance in the impurity band, and thus they are able to account for the measured spin-relaxation times of materials with very different physical parameters. From a general point of view, our theory opens a new perspective for describing the hopping dynamics in random quantum networks.

Selective control of electron and hole tunneling in 2D assembly

PubMed Central

Chu, Dongil; Lee, Young Hee; Kim, Eun Kyu

2017-01-01

Recent discoveries in the field of two-dimensional (2D) materials have led to the demonstration of exotic devices. Although they have new potential applications in electronics, thermally activated transport over a metal/semiconductor barrier sets physical subthermionic limitations. The challenge of realizing an innovative transistor geometry that exploits this concern remains. A new class of 2D assembly (namely, “carristor”) with a configuration similar to the metal-insulator-semiconductor structure is introduced in this work. Superior functionalities, such as a current rectification ratio of up to 400,000 and a switching ratio of higher than 106 at room temperature, are realized by quantum-mechanical tunneling of majority and minority carriers across the barrier. These carristors have a potential application as the fundamental building block of low–power consumption electronics. PMID:28439554

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Enhanced von Weizsäcker Wang-Govind-Carter kinetic energy density functional for semiconductors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shin, Ilgyou; Carter, Emily A., E-mail: eac@princeton.edu

2014-05-14

We propose a new form of orbital-free (OF) kinetic energy density functional (KEDF) for semiconductors that is based on the Wang-Govind-Carter (WGC99) nonlocal KEDF. We enhance within the latter the semi-local von Weizsäcker KEDF term, which is exact for a single orbital. The enhancement factor we introduce is related to the extent to which the electron density is localized. The accuracy of the new KEDF is benchmarked against Kohn-Sham density functional theory (KSDFT) by comparing predicted energy differences between phases, equilibrium volumes, and bulk moduli for various semiconductors, along with metal-insulator phase transition pressures. We also compare point defect andmore » (100) surface energies in silicon for a broad test of its applicability. This new KEDF accurately reproduces the exact non-interacting kinetic energy of KSDFT with only one additional adjustable parameter beyond the three parameters in the WGC99 KEDF; it exhibits good transferability between semiconducting to metallic silicon phases and between various III-V semiconductors without parameter adjustment. Overall, this KEDF is more accurate than previously proposed OF KEDFs (e.g., the Huang-Carter (HC) KEDF) for semiconductors, while the computational efficiency remains at the level of the WGC99 KEDF (several hundred times faster than the HC KEDF). This accurate, fast, and transferable new KEDF holds considerable promise for large-scale OFDFT simulations of metallic through semiconducting materials.« less

Capacitor-type micrometeoroid detectors

NASA Technical Reports Server (NTRS)

Wortman, J. J.; Griffis, D. P.; Bryan, S. R.; Kinard, W.

1986-01-01

The metal oxide semiconductor (MOS) capacitor micrometeroid detector consists of a thin dielectric capacitor fabricated on a silicon wafer. In operation, the device is charged to a voltage level sufficiently near breakdown that micrometeoroid impacts will cause dielectric deformation or heating and subsequent arc-over at the point of impact. Each detector is capable of recording multiple impacts because of the self-healing characteristics of the device. Support instrumentation requirements consist of a voltage source and pulse counters that monitor the pulse of recharging current following every impact. An investigation has been conducted in which 0.5 to 5 micron diameter carbonized iron spheres traveling at velocities of 4 to 10 Km/sec were impacted on to detectors with either a dielectric thickness of 0.4 or 1.0 micron. This study demonstrated that an ion microprobe tuned to sufficiently high resolution can detect Fe remaining on the detector after the impact. Furthermore, it is also possible to resolve Fe ion images free of mass interferences from Si, for example, giving its spatial distribution after impact. Specifically this technique has shown that significant amounts of impacting particles remain in the crater and near it which can be analyzed for isotopic content. Further testing and calibration could lead to quantitive analysis. This study has shown that the capacitor type micrometeroid detector is capable of not only time and flux measurements but can also be used for isotopic analysis.

Coated semiconductor devices for neutron detection

DOEpatents

Klann, Raymond T.; McGregor, Douglas S.

2002-01-01

A device for detecting neutrons includes a semi-insulated bulk semiconductor substrate having opposed polished surfaces. A blocking Schottky contact comprised of a series of metals such as Ti, Pt, Au, Ge, Pd, and Ni is formed on a first polished surface of the semiconductor substrate, while a low resistivity ("ohmic") contact comprised of metals such as Au, Ge, and Ni is formed on a second, opposed polished surface of the substrate. In one embodiment, n-type low resistivity pinout contacts comprised of an Au/Ge based eutectic alloy or multi-layered Pd/Ge/Ti/Au are also formed on the opposed polished surfaces and in contact with the Schottky and ohmic contacts. Disposed on the Schottky contact is a neutron reactive film, or coating, for detecting neutrons. The coating is comprised of a hydrogen rich polymer, such as a polyolefin or paraffin; lithium or lithium fluoride; or a heavy metal fissionable material. By varying the coating thickness and electrical settings, neutrons at specific energies can be detected. The coated neutron detector is capable of performing real-time neutron radiography in high gamma fields, digital fast neutron radiography, fissile material identification, and basic neutron detection particularly in high radiation fields.

Prediction of weak and strong topological insulators in layered semiconductors.

NASA Astrophysics Data System (ADS)

Felser, Claudia

2013-03-01

We investigate a new class of ternary materials such as LiAuSe and KHgSb with a honeycomb structure in Au-Se and Hg-Sb layers. We demonstrate the band inversion in these materials similar to HgTe, which is a strong precondition for existence of the topological surface states. In contrast with graphene, these materials exhibit strong spin-orbit coupling and a small direct band gap at the point. Since these materials are centrosymmetric, it is straightforward to determine the parity of their wave functions, and hence their topological character. Surprisingly, the compound with strong spin-orbit coupling (KHgSb) is trivial, whereas LiAuSe is found to be a topological insulator. However KHgSb is a weak topological insulators in case of an odd number of layers in the primitive unit cell. Here, the single-layered KHgSb shows a large bulk energy gap of 0.24 eV. Its side surface hosts metallic surface states, forming two anisotropic Dirac cones. Although the stacking of even-layered structures leads to trivial insulators, the structures can host a quantum spin Hall layer with a large bulk gap, if an additional single layer exists as a stacking fault in the crystal. The reported honeycomb compounds can serve as prototypes to aid in the finding of new weak topological insulators in layered small-gap semiconductors. In collaboration with Binghai Yan, Lukas Müchler, Hai-Jun Zhang, Shou-Cheng Zhang and Jürgen Kübler.

Method for producing a hybridization of detector array and integrated circuit for readout

NASA Technical Reports Server (NTRS)

Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

1993-01-01

A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

Slow dynamics of electron glasses: The role of disorder

NASA Astrophysics Data System (ADS)

Ovadyahu, Z.

2017-04-01

We examine in this work the role of disorder in contributing to the sluggish relaxation observed in intrinsic electron glasses. Our approach is guided by several empirical observations: First and foremost, Anderson localization is a pre-requisite for observing these nonequilibrium phenomena. Secondly, sluggish relaxation appears to favor Anderson insulators with relatively large Fermi energies (hence proportionally large disorder). These observations motivated us to consider a way to measure the underlying disorder in a realistic Anderson insulator. Optical studies using a series of amorphous indium oxide (InxO ) establish a simple connection between carrier concentration and the disorder necessary to approach the metal-insulator transition from the insulating side. This is used to estimate the typical magnitude of the quenched potential fluctuation in the electron-glass phase of this system. The implications of our findings on the slow dynamics of Anderson insulators are discussed. In particular, the reason for the absence of a memory dip and the accompanying electron-glass effects in lightly-doped semiconductors emerges as a natural consequence of their weak disorder.

Cu-Induced Dielectric Breakdown of Porous Low-Dielectric-Constant Film

NASA Astrophysics Data System (ADS)

Cheng, Yi-Lung; Lee, Chih-Yen; Huang, Yao-Liang; Sun, Chung-Ren; Lee, Wen-Hsi; Chen, Giin-Shan; Fang, Jau-Shiung; Phan, Bach Thang

2017-06-01

Dielectric breakdown induced by Cu ion migration in porous low- k dielectric films has been investigated in alternating-polarity bias conditions using a metal-insulator-metal capacitor with Cu top metal electrode. The experimental results indicated that Cu ions migrated into the dielectric film under stress with positive polarity, leading to weaker dielectric strength and shorter time to failure (TTF). In the alternating-polarity test, the measured TTFs increased with decreasing stressing frequency, implying backward migration of Cu ions during reverse-bias stress. Additionally, compared with a direct-current stress condition, the measured TTFs were higher as the frequency was decreased to 10-2 Hz. The electric-field acceleration factor for porous low- k dielectric film breakdown in the alternating-polarity test was also found to increase. This Cu backward migration effect is effective when the stressing time under negative polarity is longer than 0.1 s.

Thermal strain-induced dielectric anisotropy in Ba0.7Sr0.3TiO3 thin films grown on silicon-based substrates

NASA Astrophysics Data System (ADS)

Zhu, X. H.; Guigues, B.; Defaÿ, E.; Dubarry, C.; Aïd, M.

2009-07-01

Dielectric properties of Ba0.7Sr0.3TiO3 (BST) thin films, which were prepared on silicon-based substrates by ion beam sputtering and postdeposition annealing method, were systematically investigated in different electrode configurations of metal-insulator-metal and coplanar interdigital capacitors. It was found that a large dielectric anisotropy exists in the films with better in-plane dielectric properties (higher dielectric permittivity and tunability) than those along the out-of-plane direction. The observed anisotropic dielectric responses are explained qualitatively in terms of a thermal strain effect that is related to dissimilar film strains along the in-plane and out-of-plane directions. Another reason for the dielectric anisotropy is due to different influences of the interfacial low-dielectric layer between the BST film and the substrate (metal electrode).

Power module assembly

DOEpatents

Campbell, Jeremy B [Torrance, CA; Newson, Steve [Redondo Beach, CA

2011-11-15

A power module assembly of the type suitable for deployment in a vehicular power inverter, wherein the power inverter has a grounded chassis, is provided. The power module assembly comprises a conductive base layer electrically coupled to the chassis, an insulating layer disposed on the conductive base layer, a first conductive node disposed on the insulating layer, a second conductive node disposed on the insulating layer, wherein the first and second conductive nodes are electrically isolated from each other. The power module assembly also comprises a first capacitor having a first electrode electrically connected to the conductive base layer, and a second electrode electrically connected to the first conductive node, and further comprises a second capacitor having a first electrode electrically connected to the conductive base layer, and a second electrode electrically connected to the second conductive node.

The Mechanism of Extracellular Stimulation of Nerve Cells on an Electrolyte-Oxide-Semiconductor Capacitor

PubMed Central

Schoen, Ingmar; Fromherz, Peter

2007-01-01

Extracellular excitation of neurons is applied in studies of cultured networks and brain tissue, as well as in neuroprosthetics. We elucidate its mechanism in an electrophysiological approach by comparing voltage-clamp and current-clamp recordings of individual neurons on an insulated planar electrode. Noninvasive stimulation of neurons from pedal ganglia of Lymnaea stagnalis is achieved by defined voltage ramps applied to an electrolyte/HfO2/silicon capacitor. Effects on the smaller attached cell membrane and the larger free membrane are distinguished in a two-domain-stimulation model. Under current-clamp, we study the polarization that is induced for closed ion channels. Under voltage-clamp, we determine the capacitive gating of ion channels in the attached membrane by falling voltage ramps and for comparison also the gating of all channels by conventional variation of the intracellular voltage. Neuronal excitation is elicited under current-clamp by two mechanisms: Rising voltage ramps depolarize the free membrane such that an action potential is triggered. Falling voltage ramps depolarize the attached membrane such that local ion currents are activated that depolarize the free membrane and trigger an action potential. The electrophysiological analysis of extracellular stimulation in the simple model system is a basis for its systematic optimization in neuronal networks and brain tissue. PMID:17098803

Significantly improved dielectric performances of nanocomposites via loading two-dimensional core-shell structure Bi2Te3@SiO2 nanosheets

NASA Astrophysics Data System (ADS)

Chen, Jianwen; Wang, Xiucai; Yu, Xinmei; Fan, Yun; Duan, Zhikui; Jiang, Yewen; Yang, Faquan; Zhou, Yuexia

2018-07-01

Polymer/semiconductor-insulator nanocomposites can display high dielectric constants with a relatively low dissipation factor under low electric fields, and thus seem to promising for high energy density capacitors. Here, a novel nanocomposite films is developed by loading two-dimensional (2D) core-shell structure Bi2Te3@SiO2 nanosheets in the poly (vinylidene fluoride-hexafluoro propylene) (P(VDF-HFP)) polymer matrix. The 2D Bi2Te3 nanosheets were prepared through simple microwave-assisted method. The experimental results suggesting that the SiO2 shell layer between the fillers and polymer matrix could effectively improve the dielectric constant, dielectric loss, AC conductivity, and breakdown strength of composites films. The composite films load with 10 vol.% 2D Bi2Te3@SiO2 nanosheets exhibits a high dielectric constant of 70.3 at 1 kHz and relatively low dielectric loss of 0.058 at 1 kHz. The finite element simulation of electric field and electric current density distribution revealed that the SiO2 shell layer between the fillers and polymer matrix could effectively improve the energy loss, local electric field strength, and breakdown strength of composite films. Therefore, this work will provide a promising route to achieve high-performance capacitors.

Spiers memorial lecture. Organic electronics: an organic materials perspective.

PubMed

Wudl, Fred

2014-01-01

This Introductory Lecture is intended to provide a background to Faraday Discussion 174: "Organic Photonics and Electronics" and will consist of a chronological, subjective review of organic electronics. Starting with "ancient history" (1888) and history (1950-present), the article will take us to the present. The principal developments involved the processes of charge carrier generation and charge transport in molecular solids, starting with insulators (photoconductors) and moving to metals, to semiconductors and ending with the most popular semiconductor devices, such as organic light-emitting diodes (OLEDs), organic field effect transistors (OFETs) and organic photovoltaics (OPVs). The presentation will be from an organic chemistry/materials point of view.

Nondestructive Memory Elements Based on Polymeric Langmuir-Blodgett Thin Films

NASA Astrophysics Data System (ADS)

Reece, T. J.; Ducharme, S.

2007-03-01

Ferroelectric field effect transistors (FeFETs) have attracted much attention recently because of their low power consumption and fast nondestructive readout. Among the ferroelectric thin films used in FET devices; the ferroelectric copolymer of polyvinylidene fluoride, PVDF (C2H2F2), with trifluoroethylene, TrFE (C2HF3), has distinct advantages, including low dielectric constant, low processing temperature, low cost and compatibility with organic semiconductors. By employing the Langmuir-Blodgett technique, we are able to deposit films as thin as 1.8 nm. We discuss the characterization, modeling and fabrication of metal-ferroelectric-insulator-semiconductor (MFIS) structures incorporating these films.

Determination of work function of graphene under a metal electrode and its role in contact resistance.

PubMed

Song, Seung Min; Park, Jong Kyung; Sul, One Jae; Cho, Byung Jin

2012-08-08

Although the work function of graphene under a given metal electrode is critical information for the realization of high-performance graphene-based electronic devices, relatively little relevant research has been carried out to date. In this work, the work function values of graphene under various metals are accurately measured for the first time through a detailed analysis of the capacitance-voltage (C-V) characteristics of a metal-graphene-oxide-semiconductor (MGOS) capacitor structure. In contrast to the high work function of exposed graphene of 4.89-5.16 eV, the work function of graphene under a metal electrode varies depending on the metal species. With a Cr/Au or Ni contact, the work function of graphene is pinned to that of the contacted metal, whereas with a Pd or Au contact the work function assumes a value of ∼4.62 eV regardless of the work function of the contact metal. A study of the gate voltage dependence on the contact resistance shows that the latter case provides lower contact resistance.

Hybrid nanomembrane-based capacitors for the determination of the dielectric constant of semiconducting molecular ensembles.

PubMed

Petrini, Paula A; Silva, Ricardo M L; de Oliveira, Rafael F; Merces, Leandro; Bof Bufon, Carlos C

2018-06-29

Considerable advances in the field of molecular electronics have been achieved over the recent years. One persistent challenge, however, is the exploitation of the electronic properties of molecules fully integrated into devices. Typically, the molecular electronic properties are investigated using sophisticated techniques incompatible with a practical device technology, such as the scanning tunneling microscopy. The incorporation of molecular materials in devices is not a trivial task as the typical dimensions of electrical contacts are much larger than the molecular ones. To tackle this issue, we report on hybrid capacitors using mechanically-compliant nanomembranes to encapsulate ultrathin molecular ensembles for the investigation of molecular dielectric properties. As the prototype material, copper (II) phthalocyanine (CuPc) has been chosen as information on its dielectric constant (k CuPc ) at the molecular scale is missing. Here, hybrid nanomembrane-based capacitors containing metallic nanomembranes, insulating Al 2 O 3 layers, and the CuPc molecular ensembles have been fabricated and evaluated. The Al 2 O 3 is used to prevent short circuits through the capacitor plates as the molecular layer is considerably thin (<30 nm). From the electrical measurements of devices with molecular layers of different thicknesses, the CuPc dielectric constant has been reliably determined (k CuPc  = 4.5 ± 0.5). These values suggest a mild contribution of the molecular orientation on the CuPc dielectric properties. The reported nanomembrane-based capacitor is a viable strategy for the dielectric characterization of ultrathin molecular ensembles integrated into a practical, real device technology.

Hybrid nanomembrane-based capacitors for the determination of the dielectric constant of semiconducting molecular ensembles

NASA Astrophysics Data System (ADS)

Petrini, Paula A.; Silva, Ricardo M. L.; de Oliveira, Rafael F.; Merces, Leandro; Bof Bufon, Carlos C.

2018-06-01

Considerable advances in the field of molecular electronics have been achieved over the recent years. One persistent challenge, however, is the exploitation of the electronic properties of molecules fully integrated into devices. Typically, the molecular electronic properties are investigated using sophisticated techniques incompatible with a practical device technology, such as the scanning tunneling microscopy. The incorporation of molecular materials in devices is not a trivial task as the typical dimensions of electrical contacts are much larger than the molecular ones. To tackle this issue, we report on hybrid capacitors using mechanically-compliant nanomembranes to encapsulate ultrathin molecular ensembles for the investigation of molecular dielectric properties. As the prototype material, copper (II) phthalocyanine (CuPc) has been chosen as information on its dielectric constant (k CuPc) at the molecular scale is missing. Here, hybrid nanomembrane-based capacitors containing metallic nanomembranes, insulating Al2O3 layers, and the CuPc molecular ensembles have been fabricated and evaluated. The Al2O3 is used to prevent short circuits through the capacitor plates as the molecular layer is considerably thin (<30 nm). From the electrical measurements of devices with molecular layers of different thicknesses, the CuPc dielectric constant has been reliably determined (k CuPc = 4.5 ± 0.5). These values suggest a mild contribution of the molecular orientation on the CuPc dielectric properties. The reported nanomembrane-based capacitor is a viable strategy for the dielectric characterization of ultrathin molecular ensembles integrated into a practical, real device technology.

Evaluating electrically insulating films deposited on V-4% Cr-4% Ti by reactive CVD

DOE Office of Scientific and Technical Information (OSTI.GOV)

Park, J.H.; Cho, W.D.

1997-04-01

Previous CaO coatings on V-4%Cr-4%Ti exhibited high-ohmic insulator behavior even though a small amount of vanadium from the alloy was incorporated in the coating. However, when the vanadium concentration in the coatings is > 15 wt%, the coating becomes conductive. When the vanadium concentration is high in localized areas, a calcium vanadate phase that exhibits semiconductor behavior can form. To explore this situation, CaO and Ca-V-O coatings were produced on vanadium alloys by chemical vapor deposition (CVD) and by a metallic-vapor process to investigate the electrical resistance of the coatings. Initially, the vanadium alloy specimens were either charged with oxygenmore » in argon that contained trace levels of oxygen, or oxidized for 1.5-3 h in a 1% CO-CO{sub 2} gas mixture or in air to form vanadium oxide at 625-650{degrees}C. Most of the specimens were exposed to calcium vapor at 800-850{degrees}C. Initial and final weights were obtained to monitor each step, and surveillance samples were removed for examination by optical and scanning electron microscopy and electron-energy-dispersive and X-ray diffraction analysis; the electrical resistivity was also measured. The authors found that Ca-V-O films exhibited insulator behavior when the ratio of calcium concentration to vanadium concentration R in the film was > 0.9, and semiconductor or conductor behavior for R < 0.8. However, in some cases, semiconductor behavior was observed when CaO-coated samples with R > 0.98 were exposed in liquid lithium. Based on these studies, the authors conclude that semiconductor behavior occurs if a conductive calcium vanadate phase is present in localized regions in the CaO coating.« less

rf Quantum Capacitance of the Topological Insulator Bi2Se3 in the Bulk Depleted Regime for Field-Effect Transistors

NASA Astrophysics Data System (ADS)

Inhofer, A.; Duffy, J.; Boukhicha, M.; Bocquillon, E.; Palomo, J.; Watanabe, K.; Taniguchi, T.; Estève, I.; Berroir, J. M.; Fève, G.; Plaçais, B.; Assaf, B. A.

2018-02-01

A metal-dielectric topological-insulator capacitor device based on hexagonal-boron-nitrate- (h -BN) encapsulated CVD-grown Bi2Se3 is realized and investigated in the radio-frequency regime. The rf quantum capacitance and device resistance are extracted for frequencies as high as 10 GHz and studied as a function of the applied gate voltage. The superior quality h -BN gate dielectric combined with the optimized transport characteristics of CVD-grown Bi2Se3 (n ˜1018 cm-3 in 8 nm) on h -BN allow us to attain a bulk depleted regime by dielectric gating. A quantum-capacitance minimum and a linear variation of the capacitance with the chemical potential are observed revealing a Dirac regime. The topological surface state in proximity to the gate is seen to reach charge neutrality, but the bottom surface state remains charged and capacitively coupled to the top via the insulating bulk. Our work paves the way toward implementation of topological materials in rf devices.

Apparatus for improving performance of electrical insulating structures

DOEpatents

Wilson, Michael J.; Goerz, David A.

2004-08-31

Removing the electrical field from the internal volume of high-voltage structures; e.g., bushings, connectors, capacitors, and cables. The electrical field is removed from inherently weak regions of the interconnect, such as between the center conductor and the solid dielectric, and places it in the primary insulation. This is accomplished by providing a conductive surface on the inside surface of the principal solid dielectric insulator surrounding the center conductor and connects the center conductor to this conductive surface. The advantage of removing the electric fields from the weaker dielectric region to a stronger area improves reliability, increases component life and operating levels, reduces noise and losses, and allows for a smaller compact design. This electric field control approach is currently possible on many existing products at a modest cost. Several techniques are available to provide the level of electric field control needed. Choosing the optimum technique depends on material, size, and surface accessibility. The simplest deposition method uses a standard electroless plating technique, but other metalization techniques include vapor and energetic deposition, plasma spraying, conductive painting, and other controlled coating methods.

Apparatus for improving performance of electrical insulating structures

DOEpatents

Wilson, Michael J.; Goerz, David A.

2002-01-01

Removing the electrical field from the internal volume of high-voltage structures; e.g., bushings, connectors, capacitors, and cables. The electrical field is removed from inherently weak regions of the interconnect, such as between the center conductor and the solid dielectric, and places it in the primary insulation. This is accomplished by providing a conductive surface on the inside surface of the principal solid dielectric insulator surrounding the center conductor and connects the center conductor to this conductive surface. The advantage of removing the electric fields from the weaker dielectric region to a stronger area improves reliability, increases component life and operating levels, reduces noise and losses, and allows for a smaller compact design. This electric field control approach is currently possible on many existing products at a modest cost. Several techniques are available to provide the level of electric field control needed. Choosing the optimum technique depends on material, size, and surface accessibility. The simplest deposition method uses a standard electroless plating technique, but other metalization techniques include vapor and energetic deposition, plasma spraying, conductive painting, and other controlled coating methods.

Method for improving performance of highly stressed electrical insulating structures

DOEpatents

Wilson, Michael J.; Goerz, David A.

2002-01-01

Removing the electrical field from the internal volume of high-voltage structures; e.g., bushings, connectors, capacitors, and cables. The electrical field is removed from inherently weak regions of the interconnect, such as between the center conductor and the solid dielectric, and places it in the primary insulation. This is accomplished by providing a conductive surface on the inside surface of the principal solid dielectric insulator surrounding the center conductor and connects the center conductor to this conductive surface. The advantage of removing the electric fields from the weaker dielectric region to a stronger area improves reliability, increases component life and operating levels, reduces noise and losses, and allows for a smaller compact design. This electric field control approach is currently possible on many existing products at a modest cost. Several techniques are available to provide the level of electric field control needed. Choosing the optimum technique depends on material, size, and surface accessibility. The simplest deposition method uses a standard electroless plating technique, but other metalization techniques include vapor and energetic deposition, plasma spraying, conductive painting, and other controlled coating methods.

Tunable Electronic and Topological Properties of Germanene by Functional Group Modification

PubMed Central

Ren, Ceng-Ceng; Zhang, Shu-Feng; Ji, Wei-Xiao; Zhang, Chang-Wen; Li, Ping; Wang, Pei-Ji

2018-01-01

Electronic and topological properties of two-dimensional germanene modified by functional group X (X = H, F, OH, CH3) at full coverage are studied with first-principles calculation. Without considering the effect of spin-orbit coupling (SOC), all functionalized configurations become semiconductors, removing the Dirac cone at K point in pristine germanene. We also find that their band gaps can be especially well tuned by an external strain. When the SOC is switched on, GeX (X = H, CH3) is a normal insulator and strain leads to a phase transition to a topological insulator (TI) phase. However, GeX (X = F, OH) becomes a TI with a large gap of 0.19 eV for X = F and 0.24 eV for X = OH, even without external strains. More interestingly, when all these functionalized monolayers form a bilayer structure, semiconductor-metal states are observed. All these results suggest a possible route of modulating the electronic properties of germanene and promote applications in nanoelectronics. PMID:29509699

Complex dewetting scenarios of ultrathin silicon films for large-scale nanoarchitectures

PubMed Central

Naffouti, Meher; Backofen, Rainer; Salvalaglio, Marco; Bottein, Thomas; Lodari, Mario; Voigt, Axel; David, Thomas; Benkouider, Abdelmalek; Fraj, Ibtissem; Favre, Luc; Ronda, Antoine; Berbezier, Isabelle; Grosso, David; Abbarchi, Marco; Bollani, Monica

2017-01-01

Dewetting is a ubiquitous phenomenon in nature; many different thin films of organic and inorganic substances (such as liquids, polymers, metals, and semiconductors) share this shape instability driven by surface tension and mass transport. Via templated solid-state dewetting, we frame complex nanoarchitectures of monocrystalline silicon on insulator with unprecedented precision and reproducibility over large scales. Phase-field simulations reveal the dominant role of surface diffusion as a driving force for dewetting and provide a predictive tool to further engineer this hybrid top-down/bottom-up self-assembly method. Our results demonstrate that patches of thin monocrystalline films of metals and semiconductors share the same dewetting dynamics. We also prove the potential of our method by fabricating nanotransfer molding of metal oxide xerogels on silicon and glass substrates. This method allows the novel possibility of transferring these Si-based patterns on different materials, which do not usually undergo dewetting, offering great potential also for microfluidic or sensing applications. PMID:29296680

Complex dewetting scenarios of ultrathin silicon films for large-scale nanoarchitectures.

PubMed

Naffouti, Meher; Backofen, Rainer; Salvalaglio, Marco; Bottein, Thomas; Lodari, Mario; Voigt, Axel; David, Thomas; Benkouider, Abdelmalek; Fraj, Ibtissem; Favre, Luc; Ronda, Antoine; Berbezier, Isabelle; Grosso, David; Abbarchi, Marco; Bollani, Monica

2017-11-01

Dewetting is a ubiquitous phenomenon in nature; many different thin films of organic and inorganic substances (such as liquids, polymers, metals, and semiconductors) share this shape instability driven by surface tension and mass transport. Via templated solid-state dewetting, we frame complex nanoarchitectures of monocrystalline silicon on insulator with unprecedented precision and reproducibility over large scales. Phase-field simulations reveal the dominant role of surface diffusion as a driving force for dewetting and provide a predictive tool to further engineer this hybrid top-down/bottom-up self-assembly method. Our results demonstrate that patches of thin monocrystalline films of metals and semiconductors share the same dewetting dynamics. We also prove the potential of our method by fabricating nanotransfer molding of metal oxide xerogels on silicon and glass substrates. This method allows the novel possibility of transferring these Si-based patterns on different materials, which do not usually undergo dewetting, offering great potential also for microfluidic or sensing applications.

Method of manufacturing a shapeable short-resistant capacitor

DOEpatents

Taylor, Ralph S.; Myers, John D.; Baney, William J.

2013-04-02

A method that employs a novel combination of conventional fabrication techniques provides a ceramic short-resistant capacitor that is bendable and/or shapeable to provide a multiple layer capacitor that is extremely compact and amenable to desirable geometries. The method allows thinner and more flexible ceramic capacitors to be made. The method includes forming a first thin metal layer on a substrate; depositing a thin, ceramic dielectric layer over the metal layer; depositing a second thin metal layer over the dielectric layer to form a capacitor exhibiting a benign failure mode; and separating the capacitor from the substrate. The method may also include bending the resulting capacitor into a serpentine arrangement with gaps between the layers that allow venting of evaporated electrode material in the event of a benign failure.

A General Strategy to Achieve Colossal Permittivity and Low Dielectric Loss Through Constructing Insulator/Semiconductor/Insulator Multilayer Structures

NASA Astrophysics Data System (ADS)

Liu, Kai; Sun, Yalong; Zheng, Fengang; Tse, Mei-Yan; Sun, Qingbo; Liu, Yun; Hao, Jianhua

2018-06-01

In this work, we propose a route to realize high-performance colossal permittivity (CP) by creating multilayer structures of insulator/semiconductor/insulator. To prove the new concept, we made heavily reduced rutile TiO2 via annealing route in Ar/H2 atmosphere. Dielectric studies show that the maximum dielectric permittivity ( 3.0 × 104) of our prepared samples is about 100 times higher than that ( 300) of conventional TiO2. The minimum dielectric loss is 0.03 (at 104-105 Hz). Furthermore, CP is almost independent of the frequency (100-106 Hz) and the temperature (20-350 K). We suggest that the colossal permittivity is attributed to the high carrier concentration of the inner TiO2 semiconductor, while the low dielectric loss is due to the presentation of the insulator layer on the surface of TiO2. The method proposed here can be expanded to other material systems, such as semiconductor Si sandwiched by top and bottom insulator layers of Ga2O3.

Enlarging photovoltaic effect: combination of classic photoelectric and ferroelectric photovoltaic effects.

PubMed

Zhang, Jingjiao; Su, Xiaodong; Shen, Mingrong; Dai, Zhihua; Zhang, Lingjun; He, Xiyun; Cheng, Wenxiu; Cao, Mengyu; Zou, Guifu

2013-01-01

Converting light energy to electrical energy in photovoltaic devices relies on the photogenerated electrons and holes separated by the built-in potential in semiconductors. Photo-excited electrons in metal electrodes are usually not considered in this process. Here, we report an enhanced photovoltaic effect in the ferroelectric lanthanum-modified lead zirconate titanate (PLZT) by using low work function metals as the electrodes. We believe that electrons in the metal with low work function could be photo-emitted into PLZT and form the dominant photocurrent in our devices. Under AM1.5 (100 mW/cm²) illumination, the short-circuit current and open-circuit voltage of Mg/PLZT/ITO are about 150 and 2 times of those of Pt/PLZT/ITO, respectively. The photovoltaic response of PLZT capacitor was expanded from ultraviolet to visible spectra, and it may have important impact on design and fabrication of high performance photovoltaic devices based on ferroelectric materials.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Holmium hafnate: An emerging electronic device material

NASA Astrophysics Data System (ADS)

Pavunny, Shojan P.; Sharma, Yogesh; Kooriyattil, Sudheendran; Dugu, Sita; Katiyar, Rajesh K.; Scott, James F.; Katiyar, Ram S.

2015-03-01

We report structural, optical, charge transport, and temperature properties as well as the frequency dependence of the dielectric constant of Ho2Hf2O7 (HHO) which make this material desirable as an alternative high-k dielectric for future silicon technology devices. A high dielectric constant of ˜20 and very low dielectric loss of ˜0.1% are temperature and voltage independent at 100 kHz near ambient conditions. The Pt/HHO/Pt capacitor exhibits exceptionally low Schottky emission-based leakage currents. In combination with the large observed bandgap Eg of 5.6 eV, determined by diffuse reflectance spectroscopy, our results reveal fundamental physics and materials science of the HHO metal oxide and its potential application as a high-k dielectric for the next generation of complementary metal-oxide-semiconductor devices.

Comparison of the physical, chemical and electrical properties of ALD Al 2 O 3 on c- and m- plane GaN: Comparison of the physical, chemical and electrical properties of ALD Al 2 O 3 on c- and m- plane GaN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, D.; Hossain, T.; Nepal, N.

2014-02-01

Our study compares the physical, chemical and electrical properties of Al 2O 3 thin films deposited on gallium polar c- and nonpolar m -plane GaN substrates by atomic layer deposition (ALD). Correlations were sought between the film's structure, composition, and electrical properties. The thickness of the Al 2O 3 films was 19.2 nm as determined from a Si witness sample by spectroscopic ellipsometry. We measured the gate dielectric was slightly aluminum-rich (Al:O=1:1.3) from X-ray photoelectron spectroscopy (XPS) depth profile, and the oxide-semiconductor interface carbon concentration was lower on c -plane GaN. The oxide's surface morphology was similar on both substrates,more » but was smoothest on c -plane GaN as determined by atomic force microscopy (AFM). Circular capacitors (50-300 μm diameter) with Ni/Au (20/100 nm) metal contacts on top of the oxide were created by standard photolithography and e-beam evaporation methods to form metal-oxide-semiconductor capacitors (MOSCAPs). Moreover, the alumina deposited on c -plane GaN showed less hysteresis (0.15 V) than on m -plane GaN (0.24 V) in capacitance-voltage (CV) characteristics, consistent with its better quality of this dielectric as evidenced by negligible carbon contamination and smooth oxide surface. These results demonstrate the promising potential of ALD Al 2O 3 on c -plane GaN, but further optimization of ALD is required to realize the best properties of Al 2O 3 on m -plane GaN.« less

Hot-electron-induced hydrogen redistribution and defect generation in metal-oxide-semiconductor capacitors

NASA Astrophysics Data System (ADS)

Buchanan, D. A.; Marwick, A. D.; Dimaria, D. J.; Dori, L.

1994-09-01

Redistribution of hydrogen caused by hot-electron injection has been studied by hydrogen depth profiling with N-15 nuclear reaction analysis and electrical methods. Internal photoemission and Fowler-Nordheim injection were used for electron injection into large Al-gate and polysilicon-gate capacitors, respectively. A hydrogen-rich layer (about 10(exp 15) atoms/sq cm) observed at the Al/SiO2 interface was found to serve as the source of hydrogen during the hot-electron stress. A small fraction of the hydrogen released from this layer was found to be retrapped near the Si/SiO2 interface for large electron fluences in the Al-gate samples. Within the limit of detectability, about 10(exp 14)/sq cm, no hydrogen was measured using nuclear reaction analysis in the polysilicon-gate samples. The buildup of hydrogen at the Si/SiO2 interface exhibits a threshold at about 1 MV/cm, consistent with the threshold for electron heating in SiO2. In the 'wet' SiO2 films with purposely introduced excess hydrogen, the rate of hydrogen buildup at the Si/SiO2 interface is found to be significantly greater than that found in the 'dry' films. During electron injection, hydrogen redistribution was also confirmed via the deactivation of boron dopant in the silicon substrate. The generation rates of interface states, neutral electron traps, and anomalous positive charge are found to increase with increasing hydrogen buildup in the substrate and the initial hydrogen concentration in the film. It is concluded that the generation of defects is preceded by the hot-electron-induced release and transport of atomic hydrogen and it is the chemical reaction of this species within the metal-oxide-semiconductor structure that generates the electrically active defects.

Probing Electronic States of Magnetic Semiconductors Using Atomic Scale Microscopy & Spectroscopy

DTIC Science & Technology

2013-12-01

the metal- insulator transition, a feature that has long been predicted theoretically. We showed that a similar picture is at play in magnetic doping of... magnetic atoms on the surface of a superconductor can be used as a versatile platform for creating a topological superconductor . These initial...topological superconductivity and Majorana fermions in a chain of magnetic atoms on the surface of a superconductor Students and postdocs supported