Bus-Programmable Slave Card

NASA Technical Reports Server (NTRS)

Hall, William A.

1990-01-01

Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.

Maxi CAI with a Micro.

ERIC Educational Resources Information Center

Gerhold, George; And Others

This paper describes an effective microprocessor-based CAI system which has been repeatedly tested by a large number of students and edited accordingly. Tasks not suitable for microprocessor based systems (authoring, testing, and debugging) were handled on larger multi-terminal systems. This approach requires that the CAI language used on the…

77 FR 22384 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-13

... passive, microprocessor-based device which includes a starter interrupt function, transponder key and a.... Porsche stated that the antitheft system consists of two major subsystems: a microprocessor-based...

MICROPROCESSOR CONTROL OF ROTOGRAVURE AIRFLOWS

EPA Science Inventory

The report discusses the technical and economic viability of using micro-processor-based control technology to collect volatile organic compound (VOC) emissions from a paper coating operation. The microprocessor-based control system monitors and controls both the airflow rate and...

Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Soeder, J. F.

1983-01-01

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

The design of a microprocessor-based data logger

USGS Publications Warehouse

Leap, K.J.; Dedini, L.A.

1982-01-01

The design of a microprocessor-based data logger, which collects and digitizes analog voltage signals from a continuous-measuring instrumentation system and transmits serial data to a magnetic tape recorder, is discussed. The data logger was assembled from commercially-available components and can be user-programmed for greater flexibility. A description of the data logger hardware and software designs, general operating instructions, the microprocessor program listing, and electrical schematic diagrams are presented.

Microprocessor based implementation of attitude and shape control of large space structures

NASA Technical Reports Server (NTRS)

Reddy, A. S. S. R.

1984-01-01

The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.

Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Korsah, K.

This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I&C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I&C system upgrades of present-day nuclear power plants, as well as I&C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current,more » analog-based I&C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC document was published in 1998, and should reflect any new qualification concerns, from the European perspective, with regard to the use of microprocessor-based safety systems in power plants.« less

An assembler for the MOS Technology 6502 microprocessor as implemented in jolt (TM) and KIM-1 (TM)

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.

A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

NASA Astrophysics Data System (ADS)

Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

1986-06-01

This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

Small Microprocessor for ASIC or FPGA Implementation

NASA Technical Reports Server (NTRS)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

Pupillometry, a bioengineering overview

NASA Technical Reports Server (NTRS)

Myers, G.; Anchetta, J.; Hannaford, B.; Peng, P.; Sherman, K.; Stark, L.; Sun, F.; Usui, S.

1981-01-01

The pupillary control system is examined using a microprocessor based integrative pupillometer. The real time software functions of the microprocessor include: data collection, stimulus generation and area to diameter conversion. Results of an analysis of linear and nonlinear phenomena are presented.

DSS 13 microprocessor antenna controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1988-01-01

A microprocessor-based antenna monitor and control system with multiple CPUs are described. The system was developed as part of the unattended station project for DSS 13 and was enhanced for use by the SETI project. The operational features, hardware, and software designs are described, and a discussion is provided of the major problems encountered.

Microprocessor-Based Neural-Pulse-Wave Analyzer

NASA Technical Reports Server (NTRS)

Kojima, G. K.; Bracchi, F.

1983-01-01

Microprocessor-based system analyzes amplitudes and rise times of neural waveforms. Displaying histograms of measured parameters helps researchers determine how many nerves contribute to signal and specify waveform characteristics of each. Results are improved noise rejection, full or partial separation of overlapping peaks, and isolation and identification of related peaks in different histograms. 2

Microprocessor design for GaAs technology

NASA Astrophysics Data System (ADS)

Milutinovic, Veljko M.

Recent advances in the design of GaAs microprocessor chips are examined in chapters contributed by leading experts; the work is intended as reading material for a graduate engineering course or as a practical R&D reference. Topics addressed include the methodology used for the architecture, organization, and design of GaAs processors; GaAs device physics and circuit design; design concepts for microprocessor-based GaAs systems; a 32-bit GaAs microprocessor; a 32-bit processor implemented in GaAs JFET; and a direct coupled-FET-logic E/D-MESFET experimental RISC machine. Drawings, micrographs, and extensive circuit diagrams are provided.

Scaling theory for information networks.

PubMed

Moses, Melanie E; Forrest, Stephanie; Davis, Alan L; Lodder, Mike A; Brown, James H

2008-12-06

Networks distribute energy, materials and information to the components of a variety of natural and human-engineered systems, including organisms, brains, the Internet and microprocessors. Distribution networks enable the integrated and coordinated functioning of these systems, and they also constrain their design. The similar hierarchical branching networks observed in organisms and microprocessors are striking, given that the structure of organisms has evolved via natural selection, while microprocessors are designed by engineers. Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to an organism is proportional to its mass raised to the 3/4 power. We show that computational systems are also characterized by nonlinear network scaling and use MST principles to characterize how information networks scale, focusing on how MST predicts properties of clock distribution networks in microprocessors. The MST equations are modified to account for variation in the size and density of transistors and terminal wires in microprocessors. Based on the scaling of the clock distribution network, we predict a set of trade-offs and performance properties that scale with chip size and the number of transistors. However, there are systematic deviations between power requirements on microprocessors and predictions derived directly from MST. These deviations are addressed by augmenting the model to account for decentralized flow in some microprocessor networks (e.g. in logic networks). More generally, we hypothesize a set of constraints between the size, power and performance of networked information systems including transistors on chips, hosts on the Internet and neurons in the brain.

A microprocessor-based position control system for a telescope secondary mirror

NASA Technical Reports Server (NTRS)

Lorell, K. R.; Barrows, W. F.; Clappier, R. R.; Lee, G. K.

1983-01-01

The pointing requirements for the Shuttle IR Telescope Facility (SIRTF), which consists of an 0.85-m cryogenically cooled IR telescope, call for an image stability of 0.25 arcsec. Attention is presently given to a microprocessor-based position control system developed for the control of the SIRTF secondary mirror, employing a special control law (to minimize energy dissipation), a precision capacitive position sensor, and a specially designed power amplifier/actuator combination. The microprocessor generates the command angular position and rate waveforms in order to maintain a 90 percent dwell time/10 percent transition time ratio independently of chop frequency or amplitude. Performance and test results of a prototype system designed for use with a demonstration model of the SIRTF focal plane fine guidance sensor are presented.

Loran-C digital word generator for use with a KIM-1 microprocessor system

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1977-01-01

The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator.

The Minerva Multi-Microprocessor.

DTIC Science & Technology

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

A methodology was developed a assess the upset susceptibility/reliability of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general purpose microprocessor were studied. The upset tests involved the random input of analog transients which model lightning induced signals onto interface lines of an 8080 based microcomputer from which upset error data was recorded. The program code on the microprocessor during tests is designed to exercise all of the machine cycles and memory addressing techniques implemented in the 8080 central processing unit. A statistical analysis is presented in which possible correlations are established between the probability of upset occurrence and transient signal inputs during specific processing states and operations. A stochastic upset susceptibility model for the 8080 microprocessor is presented. The susceptibility of this microprocessor to upset, once analog transients have entered the system, is determined analytically by calculating the state probabilities of the stochastic model.

A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

NASA Technical Reports Server (NTRS)

Braswell, F. M.

1981-01-01

An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Mark IVA microprocessor support

NASA Technical Reports Server (NTRS)

Burford, A. L.

1982-01-01

The requirements and plans for the maintenance support of microprocessor-based controllers in the Deep Space Network Mark IVA System are discussed. Additional new interfaces and 16-bit processors have introduced problems not present in the Mark III System. The need for continuous training of maintenance personnel to maintain a level of expertise consistent with the sophistication of the required tools is also emphasized.

Feasibility study of a microprocessor based oculometer system

NASA Technical Reports Server (NTRS)

Varanasi, M. R.

1981-01-01

The elimination of redundancy in data to maximize processing speed and minimize storage requirements were objectives in a feasibility study of a microprocessor based oculometer system that would be portable in size and flexible in use. The appropriate architectural design of the signal processor, improved optics, and the reduction of size, weight, and power to the system were investigated. A flow chart is presented showing the strategy of the design. The simulation for developing microroutines for the high speed algorithmic processor subsystem is discussed as well as the Karhunen-Loeve transform technique for data compression.

A methodology based on reduced complexity algorithm for system applications using microprocessors

NASA Technical Reports Server (NTRS)

Yan, T. Y.; Yao, K.

1988-01-01

The paper considers a methodology on the analysis and design of a minimum mean-square error criterion linear system incorporating a tapped delay line (TDL) where all the full-precision multiplications in the TDL are constrained to be powers of two. A linear equalizer based on the dispersive and additive noise channel is presented. This microprocessor implementation with optimized power of two TDL coefficients achieves a system performance comparable to the optimum linear equalization with full-precision multiplications for an input data rate of 300 baud.

Real-time fetal ECG system design using embedded microprocessors

NASA Astrophysics Data System (ADS)

Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

2016-05-01

The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

Self-Checking Pairs Of Microprocessors

NASA Technical Reports Server (NTRS)

Smith, Brian S.

1995-01-01

Method of imparting fault tolerance to computer system provides for immediate detection of faults at microprocessor level. Shadow microprocessor provides nominal duplicate outputs to verify functioning of main microprocessor. When output signal on any pin of one microprocessor differs from that on corresponding pin of other microprocessor, comparator puts out alarm signal.

Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

NASA Technical Reports Server (NTRS)

Baez, A. N.

1985-01-01

Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

Control methodologies for large space structures

NASA Technical Reports Server (NTRS)

Mcree, G. J.; Altonji, E.

1984-01-01

The objectives of this research were to develop techniques of controlling a dc-motor driven flywheel which would apply torque to the structure to which it was mounted. The motor control system was to be implemented using a microprocessor based controller. The purpose of the torque applied by this system was to dampen oscillations of the structure to which it was mounted. Before the work was terminated due to the unavailability of equipment, a system was developed and partially tested which would provide tight control of the flywheel velocity when it received a velocity command in the form of a voltage. The procedure followed in this development was to first model the motor and flywheel system on an analog computer. Prior to the time the microprocessor development system was available, an analog control loop was replaced by the microprocessor and the system was partially tested.

FEDS - An experiment with a microprocessor-based orbit determination system using TDRS data

NASA Technical Reports Server (NTRS)

Shank, D.; Pajerski, R.

1986-01-01

An experiment in microprocessor-based onboard orbit determination has been conducted at NASA's Goddard Space Flight Center. The experiment collected forward-link observation data in real time from a prototype transponder and performed orbit estimation on a typical low-earth scientific satellite. This paper discusses the hardware and organizational configurations of the experiment, the structure of the onboard software, the mathematical models, and the experiment results.

Software and languages for microprocessors

NASA Astrophysics Data System (ADS)

Williams, David O.

1986-08-01

This paper forms the basis for lectures given at the 6th Summer School on Computing Techniques in Physics, organised by the Computational Physics group of the European Physics Society, and held at the Hotel Ski, Nové Město na Moravě, Czechoslovakia, on 17-26 September 1985. Various types of microprocessor applications are discussed and the main emphasis of the paper is devoted to 'embedded' systems, where the software development is not carried out on the target microprocessor. Some information is provided on the general characteristics of microprocessor hardware. Various types of microprocessor operating system are compared and contrasted. The selection of appropriate languages and software environments for use with microprocessors is discussed. Mechanisms for interworking between different languages, including reasonable error handling, are treated. The CERN developed cross-software suite for the Motorola 68000 family is described. Some remarks are made concerning program tools applicable to microprocessors. PILS, a Portable Interactive Language System, which can be interpreted or compiled for a range of microprocessors, is described in some detail, and the implementation techniques are discussed.

Development of a fault-tolerant microprocessor based computer system for space flight

NASA Technical Reports Server (NTRS)

Montgomery, V. T.

1981-01-01

A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.

Microprocessors in Systems Engineering at the U.S. Naval Academy.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Lowe, W. M., Ed.

1982-01-01

Describes the introduction of microprocessors into the Weapons and Systems Engineering Department at the U.S. Naval Academy, including planning decisions, implementation, procedures, uses of microprocessors in the department, and impact on the Systems Engineering major and curriculum. (SK)

Automated Liquid-Level Control of a Nutrient Reservoir for a Hydroponic System

NASA Technical Reports Server (NTRS)

Smith, Boris; Asumadu, Johnson A.; Dogan, Numan S.

1997-01-01

A microprocessor-based system for control of the liquid level of a nutrient reservoir for a plant hydroponic growing system has been developed. The system uses an ultrasonic transducer to sense the liquid level or height. A National Instruments' Multifunction Analog and Digital Input/Output PC Kit includes NI-DAQ DOS/Windows driver software for an IBM 486 personal computer. A Labview Full Development system for Windows is the graphical programming system being used. The system allows liquid level control to within 0.1 cm for all levels tried between 8 and 36 cm in the hydroponic system application. The detailed algorithms have been developed and a fully automated microprocessor based nutrient replenishment system has been described for this hydroponic system.

Redundant Asynchronous Microprocessor System

NASA Technical Reports Server (NTRS)

Meyer, G.; Johnston, J. O.; Dunn, W. R.

1985-01-01

Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.

Use of electronic microprocessor-based instrumentation by the U.S. geological survey for hydrologic data collection

USGS Publications Warehouse

Shope, William G.; ,

1991-01-01

The U.S. Geological Survey is acquiring a new generation of field computers and communications software to support hydrologic data-collection at field locations. The new computer hardware and software mark the beginning of the Survey's transition from the use of electromechanical devices and paper tapes to electronic microprocessor-based instrumentation. Software is being developed for these microprocessors to facilitate the collection, conversion, and entry of data into the Survey's National Water Information System. The new automated data-collection process features several microprocessor-controlled sensors connected to a serial digital multidrop line operated by an electronic data recorder. Data are acquired from the sensors in response to instructions programmed into the data recorder by the user through small portable lap-top or hand-held computers. The portable computers, called personal field computers, also are used to extract data from the electronic recorders for transport by courier to the office computers. The Survey's alternative to manual or courier retrieval is the use of microprocessor-based remote telemetry stations. Plans have been developed to enhance the Survey's use of the Geostationary Operational Environmental Satellite telemetry by replacing the present network of direct-readout ground stations with less expensive units. Plans also provide for computer software that will support other forms of telemetry such as telephone or land-based radio.

A microprocessor-based automation test system for the experiment of the multi-stage compressor

NASA Astrophysics Data System (ADS)

Zhang, Huisheng; Lin, Chongping

1991-08-01

An automation test system that is controlled by the microprocessor and used in the multistage compressor experiment is described. Based on the analysis of the compressor experiment performances, a complete hardware system structure is set up. It is composed of a IBM PC/XT computer, a large scale sampled data system, the moving machine with three directions, the scanners, the digital instrumentation and some output devices. A program structure of real-time software system is described. The testing results show that this test system can take the measure of many parameter magnitudes in the blade row places and on a boundary layer in different states. The automatic extent and the accuracy of experiment is increased and the experimental cost is reduced.

System and method for leveraging human physiological traits to control microprocessor frequency

DOEpatents

Shye, Alex; Pan, Yan; Scholbrock, Benjamin; Miller, J. Scott; Memik, Gokhan; Dinda, Peter A; Dick, Robert P

2014-03-25

A system and method for leveraging physiological traits to control microprocessor frequency are disclosed. In some embodiments, the system and method may optimize, for example, a particular processor-based architecture based on, for example, end user satisfaction. In some embodiments, the system and method may determine, for example, whether their users are satisfied to provide higher efficiency, improved reliability, reduced power consumption, increased security, and a better user experience. The system and method may use, for example, biometric input devices to provide information about a user's physiological traits to a computer system. Biometric input devices may include, for example, one or more of the following: an eye tracker, a galvanic skin response sensor, and/or a force sensor.

Programmable calculator as a data system controller

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, A.W.; Strasburg, A.C.

Digital data techniques are in common use for analysis of analog information obtained in various tests, and systems have been developed which use a minicomputer as the central controller and data processor. Now, microprocessors allow new design approaches at considerably less cost. This report outlines an approach to system design based on the use of a programmable calculator as the data system controller. A block diagram of the calculator-controlled data system is shown. It was found that the programmable calculator provides a viable alternative to minicomputers or microprocessors for the development laboratory requiring digital data processing. 3 figures. (RWR)

JPRS Report, Science & Technology, China, High-Performance Computer Systems

DTIC Science & Technology

1992-10-28

microprocessor array The microprocessor array in the AP85 system is com- posed of 16 completely identical array element micro - processors . Each array element...microprocessors and capable of host machine reading and writing. The memory capacity of the array element micro - processors as a whole can be expanded...transmission functions to carry out data transmission from array element micro - processor to array element microprocessor, from array element

Application of Fault-Tolerant Computing For Spacecraft Using Commercial-Off-The-Shelf Microprocessors

DTIC Science & Technology

2000-06-01

real - time operating system and design of a human-computer interface (HCI) for a triple modular redundant (TMR) fault-tolerant microprocessor for use in space-based applications. Once disadvantage of using COTS hardware components is their susceptibility to the radiation effects present in the space environment. and specifically, radiation-induced single-event upsets (SEUs). In the event of an SEU, a fault-tolerant system can mitigate the effects of the upset and continue to process from the last known correct system state. The TMR basic hardware

Small Private Key PKS on an Embedded Microprocessor

PubMed Central

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

Small private key MQPKS on an embedded microprocessor.

PubMed

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-03-19

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

Microprocessor realizations of range rate filters

NASA Technical Reports Server (NTRS)

1979-01-01

The performance of five digital range rate filters is evaluated. A range rate filter receives an input of range data from a radar unit and produces an output of smoothed range data and its estimated derivative range rate. The filters are compared through simulation on an IBM 370. Two of the filter designs are implemented on a 6800 microprocessor-based system. Comparisons are made on the bases of noise variance reduction ratios and convergence times of the filters in response to simulated range signals.

Microprocessor-based cardiopulmonary monitoring system

NASA Technical Reports Server (NTRS)

1978-01-01

The system uses a dedicated microprocessor for transducer control and data acquisition and analysis. No data will be stored in this system, but the data will be transmitted to the onboard data system. The data system will require approximately 12 inches of rack space and will consume only 100 watts of power. An experiment specific control panel, through a series of lighted buttons, will guide the operator through the test series providing a smaller margin of error. The experimental validity of the system was verified, and the reproducibility of data and reliability of the system checked. In addition, ease of training, ease of operator interaction, and crew acceptance were evaluated in actual flight conditions.

Stand-alone development system using a KIM-1 microcomputer module

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1978-01-01

A small microprocessor-based system designed to: contain all or most of the interface hardware, designed to be easy to access and modify the hardware, to be capable of being strapped to the seat of a small general aviation aircraft, and to be independent of the aircraft power system is described. The system is used to develop a low cost Loran C sensor processor, but is designed such that the Loran interface boards may be removed and other hardware interfaces inserted into the same connectors. This flexibility is achieved through memory-mapping techniques into the microprocessor.

Microprocessor-Controlled Laser Balancing System

NASA Technical Reports Server (NTRS)

Demuth, R. S.

1985-01-01

Material removed by laser action as part tested for balance. Directed by microprocessor, laser fires appropriate amount of pulses in correct locations to remove necessary amount of material. Operator and microprocessor software interact through video screen and keypad; no programing skills or unprompted system-control decisions required. System provides complete and accurate balancing in single load-and-spinup cycle.

A microprocessor controlled pressure scanning system

NASA Technical Reports Server (NTRS)

Anderson, R. C.

1976-01-01

A microprocessor-based controller and data logger for pressure scanning systems is described. The microcomputer positions and manages data from as many as four 48-port electro-mechanical pressure scanners. The maximum scanning rate is 80 pressure measurements per second (20 ports per second on each of four scanners). The system features on-line calibration, position-directed data storage, and once-per-scan display in engineering units of data from a selected port. The system is designed to be interfaced to a facility computer through a shared memory. System hardware and software are described. Factors affecting measurement error in this type of system are also discussed.

A microprocessor-based control system for the Vienna PDS microdensitometer

NASA Technical Reports Server (NTRS)

Jenkner, H.; Stoll, M.; Hron, J.

1984-01-01

The Motorola Exorset 30 system, based on a Motorola 6809 microprocessor which serves as control processor for the microdensitometer is presented. User communication and instrument control are implemented in this syatem; data transmission to a host computer is provided via standard interfaces. The Vienna PDS system (VIPS) software was developed in BASIC and M6809 assembler. It provides efficient user interaction via function keys and argument input in a menu oriented environment. All parameters can be stored on, and retrieved from, minifloppy disks, making it possible to set up large scanning tasks. Extensive user information includes continuously updated status and coordinate displays, as well as a real time graphic display during scanning.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

A microprocessor based anti-aliasing filter for a PCM system

NASA Technical Reports Server (NTRS)

Morrow, D. C.; Sandlin, D. R.

1984-01-01

Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.

Horizontal Directional Drilling-Length Detection Technology While Drilling Based on Bi-Electro-Magnetic Sensing.

PubMed

Wang, Yudan; Wen, Guojun; Chen, Han

2017-04-27

The drilling length is an important parameter in the process of horizontal directional drilling (HDD) exploration and recovery, but there has been a lack of accurate, automatically obtained statistics regarding this parameter. Herein, a technique for real-time HDD length detection and a management system based on the electromagnetic detection method with a microprocessor and two magnetoresistive sensors employing the software LabVIEW are proposed. The basic principle is to detect the change in the magnetic-field strength near a current coil while the drill stem and drill-stem joint successively pass through the current coil forward or backward. The detection system consists of a hardware subsystem and a software subsystem. The hardware subsystem employs a single-chip microprocessor as the main controller. A current coil is installed in front of the clamping unit, and two magneto resistive sensors are installed on the sides of the coil symmetrically and perpendicular to the direction of movement of the drill pipe. Their responses are used to judge whether the drill-stem joint is passing through the clamping unit; then, the order of their responses is used to judge the movement direction. The software subsystem is composed of a visual software running on the host computer and a software running in the slave microprocessor. The host-computer software processes, displays, and saves the drilling-length data, whereas the slave microprocessor software operates the hardware system. A combined test demonstrated the feasibility of the entire drilling-length detection system.

Horizontal Directional Drilling-Length Detection Technology While Drilling Based on Bi-Electro-Magnetic Sensing

PubMed Central

Wang, Yudan; Wen, Guojun; Chen, Han

2017-01-01

The drilling length is an important parameter in the process of horizontal directional drilling (HDD) exploration and recovery, but there has been a lack of accurate, automatically obtained statistics regarding this parameter. Herein, a technique for real-time HDD length detection and a management system based on the electromagnetic detection method with a microprocessor and two magnetoresistive sensors employing the software LabVIEW are proposed. The basic principle is to detect the change in the magnetic-field strength near a current coil while the drill stem and drill-stem joint successively pass through the current coil forward or backward. The detection system consists of a hardware subsystem and a software subsystem. The hardware subsystem employs a single-chip microprocessor as the main controller. A current coil is installed in front of the clamping unit, and two magneto resistive sensors are installed on the sides of the coil symmetrically and perpendicular to the direction of movement of the drill pipe. Their responses are used to judge whether the drill-stem joint is passing through the clamping unit; then, the order of their responses is used to judge the movement direction. The software subsystem is composed of a visual software running on the host computer and a software running in the slave microprocessor. The host-computer software processes, displays, and saves the drilling-length data, whereas the slave microprocessor software operates the hardware system. A combined test demonstrated the feasibility of the entire drilling-length detection system. PMID:28448445

A monitoring system for vegetable greenhouses based on a wireless sensor network.

PubMed

Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

2010-01-01

A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring.

Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

NASA Technical Reports Server (NTRS)

Barry, R. C.

1980-01-01

Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Multitasking operating systems for microprocessors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cramer, T.

1981-01-01

Microprocessors, because of their low cost, low power consumption, and small size, have caused an explosion in the number of innovative computer applications. Although there is a great deal of variation in microprocessor applications software, there is relatively little variation in the operating-system-level software from one application to the next. Nonetheless, operating system software, especially when multitasking is involved, can be very time consuming and expensive to develop. The major microprocessor manufacturers have acknowledged the need for operating systems in microprocessor applications and are now supplying real-time multitasking operating system software that is adaptable to a wide variety of usermore » systems. Use of this existing operating system software will decrease the number of redundant operating system development efforts, thus freeing programmers to work on more creative and productive problems. This paper discusses the basic terminology and concepts involved with multitasking operating systems. It is intended to provide a general understanding of the subject, so that the reader will be prepared to evaluate specific operating system software according to his or her needs. 2 references.« less

Utilization of Educationally Oriented Microcomputer Based Laboratories

ERIC Educational Resources Information Center

Fitzpatrick, Michael J.; Howard, James A.

1977-01-01

Describes one approach to supplying engineering and computer science educators with an economical portable digital systems laboratory centered around microprocessors. Expansion of the microcomputer based laboratory concept to include Learning Resource Aided Instruction (LRAI) systems is explored. (Author)

A microprocessor-based cardiotachometer

NASA Technical Reports Server (NTRS)

Donaldson, J. A.; Crosier, W. G.

1979-01-01

The development of a highly accurate and reliable cardiotachometer for measuring the heart rate of test subjects is discussed. It measures heart rate over the range of 30 to 250 beats/minute and gives instantaneous (beat to beat) updates on the system output so that occasional noise artifacts or ectopic beats could be more easily identified except that occasional missed beats caused by switching ECG leads should not cause a change in the output. The cardiotachometer uses an improved analog filter and R-wave detector and an Intel 8080A microprocessor to handle all of the logic and arithmetic necessary. By using the microprocessor, future hardware modifications could easily be made if functional changes were needed.

Flight Experiment Demonstration System (FEDS) functional description and interface document

NASA Technical Reports Server (NTRS)

Belcher, R. C.; Shank, D. E.

1984-01-01

This document presents a functional description of the Flight Experiment Demonstration System (FEDS) and of interfaces between FEDS and external hardware and software. FEDS is a modification of the Automated Orbit Determination System (AODS). FEDS has been developed to support a ground demonstration of microprocessor-based onboard orbit determination. This document provides an overview of the structure and logic of FEDS and details the various operational procedures to build and execute FEDS. It also documents a microprocessor interface between FEDS and a TDRSS user transponder and describes a software simulator of the interface used in the development and system testing of FEDS.

The development of a microprocessor-controlled linearly-actuated valve assembly

NASA Technical Reports Server (NTRS)

Wall, R. H.

1984-01-01

The development of a proportional fluid control valve assembly is presented. This electromechanical system is needed for space applications to replace the current proportional flow controllers. The flow is controlled by a microprocessor system that monitors the control parameters of upstream pressure and requested volumetric flow rate. The microprocessor achieves the proper valve stem displacement by means of a digital linear actuator. A linear displacement sensor is used to measure the valve stem position. This displacement is monitored by the microprocessor system as a feedback signal to close the control loop. With an upstream pressure between 15 and 47 psig, the developed system operates between 779 standard CU cm/sec (SCCS) and 1543 SCCS.

Microprocessor-based multichannel flutter monitor using dynamic strain gage signals

NASA Technical Reports Server (NTRS)

Smalley, R. R.

1976-01-01

Two microprocessor-based multichannel monitors for monitoring strain gage signals during aerodynamic instability (flutter) testing in production type turbojet engines were described. One system monitors strain gage signals in the time domain and gives an output indication whenever the signal amplitude of any gage exceeds a pre-set alarm or abort level for that particular gage. The second system monitors the strain gage signals in the frequency domain and therefore is able to use both the amplitude and frequency information. Thus, an alarm signal is given whenever the spectral content of the strain gage signal exceeds, at any point, its corresponding amplitude vs. frequency limit profiles. Each system design is described with details on design trade-offs, hardware, software, and operating experience.

Microprocessor-based single particle calibration of scintillation counter

NASA Technical Reports Server (NTRS)

Mazumdar, G. K. D.; Pathak, K. M.

1985-01-01

A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available.

APPLEPIPS /Apple Personal Image Processing System/ - An interactive digital image processing system for the Apple II microcomputer

NASA Technical Reports Server (NTRS)

Masuoka, E.; Rose, J.; Quattromani, M.

1981-01-01

Recent developments related to microprocessor-based personal computers have made low-cost digital image processing systems a reality. Image analysis systems built around these microcomputers provide color image displays for images as large as 256 by 240 pixels in sixteen colors. Descriptive statistics can be computed for portions of an image, and supervised image classification can be obtained. The systems support Basic, Fortran, Pascal, and assembler language. A description is provided of a system which is representative of the new microprocessor-based image processing systems currently on the market. While small systems may never be truly independent of larger mainframes, because they lack 9-track tape drives, the independent processing power of the microcomputers will help alleviate some of the turn-around time problems associated with image analysis and display on the larger multiuser systems.

A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

PubMed Central

González, Diego; Botella, Guillermo; Meyer-Baese, Uwe; García, Carlos; Sanz, Concepción; Prieto-Matías, Manuel; Tirado, Francisco

2012-01-01

This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system. PMID:23201989

Design of Plant Eco-physiology Monitoring System Based on Embedded Technology

NASA Astrophysics Data System (ADS)

Li, Yunbing; Wang, Cheng; Qiao, Xiaojun; Liu, Yanfei; Zhang, Xinlu

A real time system has been developed to collect plant's growth information comprehensively. Plant eco-physiological signals can be collected and analyzed effectively. The system adopted embedded technology: wireless sensors network collect the eco-physiological information. Touch screen and ARM microprocessor make the system work independently without PC. The system is versatile and all parameters can be set by the touch screen. Sensors' intelligent compensation can be realized in this system. Information can be displayed by either graphically or in table mode. The ARM microprocessor provides the interface to connect with the internet, so the system support remote monitoring and controlling. The system has advantages of friendly interface, flexible construction and extension. It's a good tool for plant's management.

A programmable controller based on CAN field bus embedded microprocessor and FPGA

NASA Astrophysics Data System (ADS)

Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

2008-10-01

One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

DSS 13 Microprocessor Antenna Controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1984-01-01

A microprocessor based antenna controller system developed as part of the unattended station project for DSS 13 is described. Both the hardware and software top level designs are presented and the major problems encounted are discussed. Developments useful to related projects include a JPL standard 15 line interface using a single board computer, a general purpose parser, a fast floating point to ASCII conversion technique, and experience gained in using off board floating point processors with the 8080 CPU.

Device and method for measuring multi-phase fluid flow in a conduit using an elbow flow meter

DOEpatents

Ortiz, Marcos G.; Boucher, Timothy J.

1997-01-01

A system for measuring fluid flow in a conduit. The system utilizes pressure transducers disposed generally in line upstream and downstream of the flow of fluid in a bend in the conduit. Data from the pressure transducers is transmitted to a microprocessor or computer. The pressure differential measured by the pressure transducers is then used to calculate the fluid flow rate in the conduit. Control signals may then be generated by the microprocessor or computer to control flow, total fluid dispersed, (in, for example, an irrigation system), area of dispersal or other desired effect based on the fluid flow in the conduit.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

A microprocessor based high speed packet switch for satellite communications

NASA Technical Reports Server (NTRS)

Arozullah, M.; Crist, S. C.

1980-01-01

The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.

External Verification of SCADA System Embedded Controller Firmware

DTIC Science & Technology

2012-03-01

microprocessor and read-only memory (ROM) or flash memory for storing firmware and control logic [5],[8]. A PLC typically has three software levels as shown in...implementing different firmware. Because PLCs are in effect a microprocessor device, an analysis of the current research on embedded devices is important...Electronics Engineers (IEEE) published a 15 best practices guide for firmware control on microprocessors [44]. IEEE suggests that microprocessors

OS friendly microprocessor architecture: Hardware level computer security

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; La Fratta, Patrick

2016-05-01

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

Rapidly quantifying the relative distention of a human bladder

NASA Technical Reports Server (NTRS)

Companion, John A. (Inventor); Heyman, Joseph S. (Inventor); Mineo, Beth A. (Inventor); Cavalier, Albert R. (Inventor); Blalock, Travis N. (Inventor)

1991-01-01

A device and method was developed to rapidly quantify the relative distention of the bladder of a human subject. An ultrasonic transducer is positioned on the human subject near the bladder. A microprocessor controlled pulser excites the transducer by sending an acoustic wave into the human subject. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer where it is received, amplified, and processed by the receiver. The resulting signal is digitized by an analog to digital converter, controlled by the microprocessor again, and is stored in data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy. Based on programmed scientific measurements and the human subject's past history as contained in program memory, the microprocessor sends out a signal to turn on any or all of the available alarms. The alarm system includes and audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

A Monitoring System for Vegetable Greenhouses based on a Wireless Sensor Network

PubMed Central

Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

2010-01-01

A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetatables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring. PMID:22163391

A Microprocessor-Based Real-Time Simulator of a Turbofan Engine

DTIC Science & Technology

1988-01-01

NASA AVSCOM Technical Memorandum 100889 Technical Report 88-C-011 Lfl A Microprocessor-Based Real-Time Simulator of a Turbofan Engine CD I Jonathan S...Accession For NTIS GRA&I A MICROPROCESSOR-BASED REAL-TIME SIMULATOR DTIC TABUnannounced OF A TURBOFAN ENGINE Justifiaation, Jonathan S. Litt Propulsion...the F100 engine without augmentation (without afterburning). HYTESS is a simplified simulation written in FORTRAN of a generalized turbofan engine . To

Distributed asynchronous microprocessor architectures in fault tolerant integrated flight systems

NASA Technical Reports Server (NTRS)

Dunn, W. R.

1983-01-01

The paper discusses the implementation of fault tolerant digital flight control and navigation systems for rotorcraft application. It is shown that in implementing fault tolerance at the systems level using advanced LSI/VLSI technology, aircraft physical layout and flight systems requirements tend to define a system architecture of distributed, asynchronous microprocessors in which fault tolerance can be achieved locally through hardware redundancy and/or globally through application of analytical redundancy. The effects of asynchronism on the execution of dynamic flight software is discussed. It is shown that if the asynchronous microprocessors have knowledge of time, these errors can be significantly reduced through appropiate modifications of the flight software. Finally, the papear extends previous work to show that through the combined use of time referencing and stable flight algorithms, individual microprocessors can be configured to autonomously tolerate intermittent faults.

Microprocessor Airborne Data Acquisition & Replay (MADAR) System,

DTIC Science & Technology

1984-03-01

Time Record 7. TAPE USAGE 28 7.1 Geseral2 7.2 Tape Time Remanfng lbdocator 28 7.3 Tape Record Capacity 30 . 8. MODULE CONSTRUCTION 30 8.1 Gemeral...general purpose quick-fit type, calibrated for use with a range of different aircraft. The concept was modified such that the microprocessor module was not...dedicated to boom usage but a versatile instrument for other applications. The microprocessor module (Fig. 1) became known as the Microprocessor

Concept report: Microprocessor control of electrical power system

NASA Technical Reports Server (NTRS)

Perry, E.

1977-01-01

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

The Stand-Alone Microprocessor System: A Valuable Tool in College Admissions and Recruitment.

ERIC Educational Resources Information Center

Garrett, Larry Neal

1983-01-01

The stand-alone microprocessor is seen as one innovative tool that can be used both in the organizational management of decline and in meeting specific organizational needs such as those of the admissions director and staff. The term "microprocessor" is defined. (MLW)

Microprocessors in the Curriculum and the Classroom.

ERIC Educational Resources Information Center

Summers, M. K.

1978-01-01

This article, directed at teachers concerned with computer science courses at sixth-form level with no prior knowledge of microprocessors, provides a basic introduction, and describes possible applications of a microprocessor development system as a teaching aid in computer sciences courses in UK secondary school. (Author/RAO)

A COTS-Based Replacement Strategy for Aging Avionics Computers

DTIC Science & Technology

2001-12-01

Communication Control Unit. A COTS-Based Replacement Strategy for Aging Avionics Computers COTS Microprocessor Real Time Operating System New Native Code...Native Code Objec ts Native Code Thread Real - Time Operating System Legacy Function x Virtual Component Environment Context Switch Thunk Add-in Replace

Automated mixed traffic transit vehicle microprocessor controller

NASA Technical Reports Server (NTRS)

Marks, R. A.; Cassell, P.; Johnston, A. R.

1981-01-01

An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

Device and method for measuring multi-phase fluid flow in a conduit using an elbow flow meter

DOEpatents

Ortiz, M.G.; Boucher, T.J.

1997-06-24

A system is described for measuring fluid flow in a conduit. The system utilizes pressure transducers disposed generally in line upstream and downstream of the flow of fluid in a bend in the conduit. Data from the pressure transducers is transmitted to a microprocessor or computer. The pressure differential measured by the pressure transducers is then used to calculate the fluid flow rate in the conduit. Control signals may then be generated by the microprocessor or computer to control flow, total fluid dispersed, (in, for example, an irrigation system), area of dispersal or other desired effect based on the fluid flow in the conduit. 2 figs.

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

Advanced composite aircraft designs include fault-tolerant computer-based digital control systems with thigh reliability requirements for adverse as well as optimum operating environments. Since aircraft penetrate intense electromagnetic fields during thunderstorms, onboard computer systems maya be subjected to field-induced transient voltages and currents resulting in functional error modes which are collectively referred to as digital system upset. A methodology was developed for assessing the upset susceptibility of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general-purpose microprocessor were studied via tests which involved the random input of analog transients which model lightning-induced signals onto interface lines of an 8080-based microcomputer from which upset error data were recorded. The application of Markov modeling to upset susceptibility estimation is discussed and a stochastic model development.

FAME, a microprocessor based front-end analysis and modeling environment

NASA Technical Reports Server (NTRS)

Rosenbaum, J. D.; Kutin, E. B.

1980-01-01

Higher order software (HOS) is a methodology for the specification and verification of large scale, complex, real time systems. The HOS methodology was implemented as FAME (front end analysis and modeling environment), a microprocessor based system for interactively developing, analyzing, and displaying system models in a low cost user-friendly environment. The nature of the model is such that when completed it can be the basis for projection to a variety of forms such as structured design diagrams, Petri-nets, data flow diagrams, and PSL/PSA source code. The user's interface with the analyzer is easily recognized by any current user of a structured modeling approach; therefore extensive training is unnecessary. Furthermore, when all the system capabilities are used one can check on proper usage of data types, functions, and control structures thereby adding a new dimension to the design process that will lead to better and more easily verified software designs.

49 CFR 229.27 - Annual tests.

Code of Federal Regulations, 2011 CFR

2011-10-01

... DMU locomotive or an MU locomotive, equipped with a microprocessor-based event recorder that includes...) A microprocessor-based event recorder with a self-monitoring feature equipped to verify that all...

Enhancement of a prosthetic knee with a microprocessor-controlled gait phase switch reduces falls and improves balance confidence and gait speed in community ambulators with unilateral transfemoral amputation.

PubMed

Fuenzalida Squella, Sara Agueda; Kannenberg, Andreas; Brandão Benetti, Ângelo

2018-04-01

Despite the evidence for improved safety and function of microprocessor stance and swing-controlled prosthetic knees, non-microprocessor-controlled prosthetic knees are still standard of care for persons with transfemoral amputations in most countries. Limited feature microprocessor-control enhancement of such knees could stand to significantly improve patient outcomes. To evaluate gait speed, balance, and fall reduction benefits of the new 3E80 default stance hydraulic knee compared to standard non-microprocessor-controlled prosthetic knees. Comparative within-subject clinical study. A total of 13 young, high-functioning community ambulators with a transfemoral amputation underwent assessment of performance-based (e.g. 2-min walk test, timed ramp/stair tests) and self-reported (e.g. falls, Activities-Specific Balance Confidence scale, Prosthesis Evaluation Questionnaire question #1, Satisfaction with the Prosthesis) outcome measures for their non-microprocessor-controlled prosthetic knees and again after 8 weeks of accommodation to the 3E80 microprocessor-enhanced knee. Self-reported falls significantly declined 77% ( p = .04), Activities-Specific Balance Confidence scores improved 12 points ( p = .005), 2-min walk test walking distance increased 20 m on level ( p = .01) and uneven ( p = .045) terrain, and patient satisfaction significantly improved ( p < .01) when using the 3E80 knee. Slope and stair ambulation performance did not differ between knee conditions. The 3E80 knee reduced self-reported fall incidents and improved balance confidence. Walking performance on both level and uneven terrains also improved compared to non-microprocessor-controlled prosthetic knees. Subjects' satisfaction was significantly higher than with their previous non-microprocessor-controlled prosthetic knees. The 3E80 may be considered a prosthetic option for improving gait performance, balance confidence, and safety in highly active amputees. Clinical relevance This study compared performance-based and self-reported outcome measures when using non-microprocessor and a new microprocessor-enhanced, default stance rotary hydraulic knee. The results inform rehabilitation professionals about the functional benefits of a limited-feature, microprocessor-enhanced hydraulic prosthetic knee over standard non-microprocessor-controlled prosthetic knees.

High-speed microprocessor characterization. Final report/project accomplishments summary, CRADA Number KCP-94-1004

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brown, L.W.

The objective of the project was to characterize and document the critical operating parameters of an 0.8-micron, 350-MHz, 32-bit microprocessor prototype. The roles of FM and T and the participant company were: FM and T -- evaluation performance of the prototype 32-bit microprocessor using the IDS5000 and Tektronix S3260 Integrated Circuit Test System; Corda -- design and build the prototype microprocessor. This project was terminated with nearly all of the planned activities unaddressed.

Fast computational scheme of image compression for 32-bit microprocessors

NASA Technical Reports Server (NTRS)

Kasperovich, Leonid

1994-01-01

This paper presents a new computational scheme of image compression based on the discrete cosine transform (DCT), underlying JPEG and MPEG International Standards. The algorithm for the 2-d DCT computation uses integer operations (register shifts and additions / subtractions only); its computational complexity is about 8 additions per image pixel. As a meaningful example of an on-board image compression application we consider the software implementation of the algorithm for the Mars Rover (Marsokhod, in Russian) imaging system being developed as a part of Mars-96 International Space Project. It's shown that fast software solution for 32-bit microprocessors may compete with the DCT-based image compression hardware.

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

MICROPROCESSOR-BASED DATA-ACQUISITION SYSTEM FOR A BOREHOLE RADAR.

USGS Publications Warehouse

Bradley, Jerry A.; Wright, David L.

1987-01-01

An efficient microprocessor-based system is described that permits real-time acquisition, stacking, and digital recording of data generated by a borehole radar system. Although the system digitizes, stacks, and records independently of a computer, it is interfaced to a desktop computer for program control over system parameters such as sampling interval, number of samples, number of times the data are stacked prior to recording on nine-track tape, and for graphics display of the digitized data. The data can be transferred to the desktop computer during recording, or it can be played back from a tape at a latter time. Using the desktop computer, the operator observes results while recording data and generates hard-copy graphics in the field. Thus, the radar operator can immediately evaluate the quality of data being obtained, modify system parameters, study the radar logs before leaving the field, and rerun borehole logs if necessary. The system has proven to be reliable in the field and has increased productivity both in the field and in the laboratory.

A MICROPROCESSOR ASCII CHARACTER BUFFERING SYSTEM

EPA Science Inventory

A microprocessor buffering system (MBS) was developed at the Environmental Monitoring and Support Laboratory -Cincinnati (EMSL-CI) to provide an efficient transfer for serial ASCII information between intelligent instrument systema and a Data General NOVA laboratory automation co...

Safety of Vital Control and Communication Systems in Guided Ground Transportation : Analysis of Railroad Signaling System Microprocessor Interlocking

DOT National Transportation Integrated Search

1993-05-01

This study has been conducted with the goal of gaining an insight into the issues of maintaining vital signal systems implemented with microprocessor chips and of making field changes to the application of such systems. To relate these abstract topic...

Talking Fire Alarms Calm Kids.

ERIC Educational Resources Information Center

Executive Educator, 1984

1984-01-01

The new microprocessor-based fire alarm systems can help to control smoke movement throughout school buildings by opening vents and doors, identify the burning section, activate voice alarms, provide firefighters with telephone systems during the fire, and release fire-preventing gas. (KS)

Development of an Automated Emergency Response System (AERS) for Rail Transit Systems

DOT National Transportation Integrated Search

1984-10-01

As a result of a fire in 1979 at the Bay Area Rapid Transit District (BART), a microprocessor-based information retrieval system was developed to aid in the emergency decision-making process. This system was proposed, designed and programmed by a sup...

Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

NASA Astrophysics Data System (ADS)

Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

2018-03-01

We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

Special purpose parallel computer architecture for real-time control and simulation in robotic applications

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1993-01-01

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call.

Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

DTIC Science & Technology

2016-02-05

SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they... microprocessors in a way that they can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of...Progress The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they can be added and

PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-08-18

Written Using  Synopsys Processor Designer1  David Whelihan, Ph.D. and Kate Thurmer  MIT Lincoln Laboratory, Lexington, MA, USA    ABSTRACT  Microprocessors ...internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors... microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its

Design of multifunction anti-terrorism robotic system based on police dog

NASA Astrophysics Data System (ADS)

You, Bo; Liu, Suju; Xu, Jun; Li, Dongjie

2007-11-01

Aimed at some typical constraints of police dogs and robots used in the areas of reconnaissance and counterterrorism currently, the multifunction anti-terrorism robotic system based on police dog has been introduced. The system is made up of two parts: portable commanding device and police dog robotic system. The portable commanding device consists of power supply module, microprocessor module, LCD display module, wireless data receiving and dispatching module and commanding module, which implements the remote control to the police dogs and takes real time monitor to the video and images. The police dog robotic system consists of microprocessor module, micro video module, wireless data transmission module, power supply module and offence weapon module, which real time collects and transmits video and image data of the counter-terrorism sites, and gives military attack based on commands. The system combines police dogs' biological intelligence with micro robot. Not only does it avoid the complexity of general anti-terrorism robots' mechanical structure and the control algorithm, but it also widens the working scope of police dog, which meets the requirements of anti-terrorism in the new era.

A real time, FEM based optimal control algorithm and its implementation using parallel processing hardware (transistors) in a microprocessor environment

NASA Technical Reports Server (NTRS)

Patten, William Neff

1989-01-01

There is an evident need to discover a means of establishing reliable, implementable controls for systems that are plagued by nonlinear and, or uncertain, model dynamics. The development of a generic controller design tool for tough-to-control systems is reported. The method utilizes a moving grid, time infinite element based solution of the necessary conditions that describe an optimal controller for a system. The technique produces a discrete feedback controller. Real time laboratory experiments are now being conducted to demonstrate the viability of the method. The algorithm that results is being implemented in a microprocessor environment. Critical computational tasks are accomplished using a low cost, on-board, multiprocessor (INMOS T800 Transputers) and parallel processing. Progress to date validates the methodology presented. Applications of the technique to the control of highly flexible robotic appendages are suggested.

Can low-cost VOR and Omega receivers suffice for RNAV - A new computer-based navigation technique

NASA Technical Reports Server (NTRS)

Hollaar, L. A.

1978-01-01

It is shown that although RNAV is particularly valuable for the personal transportation segment of general aviation, it has not gained complete acceptance. This is due, in part, to its high cost and the necessary special-handling air traffic control. VOR/DME RNAV calculations are ideally suited for analog computers, and the use of microprocessor technology has been suggested for reducing RNAV costs. Three navigation systems, VOR, Omega, and DR, are compared for common navigational difficulties, such as station geometry, siting errors, ground disturbances, and terminal area coverage. The Kalman filtering technique is described with reference to the disadvantages when using a system including standard microprocessors. An integrated navigation system, using input data from various low-cost sensor systems, is presented and current simulation studies are noted.

Fiber optic, Fabry-Perot high temperature sensor

NASA Technical Reports Server (NTRS)

James, K.; Quick, B.

1984-01-01

A digital, fiber optic temperature sensor using a variable Fabry-Perot cavity as the sensor element was analyzed, designed, fabricated, and tested. The fiber transmitted cavity reflection spectra is dispersed then converted from an optical signal to electrical information by a charged coupled device (CCD). A microprocessor-based color demodulation system converts the wavelength information to temperature. This general sensor concept not only utilizes an all-optical means of parameter sensing and transmitting, but also exploits microprocessor technology for automated control, calibration, and enhanced performance. The complete temperature sensor system was evaluated in the laboratory. Results show that the Fabry-Perot temperature sensor has good resolution (0.5% of full seale), high accuracy, and potential high temperature ( 1000 C) applications.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device.

PubMed

Picone, Rico A R; Davis, Solomon; Devine, Cameron; Garbini, Joseph L; Sidles, John A

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

NASA Astrophysics Data System (ADS)

Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Model based design introduction: modeling game controllers to microprocessor architectures

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; Badawy, Abdel-Hameed

2017-04-01

We present an introduction to model based design. Model based design is a visual representation, generally a block diagram, to model and incrementally develop a complex system. Model based design is a commonly used design methodology for digital signal processing, control systems, and embedded systems. Model based design's philosophy is: to solve a problem - a step at a time. The approach can be compared to a series of steps to converge to a solution. A block diagram simulation tool allows a design to be simulated with real world measurement data. For example, if an analog control system is being upgraded to a digital control system, the analog sensor input signals can be recorded. The digital control algorithm can be simulated with the real world sensor data. The output from the simulated digital control system can then be compared to the old analog based control system. Model based design can compared to Agile software develop. The Agile software development goal is to develop working software in incremental steps. Progress is measured in completed and tested code units. Progress is measured in model based design by completed and tested blocks. We present a concept for a video game controller and then use model based design to iterate the design towards a working system. We will also describe a model based design effort to develop an OS Friendly Microprocessor Architecture based on the RISC-V.

Establishment of cells to monitor Microprocessor through fusion genes of microRNA and GFP

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsutsui, Motomu; Hasegawa, Hitoki; Adachi, Koichi

Microprocessor, the complex of Drosha and DGCR8, promotes the processing of primary microRNA to precursor microRNA, which is a crucial step for microRNA maturation. So far, no convenient assay systems have been developed for observing this step in vivo. Here we report the establishment of highly sensitive cellular systems where we can visually monitor the function of Microprocessor. During a series of screening of transfectants with fusion genes of the EGFP cDNA and primary microRNA genes, we have obtained certain cell lines where introduction of siRNA against DGCR8 or Drosha strikingly augments GFP signals. In contrast, these cells have notmore » responded to Dicer siRNA; thus they have a unique character that GFP signals should be negatively and specifically correlated to the action of Microprocessor among biogenesis of microRNA. These cell lines can be useful tools for real-time analysis of Microprocessor action in vivo and identifying its novel modulators.« less

A microprocessor application to a strapdown laser gyro navigator

NASA Technical Reports Server (NTRS)

Giardina, C.; Luxford, E.

1980-01-01

The replacement of analog circuit control loops for laser gyros (path length control, cross axis temperature compensation loops, dither servo and current regulators) with digital filters residing in microcomputers is addressed. In addition to the control loops, a discussion is given on applying the microprocessor hardware to compensation for coning and skulling motion where simple algorithms are processed at high speeds to compensate component output data (digital pulses) for linear and angular vibration motions. Highlights are given on the methodology and system approaches used in replacing differential equations describing the analog system in terms of the mechanized difference equations of the microprocessor. Standard one for one frequency domain techniques are employed in replacing analog transfer functions by their transform counterparts. Direct digital design techniques are also discussed along with their associated benefits. Time and memory loading analyses are also summarized, as well as signal and microprocessor architecture. Trade offs in algorithm, mechanization, time/memory loading, accuracy, and microprocessor architecture are also given.

Gallium-arsenide process evaluation based on a RISC microprocessor example

NASA Astrophysics Data System (ADS)

Brown, Richard B.; Upton, Michael; Chandna, Ajay; Huff, Thomas R.; Mudge, Trevor N.; Oettel, Richard E.

1993-10-01

This work evaluates the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivity of the microprocessor and other large circuit blocks to different process parameters is analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance.

The formal verification of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does.

The Use of Tailored Testing with Instructional Programs. Final Report.

ERIC Educational Resources Information Center

Reckase, Mark D.

A computerized testing system was implemented in conjunction with the Radar Technician Training Course at the Naval Training Center, Great Lakes, Illinois. The feasibility of the system and students' attitudes toward it were examined. The system, a multilevel, microprocessor-based computer network, administered tests in a sequential, fixed length…

Security of Personal Computer Systems: A Management Guide.

ERIC Educational Resources Information Center

Steinauer, Dennis D.

This report describes management and technical security considerations associated with the use of personal computer systems as well as other microprocessor-based systems designed for use in a general office environment. Its primary objective is to identify and discuss several areas of potential vulnerability and associated protective measures. The…

Coed Transactions, Vol. XI, No. 1, January 1979. Microprocessor Course Development Equipment Selection.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Leventhal, Lance A.

Many devices and systems related to microprocessors are available on the marketplace. The author suggests that criteria for selecting and designing workstations and development systems are necessary. Seventeen important factors of designing workstations and six desirable features of a development system are presented. The kinds of places in which…

Smart motor technology

NASA Technical Reports Server (NTRS)

Packard, D.; Schmitt, D.

1984-01-01

Current spacecraft design relies upon microprocessor control; however, motors usually require extensive additional electronic circuitry to interface with these microprocessor controls. An improved control technique that allows a smart brushless motor to connect directly to a microprocessor control system is described. An actuator with smart motors receives a spacecraft command directly and responds in a closed loop control mode. In fact, two or more smart motors can be controlled for synchronous operation.

Benchmark tests on the digital equipment corporation Alpha AXP 21164-based AlphaServer 8400, including a comparison of optimized vector and superscalar processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wasserman, H.J.

1996-02-01

The second generation of the Digital Equipment Corp. (DEC) DECchip Alpha AXP microprocessor is referred to as the 21164. From the viewpoint of numerically-intensive computing, the primary difference between it and its predecessor, the 21064, is that the 21164 has twice the multiply/add throughput per clock period (CP), a maximum of two floating point operations (FLOPS) per CP vs. one for 21064. The AlphaServer 8400 is a shared-memory multiprocessor server system that can accommodate up to 12 CPUs and up to 14 GB of memory. In this report we will compare single processor performance of the 8400 system with thatmore » of the International Business Machines Corp. (IBM) RISC System/6000 POWER-2 microprocessor running at 66 MHz, the Silicon Graphics, Inc. (SGI) MIPS R8000 microprocessor running at 75 MHz, and the Cray Research, Inc. CRAY J90. The performance comparison is based on a set of Fortran benchmark codes that represent a portion of the Los Alamos National Laboratory supercomputer workload. The advantage of using these codes, is that the codes also span a wide range of computational characteristics, such as vectorizability, problem size, and memory access pattern. The primary disadvantage of using them is that detailed, quantitative analysis of performance behavior of all codes on all machines is difficult. One important addition to the benchmark set appears for the first time in this report. Whereas the older version was written for a vector processor, the newer version is more optimized for microprocessor architectures. Therefore, we have for the first time, an opportunity to measure performance on a single application using implementations that expose the respective strengths of vector and superscalar architecture. All results in this report are from single processors. A subsequent article will explore shared-memory multiprocessing performance of the 8400 system.« less

Smartcards in Libraries: A Brave New World.

ERIC Educational Resources Information Center

Myhill, Martin

1998-01-01

Describes the University of Exeter (UK), Mondex, and NatWest UK smartcard-based campus card system project. Smartcards, wallet-sized plastic cards with microprocessors, interface with network terminal devices and are programmable as data, identity, and finance cards. International standard multiple operating system (MULTOS) increases current…

Storing Data and Video on One Tape

NASA Technical Reports Server (NTRS)

Nixon, J. H.; Cater, J. P.

1985-01-01

Microprocessor-based system originally developed for anthropometric research merges digital data with video images for storage on video cassette recorder. Combined signals later retrieved and displayed simultaneously on television monitor. System also extracts digital portion of stored information and transfers it to solid-state memory.

Operating system for a real-time multiprocessor propulsion system simulator. User's manual

NASA Technical Reports Server (NTRS)

Cole, G. L.

1985-01-01

The NASA Lewis Research Center is developing and evaluating experimental hardware and software systems to help meet future needs for real-time, high-fidelity simulations of air-breathing propulsion systems. Specifically, the real-time multiprocessor simulator project focuses on the use of multiple microprocessors to achieve the required computing speed and accuracy at relatively low cost. Operating systems for such hardware configurations are generally not available. A real time multiprocessor operating system (RTMPOS) that supports a variety of multiprocessor configurations was developed at Lewis. With some modification, RTMPOS can also support various microprocessors. RTMPOS, by means of menus and prompts, provides the user with a versatile, user-friendly environment for interactively loading, running, and obtaining results from a multiprocessor-based simulator. The menu functions are described and an example simulation session is included to demonstrate the steps required to go from the simulation loading phase to the execution phase.

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

NASA Technical Reports Server (NTRS)

Srivas, Mandayam; Bickford, Mark

1991-01-01

The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

NASA Technical Reports Server (NTRS)

Bickford, Mark; Srivas, Mandayam

1991-01-01

Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

Microprocessor control of photovoltaic systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

Pain and efficacy rating of a microprocessor-controlled metered injection system for local anaesthesia in minor hand surgery.

PubMed

Nimigan, André S; Gan, Bing Siang

2011-01-01

Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P = .0002). This same group, however, has significantly longer injection times (P < .0001). Pain during the injection process or during surgery was not different between the two groups. Conclusions. This RCT comparing traditional and microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.

An Intelligent Terminal for Access to a Medical Database

PubMed Central

Womble, M. E.; Wilson, S. D.; Keiser, H. N.; Tworek, M. L.

1978-01-01

Very powerful data base management systems (DBMS) now exist which allow medical personnel access to patient record data bases. DBMS's make it easy to retrieve either complete or abbreviated records of patients with similar characteristics. In addition, statistics on data base records are immediately accessible. However, the price of this power is a large computer with the inherent problems of access, response time, and reliability. If a general purpose, time-shared computer is used to get this power, the response time to a request can be either rapid or slow, depending upon loading by other users. Furthermore, if the computer is accessed via dial-up telephone lines, there is competition with other users for telephone ports. If either the DBMS or the host machine is replaced, the medical users, who are typically not sophisticated in computer usage, are forced to learn the new system. Microcomputers, because of their low cost and adaptability, lend themselves to a solution of these problems. A microprocessor-based intelligent terminal has been designed and implemented at the USAF School of Aerospace Medicine to provide a transparent interface between the user and his data base. The intelligent terminal system includes multiple microprocessors, floppy disks, a CRT terminal, and a printer. Users interact with the system at the CRT terminal using menu selection (framing). The system translates the menu selection into the query language of the DBMS and handles all actual communication with the DBMS and its host computer, including telephone dialing and sign on procedures, as well as the actual data base query and response. Retrieved information is stored locally for CRT display, hard copy production, and/or permanent retention. Microprocessor-based communication units provide security for sensitive medical data through encryption/decryption algorithms and high reliability error detection transmission schemes. Highly modular software design permits adapation to a different DBMS and/or host computer with only minor localized software changes. Importantly, this portability is completely transparent to system users. Although the terminal system is independent of the host computer and its DBMS, it has been linked to a UNIVAC 1108 computer supporting MRI's SYSTEM 2000 DBMS.

Development and testing of the Rho Sigma Incorporated microprocessor control subsystem

NASA Technical Reports Server (NTRS)

Hankins, J. D.

1979-01-01

Product development and performance tests of three programmable microprocessor controllers for use with solar heating and cooling systems are presented. The products were developed to be marketable for public use.

Evaluation of the performance of microprocessor-based colorimeter

PubMed Central

Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments. PMID:18924952

Evaluation of the performance of microprocessor-based colorimeter.

PubMed

Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.

A new study on the emission of EM waves from large EAS

NASA Technical Reports Server (NTRS)

Pathak, K. M.; Mazumdar, G. K. D.

1985-01-01

A method used in locating the core of individual cosmic ray showers is described. Using a microprocessor-based detecting system, the density distribution and hence, energy of each detected shower was estimated.

Using a Cray Y-MP as an array processor for a RISC Workstation

NASA Technical Reports Server (NTRS)

Lamaster, Hugh; Rogallo, Sarah J.

1992-01-01

As microprocessors increase in power, the economics of centralized computing has changed dramatically. At the beginning of the 1980's, mainframes and super computers were often considered to be cost-effective machines for scalar computing. Today, microprocessor-based RISC (reduced-instruction-set computer) systems have displaced many uses of mainframes and supercomputers. Supercomputers are still cost competitive when processing jobs that require both large memory size and high memory bandwidth. One such application is array processing. Certain numerical operations are appropriate to use in a Remote Procedure Call (RPC)-based environment. Matrix multiplication is an example of an operation that can have a sufficient number of arithmetic operations to amortize the cost of an RPC call. An experiment which demonstrates that matrix multiplication can be executed remotely on a large system to speed the execution over that experienced on a workstation is described.

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2011 CFR

2011-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2013 CFR

2013-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2014 CFR

2014-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2012 CFR

2012-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2010 CFR

2010-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

Development of the transtibial prosthesis controlled pneumatically and electrically by microcomputer system.

PubMed

Shimada, Youichi; Terayama, Yukio

2006-01-01

This report represents the development of the prototype transtibial prosthesis to assist a smooth and comfortable walking for an unilateral amputee. This prosthesis is composed of two air cylinders, solenoid valves, portable and small air tank for compressed air storage, a multiple sensor system and a microprocessor. Two air cylinders are located around the rods to act as antagonistic and agonistic muscles. The system causes flexion and extension of the foot plate jointed at the ankle with compressed air, injected -or discharged via a solenoid or electromagnetic valves. The valves or solenoids are controlled with a microprocessor (Microchip Technology Inc., PIC16F876), the microprocessor generates control signals to the interface circuits for valve opening and closing consistent with the foot position during the walking phase. The control patterns generated in the microprocessor are modified with feedback from the touch sensor, ankle joint angle sensor and the two dimensional acceleration sensor. The primary walking pattern for an individual amputee should be developed through the gait analysis with video.

Implementation of a microprocessor-based visual-evoked cortical potential recording and analysis system.

PubMed

Wilson, A; Fram, D; Sistar, J

1981-06-01

An Imsai 8080 microcomputer is being used to simultaneously generate a color graphics stimulus display and to record visual-evoked cortical potentials. A brief description of the hardware and software developed for this system is presented. Data storage and analysis techniques are also discussed.

The Use of Opto-Electronics in Viscometry.

ERIC Educational Resources Information Center

Mazza, R. J.; Washbourn, D. H.

1982-01-01

Describes a semi-automatic viscometer which incorporates a microprocessor system and uses optoelectronics to detect flow of liquid through the capillary, flow time being displayed on a timer with accuracy of 0.01 second. The system could be made fully automatic with an additional microprocessor circuit and inclusion of a pump. (Author/JN)

Could a neuroscientist understand a microprocessor?

DOE PAGES

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

2017-01-12

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

Could a Neuroscientist Understand a Microprocessor?

PubMed Central

Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods. PMID:28081141

Could a Neuroscientist Understand a Microprocessor?

PubMed

Jonas, Eric; Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.

Could a neuroscientist understand a microprocessor?

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

Virtual Instrument Simulator for CERES

NASA Technical Reports Server (NTRS)

Chapman, John J.

1997-01-01

A benchtop virtual instrument simulator for CERES (Clouds and the Earth's Radiant Energy System) has been built at NASA, Langley Research Center in Hampton, VA. The CERES instruments will fly on several earth orbiting platforms notably NASDA's Tropical Rainfall Measurement Mission (TRMM) and NASA's Earth Observing System (EOS) satellites. CERES measures top of the atmosphere radiative fluxes using microprocessor controlled scanning radiometers. The CERES Virtual Instrument Simulator consists of electronic circuitry identical to the flight unit's twin microprocessors and telemetry interface to the supporting spacecraft electronics and two personal computers (PC) connected to the I/O ports that control azimuth and elevation gimbals. Software consists of the unmodified TRW developed Flight Code and Ground Support Software which serves as the instrument monitor and NASA/TRW developed engineering models of the scanners. The CERES Instrument Simulator will serve as a testbed for testing of custom instrument commands intended to solve in-flight anomalies of the instruments which could arise during the CERES mission. One of the supporting computers supports the telemetry display which monitors the simulator microprocessors during the development and testing of custom instrument commands. The CERES engineering development software models have been modified to provide a virtual instrument running on a second supporting computer linked in real time to the instrument flight microprocessor control ports. The CERES Instrument Simulator will be used to verify memory uploads by the CERES Flight Operations TEAM at NASA. Plots of the virtual scanner models match the actual instrument scan plots. A high speed logic analyzer has been used to track the performance of the flight microprocessor. The concept of using an identical but non-flight qualified microprocessor and electronics ensemble linked to a virtual instrument with identical system software affords a relatively inexpensive simulation system capable of high fidelity.

Bristol Ridge: A 28-nm $$\\times$$ 86 Performance-Enhanced Microprocessor Through System Power Management

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sundaram, Sriram; Grenat, Aaron; Naffziger, Samuel

Power management techniques can be effective at extracting more performance and energy efficiency out of mature systems on chip (SoCs). For instance, the peak performance of microprocessors is often limited by worst case technology (Vmax), infrastructure (thermal/electrical), and microprocessor usage assumptions. Performance/watt of microprocessors also typically suffers from guard bands associated with the test and binning processes as well as worst case aging/lifetime degradation. Similarly, on multicore processors, shared voltage rails tend to limit the peak performance achievable in low thread count workloads. In this paper, we describe five power management techniques that maximize the per-part performance under the before-mentionedmore » constraints. Using these techniques, we demonstrate a net performance increase of up to 15% depending on the application and TDP of the SoC, implemented on 'Bristol Ridge,' a 28-nm CMOS, dual-core x 86 accelerated processing unit.« less

On-board landmark navigation and attitude reference parallel processor system

NASA Technical Reports Server (NTRS)

Gilbert, L. E.; Mahajan, D. T.

1978-01-01

An approach to autonomous navigation and attitude reference for earth observing spacecraft is described along with the landmark identification technique based on a sequential similarity detection algorithm (SSDA). Laboratory experiments undertaken to determine if better than one pixel accuracy in registration can be achieved consistent with onboard processor timing and capacity constraints are included. The SSDA is implemented using a multi-microprocessor system including synchronization logic and chip library. The data is processed in parallel stages, effectively reducing the time to match the small known image within a larger image as seen by the onboard image system. Shared memory is incorporated in the system to help communicate intermediate results among microprocessors. The functions include finding mean values and summation of absolute differences over the image search area. The hardware is a low power, compact unit suitable to onboard application with the flexibility to provide for different parameters depending upon the environment.

Aircraft interrogation and display system: A ground support equipment for digital flight systems

NASA Technical Reports Server (NTRS)

Glover, R. D.

1982-01-01

A microprocessor-based general purpose ground support equipment for electronic systems was developed. The hardware and software are designed to permit diverse applications in support of aircraft flight systems and simulation facilities. The implementation of the hardware, the structure of the software, describes the application of the system to an ongoing research aircraft project are described.

LLL 8080 BASIC-II interpreter user's manual

DOE Office of Scientific and Technical Information (OSTI.GOV)

McGoldrick, P.R.; Dickinson, J.; Allison, T.G.

1978-04-03

Scientists are finding increased applications for microprocessors as process controllers in their experiments. However, while microprocessors are small and inexpensive, they are difficult to program in machine or assembly language. A high-level language is needed to enable scientists to develop their own microcomputer programs for their experiments on location. Recognizing this need, LLL contracted to have such a language developed. This report describes the resulting LLL BASIC interpreter, which opeates with LLL's 8080-based MCS-8 microcomputer system. All numerical operations are done using Advanced Micro Device's Am9511 arithmetic processor chip or optionally by using a software simulation of that chip. 1more » figure.« less

Embedded algorithms within an FPGA-based system to process nonlinear time series data

NASA Astrophysics Data System (ADS)

Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

2008-03-01

This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better computational and power efficiency.

Development of the self-learning machine for creating models of microprocessor of single-phase earth fault protection devices in networks with isolated neutral voltage above 1000 V

NASA Astrophysics Data System (ADS)

Utegulov, B. B.; Utegulov, A. B.; Meiramova, S.

2018-02-01

The paper proposes the development of a self-learning machine for creating models of microprocessor-based single-phase ground fault protection devices in networks with an isolated neutral voltage higher than 1000 V. Development of a self-learning machine for creating models of microprocessor-based single-phase earth fault protection devices in networks with an isolated neutral voltage higher than 1000 V. allows to effectively implement mathematical models of automatic change of protection settings. Single-phase earth fault protection devices.

A survey of the state of the art and focused research in range systems, task 2

NASA Technical Reports Server (NTRS)

Yao, K.

1986-01-01

Many communication, control, and information processing subsystems are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since, in general, the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, the optimum powers of two coefficient solution was considered. Detailed explanations on the use of branch-and-bound algorithms for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is dully applicable to many other microprocessor controlled information processing systems.

Applications of Microcomputers in the Teaching of Physics 6502 Software.

ERIC Educational Resources Information Center

Marsh, David P.

1980-01-01

Described is a variety of uses of the microcomputer when coupled with software available for systems using 6502 microprocessors. Included are several computer programs which exhibit some of the possibilities for programing the 6502 microprocessors. (DS)

Automated quantitative muscle biopsy analysis system

NASA Technical Reports Server (NTRS)

Castleman, Kenneth R. (Inventor)

1980-01-01

An automated system to aid the diagnosis of neuromuscular diseases by producing fiber size histograms utilizing histochemically stained muscle biopsy tissue. Televised images of the microscopic fibers are processed electronically by a multi-microprocessor computer, which isolates, measures, and classifies the fibers and displays the fiber size distribution. The architecture of the multi-microprocessor computer, which is iterated to any required degree of complexity, features a series of individual microprocessors P.sub.n each receiving data from a shared memory M.sub.n-1 and outputing processed data to a separate shared memory M.sub.n+1 under control of a program stored in dedicated memory M.sub.n.

Ambulatory REACT: real-time seizure detection with a DSP microprocessor.

PubMed

McEvoy, Robert P; Faul, Stephen; Marnane, William P

2010-01-01

REACT (Real-Time EEG Analysis for event deteCTion) is a Support Vector Machine based technology which, in recent years, has been successfully applied to the problem of automated seizure detection in both adults and neonates. This paper describes the implementation of REACT on a commercial DSP microprocessor; the Analog Devices Blackfin®. The primary aim of this work is to develop a prototype system for use in ambulatory or in-ward automated EEG analysis. Furthermore, the complexity of the various stages of the REACT algorithm on the Blackfin processor is analysed; in particular the EEG feature extraction stages. This hardware profile is used to select a reduced, platform-aware feature set, in order to evaluate the seizure classification accuracy of a lower-complexity, lower-power REACT system.

Microprocessor controlled advanced battery management systems

NASA Technical Reports Server (NTRS)

Payne, W. T.

1978-01-01

The advanced battery management system described uses the capabilities of an on-board microprocessor to: (1) monitor the state of the battery on a cell by cell basis; (2) compute the state of charge of each cell; (3) protect each cell from reversal; (4) prevent overcharge on each individual cell; and (5) control dual rate reconditioning to zero volts per cell.

Preliminary experience with a hospital blood pressure follow up clinic with nurse practitioner assessment and microprocessor based data retrieval.

PubMed Central

Rubin, P C; Curzio, J L; Kelman, A; Elliott, H L; Reid, J L

1984-01-01

Experience over two years with 376 hypertensive patients managed at a clinic where the primary observations are made by a trained nurse, clinical information is held on a microprocessor, and treatment follows a standard stepped care approach has been assessed. Blood pressure control after both one and two years was appreciably improved, with over 70% of patients having diastolic pressure below 90 mm Hg compared with 22% of patients when they first attended the new clinic. The non-attendance rate was half that of the conventional hospital outpatient clinic. A computer based record system with a nurse run hypertension clinic is acceptable to patients and offers the possibility of more effective long term control of blood pressure in large numbers of patients. PMID:6432180

An Ill-Structured PBL-Based Microprocessor Course without Formal Laboratory

ERIC Educational Resources Information Center

Kim, Jungkuk

2012-01-01

This paper introduces a problem-based learning (PBL) microprocessor application course designed according to the following strategies: 1) hands-on training without having a formal laboratory, and 2) intense student-centered cooperative learning through an ill-structured problem. PBL was adopted as the core educational technique of the course to…

78 FR 53500 - Petition for Exemption From the Federal Motor Vehicle Theft Prevention Standard; Chrysler

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-29

...) transceiver and a microprocessor and it initiates the ignition process by communicating with the BCM through SKIS. The microprocessor-based SKIS hardware and software also use electronic messages to communicate...

Nearest Neighbor Searching in Binary Search Trees: Simulation of a Multiprocessor System.

ERIC Educational Resources Information Center

Stewart, Mark; Willett, Peter

1987-01-01

Describes the simulation of a nearest neighbor searching algorithm for document retrieval using a pool of microprocessors. Three techniques are described which allow parallel searching of a binary search tree as well as a PASCAL-based system, PASSIM, which can simulate these techniques. Fifty-six references are provided. (Author/LRW)

Microprocessor control and networking for the amps breadboard

NASA Technical Reports Server (NTRS)

Floyd, Stephen A.

1987-01-01

Future space missions will require more sophisticated power systems, implying higher costs and more extensive crew and ground support involvement. To decrease this human involvement, as well as to protect and most efficiently utilize this important resource, NASA has undertaken major efforts to promote progress in the design and development of autonomously managed power systems. Two areas being actively pursued are autonomous power system (APS) breadboards and knowledge-based expert system (KBES) applications. The former are viewed as a requirement for the timely development of the latter. Not only will they serve as final testbeds for the various KBES applications, but will play a major role in the knowledge engineering phase of their development. The current power system breadboard designs are of a distributed microprocessor nature. The distributed nature, plus the need to connect various external computer capabilities (i.e., conventional host computers and symbolic processors), places major emphasis on effective networking. The communications and networking technologies for the first power system breadboard/test facility are described.

The Microprocessor controls the activity of mammalian retrotransposons

PubMed Central

Heras, Sara R.; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L.; Cáceres, Javier F.

2013-01-01

More than half of the human genome is made of Transposable Elements. Their ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human LINE-1 (Long INterspersed Element 1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons acting as a defender of human genome integrity. PMID:23995758

The Microprocessor controls the activity of mammalian retrotransposons.

PubMed

Heras, Sara R; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L; Cáceres, Javier F

2013-10-01

More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons and a defender of human genome integrity.

Low-power circuits design for the wireless force measurement system of the total knee arthroplasty.

PubMed

Chen, Hong; Liu, Ming; Wan, Weiyi; Jia, Chen; Zhang, Chun; Wang, Zihua

2010-01-01

This paper proposes a novel wireless force measurement system for the Total Knee Arthroplasty (TKA) to improve the ligament balancing procedure during TKA. The force measurement system is comprised of a Wireless Force Measurement Spacer (WFMS) and the display part. They communicate with each other by the Radio Frequency (RF) signal. The WFMS is designed to measure the force between the WFMS and the femoral component of the artificial implants and to transmit the force data wirelessly by a low power transceiver. The display part demonstrates the force data in 3D images in real time. The WFMS composes of a sensors array, a Universal Transducer Interfaces (UTIs) array, a low-power sub-threshold microprocessor and a transceiver. The sub-threshold 8-bit microprocessor is taped out with 0.18 microm CMOS technology. The testing results of the microprocessor show that the leakage power of 46nW and the dynamic power of 385nW@165kHz are achieved with the operating voltage of 350 mV. The test results of the system are given and the errors of the system are analyzed. The results verified the reliability of the system. The future work is to design the microprocessor and a lower power transceiver within a single chip.

Gait termination on a declined surface in trans-femoral amputees: Impact of using microprocessor-controlled limb system.

PubMed

Abdulhasan, Zahraa M; Scally, Andy J; Buckley, John G

2018-05-30

Walking down ramps is a demanding task for transfemoral-amputees and terminating gait on ramps is even more challenging because of the requirement to maintain a stable limb so that it can do the necessary negative mechanical work on the centre-of-mass in order to arrest (dissipate) forward/downward velocity. We determined how the use of a microprocessor-controlled limb system (simultaneous control over hydraulic resistances at ankle and knee) affected the negative mechanical work done by each limb when transfemoral-amputees terminated gait during ramp descent. Eight transfemoral-amputees completed planned gait terminations (stopping on prosthesis) on a 5-degree ramp from slow and customary walking speeds, with the limb's microprocessor active or inactive. When active the limb operated in its 'ramp-descent' mode and when inactive the knee and ankle devices functioned at constant default levels. Negative limb work, determined as the integral of the negative mechanical (external) limb power during the braking phase, was compared across speeds and microprocessor conditions. Negative work done by each limb increased with speed (p < 0.001), and on the prosthetic limb it was greater when the microprocessor was active compared to inactive (p = 0.004). There was no change in work done across microprocessor conditions on the intact limb (p = 0.35). Greater involvement of the prosthetic limb when the limb system was active indicates its ramp-descent mode effectively altered the hydraulic resistances at the ankle and knee. Findings highlight participants became more assured using their prosthetic limb to arrest centre-of-mass velocity. Copyright © 2018 Elsevier Ltd. All rights reserved.

A Multi-Media CAI Terminal Based upon a Microprocessor with Applications for the Handicapped.

ERIC Educational Resources Information Center

Brebner, Ann; Hallworth, H. J.

The design of the CAI interface described is based on the microprocessor in order to meet three basic requirements for providing appropriate instruction to the developmentally handicapped: (1) portability, so that CAI can be taken into the customary learning environment; (2) reliability; and (3) flexibility, to permit use of new input and output…

RS-600 programmable controller: Solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

Three identical microprocessor control subsystems were developed which can be used in heating, heating and cooling, and/or hot water systems for single family, multifamily, or commercial applications. The controller incorporates a low cost, highly reliable (all solid state) microprocessor which can be easily reprogrammed.

Formal verification of an avionics microprocessor

NASA Technical Reports Server (NTRS)

Srivas, Mandayam, K.; Miller, Steven P.

1995-01-01

Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.

Design and Development of a Multiprogramming Operating System for Sixteen Bit Microprocessors.

DTIC Science & Technology

1981-12-01

with the technical details of how services are programmed or produced, except perhaps when they fail to meet user requirements. Users are interested in...locations and loading decks. As the expense *and speed of computers increased, executive programs were created to allow several users to sequence...single user operating system as a companion to the 8080 microprocessor. CP/M (Control Program for Microcomputers) was a single user operating system that

A mechanized process algebra for verification of device synchronization protocols

NASA Technical Reports Server (NTRS)

Schubert, E. Thomas

1992-01-01

We describe the formalization of a process algebra based on CCS within the Higher Order Logic (HOL) theorem-proving system. The representation of four types of device interactions and a correctness proof of the communication between a microprocessor and MMU is presented.

Design of a Distributed Microprocessor Sensor System

DTIC Science & Technology

1990-04-01

implemented through these methods, multiversion software and recovery the use of multiple identical software tasks running on blocks, are intended to... Multiversion software for real-time systems tolerant microprocessor that uses three processing is discussed by Shepherd32, Hitt33, Avizienis’, and...tasks and the there are no data available to determine the cost third is used for noncritical tasks. If a discrepancy effectiveness of multiversion

A central microprocessor controlled electrical storage heating system

NASA Astrophysics Data System (ADS)

Horstmann, H.

1980-12-01

The use of a microprocessor to control the reloading of electrical storage heaters not only during the night, but whenever the electrical grid is cycled down, was tested. The test setup, used to control a total of about 10 MW installed storage heating in 96 dwellings, is described. It is demonstrated that additional consumers can be connected to the system without demand for more power stations.

Microprogrammable Integrated Data Acquisition System-Fatigue Life Data Application

DTIC Science & Technology

1976-03-01

Lt. James W. Sturges, successfully applied the Midas general system [Sturges, 1975] to the fatigue life data monitoring problem and proved its...life data problem . The Midas FLD system computer program generates the required signals in the proper sequence for effectively sampling the 8-channel...Integrated Data Acquisition System- Fatigue Life Data Application" ( Midas FLD) is a microprocessor based data acquisition system. It incorporates a Pro-Log

Concept for a power system controller for large space electrical power systems

NASA Technical Reports Server (NTRS)

Lollar, L. F.; Lanier, J. R., Jr.; Graves, J. R.

1981-01-01

The development of technology for a fail-operatonal power system controller (PSC) utilizing microprocessor technology for managing the distribution and power processor subsystems of a large multi-kW space electrical power system is discussed. The specific functions which must be performed by the PSC, the best microprocessor available to do the job, and the feasibility, cost savings, and applications of a PSC were determined. A limited function breadboard version of a PSC was developed to demonstrate the concept and potential cost savings.

Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

PubMed Central

Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

2011-01-01

This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

Microprocessor-controlled iontophoretic drug delivery of 5-fluorouracil: pharmacodynamic and pharmacokinetic study.

PubMed

Chandrashekar, N S; Shobha Rani, R H

2007-01-01

The purpose of this study was to fabricate monolithic 5-fluorouracil (5-FU) transdermal patch with microprocessor- controlled iontophoretic delivery, to evaluate the pharmacodynamic effects on Dalton's lymphoma ascites (DLA) induced in Balb/c mice, and to study pharmacokinetics in rabbits. The transdermal patches were prepared by solvent casting method; a reprogrammable microprocessor was developed and connected to the patches. DLA cells were injected to the hind limb of Balb/c mice (10 animals/group). In the first group of mice 5-FU was administered i.v. (12 mg/kg). In the second group of mice, transdermal patches (20 mg/patch/animal) were installed and kept for 10 consecutive days, while the third (control) group was kept without any treatment. The tumor diameter was measured every 5th day for 30 days, and the animal survival time and death pattern were studied. The electric current density protocol of 0.5 mA/cm(2) for 30 min was used in the pharmacokinetic study in rabbits. There was a significant reduction in tumor volume in the animals treated with monolithic matrix 5-FU transdermal patch compared to untreated controls and i.v. therapy. Tumor volume of the control animals was 5.8 cm(3) on the 30th day, while in 5-FU with transdermal patch delivery animals it was only 0.23 cm(3) (p <0.05). DLA cells tumor-bearing mice treated with 5-FU with transdermal patch had significantly increased lifespan (ILS). Control animals survived only 21+/-1 days after the tumor inoculation, while i.v. 5-FU and 5-FU patches animals survived 24+/-2.7 days and 39.5+/-1.87 days with ILS of 25.58% and 88.09%, respectively (p <0.01). There was significant sustained release of 5-FU through microprocessor-controlled patches and half-life was significantly higher (p <0.05) compared to the i.v. route. Cytotoxic concentration of 5-FU can be achieved through the transdermal drug delivery and effective therapeutic drug concentration can be maintained up to 24 h, with less toxicity. A new generation of transdermal drug delivery systems based on microprocessor-controlled iontophoresis is in the late stages of development and promises to enhance the treatment of local and systemic medical conditions. The incorporation of microprocessor into these systems has been an important advancement to ensure safe and efficient administration of a wide variety of drugs.

A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

PubMed

Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

2011-10-01

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

An Interdisciplinary Microprocessor Project.

ERIC Educational Resources Information Center

Wilcox, Alan D.; And Others

1985-01-01

Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)

A rocket-borne pulse-height analyzer for energetic particle measurements

NASA Technical Reports Server (NTRS)

Leung, W.; Smith, L. G.; Voss, H. D.

1979-01-01

The pulse-height analyzer basically resembles a time-sharing multiplexing data-acquisition system which acquires analog data (from energetic particle spectrometers) and converts them into digital code. The PHA simultaneously acquires pulse-height information from the analog signals of the four input channels and sequentially multiplexes the digitized data to a microprocessor. The PHA together with the microprocessor form an on-board real-time data-manipulation system. The system processes data obtained during the rocket flight and reduces the amount of data to be sent back to the ground station. Consequently the data-reduction process for the rocket experiments is speeded up. By using a time-sharing technique, the throughput rate of the microprocessor is increased. Moreover, data from several particle spectrometers are manipulated to share one information channel; consequently, the TM capacity is increased.

ZEUS hardware control system

NASA Astrophysics Data System (ADS)

Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

1989-12-01

The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users.

A portable real-time data processing system for standard meteorological radiosondes

NASA Technical Reports Server (NTRS)

Staffanson, F. L.

1983-01-01

The UMET-1 is a microprocessor-based portable system for automatic real-time processing of flight data transmitted from the standard RAWINSONDE upper atmosphere meteorological balloonsonde. The first 'target system' is described which was designed to receive data from a mobile tracking and telemetry receiving station (TRADAT), as the balloonsonde ascends to apogee. After balloon-burst, the UMET-1 produces user-ready hardcopy.

Microprocessor-Based Systems Control for the Rigidized Inflatable Get-Away-Special Experiment

DTIC Science & Technology

2004-03-01

communications and faster data throughput increase, satellites are becoming larger. Larger satellite antennas help to provide the needed gain to...increase communications in space. Compounding the performance and size trade-offs are the payload weight and size limit imposed by the launch vehicles...increased communications capacity, and reduce launch costs. This thesis develops and implements the computer control system and power system to

Optical detector calibrator system

NASA Technical Reports Server (NTRS)

Strobel, James P. (Inventor); Moerk, John S. (Inventor); Youngquist, Robert C. (Inventor)

1996-01-01

An optical detector calibrator system simulates a source of optical radiation to which a detector to be calibrated is responsive. A light source selected to emit radiation in a range of wavelengths corresponding to the spectral signature of the source is disposed within a housing containing a microprocessor for controlling the light source and other system elements. An adjustable iris and a multiple aperture filter wheel are provided for controlling the intensity of radiation emitted from the housing by the light source to adjust the simulated distance between the light source and the detector to be calibrated. The geared iris has an aperture whose size is adjustable by means of a first stepper motor controlled by the microprocessor. The multiple aperture filter wheel contains neutral density filters of different attenuation levels which are selectively positioned in the path of the emitted radiation by a second stepper motor that is also controlled by the microprocessor. An operator can select a number of detector tests including range, maximum and minimum sensitivity, and basic functionality. During the range test, the geared iris and filter wheel are repeatedly adjusted by the microprocessor as necessary to simulate an incrementally increasing simulated source distance. A light source calibration subsystem is incorporated in the system which insures that the intensity of the light source is maintained at a constant level over time.

Work and Programmable Automation.

ERIC Educational Resources Information Center

DeVore, Paul W.

A new industrial era based on electronics and the microprocessor has arrived, an era that is being called intelligent automation. Intelligent automation, in the form of robots, replaces workers, and the new products, using microelectronic devices, require significantly less labor to produce than the goods they replace. The microprocessor thus…

Design of control system based on SCM music fountain

NASA Astrophysics Data System (ADS)

Li, Biqing; Li, Zhao; Jiang, Suping

2018-06-01

The design of the design of a microprocessor controlled by simple circuit, introduced this design applied to the components, and draw the main flow chart presentation. System is the use of an external music source, the intensity of the input audio signal lights will affect the light off, the fountain spray of water level will be based on changes in the lantern light off. This design uses a single-chip system is simple, powerful, good reliability and low cost.

Development of a patch type embedded cardiac function monitoring system using dual microprocessor for arrhythmia detection in heart disease patient.

PubMed

Jang, Yongwon; Noh, Hyung Wook; Lee, I B; Jung, Ji-Wook; Song, Yoonseon; Lee, Sooyeul; Kim, Seunghwan

2012-01-01

A patch type embedded cardiac function monitoring system was developed to detect arrhythmias such as PVC (Premature Ventricular Contraction), pause, ventricular fibrillation, and tachy/bradycardia. The overall system is composed of a main module including a dual processor and a Bluetooth telecommunication module. The dual microprocessor strategy minimizes power consumption and size, and guarantees the resources of embedded software programs. The developed software was verified with standard DB, and showed good performance.

Microprocessor control system for 200-kilowatt Mod-OA wind turbines

NASA Technical Reports Server (NTRS)

Nyland, T. W.; Birchenough, A. G.

1982-01-01

The microprocessor system and program used to control the operation of the 200-kW Mod-OA wind turbines is described. The system is programmed to begin startup and shutdown sequences automatically and to control yaw motion. Rotor speed and power output are controlled with integral and proportional control of the blade pitch angle. Included in the report are a description of the hardware and a discussion of the software programming technique. A listing of the PL/M software program is given.

Operation of commercial R3000 processors in the low earth orbit (LEO) space environment

NASA Astrophysics Data System (ADS)

Kaschmitter, J. L.; Shaeffer, D. L.; Colella, N. J.; McKnett, C. L.; Coakley, P. G.

1991-12-01

Spacecraft processors must operate with minimal degradation of performance in the LEO radiation environment, which includes the effects of total accumulated ionizing dose and single event phenomena (SEP) caused by protons and cosmic rays. Commercially available microprocessors can offer a number of advantages relative to radiation-hardened devices but are not normally designed to tolerate effects induced by the LEO environment. Extensive testing of the MIPS R3000 Reduced Instruction Set Computer (RISC) microprocessor family for operation in LEO environments is reported. The authors have characterized total dose and SEP effects for altitudes and inclinations of interest to systems operating in LEO, and they postulate techniques for detection and alleviation of SEP effects based on experimental results.

Multi-sensor Array for High Altitude Balloon Missions to the Stratosphere

NASA Astrophysics Data System (ADS)

Davis, Tim; McClurg, Bryce; Sohl, John

2008-10-01

We have designed and built a microprocessor controlled and expandable multi-sensor array for data collection on near space missions. Weber State University has started a high altitude research balloon program called HARBOR. This array has been designed to data log a base set of measurements for every flight and has room for six guest instruments. The base measurements are absolute pressure, on-board temperature, 3-axis accelerometer for attitude measurement, and 2-axis compensated magnetic compass. The system also contains a real time clock and circuitry for logging data directly to a USB memory stick. In typical operation the measurements will be cycled through in sequence and saved to the memory stick along with the clock's time stamp. The microprocessor can be reprogrammed to adapt to guest experiments with either analog or digital interfacing. This system will fly with every mission and will provide backup data collection for other instrumentation for which the primary task is measuring atmospheric pressure and temperature. The attitude data will be used to determine the orientation of the onboard camera systems to aid in identifying features in the images. This will make these images easier to use for any future GIS (geographic information system) remote sensing missions.

Embedded C Programming: A Practical Course Introducing Programmable Microprocessors

ERIC Educational Resources Information Center

Laverty, David M.; Milliken, Jonny; Milford, Matthew; Cregan, Michael

2012-01-01

This paper presents a new laboratory-based module for embedded systems teaching, which addresses the current lack of consideration for the link between hardware development, software implementation, course content and student evaluation in a laboratory environment. The course introduces second year undergraduate students to the interface between…

Microprocessor Based Temperature Control of Liquid Delivery with Flow Disturbances.

ERIC Educational Resources Information Center

Kaya, Azmi

1982-01-01

Discusses analytical design and experimental verification of a PID control value for a temperature controlled liquid delivery system, demonstrating that the analytical design techniques can be experimentally verified by using digital controls as a tool. Digital control instrumentation and implementation are also demonstrated and documented for…

Dynamic characterization and microprocessor control of the NASA/UVA proof mass actuator

NASA Technical Reports Server (NTRS)

Zimmerman, D. C.; Inman, D. J.; Horner, G. C.

1984-01-01

The self-contained electromagnetic-reaction-type force-actuator system developed by NASA/UVA for the verification of spacecraft-structure vibration-control laws is characterized and demonstrated. The device is controlled by a dedicated microprocessor and has dynamic characteristics determined by Fourier analysis. Test data on a cantilevered beam are shown.

Microprocessor Design Using Hardware Description Language

ERIC Educational Resources Information Center

Mita, Rosario; Palumbo, Gaetano

2008-01-01

The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

Robust Duplication with Comparison Methods in Microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

Robust Duplication with Comparison Methods in Microcontrollers

DOE PAGES

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.; ...

2016-01-01

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

Innovative architectures for dense multi-microprocessor computers

NASA Technical Reports Server (NTRS)

Larson, Robert E.

1989-01-01

The purpose is to summarize a Phase 1 SBIR project performed for the NASA/Langley Computational Structural Mechanics Group. The project was performed from February to August 1987. The main objectives of the project were to: (1) expand upon previous research into the application of chordal ring architectures to the general problem of designing multi-microcomputer architectures, (2) attempt to identify a family of chordal rings such that each chordal ring can be simply expanded to produce the next member of the family, (3) perform a preliminary, high-level design of an expandable multi-microprocessor computer based upon chordal rings, (4) analyze the potential use of chordal ring based multi-microprocessors for sparse matrix problems and other applications arising in computational structural mechanics.

Human supervision and microprocessor control of an optical tracking system

NASA Technical Reports Server (NTRS)

Bigley, W. J.; Vandenberg, J. D.

1981-01-01

Gunners using small calibre anti-aircraft systems have not been able to track high-speed air targets effectively. Substantial improvement in the accuracy of surface fire against attacking aircraft has been realized through the design of a director-type weapon control system. This system concept frees the gunner to exercise a supervisory/monitoring role while the computer takes over continuous target tracking. This change capitalizes on a key consideration of human factors engineering while increasing system accuracy. The advanced system design, which uses distributed microprocessor control, is discussed at the block diagram level and is contrasted with the previous implementation.

Low-level processing for real-time image analysis

NASA Technical Reports Server (NTRS)

Eskenazi, R.; Wilf, J. M.

1979-01-01

A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.

A microprocessor-based one dimensional optical data processor for spatial frequency analysis

NASA Technical Reports Server (NTRS)

Collier, R. L.; Ballard, G. S.

1982-01-01

A high degree of accuracy was obtained in measuring the spatial frequency spectrum of known samples using an optical data processor based on a microprocessor, which reliably collected intensity versus angle data. Stray light control, system alignment, and angle measurement problems were addressed and solved. The capabilities of the instrument were extended by the addition of appropriate optics to allow the use of different wavelengths of laser radiation and by increasing the travel limits of the rotating arm to + or - 160 degrees. The acquisition, storage, and plotting of data by the computer permits the researcher a free hand in data manipulation such as subtracting background scattering from a diffraction pattern. Tests conducted to verify the operation of the processor using a 25 mm diameter pinhole, a 39.37 line pairs per mm series of multiple slits, and a microscope slide coated with 1.091 mm diameter polystyrene latex spheres are described.

Description and Applications for an Automated Inertial Azimuth Measuring System,

DTIC Science & Technology

specialized field environment. The present system consists of two integrated inertial sensors , an angle transfer system, a tiltmeter array and a...optical path. Highly sensitive tiltmeters are used to measure and correct for errors due to base motions of the inertial sensors . Data handling and...microprocessor. The inertial sensors use gimbal-mounted rate gyrocompasses to indicate the azimuths of two transfer mirrors with respect to true North. The

Microprocessors as a tool in determining correlation between sferics and tornado genesis: an update

DOE Office of Scientific and Technical Information (OSTI.GOV)

Witte, D.R.

1980-09-01

Sferics - atmospheric electromagnetic radiation - can be directly correlated, it is believed, to the genesis of tornadoes and other severe weather. Sferics are generated by lightning and other atmospheric disturbances that are not yet entirely understood. The recording and analysis of the patterns in which sferics events occur, it is hoped, will lead to accurate real-time prediction of tornadoes and other severe weather. Collection of the tremendous amount of sferics data generated by one storm system becomes cumbersome when correlation between at least two stations is necessary for triangulation. Microprocessor-based computing systems have made the task of data collectionmore » and manipulation inexpensive and manageable. The original paper on this subject delivered at MAECON '78 dealt with hardware interfacing. Presented were hardware and software tradeoffs, as well as design and construction techniques to yield a cost effective system. This updated paper presents an overview of where the data comes from, how it is collected, and some current manipulation and interpretation techniques used.« less

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

NASA Technical Reports Server (NTRS)

1977-01-01

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

An Assessment of a Beowulf System for a Wide Class of Analysis and Design Software

NASA Technical Reports Server (NTRS)

Katz, D. S.; Cwik, T.; Kwan, B. H.; Lou, J. Z.; Springer, P. L.; Sterling, T. L.; Wang, P.

1997-01-01

A typical Beowulf system, such as the machine at the Jet Propulsion Laboratory (JPL), may comprise 16 nodes interconnected by 100 base T Fast Ethernet. Each node may include a single Inter Pentium Pro 200 MHz microprocessor, 128 MBytes of DRAM, 2.5 GBytes of IDE disk, and PCI bus backplane, and an assortment of other devices.

A microprocessor-based real-time simulator of a turbofan engine

NASA Technical Reports Server (NTRS)

Litt, Jonathan S.; Delaat, John C.; Merrill, Walter C.

1988-01-01

A real-time digital simulator of a Pratt and Whitney F 100 engine is discussed. This self-contained unit can operate in an open-loop stand-alone mode or as part of a closed-loop control system. It can also be used in control system design and development. It accepts five analog control inputs and its sixteen outputs are returned as analog signals.

TMS communications hardware. Volume 2: Bus interface unit

NASA Technical Reports Server (NTRS)

Brown, J. S.; Hopkins, G. T.

1979-01-01

A prototype coaxial cable bus communication system used in the Trend Monitoring System to interconnect intelligent graphics terminals to a host minicomputer is described. The terminals and host are connected to the bus through a microprocessor-based RF modem termed a Bus Interface Unit (BIU). The BIU hardware and the Carrier Sense Multiple Access Listen-While-Talk protocol used on the network are described.

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

Information distribution in distributed microprocessor based flight control systems

NASA Technical Reports Server (NTRS)

Montgomery, R. C.; Lee, P. S.

1977-01-01

This paper presents an optimal control theory that accounts for variable time intervals in the information distribution to control effectors in a distributed microprocessor based flight control system. The theory is developed using a linear process model for the aircraft dynamics and the information distribution process is modeled as a variable time increment process where, at the time that information is supplied to the control effectors, the control effectors know the time of the next information update only in a stochastic sense. An optimal control problem is formulated and solved that provides the control law that minimizes the expected value of a quadratic cost function. An example is presented where the theory is applied to the control of the longitudinal motions of the F8-DFBW aircraft. Theoretical and simulation results indicate that, for the example problem, the optimal cost obtained using a variable time increment Markov information update process where the control effectors know only the past information update intervals and the Markov transition mechanism is almost identical to that obtained using a known uniform information update interval.

Microprocessor implementation of an FFT for ionospheric VLF observations

NASA Technical Reports Server (NTRS)

Elvidge, J.; Kintner, P.; Holzworth, R.

1984-01-01

A fast Fourier transform algorithm is implemented on a CMOS microprocessor for application to very low-frequency electric fields (less than 10 kHz) sensed on high-altitude scientific balloons. Two FFT's are calculated simultaneously by associating them with conjugate symmetric and conjugate antisymmetric results. One goal of the system was to detect spectral signatures associated with fast time variations present in natural signals such as whistlers and chorus. Although a full evaluation of the system was not possible for operational reasons, a measure of the system's success has been defined and evaluated.

Two examples of intelligent systems based on smart materials

DOE Office of Scientific and Technical Information (OSTI.GOV)

Unsworth, J.

1994-12-31

Two intelligent systems are described which are based on smart materials. The operation of the systems also rely on conventional well known technologies such as electronics, signal conditioning, signal processing, microprocessors and engineering design. However without the smart materials the development and integration into the intelligent systems would not have been possible. System 1 is a partial discharge monitor for on-line continuous checking of the condition of electrical power transformers. The ultrasonic and radio frequency detectors in this system rely on special piezoelectric composite integrated with a compact annular metal ring. Partial discharges set up ultrasonic and radio frequency signalsmore » which are received by the integrated detectors. The signals are amplified, conditioned, signal processed, the time interval between the two signals measured and the level of partial discharge activity averaged and assessed for numerous pairs and alarms triggered on remote control panels if the level is dangerous. The system has the capability of initiating automatic shutdown of the transformer once it is linked into the control computers of the electrical power authority. System 2 is called a Security Cradle and is an intelligent 3D shield designed to use the properties of electro active polymers to prevent hardware hackers from stealing valuable of sensitive information from memory devices (e.g., EPROMS) housed in computer or microprocessor installations.« less

Multiprocessor switch with selective pairing

DOEpatents

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

2014-03-11

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

Control electronics for a multi-laser/multi-detector scanning system

NASA Technical Reports Server (NTRS)

Kennedy, W.

1980-01-01

The Mars Rover Laser Scanning system uses a precision laser pointing mechanism, a photodetector array, and the concept of triangulation to perform three dimensional scene analysis. The system is used for real time terrain sensing and vision. The Multi-Laser/Multi-Detector laser scanning system is controlled by a digital device called the ML/MD controller. A next generation laser scanning system, based on the Level 2 controller, is microprocessor based. The new controller capabilities far exceed those of the ML/MD device. The first draft circuit details and general software structure are presented.

Analysis of inadvertent microprocessor lag time on eddy covariance results

Treesearch

Karl Zeller; Gary Zimmerman; Ted Hehn; Evgeny Donev; Diane Denny; Jeff Welker

2001-01-01

Researchers using the eddy covariance approach to measuring trace gas fluxes are often hoping to measure carbon dioxide and energy fluxes for ecosystem intercomparisons. This paper demonstrates a systematic microprocessor- caused lag of 20.1 to 20.2 s in a commercial sonic anemometer-analog-to-digital datapacker system operated at 10 Hz. The result of the inadvertent...

European Science Notes Information Bulletin Reports on Current European and Middle Eastern Science

DTIC Science & Technology

1992-01-01

evclopment in the Abbey-Polymer Processing and Properties ................... 524 J, Magill Corrosion and Protection Centre at the University of...34* Software Engineering and microprocessors and communication chips. The Information Processing Systems recently announced T9000 microprocessor will...computational fluid dynamics, struc- In addition to general and special-purpose tural mechanics, partial differential equations, processing , Europe has a

Time transfer using NAVSTAR GPS

NASA Technical Reports Server (NTRS)

Vandierendock, A. J.; Hua, Q. D.; Mclean, J. R.; Denz, A. R.

1982-01-01

A time transfer unit (TTU) developed for the U.S. Naval Observatory (USNO) has consistently demonstrated the transfer of time with accuracies much better than 100 nanoseconds. A new time transfer system (TTS), the TTS 502 was developed. The TTS 502 is a relatively compact microprocessor-based system with a variety of options that meet each individual's requirements, and has the same performance as the USNO system. The time transfer performance of that USNO system and the details of the new system are presented.

Global identification of target recognition and cleavage by the Microprocessor in human ES cells

PubMed Central

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-01-01

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein–RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3′ overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. PMID:25326327

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape.

PubMed

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem-loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis

PubMed Central

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2016-01-01

Background: There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. Objectives: The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Study design: Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Methods: Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. Results: The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation (p = .001), paretic limb health (p = .04), sounds (p = .02), and well-being (p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. Conclusion: The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety. PMID:27151648

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

PubMed Central

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed. PMID:29922322

Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis.

PubMed

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2017-02-01

There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation ( p = .001), paretic limb health ( p = .04), sounds ( p = .02), and well-being ( p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety.

The biological microprocessor, or how to build a computer with biological parts

PubMed Central

Moe-Behrens, Gerd HG

2013-01-01

Systemics, a revolutionary paradigm shift in scientific thinking, with applications in systems biology, and synthetic biology, have led to the idea of using silicon computers and their engineering principles as a blueprint for the engineering of a similar machine made from biological parts. Here we describe these building blocks and how they can be assembled to a general purpose computer system, a biological microprocessor. Such a system consists of biological parts building an input / output device, an arithmetic logic unit, a control unit, memory, and wires (busses) to interconnect these components. A biocomputer can be used to monitor and control a biological system. PMID:24688733

A microprocessor-based multichannel subsensory stochastic resonance electrical stimulator.

PubMed

Chang, Gwo-Ching

2013-01-01

Stochastic resonance electrical stimulation is a novel intervention which provides potential benefits for improving postural control ability in the elderly, those with diabetic neuropathy, and stroke patients. In this paper, a microprocessor-based subsensory white noise electrical stimulator for the applications of stochastic resonance stimulation is developed. The proposed stimulator provides four independent programmable stimulation channels with constant-current output, possesses linear voltage-to-current relationship, and has two types of stimulation modes, pulse amplitude and width modulation.

Implementation Of The Configurable Fault Tolerant System Experiment On NPSAT 1

DTIC Science & Technology

2016-03-01

REPORT TYPE AND DATES COVERED Master’s thesis 4. TITLE AND SUBTITLE IMPLEMENTATION OF THE CONFIGURABLE FAULT TOLERANT SYSTEM EXPERIMENT ON NPSAT...open-source microprocessor without interlocked pipeline stages (MIPS) based processor softcore, a cached memory structure capable of accessing double...data rate type three and secure digital card memories, an interface to the main satellite bus, and XILINX’s soft error mitigation softcore. The

Introduction to the concepts of TELEDEMO and TELEDIMS

NASA Technical Reports Server (NTRS)

Rice, R. F.; Schlutsmeyer, A. P.

1982-01-01

An introduction to the system concepts: TELEDEMO and TELEDIMS is provided. TELEDEMO is derived primarily from computer graphics and, via incorporation of sophisticated image data compression, enables effective low cost teleconferencing at data rates as low as 1K bit/second using dial-up phone lines. Combining TELEDEMO's powerful capabilities for the development of presentation material with microprocessor-based Information Management Systems (IMS) yields a truly all electronic IMS called TELEDIMS.

Proceedings of GeoTech 85: Personal computers in geology conference

DOE Office of Scientific and Technical Information (OSTI.GOV)

Not Available

1985-01-01

This book presents the papers given at a conference which considered the use of microprocessors in the exploration of petroleum and natural gas deposits. Topics covered at the conference included seismic surveys, geochemistry, expert systems, artificial intelligence, data base management systems, a portable exploration work station, open pit planning on a microcomputer, well logging, fracture analysis, production scheduling of open pit mines, resistivity logging, and coal washability.

Developing stereo image based robot control system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Suprijadi,; Pambudi, I. R.; Woran, M.

Application of image processing is developed in various field and purposes. In the last decade, image based system increase rapidly with the increasing of hardware and microprocessor performance. Many fields of science and technology were used this methods especially in medicine and instrumentation. New technique on stereovision to give a 3-dimension image or movie is very interesting, but not many applications in control system. Stereo image has pixel disparity information that is not existed in single image. In this research, we proposed a new method in wheel robot control system using stereovision. The result shows robot automatically moves based onmore » stereovision captures.« less

Proceedings: DISE Workshop on Microprocessors and Education (Fort Collins, Colorado, August 16-18, 1976).

ERIC Educational Resources Information Center

Pittsburgh Univ., PA. Dept. of Electrical Engineering.

Papers presented during four sessions of a workshop, which addressed the role of microprocessors in education, are included in this publication. The issues covered involved seven areas: (1) views of the microelectronics industry; (2) microprocessor architecture; (3) microprocessor chip design; (4) microprocessor software; (5) the impact of…

Basic avionics module design for general aviation aircraft

NASA Technical Reports Server (NTRS)

Smyth, R. K.; Smyth, D. E.

1978-01-01

The design of an advanced digital avionics system (basic avionics module) for general aviation aircraft operated with a single pilot under IFR conditions is described. The microprocessor based system provided all avionic functions, including flight management, navigation, and lateral flight control. The mode selection was interactive with the pilot. The system used a navigation map data base to provide operation in the current and planned air traffic control environment. The system design included software design listings for some of the required modules. The distributed microcomputer uses the IEEE 488 bus for interconnecting the microcomputer and sensors.

A Hospital Local Area Communication Network—The First Year's Experience

PubMed Central

Simborg, D. W.; Chadwick, M.; Whiting-O'Keefe, Q. E.; Tolchin, S. G.; Stewart, R. L.; Kahn, S. A.; Bergan, E. S.; Gafke, G. P.

1982-01-01

A local area communications network has been implemented at the University of California, San Francisco Hospital to integrate major components of the hospital's information system. This microprocessor-based network technology was developed by The Applied Physics Laboratory of the Johns Hopkins University. The first year's experience has demonstrated the basic feasibility of this technology in simplifying the integration of diverse hardware and software systems. Four minicomputer-based UCSF systems now use the network to synchronize key patient identification and registration information among the systems. Clinical uses of the network will begin during the second year of the project.

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial change to the current DMS design at this time.

A car theft deterrent system research based on ARM9

NASA Astrophysics Data System (ADS)

Zhang, Kaisheng; Liu, Jinhao; Fan, Lijun

2009-07-01

The traditional automotive burglarproof systems commonly only rely on the simple remote control to security which measures are not perfect and functions are too single. With the development of society, people tend to concern on the fingerprint recognition technology, GSM /GPRS wireless transmission technology, the idea of ARM9-based design of automobile burglarproof system is dependent on both of them. The S3C2410 microprocessor embedded system is used in this system, which is illuminated the idea of the control system design through the hardware and software. The spot use indicates that the high control precision, steady performance and the humanistic rational design of automotive burglarproof system.

Digital signal processing in microwave radiometers

NASA Technical Reports Server (NTRS)

Lawrence, R. W.; Stanley, W. D.; Harrington, R. F.

1980-01-01

A microprocessor based digital signal processing unit has been proposed to replace analog sections of a microwave radiometer. A brief introduction to the radiometer system involved and a description of problems encountered in the use of digital techniques in radiometer design are discussed. An analysis of the digital signal processor as part of the radiometer is then presented.

Fidelity Optimization of Microprocessor System Simulations.

DTIC Science & Technology

1981-03-01

effort feasible in terms of required CPU time would be to employ a separate clock with an artificially compressed time base in the serial...RETURN ILINCR -NU𔃾OPS D.% PROt.ESSING 900 IF IIERP2.NF.41 GO TO 1000 IFRCOD - L CALL VAIRCO 1A(61,NUMVALLEPCOOl IEPRZ -IEACCO IF hEARR .GT. 01 RETURN I

Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Choi, G.; Iyer, R. K.

1990-01-01

A simulation study is described which predicts the susceptibility of an advanced control system to electrical transients resulting in logic errors, latched errors, error propagation, and digital upset. The system is based on a custom-designed microprocessor and it incorporates fault-tolerant techniques. The system under test and the method to perform the transient injection experiment are described. Results for 2100 transient injections are analyzed and classified according to charge level, type of error, and location of injection.

Interface For Fault-Tolerant Control System

NASA Technical Reports Server (NTRS)

Shaver, Charles; Williamson, Michael

1989-01-01

Interface unit and controller emulator developed for research on electronic helicopter-flight-control systems equipped with artificial intelligence. Interface unit interrupt-driven system designed to link microprocessor-based, quadruply-redundant, asynchronous, ultra-reliable, fault-tolerant control system (controller) with electronic servocontrol unit that controls set of hydraulic actuators. Receives digital feedforward messages from, and transmits digital feedback messages to, controller through differential signal lines or fiber-optic cables (thus far only differential signal lines have been used). Analog signals transmitted to and from servocontrol unit via coaxial cables.

Engineering studies of vectorcardiographs in blood pressure measuring systems

NASA Technical Reports Server (NTRS)

Mark, R. G.

1975-01-01

The following projects involving cardiovascular instrumentation were conducted: (1) the development and fabrication of a three-dimensional display measurement system for vectorcardiograms, (2) the development and fabrication of a cardiovascular monitoring system to noninvasively monitor beat-by-beat the blood pressure and heart rate using aortic pulse wave velocity, (3) the development of software for an interactive system to analyze systolic time interval data, and (4) the development of microprocessor-based physiologic instrumentation, focussing initially on EKG rhythm analysis. Brief descriptions of these projects were given.

Earth Observation Services Weather Imaging

NASA Technical Reports Server (NTRS)

1992-01-01

Microprocessor-based systems for processing satellite data offer mariners real-time images of weather systems, day and night, of large areas or allow them to zoom in on a few square miles. Systems West markets these commercial image processing systems, which have significantly decreased the cost of satellite weather stations. The company was assisted by the EOCAP program, which provides government co-funding to encourage private investment in, and to broaden the use of, NASA-developed technology for analyzing information about Earth and ocean resources.

A Microprocessor-Controlled Data Acquisition System for the Federal Scientific Model UA-500-1 Ubiquitous Spectrum Analyzer

DTIC Science & Technology

1976-09-01

Model AN/ UGC -59A teletype and paper-tape punch console. This unit is connected with the Intellec 8 computer and punching operations are controlled by...order to use this program, the microprocessor would have to be one of the many types on the market that make use of the INTEL 8008-1 CPD chip. The use

The Use of a Microprocessor-Controlled, Video Output Atomic Absorption Spectrometer as an Educational Tool in a Two-Year Technical Curriculum.

ERIC Educational Resources Information Center

Kerfoot, Henry B.

Based on instructional experiences at Charles County Community College, Maryland, this report examines the pedagogical advantage of teaching atomic absorption (AA) spectroscopy with an AA spectrophotometer that is equipped with a microprocessor and video output mechanism. The report first discusses the growing importance of AA spectroscopy in…

A real-time implementation of an advanced sensor failure detection, isolation, and accommodation algorithm

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Merrill, W. C.

1983-01-01

A sensor failure detection, isolation, and accommodation algorithm was developed which incorporates analytic sensor redundancy through software. This algorithm was implemented in a high level language on a microprocessor based controls computer. Parallel processing and state-of-the-art 16-bit microprocessors are used along with efficient programming practices to achieve real-time operation.

A microprocessor-based table lookup approach for magnetic bearing linearization

NASA Technical Reports Server (NTRS)

Groom, N. J.; Miller, J. B.

1981-01-01

An approach for producing a linear transfer characteristic between force command and force output of a magnetic bearing actuator without flux biasing is presented. The approach is microprocessor based and uses a table lookup to generate drive signals for the magnetic bearing power driver. An experimental test setup used to demonstrate the feasibility of the approach is described, and test results are presented. The test setup contains bearing elements similar to those used in a laboratory model annular momentum control device.

Development of single cell protectors for sealed silver-zinc cells, phase 1

NASA Technical Reports Server (NTRS)

Imamura, M. S.; Donovan, R. L.; Lear, J. W.; Murray, B.

1976-01-01

A single cell protector (SCP) assembly capable of protecting a single silver-zinc (Ag Zn) battery cell was designed, fabricated, and tested. The SCP provides cell-level protection against overcharge and overdischarge by a bypass circuit. The bypass circuit consists of a magnetic-latching relay that is controlled by the high and low-voltage limit comparators. Although designed specifically for secondary Ag-Zn cells, the SCP is flexible enough to be adapted to other rechargeable cells. Eighteen SCPs were used in life testing of an 18-cell battery. The cells were sealed Ag-Zn system with inorganic separators. For comparison, another 18-cell battery was subjected to identical life test conditions, but with battery-level protection rather than cell-level. An alternative approach to the SCP design in the form of a microprocessor-based system was conceptually designed. The comparison of SCP and microprocessor approaches is also presented and a preferred approach for Ag-Zn battery protection is discussed.

Advanced Transport Operating System (ATOPS) color displays software description microprocessor system

NASA Technical Reports Server (NTRS)

Slominski, Christopher J.; Plyler, Valerie E.; Dickson, Richard W.

1992-01-01

This document describes the software created for the Sperry Microprocessor Color Display System used for the Advanced Transport Operating Systems (ATOPS) project on the Transport Systems Research Vehicle (TSRV). The software delivery known as the 'baseline display system', is the one described in this document. Throughout this publication, module descriptions are presented in a standardized format which contains module purpose, calling sequence, detailed description, and global references. The global reference section includes procedures and common variables referenced by a particular module. The system described supports the Research Flight Deck (RFD) of the TSRV. The RFD contains eight cathode ray tubes (CRTs) which depict a Primary Flight Display, Navigation Display, System Warning Display, Takeoff Performance Monitoring System Display, and Engine Display.

A Low Noise, Microprocessor-Controlled, Internally Digitizing Rotating-Vane Electric Field Mill for Airborne Platforms

NASA Technical Reports Server (NTRS)

Bateman, M. G.; Stewart, M. F.; Blakeslee, R. J.; Podgorny, s. J.; Christian, H. J.; Mach, D. M.; Bailey, J. C.; Daskar, D.

2006-01-01

This paper reports on a new generation of aircraft-based rotating-vane style electric field mills designed and built at NASA's Marshall Spaceflight Center. The mills have individual microprocessors that digitize the electric field signal at the mill and respond to commands from the data system computer. The mills are very sensitive (1 V/m per bit), have a wide dynamic range (115 dB), and are very low noise (+/-1 LSB). Mounted on an aircraft, these mills can measure fields from +/-1 V/m to +/-500 kV/m. Once-per-second commanding from the data collection computer to each mill allows for precise timing and synchronization. The mills can also be commanded to execute a self-calibration in flight, which is done periodically to monitor the status and health of each mill.

Global identification of target recognition and cleavage by the Microprocessor in human ES cells.

PubMed

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-11-10

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein-RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3' overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. © The Author(s) 2014. Published by Oxford University Press on behalf of Nucleic Acids Research.

The application of digital signal processing techniques to a teleoperator radar system

NASA Technical Reports Server (NTRS)

Pujol, A.

1982-01-01

A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

Synchronous clock stopper for microprocessor

NASA Technical Reports Server (NTRS)

Kitchin, David A. (Inventor)

1985-01-01

A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.

Microprocessor-based long term cardiorespirography. II. Status evaluation in term and premature newborns.

PubMed

Hörnchen, H; Betz, R; Kotlarek, F; Roebruck, P

1983-01-01

In 1965 URBACH et al. and RUDOLPH et al. [35, 39] described a loss of heart rate variability in severely ill neonates. In this study we investigated the correlation between instantaneous heart rate patterns and status diagnosis. We used a microprocessor-based cardiorespirography system. Seventy five newborn infants (51 prematures and 24 term neonates) were studied for about 12 hours each. Twenty nine patients had a second record after the first investigation. Parameters were: Type of frequency and oscillation, long time variability (LTV), short time variability (STV) and the newly introduced P-value (maximal difference between two successive R-peaks in five minutes). We found clear differences between the study groups. With increasing severity of illness mean values ("group mean values") of long time variability, short time variability and P-value decreased. Fixed heart rate became predominant. The most pronounced loss of heart rate variability was seen in infants with severe intracranial bleeding, thus offering a tentative diagnosis. For statistical analysis long time variability and the silent oscillation type have been proved as best parameters for this diagnosis. Severely decreased heart rate variations also have been seen in infants with acute renal failure--possibly because of brain edema--, after application of muscle relaxants, repeated doses of sedatives, and after prolonged anesthesia. Otherwise, the heart rate variability was probably dependent on age and gestational age in prematures and newborn infants without intracranial bleeding. It is possible to use microprocessor-based long time cardiorespirography as a simple screening method for the diagnosis of neonatal intracerebral bleeding. In future experiences transcutaneous measurements of oxygen tension should be included.

Radiation Test Results for Common CubeSat Microcontrollers and Microprocessors

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Amrbar, Mehran; Vartanian, Sergeh

2015-01-01

SEL, SEU, and TID results are presented for microcontrollers and microprocessors of interest for small satellite systems such as the TI MSP430F1611, MSP430F1612 and MSP430FR5739, Microchip PIC24F256GA110 and dsPIC33FJ256GP710, Atmel AT91SAM9G20, and Intel Atom E620T, and the Qualcomm Snapdragon APQ8064.

Digital system upset. The effects of simulated lightning-induced transients on a general-purpose microprocessor

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1983-01-01

Flight critical computer based control systems designed for advanced aircraft must exhibit ultrareliable performance in lightning charged environments. Digital system upset can occur as a result of lightning induced electrical transients, and a methodology was developed to test specific digital systems for upset susceptibility. Initial upset data indicates that there are several distinct upset modes and that the occurrence of upset is related to the relative synchronization of the transient input with the processing sate of the digital system. A large upset test data base will aid in the formulation and verification of analytical upset reliability modeling techniques which are being developed.

A microprocessor based on a two-dimensional semiconductor.

PubMed

Wachter, Stefan; Polyushkin, Dmitry K; Bethge, Ole; Mueller, Thomas

2017-04-11

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor-molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

A microprocessor based on a two-dimensional semiconductor

NASA Astrophysics Data System (ADS)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

Microprocessor controlled transdermal drug delivery.

PubMed

Subramony, J Anand; Sharma, Ashutosh; Phipps, J B

2006-07-06

Transdermal drug delivery via iontophoresis is reviewed with special focus on the delivery of lidocaine for local anesthesia and fentanyl for patient controlled acute therapy such as postoperative pain. The role of the microprocessor controller in achieving dosimetry, alternating/reverse polarity, pre-programmed, and sensor-based delivery is highlighted. Unique features such as the use of tactile signaling, telemetry control, and pulsatile waveforms in iontophoretic drug delivery are described briefly.

TMS communications software. Volume 2: Bus interface unit

NASA Technical Reports Server (NTRS)

Gregor, P. J.

1979-01-01

A data bus communication system to support the space shuttle's Trend Monitoring System (TMS) and to provide a basis for evaluation of the bus concept is described. Installation of the system included developing both hardware and software interfaces between the bus and the specific TMS computers and terminals. The software written for the microprocessor-based bus interface units is described. The software implements both the general bus communications protocol and also the specific interface protocols for the TMS computers and terminals.

Specifications Physiological Monitoring System

NASA Technical Reports Server (NTRS)

1985-01-01

The operation of a physiological monitoring system (PMS) is described. Specifications were established for performance, design, interface, and test requirements. The PMS is a compact, microprocessor-based system, which can be worn in a pack on the body or may be mounted on a Spacelab rack or other appropriate structure. It consists of two modules, the Data Control Unit (DCU) and the Remote Control/Display Unit (RCDU). Its purpose is to collect and distribute data from physiological experiments in the Spacelab and in the Orbiter.

Embedded control system for computerized franking machine

NASA Astrophysics Data System (ADS)

Shi, W. M.; Zhang, L. B.; Xu, F.; Zhan, H. W.

2007-12-01

This paper presents a novel control system for franking machine. A methodology for operating a franking machine using the functional controls consisting of connection, configuration and franking electromechanical drive is studied. A set of enabling technologies to synthesize postage management software architectures driven microprocessor-based embedded systems is proposed. The cryptographic algorithm that calculates mail items is analyzed to enhance the postal indicia accountability and security. The study indicated that the franking machine is reliability, performance and flexibility in printing mail items.

A Feasibility Study for Advanced Technology Integration for General Aviation.

DTIC Science & Technology

1980-05-01

154 4.5.9.4 Stratified Charge Reciprocating Engine ..... .. 155 4.5.9.5 Advanced Diesel Engine . ... 158 4.5.9.6 Liquid Cooling ... ........ 159... diesel , rotary combustion engine, advanced reciprocating engine concepts. (7) Powerplant control - integrated controls, microprocessor- based controls...Research Center Topics. (1) GATE (2) Positive displacement engines (a) Advanced reciprocating engines. (b) Alternative engine systems Diesel engines

Force Measurements in Magnetic Suspension and Balance System

NASA Technical Reports Server (NTRS)

Kuzin, Alexander; Shapovalov, George; Prohorov, Nikolay

1996-01-01

The description of an infrared telemetry system for measurement of drag forces in Magnetic Suspension and Balance Systems (MSBS) is presented. This system includes a drag force sensor, electronic pack and transmitter placed in the model which is of special construction, and receiver with a microprocessor-based measuring device, placed outside of the test section. Piezosensitive resonators as sensitive elements and non-magnetic steel as the material for the force sensor are used. The main features of the proposed system for load measurements are discussed and the main characteristics are presented.

Cumulative Timers for Microprocessors

NASA Technical Reports Server (NTRS)

Battle, John O.

2007-01-01

It has been proposed to equip future microprocessors with electronic cumulative timers, for essentially the same reasons for which land vehicles are equipped with odometers (total-distance-traveled meters) and aircraft are equipped with Hobbs meters (total-engine-operating time meters). Heretofore, there has been no way to determine the amount of use to which a microprocessor (or a product containing a microprocessor) has been subjected. The proposed timers would count all microprocessor clock cycles and could only be read by means of microprocessor instructions but, like odometers and Hobbs meters, could never be reset to zero without physically damaging the chip.

Design of measuring system for wire diameter based on sub-pixel edge detection algorithm

NASA Astrophysics Data System (ADS)

Chen, Yudong; Zhou, Wang

2016-09-01

Light projection method is often used in measuring system for wire diameter, which is relatively simpler structure and lower cost, and the measuring accuracy is limited by the pixel size of CCD. Using a CCD with small pixel size can improve the measuring accuracy, but will increase the cost and difficulty of making. In this paper, through the comparative analysis of a variety of sub-pixel edge detection algorithms, polynomial fitting method is applied for data processing in measuring system for wire diameter, to improve the measuring accuracy and enhance the ability of anti-noise. In the design of system structure, light projection method with orthogonal structure is used for the detection optical part, which can effectively reduce the error caused by line jitter in the measuring process. For the electrical part, ARM Cortex-M4 microprocessor is used as the core of the circuit module, which can not only drive double channel linear CCD but also complete the sampling, processing and storage of the CCD video signal. In addition, ARM microprocessor can complete the high speed operation of the whole measuring system for wire diameter in the case of no additional chip. The experimental results show that sub-pixel edge detection algorithm based on polynomial fitting can make up for the lack of single pixel size and improve the precision of measuring system for wire diameter significantly, without increasing hardware complexity of the entire system.

Technology transfer of military space microprocessor developments

NASA Astrophysics Data System (ADS)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

Development of a microprocessor controller for stand-alone photovoltaic power systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

System and method for bidirectional flow and controlling fluid flow in a conduit

DOEpatents

Ortiz, Marcos German

1999-01-01

A system for measuring bidirectional flow, including backflow, of fluid in a conduit. The system utilizes a structural mechanism to create a pressure differential in the conduit. Pressure sensors are positioned upstream from the mechanism, at the mechanism, and downstream from the mechanism. Data from the pressure sensors are transmitted to a microprocessor or computer, and pressure differential detected between the pressure sensors is then used to calculate the backflow. Control signals may then be generated by the microprocessor or computer to shut off valves located in the conduit, upon the occurrence of backflow, or to control flow, total material dispersed, etc. in the conduit.

Predictive sensor method and apparatus

NASA Technical Reports Server (NTRS)

Cambridge, Vivien J.; Koger, Thomas L.

1993-01-01

A microprocessor and electronics package employing predictive methodology was developed to accelerate the response time of slowly responding hydrogen sensors. The system developed improved sensor response time from approximately 90 seconds to 8.5 seconds. The microprocessor works in real-time providing accurate hydrogen concentration corrected for fluctuations in sensor output resulting from changes in atmospheric pressure and temperature. Following the successful development of the hydrogen sensor system, the system and predictive methodology was adapted to a commercial medical thermometer probe. Results of the experiment indicate that, with some customization of hardware and software, response time improvements are possible for medical thermometers as well as other slowly responding sensors.

Deepthi Vaidhynathan | NREL

Science.gov Websites

Complex Systems Simulation and Optimization Group on performance analysis and benchmarking latest . Research Interests High Performance Computing|Embedded System |Microprocessors & Microcontrollers

Using benchmarks for radiation testing of microprocessors and FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Robinson, William H.; Rech, Paolo

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

Using benchmarks for radiation testing of microprocessors and FPGAs

DOE PAGES

Quinn, Heather; Robinson, William H.; Rech, Paolo; ...

2015-12-17

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

An Economic Analysis of Two Groundwater Allocation Programs for the Salinas Valley

DTIC Science & Technology

1994-06-01

monitoring system would establish a definable and 17Each individual well would have a frequency generator, analog/ digital converter, microprocessor with...RTU). The cost for purchasing and installing the frequency generator is estimated to be $1,100. The RTU consists of an analog/ digital converter and a...programmable microprocessor that can accept up to eight inputs and one output. The unit can transmit and receive digital data via LAN network or

Programmable data collection platform study

NASA Technical Reports Server (NTRS)

1976-01-01

The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.

Microprocessor Technology for Managers.

DTIC Science & Technology

1976-05-01

HOURS IS THE APPLICATION OF MICROPROCESSORS TO VIDEO GAMES SUCH AS PING PONG, HANDBALL 1 SPACE WAR GAMES , AND COWBOYS AND INDIANS. MANY MANUFACTURERS OF...MICR OPROCESSOR COMPANIES AEG—T ELEFUNKEN~ 6 FRANKFURT 70, AEG-HOCHHAUS 1 GERMANY . ADAPTIVE SYSTEMS1 P.O . BOX 1481, POMPANO BEACH , FL 33061. -(305...KAWASAKI — CHI , JAPAN . WESTERN DIGITAL , 19242 RED HILL AVE. 1 NEWPORT BEACH I CA 92663. {714) 557-3550. ZILOG, 170 STATE ST., LOS ALTOS 1 CA 94022. {415

Power Converters Maximize Outputs Of Solar Cell Strings

NASA Technical Reports Server (NTRS)

Frederick, Martin E.; Jermakian, Joel B.

1993-01-01

Microprocessor-controlled dc-to-dc power converters devised to maximize power transferred from solar photovoltaic strings to storage batteries and other electrical loads. Converters help in utilizing large solar photovoltaic arrays most effectively with respect to cost, size, and weight. Main points of invention are: single controller used to control and optimize any number of "dumb" tracker units and strings independently; power maximized out of converters; and controller in system is microprocessor.

Failure analysis on false call probe pins of microprocessor test equipment

NASA Astrophysics Data System (ADS)

Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

2017-09-01

A study has been conducted to investigate failure analysis on probe pins of test modules for microprocessor. The `health condition' of the probe pin is determined by the resistance value. A test module of 5V power supplied from Arduino UNO with "Four-wire Ohm measurement" method is implemented in this study to measure the resistance of the probe pins of a microprocessor. The probe pins from a scrapped computer motherboard is used as the test sample in this study. The functionality of the test module was validated with the pre-measurement experiment via VEE Pro software. Lastly, the experimental work have demonstrated that the implemented test module have the capability to identify the probe pin's `health condition' based on the measured resistance value.

European Scientific Notes. Volume 35, Number 12,

DTIC Science & Technology

1981-12-31

been redesigned to work A. Osorio, which was organized some 3 with the Intel 8085 microprocessor, it years ago and contains about half of the has the...operational set. attempt to derive a set of invariants MOISE is based on the Intel 8085A upon which virtually speaker-invariant microprocessor, and...FACILITY software interface; a Research Signal Processor (RSP) using reduced computational It has been IBM International’s complexity algorithms for

Microprocessor-based cardiotachometer

NASA Technical Reports Server (NTRS)

Crosier, W. G.; Donaldson, J. A.

1981-01-01

Instrument operates reliably even with stress-test electrocardiogram (ECG) signals subject to noise, baseline wandering, and amplitude change. It records heart rate from preamplified, single-lead ECG input signal and produces digital and analog heart-rate outputs which are fed elsewhere. Analog hardware processes ECG input signal, producing 10-ms pulse for each heartbeat. Microprocessor analyzes resulting pulse train, identifying irregular heartbeats and maintaining stable output during lead switching. Easily modified computer program provides analysis.

Distributed Micro-Processor Applications to Guidance and Control Systems.

DTIC Science & Technology

1982-07-01

nanoseconds compared with 22 milliseconds for the older type of NMOS non-volatile RAM. This non-volatile RAM is estimated to hold its memory for 100 years...illustrated in figure 1.4.3.3 and compared with the traditional permalog chevron bubble structure. The contiguous element bubble structure is being developed ...M for its 8086 based Digital Advanced Avionics System (DAAS) developed for NASA Ames, but rejected it as being unsuitable. Ada is the new DoD

Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.

1977-01-01

The feasibility of performing the same task in real time using microprocessor technology was determined. The least square algorithm was implemented on an Intel 8080 microprocessor. Results indicated that a microprocessor could easily match the IBM implementation in accuracy and be performed inside the time limitations set.

Prototype microprocessor controller. [for STDN antennas

NASA Technical Reports Server (NTRS)

Zarur, J.; Kraeuter, R.

1980-01-01

A microcomputer controller for STDN antennas was developed. The microcomputer technology reduces the system's physical size by the implementation in firmware of functions. The reduction in the number of components increases system reliability and similar benefit is derived when a graphic video display is substituted for several control and indicator panels. A substantial reduction in the number of cables, connectors, and mechanical switches is achieved. The microcomputer based system is programmed to perform calibration and diagnostics, to update the satellite orbital vector, and to communicate with other network systems. The design is applicable to antennas and lasers.

Expert systems applied to fault isolation and energy storage management, phase 2

NASA Technical Reports Server (NTRS)

1987-01-01

A user's guide for the Fault Isolation and Energy Storage (FIES) II system is provided. Included are a brief discussion of the background and scope of this project, a discussion of basic and advanced operating installation and problem determination procedures for the FIES II system and information on hardware and software design and implementation. A number of appendices are provided including a detailed specification for the microprocessor software, a detailed description of the expert system rule base and a description and listings of the LISP interface software.

Versatile, low-cost, computer-controlled, sample positioning system for vacuum applications

NASA Technical Reports Server (NTRS)

Vargas-Aburto, Carlos; Liff, Dale R.

1991-01-01

A versatile, low-cost, easy to implement, microprocessor-based motorized positioning system (MPS) suitable for accurate sample manipulation in a Second Ion Mass Spectrometry (SIMS) system, and for other ultra-high vacuum (UHV) applications was designed and built at NASA LeRC. The system can be operated manually or under computer control. In the latter case, local, as well as remote operation is possible via the IEEE-488 bus. The position of the sample can be controlled in three linear orthogonal and one angular coordinates.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

Personal Cabin Pressure Monitor and Warning System

NASA Technical Reports Server (NTRS)

Zysko, Jan A. (Inventor)

2002-01-01

A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.

Personal Cabin Pressure Monitor and Warning System

NASA Astrophysics Data System (ADS)

Zysko, Jan A.

2002-09-01

A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.

An FPGA computing demo core for space charge simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Jinyuan; Huang, Yifei; /Fermilab

2009-01-01

In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computedmore » using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.« less

Microprocessors in U.S. Electrical Engineering Departments, 1974-1975.

ERIC Educational Resources Information Center

Sloan, M. E.

Drawn from a survey of engineering departments known to be teaching microprocessor courses, this paper shows that the adoption of microprocessors by Electrical Engineering Departments has been rapid compared with their adoption of minicomputers. The types of courses that are being taught can be categorized as: surveys of microprocessors, intensive…

76 FR 39895 - In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-07

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-781] In the Matter of Certain Microprocessors... importation of certain microprocessors, components thereof, and products containing same by reason of... microprocessors, components thereof, and products containing same that infringe one or more of claims 11-16, 41...

Development of a Low-Cost, Stand-Alone Microterminal for Support of Testing and Instruction. Final Report for Period January 1977-February 1978.

ERIC Educational Resources Information Center

Steffen, Dale A.; And Others

A study was undertaken to develop a microterminal for use in a computer-based instructional system. Objectives were to use new microprocessor technology to produce one terminal that is more effective and efficient than either the management terminal or the plasma type interactive terminal presently in use by the Air Force Advanced Instructional…

The special radiation-hardened processors for new highly informative experiments in space

NASA Astrophysics Data System (ADS)

Serdin, O. V.; Antonov, A. A.; Dubrovsky, A. G.; Novogilov, E. A.; Zuev, A. L.

2017-01-01

The article provides a detailed description of the series of special radiation-hardened microprocessor developed by SRISA for use in space technology. The microprocessors have 32-bit and 64-bit KOMDIV architecture with embedded SpaceWire, RapidIO, Ethernet and MIL-STD-1553B interfaces. These devices are used in space telescope GAMMA-400 data acquisition system, and may also be applied to other experiments in space (such as observatory “Millimetron” etc.).

Test report for single event effects of the 80386DX microprocessor

NASA Technical Reports Server (NTRS)

Watson, R. Kevin; Schwartz, Harvey R.; Nichols, Donald K.

1993-01-01

The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.

TDP-43 regulates the microprocessor complex activity during in vitro neuronal differentiation.

PubMed

Di Carlo, Valerio; Grossi, Elena; Laneve, Pietro; Morlando, Mariangela; Dini Modigliani, Stefano; Ballarino, Monica; Bozzoni, Irene; Caffarelli, Elisa

2013-12-01

TDP-43 (TAR DNA-binding protein 43) is an RNA-binding protein implicated in RNA metabolism at several levels. Even if ubiquitously expressed, it is considered as a neuronal activity-responsive factor and a major signature for neurological pathologies, making the comprehension of its activity in the nervous system a very challenging issue. TDP-43 has also been described as an accessory component of the Drosha-DGCR8 (DiGeorge syndrome critical region gene 8) microprocessor complex, which is crucially involved in basal and tissue-specific RNA processing events. In the present study, we exploited in vitro neuronal differentiation systems to investigate the TDP-43 demand for the microprocessor function, focusing on both its canonical microRNA biosynthetic activity and its alternative role as a post-transcriptional regulator of gene expression. Our findings reveal a novel role for TDP-43 as an essential factor that controls the stability of Drosha protein during neuronal differentiation, thus globally affecting the production of microRNAs. We also demonstrate that TDP-43 is required for the Drosha-mediated regulation of Neurogenin 2, a master gene orchestrating neurogenesis, whereas post-transcriptional control of Dgcr8, another Drosha target, resulted to be TDP-43-independent. These results implicate a previously uncovered contribution of TDP-43 in regulating the abundance and the substrate specificity of the microprocessor complex and provide new insights into TDP-43 as a key player in neuronal differentiation.

Autoregulatory mechanisms controlling the Microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2010-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature 22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part ofa newly identified regulatory mechanism controlling Microprocessor activity.

Maximum Temperature Detection System for Integrated Circuits

NASA Astrophysics Data System (ADS)

Frankiewicz, Maciej; Kos, Andrzej

2015-03-01

The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

Experience in the installation of a microprocessor system for controlling converter units of the Vyborg substation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gusakovskii, K. B.; Zmaznov, E. Yu.; Katantsev, S. V.

The experience in the installation of modern digital systems for controlling converter units at the Vyborg converter substation on the basis of advanced microprocessor devices is considered. It is shown that debugging of a control and protection system on mathematical and physical models does not guarantee optimum control of actual converter devices. Examples of advancing the control and protection system are described, the necessity for which has become obvious in tests of actual equipment. Comparison of oscillograms of processes before optimization of the control system and after its optimization and adjustment shows that the digital control system makes it possiblemore » to improve substantially the algorithms of control and protection in the short term and without changing the hardware component.« less

FPGA-based multiprocessor system for injection molding control.

PubMed

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P; Osornio-Rios, Roque A

2012-10-18

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

Development report: Automatic System Test and Calibration (ASTAC) equipment

NASA Technical Reports Server (NTRS)

Thoren, R. J.

1981-01-01

A microcomputer based automatic test system was developed for the daily performance monitoring of wind energy system time domain (WEST) analyzer. The test system consists of a microprocessor based controller and hybrid interface unit which are used for inputing prescribed test signals into all WEST subsystems and for monitoring WEST responses to these signals. Performance is compared to theoretically correct performance levels calculated off line on a large general purpose digital computer. Results are displayed on a cathode ray tube or are available from a line printer. Excessive drift and/or lack of repeatability of the high speed analog sections within WEST is easily detected and the malfunctioning hardware identified using this system.

The Single Event Effect Characteristics of the 486-DX4 Microprocessor

NASA Technical Reports Server (NTRS)

Kouba, Coy; Choi, Gwan

1996-01-01

This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

General, database-driven fast-feedback system for the Stanford Linear Collider

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rouse, F.; Allison, S.; Castillo, S.

A new feedback system has been developed for stabilizing the SLC beams at many locations. The feedback loops are designed to sample and correct at the 60 Hz repetition rate of the accelerator. Each loop can be distributed across several of the standard 80386 microprocessors which control the SLC hardware. A new communications system, KISNet, has been implemented to pass signals between the microprocessors at this rate. The software is written in a general fashion using the state space formalism of digital control theory. This allows a new loop to be implemented by just setting up the online database andmore » perhaps installing a communications link. 3 refs., 4 figs.« less

System and method for bidirectional flow and controlling fluid flow in a conduit

DOEpatents

Ortiz, M.G.

1999-03-23

A system for measuring bidirectional flow, including backflow, of fluid in a conduit is disclosed. The system utilizes a structural mechanism to create a pressure differential in the conduit. Pressure sensors are positioned upstream from the mechanism, at the mechanism, and downstream from the mechanism. Data from the pressure sensors are transmitted to a microprocessor or computer, and pressure differential detected between the pressure sensors is then used to calculate the backflow. Control signals may then be generated by the microprocessor or computer to shut off valves located in the conduit, upon the occurrence of backflow, or to control flow, total material dispersed, etc. in the conduit. 3 figs.

Debris measure subsystem of the nanosatellite IRECIN

NASA Astrophysics Data System (ADS)

Ferrante, M.; di Ciolo, L.; Ortenzi, A.; Petrozzi, M.; del Re, V.

2003-09-01

The on board resources, needed to perform the mission tasks, are very limited in nano-satellites. This paper proposes an Electronic real-time system that acquires space debris measures. It uses a piezo-electric sensor. The described device is a subsystem on board of the IRECIN nanosatellite composed mainly by a r.i.s.c. microprocessor, an electronic part that interfaces to the debris sensor in order to provide a low noise electrical and suitable range to ADC 12 bit converter, and finally a memory in order to store the data. The microprocessor handles the Debris Measure System measuring the impacts number, their intensity and storing their waves form. This subsystem is able to communicate with the other IRECIN subsystems through I2C Bus and principally with the "Main Microprocessor" subsystem allowing the data download directly to the Ground Station. Moreover this subsystem lets free the "Main Microprocessor Board" from the management and charge of debris data. All electronic components are SMD technology in order to reduce weight and size. The realized Electronic board are completely developed, realized and tested at the Vitrociset S.P.A. under control of Research and Development Group. The proposed system is implemented on the IRECIN, a modular nanosatellite weighting less than 1.5 kg, constituted by sixteen external sides with surface-mounted solar cells and three internal Al plates, kept together by four steel bars. Lithium-ions batteries are added for eclipse operations. Attitude is determined by two three-axis magnetometers and the solar panels data. Control is provided by an active magnetic control system. The spacecraft will be spin-stabilized with the spin-axis normal to the orbit. debris and micrometeoroids mass and velocity.

Design of Remote GPRS-based Gas Data Monitoring System

NASA Astrophysics Data System (ADS)

Yan, Xiyue; Yang, Jianhua; Lu, Wei

2018-01-01

In order to solve the problem of remote data transmission of gas flowmeter, and realize unattended operation on the spot, an unattended remote monitoring system based on GPRS for gas data is designed in this paper. The slave computer of this system adopts embedded microprocessor to read data of gas flowmeter through rs-232 bus and transfers it to the host computer through DTU. In the host computer, the VB program dynamically binds the Winsock control to receive and parse data. By using dynamic data exchange, the Kingview configuration software realizes history trend curve, real time trend curve, alarm, print, web browsing and other functions.

Integrating Software Modules For Robot Control

NASA Technical Reports Server (NTRS)

Volpe, Richard A.; Khosla, Pradeep; Stewart, David B.

1993-01-01

Reconfigurable, sensor-based control system uses state variables in systematic integration of reusable control modules. Designed for open-architecture hardware including many general-purpose microprocessors, each having own local memory plus access to global shared memory. Implemented in software as extension of Chimera II real-time operating system. Provides transparent computing mechanism for intertask communication between control modules and generic process-module architecture for multiprocessor realtime computation. Used to control robot arm. Proves useful in variety of other control and robotic applications.

A microprocessor based on a two-dimensional semiconductor

PubMed Central

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-01-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III–V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor—molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material. PMID:28398336

Provably secure time distribution for the electric grid

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith IV, Amos M; Evans, Philip G; Williams, Brian P

We demonstrate a quantum time distribution (QTD) method that combines the precision of optical timing techniques with the integrity of quantum key distribution (QKD). Critical infrastructure is dependent on microprocessor- and programmable logic-based monitoring and control systems. The distribution of timing information across the electric grid is accomplished by GPS signals which are known to be vulnerable to spoofing. We demonstrate a method for synchronizing remote clocks based on the arrival time of photons in a modifed QKD system. This has the advantage that the signal can be veried by examining the quantum states of the photons similar to QKD.

Update on radiation-hardened microcomputers for robotics and teleoperated systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sias, F.R. Jr.; Tulenko, J.S.

1993-12-31

Since many programs sponsored by the Department of Defense are being canceled, it is important to select carefully radiation-hardened microprocessors for projects that will mature (or will require continued support) several years in the future. At the present time there are seven candidate 32-bit processors that should be considered for long-range planning for high-performance radiation-hardened computer systems. For Department of Energy applications it is also important to consider efforts at standardization that require the use of the VxWorks operating system and hardware based on the VMEbus. Of the seven processors, one has been delivered and is operating and other systemsmore » are scheduled to be delivered late in 1993 or early in 1994. At the present time the Honeywell-developed RH32, the Harris RH-3000 and the Harris RHC-3000 are leading contenders for meeting DOE requirements for a radiation-hardened advanced 32-bit microprocessor. These are all either compatible with or are derivatives of the MIPS R3000 Reduced Instruction Set Computer. It is anticipated that as few as two of the seven radiation-hardened processors will be supported by the space program in the long run.« less

Implementation of the DAST ARW II control laws using an 8086 microprocessor and an 8087 floating-point coprocessor. [drones for aeroelasticity research

NASA Technical Reports Server (NTRS)

Kelly, G. L.; Berthold, G.; Abbott, L.

1982-01-01

A 5 MHZ single-board microprocessor system which incorporates an 8086 CPU and an 8087 Numeric Data Processor is used to implement the control laws for the NASA Drones for Aerodynamic and Structural Testing, Aeroelastic Research Wing II. The control laws program was executed in 7.02 msec, with initialization consuming 2.65 msec and the control law loop 4.38 msec. The software emulator execution times for these two tasks were 36.67 and 61.18, respectively, for a total of 97.68 msec. The space, weight and cost reductions achieved in the present, aircraft control application of this combination of a 16-bit microprocessor with an 80-bit floating point coprocessor may be obtainable in other real time control applications.

"Smart" Sensor Module

NASA Technical Reports Server (NTRS)

Mahajan, Ajay

2007-01-01

An assembly that contains a sensor, sensor-signal-conditioning circuitry, a sensor-readout analog-to-digital converter (ADC), data-storage circuitry, and a microprocessor that runs special-purpose software and communicates with one or more external computer(s) has been developed as a prototype of "smart" sensor modules for monitoring the integrity and functionality (the "health") of engineering systems. Although these modules are now being designed specifically for use on rocket-engine test stands, it is anticipated that they could also readily be designed to be incorporated into health-monitoring subsystems of such diverse engineering systems as spacecraft, aircraft, land vehicles, bridges, buildings, power plants, oilrigs, and defense installations. The figure is a simplified block diagram of the "smart" sensor module. The analog sensor readout signal is processed by the ADC, the digital output of which is fed to the microprocessor. By means of a standard RS-232 cable, the microprocessor is connected to a local personal computer (PC), from which software is downloaded into a randomaccess memory in the microprocessor. The local PC is also used to debug the software. Once the software is running, the local PC is disconnected and the module is controlled by, and all output data from the module are collected by, a remote PC via an Ethernet bus. Several smart sensor modules like this one could be connected to the same Ethernet bus and controlled by the single remote PC. The software running in the microprocessor includes driver programs for operation of the sensor, programs that implement self-assessment algorithms, programs that implement protocols for communication with the external computer( s), and programs that implement evolutionary methodologies to enable the module to improve its performance over time. The design of the module and of the health-monitoring system of which it is a part reflects the understanding that the main purpose of a health-monitoring system is to detect damage and, therefore, the health-monitoring system must be able to function effectively in the presence of damage and should be capable of distinguishing between damage to itself and damage to the system being monitored. A major benefit afforded by the self-assessment algorithms is that in the output of the module, the sensor data indicative of the health of the engineering system being monitored are coupled with a confidence factor that quantifies the degree of reliability of the data. Hence, the output includes information on the health of the sensor module itself in addition to information on the health of the engineering system being monitored.

Microprocessor Control Design for a Low-Head Crossflow Turbine.

DTIC Science & Technology

1985-03-01

Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

Autoregulatory mechanisms controlling the microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2011-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature ∼22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part of a newly identified regulatory mechanism controlling Microprocessor activity.

Post-transcriptional control of DGCR8 expression by the Microprocessor.

PubMed

Triboulet, Robinson; Chang, Hao-Ming; Lapierre, Robert J; Gregory, Richard I

2009-06-01

The Microprocessor, comprising the RNase III Drosha and the double-stranded RNA binding protein DGCR8, is essential for microRNA (miRNA) biogenesis. In the miRNA processing pathway certain hairpin structures within primary miRNA (pri-miRNA) transcripts are specifically cleaved by the Microprocessor to release approximately 60-70-nucleotide precursor miRNA (pre-miRNA) intermediates. Although both Drosha and DGCR8 are required for Microprocessor activity, the mechanisms regulating the expression of these proteins are unknown. Here we report that the Microprocessor negatively regulates DGCR8 expression. Using in vitro reconstitution and in vivo studies, we demonstrate that a hairpin, localized in the 5' untranslated region (5'UTR) of DGCR8 mRNA, is cleaved by the Microprocessor. Accordingly, knockdown of Drosha leads to an increase in DGCR8 mRNA and protein levels in cells. Furthermore, we found that the DGCR8 5'UTR confers Microprocessor-dependent repression of a luciferase reporter gene in vivo. Our results uncover a novel feedback loop that regulates DGCR8 levels.

Microprocessors in Schools?

ERIC Educational Resources Information Center

Cuthbert, L. G.

1981-01-01

Examines reasons for including microprocessors in school curricula. Indicates that practical work with microprocessors is not easy and discusses problems associated with using and constructing these control and processing devices of microcomputers. (SK)

Computer Technology: State of the Art.

ERIC Educational Resources Information Center

Withington, Frederic G.

1981-01-01

Describes the nature of modern general-purpose computer systems, including hardware, semiconductor electronics, microprocessors, computer architecture, input output technology, and system control programs. Seven suggested readings are cited. (FM)

Microprocessor prosthetic knees.

PubMed

Berry, Dale

2006-02-01

This article traces the development of microprocessor prosthetic knees from early research in the 1970s to the present. Read about how microprocessor knees work, functional options, patient selection, and the future of this prosthetic.

Development of land based radar polarimeter processor system

NASA Technical Reports Server (NTRS)

Kronke, C. W.; Blanchard, A. J.

1983-01-01

The processing subsystem of a land based radar polarimeter was designed and constructed. This subsystem is labeled the remote data acquisition and distribution system (RDADS). The radar polarimeter, an experimental remote sensor, incorporates the RDADS to control all operations of the sensor. The RDADS uses industrial standard components including an 8-bit microprocessor based single board computer, analog input/output boards, a dynamic random access memory board, and power supplis. A high-speed digital electronics board was specially designed and constructed to control range-gating for the radar. A complete system of software programs was developed to operate the RDADS. The software uses a powerful real time, multi-tasking, executive package as an operating system. The hardware and software used in the RDADS are detailed. Future system improvements are recommended.

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2013 CFR

2013-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2010 CFR

2010-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for ‘military...

Code of Federal Regulations, 2014 CFR

2014-01-01

... reexports of general purpose microprocessors for âmilitary end usesâ and to âmilitary end usersâ. 744.17... microprocessors for ‘military end uses’ and to ‘military end users’. (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2012 CFR

2012-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2011 CFR

2011-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

Vibration monitoring of Kraftwerk Union pressurized water reactors - Review, present status, and further development

DOE Office of Scientific and Technical Information (OSTI.GOV)

Stolben, H.; Wehling, H.J.

Incipient damage to mechanical structure may be detected early in time by deviations from normal dynamic behavior. For vibration monitoring of coupled systems, only a small number of transducers are necessary, in general. On the basis, Kraftwerk Union has been involved in the development and construction of vibration monitoring systems for pressurized water reactors over the last 20 yr. The current state of the art permits vibration monitoring during normal operation by reactor personnel without expert assistance. The new SUS-86 microprocessor-based system allows further expansion toward an expert system.

Microprocessor tester for the treat upgrade reactor trip system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lenkszus, F.R.; Bucher, R.G.

1984-01-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety systemmore » is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations.« less

Generic interpreters and microprocessor verification

NASA Technical Reports Server (NTRS)

Windley, Phillip J.

1990-01-01

The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocessors; (3) microprocessor verification; (4) determining correctness; (5) hierarchical decomposition; (6) interpreter theory; (7) AVM-1; (8) phase-level specification; and future work.

Research and design of intelligent distributed traffic signal light control system based on CAN bus

NASA Astrophysics Data System (ADS)

Chen, Yu

2007-12-01

Intelligent distributed traffic signal light control system was designed based on technologies of infrared, CAN bus, single chip microprocessor (SCM), etc. The traffic flow signal is processed with the core of SCM AT89C51. At the same time, the SCM controls the CAN bus controller SJA1000/transceiver PCA82C250 to build a CAN bus communication system to transmit data. Moreover, up PC realizes to connect and communicate with SCM through USBCAN chip PDIUSBD12. The distributed traffic signal light control system with three control styles of Vehicle flux, remote and PC is designed. This paper introduces the system composition method and parts of hardware/software design in detail.

FPGA-Based Multiprocessor System for Injection Molding Control

PubMed Central

Muñoz-Barron, Benigno; Morales-Velazquez, Luis; Romero-Troncoso, Rene J.; Rodriguez-Donate, Carlos; Trejo-Hernandez, Miguel; Benitez-Rangel, Juan P.; Osornio-Rios, Roque A.

2012-01-01

The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA) device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected. PMID:23202036

Nuclear Science Symposium, 23rd, Scintillation and Semiconductor Counter Symposium, 15th, and Nuclear Power Systems Symposium, 8th, New Orleans, La., October 20-22, 1976, Proceedings

NASA Technical Reports Server (NTRS)

Wagner, L. J.

1977-01-01

The volume includes papers on semiconductor radiation detectors of various types, components of radiation detection and dosimetric systems, digital and microprocessor equipment in nuclear industry and science, and a wide variety of applications of nuclear radiation detectors. Semiconductor detectors of X-rays, gamma radiation, heavy ions, neutrons, and other nuclear particles, plastic scintillator arrays, drift chambers, spark wire chambers, and radiation dosimeter systems are reported on. Digital and analog conversion systems, digital data and control systems, microprocessors, and their uses in scientific research and nuclear power plants are discussed. Large-area imaging and biomedical nucleonic instrumentation, nuclear power plant safeguards, reactor instrumentation, nuclear power plant instrumentation, space instrumentation, and environmental instrumentation are dealt with. Individual items are announced in this issue.

Microprocessor controlled portable TLD system

NASA Technical Reports Server (NTRS)

Apathy, I.; Deme, S.; Feher, I.

1996-01-01

An up-to-date microprocessor controlled thermoluminescence dosemeter (TLD) system for environmental and space dose measurements has been developed. The earlier version of the portable TLD system, Pille, was successfully used on Soviet orbital stations as well as on the US Space Shuttle, and for environmental monitoring. The new portable TLD system, Pille'95, consists of a reader and TL bulb dosemeters, and each dosemeter is provided with an EEPROM chip for automatic identification. The glow curve data are digitised and analysed by the program of the reader. The measured data and the identification number appear on the LED display of the reader. Up to several thousand measured data together with the glow curves can be stored on a removable flash memory card. The whole system is supplied either from built-in rechargeable batteries or from the mains of the space station.

Progress on advanced dc and ac induction drives for electric vehicles

NASA Technical Reports Server (NTRS)

Schwartz, H. J.

1982-01-01

Progress is reported in the development of complete electric vehicle propulsion systems, and the results of tests on the Road Load Simulator of two such systems representative of advanced dc and ac drive technology are presented. One is the system used in the DOE's ETV-1 integrated test vehicle which consists of a shunt wound dc traction motor under microprocessor control using a transistorized controller. The motor drives the vehicle through a fixed ratio transmission. The second system uses an ac induction motor controlled by transistorized pulse width modulated inverter which drives through a two speed automatically shifted transmission. The inverter and transmission both operate under the control of a microprocessor. The characteristics of these systems are also compared with the propulsion system technology available in vehicles being manufactured at the inception of the DOE program and with an advanced, highly integrated propulsion system upon which technology development was recently initiated.

Electronic Design Automation (EDA) Roadmap Taskforce Report, Design of Microprocessors

DTIC Science & Technology

1999-04-01

through on time. Hence, the study is not a crystal-ball- gazing exercise, but a rigorous, schedulable plan of action to attain the goal. NTRS97...formats so as not to impose too heavy a maintenance burden on their users Object Interfaces eliminate these problems: • A tool that binds the interface ...and User Interface - Design Tool Communication - EDA System Extension Language - EDA Standards- Based Software Development Environment - Design and

A Methodology for Formal Hardware Verification, with Application to Microprocessors.

DTIC Science & Technology

1993-08-29

concurrent programming lan- guages. Proceedings of the NATO Advanced Study Institute on Logics and Models of Concurrent Systems ( Colle - sur - Loup , France, 8-19...restricted class of formu- las . Bose and Fisher [26] developed a symbolic model checker based on a Cosmos switch-level model. Their modeling approach...verification using SDVS-the method and a case study. 17th Anuual Microprogramming Workshop (New Orleans, LA , 30 October-2 November 1984). Published as

Army/NASA small turboshaft engine digital controls research program

NASA Technical Reports Server (NTRS)

Sellers, J. F.; Baez, A. N.

1981-01-01

The emphasis of a program to conduct digital controls research for small turboshaft engines is on engine test evaluation of advanced control logic using a flexible microprocessor based digital control system designed specifically for research on advanced control logic. Control software is stored in programmable memory. New control algorithms may be stored in a floppy disk and loaded directly into memory. This feature facilitates comparative evaluation of different advanced control modes. The central processor in the digital control is an Intel 8086 16 bit microprocessor. Control software is programmed in assembly language. Software checkout is accomplished prior to engine test by connecting the digital control to a real time hybrid computer simulation of the engine. The engine currently installed in the facility has a hydromechanical control modified to allow electrohydraulic fuel metering and VG actuation by the digital control. Simulation results are presented which show that the modern control reduces the transient rotor speed droop caused by unanticipated load changes such as cyclic pitch or wind gust transients.

The revolution in data gathering systems. [mini and microcomputers in NASA wind tunnels

NASA Technical Reports Server (NTRS)

Cambra, J. M.; Trover, W. F.

1975-01-01

This paper gives a review of the data-acquisition systems used in NASA's wind tunnels from the 1950's to the present as a basis for assessing the impact of minicomputers and microcomputers on data acquisition and processing. The operation and disadvantages of wind-tunnel data systems are summarized for the period before 1950, the early 1950's, the early and late 1960's, and the early 1970's. Some significant advances discussed include the use or development of solid-state components, minicomputer systems, large central computers, on-line data processing, autoranging DC amplifiers, MOS-FET multiplexers, MSI and LSI logic, computer-controlled programmable amplifiers, solid-state remote multiplexing, integrated circuits, and microprocessors. The distributed system currently in use with the 40-ft by 80-ft wind tunnel at Ames Research Center is described in detail. The expected employment of distributed systems and microprocessors in the next decade is noted.

Arranging computer architectures to create higher-performance controllers

NASA Technical Reports Server (NTRS)

Jacklin, Stephen A.

1988-01-01

Techniques for integrating microprocessors, array processors, and other intelligent devices in control systems are reviewed, with an emphasis on the (re)arrangement of components to form distributed or parallel processing systems. Consideration is given to the selection of the host microprocessor, increasing the power and/or memory capacity of the host, multitasking software for the host, array processors to reduce computation time, the allocation of real-time and non-real-time events to different computer subsystems, intelligent devices to share the computational burden for real-time events, and intelligent interfaces to increase communication speeds. The case of a helicopter vibration-suppression and stabilization controller is analyzed as an example, and significant improvements in computation and throughput rates are demonstrated.

Application of digital control to a magnetic model suspension and balance model

NASA Technical Reports Server (NTRS)

Luh, P. B.; Covert, E. E.; Whitaker, H. P.; Haldeman, C. W.

1978-01-01

The feasibility of using a digital computer for performing the automatic control functions for a magnetic suspension and balance system (MSBS) for use with wind tunnel models was investigated. Modeling was done using both a prototype MSBS and a one dimensional magnetic balance. A microcomputer using the Intel 8080 microprocessor is described and results are given using this microprocessor to control the one dimensional balance. Hybrid simulations for one degree of freedom of the MSBS were also performed and are reported. It is concluded that use of a digital computer to control the MSBS is eminently feasible and should extend both the accuracy and utility of the system.

Single event effect testing of the Intel 80386 family and the 80486 microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Moran, A.; LaBel, K.; Gates, M.

The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.

Microprocessors and the Curriculum.

ERIC Educational Resources Information Center

Pasahow, Edward J.

1981-01-01

Presents three approaches to teaching the use of a microprocessor: (1) a "generic" device on paper; (2) a "conglomeration" device, surveying a number of real products; and (3) the "how" course which covers a small number of actual but related microprocessors. (CT)

1989 IEEE Aerospace Applications Conference, Breckenridge, CO, Feb. 12-17, 1989, Conference Digest

NASA Astrophysics Data System (ADS)

Recent advances in electronic devices for aerospace applications are discussed in reviews and reports. Topics addressed include large-aperture mm-wave antennas, a cross-array radiometer for spacecraft applications, a technique for computing the propagation characteristics of optical fibers, an analog light-wave system for improving microwave-telemetry data communication, and a ground demonstration of an orbital-debris radar. Consideration is given to a verifiable autonomous satellite control system, Inmarsat second-generation satellites for mobile communication, automated tools for data-base design and criteria for their selection, and a desk-top simulation work station based on the DSP96002 microprocessor chip.

Programming for energy monitoring/display system in multicolor lidar system research

NASA Technical Reports Server (NTRS)

Alvarado, R. C., Jr.; Allen, R. J.

1982-01-01

The Z80 microprocessor based computer program that directs and controls the operation of the six channel energy monitoring/display system that is a part of the NASA Multipurpose Airborne Differential Absorption Lidar (DIAL) system is described. The program is written in the Z80 assembly language and is located on EPROM memories. All source and assembled listings of the main program, five subroutines, and two service routines along with flow charts and memory maps are included. A combinational block diagram shows the interfacing (including port addresses) between the six power sensors, displays, front panel controls, the main general purpose minicomputer, and this dedicated microcomputer system.

A Leak Monitor for Industry

NASA Technical Reports Server (NTRS)

1996-01-01

GenCorp Aerojet Industrial Products, Lewis Research Center, Marshall Space Flight Center, and Case Western Reserve University developed a gas leak detection system, originally for use with the Space Shuttle propulsion system and reusable launch vehicles. The Model HG200 Automated Gas Leak Detection System has miniaturized sensors that can identify extremely low concentrations of hydrogen without requiring oxygen. A microprocessor-based hardware/software system monitors the sensors and displays the source and magnitude of hydrogen leaks in real time. The system detects trace hydrogen around pipes, connectors, flanges and pressure tanks, and has been used by Ford Motor Company in the production of a natural gas-powered car.

IEEE 1451.2 based Smart sensor system using ADuc847

NASA Astrophysics Data System (ADS)

Sreejithlal, A.; Ajith, Jose

IEEE 1451 standard defines a standard interface for connecting transducers to microprocessor based data acquisition systems, instrumentation systems, control and field networks. Smart transducer interface module (STIM) acts as a unit which provides signal conditioning, digitization and data packet generation functions to the transducers connected to it. This paper describes the implementation of a microcontroller based smart transducer interface module based on IEEE 1451.2 standard. The module, implemented using ADuc847 microcontroller has 2 transducer channels and is programmed using Embedded C language. The Sensor system consists of a Network Controlled Application Processor (NCAP) module which controls the Smart transducer interface module (STIM) over an IEEE1451.2-RS232 bus. The NCAP module is implemented as a software module in C# language. The hardware details, control principles involved and the software implementation for the STIM are described in detail.

Software resilience and the effectiveness of software mitigation in microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Baker, Zachary; Fairbanks, Tom

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

Software resilience and the effectiveness of software mitigation in microcontrollers

DOE PAGES

Quinn, Heather; Baker, Zachary; Fairbanks, Tom; ...

2015-12-01

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

Proceedings of the 1981 Army Numerical Analysis and Computers Conference, held U. S. Army Missile Command, Redstone Arsenal, Alabama, 26-27 February 1981

DTIC Science & Technology

1981-08-01

loaded Loading done Time= 1295 msec. SQRT(3) %I + 1 SQRT(3) %I - 1 SQRT(3) %I f 1 (D13) TX = 1---------+-1** x = C-l---+-------, x = - 1, x...thnrl its competitors. As is to be expected, the table makes cJc ;lr the benefits of subincrement ing for nny approximation. For example, usiny the...Acquisition Systems ( DACS ) and a Data Analysis System (DAN), The DACs will be microprocessor-based recording devices with software-control

Automatic Control Of Length Of Welding Arc

NASA Technical Reports Server (NTRS)

Iceland, William F.

1991-01-01

Nonlinear relationships among current, voltage, and length stored in electronic memory. Conceptual microprocessor-based control subsystem maintains constant length of welding arc in gas/tungsten arc-welding system, even when welding current varied. Uses feedback of current and voltage from welding arc. Directs motor to set position of torch according to previously measured relationships among current, voltage, and length of arc. Signal paths marked "calibration" or "welding" used during those processes only. Other signal paths used during both processes. Control subsystem added to existing manual or automatic welding system equipped with automatic voltage control.

Paver automation for road surfacing

NASA Astrophysics Data System (ADS)

Tihonov, A.; Velichkin, V.

2017-10-01

The paper discusses factors that bear on the quality of motor road pavement as access roads and highways are built and used. A block diagram is proposed to organize elements of the automatic control system to control the asphalt paver’s mechanisms; the system is based on a microprocessor onboard controller to maintain preset elevation of the finishing plate; description of its operation principle is offered. The paper names primary converters to control the finishing plate elevation. A new control method is described to control the machine’s straight-line movement with GLONASS Satellite Positioning System (SPS) during operation.

Intelligent lightening system of urban and rural road traffic based on pyroelectric infrared detector

NASA Astrophysics Data System (ADS)

Miao, Man-Xiang

2007-12-01

By using the photo-voltage characteristics of pyroelectric infrared detector to fulfill signal acquisition, the detecting signal is processed with the core of a single chip microprocessor AT89C51. AT89C51 controls the CAN bus controller SJA1000/transceiver 82C250 to structure CAN bus communication system to transmit data through serial interface MAX232 connected with PC. The intelligent lightening system of urban and rural road traffic was carried out. In this paper, its construction and part's methods of hardware and software design were introduced in detail.

Vehicle Tracking System using Nanotechnology Satellites and Tags

NASA Technical Reports Server (NTRS)

Lorenzini, Dino A.; Tubis, Chris

1995-01-01

This paper describes a joint project to design, develop, and deploy a satellite based tracking system incorporating micro-nanotechnology components. The system consists of a constellation of 'nanosats', a satellite command station and data collection sites, and a large number of low-cost electronic 'tags'. Both government and commercial applications are envisioned for the satellite based tracking system. The projected low price for the tracking service is made possible by the lightweight nanosats and inexpensive electronic tags which use high production volume single chip transceivers and microprocessor devices. The nanosat consists of a five inch aluminum cube with body mounted solar panels (GaAs solar cells) on all six faces. A UHF turnstile antenna and a simple, spring release mechanism complete the external configuration of the spacecraft.

Computerized system for the follow-up of patients with heart valve replacements.

PubMed

Bain, W H; Fyfe, I C; Rodger, R A

1985-04-01

A system is described which will accept, store, retrieve and analyze information on large numbers of patients who undergo valve replacement surgery. The purpose of the database is to yield readily available facts concerning the patient's clinical course, prosthetic valve function, length of survival, and incidence of complications. The system uses the Apple Macintosh computer, which is one of the current examples of small, desk-top microprocessors. The software for the input, editing and analysis programs has been written by a professional software writer in close collaboration with a cardiac surgeon. Its content is based on 8 years' experience of computer-based valve follow-up. The system is inexpensive and has proved easy to use in practice.

A microcomputer-based position updating system for general aviation utilizing Loran-C

NASA Technical Reports Server (NTRS)

Fischer, J. P.

1982-01-01

Modern digital electronic technology is used to produce a device to convert LORAN C to useful pilot information using a simple software algebra and low cost microprocessor devices. Results indicate that the processor based LORAN C navigator has an accuracy of 1.0 nm or less over an area typically covered by a triad of Loran C stations and can execute a position update in less than 0.2 seconds. The system was tested in 30 hours of flight and proved that it can give reliable and accurate navigation information. Methods of converting time differences to position, design considerations for the microcomputer system, and the system for coordinate conversion are discussed. Testing with predetermined points and possible fixes for errors are also considered.

In situ measurements of thunderstorm electrical properties

NASA Technical Reports Server (NTRS)

Marshall, T. C.

1982-01-01

An airplane sensor to measure the charge, size and two dimensional shape of precipitation particles and large cloud particles was developed. The basic design of the instrument includes: the transducers and analog electronics, the analog to digital conversion electronics and a microprocessor based system to run the electronics and load the digital data onto magnetic tape. Prototype instrumentation for the proposed lightning mapper satellite was tested by flying it in a U-2 aircraft over severe storms in Oklahoma. Flight data are compared to data from ground based instruments.

Experimental Verification of Electric Drive Technologies Based on Artificial Intelligence Tools

NASA Technical Reports Server (NTRS)

Rubaai, Ahmed; Kankam, David (Technical Monitor)

2003-01-01

A laboratory implementation of a fuzzy logic-tracking controller using a low cost Motorola MC68HC11E9 microprocessor is described in this report. The objective is to design the most optimal yet practical controller that can be implemented and marketed, and which gives respectable performance, even when the system loads, inertia and parameters are varying. A distinguishing feature of this work is the by-product goal of developing a marketable, simple, functional and low cost controller. Additionally, real-time nonlinearities are not ignored, and a mathematical model is not required. A number of components have been designed, built and tested individually, and in various combinations of hardware and software segments. These components have been integrated with a brushless motor to constitute the drive system. A microprocessor-based FLC is incorporated to provide robust speed and position control. Design objectives that are difficult to express mathematically can be easily incorporated in a fuzzy logic-based controller by linguistic information (in the form of fuzzy IF-THEN rules). The theory and design are tested in the laboratory using a hardware setup. Several test cases have been conducted to confirm the effectiveness of the proposed controller. The results indicate excellent tracking performance for both speed and position trajectories. For the purpose of comparison, a bang-bang controller has been tested. The fuzzy logic controller performs significantly better than the traditional bang-bang controller. The bang-bang controller has been shown to be relatively inaccurate and lacking in robustness. Description of the implementation hardware system is also given.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Instruction-Level Characterization of Scientific Computing Applications Using Hardware Performance Counters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Luo, Y.; Cameron, K.W.

1998-11-24

Workload characterization has been proven an essential tool to architecture design and performance evaluation in both scientific and commercial computing areas. Traditional workload characterization techniques include FLOPS rate, cache miss ratios, CPI (cycles per instruction or IPC, instructions per cycle) etc. With the complexity of sophisticated modern superscalar microprocessors, these traditional characterization techniques are not powerful enough to pinpoint the performance bottleneck of an application on a specific microprocessor. They are also incapable of immediately demonstrating the potential performance benefit of any architectural or functional improvement in a new processor design. To solve these problems, many people rely on simulators,more » which have substantial constraints especially on large-scale scientific computing applications. This paper presents a new technique of characterizing applications at the instruction level using hardware performance counters. It has the advantage of collecting instruction-level characteristics in a few runs virtually without overhead or slowdown. A variety of instruction counts can be utilized to calculate some average abstract workload parameters corresponding to microprocessor pipelines or functional units. Based on the microprocessor architectural constraints and these calculated abstract parameters, the architectural performance bottleneck for a specific application can be estimated. In particular, the analysis results can provide some insight to the problem that only a small percentage of processor peak performance can be achieved even for many very cache-friendly codes. Meanwhile, the bottleneck estimation can provide suggestions about viable architectural/functional improvement for certain workloads. Eventually, these abstract parameters can lead to the creation of an analytical microprocessor pipeline model and memory hierarchy model.« less

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

NASA Astrophysics Data System (ADS)

Liebmann, Lars W.; Graur, Ioana C.; Leipold, William C.; Oberschmidt, James M.; O'Grady, David S.; Regaill, Denis

1999-07-01

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

Adaptive real-time methodology for optimizing energy-efficient computing

DOEpatents

Hsu, Chung-Hsing [Los Alamos, NM; Feng, Wu-Chun [Blacksburg, VA

2011-06-28

Dynamic voltage and frequency scaling (DVFS) is an effective way to reduce energy and power consumption in microprocessor units. Current implementations of DVFS suffer from inaccurate modeling of power requirements and usage, and from inaccurate characterization of the relationships between the applicable variables. A system and method is proposed that adjusts CPU frequency and voltage based on run-time calculations of the workload processing time, as well as a calculation of performance sensitivity with respect to CPU frequency. The system and method are processor independent, and can be applied to either an entire system as a unit, or individually to each process running on a system.

Microprocessor Seminar, phase 2

NASA Technical Reports Server (NTRS)

Scott, W. R.

1977-01-01

Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.

Operational experience on the MP-200 series commercial wind turbine generators

NASA Technical Reports Server (NTRS)

Rose, M. B.

1982-01-01

The MP-200 wind turbine generator is described. The mechanical system, microprocessor controller, and display devices, are described. Also discussed are modifications to the prototype, operational experience, and MP-600 systems development.

An airborne meteorological data collection system using satellite relay (ASDAR)

NASA Technical Reports Server (NTRS)

Bagwell, J. W.; Lindow, B. G.

1978-01-01

The National Aeronautics and Space Administration (NASA) has developed an airborne data acquisition and communication system for the National Oceanic and Atmospheric Administration (NOAA). This system known as ASDAR, the Aircraft to Satellite Data Relay, consists of a microprocessor based controller, time clock, transmitter and antenna. Together they acquire meteorological and position information from existing aircraft systems on B-747 aircraft, convert and format these, and transmit them to the ground via the GOES meteorological satellite series. The development and application of the ASDAR system is described with emphasis on unique features. Performance to date is exceptional, providing horizon-to-horizon coverage of aircraft flights. The data collected is of high quality and is considered a valuable addition to the data base from which NOAA generates its weather forecasts.

Development of 3 and 5kW Fuel Cell Power Plants

DTIC Science & Technology

1985-12-12

automotive type air -cooled (cross-flow) copper heat exchanger (Figure 7.7) was used for water reclamation. A 48V, 0.5A brushless DC blower was used to...and the balance is combusted in ’a burner to supply heat required for the endothermic reforming process. The phosphoric acid fuel cell stack is air ...the use of inter- changeable power conditioners . A microprocessor based con- troller provides event sequencing and system. control during startup

Operation of commercially-based microcomputer technology in a space radiation environment

NASA Astrophysics Data System (ADS)

Yelverton, J. N.

This paper focuses on detection and recovery techniques that should enable the reliable operation of commercially-based microprocessor technology in the harsh radiation environment of space and at high altitudes. This approach is especially significant in light of the current shift in emphasis (due to cost) from space hardened Class-S parts qualification to a more direct use of commercial parts. The method should offset some of the concern that the newer high density state-of-the-art RISC and CISC microprocessors can be used in future space applications. Also, commercial aviation, should benefit, since radiation induced transients are a new issue arising from the increased quantities of microcomputers used in aircraft avionics.

78 FR 3449 - Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-01-16

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-781] Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements on the Public Interest AGENCY: U.S... a limited exclusion order as to subject Intel microprocessors, but that implementation be delayed...

The Fermilab Accelerator control system

NASA Astrophysics Data System (ADS)

Bogert, Dixon

1986-06-01

With the advent of the Tevatron, considerable upgrades have been made to the controls of all the Fermilab Accelerators. The current system is based on making as large an amount of data as possible available to many operators or end-users. Specifically there are about 100 000 separate readings, settings, and status and control registers in the various machines, all of which can be accessed by seventeen consoles, some in the Main Control Room and others distributed throughout the complex. A "Host" computer network of approximately eighteen PDP-11/34's, seven PDP-11/44's, and three VAX-11/785's supports a distributed data acquisition system including Lockheed MAC-16's left from the original Main Ring and Booster instrumentation and upwards of 1000 Z80, Z8002, and M68000 microprocessors in dozens of configurations. Interaction of the various parts of the system is via a central data base stored on the disk of one of the VAXes. The primary computer-hardware communication is via CAMAC for the new Tevatron and Antiproton Source; certain subsystems, among them vacuum, refrigeration, and quench protection, reside in the distributed microprocessors and communicate via GAS, an in-house protocol. An important hardware feature is an accurate clock system making a large number of encoded "events" in the accelerator supercycle available for both hardware modules and computers. System software features include the ability to save the current state of the machine or any subsystem and later restore it or compare it with the state at another time, a general logging facility to keep track of specific variables over long periods of time, detection of "exception conditions" and the posting of alarms, and a central filesharing capability in which files on VAX disks are available for access by any of the "Host" processors.

Control Structures for VSC-based FACTS Devices under Normal and Faulted AC-systems

NASA Astrophysics Data System (ADS)

Babaei, Saman

This thesis is concerned with improving the Flexible AC Transmission Systems (FACTS) devices performance under the normal and fault AC-system conditions by proposing new control structures and also converter topologies. The combination of the increasing electricity demand and restrictions in expanding the power system infrastructures has urged the utility owners to deploy the utility-scaled power electronics in the power system. Basically, FACTS is referred to the application of the power electronics in the power systems. Voltage Source Converter (VSC) is the preferred building block of the FACTS devices and many other utility-scale power electronics applications. Despite of advances in the semiconductor technology and ultra-fast microprocessor based controllers, there are still many issues to address and room to improve[25]. An attempt is made in this thesis to address these important issues of the VSC-based FACTS devices and provide solutions to improve them.

Development of online NIR urine analyzing system based on AOTF

NASA Astrophysics Data System (ADS)

Wan, Feng; Sun, Zhendong; Li, Xiaoxia

2006-09-01

In this paper, some key techniques on development of on-line MR urine analyzing system based on AOTF (Acousto - Optics Tunable Filter) are introduced. Problems about designing the optical system including collimation of incident light and working distance (the shortest distance for separating incident light and diffracted light) are analyzed and researched. DDS (Direct Digital Synthesizer) controlled by microprocessor is used to realize the wavelength scan. The experiment results show that this MR urine analyzing system based on. AOTF has 10000 - 4000cm -1 wavelength range and O.3ms wavelength transfer rate. Compare with the conventional Fourier Transform NIP. spectrophotometer for analyzing multi-components in urine, this system features low cost, small volume and on-line measurement function. Unscrambler software (multivariate statistical software by CAMO Inc. Norway) is selected as the software for processing the data. This system can realize on line quantitative analysis of protein, urea and creatinine in urine.

A micro-computer-based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, Rajan

1987-01-01

A mathematical model of magnetic variation in the continental United States was implemented in the Ohio University Loran-C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based Loran-C receiver is possible with the help of a math chip which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter is used to communicate between the 6502 based microcomputer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

A programmable power processor for a 25-kW power module

NASA Technical Reports Server (NTRS)

Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

1979-01-01

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

Information Technologies for the 1980's: Lasers and Microprocessors.

ERIC Educational Resources Information Center

Mathews, William D.

This discussion of the development and application of lasers and microprocessors to information processing stresses laser communication in relation to capacity, reliability, and cost and the advantages of this technology to real-time information access and information storage. The increased capabilities of microprocessors are reviewed, and a…

Integrally regulated solar array demonstration using an Intel 8080 microprocessor

NASA Technical Reports Server (NTRS)

Petrik, E. J.

1977-01-01

A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

PubMed

Shenoy, Archana; Blelloch, Robert

2009-09-11

The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript. To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES) cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8. We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

Performance, operational limits, of an Electronic Switching Spherical Array (ESSA) antenna

NASA Technical Reports Server (NTRS)

Stockton, R.

1979-01-01

The development of a microprocessor controller which provides multimode operational capability for the Electronic Switching Spherical Array (ESSA) Antenna is described. The best set of operating conditions were determined and the performance of an ESSA antenna was demonstrated in the following modes: (1) omni; (2) acquisition/track; (3) directive; and (4) multibeam. The control algorithms, software flow diagrams, and electronic circuitry were developed. The microprocessor and control electronics were built and interfaced with the antenna to carry out performance testing. The acquisition/track mode for users in the Tracking and Data Relay Satellite System is emphasized.

Microprocessor-controlled laser tracker for atmospheric sensing

NASA Technical Reports Server (NTRS)

Johnson, R. A.; Webster, C. R.; Menzies, R. T.

1985-01-01

An optical tracking system comprising a visible HeNe laser, an imaging detector, and a microprocessor-controlled mirror, has been designed to track a moving retroreflector located up to 500 m away from an atmospheric instrument and simultaneously direct spectrally tunable infrared laser radiation to the retroreflector for double-ended, long-path absorption measurements of atmospheric species. The tracker has been tested during the recent flight of a balloon-borne tunable diode laser absorption spectrometer which monitors the concentrations of stratospheric species within a volume defined by a 0.14-m-diameter retroreflector lowered 500 m below the instrument gondola.

A Performance Evaluation of the Cray X1 for Scientific Applications

NASA Technical Reports Server (NTRS)

Oliker, Leonid; Biswas, Rupak; Borrill, Julian; Canning, Andrew; Carter, Jonathan; Djomehri, M. Jahed; Shan, Hongzhang; Skinner, David

2004-01-01

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end capability and cost effectiveness. However, the recent development of massively parallel vector systems is having a significant effect on the supercomputing landscape. In this paper, we compare the performance of the recently released Cray X1 vector system with that of the cacheless NEC SX-6 vector machine, and the superscalar cache-based IBM Power3 and Power4 architectures for scientific applications. Overall results demonstrate that the X1 is quite promising, but performance improvements are expected as the hardware, systems software, and numerical libraries mature. Code reengineering to effectively utilize the complex architecture may also lead to significant efficiency enhancements.

Optical attenuation mechanism upgrades, MOBLAS, and TLRS systems

NASA Technical Reports Server (NTRS)

Eichinger, Richard; Johnson, Toni; Malitson, Paul; Oldham, Thomas; Stewart, Loyal

1993-01-01

This poster presentation describes the Optical Attenuation Mechanism (OAM) Upgrades to the MOBLAS and TLRS Crustal Dynamics Satellite Laser Ranging (CDSLR) systems. The upgrades were for the purposes of preparing these systems to laser range to the TOPEX/POSEIDON spacecraft when it will be launched in the summer of 1992. The OAM permits the laser receiver to operate over the expected large signal dynamic range from TOPEX/POSEIDON and it reduces the number of pre- and post-calibrations for each satellite during multi-satellite tracking operations. It further simplifies the calibration bias corrections that had been made due to the pass-to-pass variation of the photomultiplier supply voltage and the transmit filter glass thickness. The upgrade incorporated improvements to the optical alignment capability of each CDSLR system through the addition of a CCD camera into the MOBLAS receive telescope and an alignment telescope onto the TLRS optical table. The OAM is stepper motor and microprocessor based; and the system can be controlled either manually by a control switch panel or computer controlled via an EIA RS-232C serial interface. The OAM has a neutral density (ND) range of 0.0 to 4.0 and the positioning is absolute referenced in steps of 0.1 ND. Both the fixed transmit filter and the daylight filter are solenoid actuated with digital inputs and outputs to and from the OAM microprocessor. During automated operation, the operator has the option to overide the remote control and control the OAM system via a local control switch panel.

Design Method of Digital Optimal Control Scheme and Multiple Paralleled Bridge Type Current Amplifier for Generating Gradient Magnetic Fields in MRI Systems

NASA Astrophysics Data System (ADS)

Watanabe, Shuji; Takano, Hiroshi; Fukuda, Hiroya; Hiraki, Eiji; Nakaoka, Mutsuo

This paper deals with a digital control scheme of multiple paralleled high frequency switching current amplifier with four-quadrant chopper for generating gradient magnetic fields in MRI (Magnetic Resonance Imaging) systems. In order to track high precise current pattern in Gradient Coils (GC), the proposal current amplifier cancels the switching current ripples in GC with each other and designed optimum switching gate pulse patterns without influences of the large filter current ripple amplitude. The optimal control implementation and the linear control theory in GC current amplifiers have affinity to each other with excellent characteristics. The digital control system can be realized easily through the digital control implementation, DSPs or microprocessors. Multiple-parallel operational microprocessors realize two or higher paralleled GC current pattern tracking amplifier with optimal control design and excellent results are given for improving the image quality of MRI systems.

Investigation of new techniques for aircraft navigation using the omega navigation

NASA Technical Reports Server (NTRS)

Baxa, E. G., Jr.

1978-01-01

An OMEGA navigation receiver with a microprocessor as the computational component was investigated. A version of the INTEL 4004 microprocessor macroassembler suitable for use on the CDC-6600 system and development of a FORTRAN IV simulator program for the microprocessor was developed. Supporting studies included development and evaluation of navigation algorithms to generate relative position information from OMEGA VLF phase measurements. Simulation studies were used to evaluate assumptions made in developing a navigation equation in OMEGA Line of Position (LOP) coordinates. Included in the navigation algorithms was a procedure for calculating a position in latitude/longitude given an OMEGA LOP fix. Implementation of a digital phase locked loop (DPLL) was evaluated on the basic of phase response characteristics over a range of input phase variations. Included also is an analytical evaluation on the basis of error probability of an algorithm for automatic time synchronization of the receiver to the OMEGA broadcast format. The use of actual OMEGA phase data and published propagation prediction corrections to determine phase velocity estimates was discussed.

Generalized fast feedback system in the SLC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hendrickson, L.; Allison, S.; Gromme, T.

A generalized fast feedback system has been developed to stabilize beams at various locations in the SLC. The system is designed to perform measurements and change actuator settings to control beam states such as position, angle and energy on a pulse to pulse basis. The software design is based on the state space formalism of digital control theory. The system is database-driven, facilitating the addition of new loops without requiring additional software. A communications system, KISNet, provides fast communications links between microprocessors for feedback loops which involve multiple micros. Feedback loops have been installed in seventeen locations throughout the SLCmore » and have proven to be invaluable in stabilizing the machine.« less

Device for rapid quantification of human carotid baroreceptor-cardiac reflex responses

NASA Technical Reports Server (NTRS)

Sprenkle, J. M.; Eckberg, D. L.; Goble, R. L.; Schelhorn, J. J.; Halliday, H. C.

1986-01-01

A new device has been designed, constructed, and evaluated to characterize the human carotid baroreceptor-cardiac reflex response relation rapidly. This system was designed for study of reflex responses of astronauts before, during, and after space travel. The system comprises a new tightly sealing silicon rubber neck chamber, a stepping motor-driven electrodeposited nickel bellows pressure system, capable of delivering sequential R-wave-triggered neck chamber pressure changes between +40 and -65 mmHg, and a microprocessor-based electronics system for control of pressure steps and analysis and display of responses. This new system provokes classic sigmoid baroreceptor-cardiac reflex responses with threshold, linear, and saturation ranges in most human volunteers during one held expiration.

Commercial Parts Radiation Testing

DTIC Science & Technology

2015-01-13

New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen

Microprocessors: An Understandable Guide for the Classroom Teacher.

ERIC Educational Resources Information Center

Okinaka, Russell T.

A microprocessor constitutes the heart and soul of a personal computer. Indeed, the quality of a personal computer is determined largely by the type of microprocessor that is included within its circuitry. Since the microcomputer revolution began in the late 1970s, these special chips have gone through a series of improvements and modifications.…

Cellular functions of the microprocessor.

PubMed

Macias, Sara; Cordiner, Ross A; Cáceres, Javier F

2013-08-01

The microprocessor is a complex comprising the RNase III enzyme Drosha and the double-stranded RNA-binding protein DGCR8 (DiGeorge syndrome critical region 8 gene) that catalyses the nuclear step of miRNA (microRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as an endonuclease. Recent global analyses of microprocessor and Dicer proteins have suggested novel functions for these components independent of their role in miRNA biogenesis. A HITS-CLIP (high-throughput sequencing of RNA isolated by cross-linking immunoprecipitation) experiment designed to identify novel substrates of the microprocessor revealed that this complex binds and regulates a large variety of cellular RNAs. The microprocessor-mediated cleavage of several classes of RNAs not only regulates transcript levels, but also modulates alternative splicing events, independently of miRNA function. Importantly, DGCR8 can also associate with other nucleases, suggesting the existence of alternative DGCR8 complexes that may regulate the fate of a subset of cellular RNAs. The aim of the present review is to provide an overview of the diverse functional roles of the microprocessor.

Field programmable chemistry: integrated chemical and electronic processing of informational molecules towards electronic chemical cells.

PubMed

Wagler, Patrick F; Tangen, Uwe; Maeke, Thomas; McCaskill, John S

2012-07-01

The topic addressed is that of combining self-constructing chemical systems with electronic computation to form unconventional embedded computation systems performing complex nano-scale chemical tasks autonomously. The hybrid route to complex programmable chemistry, and ultimately to artificial cells based on novel chemistry, requires a solution of the two-way massively parallel coupling problem between digital electronics and chemical systems. We present a chemical microprocessor technology and show how it can provide a generic programmable platform for complex molecular processing tasks in Field Programmable Chemistry, including steps towards the grand challenge of constructing the first electronic chemical cells. Field programmable chemistry employs a massively parallel field of electrodes, under the control of latched voltages, which are used to modulate chemical activity. We implement such a field programmable chemistry which links to chemistry in rather generic, two-phase microfluidic channel networks that are separated into weakly coupled domains. Electric fields, produced by the high-density array of electrodes embedded in the channel floors, are used to control the transport of chemicals across the hydrodynamic barriers separating domains. In the absence of electric fields, separate microfluidic domains are essentially independent with only slow diffusional interchange of chemicals. Electronic chemical cells, based on chemical microprocessors, exploit a spatially resolved sandwich structure in which the electronic and chemical systems are locally coupled through homogeneous fine-grained actuation and sensor networks and play symmetric and complementary roles. We describe how these systems are fabricated, experimentally test their basic functionality, simulate their potential (e.g. for feed forward digital electrophoretic (FFDE) separation) and outline the application to building electronic chemical cells. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

Implementation of Segment Management for a Secure Archival Storage System.

DTIC Science & Technology

1980-09-01

microprocessor operating systems from which the subset, SASS, was later derived (6]. In their work, two of the primary motivations were to provide a system...facility provided by segmentation. The ju~stification Is based on a design decision motivated by another goal of SASS -- reduction of bus contention among...1- I ’ E-4 P4 2-4 E-:t 1 P- W E-E-4&r,3- ’-4 :/I 64 t Ln i.. E-.’f2) V) : / x W~ E.4 E- $=I~ P4 X * U C - ~-4 :Pz=r- -C4 PS4 &2- I-.4 14~ PC: co E E

Transcription of the Workshop on General Aviation Advanced Avionics Systems

NASA Technical Reports Server (NTRS)

Tashker, M. (Editor)

1975-01-01

Papers are presented dealing with the design of reliable, low cost, advanced avionics systems applicable to general aviation in the 1980's and beyond. Sensors, displays, integrated circuits, microprocessors, and minicomputers are among the topics discussed.

The Blind, From Braille to the Present.

ERIC Educational Resources Information Center

Truquet, Monique

1980-01-01

Traces the historical development of processing information for the blind from the system devised by Barbier to present systems of producing Braille documents using computers. Cites the impact of microprocessors and outlines possibilities for Braille reproductions in the future. (GS)

Description of data base management systems activities

NASA Technical Reports Server (NTRS)

1983-01-01

One of the major responsibilities of the JPL Computing and Information Services Office is to develop and maintain a JPL plan for providing computing services to the JPL management and administrative community that will lead to improved productivity. The CISO plan to accomplish this objective has been titled 'Management and Administrative Support Systems' (MASS). The MASS plan is based on the continued use of JPL's IBM 3032 Computer system for administrative computing and for the MASS functions. The current candidate administrative Data Base Management Systems required to support the MASS include ADABASE, Cullinane IDMS and TOTAL. Previous uses of administrative Data Base Systems have been applied to specific local functions rather than in a centralized manner with elements common to the many user groups. Limited capacity data base systems have been installed in microprocessor based office automation systems in a few Project and Management Offices using Ashton-Tate dBASE II. These experiences plus some other localized in house DBMS uses have provided an excellent background for developing user and system requirements for a single DBMS to support the MASS program.

Microcomputer Enhancement of the Articulated Total Body (ATB) Biodynamic Modeling System

DTIC Science & Technology

1990-01-01

products. In view of the broad market base, continued hardware and software support can be reasonably expected. The Intel family of microprocessors...time library. Their use became sufficiently widespread that "after- market " support libraries have been written for several devices, such as the...11,11,82,12,12,11,11,12) , NPRT4 HEDING 11 LOLD - FALSE. HED ING LNEW - .TRUE. HEDING GO TO 13 HEDING 12 LOLD - .TRUE. HEDING LNEW -FALSE. FIEDING 13 MT -20 HEDING NLINES

DESIGN, DEVELOPMENT, AND FIELD DEMONSTRATION OF A REMOTELY DEPLOYABLE WATER QUALITY MONITORING SYSTEM

EPA Science Inventory

A prototype water quality monitoring system is described which offers almost continuous in situ monitoring. The two-man portable system features: (1) a microprocessor controlled central processing unit which allows preprogrammed sampling schedules and reprogramming in situ; (2) a...

State recovery and lockstep execution restart in a system with multiprocessor pairing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gara, Alan; Gschwind, Michael K; Salapura, Valentina

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switchmore » or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.« less

Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.

Evolution of a standard microprocessor-based space computer

NASA Technical Reports Server (NTRS)

Fernandez, M.

1980-01-01

An existing in inventory computer hardware/software package (B-1 RFS/ECM) was repackaged and applied to multiple missile/space programs. Concurrent with the application efforts, low risk modifications were made to the computer from program to program to take advantage of newer, advanced technology and to meet increasingly more demanding requirements (computational and memory capabilities, longer life, and fault tolerant autonomy). It is concluded that microprocessors hold promise in a number of critical areas for future space computer applications. However, the benefits of the DoD VHSIC Program are required and the old proliferation problem must be revised.

[Multimag-M magnetotherapy system of the new generation].

PubMed

Borisov, A G; Grigor'ev, E M; Gurzhin, S G; Zhulev, V I; Kriakov, V G; Proshin, E M

2007-01-01

The Multimag-M microprocessor chronomagne-totherapy system of the new generation is described. The system provides on-line diagnosis of the pulse parameters and the breathing rate during a biotechnical feedback session. The requirements to the system software, as well as its specific features and design principles, are considered.

Rapidly quantifying the relative distention of a human bladder

NASA Technical Reports Server (NTRS)

Companion, John A. (Inventor); Heyman, Joseph S. (Inventor); Mineo, Beth A. (Inventor); Cavalier, Albert R. (Inventor); Blalock, Travis N. (Inventor)

1989-01-01

A device and method of rapidly quantifying the relative distention of the bladder in a human subject are disclosed. The ultrasonic transducer which is positioned on the subject in proximity to the bladder is excited by a pulser under the command of a microprocessor to launch an acoustic wave into the patient. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer, when it is received, amplified and processed by the receiver. The resulting signal is digitized by an analog-to-digital converter under the command of the microprocessor and is stored in the data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy; and based on programmed scientific measurements and individual, anatomical, and behavioral characterists of the specific subject as contained in the program memory, sends out a signal to turn on any or all of the audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

High Accuracy Investigation of Microwave Absorption in Polymer Electrical Components on Motherboard of Computers

NASA Astrophysics Data System (ADS)

Dašić, P.; Hutanu, C.; Jevremović, V.; Dobra, R.; Risteiu, M.; Ileana, I.

2017-06-01

Electronic operating at high frequencies can have problems with emission of high frequency noise. Once put inside an enclosure, the energy will add in phase at certain frequencies to cause resonances which will hinder the performance of the device. These absorbers are based upon open celled foam impregnated with a carbon coating. It is quite possible that in the near future, microprocessors would be to work on a frequency located in 5 to 10 GHz. In these circumstances it is useful to know how and how much of the electromagnetic field emitted by a microprocessor, it is absorbed by the circuit elements in the immediate vicinity of the microprocessor. The aim of this contribution is to demonstrate throughout high-level experimental analysis how the main electric parameters of polymer materials, which build the printed circuits and the one of electric capacitors and resistors, depend on the frequencies on which they work from the microwave range.

Digital interface of electronic transformers based on embedded system

NASA Astrophysics Data System (ADS)

Shang, Qiufeng; Qi, Yincheng

2008-10-01

Benefited from digital interface of electronic transformers, information sharing and system integration in substation can be realized. An embedded system-based digital output scheme of electronic transformers is proposed. The digital interface is designed with S3C44B0X 32bit RISC microprocessor as the hardware platform. The μCLinux operation system (OS) is transplanted on ARM7 (S3C44B0X). Applying Ethernet technology as the communication mode in the substation automation system is a new trend. The network interface chip RTL8019AS is adopted. Data transmission is realized through the in-line TCP/IP protocol of uClinux embedded OS. The application result and character analysis show that the design can meet the real-time and reliability requirements of IEC60044-7/8 electronic voltage/current instrument transformer standards.

Computer based guidance in the modern operating room: a historical perspective.

PubMed

Bova, Frank

2010-01-01

The past few decades have seen the introduction of many different and innovative approaches aimed at enhancing surgical technique. As microprocessors have decreased in size and increased in processing power, more sophisticated systems have been developed. Some systems have attempted to provide enhanced instrument control while others have attempted to provide tools for surgical guidance. These systems include robotics, image enhancements, and frame-based and frameless guidance procedures. In almost every case the system's design goals were achieved and surgical outcomes were enhanced, yet a vast majority of today's surgical procedures are conducted without the aid of these advances. As new tools are developed and existing tools refined, special attention to the systems interface and integration into the operating room environment will be required before increased utilization of these technologies can be realized.

Adaptive real-time methodology for optimizing energy-efficient computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hsu, Chung-Hsing; Feng, Wu-Chun

Dynamic voltage and frequency scaling (DVFS) is an effective way to reduce energy and power consumption in microprocessor units. Current implementations of DVFS suffer from inaccurate modeling of power requirements and usage, and from inaccurate characterization of the relationships between the applicable variables. A system and method is proposed that adjusts CPU frequency and voltage based on run-time calculations of the workload processing time, as well as a calculation of performance sensitivity with respect to CPU frequency. The system and method are processor independent, and can be applied to either an entire system as a unit, or individually to eachmore » process running on a system.« less

Grain quality inspection system

NASA Technical Reports Server (NTRS)

Flood, C. A., Jr.; Singletow, D. P.; James, S. N.

1979-01-01

A review of grain quality indicators and measurement methods was conducted in order to assess the feasibility of using remote sensing technology to develop a continuous monitoring system for use during grain transfer operations. Most detection methods were found to be too slow or too expensive to be incorporated into the normal inspection procedure of a grain elevator on a continuous basis. Two indicators, moisture content and broken corn and foreign material, show potential for automation and are of an economic value. A microprocessor based system which utilizes commercially available electronic moisture meter was developed and tested. A method for automating BCFM measurement is described. A complete system description is presented along with performance test results.

Formal Verification of the AAMP-FV Microcode

NASA Technical Reports Server (NTRS)

Miller, Steven P.; Greve, David A.; Wilding, Matthew M.; Srivas, Mandayam

1999-01-01

This report describes the experiences of Collins Avionics & Communications and SRI International in formally specifying and verifying the microcode in a Rockwell proprietary microprocessor, the AAMP-FV, using the PVS verification system. This project built extensively on earlier experiences using PVS to verify the microcode in the AAMP5, a complex, pipelined microprocessor designed for use in avionics displays and global positioning systems. While the AAMP5 experiment demonstrated the technical feasibility of formal verification of microcode, the steep learning curve encountered left unanswered the question of whether it could be performed at reasonable cost. The AAMP-FV project was conducted to determine whether the experience gained on the AAMP5 project could be used to make formal verification of microcode cost effective for safety-critical and high volume devices.

Design studies for a technology assessment receiver for global positioning system

NASA Technical Reports Server (NTRS)

Painter, J. H.

1981-01-01

The operational conditions of a radio receiver - microprocessor for the global positioning system are studied. Navigation fundamentals and orbit characterization are reviewed. The global positioning system is described with emphasis upon signal structure and satellite positioning. Ranging and receiver processing techniques are discussed.

Development and Application of a Wireless Sensor for Space Charge Density Measurement in an Ultra-High-Voltage, Direct-Current Environment

PubMed Central

Xin, Encheng; Ju, Yong; Yuan, Haiwen

2016-01-01

A space charge density wireless measurement system based on the idea of distributed measurement is proposed for collecting and monitoring the space charge density in an ultra-high-voltage direct-current (UHVDC) environment. The proposed system architecture is composed of a number of wireless nodes connected with space charge density sensors and a base station. The space charge density sensor based on atmospheric ion counter method is elaborated and developed, and the ARM microprocessor and Zigbee radio frequency module are applied. The wireless network communication quality and the relationship between energy consumption and transmission distance in the complicated electromagnetic environment is tested. Based on the experimental results, the proposed measurement system demonstrates that it can adapt to the complex electromagnetic environment under the UHVDC transmission lines and can accurately measure the space charge density. PMID:27775627

Development and Application of a Wireless Sensor for Space Charge Density Measurement in an Ultra-High-Voltage, Direct-Current Environment.

PubMed

Xin, Encheng; Ju, Yong; Yuan, Haiwen

2016-10-20

A space charge density wireless measurement system based on the idea of distributed measurement is proposed for collecting and monitoring the space charge density in an ultra-high-voltage direct-current (UHVDC) environment. The proposed system architecture is composed of a number of wireless nodes connected with space charge density sensors and a base station. The space charge density sensor based on atmospheric ion counter method is elaborated and developed, and the ARM microprocessor and Zigbee radio frequency module are applied. The wireless network communication quality and the relationship between energy consumption and transmission distance in the complicated electromagnetic environment is tested. Based on the experimental results, the proposed measurement system demonstrates that it can adapt to the complex electromagnetic environment under the UHVDC transmission lines and can accurately measure the space charge density.

Interactive display of molecular models using a microcomputer system

NASA Technical Reports Server (NTRS)

Egan, J. T.; Macelroy, R. D.

1980-01-01

A simple, microcomputer-based, interactive graphics display system has been developed for the presentation of perspective views of wire frame molecular models. The display system is based on a TERAK 8510a graphics computer system with a display unit consisting of microprocessor, television display and keyboard subsystems. The operating system includes a screen editor, file manager, PASCAL and BASIC compilers and command options for linking and executing programs. The graphics program, written in USCD PASCAL, involves the centering of the coordinate system, the transformation of centered model coordinates into homogeneous coordinates, the construction of a viewing transformation matrix to operate on the coordinates, clipping invisible points, perspective transformation and scaling to screen coordinates; commands available include ZOOM, ROTATE, RESET, and CHANGEVIEW. Data file structure was chosen to minimize the amount of disk storage space. Despite the inherent slowness of the system, its low cost and flexibility suggests general applicability.

A low cost surface plasmon resonance biosensor using a laser line generator

NASA Astrophysics Data System (ADS)

Chen, Ruipeng; Wang, Manping; Wang, Shun; Liang, Hao; Hu, Xinran; Sun, Xiaohui; Zhu, Juanhua; Ma, Liuzheng; Jiang, Min; Hu, Jiandong; Li, Jianwei

2015-08-01

Due to the instrument designed by using a common surface plasmon resonance biosensor is extremely expensive, we established a portable and cost-effective surface plasmon resonance biosensing system. It is mainly composed of laser line generator, P-polarizer, customized prism, microfluidic cell, and line Charge Coupled Device (CCD) array. Microprocessor PIC24FJ128GA006 with embedded A/D converter, communication interface circuit and photoelectric signal amplifier circuit are used to obtain the weak signals from the biosensing system. Moreover, the line CCD module is checked and optimized on the number of pixels, pixels dimension, output amplifier and the timing diagram. The micro-flow cell is made of stainless steel with a high thermal conductivity, and the microprocessor based Proportional-Integral-Derivative (PID) temperature-controlled algorithm was designed to keep the constant temperature (25 °C) of the sample solutions. Correspondingly, the data algorithms designed especially to this biosensing system including amplitude-limiting filtering algorithm, data normalization and curve plotting were programmed efficiently. To validate the performance of the biosensor, ethanol solution samples at the concentrations of 5%, 7.5%, 10%, 12.5% and 15% in volumetric fractions were used, respectively. The fitting equation ΔRU = - 752987.265 + 570237.348 × RI with the R-Square of 0.97344 was established by delta response units (ΔRUs) to refractive indexes (RI). The maximum relative standard deviation (RSD) of 4.8% was obtained.

Description of a dual fail operational redundant strapdown inertial measurement unit for integrated avionics systems research

NASA Technical Reports Server (NTRS)

Bryant, W. H.; Morrell, F. R.

1981-01-01

An experimental redundant strapdown inertial measurement unit (RSDIMU) is developed as a link to satisfy safety and reliability considerations in the integrated avionics concept. The unit includes four two degree-of-freedom tuned rotor gyros, and four accelerometers in a skewed and separable semioctahedral array. These sensors are coupled to four microprocessors which compensate sensor errors. These microprocessors are interfaced with two flight computers which process failure detection, isolation, redundancy management, and general flight control/navigation algorithms. Since the RSDIMU is a developmental unit, it is imperative that the flight computers provide special visibility and facility in algorithm modification.

A rocket-borne data-manipulation experiment using a microprocessor

NASA Technical Reports Server (NTRS)

Davis, L. L.; Smith, L. G.; Voss, H. D.

1979-01-01

The development of a data-manipulation experiment using a Z-80 microprocessor is described. The instrumentation is included in the payloads of two Nike Apache sounding rockets used in an investigation of energetic particle fluxes. The data from an array of solid-state detectors and an electrostatic analyzer is processed to give the energy spectrum as a function of pitch angle. The experiment performed well in its first flight test: Nike Apache 14.543 was launched from Wallops Island at 2315 EST on 19 June 1978. The system was designed to be easily adaptable to other data-manipulation requirements and some suggestions for further development are included.

COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

ERIC Educational Resources Information Center

Marcovitz, Alan B., Ed.

This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…

COED Transactions, Vol. XI, No. 12, December 1979. Some Alternate Applications of Microprocessor Trainers in Support of Undergraduate Laboratories.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.

Ways are described for the use of a microprocessor trainer in undergraduate laboratories. Listed are microcomputer applications that have been used as demonstrations and which provide signals for other experiments which are not related to microprocessors. Information and figures are provided for methods to do the following: direct generation of…

A micro-computer based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, R.

1984-01-01

A mathematical model of magnetic variation in the continental United States (COT48) was implemented in the Ohio University LORAN C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based LORAN C receiver is possible with the help of a math chip, Am9511 which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter (M6520) is used to communicate between the 6502 based micro-computer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

Post-processing of seismic parameter data based on valid seismic event determination

DOEpatents

McEvilly, Thomas V.

1985-01-01

An automated seismic processing system and method are disclosed, including an array of CMOS microprocessors for unattended battery-powered processing of a multi-station network. According to a characterizing feature of the invention, each channel of the network is independently operable to automatically detect, measure times and amplitudes, and compute and fit Fast Fourier transforms (FFT's) for both P- and S- waves on analog seismic data after it has been sampled at a given rate. The measured parameter data from each channel are then reviewed for event validity by a central controlling microprocessor and if determined by preset criteria to constitute a valid event, the parameter data are passed to an analysis computer for calculation of hypocenter location, running b-values, source parameters, event count, P- wave polarities, moment-tensor inversion, and Vp/Vs ratios. The in-field real-time analysis of data maximizes the efficiency of microearthquake surveys allowing flexibility in experimental procedures, with a minimum of traditional labor-intensive postprocessing. A unique consequence of the system is that none of the original data (i.e., the sensor analog output signals) are necessarily saved after computation, but rather, the numerical parameters generated by the automatic analysis are the sole output of the automated seismic processor.

A Performance Evaluation of the Cray X1 for Scientific Applications

NASA Technical Reports Server (NTRS)

Oliker, Leonid; Biswas, Rupak; Borrill, Julian; Canning, Andrew; Carter, Jonathan; Djomehri, M. Jahed; Shan, Hongzhang; Skinner, David

2003-01-01

The last decade has witnessed a rapid proliferation of superscalar cache-based microprocessors to build high-end capability and capacity computers because of their generality, scalability, and cost effectiveness. However, the recent development of massively parallel vector systems is having a significant effect on the supercomputing landscape. In this paper, we compare the performance of the recently-released Cray X1 vector system with that of the cacheless NEC SX-6 vector machine, and the superscalar cache-based IBM Power3 and Power4 architectures for scientific applications. Overall results demonstrate that the X1 is quite promising, but performance improvements are expected as the hardware, systems software, and numerical libraries mature. Code reengineering to effectively utilize the complex architecture may also lead to significant efficiency enhancements.

CP/M: A Family of 8- and 16-Bit Computer Operating Systems.

ERIC Educational Resources Information Center

Kildall, Gary

1982-01-01

Traces the development of the computer CP/M (Control Program for Microcomputers) and MP/M (Multiprogramming Monitor Microcomputers) operating system by Gary Kildall of Digital Research Company. Discusses the adaptation of these operating systems to the newly emerging 16 and 32 bit microprocessors. (Author/LC)

Development of a real-time chemical injection system for air-assisted variable-rate sprayers

USDA-ARS?s Scientific Manuscript database

A chemical injection system is an effective method to minimize chemical waste and reduce the environmental pollution in pesticide spray applications. A microprocessor controlled injection system implementing a ceramic piston metering pump was developed to accurately dispense chemicals to be mixed wi...

Acurex Parabolic Dish Concentrator (PDC-2)

NASA Technical Reports Server (NTRS)

Overly, P.; Bedard, R.

1982-01-01

The design approach, rationale for the selected configuration, and the development status of a cost effective point-focus solar concentrator are discussed. The low-cost concentrator reflective surface design is based on the use of a thin, backsilvered mirror glass reflector bonded to a molded structural plastic substrate. The foundation, support, and drive subassembles are described. A hybrid, two-axis, Sun tracking control system based on microprocessor technology was selected. Coarse synthetic tracking is achieved through a microcomputer-based control system to calculate Sun position for transient periods of cloud cover as well as sundown and sunrise positioning. Accurate active tracking is achieved by two-axis optical sensors. Results of the reflective panel demonstration tests investigating slope error, hail impact survivability, temperature/humidity cycling, longitudinal strength/bending stiffness, and torsional stiffness are discussed.

Fiber Optic Strain Measurements In Filament-Wound Graphite-Epoxy Tubes Containing Embedded Fibers

NASA Astrophysics Data System (ADS)

Rogowski, R. S.; Heyman, J. S.; Holben, M. S.; Egalon, C.; Dehart, D. W.; Doederlein, T.; Koury, J.

1989-01-01

Several planned United States Air Force (USAF) and National Aeronautics and Space Administration (NASA) space systems such as Space Based Radar (SBR), Space Based Laser (SBL), and Space Station, pose serious vibration and control issues. Their low system mass combined with their large size, precision pointing/shape control and rapid retargetting requirements, will result in an unprecedented degree of interaction between the system controller and the modes of vibration of the structure. The resulting structural vibrations and/or those caused by foreign objects impacting the space structure could seriously degrade system performance, making it virtually impossible for passive structural systems to perform their missions. Therefore an active vibration control system which will sense these natural and spurious vibrations, evaluate them and dampen them out is required. This active vibration control system must be impervious to the space environment and electromagnetic interference, have very low weight, and in essence become part of the structure itself. The concept of smart structures meets these criteria. Smart structures is defined as the embedment of sensors, actuators, and possibly microprocessors in the material which forms the structure, a concept that is particularly applicable to advanced composites. These sensors, actuators, and microprocessors will work interactively to sense, evaluate, and dampen those vibrations which pose a threat to large flexible space systems (LSS). The sensors will also be capable of sensing any degradation to the structure. The Air Force Astronautics Laboratory (AFAL) has been working in the area of dynamics and control of LSS for the past five years. Several programs involving both contractual and in-house efforts to develop sensors and actuators for controlling LSS have been initiated. Presently the AFAL is developing a large scale laboratory which will have the capacity of performing large angle retargetting manuevers and vibration analysis on LSS. Advanced composite materials have been fabricated for the last seven years, consisting mostly of rocket components such as: nozzles, payload shrouds, exit cones, and nose cones. Recently, however, AFAL has been fabricating composite components such as trusses, tubes and flat panels for space applications. Research on fiber optic sensors at NASA Langley Research Center (NASA LaRC) dates back to 1979. Recently an optical phase locked loop (OPLL) has been developed that can be used to make strain and temperature measurements. Static and dynamic strain measurements have been demonstrated using this device.' To address future space requirements, AFAL and NASA have initiated a program to design, fabricate, and experimentally test composite struts and panels with embedded sensors, actuators, and microprocessors that can be used to control vibration and motion in space structures.

Clearing a Path: The 16-Bit Operating System Jungle Offers Confusion, Not Standardization.

ERIC Educational Resources Information Center

Pournelle, Jerry

1984-01-01

Discusses the design and limited uses of the Pascal, MS-DOS, CP/M, and PC-DOS operating systems as standard operating systems for 16-bit microprocessors, especially with the more sophisticated microcomputers currently being developed. Advantages and disadvantages of Unix--a multitasking, multiuser operating system--as a standard operating system…

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

[Life support of the Mars exploration crew. Control of a zeolite system for carbon dioxide removal from space cabin air within a closed air regeneration cycle].

PubMed

Chekov, Iu F

2009-01-01

The author describes a zeolite system for carbon dioxide removal integrated into a closed air regeneration cycle aboard spacecraft. The continuous operation of a double-adsorbent regeneration system with pCO2-dependable productivity is maintained through programmable setting of adsorption (desorption) semicycle time. The optimal system regulation curve is presented within the space of statistical performance family obtained in quasi-steady operating modes with controlled parameters of the recurrent adsorption-desorption cycle. The automatically changing system productivity ensures continuous intake of concentrated CO2. Control of the adsorption-desorption process is based on calculation of the differential adsorption (desorption) heat from gradient of adsorbent and test inert substance temperatures. The adaptive algorithm of digital control is implemented through the standard spacecraft interface with the board computer system and programmable microprocessor-based controllers.

A distributed microcomputer-controlled system for data acquisition and power spectral analysis of EEG.

PubMed

Vo, T D; Dwyer, G; Szeto, H H

1986-04-01

A relatively powerful and inexpensive microcomputer-based system for the spectral analysis of the EEG is presented. High resolution and speed is achieved with the use of recently available large-scale integrated circuit technology with enhanced functionality (INTEL Math co-processors 8087) which can perform transcendental functions rapidly. The versatility of the system is achieved with a hardware organization that has distributed data acquisition capability performed by the use of a microprocessor-based analog to digital converter with large resident memory (Cyborg ISAAC-2000). Compiled BASIC programs and assembly language subroutines perform on-line or off-line the fast Fourier transform and spectral analysis of the EEG which is stored as soft as well as hard copy. Some results obtained from test application of the entire system in animal studies are presented.

Microprocessors: Laboratory Simulation of Industrial Control Applications.

ERIC Educational Resources Information Center

Gedeon, David V.

1981-01-01

Describes a course to make technical managers more aware of computer technology and how data loggers, programmable controllers, and larger computer systems interact in a hierarchical configuration of manufacturing process control. (SK)

The microprocessor-based synthesizer controller

NASA Technical Reports Server (NTRS)

Wick, M. R.

1980-01-01

Implementation and performance of the microprocessor-based controllers and Dana Digiphase Synthesizer (DCO) installed in the Deep Space Network exciter in the 64-meter and 34-meter subnets to support uplink tuning required for the Voyager-Saturn Encounter is discussed. Test data in tests conducted during the production of the controllers verified the design objective for phase control accuracy of 10 to the - 12 power cycles in eight hours during ramping. Tests conducted require a phase error between a theoretical calculated value and the actual phase of no greater than + or - 1 cycle. Tests included (1) a ramp over a period of eight hours using a ramp rate which covers the synthesizer tuning range (40-51 MHz) and (2) a ramp sequence using the maximum rate (+ or kHz/s) over the tuning range.

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

Simulated fault injection - A methodology to evaluate fault tolerant microprocessor architectures

NASA Technical Reports Server (NTRS)

Choi, Gwan S.; Iyer, Ravishankar K.; Carreno, Victor A.

1990-01-01

A simulation-based fault-injection method for validating fault-tolerant microprocessor architectures is described. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time to assess the resulting fault impact. As an example, a fault-tolerant architecture which models the digital aspects of a dual-channel real-time jet-engine controller is used. The level of effectiveness of the dual configuration with respect to single and multiple transients is measured. The results indicate 100 percent coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.

Embedded computer controlled premixing inline injection system for air-assisted variable-rate sprayers

USDA-ARS?s Scientific Manuscript database

Improvements to reduce chemical waste and environmental pollution for variable-rate sprayers used in orchards and ornamental nurseries require inline injection techniques. A microprocessor controlled premixing inline injection system implementing a ceramic piston chemical metering pump and two small...

BROADBAND DIGITAL GEOPHYSICAL TELEMETRY SYSTEM.

USGS Publications Warehouse

Seeley, Robert L.; Daniels, Jeffrey J.

1984-01-01

A system has been developed to simultaneously sample and transmit digital data from five remote geophysical data receiver stations to a control station that processes, displays, and stores the data. A microprocessor in each remote station receives commands from the control station over a single telemetry channel.

Intermittent/transient faults in digital systems

NASA Technical Reports Server (NTRS)

Masson, G. M.; Glazer, R. E.

1982-01-01

Containment set techniques are applied to 8085 microprocessor controllers so as to transform a typical control system into a slightly modified version, shown to be crashproof: after the departure of the intermittent/transient fault, return to one proper control algorithm is assured, assuming no permanent faults occur.

Neural network application to comprehensive engine diagnostics

NASA Technical Reports Server (NTRS)

Marko, Kenneth A.

1994-01-01

We have previously reported on the use of neural networks for detection and identification of faults in complex microprocessor controlled powertrain systems. The data analyzed in those studies consisted of the full spectrum of signals passing between the engine and the real-time microprocessor controller. The specific task of the classification system was to classify system operation as nominal or abnormal and to identify the fault present. The primary concern in earlier work was the identification of faults, in sensors or actuators in the powertrain system as it was exercised over its full operating range. The use of data from a variety of sources, each contributing some potentially useful information to the classification task, is commonly referred to as sensor fusion and typifies the type of problems successfully addressed using neural networks. In this work we explore the application of neural networks to a different diagnostic problem, the diagnosis of faults in newly manufactured engines and the utility of neural networks for process control.

Energy and time determine scaling in biological and computer designs

PubMed Central

Bezerra, George; Edwards, Benjamin; Brown, James; Forrest, Stephanie

2016-01-01

Metabolic rate in animals and power consumption in computers are analogous quantities that scale similarly with size. We analyse vascular systems of mammals and on-chip networks of microprocessors, where natural selection and human engineering, respectively, have produced systems that minimize both energy dissipation and delivery times. Using a simple network model that simultaneously minimizes energy and time, our analysis explains empirically observed trends in the scaling of metabolic rate in mammals and power consumption and performance in microprocessors across several orders of magnitude in size. Just as the evolutionary transitions from unicellular to multicellular animals in biology are associated with shifts in metabolic scaling, our model suggests that the scaling of power and performance will change as computer designs transition to decentralized multi-core and distributed cyber-physical systems. More generally, a single energy–time minimization principle may govern the design of many complex systems that process energy, materials and information. This article is part of the themed issue ‘The major synthetic evolutionary transitions’. PMID:27431524

Energy and time determine scaling in biological and computer designs.

PubMed

Moses, Melanie; Bezerra, George; Edwards, Benjamin; Brown, James; Forrest, Stephanie

2016-08-19

Metabolic rate in animals and power consumption in computers are analogous quantities that scale similarly with size. We analyse vascular systems of mammals and on-chip networks of microprocessors, where natural selection and human engineering, respectively, have produced systems that minimize both energy dissipation and delivery times. Using a simple network model that simultaneously minimizes energy and time, our analysis explains empirically observed trends in the scaling of metabolic rate in mammals and power consumption and performance in microprocessors across several orders of magnitude in size. Just as the evolutionary transitions from unicellular to multicellular animals in biology are associated with shifts in metabolic scaling, our model suggests that the scaling of power and performance will change as computer designs transition to decentralized multi-core and distributed cyber-physical systems. More generally, a single energy-time minimization principle may govern the design of many complex systems that process energy, materials and information.This article is part of the themed issue 'The major synthetic evolutionary transitions'. © 2016 The Author(s).

[Development of an automatic pneumatic tourniquet system that determines pressures in synchrony with systolic blood pressure].

PubMed

Liu, Hongyun; Li, Kaiyuan; Zhang, Zhengbo; Guo, Junyan; Wang, Weidong

2012-11-01

The correlation coefficients between arterial occlusion pressure and systolic blood pressure, diastolic blood pressure, limb circumference, body mass etc were obtained through healthy volunteer experiments, in which tourniquet were applied on upper/lower extremities. The prediction equations were derived from the data of experiments by multiple regression analysis. Based on the microprocessor C8051F340, a new pneumatic tourniquet system that can determine tourniquet pressure in synchrony with systolic blood pressure was developed and verified the function and stability of designed system. Results showed that the pneumatic tourniquet which automatically adjusts occlusion pressure in accordance with systolic blood pressure could stop the flow of blood to get a bloodless field.

Event parallelism: Distributed memory parallel computing for high energy physics experiments

NASA Astrophysics Data System (ADS)

Nash, Thomas

1989-12-01

This paper describes the present and expected future development of distributed memory parallel computers for high energy physics experiments. It covers the use of event parallel microprocessor farms, particularly at Fermilab, including both ACP multiprocessors and farms of MicroVAXES. These systems have proven very cost effective in the past. A case is made for moving to the more open environment of UNIX and RISC processors. The 2nd Generation ACP Multiprocessor System, which is based on powerful RISC system, is described. Given the promise of still more extraordinary increases in processor performance, a new emphasis on point to point, rather than bussed, communication will be required. Developments in this direction are described.

Purchasing a Microprocessor System for Administrative Use in Schools.

ERIC Educational Resources Information Center

Marshall, David G.

1982-01-01

Describes a series of decision-making steps regarding the purchase of microcomputers for administrative use in schools. Includes such topics as defining information needs and purchasing computer hardware and software. (Author/JJD)

Data transmission system with distributed microprocessors

DOEpatents

Nambu, Shigeo

1985-01-01

A data transmission system having a common request line and a special request line in addition to a transmission line. The special request line has priority over the common request line. A plurality of node stations are multi-drop connected to the transmission line. Among the node stations, a supervising station is connected to the special request line and takes precedence over other slave stations to become a master station. The master station collects data from the slave stations. The station connected to the common request line can assign a master control function to any station requesting to be assigned the master control function within a short period of time. Each station has an auto response control circuit. The master station automatically collects data by the auto response controlling circuit independently of the microprocessors of the slave stations.

Cell cycle-dependent regulation of Aurora kinase B mRNA by the Microprocessor complex.

PubMed

Jung, Eunsun; Seong, Youngmo; Seo, Jae Hong; Kwon, Young-Soo; Song, Hoseok

2014-03-28

Aurora kinase B regulates the segregation of chromosomes and the spindle checkpoint during mitosis. In this study, we showed that the Microprocessor complex, which is responsible for the processing of the primary transcripts during the generation of microRNAs, destabilizes the mRNA of Aurora kinase B in human cells. The Microprocessor-mediated cleavage kept Aurora kinase B at a low level and prevented premature entrance into mitosis. The cleavage was reduced during mitosis leading to the accumulation of Aurora kinase B mRNA and protein. In addition to Aurora kinase B mRNA, the processing of other primary transcripts of miRNAs were also decreased during mitosis. We found that the cleavage was dependent on an RNA helicase, DDX5, and the association of DDX5 and DDX17 with the Microprocessor was reduced during mitosis. Thus, we propose a novel mechanism by which the Microprocessor complex regulates stability of Aurora kinase B mRNA and cell cycle progression. Copyright © 2014 Elsevier Inc. All rights reserved.

Gait and balance of transfemoral amputees using passive mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, K R; Levine, J A; Brey, R H; Iverson, B K; McCrady, S K; Padgett, D J; Joyner, M J

2007-10-01

Microprocessor-controlled knee joints appeared on the market a decade ago. These joints are more sophisticated and more expensive than mechanical ones. The literature is contradictory regarding changes in gait and balance when using these sophisticated devices. This study employed a crossover design to assess the comparative performance of a passive mechanical knee prosthesis compared to a microprocessor-controlled knee joint in 15 subjects with an above-knee amputation. Objective measurements of gait and balance were obtained. Subjects demonstrated significantly improved gait characteristics after receiving the microprocessor-controlled prosthetic knee joint (p<0.01). Improvements in gait were a transition from a hyperextended knee to a flexed knee during loading response which resulted in a change from an internal knee flexor moment to a knee extensor moment. The participants' balance also improved (p<0.01). All conditions of the Sensory Organization Test (SOT) demonstrated improvements in equilibrium score. The composite score also increased. Transfemoral amputees using a microprocessor-controlled knee have significant improvements in gait and balance.

Functional Anatomy of the Human Microprocessor.

PubMed

Nguyen, Tuan Anh; Jo, Myung Hyun; Choi, Yeon-Gil; Park, Joha; Kwon, S Chul; Hohng, Sungchul; Kim, V Narry; Woo, Jae-Sung

2015-06-04

MicroRNA (miRNA) maturation is initiated by Microprocessor composed of RNase III DROSHA and its cofactor DGCR8, whose fidelity is critical for generation of functional miRNAs. To understand how Microprocessor recognizes pri-miRNAs, we here reconstitute human Microprocessor with purified recombinant proteins. We find that Microprocessor is an ∼364 kDa heterotrimeric complex of one DROSHA and two DGCR8 molecules. Together with a 23-amino acid peptide from DGCR8, DROSHA constitutes a minimal functional core. DROSHA serves as a "ruler" by measuring 11 bp from the basal ssRNA-dsRNA junction. DGCR8 interacts with the stem and apical elements through its dsRNA-binding domains and RNA-binding heme domain, respectively, allowing efficient and accurate processing. DROSHA and DGCR8, respectively, recognize the basal UG and apical UGU motifs, which ensure proper orientation of the complex. These findings clarify controversies over the action mechanism of DROSHA and allow us to build a general model for pri-miRNA processing. Copyright © 2015 Elsevier Inc. All rights reserved.

Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

DTIC Science & Technology

2015-03-10

for Public Release; Distribution Unlimited Final Report: Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor The views...P.O. Box 12211 Research Triangle Park, NC 27709-2211 Superconductor technology, RSFQ, RQL, processor design, arithmetic units, high-performance...Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor Report Title The major objective of the project was to design and demonstrate operation

Energy expenditure and activity of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, Kenton R; Levine, James A; Brey, Robert H; McCrady, Shelly K; Padgett, Denny J; Joyner, Michael J

2008-07-01

To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Repeated-measures design to evaluate comparative functional outcomes. Exercise physiology laboratory and community free-living environment. Subjects (N=15; 12 men, 3 women; age, 42+/-9 y; range, 26-57 y) with transfemoral amputation. Research participants were long-term users of a mechanical prosthesis (20+/-10 y as an amputee; range, 3-36 y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18+/-8 wk) before being retested. Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Subjects demonstrated significantly increased physical activity-related energy expenditure levels in the participant's free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life.

The microcomputer workstation - An alternate hardware architecture for remotely sensed image analysis

NASA Technical Reports Server (NTRS)

Erickson, W. K.; Hofman, L. B.; Donovan, W. E.

1984-01-01

Difficulties regarding the digital image analysis of remotely sensed imagery can arise in connection with the extensive calculations required. In the past, an expensive large to medium mainframe computer system was needed for performing these calculations. For image-processing applications smaller minicomputer-based systems are now used by many organizations. The costs for such systems are still in the range from $100K to $300K. Recently, as a result of new developments, the use of low-cost microcomputers for image processing and display systems appeared to have become feasible. These developments are related to the advent of the 16-bit microprocessor and the concept of the microcomputer workstation. Earlier 8-bit microcomputer-based image processing systems are briefly examined, and a computer workstation architecture is discussed. Attention is given to a microcomputer workstation developed by Stanford University, and the design and implementation of a workstation network.

Microcomputer-based system for registration of oxygen tension in peripheral muscle.

PubMed

Odman, S; Bratt, H; Erlandsson, I; Sjögren, L

1986-01-01

For registration of oxygen tension fields in peripheral muscle a microcomputer based system was designed on the M6800 microprocessor. The system was designed to record the signals from a multiwire oxygen electrode, MDO, which is a multiwire electrode for measuring oxygen on the surface of an organ. The system contained patient safety isolation unit built on optocopplers and the upper frequency limit was 0.64 Hz. Collected data were corrected for drift and temperature changes during the measurement by using pre- and after calibrations and a linear compensation technique. Measure drift of the electrodes were proved to be linear and thus the drift could be compensated for. The system was tested in an experiment on pig. To study the distribution of oxygen statistically mean, standard deviation, skewness and curtosis were calculated. To see changes or differences between histograms a Kolmogorv-Smirnov test was used.

Functional added value of microprocessor-controlled knee joints in daily life performance of Medicare Functional Classification Level-2 amputees.

PubMed

Theeven, Patrick; Hemmen, Bea; Rings, Frans; Meys, Guido; Brink, Peter; Smeets, Rob; Seelen, Henk

2011-10-01

To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. Randomised cross-over trial. Forty-one persons with unilateral above-knee or knee disarticulation limb loss, classified as Medicare Functional Classification Level-2 (MFCL-2). Participants were measured in 3 conditions, i.e. using a mechanically controlled knee joint and two types of microprocessor-controlled prosthetic knee joints. Functional performance level was assessed using a test in which participants performed 17 simulated activities of daily living (Assessment of Daily Activity Performance in Transfemoral amputees test). Performance time was measured and self-perceived level of difficulty was scored on a visual analogue scale for each activity. High levels of within-group variability in functional performance obscured detection of any effects of using a microprocessor-controlled prosthetic knee joint. Data analysis after stratification of the participants into 3 subgroups, i.e. participants with a "low", "intermediate" and "high" functional mobility level, showed that the two higher functional subgroups performed significantly faster using microprocessor-controlled prosthetic knee joints. MFCL-2 amputees constitute a heterogeneous patient group with large variation in functional performance levels. A substantial part of this group seems to benefit from using a microprocessor-controlled prosthetic knee joint when performing activities of daily living.

Universal control and measuring system for modern classic and amorphous magnetic materials single/on-line strip testers

NASA Astrophysics Data System (ADS)

Zemánek, Ivan; Havlíček, Václav

2006-09-01

A new universal control and measuring system for classic and amorphous soft magnetic materials single/on-line strip testing has been developed at the Czech Technical University in Prague. The measuring system allows to measure magnetization characteristic and specific power losses of different tested materials (strips) at AC magnetization of arbitrary magnetic flux density waveform at wide range of frequencies 20 Hz-20 kHz. The measuring system can be used for both single strip testing in laboratories and on-line strip testing during the production process. The measuring system is controlled by two-stage master-slave control system consisting of the external PC (master) completed by three special A/D measuring plug-in boards, and local executing control unit (slave) with one-chip microprocessor 8051, connected with PC by the RS232 serial line. The "user friendly" powerful control software implemented on the PC and the effective program code for the microprocessor give possibility for full automatic measurement with high measuring power and high measuring accuracy.

Systems Engineering

DTIC Science & Technology

1989-05-01

Faced with complaints about lengthy and costly developments , rapid obsolescence, and excessive costs of ownership, we have all heard the following...microwave integrated circuits raises similar system and sub-system issues. Microprocessor developments raise new questions regarding the trade-offs between...imply the need for and utilization of more specialists, but future avionics developments will also require systems-oriented engineess. By definition

Aerospace Applications of Microprocessors

NASA Technical Reports Server (NTRS)

1980-01-01

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed.

1988 IEEE Aerospace Applications Conference, Park City, UT, Feb. 7-12, 1988, Digest

NASA Astrophysics Data System (ADS)

The conference presents papers on microwave applications, data and signal processing applications, related aerospace applications, and advanced microelectronic products for the aerospace industry. Topics include a high-performance antenna measurement system, microwave power beaming from earth to space, the digital enhancement of microwave component performance, and a GaAs vector processor based on parallel RISC microprocessors. Consideration is also given to unique techniques for reliable SBNR architectures, a linear analysis subsystem for CSSL-IV, and a structured singular value approach to missile autopilot analysis.

The automated counting of beating rates in individual cultured heart cells.

PubMed

Collins, G A; Dower, R; Walker, M J

1981-12-01

The effect of drugs on the beating rate of cultured heart cells can be monitored in a number of ways. The simultaneous automated measurement of beating rates of a number of cells allows drug effects to be rapidly quantified. A photoresistive detector placed on a television image of a cell, when coupled to operational amplifiers, gives binary signals that can be processed by a microprocessor. On this basis, we have devised a system that is capable of simultaneously monitoring the individual beating of six single cultured heart cells. A microprocessor automatically processes data obtained under different experimental conditions and records it in suitable descriptive formats such as dose-response curves and double reciprocal plots.

A proposed microcomputer implementation of an Omega navigation processor

NASA Technical Reports Server (NTRS)

Abel, J. D.

1976-01-01

A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.

An electronic flow control system for a variable-rate tree sprayer

USDA-ARS?s Scientific Manuscript database

Precise modulation of nozzle flow rates is a critical measure to achieve variable-rate spray applications. An electronic flow rate control system accommodating with microprocessors and pulse width modulation (PWM) controlled solenoid valves was designed to manipulate the output of spray nozzles inde...

Development of digital flow control system for multi-channel variable-rate sprayers

USDA-ARS?s Scientific Manuscript database

Precision modulation of nozzle flow rates is a critical step for variable-rate spray applications in orchards and ornamental nurseries. An automatic flow rate control system activated with microprocessors and pulse width modulation (PWM) controlled solenoid valves was developed to control flow rates...

Efficient system interrupt concept design at the microprogramming level

DOE Office of Scientific and Technical Information (OSTI.GOV)

Fakharzadeh, M.M.

1989-01-01

Over the past decade the demand for high speed super microcomputers has been tremendously increased. To satisfy this demand many high speed 32-bit microcomputers have been designed. However, the currently available 32-bit systems do not provide an adequate solution to many highly demanding problems such as in multitasking, and in interrupt driven applications, which both require context switching. Systems for these purposes usually incorporate sophisticated software. In order to be efficient, a high end microprocessor based system must satisfy stringent software demands. Although these microprocessors use the latest technology in the fabrication design and run at a very high speed,more » they still suffer from insufficient hardware support for such applications. All too often, this lack also is the premier cause of execution inefficiency. In this dissertation a micro-programmable control unit and operation unit is considered in an advanced design. An automaton controller is designed for high speed micro-level interrupt handling. Different stack models are designed for the single task and multitasking environment. The stacks are used for storage of various components of the processor during the interrupt calls, procedure calls, and task switching. A universal (as an example seven port) register file is designed for high speed parameter passing, and intertask communication in the multitasking environment. In addition, the register file provides a direct path between ALU and the peripheral data which is important in real-time control applications. The overall system is a highly parallel architecture, with no pipeline and internal cache memory, which allows the designer to be able to predict the processor's behavior during the critical times.« less

OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems.

PubMed

Stone, John E; Gohara, David; Shi, Guochun

2010-05-01

We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures.

The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

DTIC Science & Technology

2017-09-01

parallel, randomized, controlled clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power, will...Department of the Army position, policy or decision unless so designated by other documentation. CONTRACTING ORGANIZATION: University of Tennessee

Formal proof of the AVM-1 microprocessor using the concept of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

A microprocessor designated AVM-1 was designed to demonstrate the use of generic interpreters in verifying hierarchically decomposed microprocessor specifications. This report is intended to document the high-order language (HOL) code verifying AVM-1. The organization of the proof is discussed and some technical details concerning the execution of the proof scripts in HOL are presented. The proof scripts used to verify AVM-1 are also presented.

Full temperature single event upset characterization of two microprocessor technologies

NASA Technical Reports Server (NTRS)

Nichols, Donald K.; Coss, James R.; Smith, L. S.; Rax, Bernard; Huebner, Mark

1988-01-01

Data for the 9450 I3L bipolar microprocessor and the 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full MIL-SPEC temperature range of -55 to 125 C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different.

PDSparc: A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-09-24

Kate   Thurmer  MIT  Lincoln  Laboratory,  Lexington,   MA,  USA Distribution A: Public Release   ABSTRACT   Microprocessors are the...enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors usually start...out as soft-cores that are parameterized at design time to realize exclusively the specific needs of the application. The microprocessor is a small

Initial experience with a microprocessor controlled current based defibrillator.

PubMed Central

Dalzell, G W; Cunningham, S R; Anderson, J; Adgey, A A

1989-01-01

Intramyocardial current flow is a critical factor in successful ventricular defibrillation. The main determinants of intramyocardial current flow during transthoracic countershock are the selected energy and the transthoracic impedance of the patient. To optimise the success of the first shock and to titrate energy dosage according to each patient's transthoracic impedance, a microprocessor controlled current based defibrillator was developed. It was compared with a conventional energy based protocol of 200 J (delivered energy), 200 J, then 360 J if required in 42 consecutive episodes of ventricular fibrillation in 33 men and seven women. The mean (SD) predicted transthoracic impedance was 69.9 (14.0) omega. First shock success with the standard protocol was 80.9%, and first or second shock success was 95.2%. The microprocessor controlled current based defibrillator automatically measured transthoracic impedance and calculated the energy required to develop a selected current in each patient. A current protocol of 30 A, 30 A, then 40 A, if required, was used in 29 men and 12 women with 41 episodes of ventricular fibrillation. Transthoracic impedance (mean 65.1 (15.9) omega) was similar to that in the energy protocol group and success rates for first shock (82.9%) and first or second shocks (97.5%) were also similar. The mean delivered energy per shock with the current based defibrillator for first or second shock success was significantly less (144.8 J) with the energy protocol (200 J). The mean peak current of successful shocks was also significantly reduced (29.0 v 31.9 A). A current based defibrillator titrates energy according to transthoracic impedance; it has a success rate comparable to conventional defibrillators but it delivers significantly less energy and current per shock. Images Fig 1 PMID:2757862

Modernization of the Control Systems of High-Frequency, Brush-Free, and Collector Exciters of Turbogenerators

DOE Office of Scientific and Technical Information (OSTI.GOV)

Popov, E. N., E-mail: enpo@ruselmash.ru; Komkov, A. L.; Ivanov, S. L.

Methods of modernizing the regulation systems of electric machinery exciters with high-frequency, brush-free, and collector exciters by means of microprocessor technology are examined. The main problems of modernization are to increase the response speed of a system and to use a system stabilizer to increase the stability of the power system.

Full autonomous microline trace robot

NASA Astrophysics Data System (ADS)

Yi, Deer; Lu, Si; Yan, Yingbai; Jin, Guofan

2000-10-01

Optoelectric inspection may find applications in robotic system. In micro robotic system, smaller optoelectric inspection system is preferred. However, as miniaturizing the size of the robot, the number of the optoelectric detector becomes lack. And lack of the information makes the micro robot difficult to acquire its status. In our lab, a micro line trace robot has been designed, which autonomous acts based on its optoelectric detection. It has been programmed to follow a black line printed on the white colored ground. Besides the optoelectric inspection, logical algorithm in the microprocessor is also important. In this paper, we propose a simply logical algorithm to realize robot's intelligence. The robot's intelligence is based on a AT89C2051 microcontroller which controls its movement. The technical details of the micro robot are as follow: dimension: 30mm*25mm*35*mm; velocity: 60mm/s.

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2013 CFR

2013-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2012 CFR

2012-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2011 CFR

2011-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2014 CFR

2014-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

Flight Experiment Demonstration System (FEDS) analysis report

NASA Technical Reports Server (NTRS)

Shank, D. E.

1986-01-01

The purpose of the Flight Experiment Demonstration System (FEDS) was to show, in a simulated spacecraft environment, the feasibility of using a microprocessor to automate the onboard orbit determination functions. The software and hardware configuration used to support FEDS during the demonstration and the results of the demonstration are discussed.

Real-time video compressing under DSP/BIOS

NASA Astrophysics Data System (ADS)

Chen, Qiu-ping; Li, Gui-ju

2009-10-01

This paper presents real-time MPEG-4 Simple Profile video compressing based on the DSP processor. The programming framework of video compressing is constructed using TMS320C6416 Microprocessor, TDS510 simulator and PC. It uses embedded real-time operating system DSP/BIOS and the API functions to build periodic function, tasks and interruptions etcs. Realize real-time video compressing. To the questions of data transferring among the system. Based on the architecture of the C64x DSP, utilized double buffer switched and EDMA data transfer controller to transit data from external memory to internal, and realize data transition and processing at the same time; the architecture level optimizations are used to improve software pipeline. The system used DSP/BIOS to realize multi-thread scheduling. The whole system realizes high speed transition of a great deal of data. Experimental results show the encoder can realize real-time encoding of 768*576, 25 frame/s video images.

Greenhouse irrigation control system design based on ZigBee and fuzzy PID technology

NASA Astrophysics Data System (ADS)

Zhou, Bing; Yang, Qiliang; Liu, Kenan; Li, Peiqing; Zhang, Jing; Wang, Qijian

In order to achieve the water demand information accurately detect of the greenhouse crop and its precision irrigation automatic control, this article has designed a set of the irrigated control system based on ZigBee and fuzzy PID technology, which composed by the soil water potential sensor, CC2530F256 wireless microprocessor, IAR Embedded Workbench software development platform. And the time of Irrigation as the output .while the amount of soil water potential and crop growth cycle as the input. The article depended on Greenhouse-grown Jatropha to verify the object, the results show that the system can irrigate timely and appropriately according to the soil water potential and water demend of the different stages of Jatropha growth , which basically meet the design requirements. Therefore, the system has broad application prospects in the amount of greenhouse crop of fine control irrigation.

The comparison of transfemoral amputees using mechanical and microprocessor- controlled prosthetic knee under different walking speeds: A randomized cross-over trial.

PubMed

Cao, Wujing; Yu, Hongliu; Zhao, Weiliang; Meng, Qiaoling; Chen, Wenming

2018-04-20

The microprocessor-controlled prosthetic knees have been introduced to transfemoral amputees due to advances in biomedical engineering. A body of scientific literature has shown that the microprocessor-controlled prosthetic knees improve the gait and functional abilities of persons with transfemoral amputation. The aim of this study was to propose a new microprocessor-controlled prosthetic knee (MPK) and compare it with non-microprocessor-controlled prosthetic knees (NMPKs) under different walking speeds. The microprocessor-controlled prosthetic knee (i-KNEE) with hydraulic damper was developed. The comfortable self-selected walking speeds of 12 subjects with i-KNEE and NMPK were obtained. The maximum swing flexion knee angle and gait symmetry were compared in i-KNEE and NMPK condition. The comfortable self-selected walking speeds of some subjects were higher with i-KNEE while some were not. There was no significant difference in comfortable self-selected walking speed between the i-KNEE and the NMPK condition (P= 0.138). The peak prosthetic knee flexion during swing in the i-KNEE condition was between sixty and seventy degree under any walking speed. In the NMPK condition, the maximum swing flexion knee angle changed significantly. And it increased with walking speed. There is no significant difference in knee kinematic symmetry when the subjects wear the i-KNEE or NMPK. The results of this study indicated that the new microprocessor-controlled prosthetic knee was suitable for transfemoral amputees. The maximum swing flexion knee angle under different walking speeds showed different properties in the NMPK and i-KNEE condition. The i-KNEE was more adaptive to speed changes. There was little difference of comfortable self-selected walking speed between i-KNEE and NMPK condition.

Microprocessor Controlled Isometric Contractions of Cat Gastrocnemius Muscle.

DTIC Science & Technology

1981-12-01

A-A15 504 AIR FORCE INST OF TECH WRIGHT-PATTERSON AFS OH 5CHOO--ETC F/6 6/2 MICROPROCESSOR CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROC-ETC(U) D...CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROCNEMIUS MUSCLE THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of...1981 Appzoved for public release; distribution unlimited. AFIT/GE/EE/81D-4O \\ MICROPROCESSOR CONTROLLED ISOMETRIC COMUtCTIONS OF CAT GASTfOCNEMIUS i

Energy Expenditure and Activity of Transfemoral Amputees Using Mechanical and Microprocessor-Controlled Prosthetic Knees

PubMed Central

Kaufman, Kenton R.; Levine, James A.; Brey, Robert H.; McCrady, Shelly K.; Padgett, Denny J.; Joyner, Michael J.

2009-01-01

Objective To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Design Repeated-measures design to evaluate comparative functional outcomes. Setting Exercise physiology laboratory and community free-living environment. Participants Subjects (N=15; 12 men, 3 women; age, 42±9y; range, 26 –57y) with transfemoral amputation. Intervention Research participants were long-term users of a mechanical prosthesis (20±10y as an amputee; range, 3–36y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18±8wk) before being retested. Main Outcome Measures Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Results Subjects demonstrated significantly increased physical activity–related energy expenditure levels in the participant’s free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). Conclusions People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life. PMID:18586142

Efficacy of Code Optimization on Cache-based Processors

NASA Technical Reports Server (NTRS)

VanderWijngaart, Rob F.; Chancellor, Marisa K. (Technical Monitor)

1997-01-01

The current common wisdom in the U.S. is that the powerful, cost-effective supercomputers of tomorrow will be based on commodity (RISC) micro-processors with cache memories. Already, most distributed systems in the world use such hardware as building blocks. This shift away from vector supercomputers and towards cache-based systems has brought about a change in programming paradigm, even when ignoring issues of parallelism. Vector machines require inner-loop independence and regular, non-pathological memory strides (usually this means: non-power-of-two strides) to allow efficient vectorization of array operations. Cache-based systems require spatial and temporal locality of data, so that data once read from main memory and stored in high-speed cache memory is used optimally before being written back to main memory. This means that the most cache-friendly array operations are those that feature zero or unit stride, so that each unit of data read from main memory (a cache line) contains information for the next iteration in the loop. Moreover, loops ought to be 'fat', meaning that as many operations as possible are performed on cache data-provided instruction caches do not overflow and enough registers are available. If unit stride is not possible, for example because of some data dependency, then care must be taken to avoid pathological strides, just ads on vector computers. For cache-based systems the issues are more complex, due to the effects of associativity and of non-unit block (cache line) size. But there is more to the story. Most modern micro-processors are superscalar, which means that they can issue several (arithmetic) instructions per clock cycle, provided that there are enough independent instructions in the loop body. This is another argument for providing fat loop bodies. With these restrictions, it appears fairly straightforward to produce code that will run efficiently on any cache-based system. It can be argued that although some of the important computational algorithms employed at NASA Ames require different programming styles on vector machines and cache-based machines, respectively, neither architecture class appeared to be favored by particular algorithms in principle. Practice tells us that the situation is more complicated. This report presents observations and some analysis of performance tuning for cache-based systems. We point out several counterintuitive results that serve as a cautionary reminder that memory accesses are not the only factors that determine performance, and that within the class of cache-based systems, significant differences exist.

An integrtated approach to the use of Landsat TM data for gold exploration in west central Nevada

NASA Technical Reports Server (NTRS)

Mouat, D. A.; Myers, J. S.; Miller, N. L.

1987-01-01

This paper represents an integration of several Landsat TM image processing techniques with other data to discriminate the lithologies and associated areas of hydrothermal alteration in the vicinity of the Paradise Peak gold mine in west central Nevada. A microprocessor-based image processing system and an IDIMS system were used to analyze data from a 512 X 512 window of a Landsat-5 TM scene collected on June 30, 1984. Image processing techniques included simple band composites, band ratio composites, principal components composites, and baseline-based composites. These techniques were chosen based on their ability to discriminate the spectral characteristics of the products of hydrothermal alteration as well as of the associated regional lithologies. The simple band composite, ratio composite, two principal components composites, and the baseline-based composites separately can define the principal areas of alteration. Combined, they provide a very powerful exploration tool.

Smart call box field operational test evaluation : subtest reports

DOT National Transportation Integrated Search

1997-05-01

Smart call boxes are an enhanced version of devices used as emergency call boxes in California. The overall system consists of a microprocessor, a cellular communications transceiver, solar power sources, data collection devices, maintenance computer...

Smart call box field operational test evaluation : summary report

DOT National Transportation Integrated Search

1997-05-01

Smart call boxes are an enhanced version of devices used as emergency call boxes in California. The overall system consists of a microprocessor, a cellular communications transceiver, solar power sources, data collection devices, maintenance computer...

OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems

PubMed Central

Stone, John E.; Gohara, David; Shi, Guochun

2010-01-01

We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures. PMID:21037981

Effect of various features on the life cycle cost of the timing/synchronization subsystem of the DCS digital communications network

NASA Technical Reports Server (NTRS)

Kimsey, D. B.

1978-01-01

The effect on the life cycle cost of the timing subsystem was examined, when these optional features were included in various combinations. The features included mutual control, directed control, double-ended reference links, independence of clock error measurement and correction, phase reference combining, self-organization, smoothing for link and nodal dropouts, unequal reference weightings, and a master in a mutual control network. An overall design of a microprocessor-based timing subsystem was formulated. The microprocessor (8080) implements the digital filter portion of a digital phase locked loop, as well as other control functions such as organization of the network through communication with processors at neighboring nodes.

Radiation-hardened fast acquisition/weak signal tracking system and method

NASA Technical Reports Server (NTRS)

Winternitz, Luke (Inventor); Boegner, Gregory J. (Inventor); Sirotzky, Steve (Inventor)

2009-01-01

A global positioning system (GPS) receiver and method of acquiring and tracking GPS signals comprises an antenna adapted to receive GPS signals; an analog radio frequency device operatively connected to the antenna and adapted to convert the GPS signals from an analog format to a digital format; a plurality of GPS signal tracking correlators operatively connected to the analog RF device; a GPS signal acquisition component operatively connected to the analog RF device and the plurality of GPS signal tracking correlators, wherein the GPS signal acquisition component is adapted to calculate a maximum vector on a databit correlation grid; and a microprocessor operatively connected to the plurality of GPS signal tracking correlators and the GPS signal acquisition component, wherein the microprocessor is adapted to compare the maximum vector with a predetermined correlation threshold to allow the GPS signal to be fully acquired and tracked.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Automatic multi-banking of memory for microprocessors

NASA Technical Reports Server (NTRS)

Wiker, G. A. (Inventor)

1984-01-01

A microprocessor system is provided with added memories to expand its address spaces beyond its address word length capacity by using indirect addressing instructions of a type having a detectable operations code and dedicating designated address spaces of memory to each of the added memories, one space to a memory. By decoding each operations code of instructions read from main memory into a decoder to identify indirect addressing instructions of the specified type, and then decoding the address that follows in a decoder to determine which added memory is associated therewith, the associated added memory is selectively enabled through a unit while the main memory is disabled to permit the instruction to be executed on the location to which the effective address of the indirect address instruction points, either before the indirect address is read from main memory or afterwards, depending on how the system is arranged by a switch.

Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.; Bashkow, T.

1978-01-01

The position of an emergency transmitter may be determined by measuring the Doppler shift of the distress signal as received by an orbiting satellite. This requires the computation of an initial estimate and refinement of this estimate through an iterative, nonlinear, least squares estimation. A version of the algorithm was implemented and tested by locating a transmitter on the premises and obtaining observations from a satellite. The computer used was an IBM 360/95. The position was determined within the desired 10 km radius accuracy. The feasibility of performing the same task in real time using microprocessor technology, was determined. The least squares algorithm was implemented on an Intel 8080 microprocessor. The results indicate that a microprocessor can easily match the IBM implementation in accuracy and be performed inside the time limitations set.

Degradations to microprocessor-based systems due to environmental stressors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Messman, P. A.; Peilai, Z.; Goodenow, D. A.

Recent studies indicate that EMI/RFI is the most significant environmental Stressor with potential for leading to digital systems degradation and failure. With digital I and C and wireless technology becoming standard in many industrial environments, nuclear power plant operators of current and future plants will or already have implemented these technologies seeking to leverage the economic benefits of such technology. With digital I and C systems' higher susceptibility to EMI/RFI and the increased environmental noise introduced by wireless-based systems, this produces a dangerous combination that could lead to logic errors, equipment damage, and faults in digital I and C. Failuresmore » to these systems, especially to safety-critical systems, could lead to loss of system, which would pose a safety risk and decrease in operational efficiency. In order to better understand system degradations by these means and aid in regulation and guidance, we propose to experimentally study the susceptibility of digital I and C to wireless technology. (authors)« less

Continuous-Reading Cryogen Level Sensor

NASA Technical Reports Server (NTRS)

Barone, F. E.; Fox, E.; Macumber, S.

1984-01-01

Two pressure transducers used in system for measuring amount of cryogenic liquid in tank. System provides continuous measurements accurate within 0.03 percent. Sensors determine pressure in liquid and vapor in tank. Microprocessor uses pressure difference to compute mass of cryogenic liquid in tank. New system allows continuous sensing; unaffected by localized variations in composition and density as are capacitance-sensing schemes.

Flight Experiment Demonstration System (FEDS): Mathematical specification

NASA Technical Reports Server (NTRS)

Shank, D. E.

1984-01-01

Computational models for the flight experiment demonstration system (FEDS) code 580 were developed. The FEDS is a modification of the automated orbit determination system which was developed during 1981 and 1982. The purpose of FEDS is to demonstrate, in a simulated spacecraft environment, the feasibility of using microprocessors to perform onboard orbit determination with limited ground support.

Importance of balanced architectures in the design of high-performance imaging systems

NASA Astrophysics Data System (ADS)

Sgro, Joseph A.; Stanton, Paul C.

1999-03-01

Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.