Comparative biomechanical analysis of current microprocessor-controlled prosthetic knee joints.

PubMed

Bellmann, Malte; Schmalz, Thomas; Blumentritt, Siegmar

2010-04-01

To investigate and identify functional differences of 4 microprocessor-controlled prosthetic knee joints (C-Leg, Hybrid Knee [also called Energy Knee], Rheo Knee, Adaptive 2). Tested situations were walking on level ground, on stairs and ramps; additionally, the fall prevention potentials for each design were examined. The measuring technology used included an optoelectronic camera system combined with 2 forceplates as well as a mobile spiroergometric system. The study was conducted in a gait laboratory. Subjects with unilateral transfemoral amputations (N=9; mobility grade, 3-4; age, 22-49y) were tested. Participants were fitted and tested with 4 different microprocessor-controlled knee joints. Static prosthetic alignment, time distance parameters, kinematic and kinetic data and metabolic energy consumption. Compared with the Hybrid Knee and the Adaptive 2, the C-Leg offers clear advantages in the provision of adequate swing phase flexion resistances and terminal extension damping during level walking at various speeds, especially at higher walking speeds. The Rheo Knee provides sufficient terminal extension; however, swing phase flexion resistances seem to be too low. The values for metabolic energy consumption show only slight differences during level walking. The joint resistances generated for descending stairs and ramps relieve the contralateral side to varying degrees. When walking on stairs, safety-relevant technical differences between the investigated joint types can be observed. Designs with adequate internal resistances offer stability advantages when the foot is positioned on the step. Stumble recovery tests reveal that the different knee joint designs vary in their effectiveness in preventing the patient from falling. The patient benefits provided by the investigated electronic prosthetic knee joints differ considerably. The C-Leg appears to offer the amputee greater functional and safety-related advantages than the other tested knee joints. Reduced loading of the contralateral side has been demonstrated during ramp and stair descent. Metabolic energy consumption does not vary significantly between the tested knees. Hence, this parameter seems not to be a suitable criterion for assessing microprocessor-controlled knee components. Copyright 2010 American Congress of Rehabilitation Medicine. Published by Elsevier Inc. All rights reserved.

75 FR 2591 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2010-01-15

... on vital microprocessor-based systems. CSXT proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative procedures every 4 years after initial... vital microprocessor-based systems. These systems utilize programmed logic equations in lieu of relays...

Development and testing of the Rho Sigma Incorporated microprocessor control subsystem

NASA Technical Reports Server (NTRS)

Hankins, J. D.

1979-01-01

Product development and performance tests of three programmable microprocessor controllers for use with solar heating and cooling systems are presented. The products were developed to be marketable for public use.

Small Microprocessor for ASIC or FPGA Implementation

NASA Technical Reports Server (NTRS)

Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

2011-01-01

A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

A rocket-borne data-manipulation experiment using a microprocessor

NASA Technical Reports Server (NTRS)

Davis, L. L.; Smith, L. G.; Voss, H. D.

1979-01-01

The development of a data-manipulation experiment using a Z-80 microprocessor is described. The instrumentation is included in the payloads of two Nike Apache sounding rockets used in an investigation of energetic particle fluxes. The data from an array of solid-state detectors and an electrostatic analyzer is processed to give the energy spectrum as a function of pitch angle. The experiment performed well in its first flight test: Nike Apache 14.543 was launched from Wallops Island at 2315 EST on 19 June 1978. The system was designed to be easily adaptable to other data-manipulation requirements and some suggestions for further development are included.

High-speed microprocessor characterization. Final report/project accomplishments summary, CRADA Number KCP-94-1004

DOE Office of Scientific and Technical Information (OSTI.GOV)

Brown, L.W.

The objective of the project was to characterize and document the critical operating parameters of an 0.8-micron, 350-MHz, 32-bit microprocessor prototype. The roles of FM and T and the participant company were: FM and T -- evaluation performance of the prototype 32-bit microprocessor using the IDS5000 and Tektronix S3260 Integrated Circuit Test System; Corda -- design and build the prototype microprocessor. This project was terminated with nearly all of the planned activities unaddressed.

Microprocessor-Controlled Laser Balancing System

NASA Technical Reports Server (NTRS)

Demuth, R. S.

1985-01-01

Material removed by laser action as part tested for balance. Directed by microprocessor, laser fires appropriate amount of pulses in correct locations to remove necessary amount of material. Operator and microprocessor software interact through video screen and keypad; no programing skills or unprompted system-control decisions required. System provides complete and accurate balancing in single load-and-spinup cycle.

SEU induced errors observed in microprocessor systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Asenek, V.; Underwood, C.; Oldfield, M.

In this paper, the authors present software tools for predicting the rate and nature of observable SEU induced errors in microprocessor systems. These tools are built around a commercial microprocessor simulator and are used to analyze real satellite application systems. Results obtained from simulating the nature of SEU induced errors are shown to correlate with ground-based radiation test data.

Software resilience and the effectiveness of software mitigation in microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Baker, Zachary; Fairbanks, Tom

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

Software resilience and the effectiveness of software mitigation in microcontrollers

DOE PAGES

Quinn, Heather; Baker, Zachary; Fairbanks, Tom; ...

2015-12-01

Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

Impact of a stance phase microprocessor-controlled knee prosthesis on level walking in lower functioning individuals with a transfemoral amputation.

PubMed

Eberly, Valerie J; Mulroy, Sara J; Gronley, JoAnne K; Perry, Jacquelin; Yule, William J; Burnfield, Judith M

2014-12-01

For individuals with transfemoral amputation, walking with a prosthesis presents challenges to stability and increases the demand on the hip of the prosthetic limb. Increasing age or comorbidities magnify these challenges. Computerized prosthetic knee joints improve stability and efficiency of gait, but are seldom prescribed for less physically capable walkers who may benefit from them. To compare level walking function while wearing a microprocessor-controlled knee (C-Leg Compact) prosthesis to a traditionally prescribed non-microprocessor-controlled knee prosthesis for Medicare Functional Classification Level K-2 walkers. Crossover. Stride characteristics, kinematics, kinetics, and electromyographic activity were recorded in 10 participants while walking with non-microprocessor-controlled knee and Compact prostheses. Walking with the Compact produced significant increase in velocity, cadence, stride length, single-limb support, and heel-rise timing compared to walking with the non-microprocessor-controlled knee prosthesis. Hip and thigh extension during late stance improved bilaterally. Ankle dorsiflexion, knee extension, and hip flexion moments of the prosthetic limb were significantly improved. Improvements in walking function and stability on the prosthetic limb were demonstrated by the K-2 level walkers when using the C-Leg Compact prosthesis. Understanding the impact of new prosthetic designs on gait mechanics is essential to improve prescription guidelines for deconditioned or older persons with transfemoral amputation. Prosthetic designs that improve stability for safety and walking function have the potential to improve community participation and quality of life. © The International Society for Prosthetics and Orthotics 2013.

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

A methodology was developed a assess the upset susceptibility/reliability of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general purpose microprocessor were studied. The upset tests involved the random input of analog transients which model lightning induced signals onto interface lines of an 8080 based microcomputer from which upset error data was recorded. The program code on the microprocessor during tests is designed to exercise all of the machine cycles and memory addressing techniques implemented in the 8080 central processing unit. A statistical analysis is presented in which possible correlations are established between the probability of upset occurrence and transient signal inputs during specific processing states and operations. A stochastic upset susceptibility model for the 8080 microprocessor is presented. The susceptibility of this microprocessor to upset, once analog transients have entered the system, is determined analytically by calculating the state probabilities of the stochastic model.

Microprocessor-based single particle calibration of scintillation counter

NASA Technical Reports Server (NTRS)

Mazumdar, G. K. D.; Pathak, K. M.

1985-01-01

A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available.

49 CFR 229.27 - Annual tests.

Code of Federal Regulations, 2011 CFR

2011-10-01

... DMU locomotive or an MU locomotive, equipped with a microprocessor-based event recorder that includes...) A microprocessor-based event recorder with a self-monitoring feature equipped to verify that all...

77 FR 22384 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-13

... passive, microprocessor-based device which includes a starter interrupt function, transponder key and a.... Porsche stated that the antitheft system consists of two major subsystems: a microprocessor-based...

77 FR 30048 - Petition for Waiver of Compliance

Federal Register 2010, 2011, 2012, 2013, 2014

2012-05-21

... locking; and 236.381, Traffic locking on vital microprocessor-based systems. MNCW proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative...

Maxi CAI with a Micro.

ERIC Educational Resources Information Center

Gerhold, George; And Others

This paper describes an effective microprocessor-based CAI system which has been repeatedly tested by a large number of students and edited accordingly. Tasks not suitable for microprocessor based systems (authoring, testing, and debugging) were handled on larger multi-terminal systems. This approach requires that the CAI language used on the…

Nonanalytic function generation routines for 16-bit microprocessors

NASA Technical Reports Server (NTRS)

Soeder, J. F.; Shaufl, M.

1980-01-01

Interpolation techniques for three types (univariate, bivariate, and map) of nonanalytic functions are described. These interpolation techniques are then implemented in scaled fraction arithmetic on a representative 16 bit microprocessor. A FORTRAN program is described that facilitates the scaling, documentation, and organization of data for use by these routines. Listings of all these programs are included in an appendix.

Pupillometry, a bioengineering overview

NASA Technical Reports Server (NTRS)

Myers, G.; Anchetta, J.; Hannaford, B.; Peng, P.; Sherman, K.; Stark, L.; Sun, F.; Usui, S.

1981-01-01

The pupillary control system is examined using a microprocessor based integrative pupillometer. The real time software functions of the microprocessor include: data collection, stimulus generation and area to diameter conversion. Results of an analysis of linear and nonlinear phenomena are presented.

The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

DTIC Science & Technology

2017-09-01

parallel, randomized, controlled clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power, will...Department of the Army position, policy or decision unless so designated by other documentation. CONTRACTING ORGANIZATION: University of Tennessee

Manufacturing Methods and Technology for Digital Fault Isolation of Hybrid Microelectronic Assemblies.

DTIC Science & Technology

1982-03-01

Aircraft Company ARECAaSOENT CSR Ground Systems Group Task 007 Fullerton, California 92634 Project No. R1023 I$. =OTRS4.IWmOr SP NAnE lAD ABDASE it. REPORT...HMA feed mechanism, multiple type test sockets or adapters, and a localized UUT vessel for functional tests at temperature. The engineering model AP...test excluding (deactivated) microprocessor. * Models UUT and test adapter as a ROM. Independent latches or registers from interconnecting ports to

A programmable heater control circuit for spacecraft

NASA Technical Reports Server (NTRS)

Nguyen, D. D.; Owen, J. W.; Smith, D. A.; Lewter, W. J.

1994-01-01

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Test report for single event effects of the 80386DX microprocessor

NASA Technical Reports Server (NTRS)

Watson, R. Kevin; Schwartz, Harvey R.; Nichols, Donald K.

1993-01-01

The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2011 CFR

2011-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2013 CFR

2013-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2014 CFR

2014-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2012 CFR

2012-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

Code of Federal Regulations, 2010 CFR

2010-10-01

... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

Briefing: Microprocessors.

ERIC Educational Resources Information Center

Standing, Roy A.

1982-01-01

Reviews the basic concepts and technology behind the functions computers perform, describes the miniaturization of computer components, discusses the development of the microprocessor and the microcomputer, and makes projections concerning the future of the microcomputer market. Information is provided on the features, costs, and manufacturers of…

The Single Event Effect Characteristics of the 486-DX4 Microprocessor

NASA Technical Reports Server (NTRS)

Kouba, Coy; Choi, Gwan

1996-01-01

This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

Evaluation of function, performance, and preference as transfemoral amputees transition from mechanical to microprocessor control of the prosthetic knee.

PubMed

Hafner, Brian J; Willingham, Laura L; Buell, Noelle C; Allyn, Katheryn J; Smith, Douglas G

2007-02-01

To evaluate differences in function, performance, and preference between mechanical and microprocessor prosthetic knee control technologies. A-B-A-B reversal design. Home, community, and laboratory environments. Twenty-one unilateral, transfemoral amputees. Mechanical control prosthetic knee versus microprocessor control prosthetic knee (Otto Bock C-Leg). Stair rating, hill rating and time, obstacle course time, divided attention task accuracy and time, Amputee Mobility Predictor score, step activity, Prosthesis Evaluation Questionnaire score, Medical Outcomes Study 36-Item Short-Form Health Survey score, self-reported frequency of stumbles and falls, and self-reported concentration required for ambulation. Stair descent score, hill descent time, and hill sound-side step length showed significant (P<.01) improvement with the C-Leg. Users reported a significant (P<.05) decrease in frequency of stumbles and falls, frustration with falling, and difficulty in multitasking while using the microprocessor knee. Subject satisfaction with the C-Leg was significantly (P<.001) greater than the mechanical control prosthesis. The study population showed improved performance when negotiating stairs and hills, reduced frequency of stumbling and falling, and a preference for the microprocessor control C-Leg as compared with the mechanical control prosthetic knee.

Miniature penetrator (MinPen) acceleration recorder development test

DOE Office of Scientific and Technical Information (OSTI.GOV)

Franco, R.J.; Platzbecker, M.R.

1998-08-01

The Telemetry Technology Development Department at Sandia National Laboratories actively develops and tests acceleration recorders for penetrating weapons. This new acceleration recorder (MinPen) utilizes a microprocessor-based architecture for operational flexibility while maintaining electronics and packaging techniques developed over years of penetrator testing. MinPen has been demonstrated to function in shock environments up to 20,000 Gs. The MinPen instrumentation development has resulted in a rugged, versatile, miniature acceleration recorder and is a valuable tool for penetrator testing in a wide range of applications.

A Career in Test and Evaluation: Reflections and Observations

DTIC Science & Technology

1998-01-01

can also evaluate a wide variety of flares and see how effective they are as countermeasures. Much of the develop- ment of the Stinger reprogrammable ...and advanced polymers. Modern materials coming out of DoD research are found in diesel and gasoline powered automobiles , sporting goods, medical...scenario issue. One of the functions of and stinger reprogrammable microprocessor developmental testing is to expand and missile or over-the-horizon

Orbit determination software development for microprocessor based systems: Evaluation and recommendations

NASA Technical Reports Server (NTRS)

Shenitz, C. M.; Mcgarry, F. E.; Tasaki, K. K.

1980-01-01

A guide is presented for National Aeronautics and Space Administration management personnel who stand to benefit from the lessons learned in developing microprocessor-based flight dynamics software systems. The essential functional characteristics of microprocessors are presented. The relevant areas of system support software are examined, as are the distinguishing characteristics of flight dynamics software. Design examples are provided to illustrate the major points presented, and actual development experience obtained in this area is provided as evidence to support the conclusions reached.

The Microprocessor controls the activity of mammalian retrotransposons

PubMed Central

Heras, Sara R.; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L.; Cáceres, Javier F.

2013-01-01

More than half of the human genome is made of Transposable Elements. Their ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human LINE-1 (Long INterspersed Element 1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons acting as a defender of human genome integrity. PMID:23995758

The Microprocessor controls the activity of mammalian retrotransposons.

PubMed

Heras, Sara R; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L; Cáceres, Javier F

2013-10-01

More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons and a defender of human genome integrity.

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape.

PubMed

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem-loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis

PubMed Central

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2016-01-01

Background: There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. Objectives: The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Study design: Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Methods: Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. Results: The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation (p = .001), paretic limb health (p = .04), sounds (p = .02), and well-being (p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. Conclusion: The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety. PMID:27151648

Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

PubMed Central

Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

2018-01-01

MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed. PMID:29922322

Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis.

PubMed

Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

2017-02-01

There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation ( p = .001), paretic limb health ( p = .04), sounds ( p = .02), and well-being ( p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety.

Inhibition of Microprocessor Function during the Activation of the Type I Interferon Response.

PubMed

Witteveldt, Jeroen; Ivens, Alasdair; Macias, Sara

2018-06-12

Type I interferons (IFNs) are central components of the antiviral response. Most cell types respond to viral infections by secreting IFNs, but the mechanisms that regulate correct expression of these cytokines are not completely understood. Here, we show that activation of the type I IFN response regulates the expression of miRNAs in a post-transcriptional manner. Activation of IFN expression alters the binding of the Microprocessor complex to pri-miRNAs, reducing its processing rate and thus leading to decreased levels of a subset of mature miRNAs in an IRF3-dependent manner. The rescue of Microprocessor function during the antiviral response downregulates the levels of IFN-β and IFN-stimulated genes. All these findings support a model by which the inhibition of Microprocessor activity is an essential step to induce a robust type I IFN response in mammalian cells. Copyright © 2018 The Author(s). Published by Elsevier Inc. All rights reserved.

Microprocessor tester for the treat upgrade reactor trip system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lenkszus, F.R.; Bucher, R.G.

1984-01-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety systemmore » is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations.« less

Variable-thermoinsulation garments with a microprocessor temperature controller.

PubMed

Kurczewska, Agnieszka; Leánikowski, Jacek

2008-01-01

This paper presents the concept of active variable thermoinsulation clothing for users working in low temperatures. Those garments contain heating inserts regulated by a microprocessor temperature controller. This paper also presents the results of tests carried out on the newly designed garments.

The formal verification of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does.

A central microprocessor controlled electrical storage heating system

NASA Astrophysics Data System (ADS)

Horstmann, H.

1980-12-01

The use of a microprocessor to control the reloading of electrical storage heaters not only during the night, but whenever the electrical grid is cycled down, was tested. The test setup, used to control a total of about 10 MW installed storage heating in 96 dwellings, is described. It is demonstrated that additional consumers can be connected to the system without demand for more power stations.

Establishment of cells to monitor Microprocessor through fusion genes of microRNA and GFP

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsutsui, Motomu; Hasegawa, Hitoki; Adachi, Koichi

Microprocessor, the complex of Drosha and DGCR8, promotes the processing of primary microRNA to precursor microRNA, which is a crucial step for microRNA maturation. So far, no convenient assay systems have been developed for observing this step in vivo. Here we report the establishment of highly sensitive cellular systems where we can visually monitor the function of Microprocessor. During a series of screening of transfectants with fusion genes of the EGFP cDNA and primary microRNA genes, we have obtained certain cell lines where introduction of siRNA against DGCR8 or Drosha strikingly augments GFP signals. In contrast, these cells have notmore » responded to Dicer siRNA; thus they have a unique character that GFP signals should be negatively and specifically correlated to the action of Microprocessor among biogenesis of microRNA. These cell lines can be useful tools for real-time analysis of Microprocessor action in vivo and identifying its novel modulators.« less

A microprocessor application to a strapdown laser gyro navigator

NASA Technical Reports Server (NTRS)

Giardina, C.; Luxford, E.

1980-01-01

The replacement of analog circuit control loops for laser gyros (path length control, cross axis temperature compensation loops, dither servo and current regulators) with digital filters residing in microcomputers is addressed. In addition to the control loops, a discussion is given on applying the microprocessor hardware to compensation for coning and skulling motion where simple algorithms are processed at high speeds to compensate component output data (digital pulses) for linear and angular vibration motions. Highlights are given on the methodology and system approaches used in replacing differential equations describing the analog system in terms of the mechanized difference equations of the microprocessor. Standard one for one frequency domain techniques are employed in replacing analog transfer functions by their transform counterparts. Direct digital design techniques are also discussed along with their associated benefits. Time and memory loading analyses are also summarized, as well as signal and microprocessor architecture. Trade offs in algorithm, mechanization, time/memory loading, accuracy, and microprocessor architecture are also given.

Instruction-Level Characterization of Scientific Computing Applications Using Hardware Performance Counters

DOE Office of Scientific and Technical Information (OSTI.GOV)

Luo, Y.; Cameron, K.W.

1998-11-24

Workload characterization has been proven an essential tool to architecture design and performance evaluation in both scientific and commercial computing areas. Traditional workload characterization techniques include FLOPS rate, cache miss ratios, CPI (cycles per instruction or IPC, instructions per cycle) etc. With the complexity of sophisticated modern superscalar microprocessors, these traditional characterization techniques are not powerful enough to pinpoint the performance bottleneck of an application on a specific microprocessor. They are also incapable of immediately demonstrating the potential performance benefit of any architectural or functional improvement in a new processor design. To solve these problems, many people rely on simulators,more » which have substantial constraints especially on large-scale scientific computing applications. This paper presents a new technique of characterizing applications at the instruction level using hardware performance counters. It has the advantage of collecting instruction-level characteristics in a few runs virtually without overhead or slowdown. A variety of instruction counts can be utilized to calculate some average abstract workload parameters corresponding to microprocessor pipelines or functional units. Based on the microprocessor architectural constraints and these calculated abstract parameters, the architectural performance bottleneck for a specific application can be estimated. In particular, the analysis results can provide some insight to the problem that only a small percentage of processor peak performance can be achieved even for many very cache-friendly codes. Meanwhile, the bottleneck estimation can provide suggestions about viable architectural/functional improvement for certain workloads. Eventually, these abstract parameters can lead to the creation of an analytical microprocessor pipeline model and memory hierarchy model.« less

A microprocessor-based table lookup approach for magnetic bearing linearization

NASA Technical Reports Server (NTRS)

Groom, N. J.; Miller, J. B.

1981-01-01

An approach for producing a linear transfer characteristic between force command and force output of a magnetic bearing actuator without flux biasing is presented. The approach is microprocessor based and uses a table lookup to generate drive signals for the magnetic bearing power driver. An experimental test setup used to demonstrate the feasibility of the approach is described, and test results are presented. The test setup contains bearing elements similar to those used in a laboratory model annular momentum control device.

Advanced microprocessor based power protection system using artificial neural network techniques

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Z.; Kalam, A.; Zayegh, A.

This paper describes an intelligent embedded microprocessor based system for fault classification in power system protection system using advanced 32-bit microprocessor technology. The paper demonstrates the development of protective relay to provide overcurrent protection schemes for fault detection. It also describes a method for power fault classification in three-phase system based on the use of neural network technology. The proposed design is implemented and tested on a single line three phase power system in power laboratory. Both the hardware and software development are described in detail.

Gait and balance of transfemoral amputees using passive mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, K R; Levine, J A; Brey, R H; Iverson, B K; McCrady, S K; Padgett, D J; Joyner, M J

2007-10-01

Microprocessor-controlled knee joints appeared on the market a decade ago. These joints are more sophisticated and more expensive than mechanical ones. The literature is contradictory regarding changes in gait and balance when using these sophisticated devices. This study employed a crossover design to assess the comparative performance of a passive mechanical knee prosthesis compared to a microprocessor-controlled knee joint in 15 subjects with an above-knee amputation. Objective measurements of gait and balance were obtained. Subjects demonstrated significantly improved gait characteristics after receiving the microprocessor-controlled prosthetic knee joint (p<0.01). Improvements in gait were a transition from a hyperextended knee to a flexed knee during loading response which resulted in a change from an internal knee flexor moment to a knee extensor moment. The participants' balance also improved (p<0.01). All conditions of the Sensory Organization Test (SOT) demonstrated improvements in equilibrium score. The composite score also increased. Transfemoral amputees using a microprocessor-controlled knee have significant improvements in gait and balance.

Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.; Bashkow, T.

1978-01-01

The position of an emergency transmitter may be determined by measuring the Doppler shift of the distress signal as received by an orbiting satellite. This requires the computation of an initial estimate and refinement of this estimate through an iterative, nonlinear, least squares estimation. A version of the algorithm was implemented and tested by locating a transmitter on the premises and obtaining observations from a satellite. The computer used was an IBM 360/95. The position was determined within the desired 10 km radius accuracy. The feasibility of performing the same task in real time using microprocessor technology, was determined. The least squares algorithm was implemented on an Intel 8080 microprocessor. The results indicate that a microprocessor can easily match the IBM implementation in accuracy and be performed inside the time limitations set.

Development of a patch type embedded cardiac function monitoring system using dual microprocessor for arrhythmia detection in heart disease patient.

PubMed

Jang, Yongwon; Noh, Hyung Wook; Lee, I B; Jung, Ji-Wook; Song, Yoonseon; Lee, Sooyeul; Kim, Seunghwan

2012-01-01

A patch type embedded cardiac function monitoring system was developed to detect arrhythmias such as PVC (Premature Ventricular Contraction), pause, ventricular fibrillation, and tachy/bradycardia. The overall system is composed of a main module including a dual processor and a Bluetooth telecommunication module. The dual microprocessor strategy minimizes power consumption and size, and guarantees the resources of embedded software programs. The developed software was verified with standard DB, and showed good performance.

Concept for a power system controller for large space electrical power systems

NASA Technical Reports Server (NTRS)

Lollar, L. F.; Lanier, J. R., Jr.; Graves, J. R.

1981-01-01

The development of technology for a fail-operatonal power system controller (PSC) utilizing microprocessor technology for managing the distribution and power processor subsystems of a large multi-kW space electrical power system is discussed. The specific functions which must be performed by the PSC, the best microprocessor available to do the job, and the feasibility, cost savings, and applications of a PSC were determined. A limited function breadboard version of a PSC was developed to demonstrate the concept and potential cost savings.

The quality of life analysis of knee prosthesis with complete microprocessor control in trans-femoral amputees.

PubMed

Saglam, Yavuz; Gulenc, Baris; Birisik, Fevzi; Ersen, Ali; Yilmaz Yalcinkaya, Ebru; Yazicioglu, Onder

2017-12-01

The aim of this study was to analyze the patient demographics, etiology of limb loss as well as reporting SF-36 scores for microprocessor prosthesis users in Turkish population. We reviewed 72 patients (61 male and 11 female; mean age: 37.7 ± 10.7) with uni-lateral, above knee amputation and a history of regular and microprocessor prosthesis use. All patients were called back for a last follow-up and they were asked to fill a self-administered general health status questionnaire (SF-36). According to the SF-36 results; physical component score (PCS) score was 46 ± 7.3 and mental components summary (MCS) score was 46.5 ± 9.1. These scores have statistical similarity with Turkish healthy controls, except SF (social functioning) sub-dimension. PCS score for women microprocessor users were significantly lower than men (43.3 vs. 48.7, p = 0.03), but MCS scores were similar in between genders (46 vs. 48.2, p = 0.13). Conventional prostheses usage time was positively correlated with physical function (PF) scores (r = 0.322, p = 0.010). Microprocessor prosthesis usage time was negatively correlated with role limitations due to emotional problem (RE) scores (r = -0,313, p = 0.009). The quality of life surveys were showed that the loss of an extremity have higher physical and psychological impact on women's physical scores. Overall, SF-36 results were similar in microprocessor using amputee's and Turkish normal controls. Level IV, therapeutic study. Copyright © 2017 Turkish Association of Orthopaedics and Traumatology. Production and hosting by Elsevier B.V. All rights reserved.

Energy expenditure and activity of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, Kenton R; Levine, James A; Brey, Robert H; McCrady, Shelly K; Padgett, Denny J; Joyner, Michael J

2008-07-01

To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Repeated-measures design to evaluate comparative functional outcomes. Exercise physiology laboratory and community free-living environment. Subjects (N=15; 12 men, 3 women; age, 42+/-9 y; range, 26-57 y) with transfemoral amputation. Research participants were long-term users of a mechanical prosthesis (20+/-10 y as an amputee; range, 3-36 y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18+/-8 wk) before being retested. Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Subjects demonstrated significantly increased physical activity-related energy expenditure levels in the participant's free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life.

Dynamic characterization and microprocessor control of the NASA/UVA proof mass actuator

NASA Technical Reports Server (NTRS)

Zimmerman, D. C.; Inman, D. J.; Horner, G. C.

1984-01-01

The self-contained electromagnetic-reaction-type force-actuator system developed by NASA/UVA for the verification of spacecraft-structure vibration-control laws is characterized and demonstrated. The device is controlled by a dedicated microprocessor and has dynamic characteristics determined by Fourier analysis. Test data on a cantilevered beam are shown.

Scaling theory for information networks.

PubMed

Moses, Melanie E; Forrest, Stephanie; Davis, Alan L; Lodder, Mike A; Brown, James H

2008-12-06

Networks distribute energy, materials and information to the components of a variety of natural and human-engineered systems, including organisms, brains, the Internet and microprocessors. Distribution networks enable the integrated and coordinated functioning of these systems, and they also constrain their design. The similar hierarchical branching networks observed in organisms and microprocessors are striking, given that the structure of organisms has evolved via natural selection, while microprocessors are designed by engineers. Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to an organism is proportional to its mass raised to the 3/4 power. We show that computational systems are also characterized by nonlinear network scaling and use MST principles to characterize how information networks scale, focusing on how MST predicts properties of clock distribution networks in microprocessors. The MST equations are modified to account for variation in the size and density of transistors and terminal wires in microprocessors. Based on the scaling of the clock distribution network, we predict a set of trade-offs and performance properties that scale with chip size and the number of transistors. However, there are systematic deviations between power requirements on microprocessors and predictions derived directly from MST. These deviations are addressed by augmenting the model to account for decentralized flow in some microprocessor networks (e.g. in logic networks). More generally, we hypothesize a set of constraints between the size, power and performance of networked information systems including transistors on chips, hosts on the Internet and neurons in the brain.

Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

NASA Technical Reports Server (NTRS)

Belcastro, C. M.

1984-01-01

Advanced composite aircraft designs include fault-tolerant computer-based digital control systems with thigh reliability requirements for adverse as well as optimum operating environments. Since aircraft penetrate intense electromagnetic fields during thunderstorms, onboard computer systems maya be subjected to field-induced transient voltages and currents resulting in functional error modes which are collectively referred to as digital system upset. A methodology was developed for assessing the upset susceptibility of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general-purpose microprocessor were studied via tests which involved the random input of analog transients which model lightning-induced signals onto interface lines of an 8080-based microcomputer from which upset error data were recorded. The application of Markov modeling to upset susceptibility estimation is discussed and a stochastic model development.

A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

PubMed

Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

2011-10-01

In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

Virtual Instrument Simulator for CERES

NASA Technical Reports Server (NTRS)

Chapman, John J.

1997-01-01

A benchtop virtual instrument simulator for CERES (Clouds and the Earth's Radiant Energy System) has been built at NASA, Langley Research Center in Hampton, VA. The CERES instruments will fly on several earth orbiting platforms notably NASDA's Tropical Rainfall Measurement Mission (TRMM) and NASA's Earth Observing System (EOS) satellites. CERES measures top of the atmosphere radiative fluxes using microprocessor controlled scanning radiometers. The CERES Virtual Instrument Simulator consists of electronic circuitry identical to the flight unit's twin microprocessors and telemetry interface to the supporting spacecraft electronics and two personal computers (PC) connected to the I/O ports that control azimuth and elevation gimbals. Software consists of the unmodified TRW developed Flight Code and Ground Support Software which serves as the instrument monitor and NASA/TRW developed engineering models of the scanners. The CERES Instrument Simulator will serve as a testbed for testing of custom instrument commands intended to solve in-flight anomalies of the instruments which could arise during the CERES mission. One of the supporting computers supports the telemetry display which monitors the simulator microprocessors during the development and testing of custom instrument commands. The CERES engineering development software models have been modified to provide a virtual instrument running on a second supporting computer linked in real time to the instrument flight microprocessor control ports. The CERES Instrument Simulator will be used to verify memory uploads by the CERES Flight Operations TEAM at NASA. Plots of the virtual scanner models match the actual instrument scan plots. A high speed logic analyzer has been used to track the performance of the flight microprocessor. The concept of using an identical but non-flight qualified microprocessor and electronics ensemble linked to a virtual instrument with identical system software affords a relatively inexpensive simulation system capable of high fidelity.

Control methodologies for large space structures

NASA Technical Reports Server (NTRS)

Mcree, G. J.; Altonji, E.

1984-01-01

The objectives of this research were to develop techniques of controlling a dc-motor driven flywheel which would apply torque to the structure to which it was mounted. The motor control system was to be implemented using a microprocessor based controller. The purpose of the torque applied by this system was to dampen oscillations of the structure to which it was mounted. Before the work was terminated due to the unavailability of equipment, a system was developed and partially tested which would provide tight control of the flywheel velocity when it received a velocity command in the form of a voltage. The procedure followed in this development was to first model the motor and flywheel system on an analog computer. Prior to the time the microprocessor development system was available, an analog control loop was replaced by the microprocessor and the system was partially tested.

Energy Expenditure and Activity of Transfemoral Amputees Using Mechanical and Microprocessor-Controlled Prosthetic Knees

PubMed Central

Kaufman, Kenton R.; Levine, James A.; Brey, Robert H.; McCrady, Shelly K.; Padgett, Denny J.; Joyner, Michael J.

2009-01-01

Objective To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Design Repeated-measures design to evaluate comparative functional outcomes. Setting Exercise physiology laboratory and community free-living environment. Participants Subjects (N=15; 12 men, 3 women; age, 42±9y; range, 26 –57y) with transfemoral amputation. Intervention Research participants were long-term users of a mechanical prosthesis (20±10y as an amputee; range, 3–36y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18±8wk) before being retested. Main Outcome Measures Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Results Subjects demonstrated significantly increased physical activity–related energy expenditure levels in the participant’s free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). Conclusions People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life. PMID:18586142

Demonstration Advanced Avionics System (DAAS)

NASA Technical Reports Server (NTRS)

1982-01-01

The feasibility of developing an integrated avionics system suitable for general aviation was determined. A design of reliable integrated avionics which provides expanded functional capability that significantly enhances the utility and safety of general aviation at a cost commensurate with the general aviation market was developed. The use of a data bus, microprocessors, electronic displays and data entry devices, and improved function capabilities were emphasized. An avionics system capable of evaluating the most critical and promising elements of an integrated system was designed, built and flight tested in a twin engine general aviation aircraft.

Bristol Ridge: A 28-nm $$\\times$$ 86 Performance-Enhanced Microprocessor Through System Power Management

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sundaram, Sriram; Grenat, Aaron; Naffziger, Samuel

Power management techniques can be effective at extracting more performance and energy efficiency out of mature systems on chip (SoCs). For instance, the peak performance of microprocessors is often limited by worst case technology (Vmax), infrastructure (thermal/electrical), and microprocessor usage assumptions. Performance/watt of microprocessors also typically suffers from guard bands associated with the test and binning processes as well as worst case aging/lifetime degradation. Similarly, on multicore processors, shared voltage rails tend to limit the peak performance achievable in low thread count workloads. In this paper, we describe five power management techniques that maximize the per-part performance under the before-mentionedmore » constraints. Using these techniques, we demonstrate a net performance increase of up to 15% depending on the application and TDP of the SoC, implemented on 'Bristol Ridge,' a 28-nm CMOS, dual-core x 86 accelerated processing unit.« less

Concept report: Microprocessor control of electrical power system

NASA Technical Reports Server (NTRS)

Perry, E.

1977-01-01

An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

Implementation of the Sun Position Calculation in the PDC-1 Control Microprocessor

NASA Technical Reports Server (NTRS)

Stallkamp, J. A.

1984-01-01

The several computational approaches to providing the local azimuth and elevation angles of the Sun as a function of local time and then the utilization of the most appropriate method in the PDC-1 microprocessor are presented. The full algorithm, the FORTRAN form, is felt to be very useful in any kind or size of computer. It was used in the PDC-1 unit to generate efficient code for the microprocessor with its floating point arithmetic chip. The balance of the presentation consists of a brief discussion of the tracking requirements for PPDC-1, the planetary motion equations from the first to the final version, and the local azimuth-elevation geometry.

Distributed Microprocessor Automation Network for Synthesizing Radiotracers Used in Positron Emission Tomography [PET

DOE R&D Accomplishments Database

Russell, J. A. G.; Alexoff, D. L.; Wolf, A. P.

1984-09-01

This presentation describes an evolving distributed microprocessor network for automating the routine production synthesis of radiotracers used in Positron Emission Tomography. We first present a brief overview of the PET method for measuring biological function, and then outline the general procedure for producing a radiotracer. The paper identifies several reasons for our automating the syntheses of these compounds. There is a description of the distributed microprocessor network architecture chosen and the rationale for that choice. Finally, we speculate about how this network may be exploited to extend the power of the PET method from the large university or National Laboratory to the biomedical research and clinical community at large. (DT)

Method and apparatus for transfer function simulator for testing complex systems

NASA Technical Reports Server (NTRS)

Kavaya, M. J. (Inventor)

1985-01-01

A method and apparatus for testing the operation of a complex stabilization circuit in a closed loop system is presented. The method is comprised of a programmed analog or digital computing system for implementing the transfer function of a load thereby providing a predictable load. The digital computing system employs a table stored in a microprocessor in which precomputed values of the load transfer function are stored for values of input signal from the stabilization circuit over the range of interest. This technique may be used not only for isolating faults in the stabilization circuit, but also for analyzing a fault in a faulty load by so varying parameters of the computing system as to simulate operation of the actual load with the fault.

Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

PubMed Central

Rhee, Minsoung

2010-01-01

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

Hardware Fault Simulator for Microprocessors

NASA Technical Reports Server (NTRS)

Hess, L. M.; Timoc, C. C.

1983-01-01

Breadboarded circuit is faster and more thorough than software simulator. Elementary fault simulator for AND gate uses three gates and shaft register to simulate stuck-at-one or stuck-at-zero conditions at inputs and output. Experimental results showed hardware fault simulator for microprocessor gave faster results than software simulator, by two orders of magnitude, with one test being applied every 4 microseconds.

New techniques for test development for tactical auto-pilots using microprocessors

NASA Astrophysics Data System (ADS)

Shemeta, E. H.

1980-07-01

This paper reports on a demonstration of the application of the method to generate system level tests for a typical tactical missile autopilot. The test algorithms are based on the autopilot control law. When loaded on the tester with appropriate control information, the complete autopilot is tested to establish if the specified control law requirements are met. Thus, the test procedure not only checks to see if the hardware is functional, but also checks the operational software. The technique also uses a 'learning' mode to allow minor timing or functional deviations from the expected responses to be incorporated in the test procedures. A potential application of this test development technique is the extraction of production test data for the various subassemblies. The technique will 'learn' the input-output patterns forming the basis for developement and production tests. If successful, these new techniques should allow the test development process to keep pace with semiconductor progress.

Designs and performance of three new microprocessor-controlled knee joints.

PubMed

Thiele, Julius; Schöllig, Christina; Bellmann, Malte; Kraft, Marc

2018-02-09

A crossover design study with a small group of subjects was used to evaluate the performance of three microprocessor-controlled exoprosthetic knee joints (MPKs): C-Leg 4, Plié 3 and Rheo Knee 3. Given that the mechanical designs and control algorithms of the joints determine the user outcome, the influence of these inherent differences on the functional characteristics was investigated in this study. The knee joints were evaluated during level-ground walking at different velocities in a motion analysis laboratory. Additionally, technical analyses using patents, technical documentations and X-ray computed tomography (CT) for each knee joint were performed. The technical analyses showed that only C-Leg 4 and Rheo Knee 3 allow microprocessor-controlled adaptation of the joint resistances for different gait velocities. Furthermore, Plié 3 is not able to provide stance extension damping. The biomechanical results showed that only if a knee joint adapts flexion and extension resistances by the microprocessor all known advantages of MPKs can become apparent. But not all users may benefit from the examined functions: e.g. a good accommodation to fast walking speeds or comfortable stance phase flexion. Hence, a detailed comparison of user demands and performance of the designated knee joint is mandatory to ensure a maximum in user outcome.

Rapidly quantifying the relative distention of a human bladder

NASA Technical Reports Server (NTRS)

Companion, John A. (Inventor); Heyman, Joseph S. (Inventor); Mineo, Beth A. (Inventor); Cavalier, Albert R. (Inventor); Blalock, Travis N. (Inventor)

1991-01-01

A device and method was developed to rapidly quantify the relative distention of the bladder of a human subject. An ultrasonic transducer is positioned on the human subject near the bladder. A microprocessor controlled pulser excites the transducer by sending an acoustic wave into the human subject. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer where it is received, amplified, and processed by the receiver. The resulting signal is digitized by an analog to digital converter, controlled by the microprocessor again, and is stored in data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy. Based on programmed scientific measurements and the human subject's past history as contained in program memory, the microprocessor sends out a signal to turn on any or all of the available alarms. The alarm system includes and audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

The comparison of transfemoral amputees using mechanical and microprocessor- controlled prosthetic knee under different walking speeds: A randomized cross-over trial.

PubMed

Cao, Wujing; Yu, Hongliu; Zhao, Weiliang; Meng, Qiaoling; Chen, Wenming

2018-04-20

The microprocessor-controlled prosthetic knees have been introduced to transfemoral amputees due to advances in biomedical engineering. A body of scientific literature has shown that the microprocessor-controlled prosthetic knees improve the gait and functional abilities of persons with transfemoral amputation. The aim of this study was to propose a new microprocessor-controlled prosthetic knee (MPK) and compare it with non-microprocessor-controlled prosthetic knees (NMPKs) under different walking speeds. The microprocessor-controlled prosthetic knee (i-KNEE) with hydraulic damper was developed. The comfortable self-selected walking speeds of 12 subjects with i-KNEE and NMPK were obtained. The maximum swing flexion knee angle and gait symmetry were compared in i-KNEE and NMPK condition. The comfortable self-selected walking speeds of some subjects were higher with i-KNEE while some were not. There was no significant difference in comfortable self-selected walking speed between the i-KNEE and the NMPK condition (P= 0.138). The peak prosthetic knee flexion during swing in the i-KNEE condition was between sixty and seventy degree under any walking speed. In the NMPK condition, the maximum swing flexion knee angle changed significantly. And it increased with walking speed. There is no significant difference in knee kinematic symmetry when the subjects wear the i-KNEE or NMPK. The results of this study indicated that the new microprocessor-controlled prosthetic knee was suitable for transfemoral amputees. The maximum swing flexion knee angle under different walking speeds showed different properties in the NMPK and i-KNEE condition. The i-KNEE was more adaptive to speed changes. There was little difference of comfortable self-selected walking speed between i-KNEE and NMPK condition.

Experience with custom processors in space flight applications

NASA Technical Reports Server (NTRS)

Fraeman, M. E.; Hayes, J. R.; Lohr, D. A.; Ballard, B. W.; Williams, R. L.; Henshaw, R. M.

1991-01-01

The Applied Physics Laboratory (APL) has developed a magnetometer instrument for a swedish satellite named Freja with launch scheduled for August 1992 on a Chinese Long March rocket. The magnetometer controller utilized a custom microprocessor designed at APL with the Genesil silicon compiler. The processor evolved from our experience with an older bit-slice design and two prior single chip efforts. The architecture of our microprocessor greatly lowered software development costs because it was optimized to provide an interactive and extensible programming environment hosted by the target hardware. Radiation tolerance of the microprocessor was also tested and was adequate for Freja's mission -- 20 kRad(Si) total dose and very infrequent latch-up and single event upset events.

Variable frequency microprocessor clock generator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Branson, C.N.

A microprocessor-based system is described comprising: a digital central microprocessor provided with a clock input and having a rate of operation determined by the frequency of a clock signal input thereto; memory means operably coupled to the central microprocessor for storing programs respectively including a plurality of instructions and addressable by the central microprocessor; peripheral device operably connected to the central microprocessor, the first peripheral device being addressable by the central microprocessor for control thereby; a system clock generator for generating a digital reference clock signal having a reference frequency rate; and frequency rate reduction circuit means connected between themore » clock generator and the clock input of the central microprocessor for selectively dividing the reference clock signal to generate a microprocessor clock signal as an input to the central microprocessor for clocking the central microprocessor.« less

DGCR8 HITS-CLIP reveals novel functions for the Microprocessor

PubMed Central

Macias, Sara; Plass, Mireya; Stajuda, Agata; Michlewski, Gracjan; Eyras, Eduardo; Cáceres, Javier F.

2012-01-01

The Drosha-DGCR8 complex (Microprocessor) is required for microRNA (miRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as the endonuclease. High-throughput sequencing and crosslinking immunoprecipitation (HITS-CLIP) was used to identify RNA targets of DGCR8 in human cells. Unexpectedly, miRNAs were not the most abundant targets. DGCR8-bound RNAs also comprised several hundred mRNAs as well as snoRNAs and long non-coding RNAs. We found that the Microprocessor controls the abundance of several mRNAs as well as of MALAT-1. By contrast, DGCR8-mediated cleavage of snoRNAs is independent of Drosha, suggesting the involvement of DGCR8 in cellular complexes with other endonucleases. Interestingly, binding of DGCR8 to cassette exons, acts as a novel mechanism to regulate the relative abundance of alternatively spliced isoforms. Collectively, these data provide new insights in the complex role of DGCR8 in controlling the fate of several classes of RNAs. PMID:22796965

A microprocessor tester for the treat upgrade reactor trip system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lenkszus, F.R.; Bucher, R.G.

1985-02-01

The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. To improve the analytical extrapolation of test results to full-size assembly bundles, the facility upgrade will increase the maximum size of the test bundle from 7 to 37 fuel pins. By creating a core convertor zone around the test location, the neutron spectrum incident on the test assembly will be hardened and the maximum energy deposited in the sample will be increased. In addition, a programmable Automated Reactor Control System (ARCS) willmore » permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety system is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations. A quantitative reliability analysis of the RTS shows that the unreliability, that is, the probability of failure, is acceptable for a 10 hour mission time or risk interval.« less

MicroShell Minimalist Shell for Xilinx Microprocessors

NASA Technical Reports Server (NTRS)

Werne, Thomas A.

2011-01-01

MicroShell is a lightweight shell environment for engineers and software developers working with embedded microprocessors in Xilinx FPGAs. (MicroShell has also been successfully ported to run on ARM Cortex-M1 microprocessors in Actel ProASIC3 FPGAs, but without project-integration support.) Micro Shell decreases the time spent performing initial tests of field-programmable gate array (FPGA) designs, simplifies running customizable one-time-only experiments, and provides a familiar-feeling command-line interface. The program comes with a collection of useful functions and enables the designer to add an unlimited number of custom commands, which are callable from the command-line. The commands are parameterizable (using the C-based command-line parameter idiom), so the designer can use one function to exercise hardware with different values. Also, since many hardware peripherals instantiated in FPGAs have reasonably simple register-mapped I/O interfaces, the engineer can edit and view hardware parameter settings at any time without stopping the processor. MicroShell comes with a set of support scripts that interface seamlessly with Xilinx's EDK tool. Adding an instance of MicroShell to a project is as simple as marking a check box in a library configuration dialog box and specifying a software project directory. The support scripts then examine the hardware design, build design-specific functions, conditionally include processor-specific functions, and complete the compilation process. For code-size constrained designs, most of the stock functionality can be excluded from the compiled library. When all of the configurable options are removed from the binary, MicroShell has an unoptimized memory footprint of about 4.8 kB and a size-optimized footprint of about 2.3 kB. Since MicroShell allows unfettered access to all processor-accessible memory locations, it is possible to perform live patching on a running system. This can be useful, for instance, if a bug is discovered in a routine but the system cannot be rebooted: Shell allows a skilled operator to directly edit the binary executable in memory. With some forethought, MicroShell code can be located in a different memory location from custom code, permitting the custom functionality to be overwritten at any time without stopping the controlling shell.

Report on phase 1 of the Microprocessor Seminar. [and associated large scale integration

NASA Technical Reports Server (NTRS)

1977-01-01

Proceedings of a seminar on microprocessors and associated large scale integrated (LSI) circuits are presented. The potential for commonality of device requirements, candidate processes and mechanisms for qualifying candidate LSI technologies for high reliability applications, and specifications for testing and testability were among the topics discussed. Various programs and tentative plans of the participating organizations in the development of high reliability LSI circuits are given.

Radiation Test Results for Common CubeSat Microcontrollers and Microprocessors

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Amrbar, Mehran; Vartanian, Sergeh

2015-01-01

SEL, SEU, and TID results are presented for microcontrollers and microprocessors of interest for small satellite systems such as the TI MSP430F1611, MSP430F1612 and MSP430FR5739, Microchip PIC24F256GA110 and dsPIC33FJ256GP710, Atmel AT91SAM9G20, and Intel Atom E620T, and the Qualcomm Snapdragon APQ8064.

Microprocessor-based cardiotachometer

NASA Technical Reports Server (NTRS)

Crosier, W. G.; Donaldson, J. A.

1981-01-01

Instrument operates reliably even with stress-test electrocardiogram (ECG) signals subject to noise, baseline wandering, and amplitude change. It records heart rate from preamplified, single-lead ECG input signal and produces digital and analog heart-rate outputs which are fed elsewhere. Analog hardware processes ECG input signal, producing 10-ms pulse for each heartbeat. Microprocessor analyzes resulting pulse train, identifying irregular heartbeats and maintaining stable output during lead switching. Easily modified computer program provides analysis.

Low-power circuits design for the wireless force measurement system of the total knee arthroplasty.

PubMed

Chen, Hong; Liu, Ming; Wan, Weiyi; Jia, Chen; Zhang, Chun; Wang, Zihua

2010-01-01

This paper proposes a novel wireless force measurement system for the Total Knee Arthroplasty (TKA) to improve the ligament balancing procedure during TKA. The force measurement system is comprised of a Wireless Force Measurement Spacer (WFMS) and the display part. They communicate with each other by the Radio Frequency (RF) signal. The WFMS is designed to measure the force between the WFMS and the femoral component of the artificial implants and to transmit the force data wirelessly by a low power transceiver. The display part demonstrates the force data in 3D images in real time. The WFMS composes of a sensors array, a Universal Transducer Interfaces (UTIs) array, a low-power sub-threshold microprocessor and a transceiver. The sub-threshold 8-bit microprocessor is taped out with 0.18 microm CMOS technology. The testing results of the microprocessor show that the leakage power of 46nW and the dynamic power of 385nW@165kHz are achieved with the operating voltage of 350 mV. The test results of the system are given and the errors of the system are analyzed. The results verified the reliability of the system. The future work is to design the microprocessor and a lower power transceiver within a single chip.

Space station propulsion technology

NASA Technical Reports Server (NTRS)

Briley, G. L.

1986-01-01

The progress on the Space Station Propulsion Technology Program is described. The objectives are to provide a demonstration of hydrogen/oxygen propulsion technology readiness for the Initial Operating Capability (IOC) space station application, specifically gaseous hydrogen/oxygen and warm hydrogen thruster concepts, and to establish a means for evolving from the IOC space station propulsion to that required to support and interface with advanced station functions. The evaluation of concepts was completed. The accumulator module of the test bed was completed and, with the microprocessor controller, delivered to NASA-MSFC. An oxygen/hydrogen thruster was modified for use with the test bed and successfully tested at mixture ratios from 4:1 to 8:1.

"Smart" Sensor Module

NASA Technical Reports Server (NTRS)

Mahajan, Ajay

2007-01-01

An assembly that contains a sensor, sensor-signal-conditioning circuitry, a sensor-readout analog-to-digital converter (ADC), data-storage circuitry, and a microprocessor that runs special-purpose software and communicates with one or more external computer(s) has been developed as a prototype of "smart" sensor modules for monitoring the integrity and functionality (the "health") of engineering systems. Although these modules are now being designed specifically for use on rocket-engine test stands, it is anticipated that they could also readily be designed to be incorporated into health-monitoring subsystems of such diverse engineering systems as spacecraft, aircraft, land vehicles, bridges, buildings, power plants, oilrigs, and defense installations. The figure is a simplified block diagram of the "smart" sensor module. The analog sensor readout signal is processed by the ADC, the digital output of which is fed to the microprocessor. By means of a standard RS-232 cable, the microprocessor is connected to a local personal computer (PC), from which software is downloaded into a randomaccess memory in the microprocessor. The local PC is also used to debug the software. Once the software is running, the local PC is disconnected and the module is controlled by, and all output data from the module are collected by, a remote PC via an Ethernet bus. Several smart sensor modules like this one could be connected to the same Ethernet bus and controlled by the single remote PC. The software running in the microprocessor includes driver programs for operation of the sensor, programs that implement self-assessment algorithms, programs that implement protocols for communication with the external computer( s), and programs that implement evolutionary methodologies to enable the module to improve its performance over time. The design of the module and of the health-monitoring system of which it is a part reflects the understanding that the main purpose of a health-monitoring system is to detect damage and, therefore, the health-monitoring system must be able to function effectively in the presence of damage and should be capable of distinguishing between damage to itself and damage to the system being monitored. A major benefit afforded by the self-assessment algorithms is that in the output of the module, the sensor data indicative of the health of the engineering system being monitored are coupled with a confidence factor that quantifies the degree of reliability of the data. Hence, the output includes information on the health of the sensor module itself in addition to information on the health of the engineering system being monitored.

A Systematic Methodology for Verifying Superscalar Microprocessors

NASA Technical Reports Server (NTRS)

Srivas, Mandayam; Hosabettu, Ravi; Gopalakrishnan, Ganesh

1999-01-01

We present a systematic approach to decompose and incrementally build the proof of correctness of pipelined microprocessors. The central idea is to construct the abstraction function by using completion functions, one per unfinished instruction, each of which specifies the effect (on the observables) of completing the instruction. In addition to avoiding the term size and case explosion problem that limits the pure flushing approach, our method helps localize errors, and also handles stages with interactive loops. The technique is illustrated on pipelined and superscalar pipelined implementations of a subset of the DLX architecture. It has also been applied to a processor with out-of-order execution.

A microprocessor-based automation test system for the experiment of the multi-stage compressor

NASA Astrophysics Data System (ADS)

Zhang, Huisheng; Lin, Chongping

1991-08-01

An automation test system that is controlled by the microprocessor and used in the multistage compressor experiment is described. Based on the analysis of the compressor experiment performances, a complete hardware system structure is set up. It is composed of a IBM PC/XT computer, a large scale sampled data system, the moving machine with three directions, the scanners, the digital instrumentation and some output devices. A program structure of real-time software system is described. The testing results show that this test system can take the measure of many parameter magnitudes in the blade row places and on a boundary layer in different states. The automatic extent and the accuracy of experiment is increased and the experimental cost is reduced.

Hardware math for the 6502 microprocessor

NASA Technical Reports Server (NTRS)

Kissel, R.; Currie, J.

1985-01-01

A floating-point arithmetic unit is described which is being used in the Ground Facility of Large Space Structures Control Verification (GF/LSSCV). The experiment uses two complete inertial measurement units and a set of three gimbal torquers in a closed loop to control the structural vibrations in a flexible test article (beam). A 6502 (8-bit) microprocessor controls four AMD 9511A floating-point arithmetic units to do all the computation in 20 milliseconds.

G-cueing microcontroller (a microprocessor application in simulators)

NASA Technical Reports Server (NTRS)

Horattas, C. G.

1980-01-01

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Microprocessor activity controls differential miRNA biogenesis In Vivo.

PubMed

Conrad, Thomas; Marsico, Annalisa; Gehre, Maja; Orom, Ulf Andersson

2014-10-23

In miRNA biogenesis, pri-miRNA transcripts are converted into pre-miRNA hairpins. The in vivo properties of this process remain enigmatic. Here, we determine in vivo transcriptome-wide pri-miRNA processing using next-generation sequencing of chromatin-associated pri-miRNAs. We identify a distinctive Microprocessor signature in the transcriptome profile from which efficiency of the endogenous processing event can be accurately quantified. This analysis reveals differential susceptibility to Microprocessor cleavage as a key regulatory step in miRNA biogenesis. Processing is highly variable among pri-miRNAs and a better predictor of miRNA abundance than primary transcription itself. Processing is also largely stable across three cell lines, suggesting a major contribution of sequence determinants. On the basis of differential processing efficiencies, we define functionality for short sequence features adjacent to the pre-miRNA hairpin. In conclusion, we identify Microprocessor as the main hub for diversified miRNA output and suggest a role for uncoupling miRNA biogenesis from host gene expression. Copyright © 2014 The Authors. Published by Elsevier Inc. All rights reserved.

Microprocessor depends on hemin to recognize the apical loop of primary microRNA

PubMed Central

Park, Joha; Dang, Thi Lieu; Choi, Yeon-Gil; Kim, V Narry

2018-01-01

Abstract Microprocessor, which consists of a ribonuclease III DROSHA and its cofactor DGCR8, initiates microRNA (miRNA) maturation by cleaving primary miRNA transcripts (pri-miRNAs). We recently demonstrated that the DGCR8 dimer recognizes the apical elements of pri-miRNAs, including the UGU motif, to accurately locate and orient Microprocessor on pri-miRNAs. However, the mechanism underlying the selective RNA binding remains unknown. In this study, we find that hemin, a ferric ion-containing porphyrin, enhances the specific interaction between the apical UGU motif and the DGCR8 dimer, allowing Microprocessor to achieve high efficiency and fidelity of pri-miRNA processing in vitro. Furthermore, by generating a DGCR8 mutant cell line and carrying out rescue experiments, we discover that hemin preferentially stimulates the expression of miRNAs possessing the UGU motif, thereby conferring differential regulation of miRNA maturation. Our findings reveal the molecular action mechanism of hemin in pri-miRNA processing and establish a novel function of hemin in inducing specific RNA-protein interaction. PMID:29750274

Microprocessor depends on hemin to recognize the apical loop of primary microRNA.

PubMed

Nguyen, Tuan Anh; Park, Joha; Dang, Thi Lieu; Choi, Yeon-Gil; Kim, V Narry

2018-06-20

Microprocessor, which consists of a ribonuclease III DROSHA and its cofactor DGCR8, initiates microRNA (miRNA) maturation by cleaving primary miRNA transcripts (pri-miRNAs). We recently demonstrated that the DGCR8 dimer recognizes the apical elements of pri-miRNAs, including the UGU motif, to accurately locate and orient Microprocessor on pri-miRNAs. However, the mechanism underlying the selective RNA binding remains unknown. In this study, we find that hemin, a ferric ion-containing porphyrin, enhances the specific interaction between the apical UGU motif and the DGCR8 dimer, allowing Microprocessor to achieve high efficiency and fidelity of pri-miRNA processing in vitro. Furthermore, by generating a DGCR8 mutant cell line and carrying out rescue experiments, we discover that hemin preferentially stimulates the expression of miRNAs possessing the UGU motif, thereby conferring differential regulation of miRNA maturation. Our findings reveal the molecular action mechanism of hemin in pri-miRNA processing and establish a novel function of hemin in inducing specific RNA-protein interaction.

Rapid Damage Assessment. Volume II. Development and Testing of Rapid Damage Assessment System.

DTIC Science & Technology

1981-02-01

pixels/s Camera Line Rate 732.4 lines/s Pixels per Line 1728 video 314 blank 4 line number (binary) 2 run number (BCD) 2048 total Pixel Resolution 8 bits...sists of an LSI-ll microprocessor, a VDI -200 video display processor, an FD-2 dual floppy diskette subsystem, an FT-I function key-trackball module...COMPONENT LIST FOR IMAGE PROCESSOR SYSTEM IMAGE PROCESSOR SYSTEM VIEWS I VDI -200 Display Processor Racks, Table FD-2 Dual Floppy Diskette Subsystem FT-l

Small Private Key PKS on an Embedded Microprocessor

PubMed Central

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-01-01

Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

Small private key MQPKS on an embedded microprocessor.

PubMed

Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

2014-03-19

Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

A microprocessor-based position control system for a telescope secondary mirror

NASA Technical Reports Server (NTRS)

Lorell, K. R.; Barrows, W. F.; Clappier, R. R.; Lee, G. K.

1983-01-01

The pointing requirements for the Shuttle IR Telescope Facility (SIRTF), which consists of an 0.85-m cryogenically cooled IR telescope, call for an image stability of 0.25 arcsec. Attention is presently given to a microprocessor-based position control system developed for the control of the SIRTF secondary mirror, employing a special control law (to minimize energy dissipation), a precision capacitive position sensor, and a specially designed power amplifier/actuator combination. The microprocessor generates the command angular position and rate waveforms in order to maintain a 90 percent dwell time/10 percent transition time ratio independently of chop frequency or amplitude. Performance and test results of a prototype system designed for use with a demonstration model of the SIRTF focal plane fine guidance sensor are presented.

An FPGA computing demo core for space charge simulation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wu, Jinyuan; Huang, Yifei; /Fermilab

2009-01-01

In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computedmore » using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.« less

Gait termination on a declined surface in trans-femoral amputees: Impact of using microprocessor-controlled limb system.

PubMed

Abdulhasan, Zahraa M; Scally, Andy J; Buckley, John G

2018-05-30

Walking down ramps is a demanding task for transfemoral-amputees and terminating gait on ramps is even more challenging because of the requirement to maintain a stable limb so that it can do the necessary negative mechanical work on the centre-of-mass in order to arrest (dissipate) forward/downward velocity. We determined how the use of a microprocessor-controlled limb system (simultaneous control over hydraulic resistances at ankle and knee) affected the negative mechanical work done by each limb when transfemoral-amputees terminated gait during ramp descent. Eight transfemoral-amputees completed planned gait terminations (stopping on prosthesis) on a 5-degree ramp from slow and customary walking speeds, with the limb's microprocessor active or inactive. When active the limb operated in its 'ramp-descent' mode and when inactive the knee and ankle devices functioned at constant default levels. Negative limb work, determined as the integral of the negative mechanical (external) limb power during the braking phase, was compared across speeds and microprocessor conditions. Negative work done by each limb increased with speed (p < 0.001), and on the prosthetic limb it was greater when the microprocessor was active compared to inactive (p = 0.004). There was no change in work done across microprocessor conditions on the intact limb (p = 0.35). Greater involvement of the prosthetic limb when the limb system was active indicates its ramp-descent mode effectively altered the hydraulic resistances at the ankle and knee. Findings highlight participants became more assured using their prosthetic limb to arrest centre-of-mass velocity. Copyright © 2018 Elsevier Ltd. All rights reserved.

The microprocessor-based synthesizer controller

NASA Technical Reports Server (NTRS)

Wick, M. R.

1980-01-01

Implementation and performance of the microprocessor-based controllers and Dana Digiphase Synthesizer (DCO) installed in the Deep Space Network exciter in the 64-meter and 34-meter subnets to support uplink tuning required for the Voyager-Saturn Encounter is discussed. Test data in tests conducted during the production of the controllers verified the design objective for phase control accuracy of 10 to the - 12 power cycles in eight hours during ramping. Tests conducted require a phase error between a theoretical calculated value and the actual phase of no greater than + or - 1 cycle. Tests included (1) a ramp over a period of eight hours using a ramp rate which covers the synthesizer tuning range (40-51 MHz) and (2) a ramp sequence using the maximum rate (+ or kHz/s) over the tuning range.

Proceedings: DISE Workshop on Microprocessors and Education (Fort Collins, Colorado, August 16-18, 1976).

ERIC Educational Resources Information Center

Pittsburgh Univ., PA. Dept. of Electrical Engineering.

Papers presented during four sessions of a workshop, which addressed the role of microprocessors in education, are included in this publication. The issues covered involved seven areas: (1) views of the microelectronics industry; (2) microprocessor architecture; (3) microprocessor chip design; (4) microprocessor software; (5) the impact of…

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

Software modifications to the Demonstration Advanced Avionics Systems (DAAS)

NASA Technical Reports Server (NTRS)

Nedell, B. F.; Hardy, G. H.

1984-01-01

Critical information required for the design of integrated avionics suitable for generation aviation is applied towards software modifications for the Demonstration Advanced Avionics System (DAAS). The program emphasizes the use of data busing, distributed microprocessors, shared electronic displays and data entry devices, and improved functional capability. A demonstration advanced avionics system (DAAS) is designed, built, and flight tested in a Cessna 402, twin engine, general aviation aircraft. Software modifications are made to DAAS at Ames concurrent with the flight test program. The changes are the result of the experience obtained with the system at Ames, and the comments of the pilots who evaluated the system.

Implementation of the DAST ARW II control laws using an 8086 microprocessor and an 8087 floating-point coprocessor. [drones for aeroelasticity research

NASA Technical Reports Server (NTRS)

Kelly, G. L.; Berthold, G.; Abbott, L.

1982-01-01

A 5 MHZ single-board microprocessor system which incorporates an 8086 CPU and an 8087 Numeric Data Processor is used to implement the control laws for the NASA Drones for Aerodynamic and Structural Testing, Aeroelastic Research Wing II. The control laws program was executed in 7.02 msec, with initialization consuming 2.65 msec and the control law loop 4.38 msec. The software emulator execution times for these two tasks were 36.67 and 61.18, respectively, for a total of 97.68 msec. The space, weight and cost reductions achieved in the present, aircraft control application of this combination of a 16-bit microprocessor with an 80-bit floating point coprocessor may be obtainable in other real time control applications.

Low-level processing for real-time image analysis

NASA Technical Reports Server (NTRS)

Eskenazi, R.; Wilf, J. M.

1979-01-01

A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.

Synchronous clock stopper for microprocessor

NASA Technical Reports Server (NTRS)

Kitchin, David A. (Inventor)

1985-01-01

A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.

Demonstration Advanced Avionics System (DAAS) function description

NASA Technical Reports Server (NTRS)

Bailey, A. J.; Bailey, D. G.; Gaabo, R. J.; Lahn, T. G.; Larson, J. C.; Peterson, E. M.; Schuck, J. W.; Rodgers, D. L.; Wroblewski, K. A.

1982-01-01

The Demonstration Advanced Avionics System, DAAS, is an integrated avionics system utilizing microprocessor technologies, data busing, and shared displays for demonstrating the potential of these technologies in improving the safety and utility of general aviation operations in the late 1980's and beyond. Major hardware elements of the DAAS include a functionally distributed microcomputer complex, an integrated data control center, an electronic horizontal situation indicator, and a radio adaptor unit. All processing and display resources are interconnected by an IEEE-488 bus in order to enhance the overall system effectiveness, reliability, modularity and maintainability. A detail description of the DAAS architecture, the DAAS hardware, and the DAAS functions is presented. The system is designed for installation and flight test in a NASA Cessna 402-B aircraft.

Using benchmarks for radiation testing of microprocessors and FPGAs

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather; Robinson, William H.; Rech, Paolo

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

Using benchmarks for radiation testing of microprocessors and FPGAs

DOE PAGES

Quinn, Heather; Robinson, William H.; Rech, Paolo; ...

2015-12-17

Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

Cumulative Timers for Microprocessors

NASA Technical Reports Server (NTRS)

Battle, John O.

2007-01-01

It has been proposed to equip future microprocessors with electronic cumulative timers, for essentially the same reasons for which land vehicles are equipped with odometers (total-distance-traveled meters) and aircraft are equipped with Hobbs meters (total-engine-operating time meters). Heretofore, there has been no way to determine the amount of use to which a microprocessor (or a product containing a microprocessor) has been subjected. The proposed timers would count all microprocessor clock cycles and could only be read by means of microprocessor instructions but, like odometers and Hobbs meters, could never be reset to zero without physically damaging the chip.

Multi-crop area estimation and mapping on a microprocessor/mainframe network

NASA Technical Reports Server (NTRS)

Sheffner, E.

1985-01-01

The data processing system is outlined for a 1985 test aimed at determining the performance characteristics of area estimation and mapping procedures connected with the California Cooperative Remote Sensing Project. The project is a joint effort of the USDA Statistical Reporting Service-Remote Sensing Branch, the California Department of Water Resources, NASA-Ames Research Center, and the University of California Remote Sensing Research Program. One objective of the program was to study performance when data processing is done on a microprocessor/mainframe network under operational conditions. The 1985 test covered the hardware, software, and network specifications and the integration of these three components. Plans for the year - including planned completion of PEDITOR software, testing of software on MIDAS, and accomplishment of data processing on the MIDAS-VAX-CRAY network - are discussed briefly.

Software and languages for microprocessors

NASA Astrophysics Data System (ADS)

Williams, David O.

1986-08-01

This paper forms the basis for lectures given at the 6th Summer School on Computing Techniques in Physics, organised by the Computational Physics group of the European Physics Society, and held at the Hotel Ski, Nové Město na Moravě, Czechoslovakia, on 17-26 September 1985. Various types of microprocessor applications are discussed and the main emphasis of the paper is devoted to 'embedded' systems, where the software development is not carried out on the target microprocessor. Some information is provided on the general characteristics of microprocessor hardware. Various types of microprocessor operating system are compared and contrasted. The selection of appropriate languages and software environments for use with microprocessors is discussed. Mechanisms for interworking between different languages, including reasonable error handling, are treated. The CERN developed cross-software suite for the Motorola 68000 family is described. Some remarks are made concerning program tools applicable to microprocessors. PILS, a Portable Interactive Language System, which can be interpreted or compiled for a range of microprocessors, is described in some detail, and the implementation techniques are discussed.

Input/output models for general aviation piston-prop aircraft fuel economy

NASA Technical Reports Server (NTRS)

Sweet, L. M.

1982-01-01

A fuel efficient cruise performance model for general aviation piston engine airplane was tested. The following equations were made: (1) for the standard atmosphere; (2) airframe-propeller-atmosphere cruise performance; and (3) naturally aspirated engine cruise performance. Adjustments are made to the compact cruise performance model as follows: corrected quantities, corrected performance plots, algebraic equations, maximize R with or without constraints, and appears suitable for airborne microprocessor implementation. The following hardwares are recommended: ignition timing regulator, fuel-air mass ration controller, microprocessor, sensors and displays.

Microprocessor utilization in search and rescue missions

NASA Technical Reports Server (NTRS)

Schwartz, M.

1977-01-01

The feasibility of performing the same task in real time using microprocessor technology was determined. The least square algorithm was implemented on an Intel 8080 microprocessor. Results indicated that a microprocessor could easily match the IBM implementation in accuracy and be performed inside the time limitations set.

Microprocessors in U.S. Electrical Engineering Departments, 1974-1975.

ERIC Educational Resources Information Center

Sloan, M. E.

Drawn from a survey of engineering departments known to be teaching microprocessor courses, this paper shows that the adoption of microprocessors by Electrical Engineering Departments has been rapid compared with their adoption of minicomputers. The types of courses that are being taught can be categorized as: surveys of microprocessors, intensive…

76 FR 39895 - In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-07

... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-781] In the Matter of Certain Microprocessors... importation of certain microprocessors, components thereof, and products containing same by reason of... microprocessors, components thereof, and products containing same that infringe one or more of claims 11-16, 41...

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

NASA Technical Reports Server (NTRS)

1977-01-01

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

Vehicle safety telemetry for automated highways

NASA Technical Reports Server (NTRS)

Hansen, G. R.

1977-01-01

The emphasis in current, automatic vehicle testing and diagnosis is primarily centered on the proper operation of the engine. Lateral and longitudinal guidance technologies, including speed control and headway sensing for collision avoidance, are reviewed. The principal guidance technique remains the buried wire. Speed control and headway sensing, even though they show the same basic elements in braking and fuel systems, are proceeding independently. The applications of on-board electronic and microprocessor techniques were investigated; each application (emission control, spark advance, or anti-slip braking) is being treated as an independent problem is proposed. A unified bus system of distributed processors for accomplishing the various functions and testing required for vehicles equipped to use automated highways.

Manage Energy with Computers.

ERIC Educational Resources Information Center

American School and University, 1982

1982-01-01

Computerized energy management at Drew University (New Jersey) is accomplished by direct digital control in which microprocessor controllers control, monitor, and carry out energy management functions at the equipment level. (Author/MLF)

Autoregulatory mechanisms controlling the Microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2010-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature 22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part ofa newly identified regulatory mechanism controlling Microprocessor activity.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

Rapidly quantifying the relative distention of a human bladder

NASA Technical Reports Server (NTRS)

Companion, John A. (Inventor); Heyman, Joseph S. (Inventor); Mineo, Beth A. (Inventor); Cavalier, Albert R. (Inventor); Blalock, Travis N. (Inventor)

1989-01-01

A device and method of rapidly quantifying the relative distention of the bladder in a human subject are disclosed. The ultrasonic transducer which is positioned on the subject in proximity to the bladder is excited by a pulser under the command of a microprocessor to launch an acoustic wave into the patient. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer, when it is received, amplified and processed by the receiver. The resulting signal is digitized by an analog-to-digital converter under the command of the microprocessor and is stored in the data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy; and based on programmed scientific measurements and individual, anatomical, and behavioral characterists of the specific subject as contained in the program memory, sends out a signal to turn on any or all of the audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

A novel role for GSK3β as a modulator of Drosha microprocessor activity and MicroRNA biogenesis.

PubMed

Fletcher, Claire E; Godfrey, Jack D; Shibakawa, Akifumi; Bushell, Martin; Bevan, Charlotte L

2016-10-23

Regulation of microRNA (miR) biogenesis is complex and stringently controlled. Here, we identify the kinase GSK3β as an important modulator of miR biogenesis at Microprocessor level. Repression of GSK3β activity reduces Drosha activity toward pri-miRs, leading to accumulation of unprocessed pri-miRs and reduction of pre-miRs and mature miRs without altering levels or cellular localisation of miR biogenesis proteins. Conversely, GSK3β activation increases Drosha activity and mature miR accumulation. GSK3β achieves this through promoting Drosha:cofactor and Drosha:pri-miR interactions: it binds to DGCR8 and p72 in the Microprocessor, an effect dependent upon presence of RNA. Indeed, GSK3β itself can immunoprecipitate pri-miRs, suggesting possible RNA-binding capacity. Kinase assays identify the mechanism for GSK3β-enhanced Drosha activity, which requires GSK3β nuclear localisation, as phosphorylation of Drosha at S 300 and/or S 302 ; confirmed by enhanced Drosha activity and association with cofactors, and increased abundance of mature miRs in the presence of phospho-mimic Drosha. Functional implications of GSK3β-enhanced miR biogenesis are illustrated by increased levels of GSK3β-upregulated miR targets following GSK3β inhibition. These data, the first to link GSK3β with the miR cascade in humans, highlight a novel pro-biogenesis role for GSK3β in increasing miR biogenesis as a component of the Microprocessor complex with wide-ranging functional consequences. © The Author(s) 2016. Published by Oxford University Press on behalf of Nucleic Acids Research.

Experimental Verification of Electric Drive Technologies Based on Artificial Intelligence Tools

NASA Technical Reports Server (NTRS)

Rubaai, Ahmed; Kankam, David (Technical Monitor)

2003-01-01

A laboratory implementation of a fuzzy logic-tracking controller using a low cost Motorola MC68HC11E9 microprocessor is described in this report. The objective is to design the most optimal yet practical controller that can be implemented and marketed, and which gives respectable performance, even when the system loads, inertia and parameters are varying. A distinguishing feature of this work is the by-product goal of developing a marketable, simple, functional and low cost controller. Additionally, real-time nonlinearities are not ignored, and a mathematical model is not required. A number of components have been designed, built and tested individually, and in various combinations of hardware and software segments. These components have been integrated with a brushless motor to constitute the drive system. A microprocessor-based FLC is incorporated to provide robust speed and position control. Design objectives that are difficult to express mathematically can be easily incorporated in a fuzzy logic-based controller by linguistic information (in the form of fuzzy IF-THEN rules). The theory and design are tested in the laboratory using a hardware setup. Several test cases have been conducted to confirm the effectiveness of the proposed controller. The results indicate excellent tracking performance for both speed and position trajectories. For the purpose of comparison, a bang-bang controller has been tested. The fuzzy logic controller performs significantly better than the traditional bang-bang controller. The bang-bang controller has been shown to be relatively inaccurate and lacking in robustness. Description of the implementation hardware system is also given.

Bus-Programmable Slave Card

NASA Technical Reports Server (NTRS)

Hall, William A.

1990-01-01

Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.

PASCAL vs BASIC

ERIC Educational Resources Information Center

Mundie, David A.

1978-01-01

A comparison between PASCAL and BASIC as general purpose microprocessor languages rates PASCAL above BASIC in such points as program structure, data types, structuring methods, control structures, procedures and functions, and ease in learning. (CMV)

Performance, operational limits, of an Electronic Switching Spherical Array (ESSA) antenna

NASA Technical Reports Server (NTRS)

Stockton, R.

1979-01-01

The development of a microprocessor controller which provides multimode operational capability for the Electronic Switching Spherical Array (ESSA) Antenna is described. The best set of operating conditions were determined and the performance of an ESSA antenna was demonstrated in the following modes: (1) omni; (2) acquisition/track; (3) directive; and (4) multibeam. The control algorithms, software flow diagrams, and electronic circuitry were developed. The microprocessor and control electronics were built and interfaced with the antenna to carry out performance testing. The acquisition/track mode for users in the Tracking and Data Relay Satellite System is emphasized.

Microprocessor-controlled laser tracker for atmospheric sensing

NASA Technical Reports Server (NTRS)

Johnson, R. A.; Webster, C. R.; Menzies, R. T.

1985-01-01

An optical tracking system comprising a visible HeNe laser, an imaging detector, and a microprocessor-controlled mirror, has been designed to track a moving retroreflector located up to 500 m away from an atmospheric instrument and simultaneously direct spectrally tunable infrared laser radiation to the retroreflector for double-ended, long-path absorption measurements of atmospheric species. The tracker has been tested during the recent flight of a balloon-borne tunable diode laser absorption spectrometer which monitors the concentrations of stratospheric species within a volume defined by a 0.14-m-diameter retroreflector lowered 500 m below the instrument gondola.

Programmable calculator as a data system controller

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barth, A.W.; Strasburg, A.C.

Digital data techniques are in common use for analysis of analog information obtained in various tests, and systems have been developed which use a minicomputer as the central controller and data processor. Now, microprocessors allow new design approaches at considerably less cost. This report outlines an approach to system design based on the use of a programmable calculator as the data system controller. A block diagram of the calculator-controlled data system is shown. It was found that the programmable calculator provides a viable alternative to minicomputers or microprocessors for the development laboratory requiring digital data processing. 3 figures. (RWR)

Microprocessor control of a wind turbine generator

NASA Technical Reports Server (NTRS)

Gnecco, A. J.; Whitehead, G. T.

1978-01-01

A microprocessor based system was used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

System architecture of a gallium arsenide one-gigahertz digital IC tester

NASA Technical Reports Server (NTRS)

Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

1987-01-01

The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

Autoregulatory mechanisms controlling the microprocessor.

PubMed

Triboulet, Robinson; Gregory, Richard I

2011-01-01

The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature ∼22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part of a newly identified regulatory mechanism controlling Microprocessor activity.

Post-transcriptional control of DGCR8 expression by the Microprocessor.

PubMed

Triboulet, Robinson; Chang, Hao-Ming; Lapierre, Robert J; Gregory, Richard I

2009-06-01

The Microprocessor, comprising the RNase III Drosha and the double-stranded RNA binding protein DGCR8, is essential for microRNA (miRNA) biogenesis. In the miRNA processing pathway certain hairpin structures within primary miRNA (pri-miRNA) transcripts are specifically cleaved by the Microprocessor to release approximately 60-70-nucleotide precursor miRNA (pre-miRNA) intermediates. Although both Drosha and DGCR8 are required for Microprocessor activity, the mechanisms regulating the expression of these proteins are unknown. Here we report that the Microprocessor negatively regulates DGCR8 expression. Using in vitro reconstitution and in vivo studies, we demonstrate that a hairpin, localized in the 5' untranslated region (5'UTR) of DGCR8 mRNA, is cleaved by the Microprocessor. Accordingly, knockdown of Drosha leads to an increase in DGCR8 mRNA and protein levels in cells. Furthermore, we found that the DGCR8 5'UTR confers Microprocessor-dependent repression of a luciferase reporter gene in vivo. Our results uncover a novel feedback loop that regulates DGCR8 levels.

Microprocessors in Schools?

ERIC Educational Resources Information Center

Cuthbert, L. G.

1981-01-01

Examines reasons for including microprocessors in school curricula. Indicates that practical work with microprocessors is not easy and discusses problems associated with using and constructing these control and processing devices of microcomputers. (SK)

The Use of Tailored Testing with Instructional Programs. Final Report.

ERIC Educational Resources Information Center

Reckase, Mark D.

A computerized testing system was implemented in conjunction with the Radar Technician Training Course at the Naval Training Center, Great Lakes, Illinois. The feasibility of the system and students' attitudes toward it were examined. The system, a multilevel, microprocessor-based computer network, administered tests in a sequential, fixed length…

Test program for 4-K memory card, JOLT microprocessor

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

A memory test program is described for use with the JOLT microcomputer 4,096-word memory board used in development of an Omega navigation receiver. The program allows a quick test of the memory board by cycling the memory through all possible bit combinations in all words.

Mobility and satisfaction with a microprocessor-controlled knee in moderately active amputees: A multi-centric randomized crossover trial.

PubMed

Lansade, Céline; Vicaut, Eric; Paysant, Jean; Ménager, Doménico; Cristina, Marie-Christine; Braatz, Frank; Domayer, Stephan; Pérennou, Dominic; Chiesa, Gérard

2018-05-14

Microprocessor-controlled knees are generally prescribed and reimbursed for active amputees. Recent studies suggested that this technology could be useful for amputees with moderate activity level. We compared the efficiency of a microprocessor-controlled knee (MPK, Kenevo, Otto Bock) and non-MPKs (NMPKs) in these indications. A multi-centric randomized crossover trial was conducted in 16 hospitals from 3 European countries. Participants were randomized to an MPK-NMPK sequence, testing the MPK for 3 months and the NMPK for 1 month, or to an NMPK-MPK sequence, testing the NMPK for 1 month and the MPK for 3 months. Dynamic balance, the main criteria, was assessed with the Timed-Up and Go test (TUG), functional mobility with the Locomotor Capability Index (LCI-5), quality of life with the Medical Outcomes Study Short Form 36 v2 (SF-36v2) and satisfaction with the Quebec User Evaluation of Satisfaction with Assistive Technology 2.0. The occurrence of falls was monitored during the last month of trial. Analysis was by intent-to-treat and per-protocol (PP). We recruited 35 individuals with transfemoral amputation or knee disarticulation (27 males; mean age 65.6years [SD 10.1]). On PP analysis, dynamic balance and functional mobility were improved with the MPK, as shown by a reduced median TUG time (from 21.4s [Q1-Q3 19.3-26.6] to 17.9s [15.4-22.7], P=0.001) and higher mean global LCI-5 (from 40.4 [SD 7.6] to 42.8 [6.2], P=0.02). Median global satisfaction score increased (from 3.9 [Q1-Q3 3.8-4.4] to 4.7 [4.1-4.9], P=0.001) and quality of life was improved for the mental component summary of the SF-36v2 (median score from 53.3 [Q1-Q3 47.8-60.7] to 60.2 [51.6-62.6], P=0.03) and physical component summary but not significantly (mean score from 44.1 [SD 6.3] to 46.3 [7.0], P=0.08). Monitoring of adverse events including falls revealed no differences between both assessed devices. This study enhances the level of evidence to argue equal opportunity for all individuals with transfemoral amputation or knee disarticulation, regardless of their mobility grade, to be provided with appropriate prostheses. Copyright © 2018. Published by Elsevier Masson SAS.

Data transmission system with distributed microprocessors

DOEpatents

Nambu, Shigeo

1985-01-01

A data transmission system having a common request line and a special request line in addition to a transmission line. The special request line has priority over the common request line. A plurality of node stations are multi-drop connected to the transmission line. Among the node stations, a supervising station is connected to the special request line and takes precedence over other slave stations to become a master station. The master station collects data from the slave stations. The station connected to the common request line can assign a master control function to any station requesting to be assigned the master control function within a short period of time. Each station has an auto response control circuit. The master station automatically collects data by the auto response controlling circuit independently of the microprocessors of the slave stations.

A Microprocessor Project for Non-Electrical Engineering Students.

ERIC Educational Resources Information Center

Swingler, D. N.

1981-01-01

Offers rationale for and a description of a microprocessor-based control system project for mechanical engineering students. Includes reasons for selecting a Texas Instruments TM990/189 microprocessor system. (SK)

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2013 CFR

2013-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2010 CFR

2010-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for ‘military...

Code of Federal Regulations, 2014 CFR

2014-01-01

... reexports of general purpose microprocessors for âmilitary end usesâ and to âmilitary end usersâ. 744.17... microprocessors for ‘military end uses’ and to ‘military end users’. (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2012 CFR

2012-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

Code of Federal Regulations, 2011 CFR

2011-01-01

... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

DTIC Science & Technology

with greater range of motion and active power, will translate into improved functional performance, ambulatory safety (risk of falls) and quality of... life in trans-tibial amputees (TTA) who function as limited community ambulators. We will assess these outcomes in 54 veterans with TTA by randomizing

A functional language approach in high-speed digital simulation

NASA Technical Reports Server (NTRS)

Ercegovac, M. D.; Lu, S.-L.

1983-01-01

A functional programming approach for a multi-microprocessor architecture is presented. The language, based on Backus FP, its intermediate form and the translation process are discussed and illustrated with an example. The approach allows performance analysis to be performed at a high level as an aid in program partitioning.

TDP-43 regulates the microprocessor complex activity during in vitro neuronal differentiation.

PubMed

Di Carlo, Valerio; Grossi, Elena; Laneve, Pietro; Morlando, Mariangela; Dini Modigliani, Stefano; Ballarino, Monica; Bozzoni, Irene; Caffarelli, Elisa

2013-12-01

TDP-43 (TAR DNA-binding protein 43) is an RNA-binding protein implicated in RNA metabolism at several levels. Even if ubiquitously expressed, it is considered as a neuronal activity-responsive factor and a major signature for neurological pathologies, making the comprehension of its activity in the nervous system a very challenging issue. TDP-43 has also been described as an accessory component of the Drosha-DGCR8 (DiGeorge syndrome critical region gene 8) microprocessor complex, which is crucially involved in basal and tissue-specific RNA processing events. In the present study, we exploited in vitro neuronal differentiation systems to investigate the TDP-43 demand for the microprocessor function, focusing on both its canonical microRNA biosynthetic activity and its alternative role as a post-transcriptional regulator of gene expression. Our findings reveal a novel role for TDP-43 as an essential factor that controls the stability of Drosha protein during neuronal differentiation, thus globally affecting the production of microRNAs. We also demonstrate that TDP-43 is required for the Drosha-mediated regulation of Neurogenin 2, a master gene orchestrating neurogenesis, whereas post-transcriptional control of Dgcr8, another Drosha target, resulted to be TDP-43-independent. These results implicate a previously uncovered contribution of TDP-43 in regulating the abundance and the substrate specificity of the microprocessor complex and provide new insights into TDP-43 as a key player in neuronal differentiation.

Generic interpreters and microprocessor verification

NASA Technical Reports Server (NTRS)

Windley, Phillip J.

1990-01-01

The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocessors; (3) microprocessor verification; (4) determining correctness; (5) hierarchical decomposition; (6) interpreter theory; (7) AVM-1; (8) phase-level specification; and future work.

External Verification of SCADA System Embedded Controller Firmware

DTIC Science & Technology

2012-03-01

microprocessor and read-only memory (ROM) or flash memory for storing firmware and control logic [5],[8]. A PLC typically has three software levels as shown in...implementing different firmware. Because PLCs are in effect a microprocessor device, an analysis of the current research on embedded devices is important...Electronics Engineers (IEEE) published a 15 best practices guide for firmware control on microprocessors [44]. IEEE suggests that microprocessors

OS friendly microprocessor architecture: Hardware level computer security

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; La Fratta, Patrick

2016-05-01

We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

Microprocessor-based interface for oceanography

NASA Technical Reports Server (NTRS)

Hansen, G. R.

1979-01-01

Ocean floor imaging system incorporates five identical microprocessor-based interface units each assigned to specific sonar instrument to simplify system. Central control module based on same microprocessor eliminates need for custom tailoring hardware interfaces for each instrument.

Manufacturing Methods and Technology for Digital Fault Isolation for Printed Circuit Boards.

DTIC Science & Technology

1979-08-25

microprocessors and support chips, ROMs, RAMs, UARTs , etc. They also include rules for busses and memory testing. The special rules for test points emphasize...I 8). UART .. ...................................................... I 9). SAT...0.0 I ( 8). UART ...................................................... 0.0O S 9). SAT

Test module development to detect the flase call probe pins on microeprocessor test equipment

NASA Astrophysics Data System (ADS)

Tang, L. W.; Ong, N. R.; Mohamad, I. S. B.; Alcain, J. B.; Retnasamy, V.

2017-09-01

Probe pins are useful for electrical testing of microelectronic components, printed circuit board assembly (PCBA), microprocessors and other electronic devices due to it provides the conductivity test based on specific device circuit design. During the repeatable test runs, the load of test modules, contact failures and the current conductivity induces layer wear off all the tip of probe pins contact. Contamination will be build-up on probe pins and increased contact resistivity which results of cost loss and time loss for rectifying programs, rectifying testers and exchanging new probe pins. In this study, a resistivity approach will be developed to provide "Testing of Test Probes". The test module based on "Four-wire Ohm measurement" method with two alternative ways of applying power supply, that are 9V from a single power supply and 5V from Arduino UNO power supply were demonstrated to measure the small resistance value of microprocessor probe pin. A microcontroller with VEE Pro software was used to record the measurement data. The accuracy of both test modules were calibrated under different temperature conditions and result shows that 9V from a single power supply test module has higher measurement accuracy.

AC resistance measuring instrument

DOEpatents

Hof, P.J.

1983-10-04

An auto-ranging AC resistance measuring instrument for remote measurement of the resistance of an electrical device or circuit connected to the instrument includes a signal generator which generates an AC excitation signal for application to a load, including the device and the transmission line, a monitoring circuit which provides a digitally encoded signal representing the voltage across the load, and a microprocessor which operates under program control to provide an auto-ranging function by which range resistance is connected in circuit with the load to limit the load voltage to an acceptable range for the instrument, and an auto-compensating function by which compensating capacitance is connected in shunt with the range resistance to compensate for the effects of line capacitance. After the auto-ranging and auto-compensation functions are complete, the microprocessor calculates the resistance of the load from the selected range resistance, the excitation signal, and the load voltage signal, and displays of the measured resistance on a digital display of the instrument. 8 figs.

AC Resistance measuring instrument

DOEpatents

Hof, Peter J.

1983-01-01

An auto-ranging AC resistance measuring instrument for remote measurement of the resistance of an electrical device or circuit connected to the instrument includes a signal generator which generates an AC excitation signal for application to a load, including the device and the transmission line, a monitoring circuit which provides a digitally encoded signal representing the voltage across the load, and a microprocessor which operates under program control to provide an auto-ranging function by which range resistance is connected in circuit with the load to limit the load voltage to an acceptable range for the instrument, and an auto-compensating function by which compensating capacitance is connected in shunt with the range resistance to compensate for the effects of line capacitance. After the auto-ranging and auto-compensation functions are complete, the microprocessor calculates the resistance of the load from the selected range resistance, the excitation signal, and the load voltage signal, and displays of the measured resistance on a digital display of the instrument.

Microprocessor Airborne Data Acquisition & Replay (MADAR) System,

DTIC Science & Technology

1984-03-01

Time Record 7. TAPE USAGE 28 7.1 Geseral2 7.2 Tape Time Remanfng lbdocator 28 7.3 Tape Record Capacity 30 . 8. MODULE CONSTRUCTION 30 8.1 Gemeral...general purpose quick-fit type, calibrated for use with a range of different aircraft. The concept was modified such that the microprocessor module was not...dedicated to boom usage but a versatile instrument for other applications. The microprocessor module (Fig. 1) became known as the Microprocessor

Microprocessor-based cardiopulmonary monitoring system

NASA Technical Reports Server (NTRS)

1978-01-01

The system uses a dedicated microprocessor for transducer control and data acquisition and analysis. No data will be stored in this system, but the data will be transmitted to the onboard data system. The data system will require approximately 12 inches of rack space and will consume only 100 watts of power. An experiment specific control panel, through a series of lighted buttons, will guide the operator through the test series providing a smaller margin of error. The experimental validity of the system was verified, and the reproducibility of data and reliability of the system checked. In addition, ease of training, ease of operator interaction, and crew acceptance were evaluated in actual flight conditions.

Microprocessors and the Curriculum.

ERIC Educational Resources Information Center

Pasahow, Edward J.

1981-01-01

Presents three approaches to teaching the use of a microprocessor: (1) a "generic" device on paper; (2) a "conglomeration" device, surveying a number of real products; and (3) the "how" course which covers a small number of actual but related microprocessors. (CT)

Topological Properties of Some Integrated Circuits for Very Large Scale Integration Chip Designs

NASA Astrophysics Data System (ADS)

Swanson, S.; Lanzerotti, M.; Vernizzi, G.; Kujawski, J.; Weatherwax, A.

2015-03-01

This talk presents topological properties of integrated circuits for Very Large Scale Integration chip designs. These circuits can be implemented in very large scale integrated circuits, such as those in high performance microprocessors. Prior work considered basic combinational logic functions and produced a mathematical framework based on algebraic topology for integrated circuits composed of logic gates. Prior work also produced an historically-equivalent interpretation of Mr. E. F. Rent's work for today's complex circuitry in modern high performance microprocessors, where a heuristic linear relationship was observed between the number of connections and number of logic gates. This talk will examine topological properties and connectivity of more complex functionally-equivalent integrated circuits. The views expressed in this article are those of the author and do not reflect the official policy or position of the United States Air Force, Department of Defense or the U.S. Government.

A GaAs vector processor based on parallel RISC microprocessors

NASA Astrophysics Data System (ADS)

Misko, Tim A.; Rasset, Terry L.

A vector processor architecture based on the development of a 32-bit microprocessor using gallium arsenide (GaAs) technology has been developed. The McDonnell Douglas vector processor (MVP) will be fabricated completely from GaAs digital integrated circuits. The MVP architecture includes a vector memory of 1 megabyte, a parallel bus architecture with eight processing elements connected in parallel, and a control processor. The processing elements consist of a reduced instruction set CPU (RISC) with four floating-point coprocessor units and necessary memory interface functions. This architecture has been simulated for several benchmark programs including complex fast Fourier transform (FFT), complex inner product, trigonometric functions, and sort-merge routine. The results of this study indicate that the MVP can process a 1024-point complex FFT at a speed of 112 microsec (389 megaflops) while consuming approximately 618 W of power in a volume of approximately 0.1 ft-cubed.

Effect of various features on the life cycle cost of the timing/synchronization subsystem of the DCS digital communications network

NASA Technical Reports Server (NTRS)

Kimsey, D. B.

1978-01-01

The effect on the life cycle cost of the timing subsystem was examined, when these optional features were included in various combinations. The features included mutual control, directed control, double-ended reference links, independence of clock error measurement and correction, phase reference combining, self-organization, smoothing for link and nodal dropouts, unequal reference weightings, and a master in a mutual control network. An overall design of a microprocessor-based timing subsystem was formulated. The microprocessor (8080) implements the digital filter portion of a digital phase locked loop, as well as other control functions such as organization of the network through communication with processors at neighboring nodes.

The application of digital signal processing techniques to a teleoperator radar system

NASA Technical Reports Server (NTRS)

Pujol, A.

1982-01-01

A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

A microprocessor-based control system for the Vienna PDS microdensitometer

NASA Technical Reports Server (NTRS)

Jenkner, H.; Stoll, M.; Hron, J.

1984-01-01

The Motorola Exorset 30 system, based on a Motorola 6809 microprocessor which serves as control processor for the microdensitometer is presented. User communication and instrument control are implemented in this syatem; data transmission to a host computer is provided via standard interfaces. The Vienna PDS system (VIPS) software was developed in BASIC and M6809 assembler. It provides efficient user interaction via function keys and argument input in a menu oriented environment. All parameters can be stored on, and retrieved from, minifloppy disks, making it possible to set up large scanning tasks. Extensive user information includes continuously updated status and coordinate displays, as well as a real time graphic display during scanning.

Application of digital control to a magnetic model suspension and balance model

NASA Technical Reports Server (NTRS)

Luh, P. B.; Covert, E. E.; Whitaker, H. P.; Haldeman, C. W.

1978-01-01

The feasibility of using a digital computer for performing the automatic control functions for a magnetic suspension and balance system (MSBS) for use with wind tunnel models was investigated. Modeling was done using both a prototype MSBS and a one dimensional magnetic balance. A microcomputer using the Intel 8080 microprocessor is described and results are given using this microprocessor to control the one dimensional balance. Hybrid simulations for one degree of freedom of the MSBS were also performed and are reported. It is concluded that use of a digital computer to control the MSBS is eminently feasible and should extend both the accuracy and utility of the system.

Lithium Ion Battery (LIB) Charger: Spacesuit Battery Charger Design with 2-Fault Tolerance to Catastrophic Hazards

NASA Technical Reports Server (NTRS)

Darcy, Eric; Davies, Frank

2009-01-01

Charger design that is 2-fault tolerant to catastrophic has been achieved for the Spacesuit Li-ion Battery with key features. Power supply control circuit and 2 microprocessors independently control against overcharge. 3 microprocessor control against undercharge (false positive: Go for EVA) conditions. 2 independent channels provide functional redundancy. Capable of charge balancing cell banks in series. Cell manufacturing and performance uniformity is excellent with both designs. Once a few outliers are removed, LV cells are slightly more uniform than MoliJ cells. If cell balance feature of charger is ever invoked, it will be an indication of a significant degradation issue, not a nominal condition.

Microprocessors in Systems Engineering at the U.S. Naval Academy.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Lowe, W. M., Ed.

1982-01-01

Describes the introduction of microprocessors into the Weapons and Systems Engineering Department at the U.S. Naval Academy, including planning decisions, implementation, procedures, uses of microprocessors in the department, and impact on the Systems Engineering major and curriculum. (SK)

Redundant Asynchronous Microprocessor System

NASA Technical Reports Server (NTRS)

Meyer, G.; Johnston, J. O.; Dunn, W. R.

1985-01-01

Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.

A status report of a FASTBUS at KEK

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arai, Y.; Endo, I.; Inoue

1983-02-01

Some FASTBUS modules have been produced and successfully tested at KEK. The test system consisted of a single backplane segment equipped with ancillary logic, two masters driven by the MC68000 microprocessor and two slaves which have several read/write registers. A simple FASTBUS-CAMAC interface is also described.

Apparatus Reviews.

ERIC Educational Resources Information Center

School Science Review, 1981

1981-01-01

Reviews apparatus design and instructional uses for Fume Cupboard Monitor, Plant Tissue Culture Kit, various equipment for electronic systems course, Welwyn Microprocessor-Tutor, Sweep Function Generator SFG 606, and Harris manufacturers materials--Regulated Power Supply Units, Electronic Current and Voltage Meters, Gas Preparation Kit, and…

Microprocessor-based control systems application in nuclear power plant critical systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shah, M.R.; Nowak, J.B.

Microprocessor-based control systems have been used in fossil power plants and are receiving greater acceptance for application in nuclear plants. This technology is not new but it does require unique considerations when applied to nuclear power plants. Sargent and Lundy (S and L) has used a microprocessor-based component logic control system (interposing Logic System) for safety- and non-safety-related components in nuclear power plants under construction overseas. Currently, S and L is in the design stage to replace an existing analog control system with a microprocessor-based control system in the U.S. The trend in the industry is to replace systems inmore » existing plants or design new power plants with microprocessor-based control systems.« less

Special purpose parallel computer architecture for real-time control and simulation in robotic applications

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1993-01-01

This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call.

Measures and procedures utilized to determine the added value of microprocessor-controlled prosthetic knee joints: a systematic review

PubMed Central

2013-01-01

Background The effectiveness of microprocessor-controlled prosthetic knee joints (MPKs) has been assessed using a variety of outcome measures in a variety of health and health-related domains. However, if the patient is to receive a prosthetic knee joint that enables him to function optimally in daily life, it is vital that the clinician has adequate information about the effects of that particular component on all aspects of persons’ functioning. Especially information concerning activities and participation is of high importance, as this component of functioning closely describes the person’s ability to function with the prosthesis in daily life. The present study aimed to review the outcome measures that have been utilized to assess the effects of microprocessor-controlled prosthetic knee joints (MPK), in comparison with mechanically controlled prosthetic knee joints, and aimed to classify these measures according to the components and categories of functioning defined by the International Classification of Functioning, Disability and Health (ICF). Subsequently, the gaps in the scientific evidence regarding the effectiveness of MPKs were determined. Methods A systematic literature search in 6 databases (i.e. PubMed, CINAHL, Cochrane Library, Embase, Medline and PsychInfo) identified scientific studies that compared the effects of using MPKs with mechanically controlled prosthetic knee joints on persons’ functioning. The outcome measures that have been utilized in those studies were extracted and categorized according to the ICF framework. Also, a descriptive analysis regarding all studies has been performed. Results A total of 37 studies and 72 outcome measures have been identified. The majority (67%) of the outcome measures that described the effects of using an MPK on persons’ actual performance with the prosthesis covered the ICF body functions component. Only 31% of the measures on persons’ actual performance investigated how an MPK may affect performance in daily life. Research also typically focused on young, fit and active persons. Conclusions Scientifically valid evidence regarding the performance of persons with an MPK in everyday life is limited. Future research should specifically focus on activities and participation to increase the understanding of the possible functional added value of MPKs. PMID:24279314

Measures and procedures utilized to determine the added value of microprocessor-controlled prosthetic knee joints: a systematic review.

PubMed

Theeven, Patrick J R; Hemmen, Bea; Brink, Peter R G; Smeets, Rob J E M; Seelen, Henk A M

2013-11-27

The effectiveness of microprocessor-controlled prosthetic knee joints (MPKs) has been assessed using a variety of outcome measures in a variety of health and health-related domains. However, if the patient is to receive a prosthetic knee joint that enables him to function optimally in daily life, it is vital that the clinician has adequate information about the effects of that particular component on all aspects of persons' functioning. Especially information concerning activities and participation is of high importance, as this component of functioning closely describes the person's ability to function with the prosthesis in daily life. The present study aimed to review the outcome measures that have been utilized to assess the effects of microprocessor-controlled prosthetic knee joints (MPK), in comparison with mechanically controlled prosthetic knee joints, and aimed to classify these measures according to the components and categories of functioning defined by the International Classification of Functioning, Disability and Health (ICF). Subsequently, the gaps in the scientific evidence regarding the effectiveness of MPKs were determined. A systematic literature search in 6 databases (i.e. PubMed, CINAHL, Cochrane Library, Embase, Medline and PsychInfo) identified scientific studies that compared the effects of using MPKs with mechanically controlled prosthetic knee joints on persons' functioning. The outcome measures that have been utilized in those studies were extracted and categorized according to the ICF framework. Also, a descriptive analysis regarding all studies has been performed. A total of 37 studies and 72 outcome measures have been identified. The majority (67%) of the outcome measures that described the effects of using an MPK on persons' actual performance with the prosthesis covered the ICF body functions component. Only 31% of the measures on persons' actual performance investigated how an MPK may affect performance in daily life. Research also typically focused on young, fit and active persons. Scientifically valid evidence regarding the performance of persons with an MPK in everyday life is limited. Future research should specifically focus on activities and participation to increase the understanding of the possible functional added value of MPKs.

The Stand-Alone Microprocessor System: A Valuable Tool in College Admissions and Recruitment.

ERIC Educational Resources Information Center

Garrett, Larry Neal

1983-01-01

The stand-alone microprocessor is seen as one innovative tool that can be used both in the organizational management of decline and in meeting specific organizational needs such as those of the admissions director and staff. The term "microprocessor" is defined. (MLW)

Microprocessors in the Curriculum and the Classroom.

ERIC Educational Resources Information Center

Summers, M. K.

1978-01-01

This article, directed at teachers concerned with computer science courses at sixth-form level with no prior knowledge of microprocessors, provides a basic introduction, and describes possible applications of a microprocessor development system as a teaching aid in computer sciences courses in UK secondary school. (Author/RAO)

78 FR 3449 - Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-01-16

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-781] Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements on the Public Interest AGENCY: U.S... a limited exclusion order as to subject Intel microprocessors, but that implementation be delayed...

Development of single cell protectors for sealed silver-zinc cells, phase 1

NASA Technical Reports Server (NTRS)

Imamura, M. S.; Donovan, R. L.; Lear, J. W.; Murray, B.

1976-01-01

A single cell protector (SCP) assembly capable of protecting a single silver-zinc (Ag Zn) battery cell was designed, fabricated, and tested. The SCP provides cell-level protection against overcharge and overdischarge by a bypass circuit. The bypass circuit consists of a magnetic-latching relay that is controlled by the high and low-voltage limit comparators. Although designed specifically for secondary Ag-Zn cells, the SCP is flexible enough to be adapted to other rechargeable cells. Eighteen SCPs were used in life testing of an 18-cell battery. The cells were sealed Ag-Zn system with inorganic separators. For comparison, another 18-cell battery was subjected to identical life test conditions, but with battery-level protection rather than cell-level. An alternative approach to the SCP design in the form of a microprocessor-based system was conceptually designed. The comparison of SCP and microprocessor approaches is also presented and a preferred approach for Ag-Zn battery protection is discussed.

Information Technologies for the 1980's: Lasers and Microprocessors.

ERIC Educational Resources Information Center

Mathews, William D.

This discussion of the development and application of lasers and microprocessors to information processing stresses laser communication in relation to capacity, reliability, and cost and the advantages of this technology to real-time information access and information storage. The increased capabilities of microprocessors are reviewed, and a…

Gallium-arsenide process evaluation based on a RISC microprocessor example

NASA Astrophysics Data System (ADS)

Brown, Richard B.; Upton, Michael; Chandna, Ajay; Huff, Thomas R.; Mudge, Trevor N.; Oettel, Richard E.

1993-10-01

This work evaluates the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivity of the microprocessor and other large circuit blocks to different process parameters is analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance.

Integrally regulated solar array demonstration using an Intel 8080 microprocessor

NASA Technical Reports Server (NTRS)

Petrik, E. J.

1977-01-01

A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.

Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

An assembler for the MOS Technology 6502 microprocessor as implemented in jolt (TM) and KIM-1 (TM)

NASA Technical Reports Server (NTRS)

Lilley, R. W.

1976-01-01

Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.

Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

PubMed

Shenoy, Archana; Blelloch, Robert

2009-09-11

The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript. To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES) cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8. We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

Fiber optic, Fabry-Perot high temperature sensor

NASA Technical Reports Server (NTRS)

James, K.; Quick, B.

1984-01-01

A digital, fiber optic temperature sensor using a variable Fabry-Perot cavity as the sensor element was analyzed, designed, fabricated, and tested. The fiber transmitted cavity reflection spectra is dispersed then converted from an optical signal to electrical information by a charged coupled device (CCD). A microprocessor-based color demodulation system converts the wavelength information to temperature. This general sensor concept not only utilizes an all-optical means of parameter sensing and transmitting, but also exploits microprocessor technology for automated control, calibration, and enhanced performance. The complete temperature sensor system was evaluated in the laboratory. Results show that the Fabry-Perot temperature sensor has good resolution (0.5% of full seale), high accuracy, and potential high temperature ( 1000 C) applications.

A microprocessor based anti-aliasing filter for a PCM system

NASA Technical Reports Server (NTRS)

Morrow, D. C.; Sandlin, D. R.

1984-01-01

Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.

Smart call box field operational test evaluation : subtest reports

DOT National Transportation Integrated Search

1997-05-01

Smart call boxes are an enhanced version of devices used as emergency call boxes in California. The overall system consists of a microprocessor, a cellular communications transceiver, solar power sources, data collection devices, maintenance computer...

Smart call box field operational test evaluation : summary report

DOT National Transportation Integrated Search

1997-05-01

Smart call boxes are an enhanced version of devices used as emergency call boxes in California. The overall system consists of a microprocessor, a cellular communications transceiver, solar power sources, data collection devices, maintenance computer...

Progress on advanced dc and ac induction drives for electric vehicles

NASA Technical Reports Server (NTRS)

Schwartz, H. J.

1982-01-01

Progress is reported in the development of complete electric vehicle propulsion systems, and the results of tests on the Road Load Simulator of two such systems representative of advanced dc and ac drive technology are presented. One is the system used in the DOE's ETV-1 integrated test vehicle which consists of a shunt wound dc traction motor under microprocessor control using a transistorized controller. The motor drives the vehicle through a fixed ratio transmission. The second system uses an ac induction motor controlled by transistorized pulse width modulated inverter which drives through a two speed automatically shifted transmission. The inverter and transmission both operate under the control of a microprocessor. The characteristics of these systems are also compared with the propulsion system technology available in vehicles being manufactured at the inception of the DOE program and with an advanced, highly integrated propulsion system upon which technology development was recently initiated.

Horizontal Directional Drilling-Length Detection Technology While Drilling Based on Bi-Electro-Magnetic Sensing.

PubMed

Wang, Yudan; Wen, Guojun; Chen, Han

2017-04-27

The drilling length is an important parameter in the process of horizontal directional drilling (HDD) exploration and recovery, but there has been a lack of accurate, automatically obtained statistics regarding this parameter. Herein, a technique for real-time HDD length detection and a management system based on the electromagnetic detection method with a microprocessor and two magnetoresistive sensors employing the software LabVIEW are proposed. The basic principle is to detect the change in the magnetic-field strength near a current coil while the drill stem and drill-stem joint successively pass through the current coil forward or backward. The detection system consists of a hardware subsystem and a software subsystem. The hardware subsystem employs a single-chip microprocessor as the main controller. A current coil is installed in front of the clamping unit, and two magneto resistive sensors are installed on the sides of the coil symmetrically and perpendicular to the direction of movement of the drill pipe. Their responses are used to judge whether the drill-stem joint is passing through the clamping unit; then, the order of their responses is used to judge the movement direction. The software subsystem is composed of a visual software running on the host computer and a software running in the slave microprocessor. The host-computer software processes, displays, and saves the drilling-length data, whereas the slave microprocessor software operates the hardware system. A combined test demonstrated the feasibility of the entire drilling-length detection system.

Horizontal Directional Drilling-Length Detection Technology While Drilling Based on Bi-Electro-Magnetic Sensing

PubMed Central

Wang, Yudan; Wen, Guojun; Chen, Han

2017-01-01

The drilling length is an important parameter in the process of horizontal directional drilling (HDD) exploration and recovery, but there has been a lack of accurate, automatically obtained statistics regarding this parameter. Herein, a technique for real-time HDD length detection and a management system based on the electromagnetic detection method with a microprocessor and two magnetoresistive sensors employing the software LabVIEW are proposed. The basic principle is to detect the change in the magnetic-field strength near a current coil while the drill stem and drill-stem joint successively pass through the current coil forward or backward. The detection system consists of a hardware subsystem and a software subsystem. The hardware subsystem employs a single-chip microprocessor as the main controller. A current coil is installed in front of the clamping unit, and two magneto resistive sensors are installed on the sides of the coil symmetrically and perpendicular to the direction of movement of the drill pipe. Their responses are used to judge whether the drill-stem joint is passing through the clamping unit; then, the order of their responses is used to judge the movement direction. The software subsystem is composed of a visual software running on the host computer and a software running in the slave microprocessor. The host-computer software processes, displays, and saves the drilling-length data, whereas the slave microprocessor software operates the hardware system. A combined test demonstrated the feasibility of the entire drilling-length detection system. PMID:28448445

Universal control and measuring system for modern classic and amorphous magnetic materials single/on-line strip testers

NASA Astrophysics Data System (ADS)

Zemánek, Ivan; Havlíček, Václav

2006-09-01

A new universal control and measuring system for classic and amorphous soft magnetic materials single/on-line strip testing has been developed at the Czech Technical University in Prague. The measuring system allows to measure magnetization characteristic and specific power losses of different tested materials (strips) at AC magnetization of arbitrary magnetic flux density waveform at wide range of frequencies 20 Hz-20 kHz. The measuring system can be used for both single strip testing in laboratories and on-line strip testing during the production process. The measuring system is controlled by two-stage master-slave control system consisting of the external PC (master) completed by three special A/D measuring plug-in boards, and local executing control unit (slave) with one-chip microprocessor 8051, connected with PC by the RS232 serial line. The "user friendly" powerful control software implemented on the PC and the effective program code for the microprocessor give possibility for full automatic measurement with high measuring power and high measuring accuracy.

Microprocessors: An Understandable Guide for the Classroom Teacher.

ERIC Educational Resources Information Center

Okinaka, Russell T.

A microprocessor constitutes the heart and soul of a personal computer. Indeed, the quality of a personal computer is determined largely by the type of microprocessor that is included within its circuitry. Since the microcomputer revolution began in the late 1970s, these special chips have gone through a series of improvements and modifications.…

Microprocessor design for GaAs technology

NASA Astrophysics Data System (ADS)

Milutinovic, Veljko M.

Recent advances in the design of GaAs microprocessor chips are examined in chapters contributed by leading experts; the work is intended as reading material for a graduate engineering course or as a practical R&D reference. Topics addressed include the methodology used for the architecture, organization, and design of GaAs processors; GaAs device physics and circuit design; design concepts for microprocessor-based GaAs systems; a 32-bit GaAs microprocessor; a 32-bit processor implemented in GaAs JFET; and a direct coupled-FET-logic E/D-MESFET experimental RISC machine. Drawings, micrographs, and extensive circuit diagrams are provided.

Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.

Differences in knee flexion between the Genium and C-Leg microprocessor knees while walking on level ground and ramps.

PubMed

Lura, Derek J; Wernke, Matthew M; Carey, Stephanie L; Kahle, Jason T; Miro, Rebecca M; Highsmith, M Jason

2015-02-01

Microprocessor knees have improved the gait and functional abilities of persons with transfemoral amputation. The Genium prosthetic knee offers an advanced sensor and control system designed to decrease impairment by: allowing greater stance phase flexion, easing transitions between gait phases, and compensating for changes in terrain. The aim of this study was to determine differences between the knee flexion angle of persons using the Genium knee, the C-Leg knee, and non-amputee controls; and to evaluate the impact the prostheses on gait and level of impairment of the user. This study used a randomized experimental crossover of persons with transfemoral amputation using the Genium and C-Leg microprocessor knees (n=25), with an observational sample of non-amputee controls (n=5). Gait analysis by 3D motion tracking of subjects ambulating at different speeds on level ground and on 5° and 10° ramps was completed. Use of the Genium resulted in a significant increase in peak knee flexion for swing (5°, p<0.01, d=0.34) and stance (2°, p<0.01, d=0.19) phases relative to C-Leg use. There was a high degree of variability between subjects, and significant differences still remain between the Genium group and the control group's knee flexion angles for most speeds and slopes. The Genium knee generally increases flexion in swing and stance, potentially decreasing the level of impairment for persons with transfemoral amputation. This study demonstrates functional differences between the C-Leg and Genium knees to help prosthetists determine if the Genium will provide functional benefits to individual patients. Copyright © 2014 Elsevier Ltd. All rights reserved.

Single-chip microprocessor that communicates directly using light

NASA Astrophysics Data System (ADS)

Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

2015-12-01

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Single-chip microprocessor that communicates directly using light.

PubMed

Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

2015-12-24

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Designs and performance of microprocessor-controlled knee joints.

PubMed

Thiele, Julius; Westebbe, Bettina; Bellmann, Malte; Kraft, Marc

2014-02-01

In this comparative study, three transfemoral amputee subjects were fitted with four different microprocessor-controlled exoprosthetic knee joints (MPK): C-Leg, Orion, Plié2.0, and Rel-K. In a motion analysis laboratory, objective gait measures were acquired during level walking at different velocities. Subsequent technical analyses, which involved X-ray computed tomography, identified the functional mechanisms of each device and enabled corroboration of the performance in the gait laboratory by the engineering design of the MPK. Gait measures showed that the mean increase of the maximum knee flexion angle at different walking velocities was closest in value to the unaffected contralateral knee (6.2°/m/s) with C-Leg (3.5°/m/s; Rel-K 17.0°/m/s, Orion 18.3°/m/s, and Plié2.0 28.1°/m/s). Technical analyses corroborated that only with Plié2.0 the flexion resistances were not regulated by microprocessor control at different walking velocities. The muscular effort for the initiation of the swing phase, measured by the minimum hip moment, was found to be lowest with C-Leg (-82.1±14.1 Nm; Rel-K -83.59±17.8 Nm, Orion -88.0±16.3 Nm, and Plié2.0 -91.6±16.5 Nm). Reaching the extension stop at the end of swing phase was reliably executed with both Plié2.0 and C-Leg. Abrupt terminal stance phase extension observed with Plié2.0 and Rel-K could be attributed to the absence of microprocessor control of extension resistance.

Impact of stance phase microprocessor-controlled knee prosthesis on ramp negotiation and community walking function in K2 level transfemoral amputees.

PubMed

Burnfield, Judith M; Eberly, Valerie J; Gronely, Joanne K; Perry, Jacquelin; Yule, William Jared; Mulroy, Sara J

2012-03-01

Microprocessor controlled prosthetic knees (MPK) offer opportunities for improved walking stability and function, but some devices' swing phase features may exceed needs of users with invariable cadence. One MPK offers computerized control of only stance (C-Leg Compact). To assess Medicare Functional Classification Level K2 walkers' ramp negotiation performance, function and balance while using a non-MPK (NMPK) compared to the C-Leg Compact. Crossover. Gait while ascending and descending a ramp (stride characteristics, kinematics, electromyography) and function were assessed in participant's existing NMPK and again in the C-Leg Compact following accommodation. Ramp ascent and descent were markedly faster in the C-Leg Compact compared to the NMPK (p ≤ 0.006), owing to increases in stride length (p ≤ 0.020) and cadence (p ≤ 0.020). Residual limb peak knee flexion and ankle dorsiflexion were significantly greater (12.9° and 4.9° more, respectively) during single limb support while using the C-Leg Compact to descend ramps. Electromyography (mean, peak) did not differ significantly between prosthesis. Function improved in the C-Leg Compact as evidenced by a significantly faster Timed Up and Go and higher functional questionnaire scores. Transfemoral K2 walkers exhibited significantly improved function and balance while using the stance-phase only MPK compared to their traditional NMPK.

A distributed microcomputer-controlled system for data acquisition and power spectral analysis of EEG.

PubMed

Vo, T D; Dwyer, G; Szeto, H H

1986-04-01

A relatively powerful and inexpensive microcomputer-based system for the spectral analysis of the EEG is presented. High resolution and speed is achieved with the use of recently available large-scale integrated circuit technology with enhanced functionality (INTEL Math co-processors 8087) which can perform transcendental functions rapidly. The versatility of the system is achieved with a hardware organization that has distributed data acquisition capability performed by the use of a microprocessor-based analog to digital converter with large resident memory (Cyborg ISAAC-2000). Compiled BASIC programs and assembly language subroutines perform on-line or off-line the fast Fourier transform and spectral analysis of the EEG which is stored as soft as well as hard copy. Some results obtained from test application of the entire system in animal studies are presented.

A COTS-Based Replacement Strategy for Aging Avionics Computers

DTIC Science & Technology

2001-12-01

Communication Control Unit. A COTS-Based Replacement Strategy for Aging Avionics Computers COTS Microprocessor Real Time Operating System New Native Code...Native Code Objec ts Native Code Thread Real - Time Operating System Legacy Function x Virtual Component Environment Context Switch Thunk Add-in Replace

Operation of commercial R3000 processors in the low earth orbit (LEO) space environment

NASA Astrophysics Data System (ADS)

Kaschmitter, J. L.; Shaeffer, D. L.; Colella, N. J.; McKnett, C. L.; Coakley, P. G.

1991-12-01

Spacecraft processors must operate with minimal degradation of performance in the LEO radiation environment, which includes the effects of total accumulated ionizing dose and single event phenomena (SEP) caused by protons and cosmic rays. Commercially available microprocessors can offer a number of advantages relative to radiation-hardened devices but are not normally designed to tolerate effects induced by the LEO environment. Extensive testing of the MIPS R3000 Reduced Instruction Set Computer (RISC) microprocessor family for operation in LEO environments is reported. The authors have characterized total dose and SEP effects for altitudes and inclinations of interest to systems operating in LEO, and they postulate techniques for detection and alleviation of SEP effects based on experimental results.

Microprocessor-based multichannel flutter monitor using dynamic strain gage signals

NASA Technical Reports Server (NTRS)

Smalley, R. R.

1976-01-01

Two microprocessor-based multichannel monitors for monitoring strain gage signals during aerodynamic instability (flutter) testing in production type turbojet engines were described. One system monitors strain gage signals in the time domain and gives an output indication whenever the signal amplitude of any gage exceeds a pre-set alarm or abort level for that particular gage. The second system monitors the strain gage signals in the frequency domain and therefore is able to use both the amplitude and frequency information. Thus, an alarm signal is given whenever the spectral content of the strain gage signal exceeds, at any point, its corresponding amplitude vs. frequency limit profiles. Each system design is described with details on design trade-offs, hardware, software, and operating experience.

One GHz digitizer for space based laser altimeter

NASA Technical Reports Server (NTRS)

Staples, Edward J.

1991-01-01

This is the final report for the research and development of the one GHz digitizer for space based laser altimeter. A feasibility model was designed, built, and tested. Only partial testing of essential functions of the digitizer was completed. Hybrid technology was incorporated which allows analog storage (memory) of the digitally sampled data. The actual sampling rate is 62.5 MHz, but executed in 16 parallel channels, to provide an effective sampling rate of one GHz. The average power consumption of the one GHz digitizer is not more than 1.5 Watts. A one GHz oscillator is incorporated for timing purposes. This signal is also made available externally for system timing. A software package was also developed for internal use (controls, commands, etc.) and for data communication with the host computer. The digitizer is equipped with an onboard microprocessor for this purpose.

COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

ERIC Educational Resources Information Center

Marcovitz, Alan B., Ed.

This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…

COED Transactions, Vol. XI, No. 12, December 1979. Some Alternate Applications of Microprocessor Trainers in Support of Undergraduate Laboratories.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.

Ways are described for the use of a microprocessor trainer in undergraduate laboratories. Listed are microcomputer applications that have been used as demonstrations and which provide signals for other experiments which are not related to microprocessors. Information and figures are provided for methods to do the following: direct generation of…

Microprocessor Based Real-Time Monitoring of Multiple ECG Signals

PubMed Central

Nasipuri, M.; Basu, D.K.; Dattagupta, R.; Kundu, M.; Banerjee, S.

1987-01-01

A microprocessor based system capable of realtime monitoring of multiple ECG signals has been described. The system consists of a number of microprocessors connected in a hierarchical fashion and capable of working concurrently on ECG data collected from different channels. The system can monitor different arrhythmic abnormalities for at least 36 patients even for a heart rate of 500 beats/min.

Road load simulator tests of the Gould phase 1 functional model silicon controlled rectifier ac motor controller for electric vehicles

NASA Astrophysics Data System (ADS)

Gourash, F.

1984-02-01

The test results for a functional model ac motor controller for electric vehicles and a three-phase induction motor which were dynamically tested on the Lewis Research Center road load simulator are presented. Results show that the controller has the capability to meet the SAE-J227a D cycle test schedule and to accelerate a 1576-kg (3456-lb) simulated vehicle to a cruise speed of 88.5 km/hr (55 mph). Combined motor controller efficiency is 72 percent and the power inverter efficiency alone is 89 percent for the cruise region of the D cycle. Steady state test results for motoring, regeneration, and thermal data obtained by operating the simulator as a conventional dynamometer are in agreement with the contractor's previously reported data. The regeneration test results indicate that a reduction in energy requirements for urban driving cycles is attainable with regenerative braking. Test results and data in this report serve as a data base for further development of ac motor controllers and propulsion systems for electric vehicles. The controller uses state-of-the-art silicon controlled rectifier (SCR) power semiconductors and microprocessor-based logic and control circuitry. The controller was developed by Gould Laboratories under a Lewis contract for the Department of Energy's Electric and Hybrid Vehicle program.

Road load simulator tests of the Gould phase 1 functional model silicon controlled rectifier ac motor controller for electric vehicles

NASA Technical Reports Server (NTRS)

Gourash, F.

1984-01-01

The test results for a functional model ac motor controller for electric vehicles and a three-phase induction motor which were dynamically tested on the Lewis Research Center road load simulator are presented. Results show that the controller has the capability to meet the SAE-J227a D cycle test schedule and to accelerate a 1576-kg (3456-lb) simulated vehicle to a cruise speed of 88.5 km/hr (55 mph). Combined motor controller efficiency is 72 percent and the power inverter efficiency alone is 89 percent for the cruise region of the D cycle. Steady state test results for motoring, regeneration, and thermal data obtained by operating the simulator as a conventional dynamometer are in agreement with the contractor's previously reported data. The regeneration test results indicate that a reduction in energy requirements for urban driving cycles is attainable with regenerative braking. Test results and data in this report serve as a data base for further development of ac motor controllers and propulsion systems for electric vehicles. The controller uses state-of-the-art silicon controlled rectifier (SCR) power semiconductors and microprocessor-based logic and control circuitry. The controller was developed by Gould Laboratories under a Lewis contract for the Department of Energy's Electric and Hybrid Vehicle program.

The performance of NASA research hydrogen masers

NASA Technical Reports Server (NTRS)

Reinhardt, V. S.; Rueger, L. J.

1980-01-01

Field operable hydrogen masers based on prior maser designs are presented. These units incorporate improvements in magnetic shielding, lower noise electronics, better thermal control, and have a microprocessor for operation, monitoring, and diagnostic functions. They are ruggedly built for transportability and ease of service anywhere in the world.

Smart motor technology

NASA Technical Reports Server (NTRS)

Packard, D.; Schmitt, D.

1984-01-01

Current spacecraft design relies upon microprocessor control; however, motors usually require extensive additional electronic circuitry to interface with these microprocessor controls. An improved control technique that allows a smart brushless motor to connect directly to a microprocessor control system is described. An actuator with smart motors receives a spacecraft command directly and responds in a closed loop control mode. In fact, two or more smart motors can be controlled for synchronous operation.

The development of a microprocessor-controlled linearly-actuated valve assembly

NASA Technical Reports Server (NTRS)

Wall, R. H.

1984-01-01

The development of a proportional fluid control valve assembly is presented. This electromechanical system is needed for space applications to replace the current proportional flow controllers. The flow is controlled by a microprocessor system that monitors the control parameters of upstream pressure and requested volumetric flow rate. The microprocessor achieves the proper valve stem displacement by means of a digital linear actuator. A linear displacement sensor is used to measure the valve stem position. This displacement is monitored by the microprocessor system as a feedback signal to close the control loop. With an upstream pressure between 15 and 47 psig, the developed system operates between 779 standard CU cm/sec (SCCS) and 1543 SCCS.

Network Interface Specification for the T1 Microprocessor

DTIC Science & Technology

1994-05-01

features data transfer directly to/from processor registers, hardware dispatch directly to Active Message handlers (along with limited context...Implementation Choices 9 3.1 Overview .................................... 9 3.2 Context ..................................... 10 3.3 Data Transfer...details of the data transfer functional units, interconnect structure, and network operation. Application Layer Communication Model Communication

Flight Experiment Demonstration System (FEDS) analysis report

NASA Technical Reports Server (NTRS)

Shank, D. E.

1986-01-01

The purpose of the Flight Experiment Demonstration System (FEDS) was to show, in a simulated spacecraft environment, the feasibility of using a microprocessor to automate the onboard orbit determination functions. The software and hardware configuration used to support FEDS during the demonstration and the results of the demonstration are discussed.

The protein domains of the Dictyostelium microprocessor that are required for correct subcellular localization and for microRNA maturation.

PubMed

Kruse, Janis; Meier, Doreen; Zenk, Fides; Rehders, Maren; Nellen, Wolfgang; Hammann, Christian

2016-10-02

The maturation pathways of microRNAs (miRNAs) have been delineated for plants and several animals, belonging to the evolutionary supergroups of Archaeplastida and Opisthokonta, respectively. Recently, we reported the discovery of the microprocessor complex in Dictyostelium discoideum of the Amoebozoa supergroup. The complex is composed of the Dicer DrnB and the dsRBD (double-stranded RNA binding domain) containing protein RbdB. Both proteins localize at nucleoli, where they physically interact, and both are required for miRNA maturation. Here we show that the miRNA phenotype of a ΔdrnB gene deletion strain can be rescued by ectopic expression of a series of DrnB GFP fusion proteins, which consistently showed punctate perinucleolar localization in fluorescence microscopy. These punctate foci appear surprisingly stable, as they persist both disintegration of nucleoli and degradation of cellular nucleic acids. We observed that DrnB expression levels influence the number of microprocessor foci and alter RbdB accumulation. An investigation of DrnB variants revealed that its newly identified nuclear localization signal is necessary, but not sufficient for the perinucleolar localization. Biogenesis of miRNAs, which are RNA Pol II transcripts, is correlated with that localization. Besides its bidentate RNase III domains, DrnB contains only a dsRBD, which surprisingly is dispensable for miRNA maturation. This dsRBD can, however, functionally replace the homologous domain in RbdB. Based on the unique setup of the Dictyostelium microprocessor with a subcellular localization similar to plants, but a protein domain composition similar to animals, we propose a model for the evolutionary origin of RNase III proteins acting in miRNA maturation.

Cell cycle-dependent regulation of Aurora kinase B mRNA by the Microprocessor complex.

PubMed

Jung, Eunsun; Seong, Youngmo; Seo, Jae Hong; Kwon, Young-Soo; Song, Hoseok

2014-03-28

Aurora kinase B regulates the segregation of chromosomes and the spindle checkpoint during mitosis. In this study, we showed that the Microprocessor complex, which is responsible for the processing of the primary transcripts during the generation of microRNAs, destabilizes the mRNA of Aurora kinase B in human cells. The Microprocessor-mediated cleavage kept Aurora kinase B at a low level and prevented premature entrance into mitosis. The cleavage was reduced during mitosis leading to the accumulation of Aurora kinase B mRNA and protein. In addition to Aurora kinase B mRNA, the processing of other primary transcripts of miRNAs were also decreased during mitosis. We found that the cleavage was dependent on an RNA helicase, DDX5, and the association of DDX5 and DDX17 with the Microprocessor was reduced during mitosis. Thus, we propose a novel mechanism by which the Microprocessor complex regulates stability of Aurora kinase B mRNA and cell cycle progression. Copyright © 2014 Elsevier Inc. All rights reserved.

Development and Field Test of the Trial Battery for Project A

DTIC Science & Technology

1987-05-01

cognitive, temperament, biographical data, and vocational interest) were investigated to detect excessive redundancy among the PB measures, especially ...abili- ties. The literature review procedures were described earlier. Almost no literature was available on computerized, especially microprocessor-driven...Lhese questions, and it is acknowledged that research is necessary to obtain answers, especially with micropro- cessor-driven testing methods. Phase 3

Microprocessor-controlled optical stimulating device to improve the gait of patients with Parkinson's disease.

PubMed

Ferrarin, M; Brambilla, M; Garavello, L; Di Candia, A; Pedotti, A; Rabuffetti, M

2004-05-01

Different types of visual cue for subjects with Parkinson's disease (PD) produced an improvement in gait and helped some of them prevent or overcome freezing episodes. The paper describes a portable gait-enabling device (optical stimulating glasses (OSGs) that provides, in the peripheral field of view, different types of continuous optic flow (backward or forward) and intermittent stimuli synchronised with external events. The OSGs are a programmable, stand-alone, augmented reality system that can be interfaced with a PC for program set-up. It consists of a pair of non-corrective glasses, equipped with two matrixes of 70 micro light emitting diodes, one on each side, controlled by a microprocessor. Two foot-switches are used to synchronise optical stimulation with specific gait events. A pilot study was carried out on three PD patients and three controls, with different types of optic flow during walking along a fixed path. The continuous optic flow in the forward direction produced an increase in gait velocity in the PD patients (up to + 11% in average), whereas the controls had small variations. The stimulation synchronised with the swing phase, associated with an attentional strategy, produced a remarkable increase in stride length for all subjects. After prolonged testing, the device has shown good applicability and technical functionality, it is easily wearable and transportable, and it does not interfere with gait.

A Microprocessor-Based Real-Time Simulator of a Turbofan Engine

DTIC Science & Technology

1988-01-01

NASA AVSCOM Technical Memorandum 100889 Technical Report 88-C-011 Lfl A Microprocessor-Based Real-Time Simulator of a Turbofan Engine CD I Jonathan S...Accession For NTIS GRA&I A MICROPROCESSOR-BASED REAL-TIME SIMULATOR DTIC TABUnannounced OF A TURBOFAN ENGINE Justifiaation, Jonathan S. Litt Propulsion...the F100 engine without augmentation (without afterburning). HYTESS is a simplified simulation written in FORTRAN of a generalized turbofan engine . To

Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

DTIC Science & Technology

2015-03-10

for Public Release; Distribution Unlimited Final Report: Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor The views...P.O. Box 12211 Research Triangle Park, NC 27709-2211 Superconductor technology, RSFQ, RQL, processor design, arithmetic units, high-performance...Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor Report Title The major objective of the project was to design and demonstrate operation

Pain and efficacy rating of a microprocessor-controlled metered injection system for local anaesthesia in minor hand surgery.

PubMed

Nimigan, André S; Gan, Bing Siang

2011-01-01

Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P = .0002). This same group, however, has significantly longer injection times (P < .0001). Pain during the injection process or during surgery was not different between the two groups. Conclusions. This RCT comparing traditional and microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.

San Diego field operational test of smart call boxes : technical aspects

DOT National Transportation Integrated Search

1997-01-01

Smart call boxes are devices similar to those used as emergency call boxes in California. The basic call box consists of a microprocessor, a cellular transceiver, and a solar power source. The smart call box system also includes data-collection devic...

Army/NASA small turboshaft engine digital controls research program

NASA Technical Reports Server (NTRS)

Sellers, J. F.; Baez, A. N.

1981-01-01

The emphasis of a program to conduct digital controls research for small turboshaft engines is on engine test evaluation of advanced control logic using a flexible microprocessor based digital control system designed specifically for research on advanced control logic. Control software is stored in programmable memory. New control algorithms may be stored in a floppy disk and loaded directly into memory. This feature facilitates comparative evaluation of different advanced control modes. The central processor in the digital control is an Intel 8086 16 bit microprocessor. Control software is programmed in assembly language. Software checkout is accomplished prior to engine test by connecting the digital control to a real time hybrid computer simulation of the engine. The engine currently installed in the facility has a hydromechanical control modified to allow electrohydraulic fuel metering and VG actuation by the digital control. Simulation results are presented which show that the modern control reduces the transient rotor speed droop caused by unanticipated load changes such as cyclic pitch or wind gust transients.

Stair ascent with an innovative microprocessor-controlled exoprosthetic knee joint.

PubMed

Bellmann, Malte; Schmalz, Thomas; Ludwigs, Eva; Blumentritt, Siegmar

2012-12-01

Climbing stairs can pose a major challenge for above-knee amputees as a result of compromised motor performance and limitations to prosthetic design. A new, innovative microprocessor-controlled prosthetic knee joint, the Genium, incorporates a function that allows an above-knee amputee to climb stairs step over step. To execute this function, a number of different sensors and complex switching algorithms were integrated into the prosthetic knee joint. The function is intuitive for the user. A biomechanical study was conducted to assess objective gait measurements and calculate joint kinematics and kinetics as subjects ascended stairs. Results demonstrated that climbing stairs step over step is more biomechanically efficient for an amputee using the Genium prosthetic knee than the previously possible conventional method where the extended prosthesis is trailed as the amputee executes one or two steps at a time. There is a natural amount of stress on the residual musculoskeletal system, and it has been shown that the healthy contralateral side supports the movements of the amputated side. The mechanical power that the healthy contralateral knee joint needs to generate during the extension phase is also reduced. Similarly, there is near normal loading of the hip joint on the amputated side.

Experience in the installation of a microprocessor system for controlling converter units of the Vyborg substation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gusakovskii, K. B.; Zmaznov, E. Yu.; Katantsev, S. V.

The experience in the installation of modern digital systems for controlling converter units at the Vyborg converter substation on the basis of advanced microprocessor devices is considered. It is shown that debugging of a control and protection system on mathematical and physical models does not guarantee optimum control of actual converter devices. Examples of advancing the control and protection system are described, the necessity for which has become obvious in tests of actual equipment. Comparison of oscillograms of processes before optimization of the control system and after its optimization and adjustment shows that the digital control system makes it possiblemore » to improve substantially the algorithms of control and protection in the short term and without changing the hardware component.« less

Aerospace Applications of Microprocessors

NASA Technical Reports Server (NTRS)

1980-01-01

An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed.

Formal proof of the AVM-1 microprocessor using the concept of generic interpreters

NASA Technical Reports Server (NTRS)

Windley, P.; Levitt, K.; Cohen, G. C.

1991-01-01

A microprocessor designated AVM-1 was designed to demonstrate the use of generic interpreters in verifying hierarchically decomposed microprocessor specifications. This report is intended to document the high-order language (HOL) code verifying AVM-1. The organization of the proof is discussed and some technical details concerning the execution of the proof scripts in HOL are presented. The proof scripts used to verify AVM-1 are also presented.

Full temperature single event upset characterization of two microprocessor technologies

NASA Technical Reports Server (NTRS)

Nichols, Donald K.; Coss, James R.; Smith, L. S.; Rax, Bernard; Huebner, Mark

1988-01-01

Data for the 9450 I3L bipolar microprocessor and the 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full MIL-SPEC temperature range of -55 to 125 C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different.

The design of a microprocessor-based data logger

USGS Publications Warehouse

Leap, K.J.; Dedini, L.A.

1982-01-01

The design of a microprocessor-based data logger, which collects and digitizes analog voltage signals from a continuous-measuring instrumentation system and transmits serial data to a magnetic tape recorder, is discussed. The data logger was assembled from commercially-available components and can be user-programmed for greater flexibility. A description of the data logger hardware and software designs, general operating instructions, the microprocessor program listing, and electrical schematic diagrams are presented.

PDSparc: A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-09-24

Kate   Thurmer  MIT  Lincoln  Laboratory,  Lexington,   MA,  USA Distribution A: Public Release   ABSTRACT   Microprocessors are the...enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors usually start...out as soft-cores that are parameterized at design time to realize exclusively the specific needs of the application. The microprocessor is a small

Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

DTIC Science & Technology

2016-02-05

SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they... microprocessors in a way that they can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of...Progress The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they can be added and

Automated mixed traffic transit vehicle microprocessor controller

NASA Technical Reports Server (NTRS)

Marks, R. A.; Cassell, P.; Johnston, A. R.

1981-01-01

An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

Mold heating and cooling microprocessor conversion. Final report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hoffman, D.P.

Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessormore » board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.« less

DOE Office of Scientific and Technical Information (OSTI.GOV)

Winterbone, D.E.; Richards, P.

A microprocessor controlled test bed was built for steady state mapping of petrol engines using a sweep mapping technique. The addition of an electric motor to the fast acting dynamometer allowed rapid load changes to be applied at nominally constant speed. This made it possible to consider the dynamic behaviour of the power generation sub-system of the engine. The engine was initially subjected to ramp changes of torque but these did not give consistent results. PRBS signals were then used for the same variable and a mathematical transfer function model developed for the engine power system. The engine was consideredmore » both as a continuous and sample data system. Results will be presented which show fuel management has an appreciable effect on the engine dynamic response.« less

A versatile microprocessor-controlled hybrid receiver. [with firmware control for operation over large frequency uncertainty

NASA Technical Reports Server (NTRS)

Grant, T. L.

1978-01-01

A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.

Debris measure subsystem of the nanosatellite IRECIN

NASA Astrophysics Data System (ADS)

Ferrante, M.; di Ciolo, L.; Ortenzi, A.; Petrozzi, M.; del Re, V.

2003-09-01

The on board resources, needed to perform the mission tasks, are very limited in nano-satellites. This paper proposes an Electronic real-time system that acquires space debris measures. It uses a piezo-electric sensor. The described device is a subsystem on board of the IRECIN nanosatellite composed mainly by a r.i.s.c. microprocessor, an electronic part that interfaces to the debris sensor in order to provide a low noise electrical and suitable range to ADC 12 bit converter, and finally a memory in order to store the data. The microprocessor handles the Debris Measure System measuring the impacts number, their intensity and storing their waves form. This subsystem is able to communicate with the other IRECIN subsystems through I2C Bus and principally with the "Main Microprocessor" subsystem allowing the data download directly to the Ground Station. Moreover this subsystem lets free the "Main Microprocessor Board" from the management and charge of debris data. All electronic components are SMD technology in order to reduce weight and size. The realized Electronic board are completely developed, realized and tested at the Vitrociset S.P.A. under control of Research and Development Group. The proposed system is implemented on the IRECIN, a modular nanosatellite weighting less than 1.5 kg, constituted by sixteen external sides with surface-mounted solar cells and three internal Al plates, kept together by four steel bars. Lithium-ions batteries are added for eclipse operations. Attitude is determined by two three-axis magnetometers and the solar panels data. Control is provided by an active magnetic control system. The spacecraft will be spin-stabilized with the spin-axis normal to the orbit. debris and micrometeoroids mass and velocity.

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2013 CFR

2013-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2012 CFR

2012-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2011 CFR

2011-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2010 CFR

2010-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

49 CFR 661.7 - Waivers.

Code of Federal Regulations, 2014 CFR

2014-10-01

... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

Quasi-elastic light scattering: Signal storage, correlation, and spectrum analysis under control of an 8-bit microprocessor

NASA Astrophysics Data System (ADS)

Glatter, Otto; Fuchs, Heribert; Jorde, Christian; Eigner, Wolf-Dieter

1987-03-01

The microprocessor of an 8-bit PC system is used as a central control unit for the acquisition and evaluation of data from quasi-elastic light scattering experiments. Data are sampled with a width of 8 bits under control of the CPU. This limits the minimum sample time to 20 μs. Shorter sample times would need a direct memory access channel. The 8-bit CPU can address a 64-kbyte RAM without additional paging. Up to 49 000 sample points can be measured without interruption. After storage, a correlation function or a power spectrum can be calculated from such a primary data set. Furthermore access is provided to the primary data for stability control, statistical tests, and for comparison of different evaluation methods for the same experiment. A detailed analysis of the signal (histogram) and of the effect of overflows is possible and shows that the number of pulses but not the number of overflows determines the error in the result. The correlation function can be computed with reasonable accuracy from data with a mean pulse rate greater than one, the power spectrum needs a three times higher pulse rate for convergence. The statistical accuracy of the results from 49 000 sample points is of the order of a few percent. Additional averages are necessary to improve their quality. The hardware extensions for the PC system are inexpensive. The main disadvantage of the present system is the high minimum sampling time of 20 μs and the fact that the correlogram or the power spectrum cannot be computed on-line as it can be done with hardware correlators or spectrum analyzers. These shortcomings and the storage size restrictions can be removed with a faster 16/32-bit CPU.

An Innovative Method of Teaching Electronic System Design with PSoC

ERIC Educational Resources Information Center

Ye, Zhaohui; Hua, Chengying

2012-01-01

Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

Microprocessor Controlled Isometric Contractions of Cat Gastrocnemius Muscle.

DTIC Science & Technology

1981-12-01

A-A15 504 AIR FORCE INST OF TECH WRIGHT-PATTERSON AFS OH 5CHOO--ETC F/6 6/2 MICROPROCESSOR CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROC-ETC(U) D...CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROCNEMIUS MUSCLE THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of...1981 Appzoved for public release; distribution unlimited. AFIT/GE/EE/81D-4O \\ MICROPROCESSOR CONTROLLED ISOMETRIC COMUtCTIONS OF CAT GASTfOCNEMIUS i

Microprocessor based implementation of attitude and shape control of large space structures

NASA Technical Reports Server (NTRS)

Reddy, A. S. S. R.

1984-01-01

The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.

Global identification of target recognition and cleavage by the Microprocessor in human ES cells

PubMed Central

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-01-01

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein–RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3′ overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. PMID:25326327

Multitasking operating systems for microprocessors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cramer, T.

1981-01-01

Microprocessors, because of their low cost, low power consumption, and small size, have caused an explosion in the number of innovative computer applications. Although there is a great deal of variation in microprocessor applications software, there is relatively little variation in the operating-system-level software from one application to the next. Nonetheless, operating system software, especially when multitasking is involved, can be very time consuming and expensive to develop. The major microprocessor manufacturers have acknowledged the need for operating systems in microprocessor applications and are now supplying real-time multitasking operating system software that is adaptable to a wide variety of usermore » systems. Use of this existing operating system software will decrease the number of redundant operating system development efforts, thus freeing programmers to work on more creative and productive problems. This paper discusses the basic terminology and concepts involved with multitasking operating systems. It is intended to provide a general understanding of the subject, so that the reader will be prepared to evaluate specific operating system software according to his or her needs. 2 references.« less

Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

NASA Astrophysics Data System (ADS)

Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

2018-03-01

We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

Robust Duplication with Comparison Methods in Microcontrollers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

Robust Duplication with Comparison Methods in Microcontrollers

DOE PAGES

Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.; ...

2016-01-01

Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

Preprototype SAWD subsystem

NASA Technical Reports Server (NTRS)

Nalette, T. A.

1984-01-01

A regenerable, three man preprototype solid amine, water desorbed (SAWD) CO2 removal and concentation subsystem was designed, fabricated, and successfully acceptance tested by Hamilton Standard. The preprototype SAWD incorporates a single solid amine canister to perform the CO2 removal function, an accumulator to provide the CO2 storage and delivery function, and a microprocessor which automatically controls the subsystem sequential operation and performance. The SAWD subsystem was configured to have a CO2 removal and CO2 delivery capability at the rate of 0.12 kg/hr (0.264 lb/hr) over the relative humidity range of 35 to 70%. The controller was developed to provide fully automatic control over the relative humidity range via custom software that was generated specifically for the SAWD subsystem. The preprototype SAWD subsystem demonstrated a total of 281 hours (208) cycles of operation during ten acceptance tests that were conducted over the 3 to 70% relative humidity range. This operation was comprised of 178 hours (128 cycles) in the CO2 overboard mode and 103 hours (80 cycles) in the CO2 reduction mode. The average CO2 removal/delivery rate met or exceeded the design specification rate of 0.12 kg/hr (0.254 lb/hr) for all ten of the acceptance tests.

RCTS: A flexible environment for sensor integration and control of robot systems; the distributed processing approach

NASA Technical Reports Server (NTRS)

Allard, R.; Mack, B.; Bayoumi, M. M.

1989-01-01

Most robot systems lack a suitable hardware and software environment for the efficient research of new control and sensing schemes. Typically, engineers and researchers need to be experts in control, sensing, programming, communication and robotics in order to implement, integrate and test new ideas in a robot system. In order to reduce this time, the Robot Controller Test Station (RCTS) has been developed. It uses a modular hardware and software architecture allowing easy physical and functional reconfiguration of a robot. This is accomplished by emphasizing four major design goals: flexibility, portability, ease of use, and ease of modification. An enhanced distributed processing version of RCTS is described. It features an expanded and more flexible communication system design. Distributed processing results in the availability of more local computing power and retains the low cost of microprocessors. A large number of possible communication, control and sensing schemes can therefore be easily introduced and tested, using the same basic software structure.

Hypoxia, Monitoring, and Mitigation System

DTIC Science & Technology

2015-08-01

Oxygen Saturation Measured via Pulse - Oximeter SRS Software Requirements Specification SW Software TI Texas Instruments uPROC Micro-Processor USAARL...Financial) Table of Figures Figure 1: Pulse OX custom module...Tasks 3, 4 and 5 have not been exercised. Sensor definition testing continued on the custom pulse -ox design. Additional refinement on the pulse

Comparison of mobility and user satisfaction between a microprocessor knee and a standard prosthetic knee: a summary of seven single-subject trials.

PubMed

Howard, Charla L; Wallace, Chris; Perry, Bonnie; Stokic, Dobrivoje S

2018-03-01

Insufficient evidence of the benefits provided by costlier microprocessor knees (MPKs) over nonmicroprocessor knees (NMPKs) often causes concern when considering MPK prescription. Thus, more studies are needed to demonstrate differences between MPKs and NMPKs and define sensitive outcomes to guide MPK prescription. The aim of this study was to evaluate the impact of switching from NMPK to MPK on measures of mobility and preference. Seven long-term NMPK users (all men, ages 50-84, 3-64 years postamputation) participated in this study, which use a single-subject design (ABA or BAB; A=NMPK, B=MPK). Mobility was assessed with the Amputee Mobility Predictor, Berg Balance Scale (BBS), L-Test, 6-Min Walk Test (6MWT) with Physiological Cost Index, and self-selected normal and very fast gait speeds. The preference between NMPK and MPK was evaluated by the Prosthesis Evaluation Questionnaire (PEQ) and the visual analog scale. Mobility improved with the MPK in six of seven participants, which was most often captured with BBS (median: +6 points) and 6MWT (median: +63 m). These improvements typically exceeded minimal clinically important difference or minimal detectable change thresholds. Most participants scored the MPK higher on the PEQ (median: +20 points) and six of seven expressed a global preference toward MPK. In the BAB group, the Amputee Mobility Predictor and BBS correlated with perception of change on several PEQ domains (Ρ≥0.59). In conclusion, MPKs may provide better outcomes and user satisfaction, particularly in those with lower mobility function. BBS and 6MWT were found to be the most sensitive measures to capture changes in mobility while using MPK for several weeks.

Anti-Hassle Chip

NASA Technical Reports Server (NTRS)

1998-01-01

With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.

PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

DTIC Science & Technology

2015-08-18

Written Using  Synopsys Processor Designer1  David Whelihan, Ph.D. and Kate Thurmer  MIT Lincoln Laboratory, Lexington, MA, USA    ABSTRACT  Microprocessors ...internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors... microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its

Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Frokh; Farmanesh, Farhad F.; Swift, Gary M.; Johnston, Allen H.

2004-01-01

This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

A Fault-tolerant RISC Microprocessor for Spacecraft Applications

NASA Technical Reports Server (NTRS)

Timoc, Constantin; Benz, Harry

1990-01-01

Viewgraphs on a fault-tolerant RISC microprocessor for spacecraft applications are presented. Topics covered include: reduced instruction set computer; fault tolerant registers; fault tolerant ALU; and double rail CMOS logic.

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2012 CFR

2012-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2013 CFR

2013-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

49 CFR 229.23 - Periodic inspection: general.

Code of Federal Regulations, 2014 CFR

2014-10-01

... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

On-board landmark navigation and attitude reference parallel processor system

NASA Technical Reports Server (NTRS)

Gilbert, L. E.; Mahajan, D. T.

1978-01-01

An approach to autonomous navigation and attitude reference for earth observing spacecraft is described along with the landmark identification technique based on a sequential similarity detection algorithm (SSDA). Laboratory experiments undertaken to determine if better than one pixel accuracy in registration can be achieved consistent with onboard processor timing and capacity constraints are included. The SSDA is implemented using a multi-microprocessor system including synchronization logic and chip library. The data is processed in parallel stages, effectively reducing the time to match the small known image within a larger image as seen by the onboard image system. Shared memory is incorporated in the system to help communicate intermediate results among microprocessors. The functions include finding mean values and summation of absolute differences over the image search area. The hardware is a low power, compact unit suitable to onboard application with the flexibility to provide for different parameters depending upon the environment.

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

NASA Technical Reports Server (NTRS)

Trotter, J. D.

1982-01-01

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Operating system for a real-time multiprocessor propulsion system simulator. User's manual

NASA Technical Reports Server (NTRS)

Cole, G. L.

1985-01-01

The NASA Lewis Research Center is developing and evaluating experimental hardware and software systems to help meet future needs for real-time, high-fidelity simulations of air-breathing propulsion systems. Specifically, the real-time multiprocessor simulator project focuses on the use of multiple microprocessors to achieve the required computing speed and accuracy at relatively low cost. Operating systems for such hardware configurations are generally not available. A real time multiprocessor operating system (RTMPOS) that supports a variety of multiprocessor configurations was developed at Lewis. With some modification, RTMPOS can also support various microprocessors. RTMPOS, by means of menus and prompts, provides the user with a versatile, user-friendly environment for interactively loading, running, and obtaining results from a multiprocessor-based simulator. The menu functions are described and an example simulation session is included to demonstrate the steps required to go from the simulation loading phase to the execution phase.

Report on the formal specification and partial verification of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Brock, Bishop; Hunt, Warren A., Jr.

1991-01-01

The VIPER microprocessor chip is partitioned into four levels of abstractions. At the highest level, VIPER is described with decreasingly abstract sets of functions in LCF-LSM. At the lowest level are the gate-level models in proprietary CAD languages. The block-level and gate-level specifications are also given in the ELLA simulation language. Among VIPER's deficiencies are the fact that there is no notion of external events in the top-level specification, and it is impossible to use the top-level specifications to prove abstract properties of programs running on VIPER computers. There is no complete proof that the gate-level specifications implement the top-level specifications. Cohn's proof that the major-state machine correctly implements the top-level specifications has no formal connection with any of the other proof attempts. None of the latter address resetting the machine, memory timeout, forced error, or single step modes.

A Fourier transform with speed improvements for microprocessor applications

NASA Technical Reports Server (NTRS)

Lokerson, D. C.; Rochelle, R.

1980-01-01

A fast Fourier transform algorithm for the RCA 1802microprocessor was developed for spacecraft instrument applications. The computations were tailored for the restrictions an eight bit machine imposes. The algorithm incorporates some aspects of Walsh function sequency to improve operational speed. This method uses a register to add a value proportional to the period of the band being processed before each computation is to be considered. If the result overflows into the DF register, the data sample is used in computation; otherwise computation is skipped. This operation is repeated for each of the 64 data samples. This technique is used for both sine and cosine portions of the computation. The processing uses eight bit data, but because of the many computations that can increase the size of the coefficient, floating point form is used. A method to reduce the alias problem in the lower bands is also described.

FAME, a microprocessor based front-end analysis and modeling environment

NASA Technical Reports Server (NTRS)

Rosenbaum, J. D.; Kutin, E. B.

1980-01-01

Higher order software (HOS) is a methodology for the specification and verification of large scale, complex, real time systems. The HOS methodology was implemented as FAME (front end analysis and modeling environment), a microprocessor based system for interactively developing, analyzing, and displaying system models in a low cost user-friendly environment. The nature of the model is such that when completed it can be the basis for projection to a variety of forms such as structured design diagrams, Petri-nets, data flow diagrams, and PSL/PSA source code. The user's interface with the analyzer is easily recognized by any current user of a structured modeling approach; therefore extensive training is unnecessary. Furthermore, when all the system capabilities are used one can check on proper usage of data types, functions, and control structures thereby adding a new dimension to the design process that will lead to better and more easily verified software designs.

A Micro-Processor Based System as a Teaching Tool.

ERIC Educational Resources Information Center

Spero, Samuel W.

1979-01-01

Two instructional strategies incorporating a microprocessor-based computer system are described. These are the use of the system to drive a television monitor, and the system's use in generating problem sets. (MP)

40 CFR Appendix F to Part 60 - Quality Assurance Procedures

Code of Federal Regulations, 2012 CFR

2012-07-01

... automatically adjust the data to the corrected calibration values (e.g., microprocessor control) must be... calibration values (e.g., microprocessor control), you must program your PM CEMS to record the unadjusted...

Distributed asynchronous microprocessor architectures in fault tolerant integrated flight systems

NASA Technical Reports Server (NTRS)

Dunn, W. R.

1983-01-01

The paper discusses the implementation of fault tolerant digital flight control and navigation systems for rotorcraft application. It is shown that in implementing fault tolerance at the systems level using advanced LSI/VLSI technology, aircraft physical layout and flight systems requirements tend to define a system architecture of distributed, asynchronous microprocessors in which fault tolerance can be achieved locally through hardware redundancy and/or globally through application of analytical redundancy. The effects of asynchronism on the execution of dynamic flight software is discussed. It is shown that if the asynchronous microprocessors have knowledge of time, these errors can be significantly reduced through appropiate modifications of the flight software. Finally, the papear extends previous work to show that through the combined use of time referencing and stable flight algorithms, individual microprocessors can be configured to autonomously tolerate intermittent faults.

Global identification of target recognition and cleavage by the Microprocessor in human ES cells.

PubMed

Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

2014-11-10

The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein-RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3' overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. © The Author(s) 2014. Published by Oxford University Press on behalf of Nucleic Acids Research.

A portable battery for objective, non-obstrusive measures of human performances

NASA Technical Reports Server (NTRS)

Kennedy, R. S.

1984-01-01

The need for a standardized battery of human performance tests to measure the effects of various treatments is pointed out. Progress in such a program is reported. Three batteries are available which differ in length and the number of tests in the battery. All tests are implemented on a portable, lap held, briefcase size microprocessor. Performances measured include: information processing, memory, visual perception, reasoning, and motor skills, programs to determine norms, reliabilities, stabilities, factor structure of tests, comparisons with marker tests, apparatus suitability. Rationale for the battery is provided.

Benefits of microprocessor-controlled prosthetic knees to limited community ambulators: systematic review.

PubMed

Kannenberg, Andreas; Zacharias, Britta; Pröbsting, Eva

2014-01-01

The benefits of microprocessor-controlled prosthetic knees (MPKs) have been well established in community ambulators (Medicare Functional Classification Level [MFCL]-3) with a transfemoral amputation (TFA). A systematic review of the literature was performed to analyze whether limited community ambulators (MFCL-2) may also benefit from using an MPK in safety, performance-based function and mobility, and perceived function and satisfaction. We searched 10 scientific databases for clinical trials with MPKs and identified six publications with 57 subjects with TFA and MFCL-2 mobility grade. Using the criteria of a Cochrane Review on prosthetic components, we rated methodological quality moderate in four publications and low in two publications. MPK use may significantly reduce uncontrolled falls by up to 80% as well as significantly improve indicators of fall risk. Performance-based outcome measures suggest that persons with MFCL-2 mobility grade may be able to walk about 14% to 25% faster on level ground, be around 20% quicker on uneven surfaces, and descend a slope almost 30% faster when using an MPK. The results of this systematic review suggest that trial fittings may be used to determine whether or not individuals with TFA and MFCL-2 mobility grade benefit from MPK use. Criteria for patient selection and assessment of trial fitting success or failure are proposed.

Microprocessor Recruitment to Elongating RNA Polymerase II Is Required for Differential Expression of MicroRNAs.

PubMed

Church, Victoria A; Pressman, Sigal; Isaji, Mamiko; Truscott, Mary; Cizmecioglu, Nihal Terzi; Buratowski, Stephen; Frolov, Maxim V; Carthew, Richard W

2017-09-26

The cellular abundance of mature microRNAs (miRNAs) is dictated by the efficiency of nuclear processing of primary miRNA transcripts (pri-miRNAs) into pre-miRNA intermediates. The Microprocessor complex of Drosha and DGCR8 carries this out, but it has been unclear what controls Microprocessor's differential processing of various pri-miRNAs. Here, we show that Drosophila DGCR8 (Pasha) directly associates with the C-terminal domain of the RNA polymerase II elongation complex when it is phosphorylated by the Cdk9 kinase (pTEFb). When association is blocked by loss of Cdk9 activity, a global change in pri-miRNA processing is detected. Processing of pri-miRNAs with a UGU sequence motif in their apical junction domain increases, while processing of pri-miRNAs lacking this motif decreases. Therefore, phosphorylation of RNA polymerase II recruits Microprocessor for co-transcriptional processing of non-UGU pri-miRNAs that would otherwise be poorly processed. In contrast, UGU-positive pri-miRNAs are robustly processed by Microprocessor independent of RNA polymerase association. Copyright © 2017 The Author(s). Published by Elsevier Inc. All rights reserved.

75 FR 22174 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

Federal Register 2010, 2011, 2012, 2013, 2014

2010-04-27

... passive antitheft device installed on the Porsche Panamera includes a microprocessor-based immobilizer... modified antitheft system will now consist of a microprocessor based immobilizer system which prevents...

Low cost airborne microwave landing system receiver, task 3

NASA Technical Reports Server (NTRS)

Hager, J. B.; Vancleave, J. R.

1979-01-01

Work performed on the low cost airborne Microwave Landing System (MLS) receiver is summarized. A detailed description of the prototype low cost MLS receiver is presented. This detail includes block diagrams, schematics, board assembly drawings, photographs of subassemblies, mechanical construction, parts lists, and microprocessor software. Test procedures are described and results are presented.

Microprocessors: the engines of the digital age

PubMed Central

2017-01-01

The microprocessor—a computer central processing unit integrated onto a single microchip—has come to dominate computing across all of its scales from the tiniest consumer appliance to the largest supercomputer. This dominance has taken decades to achieve, but an irresistible logic made the ultimate outcome inevitable. The objectives of this Perspective paper are to offer a brief history of the development of the microprocessor and to answer questions such as: where did the microprocessor come from, where is it now, and where might it go in the future? PMID:28413353

Evaluation of the performance of microprocessor-based colorimeter

PubMed Central

Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments. PMID:18924952

Evaluation of the performance of microprocessor-based colorimeter.

PubMed

Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

1992-01-01

Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.

Neutron beam irradiation study of workload dependence of SER in a microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Michalak, Sarah E; Graves, Todd L; Hong, Ted

It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

An optimal controller for an electric ventricular-assist device: theory, implementation, and testing.

PubMed

Klute, G K; Tasch, U; Geselowitz, D B

1992-04-01

This paper addresses the development and testing of an optimal position feedback controller for the Penn State electric ventricular-assist device (EVAD). The control law is designed to minimize the expected value of the EVAD's power consumption for a targeted patient population. The closed-loop control law is implemented on an Intel 8096 microprocessor and in vitro test runs show that this controller improves the EVAD's efficiency by 15-21%, when compared with the performance of the currently used feedforward control scheme.

Upset due to a single particle caused propagated transients in a bulk CMOS microprocessor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Leavy, J.F.; Hoffmann, L.F.; Shoran, R.W.

1991-12-01

This paper reports on data pattern advances observed in preset, single event upset (SEU) hardened clocked flip-flops, during static Cf-252 exposures on a bulk CMOS microprocessor, that were attributable to particle caused anomalous clock signals, or propagated transients. SPICE simulations established that particle strikes in the output nodes of a clock control logic flip-flop could produce transients of sufficient amplitude and duration to be accepted as legitimate pulses by clock buffers fed by the flip-flop's output nodes. The buffers would then output false clock pulses, thereby advancing the state of the present flip-flops. Masking the clock logic on one ofmore » the test chips made the flip-flop data advance cease, confirming the clock logic as the source of the SEU. By introducing N{sub 2} gas, at reduced pressures, into the SEU test chamber to attenuate Cf-252 particle LET's, a 24-26 MeV-cm{sup 2}/mg LET threshold was deduced. Subsequent tests, at the 88-inch cyclotron at Berkeley, established an LET threshold of 30 MeV-cm{sup 2}/mg (283 MeV Cu at 0{degrees}) for the generation of false clocks. Cyclotron SEU tests are considered definitive, while Cf-252 data usually is not. However, in this instance Cf-252 tests proved analytically useful, providing SEU characterization data that was both timely and inexpensive.« less

A MICROPROCESSOR ASCII CHARACTER BUFFERING SYSTEM

EPA Science Inventory

A microprocessor buffering system (MBS) was developed at the Environmental Monitoring and Support Laboratory -Cincinnati (EMSL-CI) to provide an efficient transfer for serial ASCII information between intelligent instrument systema and a Data General NOVA laboratory automation co...

MICROPROCESSOR CONTROL OF ROTOGRAVURE AIRFLOWS

EPA Science Inventory

The report discusses the technical and economic viability of using micro-processor-based control technology to collect volatile organic compound (VOC) emissions from a paper coating operation. The microprocessor-based control system monitors and controls both the airflow rate and...

78 FR 53500 - Petition for Exemption From the Federal Motor Vehicle Theft Prevention Standard; Chrysler

Federal Register 2010, 2011, 2012, 2013, 2014

2013-08-29

...) transceiver and a microprocessor and it initiates the ignition process by communicating with the BCM through SKIS. The microprocessor-based SKIS hardware and software also use electronic messages to communicate...

Microprocessor Simulation: A Training Technique.

ERIC Educational Resources Information Center

Oscarson, David J.

1982-01-01

Describes the design and application of a microprocessor simulation using BASIC for formal training of technicians and managers and as a management tool. Illustrates the utility of the modular approach for the instruction and practice of decision-making techniques. (SK)

Microprocessor mediates transcriptional termination of long noncoding RNA transcripts hosting microRNAs.

PubMed

Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J; Jopling, Catherine L

2015-04-01

MicroRNAs (miRNAs) play a major part in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with cotranscriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. Although most miRNAs are located within introns of protein-coding transcripts, a substantial minority of miRNAs originate from long noncoding (lnc) RNAs, for which transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lncRNA transcripts containing miRNAs (lnc-pri-miRNAs) do not use the canonical cleavage-and-polyadenylation pathway but instead use Microprocessor cleavage to terminate transcription. Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a new RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells.

Microprocessor mediates transcriptional termination in long noncoding microRNA genes

PubMed Central

Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J.; Jopling, Catherine L.

2015-01-01

MicroRNA (miRNA) play a major role in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with co-transcriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. While most miRNA are located within introns of protein coding genes, a substantial minority of miRNA originate from long non coding (lnc) RNA where transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lnc-pri-miRNA do not use the canonical cleavage and polyadenylation (CPA) pathway, but instead use Microprocessor cleavage to terminate transcription. This Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a novel RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells. PMID:25730776

A new device for monitoring early motor development: prenatal nicotine-induced changes.

PubMed

Schlumpf, M; Gähwiler, M; Ribary, U; Lichtensteiger, W

1988-05-01

A new type of activity meter has been designed especially for young rats. It consists of a warmed platform for the animal, a TV camera with monitor and a microprocessor. The TV camera detects the animal as a black figure on a light background. This picture is digitalized and stored in a Z80 microprocessor. Every 200 msec a new image is compared to the foregoing one. The total number of black points that are changing from black to white and vice versa provides a measure for motor activity of the animal. Prenatally nicotine-treated rat pups were tested on the activity meter. The developmental pattern of motor activity was different for male and female pups. Motor activity of nicotine-treated male pups differed significantly from controls at postnatal days 7 and 15 while this drug effect was not seen in females.

A microprocessor-based one dimensional optical data processor for spatial frequency analysis

NASA Technical Reports Server (NTRS)

Collier, R. L.; Ballard, G. S.

1982-01-01

A high degree of accuracy was obtained in measuring the spatial frequency spectrum of known samples using an optical data processor based on a microprocessor, which reliably collected intensity versus angle data. Stray light control, system alignment, and angle measurement problems were addressed and solved. The capabilities of the instrument were extended by the addition of appropriate optics to allow the use of different wavelengths of laser radiation and by increasing the travel limits of the rotating arm to + or - 160 degrees. The acquisition, storage, and plotting of data by the computer permits the researcher a free hand in data manipulation such as subtracting background scattering from a diffraction pattern. Tests conducted to verify the operation of the processor using a 25 mm diameter pinhole, a 39.37 line pairs per mm series of multiple slits, and a microscope slide coated with 1.091 mm diameter polystyrene latex spheres are described.

AGARD Flight Test Instrumentation Series. Volume 18. Microprocessor Applications in Airborne Flight Test Instrumentation

DTIC Science & Technology

1987-02-01

flowcharting . 3. ProEram Codin in HLL. This stage consists of transcribing the previously designed program into R an t at can be translated into the machine...specified conditios 7. Documentation. Program documentation is necessary for user information, for maintenance, and for future applications. Flowcharts ...particular CP U. Asynchronous. Operating without reference to an overall timing source. BASIC. Beginners ’ All-purpose Symbolic Instruction Code; a widely

Design and fabrication of a basic mass analyzer and vacuum system

NASA Technical Reports Server (NTRS)

Judson, C. M.; Josias, C.; Lawrence, J. L., Jr.

1977-01-01

A two-inch hyperbolic rod quadrupole mass analyzer with a mass range of 400 to 200 amu and a sensitivity exceeding 100 packs per billion has been developed and tested. This analyzer is the basic hardware portion of a microprocessor-controlled quadrupole mass spectrometer for a Gas Analysis and Detection System (GADS). The development and testing of the hyperbolic-rod quadrupole mass spectrometer and associated hardware are described in detail.

OS Friendly Microprocessor Architecture

DTIC Science & Technology

2017-04-01

fact or fiction. Austin ( TX ): The Virtualization Practice; [accessed 2012 July 26]. http://www.virtualization practice.com/type-0-hypervisor-fact......needed. Do not return it to the originator. ARL-SR-0370 ● APR 2017 US Army Research Laboratory OS Friendly Microprocessor

Single-event upset in advanced commercial power PC microprocessors

NASA Technical Reports Server (NTRS)

Irom, F.; Farmanesh, F.; Swift, G. M.; Johnston, A. H.

2003-01-01

Single-event upset from heavy ions in measured for advanced commercial microprocessors, comparing upset sensitivity in registers and d-cache for several generations of devices. Multiple-bit upsets and asymmetry in registers upset cross sections are also discussed.

Applications of Microcomputers in the Teaching of Physics 6502 Software.

ERIC Educational Resources Information Center

Marsh, David P.

1980-01-01

Described is a variety of uses of the microcomputer when coupled with software available for systems using 6502 microprocessors. Included are several computer programs which exhibit some of the possibilities for programing the 6502 microprocessors. (DS)

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2012 CFR

2012-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2010 CFR

2010-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2013 CFR

2013-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2011 CFR

2011-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

Improved Training Program for Fall Prevention of Warfighters with Lower Extremity Trauma

DTIC Science & Technology

2016-10-01

productive, active civilian life. The training program utilizes a microprocessor -controlled treadmill designed to deliver task- specific training...National Military Medical Center (WRNMMC), and Mayo. The fall prevention training program utilizes a microprocessor -controlled treadmill to deliver

15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

Code of Federal Regulations, 2014 CFR

2014-01-01

... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad H.

2004-01-01

Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

Development of the self-learning machine for creating models of microprocessor of single-phase earth fault protection devices in networks with isolated neutral voltage above 1000 V

NASA Astrophysics Data System (ADS)

Utegulov, B. B.; Utegulov, A. B.; Meiramova, S.

2018-02-01

The paper proposes the development of a self-learning machine for creating models of microprocessor-based single-phase ground fault protection devices in networks with an isolated neutral voltage higher than 1000 V. Development of a self-learning machine for creating models of microprocessor-based single-phase earth fault protection devices in networks with an isolated neutral voltage higher than 1000 V. allows to effectively implement mathematical models of automatic change of protection settings. Single-phase earth fault protection devices.

Could a neuroscientist understand a microprocessor?

DOE PAGES

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

2017-01-12

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

Could a Neuroscientist Understand a Microprocessor?

PubMed Central

Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods. PMID:28081141

Could a Neuroscientist Understand a Microprocessor?

PubMed

Jonas, Eric; Kording, Konrad Paul

2017-01-01

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.

Could a neuroscientist understand a microprocessor?

DOE Office of Scientific and Technical Information (OSTI.GOV)

Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

Fine-grained parallelization of fitness functions in bioinformatics optimization problems: gene selection for cancer classification and biclustering of gene expression data.

PubMed

Gomez-Pulido, Juan A; Cerrada-Barrios, Jose L; Trinidad-Amado, Sebastian; Lanza-Gutierrez, Jose M; Fernandez-Diaz, Ramon A; Crawford, Broderick; Soto, Ricardo

2016-08-31

Metaheuristics are widely used to solve large combinatorial optimization problems in bioinformatics because of the huge set of possible solutions. Two representative problems are gene selection for cancer classification and biclustering of gene expression data. In most cases, these metaheuristics, as well as other non-linear techniques, apply a fitness function to each possible solution with a size-limited population, and that step involves higher latencies than other parts of the algorithms, which is the reason why the execution time of the applications will mainly depend on the execution time of the fitness function. In addition, it is usual to find floating-point arithmetic formulations for the fitness functions. This way, a careful parallelization of these functions using the reconfigurable hardware technology will accelerate the computation, specially if they are applied in parallel to several solutions of the population. A fine-grained parallelization of two floating-point fitness functions of different complexities and features involved in biclustering of gene expression data and gene selection for cancer classification allowed for obtaining higher speedups and power-reduced computation with regard to usual microprocessors. The results show better performances using reconfigurable hardware technology instead of usual microprocessors, in computing time and power consumption terms, not only because of the parallelization of the arithmetic operations, but also thanks to the concurrent fitness evaluation for several individuals of the population in the metaheuristic. This is a good basis for building accelerated and low-energy solutions for intensive computing scenarios.

Benchmark tests on the digital equipment corporation Alpha AXP 21164-based AlphaServer 8400, including a comparison of optimized vector and superscalar processing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wasserman, H.J.

1996-02-01

The second generation of the Digital Equipment Corp. (DEC) DECchip Alpha AXP microprocessor is referred to as the 21164. From the viewpoint of numerically-intensive computing, the primary difference between it and its predecessor, the 21064, is that the 21164 has twice the multiply/add throughput per clock period (CP), a maximum of two floating point operations (FLOPS) per CP vs. one for 21064. The AlphaServer 8400 is a shared-memory multiprocessor server system that can accommodate up to 12 CPUs and up to 14 GB of memory. In this report we will compare single processor performance of the 8400 system with thatmore » of the International Business Machines Corp. (IBM) RISC System/6000 POWER-2 microprocessor running at 66 MHz, the Silicon Graphics, Inc. (SGI) MIPS R8000 microprocessor running at 75 MHz, and the Cray Research, Inc. CRAY J90. The performance comparison is based on a set of Fortran benchmark codes that represent a portion of the Los Alamos National Laboratory supercomputer workload. The advantage of using these codes, is that the codes also span a wide range of computational characteristics, such as vectorizability, problem size, and memory access pattern. The primary disadvantage of using them is that detailed, quantitative analysis of performance behavior of all codes on all machines is difficult. One important addition to the benchmark set appears for the first time in this report. Whereas the older version was written for a vector processor, the newer version is more optimized for microprocessor architectures. Therefore, we have for the first time, an opportunity to measure performance on a single application using implementations that expose the respective strengths of vector and superscalar architecture. All results in this report are from single processors. A subsequent article will explore shared-memory multiprocessing performance of the 8400 system.« less

Educational Implications of Microelectronics and Microprocessors.

ERIC Educational Resources Information Center

Harris, N. D. C., Ed.

This conference report explores microelectronic technology, its effect on educational methods and objectives, and its implications for educator responsibilities. Two main areas were considered: the significance of the likely impact of the large scale introduction of microprocessors and microelectronics on commercial and industrial processes, the…

Considerations In The Design And Specifications Of An Automatic Inspection System

NASA Astrophysics Data System (ADS)

Lee, David T.

1980-05-01

Considerable activities have been centered around the automation of manufacturing quality control and inspection functions. Several reasons can be cited for this development. The continuous pressure of direct and indirect labor cost increase is only one of the obvious motivations. With the drive for electronics miniaturization come more and more complex processes where control parameters are critical and the yield is highly susceptible to inadequate process monitor and inspection. With multi-step, multi-layer process for substrate fabrication, process defects that are not detected and corrected at certain critical points may render the entire subassembly useless. As a process becomes more complex, the time required to test the product increases significantly in the total build cycle. The urgency to reduce test time brings more pressure to improve in-process control and inspection. The advances and improvements of components, assemblies and systems such as micro-processors, micro-computers, programmable controllers, and other intelligent devices, have made the automation of quality control much more cost effective and justifiable.

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

NASA Astrophysics Data System (ADS)

Liebmann, Lars W.; Graur, Ioana C.; Leipold, William C.; Oberschmidt, James M.; O'Grady, David S.; Regaill, Denis

1999-07-01

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBM's Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBM's internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBM's internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

Comparison between microprocessor-controlled ankle/foot and conventional prosthetic feet during stair negotiation in people with unilateral transtibial amputation.

PubMed

Agrawal, Vibhor; Gailey, Robert S; Gaunaurd, Ignacio A; O'Toole, Christopher; Finnieston, Adam A

2013-01-01

Contrary to stance-phase dorsiflexion of conventional prosthetic feet, the microprocessor-controlled Proprio foot permits swing-phase dorsiflexion on stairs. The purpose of this study was to compare Symmetry in External Work (SEW) between a microprocessor-controlled foot and conventional prosthetic feet in two groups with unilateral transtibial amputation (Medicare Functional Classification Levels K-Level-2 and K-Level-3) during stair ascent and descent. Ten subjects were evaluated while wearing three conventional prosthetic feet- solid ankle cushion heel (SACH), stationary attachment flexible endoskeleton (SAFE), and Talux-and the Proprio foot using a study socket and were given a 10- to 14-day accommodation period with each foot. Ground reaction forces were collected using F-scan sensors during stair ascent and descent. The SEW between the intact and amputated limbs was calculated for each foot. During stair ascent, the Proprio foot resulted in a higher interlimb symmetry than conventional prosthetic feet, with significant differences between the Pro prio and SACH/SAFE feet. The swing-phase dorsiflexion appeared to promote greater interlimb symmetry because it facilitated forward motion of the body, resulting in a heel-to-toe center of pressure trajectory. During stair descent, all feet had low symmetry without significant differences between feet. The movement strategy used when descending stairs, which is to roll over the edge of a step, had a greater influence on symmetry than the dorsiflexion features of prosthetic feet.

RS-600 programmable controller: Solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

Three identical microprocessor control subsystems were developed which can be used in heating, heating and cooling, and/or hot water systems for single family, multifamily, or commercial applications. The controller incorporates a low cost, highly reliable (all solid state) microprocessor which can be easily reprogrammed.

Development of the transtibial prosthesis controlled pneumatically and electrically by microcomputer system.

PubMed

Shimada, Youichi; Terayama, Yukio

2006-01-01

This report represents the development of the prototype transtibial prosthesis to assist a smooth and comfortable walking for an unilateral amputee. This prosthesis is composed of two air cylinders, solenoid valves, portable and small air tank for compressed air storage, a multiple sensor system and a microprocessor. Two air cylinders are located around the rods to act as antagonistic and agonistic muscles. The system causes flexion and extension of the foot plate jointed at the ankle with compressed air, injected -or discharged via a solenoid or electromagnetic valves. The valves or solenoids are controlled with a microprocessor (Microchip Technology Inc., PIC16F876), the microprocessor generates control signals to the interface circuits for valve opening and closing consistent with the foot position during the walking phase. The control patterns generated in the microprocessor are modified with feedback from the touch sensor, ankle joint angle sensor and the two dimensional acceleration sensor. The primary walking pattern for an individual amputee should be developed through the gait analysis with video.

Developing prescribing guidelines for microprocessor-controlled prosthetic knees in the South East England.

PubMed

Sedki, Imad; Fisher, Keren

2015-06-01

Microprocessor-controlled prosthetic knees have gained increasing popularity over the last decade. Research supports their provision to address specific problems or to achieve certain rehabilitation goals. However, there are yet no agreed protocols or prescribing criteria to assist clinicians in the identification and appropriate selection of suitable users. The aim is to reach professionals' agreement on specific prescribing guidelines for microprocessor-controlled prosthetic knees. The study involved multidisciplinary teams from the Inter Regional Prosthetic Audit Group, representing nine Prosthetic Rehabilitation Centres in the South East England region. We used the Delphi technique with a total of three rounds to reach professionals' agreement. The prescribing guidelines were agreed and will be reviewed and updated depending on new research evidence and technical advances. This project is highly useful for professionals in a clinic setting to aid in appropriate patient selection and to justify the cost of prescribing microprocessor-controlled prosthetic knees. © The International Society for Prosthetics and Orthotics 2014.

Formal verification of an avionics microprocessor

NASA Technical Reports Server (NTRS)

Srivas, Mandayam, K.; Miller, Steven P.

1995-01-01

Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.

Microprocessor, Setx, Xrn2, and Rrp6 co-operate to induce premature termination of transcription by RNAPII.

PubMed

Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

2012-09-14

Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 3'-5' exoribonuclease, Rrp6, to initiate RNAPII pausing and premature termination at the HIV-1 promoter through cleavage of the stem-loop RNA, TAR. Rrp6 further processes the cleavage product, which generates a small RNA that is required to mediate potent transcriptional repression and chromatin remodeling at the HIV-1 promoter. Using chromatin immunoprecipitation coupled to high-throughput sequencing (ChIP-seq), we identified cellular gene targets whose transcription is modulated by microprocessor. Our study reveals RNAPII pausing and premature termination mediated by the co-operative activity of ribonucleases, Drosha/Dgcr8, Xrn2, and Rrp6, as a regulatory mechanism of RNAPII-dependent transcription elongation. Copyright © 2012 Elsevier Inc. All rights reserved.

Gait asymmetry of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

PubMed

Kaufman, Kenton R; Frittoli, Serena; Frigo, Carlo A

2012-06-01

Amputees walk with an asymmetrical gait, which may lead to future musculoskeletal degenerative changes. The purpose of this study was to compare the gait asymmetry of active transfemoral amputees while using a passive mechanical knee joint or a microprocessor-controlled knee joint. Objective 3D gait measurements were obtained in 15 subjects (12 men and 3 women; age 42, range 26-57). Research participants were longtime users of a mechanical prosthesis (mean 20 years, range 3-36 years). Joint symmetry was calculated using a novel method that includes the entire waveform throughout the gait cycle. There was no significant difference in hip, knee and ankle kinematics symmetry when using the different knee prostheses. In contrast, the results demonstrated a significant improvement in lower extremity joint kinetics symmetry when using the microprocessor-controlled knee. Use of the microprocessor-controlled knee joint resulted in improved gait symmetry. These improvements may lead to a reduction in the degenerative musculoskeletal changes often experienced by amputees. Copyright © 2011 Elsevier Ltd. All rights reserved.

Automated control and data acquisition for a tunable diode laser heterodyne spectrometer

NASA Technical Reports Server (NTRS)

Shull, T. S.; Rinsland, P. L.

1983-01-01

This paper describes the hardware and software design, development, and implementation of the control and data electronics of a laser heterodyne spectrometer instrument being built at NASA Langley Research Center for a technology demonstration. Functional partitioning, applied at all levels of hardware and software, has been found to provide expedient design, development, and testing of the instrument. The instrument is composed of distributed microprocessor-based units. A master/slave protocol is presented which can be simulated by a terminal for unit checkout. All but one of the units are implemented using a set of core boards, plus unique boards where necessary. This design has led to reduced hardware development, reduced parts inventory, and replication of software modules, while providing the flexibility needed for a development instrument. The development tools and documentation guidelines are discussed.

Visual display and alarm system for wind tunnel static and dynamic loads

NASA Technical Reports Server (NTRS)

Hanly, Richard D.; Fogarty, James T.

1987-01-01

A wind tunnel balance monitor and alarm system developed at NASA Ames Research Center will produce several beneficial results. The costs of wind tunnel delays because of inadvertent balance damage and the costs of balance repair or replacement can be greatly reduced or eliminated with better real-time information on the balance static and dynamic loading. The wind tunnel itself will have enhanced utility with the elimination of overly cautious limits on test conditions. The microprocessor-based system features automatic scaling and 16 multicolored LED bargraphs to indicate both static and dynamic components of the signals from eight individual channels. Five individually programmable alarm levels are available with relay closures for internal or external visual and audible warning devices and other functions such as automatic activation of external recording devices, model positioning mechanisms, or tunnel shutdown.

Visual display and alarm system for wind tunnel static and dynamic loads

NASA Technical Reports Server (NTRS)

Hanly, Richard D.; Fogarty, James T.

1987-01-01

A wind tunnel balance monitor and alarm system developed at NASA Ames Research Center will produce several beneficial results. The costs of wind tunnel delays because of inadvertent balance damage and the costs of balance repair or replacement can be greatly reduced or eliminated with better real-time information on the balance static and dynamic loading. The wind tunnel itself will have enhanced utility with the elimination of overly cautious limits on test conditions. The microprocessor-based system features automatic scaling and 16 multicolored LED bargraphs to indicate both static and dynamic components of the signals from eight individual channels. Five individually programmable alarm levels are available with relay closures for internal or external visual and audible warning devices and other functions such as automatic activation of external recording devices, model positioning mechanism, or tunnel shutdown.

[Implementation of modern trends in the methods of the ventilation support in the new apparatus for artificial lung ventilation Avenir-221 P].

PubMed

Gal'perin, Iu Sh; Alkhimova, L R; Dmitriev, N D; Kozlova, I A; Nemirovskiĭ, S B; Makarov, M V; Safronov, A Iu

2005-01-01

In the new ventilator Avenir-221 P modern lines of development of ventilation support in intensive therapy of adults and children are implemented. The capacities of the ventilator are successfully combined with its technical decisions which include microprocessor parametrical controlling, programming-controlled electric drive, an information saturation, intuitively clear control system, protection against interruption of power supply sources and oxygen feeding falls. A set of functional characteristics (modes VCV, PCV, Ass/Contr, PSV, SIMV, PEEP, Sigh, etc.) in combination with an original design make the device the most accessible and promising for application in intensive care and resuscitation units of a wide network of Russian hospitals and clinics. The ventilator Avenir-221 P has passed all required tests and is presently commercially available.

A Demonstration Advanced Avionics System for general aviation

NASA Technical Reports Server (NTRS)

Denery, D. G.; Callas, G. P.; Jackson, C. T.; Berkstresser, B. K.; Hardy, G. H.

1979-01-01

A program initiated within NASA has emphasized the use of a data bus, microprocessors, electronic displays and data entry devices for general aviation. A Demonstration Advanced Avionics System (DAAS) capable of evaluating critical and promising elements of an integrating system that will perform the functions of (1) automated guidance and navigation; (2) flight planning; (3) weight and balance performance computations; (4) monitoring and warning; and (5) storage of normal and emergency check lists and operational limitations is described. Consideration is given to two major parts of the DAAS instrument panel: the integrated data control center and an electronic horizontal situation indicator, and to the system architecture. The system is to be installed in the Ames Research Center's Cessna 402B in the latter part of 1980; engineering flight testing will begin in the first part of 1981.

Direct conversion of solar energy to thermal energy

NASA Astrophysics Data System (ADS)

Sizmann, Rudolf

1986-12-01

Selective coatings (cermets) were produced by simultaneous evaporation of copper and silicon dioxide, and analyzed by computer assisted spectral photometers and ellipsometers; hemispherical emittance was measured. Steady state test procedures for covered and uncovered collectors were investigated. A method for evaluating the transient behavior of collectors was developed. The derived transfer functions describe their transient behavior. A stochastic approach was used for reducing the meteorological data volume. Data sets which are statistically equivalent to the original data can be synthesized. A simulation program for solar systems using analytical solutions of differential equations was developed. A large solar DHW system was optimized by a detailed modular simulation program. A microprocessor assisted data aquisition records the four characteristics of solar cells and solar cell systems in less than 10 msec. Measurements of a large photovoltaic installation (50 sqm) are reported.

Real-Time Signal Processing Systems

DTIC Science & Technology

1992-10-29

Programmer’s Model 50 15. Synchronization 67 16. Parameter Passage to Routines VIA Stacks 68 17. Typical VPH Activity Flow Chart 70 18. CPH...computing facilities to take advantage of cost effective solutions. A proliferation of different microprocessors and development systems spread among the... activities are completed, the roles of the VPH memory banks are reversed. This function-swapping is the primary reason, for the efficiency and high

Improved Planning and Programming for Energy Efficient New Army Facilities

DTIC Science & Technology

1988-10-01

setpoints to occupant comfort must be considered carefully. Cutting off the HVAC system to the bedrooms during the day produced only small savings...functions of a building and minimizing the energy usage through optimization . It includes thermostats, time switches, programmable con- trollers...microprocessor systems, computers, and sensing devices that are linked with control and power components to manage energy use. This system optimizes load

Automated quantitative muscle biopsy analysis system

NASA Technical Reports Server (NTRS)

Castleman, Kenneth R. (Inventor)

1980-01-01

An automated system to aid the diagnosis of neuromuscular diseases by producing fiber size histograms utilizing histochemically stained muscle biopsy tissue. Televised images of the microscopic fibers are processed electronically by a multi-microprocessor computer, which isolates, measures, and classifies the fibers and displays the fiber size distribution. The architecture of the multi-microprocessor computer, which is iterated to any required degree of complexity, features a series of individual microprocessors P.sub.n each receiving data from a shared memory M.sub.n-1 and outputing processed data to a separate shared memory M.sub.n+1 under control of a program stored in dedicated memory M.sub.n.

Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Soeder, J. F.

1983-01-01

High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

NASA Technical Reports Server (NTRS)

Baez, A. N.

1985-01-01

Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2013 CFR

2013-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2010 CFR

2010-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2012 CFR

2012-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

46 CFR 62.25-25 - Programable systems and devices.

Code of Federal Regulations, 2011 CFR

2011-10-01

...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

Work and Programmable Automation.

ERIC Educational Resources Information Center

DeVore, Paul W.

A new industrial era based on electronics and the microprocessor has arrived, an era that is being called intelligent automation. Intelligent automation, in the form of robots, replaces workers, and the new products, using microelectronic devices, require significantly less labor to produce than the goods they replace. The microprocessor thus…

Use of electronic microprocessor-based instrumentation by the U.S. geological survey for hydrologic data collection

USGS Publications Warehouse

Shope, William G.; ,

1991-01-01

The U.S. Geological Survey is acquiring a new generation of field computers and communications software to support hydrologic data-collection at field locations. The new computer hardware and software mark the beginning of the Survey's transition from the use of electromechanical devices and paper tapes to electronic microprocessor-based instrumentation. Software is being developed for these microprocessors to facilitate the collection, conversion, and entry of data into the Survey's National Water Information System. The new automated data-collection process features several microprocessor-controlled sensors connected to a serial digital multidrop line operated by an electronic data recorder. Data are acquired from the sensors in response to instructions programmed into the data recorder by the user through small portable lap-top or hand-held computers. The portable computers, called personal field computers, also are used to extract data from the electronic recorders for transport by courier to the office computers. The Survey's alternative to manual or courier retrieval is the use of microprocessor-based remote telemetry stations. Plans have been developed to enhance the Survey's use of the Geostationary Operational Environmental Satellite telemetry by replacing the present network of direct-readout ground stations with less expensive units. Plans also provide for computer software that will support other forms of telemetry such as telephone or land-based radio.

Portable light source unit for simulating fires having an adjustable aperture

NASA Technical Reports Server (NTRS)

Youngquist, Robert C. (Inventor); Moerk, John S. (Inventor); Strobel, James P. (Inventor)

1997-01-01

A portable, hand held light source unit is employed to check operation of fire detectors, such as hydrogen fire detectors. The unit emits radiation in a narrow band of wavelengths which are generated by the type of fire to be tested, but not by other light sources such as the sun or incandescent lamps. The unit can test fire detectors at different distances, and of different sensitivities. The intensity of the radiation emitted by the unit is adjustable for this purpose by means of a rotatable disk having a plurality of different sized apertures for selective placement between the light source and an output lens. The disk can also be rotated to a calibration position which causes a microprocessor circuit in the unit to initiate a calibration procedure. During this procedure, the lamp intensity is measured by a photodetector contained within the unit, and the microprocessor adjusts the lamp current to insure that its intensity remains within a preset range of values. A green and a red LED are mounted on the unit which indicate to an operator whether the calibration is successful, as well as the condition of the unit's battery power supply.

Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

NASA Technical Reports Server (NTRS)

Barrett, W. J.; Rembold, J. P.; Burcham, F. W.; Myers, L.

1981-01-01

The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

Development of a simple, self-contained flight test data acquisition system

NASA Technical Reports Server (NTRS)

Clarke, R.; Shane, D.; Roskam, J.; Rummer, D. I.

1982-01-01

The flight test system described combines state-of-the-art microprocessor technology and high accuracy instrumentation with parameter identification technology which minimize data and flight time requirements. The system was designed to avoid permanent modifications of the test airplane and allow quick installation. It is capable of longitudinal and lateral-directional stability and control derivative estimation. Details of this system, calibration and flight test procedures, and the results of the Cessna 172 flight test program are presented. The system proved easy to install, simple to operate, and capable of accurate estimation of stability and control parameters in the Cessna 172 flight tests.

Development history of the Hybrid Test Vehicle

NASA Technical Reports Server (NTRS)

Trummel, M. C.; Burke, A. F.

1983-01-01

Phase I of a joint Department of Energy/Jet Propulsion Laboratory Program undertook the development of the Hybrid Test Vehicle (HTV), which has subsequently progressed through design, fabrication, and testing and evaluation phases. Attention is presently given to the design and test experience gained during the HTV development program, and a discussion is presented of the design features and performance capabilities of the various 'mule' vehicles, devoted to the separate development of engine microprocessor control, vehicle structure, and mechanical components, whose elements were incorporated into the final HTV design. Computer projections of the HTV's performance are given.

Latest trends in parts SEP susceptibility from heavy ions

NASA Technical Reports Server (NTRS)

Nichols, Donald K.; Smith, L. S.; Soli, George A.; Koga, R.; Kolasinski, W. A.

1989-01-01

JPL and Aerospace have collected a third set of heavy-ion single-event phenomena (SEP) test data since their last joint IEEE publications in December 1985 and December 1987. Trends in SEP susceptibility (e.g., soft errors and latchup) for state-of-the-art parts are presented. Results of the study indicate that hard technologies and unacceptably soft technologies can be flagged. In some instances, specific tested parts can be taken as candidates for key microprocessors or memories. As always with radiation test data, specific test data for qualified flight parts is recommended for critical applications.

Teacher Training for High Technology. Final Report.

ERIC Educational Resources Information Center

Goettmann, Thomas L.

The objective of this project was to develop computer literacy and a working knowledge of microprocessor applications and digital circuits for teachers in selected vocational subject areas. Twenty-four vocational trade and industry teachers completed 16 hours of training in microprocessor skills for computerized instruction and curriculum update.…

Walking-Beam Solar-Cell Conveyor

NASA Technical Reports Server (NTRS)

Feder, H.; Frasch, W.

1982-01-01

Microprocessor-controlled walking-beam conveyor moves cells between work stations in automated assembly line. Conveyor has arm at each work station. In unison arms pick up all solar cells and advance them one station; then beam retracks to be in position for next step. Microprocessor sets beam stroke, speed, and position.

Safety of Vital Control and Communication Systems in Guided Ground Transportation : Analysis of Railroad Signaling System Microprocessor Interlocking

DOT National Transportation Integrated Search

1993-05-01

This study has been conducted with the goal of gaining an insight into the issues of maintaining vital signal systems implemented with microprocessor chips and of making field changes to the application of such systems. To relate these abstract topic...

High Stability Metal-Protein Interactions Evaluated by Microcalorimetry

DTIC Science & Technology

2016-04-29

microprocessor -controlled internal vacuum pump runs for a 90 second period, then it evaluates the vacuum pressure attained, and if that value meets spec...and the other with the software. There is a place in the wash module program where the ITC’s microprocessor - controlled internal vacuum pump runs for

An Interdisciplinary Microprocessor Project.

ERIC Educational Resources Information Center

Wilcox, Alan D.; And Others

1985-01-01

Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)

Advanced Electricity. Microprocessors and Robotics. Curriculum Development. Bulletin 1803.

ERIC Educational Resources Information Center

Southeastern Louisiana Univ., Hammond.

This model instructional unit was developed to aid industrial arts/technology education teachers in Louisiana to teach a course on microprocessors and robotics in grades 11 and 12. It provides guidance on model performance objectives, current technology content, sources, and supplemental materials. Following a course description, rationale, and…

Preliminary design and development of a reflectance spectrometer instrument

NASA Technical Reports Server (NTRS)

Mccord, T. B.

1979-01-01

An improved design for the reflectance spectrometer is described to be used on various terrestrial body missions. These improvements were made on the original Lunar Polar Orbiter design. These include a larger entrance mirror, rectangular aperture, multiple optical beams, spatial resolution, and a bandwidth extension to 5 microns. In addition, detailed electronic designs were produced for a charge amplifier and an amplifier/demodulator/integrator. Design of a microprocessor driven test system was begun. Laboratory tests were performed on a tuning fork chopper.

A Study of a Standard BIT Circuit.

DTIC Science & Technology

1977-02-01

IENDED BIT APPROACHES FOR QED MODULES AND APPLICATION OF THE ANALYTIC MEASURES 36 4.1 Built-In-Test for Memory Class Modules 37 4.1.1 Random Access...Implementation 68 4.1.5.5 Criti cal Parameters 68 4.1.5.6 QED Module Test Equipment Requirements 68 4.1.6 Application of Analytic Measures to the...Microprocessor BIT Techniques.. 121 4.2.9 Application of Analytic Measures to the Recommended BIT App roaches 125 4.2.10 Process Class BIT by Partial

USAFA/8086 - A State of the Art Microprocessor System. Volume II. Software Documentation.

DTIC Science & Technology

1980-06-01

34 /* THE THREE FOLLOWING STRUCTU2RES APE NECESSARY TO MLLLO ThE OPERATING SYTEM TO HAVE INDIRECT ACCESS TL 41EMOP *. 13- ** _3_ -- - , -- K k"" , PijPL...FILLJ$ ERROR$ ONE IOPB CHECKER LINK$IN$ DIR$IN$ ABM $IN$ DATA$IN$ OUT OUT OUT OUT DisK86 MODUlE FiGuRE 8. DATA TRANSFER UTILITIE.S 62 In addition to...SUPPORT ROUTINES. Table 3 shows the functions of these routines. TABLE 3. SUPPORT PROCEDURES ROUTINE FUNCTION ABM $ZERO Makes a given sector on a

Loran-C digital word generator for use with a KIM-1 microprocessor system

NASA Technical Reports Server (NTRS)

Nickum, J. D.

1977-01-01

The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device.

PubMed

Picone, Rico A R; Davis, Solomon; Devine, Cameron; Garbini, Joseph L; Sidles, John A

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

NASA Astrophysics Data System (ADS)

Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

2017-04-01

We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

Electrical Connection of Enzyme Redox Centers to Electrodes

DTIC Science & Technology

1992-03-20

concentration in the target organ or the affected physiological function ; and a microcontroller or microprocessor calculating the dose and timing the delivery...followed by introduction of medical feedback loops will allow the pharmaceutical industry to expand its range of drug delivery methods. Today’s primary ...inhalation (derived of the large lung surface area) and continuous, non -invasive administration, in the case of iontophoresis. The use of these

Analysis of clinically important factors on the performance of advanced hydraulic, microprocessor-controlled exo-prosthetic knee joints based on 899 trial fittings

PubMed Central

Hahn, Andreas; Lang, Michael; Stuckart, Claudia

2016-01-01

Abstract The objective of this work is to evaluate whether clinically important factors may predict an individual's capability to utilize the functional benefits provided by an advanced hydraulic, microprocessor-controlled exo-prosthetic knee component. This retrospective cross-sectional cohort analysis investigated the data of above knee amputees captured during routine trial fittings. Prosthetists rated the performance indicators showing the functional benefits of the advanced maneuvering capabilities of the device. Subjects were asked to rate their perception. Simple and multiple linear and logistic regression was applied. Data from 899 subjects with demographics typical for the population were evaluated. Ability to vary gait speed, perform toileting, and ascend stairs were identified as the most sensitive performance predictors. Prior C-Leg users showed benefits during advanced maneuvering. Variables showed plausible and meaningful effects, however, could not claim predictive power. Mobility grade showed the largest effect but also failed to be predictive. Clinical parameters such as etiology, age, mobility grade, and others analyzed here do not suffice to predict individual potential. Daily walking distance may pose a threshold value and be part of a predictive instrument. Decisions based solely on single parameters such as mobility grade rating or walking distance seem to be questionable. PMID:27828871

Analysis of clinically important factors on the performance of advanced hydraulic, microprocessor-controlled exo-prosthetic knee joints based on 899 trial fittings.

PubMed

Hahn, Andreas; Lang, Michael; Stuckart, Claudia

2016-11-01

The objective of this work is to evaluate whether clinically important factors may predict an individual's capability to utilize the functional benefits provided by an advanced hydraulic, microprocessor-controlled exo-prosthetic knee component.This retrospective cross-sectional cohort analysis investigated the data of above knee amputees captured during routine trial fittings. Prosthetists rated the performance indicators showing the functional benefits of the advanced maneuvering capabilities of the device. Subjects were asked to rate their perception. Simple and multiple linear and logistic regression was applied.Data from 899 subjects with demographics typical for the population were evaluated. Ability to vary gait speed, perform toileting, and ascend stairs were identified as the most sensitive performance predictors. Prior C-Leg users showed benefits during advanced maneuvering. Variables showed plausible and meaningful effects, however, could not claim predictive power. Mobility grade showed the largest effect but also failed to be predictive.Clinical parameters such as etiology, age, mobility grade, and others analyzed here do not suffice to predict individual potential. Daily walking distance may pose a threshold value and be part of a predictive instrument. Decisions based solely on single parameters such as mobility grade rating or walking distance seem to be questionable.

Annual Conference on Nuclear and Space Radiation Effects, 18th, University of Washington, Seattle, WA, July 21-24, 1981, Proceedings

NASA Technical Reports Server (NTRS)

Tasca, D. M.

1981-01-01

Single event upset phenomena are discussed, taking into account cosmic ray induced errors in IIL microprocessors and logic devices, single event upsets in NMOS microprocessors, a prediction model for bipolar RAMs in a high energy ion/proton environment, the search for neutron-induced hard errors in VLSI structures, soft errors due to protons in the radiation belt, and the use of an ion microbeam to study single event upsets in microcircuits. Basic mechanisms in materials and devices are examined, giving attention to gamma induced noise in CCD's, the annealing of MOS capacitors, an analysis of photobleaching techniques for the radiation hardening of fiber optic data links, a hardened field insulator, the simulation of radiation damage in solids, and the manufacturing of radiation resistant optical fibers. Energy deposition and dosimetry is considered along with SGEMP/IEMP, radiation effects in devices, space radiation effects and spacecraft charging, EMP/SREMP, and aspects of fabrication, testing, and hardness assurance.

Microprocessor control and networking for the amps breadboard

NASA Technical Reports Server (NTRS)

Floyd, Stephen A.

1987-01-01

Future space missions will require more sophisticated power systems, implying higher costs and more extensive crew and ground support involvement. To decrease this human involvement, as well as to protect and most efficiently utilize this important resource, NASA has undertaken major efforts to promote progress in the design and development of autonomously managed power systems. Two areas being actively pursued are autonomous power system (APS) breadboards and knowledge-based expert system (KBES) applications. The former are viewed as a requirement for the timely development of the latter. Not only will they serve as final testbeds for the various KBES applications, but will play a major role in the knowledge engineering phase of their development. The current power system breadboard designs are of a distributed microprocessor nature. The distributed nature, plus the need to connect various external computer capabilities (i.e., conventional host computers and symbolic processors), places major emphasis on effective networking. The communications and networking technologies for the first power system breadboard/test facility are described.

Biosorption of gold from computer microprocessor leachate solutions using chitin.

PubMed

Côrtes, Letícia N; Tanabe, Eduardo H; Bertuol, Daniel A; Dotto, Guilherme L

2015-11-01

The biosorption of gold from discarded computer microprocessor (DCM) leachate solutions was studied using chitin as a biosorbent. The DCM components were leached with thiourea solutions, and two procedures were tested for recovery of gold from the leachates: (1) biosorption and (2) precipitation followed by biosorption. For each procedure, the biosorption was evaluated considering kinetic, equilibrium, and thermodynamic aspects. The general order model was able to represent the kinetic behavior, and the equilibrium was well represented by the BET model. The maximum biosorption capacities were around 35 mg g(-1) for both procedures. The biosorption of gold on chitin was a spontaneous, favorable, and exothermic process. It was found that precipitation followed by biosorption resulted in the best gold recovery, because other species were removed from the leachate solution in the precipitation step. This method enabled about 80% of the gold to be recovered, using 20 g L(-1) of chitin at 298 K for 4 h. Copyright © 2015 Elsevier Ltd. All rights reserved.

A monitoring system for vegetable greenhouses based on a wireless sensor network.

PubMed

Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

2010-01-01

A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring.

Computer Architecture's Changing Role in Rebooting Computing

DOE Office of Scientific and Technical Information (OSTI.GOV)

DeBenedictis, Erik P.

In this paper, Windows 95 started the Wintel era, in which Microsoft Windows running on Intel x86 microprocessors dominated the computer industry and changed the world. Retaining the x86 instruction set across many generations let users buy new and more capable microprocessors without having to buy software to work with new architectures.

An Ill-Structured PBL-Based Microprocessor Course without Formal Laboratory

ERIC Educational Resources Information Center

Kim, Jungkuk

2012-01-01

This paper introduces a problem-based learning (PBL) microprocessor application course designed according to the following strategies: 1) hands-on training without having a formal laboratory, and 2) intense student-centered cooperative learning through an ill-structured problem. PBL was adopted as the core educational technique of the course to…

Microprocessor-Based Neural-Pulse-Wave Analyzer

NASA Technical Reports Server (NTRS)

Kojima, G. K.; Bracchi, F.

1983-01-01

Microprocessor-based system analyzes amplitudes and rise times of neural waveforms. Displaying histograms of measured parameters helps researchers determine how many nerves contribute to signal and specify waveform characteristics of each. Results are improved noise rejection, full or partial separation of overlapping peaks, and isolation and identification of related peaks in different histograms. 2

The Use of Opto-Electronics in Viscometry.

ERIC Educational Resources Information Center

Mazza, R. J.; Washbourn, D. H.

1982-01-01

Describes a semi-automatic viscometer which incorporates a microprocessor system and uses optoelectronics to detect flow of liquid through the capillary, flow time being displayed on a timer with accuracy of 0.01 second. The system could be made fully automatic with an additional microprocessor circuit and inclusion of a pump. (Author/JN)

Coed Transactions, Vol. XI, No. 1, January 1979. Microprocessor Course Development Equipment Selection.

ERIC Educational Resources Information Center

Mitchell, Eugene E., Ed.; Leventhal, Lance A.

Many devices and systems related to microprocessors are available on the marketplace. The author suggests that criteria for selecting and designing workstations and development systems are necessary. Seventeen important factors of designing workstations and six desirable features of a development system are presented. The kinds of places in which…

Microprocessor Design Using Hardware Description Language

ERIC Educational Resources Information Center

Mita, Rosario; Palumbo, Gaetano

2008-01-01

The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

The Effects of Microprocessors on Industry, Society and Employment: A Meeting of the Frontier Group on Strategies for Change in a Technological Society (Bath, England, March 13, 1979).

ERIC Educational Resources Information Center

Harris, N. D. C.

Discussed are the multiple impacts of microelectronics on society. Included are discussions of the problem of predicting effects, difficulty of exploiting new technology, manpower consequences, and needs within the United Kingdom relating to microprocessors. (RE)

DSS 13 microprocessor antenna controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1988-01-01

A microprocessor-based antenna monitor and control system with multiple CPUs are described. The system was developed as part of the unattended station project for DSS 13 and was enhanced for use by the SETI project. The operational features, hardware, and software designs are described, and a discussion is provided of the major problems encountered.

Computer Architecture's Changing Role in Rebooting Computing

DOE PAGES

DeBenedictis, Erik P.

2017-04-26

In this paper, Windows 95 started the Wintel era, in which Microsoft Windows running on Intel x86 microprocessors dominated the computer industry and changed the world. Retaining the x86 instruction set across many generations let users buy new and more capable microprocessors without having to buy software to work with new architectures.

Development of a Low-Cost, Stand-Alone Microterminal for Support of Testing and Instruction. Final Report for Period January 1977-February 1978.

ERIC Educational Resources Information Center

Steffen, Dale A.; And Others

A study was undertaken to develop a microterminal for use in a computer-based instructional system. Objectives were to use new microprocessor technology to produce one terminal that is more effective and efficient than either the management terminal or the plasma type interactive terminal presently in use by the Air Force Advanced Instructional…

Solid State Audio/Speech Processor Analysis.

DTIC Science & Technology

1980-03-01

techniques. The techniques were demonstrated to be worthwhile in an efficient realtime AWR system. Finally, microprocessor architectures were designed to...do not include custom chip development, detailed hardware design , construction or testing. ITTDCD is very encouraged by the results obtained in this...California, Berkley, was responsible for furnishing the simulation data of OD speech analysis techniques and for the design and development of the hardware OD

Development of a CPM Machine for Injured Fingers.

PubMed

Fu, Yili; Zhang, Fuxiang; Ma, Xin; Meng, Qinggang

2005-01-01

Human fingers are easy to be injured. A CPM machine is a mechanism based on the rehabilitation theory of continuous passive motion (CPM). To develop a CPM machine for the clinic application in the rehabilitation of injured fingers is a significant task. Therefore, based on the theories of evidence based medicine (EBM) and CPM, we've developed a set of biomimetic mechanism after modeling the motions of fingers and analyzing its kinematics and dynamics analysis. We also design an embedded operating system based on ARM (a kind of 32-bit RISC microprocessor). The equipment can achieve the precise control of moving scope of fingers, finger's force and speed. It can serves as a rational checking method and a way of assessment for functional rehabilitation of human hands. Now, the first prototype has been finished and will start the clinical testing in Harbin Medical University shortly.

Validation of a wireless modular monitoring system for structures

NASA Astrophysics Data System (ADS)

Lynch, Jerome P.; Law, Kincho H.; Kiremidjian, Anne S.; Carryer, John E.; Kenny, Thomas W.; Partridge, Aaron; Sundararajan, Arvind

2002-06-01

A wireless sensing unit for use in a Wireless Modular Monitoring System (WiMMS) has been designed and constructed. Drawing upon advanced technological developments in the areas of wireless communications, low-power microprocessors and micro-electro mechanical system (MEMS) sensing transducers, the wireless sensing unit represents a high-performance yet low-cost solution to monitoring the short-term and long-term performance of structures. A sophisticated reduced instruction set computer (RISC) microcontroller is placed at the core of the unit to accommodate on-board computations, measurement filtering and data interrogation algorithms. The functionality of the wireless sensing unit is validated through various experiments involving multiple sensing transducers interfaced to the sensing unit. In particular, MEMS-based accelerometers are used as the primary sensing transducer in this study's validation experiments. A five degree of freedom scaled test structure mounted upon a shaking table is employed for system validation.

Flight evaluation results from the general-aviation advanced avionics system program

NASA Technical Reports Server (NTRS)

Callas, G. P.; Denery, D. G.; Hardy, G. H.; Nedell, B. F.

1983-01-01

A demonstration advanced avionics system (DAAS) for general-aviation aircraft was tested at NASA Ames Research Center to provide information required for the design of reliable, low-cost, advanced avionics systems which would make general-aviation operations safer and more practicable. Guest pilots flew a DAAS-equipped NASA Cessna 402-B aircraft to evaluate the usefulness of data busing, distributed microprocessors, and shared electronic displays, and to provide data on the DAAS pilot/system interface for the design of future integrated avionics systems. Evaluation results indicate that the DAAS hardware and functional capability meet the program objective. Most pilots felt that the DAAS representative of the way avionics systems would evolve and felt the added capability would improve the safety and practicability of general-aviation operations. Flight-evaluation results compiled from questionnaires are presented, the results of the debriefings are summarized. General conclusions of the flight evaluation are included.

Development of flying qualities criteria for single pilot instrument flight operations

NASA Technical Reports Server (NTRS)

Bar-Gill, A.; Nixon, W. B.; Miller, G. E.

1982-01-01

Flying qualities criteria for Single Pilot Instrument Flight Rule (SPIFR) operations were investigated. The ARA aircraft was modified and adapted for SPIFR operations. Aircraft configurations to be flight-tested were chosen and matched on the ARA in-flight simulator, implementing modern control theory algorithms. Mission planning and experimental matrix design were completed. Microprocessor software for the onboard data acquisition system was debugged and flight-tested. Flight-path reconstruction procedure and the associated FORTRAN program were developed. Algorithms associated with the statistical analysis of flight test results and the SPIFR flying qualities criteria deduction are discussed.

Microprocessor controlled advanced battery management systems

NASA Technical Reports Server (NTRS)

Payne, W. T.

1978-01-01

The advanced battery management system described uses the capabilities of an on-board microprocessor to: (1) monitor the state of the battery on a cell by cell basis; (2) compute the state of charge of each cell; (3) protect each cell from reversal; (4) prevent overcharge on each individual cell; and (5) control dual rate reconditioning to zero volts per cell.

A Multi-Media CAI Terminal Based upon a Microprocessor with Applications for the Handicapped.

ERIC Educational Resources Information Center

Brebner, Ann; Hallworth, H. J.

The design of the CAI interface described is based on the microprocessor in order to meet three basic requirements for providing appropriate instruction to the developmentally handicapped: (1) portability, so that CAI can be taken into the customary learning environment; (2) reliability; and (3) flexibility, to permit use of new input and output…

Microcprocessing Computer Technician, Digital and Microprocessor Technician Program. Post-Graduate 5th Year.

ERIC Educational Resources Information Center

Carangelo, Pasquale R.; Janeczek, Anthony J.

Materials are provided for a two-semester digital and microprocessor technician postgraduate program. Prerequisites stated for the program include a background in DC and AC theory, solid state devices, basic circuit fundamentals, and basic math. A chronology of major topics and a listing of course objectives appear first. Theory outlines for each…

The Minerva Multi-Microprocessor.

DTIC Science & Technology

A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.

Innovative architectures for dense multi-microprocessor computers

NASA Technical Reports Server (NTRS)

Larson, Robert E.

1989-01-01

The purpose is to summarize a Phase 1 SBIR project performed for the NASA/Langley Computational Structural Mechanics Group. The project was performed from February to August 1987. The main objectives of the project were to: (1) expand upon previous research into the application of chordal ring architectures to the general problem of designing multi-microcomputer architectures, (2) attempt to identify a family of chordal rings such that each chordal ring can be simply expanded to produce the next member of the family, (3) perform a preliminary, high-level design of an expandable multi-microprocessor computer based upon chordal rings, (4) analyze the potential use of chordal ring based multi-microprocessors for sparse matrix problems and other applications arising in computational structural mechanics.

EFFECTS OF THE GENIUM MICROPROCESSOR KNEE SYSTEM ON KNEE MOMENT SYMMETRY DURING HILL WALKING.

PubMed

Highsmith, M Jason; Klenow, Tyler D; Kahle, Jason T; Wernke, Matthew M; Carey, Stephanie L; Miro, Rebecca M; Lura, Derek J

2016-09-01

Use of the Genium microprocessor knee (MPK) system reportedly improves knee kinematics during walking and other functional tasks compared to other MPK systems. This improved kinematic pattern was observed when walking on different hill conditions and at different speeds. Given the improved kinematics associated with hill walking while using the Genium, a similar improvement in the symmetry of knee kinetics is also feasible. The purpose of this study was to determine if Genium MPK use would reduce the degree of asymmetry (DoA) of peak stance knee flexion moment compared to the C-Leg MPK in transfemoral amputation (TFA) patients. This study used a randomized experimental crossover of TFA patients using Genium and C-Leg MPKs ( n = 20). Biomechanical gait analysis by 3D motion tracking with floor mounted force plates of TFA patients ambulating at different speeds on 5° ramps was completed. Knee moment DoA was significantly different between MPK conditions in the slow and fast uphill as well as the slow and self-selected downhill conditions. In a sample of high-functioning TFA patients, Genium knee system accommodation and use improved knee moment symmetry in slow speed walking up and down a five degree ramp compared with C-Leg. Additionally, the Genium improved knee moment symmetry when walking downhill at comfortable speed. These results likely have application in other patients who could benefit from more consistent knee function, such as older patients and others who have slower walking speeds.

Controller Chips Preserve Microprocessor Function

NASA Technical Reports Server (NTRS)

2012-01-01

Above the Atlantic Ocean, off the coast of Brazil, there is a dip in the Earth s surrounding magnetic field called the South Atlantic Anomaly. Here, space radiation can reach into Earth s upper atmosphere to interfere with the functioning of satellites, aircraft, and even the International Space Station. "The South Atlantic Anomaly is a hot spot of radiation that the space station goes through at a certain point in orbit," Miria Finckenor, a physicist at Marshall Space Flight Center, describes, "If there s going to be a problem with the electronics, 90 percent of that time, it is going to be in that spot." Space radiation can cause physical damage to microchips and can actually change the software commands in computers. When high-energy particles penetrate a satellite or other spacecraft, the electrical components can absorb the energy and temporarily switch off. If the energy is high enough, it can cause the device to enter a hung state, which can only be addressed by restarting the system. When space radiation affects the operational status of microprocessors, the occurrence is called single event functional interrupt (SEFI). SEFI happens not only to the computers onboard spacecraft in Earth orbit, but to the computers on spacecraft throughout the solar system. "One of the Mars rovers had this problem in the radiation environment and was rebooting itself several times a day. On one occasion, it rebooted 40 times in one day," Finckenor says. "It s hard to obtain any data when you have to constantly reboot and start over."

Fast Initialization of Bubble-Memory Systems

NASA Technical Reports Server (NTRS)

Looney, K. T.; Nichols, C. D.; Hayes, P. J.

1986-01-01

Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

Electronic system for data acquisition to study radiation effects on operating MOSFET transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alves de Oliveira, Juliano; Assis de Melo, Marco Antônio; Guazzelli da Silveira, Marcilei A.

In this work we present the development of an acquisition system for characterizing transistors under X-ray radiation. The system is able to carry out the acquisition and to storage characteristic transistor curves. To test the acquisition system we have submitted polarized P channel MOS transistors under continuous 10-keV X-ray doses up to 1500 krad. The characterization system can operate in the saturation region or in the linear region in order to observe the behavior of the currents or voltages involved during the irradiation process. Initial tests consisted of placing the device under test (DUT) in front of the X-ray beammore » direction, while its drain current was constantly monitored through the prototype generated in this work, the data are stored continuously and system behavior was monitored during the test. In order to observe the behavior of the DUT during the radiation tests, we used an acquisition system that consists of an ultra-low consumption16-bit Texas Instruments MSP430 microprocessor. Preliminary results indicate linear behavior of the voltage as a function of the exposure time and fast recovery. These features may be favorable to use this device as a radiation dosimeter to monitor low rate X-ray.« less

Ambulatory ventricular function monitor: validation and preliminary clinical results

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wilson, R.A.; Sullivan, P.J.; Moore, R.H.

1983-09-01

A device for the continuous measurement of left ventricular (LV) function was tested in a series of 34 subjects. The instrument consisted of 2 arrays of radiation sensitive cadmium telluride detectors held in place over the region of the left ventricle and lung by a vest-like garment (hence the name VEST). The VEST electronic instrumentation included analog-to-digital converters, a battery pack, microprocessor and gating device, which were worn in a back pack. Data generated by the VEST, including the digitized average electrocardiogram, RR interval, counts/13 ms in each radiation detector, and time since commencement of data recording, were recorded onmore » a cassette tape recorder every 2 minutes for subsequent analysis. At the conclusion of conventional multigated blood pool imaging, the VEST was positioned and worn by the subjects while supine, standing in place and walking. The correlation of ejection fraction calculated independently from the VEST and scintillation camera data was >0.95. The inter-record reproducibility of the ejection fraction measured by the VEST in sedentary subjects was <3%. 22 references, 6 figures.« less

General-Purpose Electronic System Tests Aircraft

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1989-01-01

Versatile digital equipment supports research, development, and maintenance. Extended aircraft interrogation and display system is general-purpose assembly of digital electronic equipment on ground for testing of digital electronic systems on advanced aircraft. Many advanced features, including multiple 16-bit microprocessors, pipeline data-flow architecture, advanced operating system, and resident software-development tools. Basic collection of software includes program for handling many types of data and for displays in various formats. User easily extends basic software library. Hardware and software interfaces to subsystems provided by user designed for flexibility in configuration to meet user's requirements.

A Microprocessor Development System for the ALTOS Series Microcomputers.

DTIC Science & Technology

1981-06-01

location, and 3) routines for online user self-help and system use instructions. The primary ccnsideration in the desin of the HOST control program was...TO LOWER CASE CPI ;rYNAMIC SET ITEMIZE JZ MAKEI CPI Vt" ;LYNAMIC SET TOTAL ONLY JZ MAKET CPI "e JNZ STACKIT ;RESTART TEST IF NOT E MEM55 LXI HMEMM...RESET STACK JMP MEM0I ;RESTART TEST MAKEI MVI All ;MAKE ITEMIZE STA MEMP CALL BSOUT RET MAKET MJI A,O ;MAKE TOTAL ONLY STA MEMP CALL BSOUT RET * LONE WITH

Reliability Testing on the CTI-Cryogenic 1 Watt Integral Cooler (HD- 1033C/UA)

DTIC Science & Technology

1989-09-01

SUBJECT TERMS (Continue on reverse if necessary and identify by block numbe) FIELD GROUP SUB- GROUP Cryocooler, Stirling Cycle, Cryogenics 19, ABSTRCT...the Army. C2NVEO also maintains configuration management control of the forward-looking infrared (FLIR) Common Module coolers used in thermal imagers... controlled high/low temperature chamber. * A microprocessor which was programmed to automatically cycle the temperature in the chamber in accordance

A programmable transformer coupled converter for high-power space applications

NASA Technical Reports Server (NTRS)

Kapustka, R. E.; Bush, J. R., Jr.; Graves, J. R.; Lanier, J. R., Jr.

1986-01-01

A programmable transformer coupled converter (PTCC) is being developed by NASA/Marshall Space Flight Center for application in future large space power systems. The PTCC uses an internal microprocessor to control the output characteristics of its three Cuk integrated magnetics type power stages which have a combined capability of 5.4 kW (30 V at 180 A). Details of design trade-offs and test results are presented.

The SMile Card: a computerised data card for multiple sclerosis patients. SMile Card Scientific Board.

PubMed

Mancardi, G L; Uccelli, M M; Sonnati, M; Comi, G; Milanese, C; De Vincentiis, A; Battaglia, M A

2000-04-01

The SMile Card was developed as a means for computerising clinical information for the purpose of transferability, accessibility, standardisation and compilation of a national database of demographic and clinical information about multiple sclerosis (MS) patients. In many European countries, centres for MS are organised independently from one another making collaboration, consultation and patient referral complicated. Only the more highly advanced clinical centres, generally located in large urban areas, have had the possibility to utilise technical possibilities for improving the organisation of patient clinical and research information, although independently from other centres. The information system, developed utilising the Visual Basic language for Microsoft Windows 95, stores information via a 'smart card' in a database which is initiated and updated utilising a microprocessor, located at each neurological clinic. The SMile Card, currently being tested in Italy, permits patients to carry with them all relevant medical information without limitations. Neurologists are able to access and update, via the microprocessor, the patient's entire medical history and MS-related information, including the complete neurological examination and laboratory test results. The SMile Card provides MS patients and neurologists with a complete computerised archive of clinical information which is accessible throughout the country. In addition, data from the SMile Card system can be exported to other database programs.

KENNEDY SPACE CENTER, FLA. - In KSC's Vertical Processing Facility, Louise Kleba of the Vehicle Integration Test Team (VITT) and engineer Devin Tailor of Goddard Space Flight Center examine the Pistol Grip Tool (PGT), which was designed for use by astronauts during spacewalks. The PGT is a self-contained, micro-processor controlled, battery-powered tool. It also can be used as a nonpowered ratchet wrench. The experiences of the astronauts on the first Hubble Space Telescope (HST) servicing mission led to recommendations for this smaller, more efficient tool for precision work during spacewalks. The PGT will be used on the second HST servicing mission, STS-82. Liftoff aboard Discovery is scheduled Feb. 11.

NASA Image and Video Library

1997-01-22

KENNEDY SPACE CENTER, FLA. - In KSC's Vertical Processing Facility, Louise Kleba of the Vehicle Integration Test Team (VITT) and engineer Devin Tailor of Goddard Space Flight Center examine the Pistol Grip Tool (PGT), which was designed for use by astronauts during spacewalks. The PGT is a self-contained, micro-processor controlled, battery-powered tool. It also can be used as a nonpowered ratchet wrench. The experiences of the astronauts on the first Hubble Space Telescope (HST) servicing mission led to recommendations for this smaller, more efficient tool for precision work during spacewalks. The PGT will be used on the second HST servicing mission, STS-82. Liftoff aboard Discovery is scheduled Feb. 11.

Field programmable chemistry: integrated chemical and electronic processing of informational molecules towards electronic chemical cells.

PubMed

Wagler, Patrick F; Tangen, Uwe; Maeke, Thomas; McCaskill, John S

2012-07-01

The topic addressed is that of combining self-constructing chemical systems with electronic computation to form unconventional embedded computation systems performing complex nano-scale chemical tasks autonomously. The hybrid route to complex programmable chemistry, and ultimately to artificial cells based on novel chemistry, requires a solution of the two-way massively parallel coupling problem between digital electronics and chemical systems. We present a chemical microprocessor technology and show how it can provide a generic programmable platform for complex molecular processing tasks in Field Programmable Chemistry, including steps towards the grand challenge of constructing the first electronic chemical cells. Field programmable chemistry employs a massively parallel field of electrodes, under the control of latched voltages, which are used to modulate chemical activity. We implement such a field programmable chemistry which links to chemistry in rather generic, two-phase microfluidic channel networks that are separated into weakly coupled domains. Electric fields, produced by the high-density array of electrodes embedded in the channel floors, are used to control the transport of chemicals across the hydrodynamic barriers separating domains. In the absence of electric fields, separate microfluidic domains are essentially independent with only slow diffusional interchange of chemicals. Electronic chemical cells, based on chemical microprocessors, exploit a spatially resolved sandwich structure in which the electronic and chemical systems are locally coupled through homogeneous fine-grained actuation and sensor networks and play symmetric and complementary roles. We describe how these systems are fabricated, experimentally test their basic functionality, simulate their potential (e.g. for feed forward digital electrophoretic (FFDE) separation) and outline the application to building electronic chemical cells. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

Noncontact techniques for diesel engine diagnostics using exhaust waveform analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gore, D.A.; Cooke, G.J.

1987-01-01

RCA Corporation's continuing efforts to develop noncontact test techniques for diesel engines have led to recent advancements in deep engine diagnostics. The U.S. Army Tank-Automotive Command (TACOM) has been working with RCA for the development of new noncontact sensors and test techniques which use these sensors in conjunction with their family of Simplified Test Equipment (STE) to perform vehicle diagnostics. The STE systems are microprocessor-based maintenance tools that assist the Army mechanic in diagnosing malfunctions in both tactical and combat vehicles. The test systems support the mechanic by providing the sophisticated signal processing capabilities necessary for a wide range ofmore » diagnostic testing including exhaust waveform analysis.« less

Information distribution in distributed microprocessor based flight control systems

NASA Technical Reports Server (NTRS)

Montgomery, R. C.; Lee, P. S.

1977-01-01

This paper presents an optimal control theory that accounts for variable time intervals in the information distribution to control effectors in a distributed microprocessor based flight control system. The theory is developed using a linear process model for the aircraft dynamics and the information distribution process is modeled as a variable time increment process where, at the time that information is supplied to the control effectors, the control effectors know the time of the next information update only in a stochastic sense. An optimal control problem is formulated and solved that provides the control law that minimizes the expected value of a quadratic cost function. An example is presented where the theory is applied to the control of the longitudinal motions of the F8-DFBW aircraft. Theoretical and simulation results indicate that, for the example problem, the optimal cost obtained using a variable time increment Markov information update process where the control effectors know only the past information update intervals and the Markov transition mechanism is almost identical to that obtained using a known uniform information update interval.

The Use of a Microprocessor-Controlled, Video Output Atomic Absorption Spectrometer as an Educational Tool in a Two-Year Technical Curriculum.

ERIC Educational Resources Information Center

Kerfoot, Henry B.

Based on instructional experiences at Charles County Community College, Maryland, this report examines the pedagogical advantage of teaching atomic absorption (AA) spectroscopy with an AA spectrophotometer that is equipped with a microprocessor and video output mechanism. The report first discusses the growing importance of AA spectroscopy in…

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Microprocessor control of photovoltaic systems

NASA Technical Reports Server (NTRS)

Millner, A. R.; Kaufman, D. L.

1984-01-01

The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

Analysis of inadvertent microprocessor lag time on eddy covariance results

Treesearch

Karl Zeller; Gary Zimmerman; Ted Hehn; Evgeny Donev; Diane Denny; Jeff Welker

2001-01-01

Researchers using the eddy covariance approach to measuring trace gas fluxes are often hoping to measure carbon dioxide and energy fluxes for ecosystem intercomparisons. This paper demonstrates a systematic microprocessor- caused lag of 20.1 to 20.2 s in a commercial sonic anemometer-analog-to-digital datapacker system operated at 10 Hz. The result of the inadvertent...

A real-time implementation of an advanced sensor failure detection, isolation, and accommodation algorithm

NASA Technical Reports Server (NTRS)

Delaat, J. C.; Merrill, W. C.

1983-01-01

A sensor failure detection, isolation, and accommodation algorithm was developed which incorporates analytic sensor redundancy through software. This algorithm was implemented in a high level language on a microprocessor based controls computer. Parallel processing and state-of-the-art 16-bit microprocessors are used along with efficient programming practices to achieve real-time operation.

Mark IVA microprocessor support

NASA Technical Reports Server (NTRS)

Burford, A. L.

1982-01-01

The requirements and plans for the maintenance support of microprocessor-based controllers in the Deep Space Network Mark IVA System are discussed. Additional new interfaces and 16-bit processors have introduced problems not present in the Mark III System. The need for continuous training of maintenance personnel to maintain a level of expertise consistent with the sophistication of the required tools is also emphasized.

European Science Notes Information Bulletin Reports on Current European and Middle Eastern Science

DTIC Science & Technology

1992-01-01

evclopment in the Abbey-Polymer Processing and Properties ................... 524 J, Magill Corrosion and Protection Centre at the University of...34* Software Engineering and microprocessors and communication chips. The Information Processing Systems recently announced T9000 microprocessor will...computational fluid dynamics, struc- In addition to general and special-purpose tural mechanics, partial differential equations, processing , Europe has a

A survey of the state of the art and focused research in range systems, task 2

NASA Technical Reports Server (NTRS)

Yao, K.

1986-01-01

Many communication, control, and information processing subsystems are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since, in general, the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, the optimum powers of two coefficient solution was considered. Detailed explanations on the use of branch-and-bound algorithms for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is dully applicable to many other microprocessor controlled information processing systems.

Microprocessor dynamics and interactions at endogenous imprinted C19MC microRNA genes.

PubMed

Bellemer, Clément; Bortolin-Cavaillé, Marie-Line; Schmidt, Ute; Jensen, Stig Mølgaard Rask; Kjems, Jørgen; Bertrand, Edouard; Cavaillé, Jérôme

2012-06-01

Nuclear primary microRNA (pri-miRNA) processing catalyzed by the DGCR8-Drosha (Microprocessor) complex is highly regulated. Little is known, however, about how microRNA biogenesis is spatially organized within the mammalian nucleus. Here, we image for the first time, in living cells and at the level of a single microRNA cluster, the intranuclear distribution of untagged, endogenously-expressed pri-miRNAs generated at the human imprinted chromosome 19 microRNA cluster (C19MC), from the environment of transcription sites to single molecules of fully released DGCR8-bound pri-miRNAs dispersed throughout the nucleoplasm. We report that a large fraction of Microprocessor concentrates onto unspliced C19MC pri-miRNA deposited in close proximity to their genes. Our live-cell imaging studies provide direct visual evidence that DGCR8 and Drosha are targeted post-transcriptionally to C19MC pri-miRNAs as a preformed complex but dissociate separately. These dynamics support the view that, upon pri-miRNA loading and most probably concomitantly with Drosha-mediated cleavages, Microprocessor undergoes conformational changes that trigger the release of Drosha while DGCR8 remains stably bound to pri-miRNA.

NSC 800, 8-bit CMOS microprocessor

NASA Technical Reports Server (NTRS)

Suszko, S. F.

1984-01-01

The NSC 800 is an 8-bit CMOS microprocessor manufactured by National Semiconductor Corp., Santa Clara, California. The 8-bit microprocessor chip with 40-pad pin-terminals has eight address buffers (A8-A15), eight data address -- I/O buffers (AD(sub 0)-AD(sub 7)), six interrupt controls and sixteen timing controls with a chip clock generator and an 8-bit dynamic RAM refresh circuit. The 22 internal registers have the capability of addressing 64K bytes of memory and 256 I/O devices. The chip is fabricated on N-type (100) silicon using self-aligned polysilicon gates and local oxidation process technology. The chip interconnect consists of four levels: Aluminum, Polysi 2, Polysi 1, and P(+) and N(+) diffusions. The four levels, except for contact interface, are isolated by interlevel oxide. The chip is packaged in a 40-pin dual-in-line (DIP), side brazed, hermetically sealed, ceramic package with a metal lid. The operating voltage for the device is 5 V. It is available in three operating temperature ranges: 0 to +70 C, -40 to +85 C, and -55 to +125 C. Two devices were submitted for product evaluation by F. Stott, MTS, JPL Microprocessor Specialist. The devices were pencil-marked and photographed for identification.

Transient Heat Conduction Simulation around Microprocessor Die

NASA Astrophysics Data System (ADS)

Nishi, Koji

This paper explains about fundamental formula of calculating power consumption of CMOS (Complementary Metal-Oxide-Semiconductor) devices and its voltage and temperature dependency, then introduces equation for estimating power consumption of the microprocessor for notebook PC (Personal Computer). The equation is applied to heat conduction simulation with simplified thermal model and evaluates in sub-millisecond time step calculation. In addition, the microprocessor has two major heat conduction paths; one is from the top of the silicon die via thermal solution and the other is from package substrate and pins via PGA (Pin Grid Array) socket. Even though the dominant factor of heat conduction is the former path, the latter path - from package substrate and pins - plays an important role in transient heat conduction behavior. Therefore, this paper tries to focus the path from package substrate and pins, and to investigate more accurate method of estimating heat conduction paths of the microprocessor. Also, cooling performance expression of heatsink fan is one of key points to assure result with practical accuracy, while finer expression requires more computation resources which results in longer computation time. Then, this paper discusses the expression to minimize computation workload with a practical accuracy of the result.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Real-time fetal ECG system design using embedded microprocessors

NASA Astrophysics Data System (ADS)

Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

2016-05-01

The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

Virtual Sensor Test Instrumentation

NASA Technical Reports Server (NTRS)

Wang, Roy

2011-01-01

Virtual Sensor Test Instrumentation is based on the concept of smart sensor technology for testing with intelligence needed to perform sell-diagnosis of health, and to participate in a hierarchy of health determination at sensor, process, and system levels. A virtual sensor test instrumentation consists of five elements: (1) a common sensor interface, (2) microprocessor, (3) wireless interface, (4) signal conditioning and ADC/DAC (analog-to-digital conversion/ digital-to-analog conversion), and (5) onboard EEPROM (electrically erasable programmable read-only memory) for metadata storage and executable software to create powerful, scalable, reconfigurable, and reliable embedded and distributed test instruments. In order to maximize the efficient data conversion through the smart sensor node, plug-and-play functionality is required to interface with traditional sensors to enhance their identity and capabilities for data processing and communications. Virtual sensor test instrumentation can be accessible wirelessly via a Network Capable Application Processor (NCAP) or a Smart Transducer Interlace Module (STIM) that may be managed under real-time rule engines for mission-critical applications. The transducer senses the physical quantity being measured and converts it into an electrical signal. The signal is fed to an A/D converter, and is ready for use by the processor to execute functional transformation based on the sensor characteristics stored in a Transducer Electronic Data Sheet (TEDS). Virtual sensor test instrumentation is built upon an open-system architecture with standardized protocol modules/stacks to interface with industry standards and commonly used software. One major benefit for deploying the virtual sensor test instrumentation is the ability, through a plug-and-play common interface, to convert raw sensor data in either analog or digital form, to an IEEE 1451 standard-based smart sensor, which has instructions to program sensors for a wide variety of functions. The sensor data is processed in a distributed fashion across the network, providing a large pool of resources in real time to meet stringent latency requirements.

Embedded algorithms within an FPGA-based system to process nonlinear time series data

NASA Astrophysics Data System (ADS)

Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

2008-03-01

This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better computational and power efficiency.

Deformability in the cleavage site of primary microRNA is not sensed by the double-stranded RNA binding domains in the microprocessor component DGCR8.

PubMed

Quarles, Kaycee A; Chadalavada, Durga; Showalter, Scott A

2015-06-01

The prevalence of double-stranded RNA (dsRNA) in eukaryotic cells has only recently been appreciated. Of interest here, RNA silencing begins with dsRNA substrates that are bound by the dsRNA-binding domains (dsRBDs) of their processing proteins. Specifically, processing of microRNA (miRNA) in the nucleus minimally requires the enzyme Drosha and its dsRBD-containing cofactor protein, DGCR8. The smallest recombinant construct of DGCR8 that is sufficient for in vitro dsRNA binding, referred to as DGCR8-Core, consists of its two dsRBDs and a C-terminal tail. As dsRBDs rarely recognize the nucleotide sequence of dsRNA, it is reasonable to hypothesize that DGCR8 function is dependent on the recognition of specific structural features in the miRNA precursor. Previously, we demonstrated that noncanonical structural elements that promote RNA flexibility within the stem of miRNA precursors are necessary for efficient in vitro cleavage by reconstituted Microprocessor complexes. Here, we combine gel shift assays with in vitro processing assays to demonstrate that neither the N-terminal dsRBD of DGCR8 in isolation nor the DGCR8-Core construct is sensitive to the presence of noncanonical structural elements within the stem of miRNA precursors, or to single-stranded segments flanking the stem. Extending DGCR8-Core to include an N-terminal heme-binding region does not change our conclusions. Thus, our data suggest that although the DGCR8-Core region is necessary for dsRNA binding and recruitment to the Microprocessor, it is not sufficient to establish the previously observed connection between RNA flexibility and processing efficiency. © 2015 Wiley Periodicals, Inc.

Fiber Laser methane sensor with the function of self-diagnose

NASA Astrophysics Data System (ADS)

Li, Yan-fang; Wei, Yu-bin; Shang, Ying; Wang, Chang; Liu, Tong-yu

2012-02-01

Using the technology of tunable diode laser absorption spectroscopy and the technology of micro-electronics, a fiber laser methane sensor based on the microprocessor C8051F410 is given. In this paper, we use the DFB Laser as the light source of the sensor. By tuning temperature and driver current of the DFB laser, we can scan the laser over the methane absorption line, Based on the Beer-Lambert law, through detect the variation of the light power before and after the absorption we realize the methane detection. It makes the real-time and online detection of methane concentration to be true, and it has the advantages just as high accuracy, immunity to other gases , long calibration cycle and so on. The sensor has the function of adaptive gain and self-diagnose. By introducing digital potentiometers, the gain of the photoelectric conversion operational amplifier can be controlled by the microprocessor according to the light power. When the gain and the conversion voltage achieve the set value, then we can consider the sensor in a fault status, and then the software will alarm us to check the status of the probe. So we improved the dependence and the stability of the measured results. At last we give some analysis on the sensor according the field application and according the present working, we have a look of our next work in the distance.

A Microprocessor-Controlled Data Acquisition System for the Federal Scientific Model UA-500-1 Ubiquitous Spectrum Analyzer

DTIC Science & Technology

1976-09-01

Model AN/ UGC -59A teletype and paper-tape punch console. This unit is connected with the Intellec 8 computer and punching operations are controlled by...order to use this program, the microprocessor would have to be one of the many types on the market that make use of the INTEL 8008-1 CPD chip. The use

Design of a Distributed Microprocessor Sensor System

DTIC Science & Technology

1990-04-01

implemented through these methods, multiversion software and recovery the use of multiple identical software tasks running on blocks, are intended to... Multiversion software for real-time systems tolerant microprocessor that uses three processing is discussed by Shepherd32, Hitt33, Avizienis’, and...tasks and the there are no data available to determine the cost third is used for noncritical tasks. If a discrepancy effectiveness of multiversion

A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

NASA Astrophysics Data System (ADS)

Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

1986-06-01

This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

Microprocessor controlled transdermal drug delivery.

PubMed

Subramony, J Anand; Sharma, Ashutosh; Phipps, J B

2006-07-06

Transdermal drug delivery via iontophoresis is reviewed with special focus on the delivery of lidocaine for local anesthesia and fentanyl for patient controlled acute therapy such as postoperative pain. The role of the microprocessor controller in achieving dosimetry, alternating/reverse polarity, pre-programmed, and sensor-based delivery is highlighted. Unique features such as the use of tactile signaling, telemetry control, and pulsatile waveforms in iontophoretic drug delivery are described briefly.

A microarchitecture for resource-limited superscalar microprocessors

NASA Astrophysics Data System (ADS)

Basso, Todd David

1999-11-01

Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

A test matrix sequencer for research test facility automation

NASA Technical Reports Server (NTRS)

Mccartney, Timothy P.; Emery, Edward F.

1990-01-01

The hardware and software configuration of a Test Matrix Sequencer, a general purpose test matrix profiler that was developed for research test facility automation at the NASA Lewis Research Center, is described. The system provides set points to controllers and contact closures to data systems during the course of a test. The Test Matrix Sequencer consists of a microprocessor controlled system which is operated from a personal computer. The software program, which is the main element of the overall system is interactive and menu driven with pop-up windows and help screens. Analog and digital input/output channels can be controlled from a personal computer using the software program. The Test Matrix Sequencer provides more efficient use of aeronautics test facilities by automating repetitive tasks that were once done manually.

Virtex-II Pro PowerPC SEE Characterization Test Methods and Results

NASA Technical Reports Server (NTRS)

Petrick, David; Powell, Wesley; LaBel, Ken; Howard, James

2005-01-01

The Xilinx Vix-11 Pro is a platform FPGA that embeds multiple microprocessors within the fabric of an SRAM-based reprogrammable FPGA. The variety and quantity of resources provided by this family of devices make them very attractive for spaceflight applications. However,these devices will be susceptible to single event effects (SEE), which must be mitigated. Observations from prior testing of the Xilinx Virtex-II Pro suggest that the PowerPC core has significant vulnerability to SEES. However, these initial tests were not designed to exclusively target the functionality of the PowerPC, therefore making it difficult to distinguish processor upsets from fabric upsets. The main focus of this paper involves detailed SEE testing of the embedded PowerPC core. Due to the complexity of the PowerPC, various custom test applications, both static and dynamic, will be designed to isolate each Unit of the processor. Collective analysis of the test results will provide insight into the exact upset mechanism of the PowerPC. With this information, mitigations schemes can be developed and tested that address the specific susceptibilities of these devices. The test bed will be the Xilinx SEE Consortium Virtex-II Pro test board, which allows for configuration scrubbing, design triplication, and ease of data collection. Testing will be performed at the Indiana University Cyclotron Facility using protons of varying energy levels and fluencies. This paper will present the detailed test approach along with the results.

A Flight Investigation of Digital Control Using Microprocessor Technology.

DTIC Science & Technology

1979-06-01

software development system (Fig. 3-4) allow programs to be entered and tested efficiently. The ground chasis 3-7 pF MIRO -DFCS HOUSING I ANALOG...6E/V .125 06 La/V Lca/V/10 .200 07 L /V 100 LV/V .200 V 08 Step Gust .100 Scaling 10 D-VT V.073 11 Da-g Da.g/10o .060 12 g g/100 . 322 13 Vscale 1003x

Bone Analyzer

NASA Technical Reports Server (NTRS)

1985-01-01

The danger of disuse osteoporosis under weightless condition in space led to extensive research into measurements of bone stiffness and mass by the Biomedical Research Division of Ames and Stanford University. Through its Technology Utilization Program, NASA funded an advanced SOBSA, a microprocessor-controlled bone probe system. SOBSA determines bone stiffness by measuring responses to an electromagnetic shaker. With this information, a physician can identify bone disease, measure deterioration and prescribe necessary therapy. The system is now undergoing further testing.

The Shock and Vibration Digest. Volume 18, Number 9

DTIC Science & Technology

1986-09-01

microprocessors. ods for mobility measurements, methods for Modeling and computation of transient rotor analyzing mobility data, mathematical modeling...behavior and nonlinear fluid-film bearing from mobility data, and applications of modal behavior will be described. Sessions will be test results will be...Zoned Viscoelastic Analysis of the Response of Dams to Earth- soil, quakesR. Abascal, J. Dominguez V. Lotfi , N6 445 • . , .-e ’SJ. PP %-’ , Ph.D. Thesis

Development report: Automatic System Test and Calibration (ASTAC) equipment

NASA Technical Reports Server (NTRS)

Thoren, R. J.

1981-01-01

A microcomputer based automatic test system was developed for the daily performance monitoring of wind energy system time domain (WEST) analyzer. The test system consists of a microprocessor based controller and hybrid interface unit which are used for inputing prescribed test signals into all WEST subsystems and for monitoring WEST responses to these signals. Performance is compared to theoretically correct performance levels calculated off line on a large general purpose digital computer. Results are displayed on a cathode ray tube or are available from a line printer. Excessive drift and/or lack of repeatability of the high speed analog sections within WEST is easily detected and the malfunctioning hardware identified using this system.

A Monitoring System for Vegetable Greenhouses based on a Wireless Sensor Network

PubMed Central

Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

2010-01-01

A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetatables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring. PMID:22163391

A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

NASA Technical Reports Server (NTRS)

Braswell, F. M.

1981-01-01

An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles.

A rocket-borne pulse-height analyzer for energetic particle measurements

NASA Technical Reports Server (NTRS)

Leung, W.; Smith, L. G.; Voss, H. D.

1979-01-01

The pulse-height analyzer basically resembles a time-sharing multiplexing data-acquisition system which acquires analog data (from energetic particle spectrometers) and converts them into digital code. The PHA simultaneously acquires pulse-height information from the analog signals of the four input channels and sequentially multiplexes the digitized data to a microprocessor. The PHA together with the microprocessor form an on-board real-time data-manipulation system. The system processes data obtained during the rocket flight and reduces the amount of data to be sent back to the ground station. Consequently the data-reduction process for the rocket experiments is speeded up. By using a time-sharing technique, the throughput rate of the microprocessor is increased. Moreover, data from several particle spectrometers are manipulated to share one information channel; consequently, the TM capacity is increased.

European Scientific Notes. Volume 35, Number 12,

DTIC Science & Technology

1981-12-31

been redesigned to work A. Osorio, which was organized some 3 with the Intel 8085 microprocessor, it years ago and contains about half of the has the...operational set. attempt to derive a set of invariants MOISE is based on the Intel 8085A upon which virtually speaker-invariant microprocessor, and...FACILITY software interface; a Research Signal Processor (RSP) using reduced computational It has been IBM International’s complexity algorithms for

FEDS - An experiment with a microprocessor-based orbit determination system using TDRS data

NASA Technical Reports Server (NTRS)

Shank, D.; Pajerski, R.

1986-01-01

An experiment in microprocessor-based onboard orbit determination has been conducted at NASA's Goddard Space Flight Center. The experiment collected forward-link observation data in real time from a prototype transponder and performed orbit estimation on a typical low-earth scientific satellite. This paper discusses the hardware and organizational configurations of the experiment, the structure of the onboard software, the mathematical models, and the experiment results.

Simplified microprocessor design for VLSI control applications

NASA Technical Reports Server (NTRS)

Cameron, K.

1991-01-01

A design technique for microprocessors combining the simplicity of reduced instruction set computers (RISC's) with the richer instruction sets of complex instruction set computers (CISC's) is presented. They utilize the pipelined instruction decode and datapaths common to RISC's. Instruction invariant data processing sequences which transparently support complex addressing modes permit the formulation of simple control circuitry. Compact implementations are possible since neither complicated controllers nor large register sets are required.

Industry Study, Electronics Industry, Spring 2009

DTIC Science & Technology

2009-01-01

Toshiba, Samsung , and NEC.7 The microprocessor is a central processing unit containing hundreds of millions of transistors and logic to perform...business with an 11.7% market share followed closely by Samsung with a 10.3% market share.40 Intel is the leader in the production of microprocessors...while Samsung is the leading memory chip producer. Other US chip manufacturers include Texas Instruments (TI), Advanced Micro Devices (AMD), Micron

Association of a peptoid ligand with the apical loop of pri-miR-21 inhibits cleavage by Drosha

PubMed Central

Diaz, Jason P.; Chirayil, Rachel; Chirayil, Sara; Tom, Martin; Head, Katie J.; Luebke, Kevin J.

2014-01-01

We have found a small molecule that specifically inhibits cleavage of a precursor to the oncogenic miRNA, miR-21, by the microprocessor complex of Drosha and DGCR8. We identified novel ligands for the apical loop of this precursor from a screen of 14,024 N-substituted oligoglycines (peptoids) in a microarray format. Eight distinct compounds with specific affinity were obtained, three having affinities for the targeted loop in the low micromolar range and greater than 15-fold discrimination against a closely related hairpin. One of these compounds completely inhibits microprocessor cleavage of a miR-21 primary transcript at concentrations at which cleavage of another miRNA primary transcript, pri-miR-16, is little affected. The apical loop of pri-miR-21, placed in the context of pri-miR-16, is sufficient for inhibition of microprocessor cleavage by the peptoid. This compound also inhibits cleavage of pri-miR-21 containing the pri-miR-16 apical loop, suggesting an additional site of association within pri-miR-21. The reported peptoid is the first example of a small molecule that inhibits microprocessor cleavage by binding to the apical loop of a pri-miRNA. PMID:24497550

Portable neutron spectrometer and dosimeter

DOEpatents

Waechter, D.A.; Erkkila, B.H.; Vasilik, D.G.

The disclosure relates to a battery operated neutron spectrometer/dosimeter utilizing a microprocessor, a built-in tissue equivalent LET neutron detector, and a 128-channel pulse height analyzer with integral liquid crystal display. The apparatus calculates doses and dose rates from neutrons incident on the detector and displays a spectrum of rad or rem as a function of keV per micron of equivalent tissue and also calculates and displays accumulated dose in millirads and millirem as well as neutron dose rates in millirads per hour and millirem per hour.

Intercommunications in Real Time, Redundant, Distributed Computer System

NASA Technical Reports Server (NTRS)

Zanger, H.

1980-01-01

An investigation into the applicability of fiber optic communication techniques to real time avionic control systems, in particular the total automatic flight control system used for the VSTOL aircraft is presented. The system consists of spatially distributed microprocessors. The overall control function is partitioned to yield a unidirectional data flow between the processing elements (PE). System reliability is enhanced by the use of triple redundancy. Some general overall system specifications are listed here to provide the necessary background for the requirements of the communications system.

System design and installation for RS600 programmable control system for solar heating and cooling

NASA Technical Reports Server (NTRS)

1978-01-01

Procedures for installing, operating, and maintaining a programmable control system which utilizes a F8 microprocessor to perform all timing, control, and calculation functions in order to customize system performance to meet individual requirements for solar heating, combined heating and cooling, and/or hot water systems are described. The manual discusses user configuration and options, displays, theory of operation, trouble-shooting procedures, and warranty and assistance. Wiring lists, parts lists, drawings, and diagrams are included.

Flutter Generator Control and Force Computer.

DTIC Science & Technology

1985-07-01

exciter module 2. Mechanical load 3. Rectifier and triac 4. Overall system 5. Velocity control 6. Microprocessor 7. Operation in 1 ’g’ environment 8...amplifier Output voltage from the rectifier/ triac circuit (figure 3) is a function of the conduction angle of each triac . In a 400 Hz 3-phase system...3IIGCICI FIRING CIRCUIT FIRING CIRCUIT TO MOTOR Figure 3. Rectifier and triac _____ -=low AEL-0242-TNI Figure 4 DEMAND(V V49 -9 APIFE M O T OR

Embedded control system for computerized franking machine

NASA Astrophysics Data System (ADS)

Shi, W. M.; Zhang, L. B.; Xu, F.; Zhan, H. W.

2007-12-01

This paper presents a novel control system for franking machine. A methodology for operating a franking machine using the functional controls consisting of connection, configuration and franking electromechanical drive is studied. A set of enabling technologies to synthesize postage management software architectures driven microprocessor-based embedded systems is proposed. The cryptographic algorithm that calculates mail items is analyzed to enhance the postal indicia accountability and security. The study indicated that the franking machine is reliability, performance and flexibility in printing mail items.

Portable neutron spectrometer and dosimeter

DOEpatents

Waechter, David A.; Erkkila, Bruce H.; Vasilik, Dennis G.

1985-01-01

The disclosure relates to a battery operated neutron spectrometer/dosimeter utilizing a microprocessor, a built-in tissue equivalent LET neutron detector, and a 128-channel pulse height analyzer with integral liquid crystal display. The apparatus calculates doses and dose rates from neutrons incident on the detector and displays a spectrum of rad or rem as a function of keV per micron of equivalent tissue and also calculates and displays accumulated dose in millirads and millirem as well as neutron dose rates in millirads per hour and millirem per hour.

A micro-computer-based system to compute magnetic variation

NASA Technical Reports Server (NTRS)

Kaul, Rajan

1987-01-01

A mathematical model of magnetic variation in the continental United States was implemented in the Ohio University Loran-C receiver. The model is based on a least squares fit of a polynomial function. The implementation on the microprocessor based Loran-C receiver is possible with the help of a math chip which performs 32 bit floating point mathematical operations. A Peripheral Interface Adapter is used to communicate between the 6502 based microcomputer and the 9511 math chip. The implementation provides magnetic variation data to the pilot as a function of latitude and longitude. The model and the real time implementation in the receiver are described.

An Economic Analysis of Two Groundwater Allocation Programs for the Salinas Valley

DTIC Science & Technology

1994-06-01

monitoring system would establish a definable and 17Each individual well would have a frequency generator, analog/ digital converter, microprocessor with...RTU). The cost for purchasing and installing the frequency generator is estimated to be $1,100. The RTU consists of an analog/ digital converter and a...programmable microprocessor that can accept up to eight inputs and one output. The unit can transmit and receive digital data via LAN network or

Programmable data collection platform study

NASA Technical Reports Server (NTRS)

1976-01-01

The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.

High-Speed Integrated Circuits for Military Applications.

DTIC Science & Technology

1979-11-01

1.5 pm circuits at the present time. " Market economics do not justify these circuits in the time frame of the VHSI program." See also Ref. 9. 7 per...on microprocessors currently in production, but the huge commercial market that is thought to exist for these devices when they can at last be...Subsection I, below). The single-chip microprocessor dominates the commercial market and those military applications for which their through- put is

Design and Development of a Multiprogramming Operating System for Sixteen Bit Microprocessors.

DTIC Science & Technology

1981-12-01

with the technical details of how services are programmed or produced, except perhaps when they fail to meet user requirements. Users are interested in...locations and loading decks. As the expense *and speed of computers increased, executive programs were created to allow several users to sequence...single user operating system as a companion to the 8080 microprocessor. CP/M (Control Program for Microcomputers) was a single user operating system that

Microprocessor Technology for Managers.

DTIC Science & Technology

1976-05-01

HOURS IS THE APPLICATION OF MICROPROCESSORS TO VIDEO GAMES SUCH AS PING PONG, HANDBALL 1 SPACE WAR GAMES , AND COWBOYS AND INDIANS. MANY MANUFACTURERS OF...MICR OPROCESSOR COMPANIES AEG—T ELEFUNKEN~ 6 FRANKFURT 70, AEG-HOCHHAUS 1 GERMANY . ADAPTIVE SYSTEMS1 P.O . BOX 1481, POMPANO BEACH , FL 33061. -(305...KAWASAKI — CHI , JAPAN . WESTERN DIGITAL , 19242 RED HILL AVE. 1 NEWPORT BEACH I CA 92663. {714) 557-3550. ZILOG, 170 STATE ST., LOS ALTOS 1 CA 94022. {415

Power Converters Maximize Outputs Of Solar Cell Strings

NASA Technical Reports Server (NTRS)

Frederick, Martin E.; Jermakian, Joel B.

1993-01-01

Microprocessor-controlled dc-to-dc power converters devised to maximize power transferred from solar photovoltaic strings to storage batteries and other electrical loads. Converters help in utilizing large solar photovoltaic arrays most effectively with respect to cost, size, and weight. Main points of invention are: single controller used to control and optimize any number of "dumb" tracker units and strings independently; power maximized out of converters; and controller in system is microprocessor.

Achieving High Performance on the i860 Microprocessor

NASA Technical Reports Server (NTRS)

Lee, King; Kutler, Paul (Technical Monitor)

1998-01-01

The i860 is a high performance microprocessor used in the Intel Touchstone project. This paper proposes a paradigm for programming the i860 that is modelled on the vector instructions of the Cray computers. Fortran callable assembler subroutines were written that mimic the concurrent vector instructions of the Cray. Cache takes the place of vector registers. Using this paradigm we have achieved twice the performance of compiled code on a traditional solve.

A programmable controller based on CAN field bus embedded microprocessor and FPGA

NASA Astrophysics Data System (ADS)

Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

2008-10-01

One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

NASA Technical Reports Server (NTRS)

Liu, Yuan-Kwei

1991-01-01

The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial change to the current DMS design at this time.

A microprocessor based on a two-dimensional semiconductor.

PubMed

Wachter, Stefan; Polyushkin, Dmitry K; Bethge, Ole; Mueller, Thomas

2017-04-11

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor-molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

A microprocessor based on a two-dimensional semiconductor

NASA Astrophysics Data System (ADS)

Wachter, Stefan; Polyushkin, Dmitry K.; Bethge, Ole; Mueller, Thomas

2017-04-01

The advent of microcomputers in the 1970s has dramatically changed our society. Since then, microprocessors have been made almost exclusively from silicon, but the ever-increasing demand for higher integration density and speed, lower power consumption and better integrability with everyday goods has prompted the search for alternatives. Germanium and III-V compound semiconductors are being considered promising candidates for future high-performance processor generations and chips based on thin-film plastic technology or carbon nanotubes could allow for embedding electronic intelligence into arbitrary objects for the Internet-of-Things. Here, we present a 1-bit implementation of a microprocessor using a two-dimensional semiconductor--molybdenum disulfide. The device can execute user-defined programs stored in an external memory, perform logical operations and communicate with its periphery. Our 1-bit design is readily scalable to multi-bit data. The device consists of 115 transistors and constitutes the most complex circuitry so far made from a two-dimensional material.

Model based design introduction: modeling game controllers to microprocessor architectures

NASA Astrophysics Data System (ADS)

Jungwirth, Patrick; Badawy, Abdel-Hameed

2017-04-01

We present an introduction to model based design. Model based design is a visual representation, generally a block diagram, to model and incrementally develop a complex system. Model based design is a commonly used design methodology for digital signal processing, control systems, and embedded systems. Model based design's philosophy is: to solve a problem - a step at a time. The approach can be compared to a series of steps to converge to a solution. A block diagram simulation tool allows a design to be simulated with real world measurement data. For example, if an analog control system is being upgraded to a digital control system, the analog sensor input signals can be recorded. The digital control algorithm can be simulated with the real world sensor data. The output from the simulated digital control system can then be compared to the old analog based control system. Model based design can compared to Agile software develop. The Agile software development goal is to develop working software in incremental steps. Progress is measured in completed and tested code units. Progress is measured in model based design by completed and tested blocks. We present a concept for a video game controller and then use model based design to iterate the design towards a working system. We will also describe a model based design effort to develop an OS Friendly Microprocessor Architecture based on the RISC-V.

Control system for a vertical axis windmill

DOEpatents

Brulle, Robert V.

1983-10-18

A vertical axis windmill having a rotating structure is provided with a series of articulated vertical blades whose positions are controlled to maintain a constant RPM for the rotating structure, when wind speed is sufficient. A microprocessor controller is used to process information on wind speed, wind direction and RPM of the rotating structure to develop an electrical signal for establishing blade position. The preferred embodiment of the invention, when connected to a utility grid, is designed to generate 40 kilowatts of power when exposed to a 20 mile per hour wind. The control system for the windmill includes electrical blade actuators that modulate the blades of the rotating structure. Blade modulation controls the blade angle of attack, which in turn controls the RPM of the rotor. In the preferred embodiment, the microprocessor controller provides the operation logic and control functions. A wind speed sensor provides inputs to start or stop the windmill, and a wind direction sensor is used to keep the blade flip region at 90.degree. and 270.degree. to the wind. The control system is designed to maintain constant rotor RPM when wind speed is between 10 and 40 miles per hour.

Control system for a vertical-axis windmill

DOEpatents

Brulle, R.V.

1981-09-03

A vertical-axis windmill having a rotating structure is provided with a series of articulated vertical blades whose positions are controlled to maintain a constant RPM for the rotating structure, when wind speed is sufficient. A microprocessor controller is used to process information on wind speed, wind direction and RPM of the rotating structure to develop an electrical signal for establishing blade position. The preferred embodiment of the invention, when connected to a utility grid, is designed to generate 40 kilowatts of power when exposed to a 20 mile per hour wind. The control system for the windmill includes electrical blade actuators that modulate the blades of the rotating structure. Blade modulation controls the blade angle of attack, which in turn controls the RPM of the rotor. In the preferred embodiment, the microprocessor controller provides the operation logic and control functions. A wind speed sensor provides inputs to start or stop the windmill, and a wind direction sensor is used to keep the blade flip region at 90 and 270/sup 0/ to the wind. The control system is designed to maintain constant rotor RPM when wind speed is between 10 and 40 miles per hour.

Importance of balanced architectures in the design of high-performance imaging systems

NASA Astrophysics Data System (ADS)

Sgro, Joseph A.; Stanton, Paul C.

1999-03-01

Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.

Design of Water Temperature Control System Based on Single Chip Microcomputer

NASA Astrophysics Data System (ADS)

Tan, Hanhong; Yan, Qiyan

2017-12-01

In this paper, we mainly introduce a multi-function water temperature controller designed with 51 single-chip microcomputer. This controller has automatic and manual water, set the water temperature, real-time display of water and temperature and alarm function, and has a simple structure, high reliability, low cost. The current water temperature controller on the market basically use bimetal temperature control, temperature control accuracy is low, poor reliability, a single function. With the development of microelectronics technology, monolithic microprocessor function is increasing, the price is low, in all aspects of widely used. In the water temperature controller in the application of single-chip, with a simple design, high reliability, easy to expand the advantages of the function. Is based on the appeal background, so this paper focuses on the temperature controller in the intelligent control of the discussion.

Instrument for controlling the application of mechanical loads to biological and bicompatible test subjects

DOEpatents

Lintilhac, Phillip M.; Vesecky, Thompson B.

1995-01-01

Apparatus and methods are disclosed facilitating the application of forces and measurement of dimensions of a test subject. In one arrangement the test subject is coupled to a forcing frame and controlled forces applied thereto. Force applied to the test subject is measured and controlled. A dimensional characteristic of the test subject, such as growth, is measured by a linear variable differential transformer. The growth measurement data can be used to control the force applied. The transducer module receives force and dimensional data from the forcing frame. The transducer module is a separate, microprocessor-based unit that communicates the test data to a controller unit that controls the application of force to the test subject and receives the test data from the transducer module for force control, storage, and/or communication to the user.

Instrument for controlling the application of mechanical loads to biological and bicompatible test subjects

DOEpatents

Lintilhac, P.M.; Vesecky, T.B.

1995-09-19

An apparatus and methods are disclosed facilitating the application of forces and measurement of dimensions of a test subject. In one arrangement the test subject is coupled to a forcing frame and controlled forces applied thereto. Force applied to the test subject is measured and controlled. A dimensional characteristic of the test subject, such as growth, is measured by a linear variable differential transformer. The growth measurement data can be used to control the force applied. The transducer module receives force and dimensional data from the forcing frame. The transducer module is a separate, microprocessor-based unit that communicates the test data to a controller unit that controls the application of force to the test subject and receives the test data from the transducer module for force control, storage, and/or communication to the user. 8 figs.

Use of a Microprocessor to Implement an ADCCP Protocol (Federal Std-1003) Operating in the Unbalanced Normal Mode.

DTIC Science & Technology

1980-05-01

andcoptrpormigfrteublne nra ls fpoeue nacrac with Federal Standard 1003 fTelecommunications: Synchronous Bit Oriented Data Link Control Procedures...and the higher level user. The solution to the producer/consumer problem involves the use of PASS and SICHAL primitives and event variables or... semaphores . The event variables have been defined for the LS-microprocessor interface as part of I-1 the internal registers that are included in the F6856

The special radiation-hardened processors for new highly informative experiments in space

NASA Astrophysics Data System (ADS)

Serdin, O. V.; Antonov, A. A.; Dubrovsky, A. G.; Novogilov, E. A.; Zuev, A. L.

2017-01-01

The article provides a detailed description of the series of special radiation-hardened microprocessor developed by SRISA for use in space technology. The microprocessors have 32-bit and 64-bit KOMDIV architecture with embedded SpaceWire, RapidIO, Ethernet and MIL-STD-1553B interfaces. These devices are used in space telescope GAMMA-400 data acquisition system, and may also be applied to other experiments in space (such as observatory “Millimetron” etc.).

A microprocessor-based multichannel subsensory stochastic resonance electrical stimulator.

PubMed

Chang, Gwo-Ching

2013-01-01

Stochastic resonance electrical stimulation is a novel intervention which provides potential benefits for improving postural control ability in the elderly, those with diabetic neuropathy, and stroke patients. In this paper, a microprocessor-based subsensory white noise electrical stimulator for the applications of stochastic resonance stimulation is developed. The proposed stimulator provides four independent programmable stimulation channels with constant-current output, possesses linear voltage-to-current relationship, and has two types of stimulation modes, pulse amplitude and width modulation.

DSS 13 Microprocessor Antenna Controller

NASA Technical Reports Server (NTRS)

Gosline, R. M.

1984-01-01

A microprocessor based antenna controller system developed as part of the unattended station project for DSS 13 is described. Both the hardware and software top level designs are presented and the major problems encounted are discussed. Developments useful to related projects include a JPL standard 15 line interface using a single board computer, a general purpose parser, a fast floating point to ASCII conversion technique, and experience gained in using off board floating point processors with the 8080 CPU.

Missile Manufacturing Technology Conference Held at Hilton Head Island, South Carolina on 22-26 September 1975. Panel Presentations: Guidance

DTIC Science & Technology

1975-01-01

Instead of the current three. Some de - tail on each component follows. II. POTENTIAL MANUFACTURING TECHNOLOGY PROJECTS Gyro Because of the...ranges of environment. With Imbedded microprocessors. It Is possible that parameters, once de - fined, can be placed within the microprocessor memory...Project cost: $53,000 Estimated duration of the project Is nine months. Benefits: Benefits to be de :ved from this project are a reduction

Use of a Microprocessor to Implement an ADCCP Protocol (Federal Standard 1003).

DTIC Science & Technology

1980-07-01

results of other studies, to evaluate the operational and economic impact of incorporating various options in Federal Standard 1003. The effort...the LSI interface and the microprocessor; the LSI chip deposits bytes in its buffer as the producer, and the MPU reads this data as the consumer...on the interface between the MPU and the LSI protocol chip. This requires two main processes to be running at the same time--transmit and receive. The

Method and apparatus for determining position using global positioning satellites

NASA Technical Reports Server (NTRS)

Ward, John (Inventor); Ward, William S. (Inventor)

1998-01-01

A global positioning satellite receiver having an antenna for receiving a L1 signal from a satellite. The L1 signal is processed by a preamplifier stage including a band pass filter and a low noise amplifier and output as a radio frequency (RF) signal. A mixer receives and de-spreads the RF signal in response to a pseudo-random noise code, i.e., Gold code, generated by an internal pseudo-random noise code generator. A microprocessor enters a code tracking loop, such that during the code tracking loop, it addresses the pseudo-random code generator to cause the pseudo-random code generator to sequentially output pseudo-random codes corresponding to satellite codes used to spread the L1 signal, until correlation occurs. When an output of the mixer is indicative of the occurrence of correlation between the RF signal and the generated pseudo-random codes, the microprocessor enters an operational state which slows the receiver code sequence to stay locked with the satellite code sequence. The output of the mixer is provided to a detector which, in turn, controls certain routines of the microprocessor. The microprocessor will output pseudo range information according to an interrupt routine in response detection of correlation. The pseudo range information is to be telemetered to a ground station which determines the position of the global positioning satellite receiver.

Microprocessor controlled movement of liquid gastric content using sequential neural electrical stimulation

PubMed Central

Mintchev, M; Sanmiguel, C; Otto, S; Bowes, K

1998-01-01

Background—Gastric electrical stimulation has been attempted for several years with little success. 
Aims—To determine whether movement of liquid gastric content could be achieved using microprocessor controlled sequential electrical stimulation. 
Methods—Eight anaesthetised dogs underwent laparotomy and implantation of four sets of bipolar stainless steel wire electrodes. Each set consisted of two to six electrodes (10×0.25 mm, 3 cm apart) implanted circumferentially. The stomach was filled with water and the process of gastric emptying was monitored. Artificial contractions were produced using microprocessor controlled phase locked bipolar four second trains of 50 Hz, 14 V (peak to peak) rectangular voltage. In four of the dogs four force transducers were implanted close to each circumferential electrode set. In one gastroparetic patient the effect of direct electrical stimulation was determined at laparotomy. 
Results—Using the above stimulating parameters circumferential gastric contractions were produced which were artificially propagated distally by phase locking the stimulating voltage. Averaged stimulated gastric emptying times were significantly shorter than spontaneus emptying times (t1/2 6.7 (3.0) versus 25.3 (12.9) minutes, p<0.01). Gastric electrical stimulation of the gastroparetic patient at operation produced circumferential contractions. 
Conclusions—Microprocessor controlled electrical stimulation produced artificial peristalsis and notably accelerated the movement of liquid gastric content. 

 Keywords: gastric electrical stimulation; gastric motility PMID:9824339

A functional comparison of conventional knee-ankle-foot orthoses and a microprocessor-controlled leg orthosis system based on biomechanical parameters.

PubMed

Schmalz, Thomas; Pröbsting, Eva; Auberger, Roland; Siewert, Gordon

2016-04-01

The microprocessor-controlled leg orthosis C-Brace enables patients with paretic or paralysed lower limb muscles to use dampened knee flexion under weight-bearing and speed-adapted control of the swing phase. The objective of the present study was to investigate the new technical functions of the C-Brace orthosis, based on biomechanical parameters. The study enrolled six patients. The C-Brace orthosis is compared with conventional leg orthoses (four stance control orthoses, two locked knee-ankle-foot orthoses) using biomechanical parameters of level walking, descending ramps and descending stairs. Ground reaction forces, joint moments and kinematic parameters were measured for level walking as well as ascending and descending ramps and stairs. With the C-Brace, a nearly natural stance phase knee flexion was measured during level walking (mean value 11° ± 5.6°). The maximum swing phase knee flexion angle of the C-Brace approached the normal value of 65° more closely than the stance control orthoses (66° ± 8.5° vs 74° ± 6.4°). No significant differences in the joint moments were found between the C-Brace and stance control orthosis conditions. In contrast to the conventional orthoses, all patients were able to ambulate ramps and stairs using a step-over-step technique with C-Brace (flexion angle 64.6° ± 8.2° and 70.5° ± 12.4°). The results show that the functions of the C-Brace for situation-dependent knee flexion under weight bearing have been used by patients with a high level of confidence. The functional benefits of the C-Brace in comparison with the conventional orthotic mechanisms could be demonstrated most clearly for descending ramps and stairs. The C-Brace orthosis is able to combine improved orthotic function with sustained orthotic safety. © The International Society for Prosthetics and Orthotics 2014.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Benefits for Adults with Transfemoral Amputations and Peripheral Artery Disease Using Microprocessor Compared with Nonmicroprocessor Prosthetic Knees.

PubMed

Wong, Christopher Kevin; Rheinstein, John; Stern, Michelle A

2015-10-01

Approximately 50% of people with leg amputation fall annually. Evidence suggests that microprocessor knees (MK) may decrease falls and improve prosthetic function in people with traumatic amputations. This study explored whether adults with transfemoral amputations and peripheral artery disease would have reduced falls and improved balance confidence, balance, and walking ability when using prostheses with MK compared with non-MK. This was a prospective cohort study. Eight subjects averaged 60.8 ± 11.3 yrs or age and 9.5 ± 16.1 yrs since first amputation. Four were K1-K2-level and four were K3-level functional walkers; only Houghton prosthetic use score was different between K1-K2 and K3 walkers (P = 0.03). After 48.3 ± 38.1 wks of acclimation using MK, subjects demonstrated improvements in fear of falling, balance confidence, Timed Up-and-Go time, and rate of falls (P < 0.05). The improvements in fear of falling, balance confidence, and rate of falls had large effect sizes (d > 0.80). Average decreased Timed Up-and-Go time (12.3 secs) had a medium effect size (d = 0.34). Decreases in the number of falls correlated with faster Timed Up-and-Go speed (ρ = -0.76) and greater balance confidence (ρ = 0.83). People with peripheral artery disease and transfemoral amputations had fewer falls and improved balance confidence and walking performance when using prostheses with MK.

Analog-digital simulation of transient-induced logic errors and upset susceptibility of an advanced control system

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Choi, G.; Iyer, R. K.

1990-01-01

A simulation study is described which predicts the susceptibility of an advanced control system to electrical transients resulting in logic errors, latched errors, error propagation, and digital upset. The system is based on a custom-designed microprocessor and it incorporates fault-tolerant techniques. The system under test and the method to perform the transient injection experiment are described. Results for 2100 transient injections are analyzed and classified according to charge level, type of error, and location of injection.

Specifications Physiological Monitoring System

NASA Technical Reports Server (NTRS)

1985-01-01

The operation of a physiological monitoring system (PMS) is described. Specifications were established for performance, design, interface, and test requirements. The PMS is a compact, microprocessor-based system, which can be worn in a pack on the body or may be mounted on a Spacelab rack or other appropriate structure. It consists of two modules, the Data Control Unit (DCU) and the Remote Control/Display Unit (RCDU). Its purpose is to collect and distribute data from physiological experiments in the Spacelab and in the Orbiter.

Human operator tracking performance with a vibrotactile display

NASA Technical Reports Server (NTRS)

Inbar, Gideon F.

1991-01-01

Vibrotactile displays have been designed and used as a sensory aid for the blind. In the present work the same 6 x 24 'Optacon' type vibrotactile display (VTD) was used to characterize human operator (HO) tracking performance in pursuit and compensatory tasks. The VTD was connected via a microprocessor to a one-dimensional joy stick manipulator. Various display schemes were tested on the VDT, and were also compared to visual tracking performance using a specially constructed photo diode matrix display comparable to the VTD.

Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Korsah, K.

This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I&C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I&C system upgrades of present-day nuclear power plants, as well as I&C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current,more » analog-based I&C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC document was published in 1998, and should reflect any new qualification concerns, from the European perspective, with regard to the use of microprocessor-based safety systems in power plants.« less

A micrometeoroid deceleration and capture experiment: Conceptual experiment design description

NASA Technical Reports Server (NTRS)

Wolfe, J. H.; Ballard, R. W.; Carle, G. C.; Bunch, T. E.

1986-01-01

The preliminary conceptual design for a cosmic dust collector is described. For the case of low Earth orbit (LEO), dust particles enter the collector through the collimator at a few volts negative potential due to charging in the ionosphere, at a velocity of 1 to 50 km/sec. The particles then pass through an electron stream and are charged to about 1 KV negative (regardless of incoming polarity). The 1 KV negatively charged particle then passes through three sensing grids coupled to charge sensitive preamps (CSP). The comparison of the two pulses provided by S(1) and S(2) are utilized by the microprocessor to determine the charge, q, on the particle (pulse amplitude) and its velocity, v (by time of flight). The third sensing grid, S(3), is kept at about 20 KV negative so that the dust particle will now be decelerated in passing from S(2) (zero potential) to S(3). S(3) is capacitively coupled to its CSP and the pulse from S(3) is utilized by the microprocessor to determine the particle's energy, E, and therefore its mass, m (again by time of flight) by comparison with the pulses from S(1) and S(2). The microprocessor can now precisely program the high-voltage switching network for the proper timing in the grounding of the successive deceleration grids. As determined by the microprocessor, each successive deceleration grid is grounded just after the dust particle passes, thus reducing the particle's energy by the amount q*100 KV at each stage. The microprocessor also determines at which stage the particle will fall below a certain critical energy where all remaining grids remain unswitched so that the particle will drift to the collector. The collector is kept at about 100V positive and is covered with gold foil to eliminate contamination and is removable for subsequent return to earth for detailed analysis.

MicroRNAs as Key Effectors in the p53 Network.

PubMed

Goeman, Frauke; Strano, Sabrina; Blandino, Giovanni

2017-01-01

The guardian of the genome p53 is embedded in a fine-spun network of MicroRNAs. p53 is able to activate or repress directly the transcription of MicroRNAs that are participating in the tumor-suppressive mission of p53. On the other hand, the expression of p53 is under tight control of MicroRNAs that are either targeting directly p53 or factors that are modifying its protein level or activity. Although the most important function of p53 is suggested to be transcriptional regulation, there are several nontranscriptional functions described. One of those regards the modulation of MicroRNA biogenesis. Wild-type p53 is increasing the maturation of selected MicroRNAs from the primary transcript to the precursor MiRNA by interacting with the Microprocessor complex. Furthermore, p53 is modulating the mRNA accessibility for certain MicroRNAs by association with the RISC complex and transcriptional regulation of RNA-binding proteins. In this way p53 is able to remodel the MiRNA-mRNA interaction network. As wild-type p53 is employing MicroRNAs to suppress cancer development, gain-of-function mutant p53 proteins use MicroRNAs to confer oncogenic properties like chemoresistance and the ability to drive metastasis. Like its wild-type counterpart mutant p53 is able to regulate MicroRNAs transcriptionally and posttranscriptionally. Mutant p53 affects the MiRNA processing at two cleavage steps through interfering with the Microprocessor complex and by downregulating Dicer and KSRP, a modulator of MiRNA biogenesis. Thus, MicroRNAs are essential components in the p53 pathway, contributing substantially to combat or enhance tumor development depending on the wild-type or mutant p53 context. © 2017 Elsevier Inc. All rights reserved.

NASA Tech Briefs, February 2006

NASA Technical Reports Server (NTRS)

2006-01-01

Topics discussed include: Nearly Direct Measurement of Relative Permittivity; DCS-Neural-Network Program for Aircraft Control and Testing; Dielectric Heaters for Testing Spacecraft Nuclear Reactors; Using Doppler Shifts of GPS Signals To Measure Angular Speed; Monitoring Temperatures of Tires Using Luminescent Materials; Highly Efficient Multilayer Thermoelectric Devices; Very High-Speed Digital Video Capability for In-Flight Use; MMIC DHBT Common-Base Amplifier for 172 GHz; Modular, Microprocessor-Controlled Flash Lighting System; Generic Environment for Simulating Launch Operations; Modular Aero-Propulsion System Simulation; X-Windows Socket Widget Class; Infrastructure for Rapid Development of Java GUI Programs; Processing Raman Spectra of High-Pressure Hydrogen Flames; X-Windows Information Sharing Protocol Widget Class; Simulating Humans as Integral Parts of Spacecraft Missions; Analyzing Power Supply and Demand on the ISS; Polyimides From a-BPDA and Aromatic Diamines; Making Plant-Support Structures From Waste Plant Fiber; Large Deployable Reflectarray Antenna; Periodically Discharging, Gas-Coalescing Filter; Ion Milling On Steps for Fabrication of Nanowires; Neuro-Prosthetic Implants With Adjustable Electrode Arrays; Microfluidic Devices for Studying Biomolecular Interactions; Studying Functions of All Yeast Genes Simultaneously; Polarization Phase-Compensating Coats for Metallic Mirrors; Tunable-Bandwidth Filter System; Methodology for Designing Fault-Protection Software; and Ground-Based Localization of Mars Rovers.

Microprocessor Control Design for a Low-Head Crossflow Turbine.

DTIC Science & Technology

1985-03-01

Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

Microprocessor realizations of range rate filters

NASA Technical Reports Server (NTRS)

1979-01-01

The performance of five digital range rate filters is evaluated. A range rate filter receives an input of range data from a radar unit and produces an output of smoothed range data and its estimated derivative range rate. The filters are compared through simulation on an IBM 370. Two of the filter designs are implemented on a 6800 microprocessor-based system. Comparisons are made on the bases of noise variance reduction ratios and convergence times of the filters in response to simulated range signals.

Frequency Dependence of Single-Event Upset in Highly Advanced PowerPC Microprocessors

NASA Technical Reports Server (NTRS)

Irom, Farokh; Farmanesh, Farhad; White, Mark; Kouba, Coy K.

2006-01-01

Single-event upset effects from heavy ions were measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes at three frequencies of 500, 1066 and 1600 MHz. Frequency dependence of single-event upsets is discussed. The results of our studies suggest the single-event upset in registers and D-Cache tend to increase with frequency. This might have important implications for the overall single-event upset trend as technology moves toward higher frequencies.

Microprocessor control system for 200-kilowatt Mod-OA wind turbines

NASA Technical Reports Server (NTRS)

Nyland, T. W.; Birchenough, A. G.

1982-01-01

The microprocessor system and program used to control the operation of the 200-kW Mod-OA wind turbines is described. The system is programmed to begin startup and shutdown sequences automatically and to control yaw motion. Rotor speed and power output are controlled with integral and proportional control of the blade pitch angle. Included in the report are a description of the hardware and a discussion of the software programming technique. A listing of the PL/M software program is given.