A miniature on-chip multi-functional ECG signal processor with 30 µW ultra-low power consumption.

PubMed

Liu, Xin; Zheng, Yuan Jin; Phyu, Myint Wai; Zhao, Bin; Je, Minkyu; Yuan, Xiao Jun

2010-01-01

In this paper, a miniature low-power Electrocardiogram (ECG) signal processing application specific integrated circuit (ASIC) chip is proposed. This chip provides multiple critical functions for ECG analysis using a systematic wavelet transform algorithm and a novel SRAM-based ASIC architecture, while achieves low cost and high performance. Using 0.18 µm CMOS technology and 1 V power supply, this ASIC chip consumes only 29 µW and occupies an area of 3 mm(2). This on-chip ECG processor is highly suitable for reliable real-time cardiac status monitoring applications.

Parallel processing data network of master and slave transputers controlled by a serial control network

DOEpatents

Crosetto, D.B.

1996-12-31

The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor to a plurality of slave processors to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor`s status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer, a digital signal processor, a parallel transfer controller, and two three-port memory devices. A communication switch within each node connects it to a fast parallel hardware channel through which all high density data arrives or leaves the node. 6 figs.

A hybrid optic-fiber sensor network with the function of self-diagnosis and self-healing

NASA Astrophysics Data System (ADS)

Xu, Shibo; Liu, Tiegen; Ge, Chunfeng; Chen, Cheng; Zhang, Hongxia

2014-11-01

We develop a hybrid wavelength division multiplexing optical fiber network with distributed fiber-optic sensors and quasi-distributed FBG sensor arrays which detect vibrations, temperatures and strains at the same time. The network has the ability to locate the failure sites automatically designated as self-diagnosis and make protective switching to reestablish sensing service designated as self-healing by cooperative work of software and hardware. The processes above are accomplished by master-slave processors with the help of optical and wireless telemetry signals. All the sensing and optical telemetry signals transmit in the same fiber either working fiber or backup fiber. We take wavelength 1450nm as downstream signal and wavelength 1350nm as upstream signal to control the network in normal circumstances, both signals are sent by a light emitting node of the corresponding processor. There is also a continuous laser wavelength 1310nm sent by each node and received by next node on both working and backup fibers to monitor their healthy states, but it does not carry any message like telemetry signals do. When fibers of two sensor units are completely damaged, the master processor will lose the communication with the node between the damaged ones.However we install RF module in each node to solve the possible problem. Finally, the whole network state is transmitted to host computer by master processor. Operator could know and control the network by human-machine interface if needed.

Electric Fuel Pump Condition Monitor System Using Electricalsignature Analysis

DOEpatents

Haynes, Howard D [Knoxville, TN; Cox, Daryl F [Knoxville, TN; Welch, Donald E [Oak Ridge, TN

2005-09-13

A pump diagnostic system and method comprising current sensing probes clamped on electrical motor leads of a pump for sensing only current signals on incoming motor power, a signal processor having a means for buffering and anti-aliasing current signals into a pump motor current signal, and a computer having a means for analyzing, displaying, and reporting motor current signatures from the motor current signal to determine pump health using integrated motor and pump diagnostic parameters.

Electrochemical sensing using voltage-current time differential

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2017-02-28

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Architecture design of the multi-functional wavelet-based ECG microprocessor for realtime detection of abnormal cardiac events.

PubMed

Cheng, Li-Fang; Chen, Tung-Chien; Chen, Liang-Gee

2012-01-01

Most of the abnormal cardiac events such as myocardial ischemia, acute myocardial infarction (AMI) and fatal arrhythmia can be diagnosed through continuous electrocardiogram (ECG) analysis. According to recent clinical research, early detection and alarming of such cardiac events can reduce the time delay to the hospital, and the clinical outcomes of these individuals can be greatly improved. Therefore, it would be helpful if there is a long-term ECG monitoring system with the ability to identify abnormal cardiac events and provide realtime warning for the users. The combination of the wireless body area sensor network (BASN) and the on-sensor ECG processor is a possible solution for this application. In this paper, we aim to design and implement a digital signal processor that is suitable for continuous ECG monitoring and alarming based on the continuous wavelet transform (CWT) through the proposed architectures--using both programmable RISC processor and application specific integrated circuits (ASIC) for performance optimization. According to the implementation results, the power consumption of the proposed processor integrated with an ASIC for CWT computation is only 79.4 mW. Compared with the single-RISC processor, about 91.6% of the power reduction is achieved.

Electrochemical sensing using comparison of voltage-current time differential values during waveform generation and detection

DOE Office of Scientific and Technical Information (OSTI.GOV)

Woo, Leta Yar-Li; Glass, Robert Scott; Fitzpatrick, Joseph Jay

2018-01-02

A device for signal processing. The device includes a signal generator, a signal detector, and a processor. The signal generator generates an original waveform. The signal detector detects an affected waveform. The processor is coupled to the signal detector. The processor receives the affected waveform from the signal detector. The processor also compares at least one portion of the affected waveform with the original waveform. The processor also determines a difference between the affected waveform and the original waveform. The processor also determines a value corresponding to a unique portion of the determined difference between the original and affected waveforms.more » The processor also outputs the determined value.« less

Acoustically based fetal heart rate monitor

NASA Technical Reports Server (NTRS)

Baker, Donald A.; Zuckerwar, Allan J.

1991-01-01

The acoustically based fetal heart rate monitor permits an expectant mother to perform the fetal Non-Stress Test in her home. The potential market would include the one million U.S. pregnancies per year requiring this type of prenatal surveillance. The monitor uses polyvinylidene fluoride (PVF2) piezoelectric polymer film for the acoustic sensors, which are mounted in a seven-element array on a cummerbund. Evaluation of the sensor ouput signals utilizes a digital signal processor, which performs a linear prediction routine in real time. Clinical tests reveal that the acoustically based monitor provides Non-Stress Test records which are comparable to those obtained with a commercial ultrasonic transducer.

Parallel processing data network of master and slave transputers controlled by a serial control network

DOEpatents

Crosetto, Dario B.

1996-01-01

The present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

System for detecting special nuclear materials

DOEpatents

Jandel, Marian; Rusev, Gencho Yordanov; Taddeucci, Terry Nicholas

2015-07-14

The present disclosure includes a radiological material detector having a convertor material that emits one or more photons in response to a capture of a neutron emitted by a radiological material; a photon detector arranged around the convertor material and that produces an electrical signal in response to a receipt of a photon; and a processor connected to the photon detector, the processor configured to determine the presence of a radiological material in response to a predetermined signature of the electrical signal produced at the photon detector. One or more detectors described herein can be integrated into a detection system that is suited for use in port monitoring, treaty compliance, and radiological material management activities.

Probe for optically monitoring progress of in-situ vitrification of soil

DOEpatents

Timmerman, Craig L.; Oma, Kenton H.; Davis, Karl C.

1988-01-01

A detector system for sensing the progress of an ISV process along an expected path comprises multiple sensors each having an input port. The input ports are distributed along the expected path of the ISV process between a starting location and an expected ending location. Each sensor generates an electrical signal representative of the temperature in the vicinity of its input port. A signal processor is coupled to the sensors to receive an electrical signal generated by a sensor, and generate a signal which is encoded with information which identifies the sensor and whether the ISV process has reached the sensor's input port. A transmitter propagates the encoded signal. The signal processor and the transmitter are below ground at a location beyond the expected ending location of the ISV process in the direction from the starting location to the expected ending location. A signal receiver and a decoder are located above ground for receiving the encoded signal propagated by the transmitter, decoding the encoded signal and providing a human-perceptible indication of the progress of the ISV process.

Probe for optically monitoring progress of in-situ vitrification of soil

DOEpatents

Timmerman, C.L.; Oma, K.H.; Davis, K.C.

1988-08-09

A detector system for sensing the progress of an ISV process along an expected path comprises multiple sensors each having an input port. The input ports are distributed along the expected path of the ISV process between a starting location and an expected ending location. Each sensor generates an electrical signal representative of the temperature in the vicinity of its input port. A signal processor is coupled to the sensors to receive an electrical signal generated by a sensor, and generate a signal which is encoded with information which identifies the sensor and whether the ISV process has reached the sensor's input port. A transmitter propagates the encoded signal. The signal processor and the transmitter are below ground at a location beyond the expected ending location of the ISV process in the direction from the starting location to the expected ending location. A signal receiver and a decoder are located above ground for receiving the encoded signal propagated by the transmitter, decoding the encoded signal and providing a human-perceptible indication of the progress of the ISV process. 7 figs.

Database for LDV Signal Processor Performance Analysis

NASA Technical Reports Server (NTRS)

Baker, Glenn D.; Murphy, R. Jay; Meyers, James F.

1989-01-01

A comparative and quantitative analysis of various laser velocimeter signal processors is difficult because standards for characterizing signal bursts have not been established. This leaves the researcher to select a signal processor based only on manufacturers' claims without the benefit of direct comparison. The present paper proposes the use of a database of digitized signal bursts obtained from a laser velocimeter under various configurations as a method for directly comparing signal processors.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

A computer controlled signal preprocessor for laser fringe anemometer applications

NASA Technical Reports Server (NTRS)

Oberle, Lawrence G.

1987-01-01

The operation of most commercially available laser fringe anemometer (LFA) counter-processors assumes that adjustments are made to the signal processing independent of the computer used for reducing the data acquired. Not only does the researcher desire a record of these parameters attached to the data acquired, but changes in flow conditions generally require that these settings be changed to improve data quality. Because of this limitation, on-line modification of the data acquisition parameters can be difficult and time consuming. A computer-controlled signal preprocessor has been developed which makes possible this optimization of the photomultiplier signal as a normal part of the data acquisition process. It allows computer control of the filter selection, signal gain, and photo-multiplier voltage. The raw signal from the photomultiplier tube is input to the preprocessor which, under the control of a digital computer, filters the signal and amplifies it to an acceptable level. The counter-processor used at Lewis Research Center generates the particle interarrival times, as well as the time-of-flight of the particle through the probe volume. The signal preprocessor allows computer control of the acquisition of these data.Through the preprocessor, the computer also can control the hand shaking signals for the interface between itself and the counter-processor. Finally, the signal preprocessor splits the pedestal from the signal before filtering, and monitors the photo-multiplier dc current, sends a signal proportional to this current to the computer through an analog to digital converter, and provides an alarm if the current exceeds a predefined maximum. Complete drawings and explanations are provided in the text as well as a sample interface program for use with the data acquisition software.

Integrated Advanced Microwave Sounding Unit-A(AMSU-A). Engineering Test Report: METSAT A1 Signal Processor, (P/N 1331670-2, S /N F05)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the AI METSAT Signal Processor Assembly P/N 1331670-2, S/N F05. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N 1331670-2, S/N F03)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F03. This assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Shuttle orbiter S-band payload communications equipment design evaluation

NASA Technical Reports Server (NTRS)

Springett, J. C.; Maronde, R. G.

1979-01-01

The analysis of the design, and the performance assessment of the Orbiter S-band communication equipment are reported. The equipment considered include: network transponder, network signal processor, FM transmitter, FM signal processor, payload interrogator, and payload signal processor.

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N: 1331670-2, S/N: F04)

NASA Technical Reports Server (NTRS)

Lund, D.

1998-01-01

This report presents a description of the tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

Development and Testing of a Portable Vocal Accumulator

ERIC Educational Resources Information Center

Cheyne, Harold A.; Hanson, Helen M.; Genereux, Ronald P.; Stevens, Kenneth N.; Hillman, Robert E.

2003-01-01

This research note describes the design and testing of a device for unobtrusive, long-term ambulatory monitoring of voice use, named the Portable Vocal Accumulator (PVA). The PVA contains a digital signal processor for analyzing input from a neck-placed miniature accelerometer. During its development, accelerometer recordings were obtained from 99…

Night-day-night sleep-wakefulness monitoring by ambulatory integrated circuit memories.

PubMed

Yamamoto, M; Nakao, M; Katayama, N; Waku, M; Suzuki, K; Irokawa, K; Abe, M; Ueno, T

1999-04-01

A medium-sized portable digital recorder with fully integrated circuit (IC) memories for sleep monitoring has been developed. It has five amplifiers for EEG, EMG, EOG, ECG, and a signal of body acceleration or respiration sound, four event markers, an 8 ch A/D converter, a digital signal processor (DSP), 192 Mbytes IC flash memories, and batteries. The whole system weighs 1200 g including batteries and is put into a small bag worn on the subject's waist or carried in their hand. The sampling rate for each input channel is programmable through the DSP. This apparatus is valuable for continuously monitoring the states of sleep-wakefulness over 24 h, making a night-day-night recording possible in a hospital, home, or car.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Astrophysics Data System (ADS)

Carreno, Victor A.; Angellatta, Rob K.

1991-09-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

A case study for the real-time experimental evaluation of the VIPER microprocessor

NASA Technical Reports Server (NTRS)

Carreno, Victor A.; Angellatta, Rob K.

1991-01-01

An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

ISFET-based sensor signal processor chip design for environment monitoring applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Wang, Ming-Ga

2004-12-01

In recent years Ion-Sensitive Field Effect Transistor (ISFET) based transducers create valuable applications in physiological data acquisition and environment monitoring. This paper presents a mixed-mode ASIC design for potentiometric ISFET-based bio-chemical sensor applications including H+ sensing and hand-held pH meter. For battery power consideration, the proposed system consists of low voltage (3V) analog front-end readout circuits and digital processor has been developed and fabricated in a 0.5mm double-poly double-metal CMOS technology. To assure that the correct pH value can be measured, the two-point calibration circuitry based on the response of standard pH4 and pH7 buffer solution has been implemented by using algorithmic state machine hardware algorithms. The measurement accuracy of the chip is 10 bits and the measured range between pH 2 to pH 12 compared to ideal values is within the accuracy of 0.1pH. For homeland environmental applications, the system provide rapid, easy to use, and cost-effective on-site testing on the quality of water, such as drinking water, ground water and river water. The processor has a potential usage in battery-operated and portable devices in environmental monitoring applications compared to commercial hand-held pH meter.

Automobile Crash Sensor Signal Processor

DOT National Transportation Integrated Search

1973-11-01

The crash sensor signal processor described interfaces between an automobile-installed doppler radar and an air bag activating solenoid or equivalent electromechanical device. The processor utilizes both digital and analog techniques to produce an ou...

JPRS Report, Science & Technology, Europe.

DTIC Science & Technology

1991-04-30

processor in collaboration with Intel . The processor , christened Touchstone, will be used as the core of a parallel computer with 2,000 processors . One of...ELECTRONIQUE HEBDO in French 24 Jan 91 pp 14-15 [Article by Claire Remy: "Everything Set for Neural Signal Processors " first paragraph is ELECTRONIQUE...paving the way for neural signal processors in so doing. The principal advantage of this specific circuit over a neuromimetic software program is

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Semiconductor-laser Fourier processors of electric signals

NASA Astrophysics Data System (ADS)

Blok, A. S.; Bukhenskii, A. F.; Krupitskii, É. I.; Morozov, S. V.; Pelevin, V. Yu; Sergeenko, T. N.; Yakovlev, V. I.

1995-10-01

An investigation is reported of acousto-optical and fibre-optic Fourier processors of electric signals, based on semiconductor lasers. A description is given of practical acousto-optical processors with an analysis band 120 MHz wide, a resolution of 200 kHz, and 7 cm × 8 cm × 18 cm dimensions. Fibre-optic Fourier processors are considered: they represent a new class of devices which are promising for the processing of gigahertz signals.

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

Gamma thermometer based reactor core liquid level detector

DOEpatents

Burns, Thomas J.

1983-01-01

A system is provided which employs a modified gamma thermometer for determining the liquid coolant level within a nuclear reactor core. The gamma thermometer which normally is employed to monitor local core heat generation rate (reactor power), is modified by thermocouple junctions and leads to obtain an unambiguous indication of the presence or absence of coolant liquid at the gamma thermometer location. A signal processor generates a signal based on the thermometer surface heat transfer coefficient by comparing the signals from the thermocouples at the thermometer location. The generated signal is a direct indication of loss of coolant due to the change in surface heat transfer when coolant liquid drops below the thermometer location. The loss of coolant indication is independent of reactor power at the thermometer location. Further, the same thermometer may still be used for the normal power monitoring function.

Stanford Hardware Development Program

NASA Technical Reports Server (NTRS)

Peterson, A.; Linscott, I.; Burr, J.

1986-01-01

Architectures for high performance, digital signal processing, particularly for high resolution, wide band spectrum analysis were developed. These developments are intended to provide instrumentation for NASA's Search for Extraterrestrial Intelligence (SETI) program. The real time signal processing is both formal and experimental. The efficient organization and optimal scheduling of signal processing algorithms were investigated. The work is complemented by efforts in processor architecture design and implementation. A high resolution, multichannel spectrometer that incorporates special purpose microcoded signal processors is being tested. A general purpose signal processor for the data from the multichannel spectrometer was designed to function as the processing element in a highly concurrent machine. The processor performance required for the spectrometer is in the range of 1000 to 10,000 million instructions per second (MIPS). Multiple node processor configurations, where each node performs at 100 MIPS, are sought. The nodes are microprogrammable and are interconnected through a network with high bandwidth for neighboring nodes, and medium bandwidth for nodes at larger distance. The implementation of both the current mutlichannel spectrometer and the signal processor as Very Large Scale Integration CMOS chip sets was commenced.

Method and system for selecting data sampling phase for self timed interface logic

DOEpatents

Hoke, Joseph Michael; Ferraiolo, Frank D.; Lo, Tin-Chee; Yarolin, John Michael

2005-01-04

An exemplary embodiment of the present invention is a method for transmitting data among processors over a plurality of parallel data lines and a clock signal line. A receiver processor receives both data and a clock signal from a sender processor. At the receiver processor a bit of the data is phased aligned with the transmitted clock signal. The phase aligning includes selecting a data phase from a plurality of data phases in a delay chain and then adjusting the selected data phase to compensate for a round-off error. Additional embodiments include a system and storage medium for transmitting data among processors over a plurality of parallel data lines and a clock signal line.

Phase coherence adaptive processor for automatic signal detection and identification

NASA Astrophysics Data System (ADS)

Wagstaff, Ronald A.

2006-05-01

A continuously adapting acoustic signal processor with an automatic detection/decision aid is presented. Its purpose is to preserve the signals of tactical interest, and filter out other signals and noise. It utilizes single sensor or beamformed spectral data and transforms the signal and noise phase angles into "aligned phase angles" (APA). The APA increase the phase temporal coherence of signals and leave the noise incoherent. Coherence thresholds are set, which are representative of the type of source "threat vehicle" and the geographic area or volume in which it is operating. These thresholds separate signals, based on the "quality" of their APA coherence. An example is presented in which signals from a submerged source in the ocean are preserved, while clutter signals from ships and noise are entirely eliminated. Furthermore, the "signals of interest" were identified by the processor's automatic detection aid. Similar performance is expected for air and ground vehicles. The processor's equations are formulated in such a manner that they can be tuned to eliminate noise and exploit signal, based on the "quality" of their APA temporal coherence. The mathematical formulation for this processor is presented, including the method by which the processor continuously self-adapts. Results show nearly complete elimination of noise, with only the selected category of signals remaining, and accompanying enhancements in spectral and spatial resolution. In most cases, the concept of signal-to-noise ratio looses significance, and "adaptive automated /decision aid" is more relevant.

Design and performance of a high resolution, low latency stripline beam position monitor system

NASA Astrophysics Data System (ADS)

Apsimon, R. J.; Bett, D. R.; Blaskovic Kraljevic, N.; Burrows, P. N.; Christian, G. B.; Clarke, C. I.; Constance, B. D.; Dabiri Khah, H.; Davis, M. R.; Perry, C.; Resta López, J.; Swinson, C. J.

2015-03-01

A high-resolution, low-latency beam position monitor (BPM) system has been developed for use in particle accelerators and beam lines that operate with trains of particle bunches with bunch separations as low as several tens of nanoseconds, such as future linear electron-positron colliders and free-electron lasers. The system was tested with electron beams in the extraction line of the Accelerator Test Facility at the High Energy Accelerator Research Organization (KEK) in Japan. It consists of three stripline BPMs instrumented with analogue signal-processing electronics and a custom digitizer for logging the data. The design of the analogue processor units is presented in detail, along with measurements of the system performance. The processor latency is 15.6 ±0.1 ns . A single-pass beam position resolution of 291 ±10 nm has been achieved, using a beam with a bunch charge of approximately 1 nC.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Fault detection and bypass in a sequence information signal processor

NASA Technical Reports Server (NTRS)

Peterson, John C. (Inventor); Chow, Edward T. (Inventor)

1992-01-01

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

Signal generation and mixing electronics for frequency-domain lifetime and spectral fluorometry

NASA Technical Reports Server (NTRS)

Cruce, Tommy Clay (Inventor); Hallidy, William H. (Inventor); Chin, Robert C. (Inventor)

2007-01-01

The present invention additionally comprises a method and apparatus for generating and mixing signals for frequency-domain lifetime and spectral fluorometry. The present invention comprises a plurality of signal generators that generate a plurality of signals where the signal generators modulate the amplitude and/or the frequency of the signals. The present invention uses one of these signals to drive an excitation signal that the present invention then directs and transmits at a target mixture, which absorbs the energy from the excitation signal. The property of fluorescence causes the target mixture to emit an emitted signal that the present invention detects with a signal detector. The present invention uses a plurality of mixers to produce a processor reference signal and a data signal. The present invention then uses a processor to compare the processor reference signal with the data signal by analyzing the differences in the phase and the differences in the amplitude between the two signals. The processor then extracts the fluorescence lifetime and fluorescence spectrum of the emitted signal from the phase and amplitude information using a chemometric analysis.

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

NASA Astrophysics Data System (ADS)

Xie, Yiwei; Geng, Zihan; Zhuang, Leimeng; Burla, Maurizio; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Roeloffzen, Chris G. H.; Boller, Klaus-J.; Lowery, Arthur J.

2017-12-01

Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF) filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP)-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

a Continuous Health Monitoring Guided Wave Fmd System for Retrofit to Existing Offshore Oilrigs

NASA Astrophysics Data System (ADS)

Mijarez, R.; Solis, L.; Martinez, F.

2010-02-01

An automatic health monitoring guided wave flood member detection (FMD) system, for retrofit to existing offshore oilrigs is presented. The system employs a microcontroller piezoelectric (PZT) based transmitter and a receiver instrumentation package composed of a PZT 40 kHz ultrasound transducer and a digital signal processor (DSP) module connected to a PC via USB for monitoring purposes. The transmitter and receiver were attached, non-intrusively, to the external wall of a steel tube; 1 m×27 cm×2 mm. Experiments performed in the laboratory have successfully identified automatically flooded tubes.

Vital signs monitoring system

NASA Technical Reports Server (NTRS)

Steffen, Dale A. (Inventor); Sturm, Ronald E. (Inventor); Rinard, George A. (Inventor)

1981-01-01

A system is disclosed for monitoring vital physiological signs. Each of the system components utilizes a single hybrid circuit with each component having high accuracy without the necessity of repeated calibration. The system also has low power requirements, provides a digital display, and is of sufficiently small size to be incorporated into a hand-carried case for portable use. Components of the system may also provide independent outputs making the component useful, of itself, for monitoring one or more vital signs. The overall system preferably includes an ECG amplifier and cardiotachometer signal conditioner unit, an impedance pneumograph and respiration rate signal conditioner unit, a heart/breath rate processor unit, a temperature monitoring unit, a selector switch, a clock unit, and an LCD driver unit and associated LCDs, with the system being capable of being expanded as needed or desired, such as, for example, by addition of a systolic/diastolic blood pressure unit.

A universal computer control system for motors

NASA Technical Reports Server (NTRS)

Szakaly, Zoltan F. (Inventor)

1991-01-01

A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor.

Simulink/PARS Integration Support

DOE Office of Scientific and Technical Information (OSTI.GOV)

Vacaliuc, B.; Nakhaee, N.

2013-12-18

The state of the art for signal processor hardware has far out-paced the development tools for placing applications on that hardware. In addition, signal processors are available in a variety of architectures, each uniquely capable of handling specific types of signal processing efficiently. With these processors becoming smaller and demanding less power, it has become possible to group multiple processors, a heterogeneous set of processors, into single systems. Different portions of the desired problem set can be assigned to different processor types as appropriate. As software development tools do not keep pace with these processors, especially when multiple processors ofmore » different types are used, a method is needed to enable software code portability among multiple processors and multiple types of processors along with their respective software environments. Sundance DSP, Inc. has developed a software toolkit called “PARS”, whose objective is to provide a framework that uses suites of tools provided by different vendors, along with modeling tools and a real time operating system, to build an application that spans different processor types. The software language used to express the behavior of the system is a very high level modeling language, “Simulink”, a MathWorks product. ORNL has used this toolkit to effectively implement several deliverables. This CRADA describes this collaboration between ORNL and Sundance DSP, Inc.« less

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report: METSAT A2 Signal Processor (P/N 1331120-2, S/N F03) S/N 107

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F03. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

Integrated Advanced Microwave Sounding Unit-A (AMSU-A): Engineering Test Report, METSAT A2 Signal Processor (P/N 1331120-2, S/N F04) S/N 108

NASA Technical Reports Server (NTRS)

1998-01-01

This report presents a description of the tests performed, and the test data, for the A2 METSAT Signal Processor Assembly PN: 1331120-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure."

Circuitry, systems and methods for detecting magnetic fields

DOEpatents

Kotter, Dale K [Shelley, ID; Spencer, David F [Idaho Falls, ID; Roybal, Lyle G [Idaho Falls, ID; Rohrbaugh, David T [Idaho Falls, ID

2010-09-14

Circuitry for detecting magnetic fields includes a first magnetoresistive sensor and a second magnetoresistive sensor configured to form a gradiometer. The circuitry includes a digital signal processor and a first feedback loop coupled between the first magnetoresistive sensor and the digital signal processor. A second feedback loop which is discrete from the first feedback loop is coupled between the second magnetoresistive sensor and the digital signal processor.

High-performance ultra-low power VLSI analog processor for data compression

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1996-01-01

An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.

Global synchronization of parallel processors using clock pulse width modulation

DOEpatents

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

A microcomputer based frequency-domain processor for laser Doppler anemometry

NASA Technical Reports Server (NTRS)

Horne, W. Clifton; Adair, Desmond

1988-01-01

A prototype multi-channel laser Doppler anemometry (LDA) processor was assembled using a wideband transient recorder and a microcomputer with an array processor for fast Fourier transform (FFT) computations. The prototype instrument was used to acquire, process, and record signals from a three-component wind tunnel LDA system subject to various conditions of noise and flow turbulence. The recorded data was used to evaluate the effectiveness of burst acceptance criteria, processing algorithms, and selection of processing parameters such as record length. The recorded signals were also used to obtain comparative estimates of signal-to-noise ratio between time-domain and frequency-domain signal detection schemes. These comparisons show that the FFT processing scheme allows accurate processing of signals for which the signal-to-noise ratio is 10 to 15 dB less than is practical using counter processors.

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Huang Meizhen; Shi Longzhao; Wang Yuxing

2006-08-15

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13x13 mm{sup 2}, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range ofmore » a 13x13 mm{sup 2} active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was {+-}20 {mu}m. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.« less

Development of a new signal processor for tetralateral position sensitive detector based on single-chip microcomputer

NASA Astrophysics Data System (ADS)

Huang, Mei-Zhen; Shi, Long-Zhao; Wang, Yu-Xing; Ni, Yi; Li, Zhen-Qing; Ding, Hai-Feng

2006-08-01

An inherently nonlinear relation between the output current of the tetralateral position sensitive detector (PSD) and the position of the incident light spot has been found theoretically. Based on single-chip microcomputer and the theoretical relation between output current and position, a new signal processor capable of correcting nonlinearity and reducing position measurement deviation of tetralateral PSD was developed. A tetralateral PSD (S1200, 13×13mm2, Hamamatsu Photonics K.K.) was measured with the new signal processor, a linear relation between the output position of the PSD, and the incident position of the light spot was obtained. In the 60% range of a 13×13mm2 active area, the position nonlinearity (rms) was 0.15% and the position measurement deviation (rms) was ±20μm. Compared with traditional analog signal processor, the new signal processor is of better compatibility, lower cost, higher precision, and easier to be interfaced.

Experimental testing of the noise-canceling processor.

PubMed

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

New Modular Ultrasonic Signal Processing Building Blocks for Real-Time Data Acquisition and Post Processing

NASA Astrophysics Data System (ADS)

Weber, Walter H.; Mair, H. Douglas; Jansen, Dion

2003-03-01

A suite of basic signal processors has been developed. These basic building blocks can be cascaded together to form more complex processors without the need for programming. The data structures between each of the processors are handled automatically. This allows a processor built for one purpose to be applied to any type of data such as images, waveform arrays and single values. The processors are part of Winspect Data Acquisition software. The new processors are fast enough to work on A-scan signals live while scanning. Their primary use is to extract features, reduce noise or to calculate material properties. The cascaded processors work equally well on live A-scan displays, live gated data or as a post-processing engine on saved data. Researchers are able to call their own MATLAB or C-code from anywhere within the processor structure. A built-in formula node processor that uses a simple algebraic editor may make external user programs unnecessary. This paper also discusses the problems associated with ad hoc software development and how graphical programming languages can tie up researchers writing software rather than designing experiments.

Real Time Calibration Method for Signal Conditioning Amplifiers

NASA Technical Reports Server (NTRS)

Medelius, Pedro J. (Inventor); Mata, Carlos T. (Inventor); Eckhoff, Anthony (Inventor); Perotti, Jose (Inventor); Lucena, Angel (Inventor)

2004-01-01

A signal conditioning amplifier receives an input signal from an input such as a transducer. The signal is amplified and processed through an analog to digital converter and sent to a processor. The processor estimates the input signal provided by the transducer to the amplifier via a multiplexer. The estimated input signal is provided as a calibration voltage to the amplifier immediately following the receipt of the amplified input signal. The calibration voltage is amplified by the amplifier and provided to the processor as an amplified calibration voltage. The amplified calibration voltage is compared to the amplified input signal, and if a significant error exists, the gain and/or offset of the amplifier may be adjusted as necessary.

Interactive Digital Signal Processor

NASA Technical Reports Server (NTRS)

Mish, W. H.

1985-01-01

Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.

Interferometric angle monitor

NASA Technical Reports Server (NTRS)

Minott, P. O. (Inventor)

1983-01-01

Two mutually coherent light beams formed from a single monochromatic light source were directed to a reflecting surface of a rotatable object. They were reflected into an imaging optical lens having a focal plane optically at infinity. A series of interference fringes were formed in the focal plane which were translated linearly in response to angular rotation of the object. Photodetectors were located adjacent the focal plane to detect the fringe translation and output a signal in response to the translation. The signal was fed to a signal processor which was adapted to count the number of fringes detected and develop a measure of the angular rotation and direction of the object.

Hardware multiplier processor

DOEpatents

Pierce, Paul E.

1986-01-01

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Hardware multiplier processor

DOEpatents

Pierce, P.E.

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

The mathematical theory of signal processing and compression-designs

NASA Astrophysics Data System (ADS)

Feria, Erlan H.

2006-05-01

The mathematical theory of signal processing, named processor coding, will be shown to inherently arise as the computational time dual of Shannon's mathematical theory of communication which is also known as source coding. Source coding is concerned with signal source memory space compression while processor coding deals with signal processor computational time compression. Their combination is named compression-designs and referred as Conde in short. A compelling and pedagogically appealing diagram will be discussed highlighting Conde's remarkable successful application to real-world knowledge-aided (KA) airborne moving target indicator (AMTI) radar.

The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

NASA Astrophysics Data System (ADS)

Åsman, B.; Achenbach, R.; Allbrooke, B. M. M.; Anders, G.; Andrei, V.; Büscher, V.; Bansil, H. S.; Barnett, B. M.; Bauss, B.; Bendtz, K.; Bohm, C.; Bracinik, J.; Brawn, I. P.; Brock, R.; Buttinger, W.; Caputo, R.; Caughron, S.; Cerrito, L.; Charlton, D. G.; Childers, J. T.; Curtis, C. J.; Daniells, A. C.; Davis, A. O.; Davygora, Y.; Dorn, M.; Eckweiler, S.; Edmunds, D.; Edwards, J. P.; Eisenhandler, E.; Ellis, K.; Ermoline, Y.; Föhlisch, F.; Faulkner, P. J. W.; Fedorko, W.; Fleckner, J.; French, S. T.; Gee, C. N. P.; Gillman, A. R.; Goeringer, C.; Hülsing, T.; Hadley, D. R.; Hanke, P.; Hauser, R.; Heim, S.; Hellman, S.; Hickling, R. S.; Hidvégi, A.; Hillier, S. J.; Hofmann, J. I.; Hristova, I.; Ji, W.; Johansen, M.; Keller, M.; Khomich, A.; Kluge, E.-E.; Koll, J.; Laier, H.; Landon, M. P. J.; Lang, V. S.; Laurens, P.; Lepold, F.; Lilley, J. N.; Linnemann, J. T.; Müller, F.; Müller, T.; Mahboubi, K.; Martin, T. A.; Mass, A.; Meier, K.; Meyer, C.; Middleton, R. P.; Moa, T.; Moritz, S.; Morris, J. D.; Mudd, R. D.; Narayan, R.; zur Nedden, M.; Neusiedl, A.; Newman, P. R.; Nikiforov, A.; Ohm, C. C.; Perera, V. J. O.; Pfeiffer, U.; Plucinski, P.; Poddar, S.; Prieur, D. P. F.; Qian, W.; Rieck, P.; Rizvi, E.; Sankey, D. P. C.; Schäfer, U.; Scharf, V.; Schmitt, K.; Schröder, C.; Schultz-Coulon, H.-C.; Schumacher, C.; Schwienhorst, R.; Silverstein, S. B.; Simioni, E.; Snidero, G.; Staley, R. J.; Stamen, R.; Stock, P.; Stockton, M. C.; Tan, C. L. A.; Tapprogge, S.; Thomas, J. P.; Thompson, P. D.; Thomson, M.; True, P.; Watkins, P. M.; Watson, A. T.; Watson, M. F.; Weber, P.; Wessels, M.; Wiglesworth, C.; Williams, S. L.

2012-12-01

The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

Electro-optic voltage sensor with Multiple Beam Splitting

DOEpatents

Woods, Gregory K.; Renak, Todd W.; Crawford, Thomas M.; Davidson, James R.

2000-01-01

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages without use of the dedicated voltage dividing hardware. The invention achieves voltage measurement without significant error contributions from neighboring conductors or environmental perturbations. The invention employs a transmitter, a sensor, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor. Within the sensor the beam undergoes the Pockels electro-optic effect. The electro-optic effect produces a modulation of the beam's polarization, which is in turn converted to a pair of independent conversely-amplitude-modulated signals, from which the voltage of the E-field is determined by the signal processor. The use of converse AM signals enables the signal processor to better distinguish signal from noise. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Ultrasonic imaging system for in-process fabric defect detection

DOEpatents

Sheen, Shuh-Haw; Chien, Hual-Te; Lawrence, William P.; Raptis, Apostolos C.

1997-01-01

An ultrasonic method and system are provided for monitoring a fabric to identify a defect. A plurality of ultrasonic transmitters generate ultrasonic waves relative to the fabric. An ultrasonic receiver means responsive to the generated ultrasonic waves from the transmitters receives ultrasonic waves coupled through the fabric and generates a signal. An integrated peak value of the generated signal is applied to a digital signal processor and is digitized. The digitized signal is processed to identify a defect in the fabric. The digitized signal processing includes a median value filtering step to filter out high frequency noise. Then a mean value and standard deviation of the median value filtered signal is calculated. The calculated mean value and standard deviation are compared with predetermined threshold values to identify a defect in the fabric.

Stroboscope Controller for Imaging Helicopter Rotors

NASA Technical Reports Server (NTRS)

Jensen, Scott; Marmie, John; Mai, Nghia

2004-01-01

A versatile electronic timing-and-control unit, denoted a rotorcraft strobe controller, has been developed for use in controlling stroboscopes, lasers, video cameras, and other instruments for capturing still images of rotating machine parts especially helicopter rotors. This unit is designed to be compatible with a variety of sources of input shaftangle or timing signals and to be capable of generating a variety of output signals suitable for triggering instruments characterized by different input-signal specifications. It is also designed to be flexible and reconfigurable in that it can be modified and updated through changes in its control software, without need to change its hardware. Figure 1 is a block diagram of the rotorcraft strobe controller. The control processor is a high-density complementary metal oxide semiconductor, singlechip 8-bit microcontroller. It is connected to a 32K x 8 nonvolatile static random-access memory (RAM) module. Also connected to the control processor is a 32K 8 electrically programmable read-only-memory (EPROM) module, which is used to store the control software. Digital logic support circuitry is implemented in a field-programmable gate array (FPGA). A 240 x 128-dot, 40- character 16-line liquid-crystal display (LCD) module serves as a graphical user interface; the user provides input through a 16-key keypad mounted next to the LCD. A 12-bit digital-to-analog converter (DAC) generates a 0-to-10-V ramp output signal used as part of a rotor-blade monitoring system, while the control processor generates all the appropriate strobing signals. Optocouplers are used to isolate all input and output digital signals, and optoisolators are used to isolate all analog signals. The unit is designed to fit inside a 19-in. (.48-cm) rack-mount enclosure. Electronic components are mounted on a custom printed-circuit board (see Figure 2). Two power-conversion modules on the printedcircuit board convert AC power to +5 VDC and 15 VDC, respectively.

Verification of a Proposed Clinical Electroacoustic Test Protocol for Personal Digital Modulation Receivers Coupled to Cochlear Implant Sound Processors.

PubMed

Nair, Erika L; Sousa, Rhonda; Wannagot, Shannon

Guidelines established by the AAA currently recommend behavioral testing when fitting frequency modulated (FM) systems to individuals with cochlear implants (CIs). A protocol for completing electroacoustic measures has not yet been validated for personal FM systems or digital modulation (DM) systems coupled to CI sound processors. In response, some professionals have used or altered the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting FM systems to CI sound processors. More recently steps were outlined in a proposed protocol. The purpose of this research is to review and compare the electroacoustic test measures outlined in a 2013 article by Schafer and colleagues in the Journal of the American Academy of Audiology titled "A Proposed Electroacoustic Test Protocol for Personal FM Receivers Coupled to Cochlear Implant Sound Processors" to the AAA electroacoustic verification steps for fitting FM systems to hearing aids when fitting DM systems to CI users. Electroacoustic measures were conducted on 71 CI sound processors and Phonak Roger DM systems using a proposed protocol and an adapted AAA protocol. Phonak's recommended default receiver gain setting was used for each CI sound processor manufacturer and adjusted if necessary to achieve transparency. Electroacoustic measures were conducted on Cochlear and Advanced Bionics (AB) sound processors. In this study, 28 Cochlear Nucleus 5/CP810 sound processors, 26 Cochlear Nucleus 6/CP910 sound processors, and 17 AB Naida CI Q70 sound processors were coupled in various combinations to Phonak Roger DM dedicated receivers (25 Phonak Roger 14 receivers-Cochlear dedicated receiver-and 9 Phonak Roger 17 receivers-AB dedicated receiver) and 20 Phonak Roger Inspiro transmitters. Employing both the AAA and the Schafer et al protocols, electroacoustic measurements were conducted with the Audioscan Verifit in a clinical setting on 71 CI sound processors and Phonak Roger DM systems to determine transparency and verify FM advantage, comparing speech inputs (65 dB SPL) in an effort to achieve equal outputs. If transparency was not achieved at Phonak's recommended default receiver gain, adjustments were made to the receiver gain. The integrity of the signal was monitored with the appropriate manufacturer's monitor earphones. Using the AAA hearing aid protocol, 50 of the 71 CI sound processors achieved transparency, and 59 of the 71 CI sound processors achieved transparency when using the proposed protocol at Phonak's recommended default receiver gain. After the receiver gain was adjusted, 3 of 21 CI sound processors still did not meet transparency using the AAA protocol, and 2 of 12 CI sound processors still did not meet transparency using the Schafer et al proposed protocol. Both protocols were shown to be effective in taking reliable electroacoustic measurements and demonstrate transparency. Both protocols are felt to be clinically feasible and to address the needs of populations that are unable to reliably report regarding the integrity of their personal DM systems. American Academy of Audiology

Development of living body information monitoring system

NASA Astrophysics Data System (ADS)

Sakamoto, Hidetoshi; Ohbuchi, Yoshifumi; Torigoe, Ippei; Miyagawa, Hidekazu; Murayama, Nobuki; Hayashida, Yuki; Igasaki, Tomohiko

2010-03-01

The easy monitoring systems of contact and non-contact living body information for preventing the the Sudden Infant Death Syndrome (SIDS) were proposed as an alternative monitoring system of the infant's vital information. As for the contact monitoring system, respiration sensor, ECG electrodes, thermistor and IC signal processor were integrated into babies' nappy holder. This contact-monitoring unit has RF transmission function and the obtained data are analyzed in real time by PC. In non-contact mortaring system, the infrared thermo camera was used. The surrounding of the infant's mouth and nose is monitored and the respiration rate is obtained by thermal image processing of its temperature change image of expired air. This proposed system of in-sleep infant's vital information monitoring system and unit are very effective as not only infant's condition monitoring but also nursing person's one.

Development of living body information monitoring system

NASA Astrophysics Data System (ADS)

Sakamoto, Hidetoshi; Ohbuchi, Yoshifumi; Torigoe, Ippei; Miyagawa, Hidekazu; Murayama, Nobuki; Hayashida, Yuki; Igasaki, Tomohiko

2009-12-01

The easy monitoring systems of contact and non-contact living body information for preventing the the Sudden Infant Death Syndrome (SIDS) were proposed as an alternative monitoring system of the infant's vital information. As for the contact monitoring system, respiration sensor, ECG electrodes, thermistor and IC signal processor were integrated into babies' nappy holder. This contact-monitoring unit has RF transmission function and the obtained data are analyzed in real time by PC. In non-contact mortaring system, the infrared thermo camera was used. The surrounding of the infant's mouth and nose is monitored and the respiration rate is obtained by thermal image processing of its temperature change image of expired air. This proposed system of in-sleep infant's vital information monitoring system and unit are very effective as not only infant's condition monitoring but also nursing person's one.

A digital signal processing system for coherent laser radar

NASA Technical Reports Server (NTRS)

Hampton, Diana M.; Jones, William D.; Rothermel, Jeffry

1991-01-01

A data processing system for use with continuous-wave lidar is described in terms of its configuration and performance during the second survey mission of NASA'a Global Backscatter Experiment. The system is designed to estimate a complete lidar spectrum in real time, record the data from two lidars, and monitor variables related to the lidar operating environment. The PC-based system includes a transient capture board, a digital-signal processing (DSP) board, and a low-speed data-acquisition board. Both unprocessed and processed lidar spectrum data are monitored in real time, and the results are compared to those of a previous non-DSP-based system. Because the DSP-based system is digital it is slower than the surface-acoustic-wave signal processor and collects 2500 spectra/s. However, the DSP-based system provides complete data sets at two wavelengths from the continuous-wave lidars.

2-D Acousto-Optic Signal Processors for Simultaneous Spectrum Analysis and Direction Finding

DTIC Science & Technology

1990-11-01

National Dfense Defence nationale 2-D ACOUSTO - OPTIC SIGNAL PROCESSORS FOR SIMULTANEOUS SPECTRUM ANALYSIS 00 AND DIRECTION FINDING (U) by NM Jim P.Y...Wr pdft .1w I0~1111191 3 05089 National DIfense Defence nationale 2-D ACOUSTO - OPTIC SIGNAL PROCESSORS FOR SIMULTANEOUS SPECTRUM ANALYSIS AND DIRECTION...Processing, J.T. Tippet et al., Eds., Chapter 38, pp. 715-748, MIT Press, Cambridge 1965. [6] A.E. Spezio," Acousto - optics for Electronic Warfare

Fault tolerant, radiation hard, high performance digital signal processor

NASA Technical Reports Server (NTRS)

Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

1990-01-01

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

The SKA1 LOW telescope: system architecture and design performance

NASA Astrophysics Data System (ADS)

Waterson, Mark F.; Labate, Maria Grazia; Schnetler, Hermine; Wagg, Jeff; Turner, Wallace; Dewdney, Peter

2016-07-01

The SKA1-LOW radio telescope will be a low-frequency (50-350 MHz) aperture array located in Western Australia. Its scientific objectives will prioritize studies of the Epoch of Reionization and pulsar physics. Development of the telescope has been allocated to consortia responsible for the aperture array front end, timing distribution, signal and data transport, correlation and beamforming signal processors, infrastructure, monitor and control systems, and science data processing. This paper will describe the system architectural design and key performance parameters of the telescope and summarize the high-level sub-system designs of the consortia.

Personal continuous air monitor

DOEpatents

Morgan, Ronald G.; Salazar, Samuel A.

2000-01-01

A personal continuous air monitor capable of giving immediate warning of the presence of radioactivity has a filter/detector head to be worn in the breathing zone of a user, containing a filter mounted adjacent to radiation detectors, and a preamplifier. The filter/detector head is connected to a belt pack to be worn at the waist or on the back of a user. The belt pack contains a signal processor, batteries, a multichannel analyzer, a logic circuit, and an alarm. An air pump also is provided in the belt pack for pulling air through the filter/detector head by way of an air tube.

Control apparatus and method for efficiently heating a fuel processor in a fuel cell system

DOEpatents

Doan, Tien M.; Clingerman, Bruce J.

2003-08-05

A control apparatus and method for efficiently controlling the amount of heat generated by a fuel cell processor in a fuel cell system by determining a temperature error between actual and desired fuel processor temperatures. The temperature error is converted to a combustor fuel injector command signal or a heat dump valve position command signal depending upon the type of temperature error. Logic controls are responsive to the combustor fuel injector command signals and the heat dump valve position command signal to prevent the combustor fuel injector command signal from being generated if the heat dump valve is opened or, alternately, from preventing the heat dump valve position command signal from being generated if the combustor fuel injector is opened.

Electro-optic voltage sensor with beam splitting

DOEpatents

Woods, Gregory K.; Renak, Todd W.; Davidson, James R.; Crawford, Thomas M.

2002-01-01

The invention is a miniature electro-optic voltage sensor system capable of accurate operation at high voltages without use of the dedicated voltage dividing hardware typically found in the prior art. The invention achieves voltage measurement without significant error contributions from neighboring conductors or environmental perturbations. The invention employs a transmitter, a sensor, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor. Within the sensor the beam undergoes the Pockels electro-optic effect. The electro-optic effect produces a modulation of the beam's polarization, which is in turn converted to a pair of independent conversely-amplitude-modulated signals, from which the voltage of the E-field is determined by the signal processor. The use of converse AM signals enables the signal processor to better distinguish signal from noise. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Adaptive control for accelerators

DOEpatents

Eaton, Lawrie E.; Jachim, Stephen P.; Natter, Eckard F.

1991-01-01

An adaptive feedforward control loop is provided to stabilize accelerator beam loading of the radio frequency field in an accelerator cavity during successive pulses of the beam into the cavity. A digital signal processor enables an adaptive algorithm to generate a feedforward error correcting signal functionally determined by the feedback error obtained by a beam pulse loading the cavity after the previous correcting signal was applied to the cavity. Each cavity feedforward correcting signal is successively stored in the digital processor and modified by the feedback error resulting from its application to generate the next feedforward error correcting signal. A feedforward error correcting signal is generated by the digital processor in advance of the beam pulse to enable a composite correcting signal and the beam pulse to arrive concurrently at the cavity.

Wireless and Powerless Sensing Node System Developed for Monitoring Motors.

PubMed

Lee, Dasheng

2008-08-27

Reliability and maintainability of tooling systems can be improved through condition monitoring of motors. However, it is difficult to deploy sensor nodes due to the harsh environment of industrial plants. Sensor cables are easily damaged, which renders the monitoring system deployed to assure the machine's reliability itself unreliable. A wireless and powerless sensing node integrated with a MEMS (Micro Electro-Mechanical System) sensor, a signal processor, a communication module, and a self-powered generator was developed in this study for implementation of an easily mounted network sensor for monitoring motors. A specially designed communication module transmits a sequence of electromagnetic (EM) pulses in response to the sensor signals. The EM pulses can penetrate through the machine's metal case and delivers signals from the sensor inside the motor to the external data acquisition center. By using induction power, which is generated by the motor's shaft rotation, the sensor node is self-sustaining; therefore, no power line is required. A monitoring system, equipped with novel sensing nodes, was constructed to test its performance. The test results illustrate that, the novel sensing node developed in this study can effectively enhance the reliability of the motor monitoring system and it is expected to be a valuable technology, which will be available to the plant for implementation in a reliable motor management program.

Wireless and Powerless Sensing Node System Developed for Monitoring Motors

PubMed Central

Lee, Dasheng

2008-01-01

Reliability and maintainability of tooling systems can be improved through condition monitoring of motors. However, it is difficult to deploy sensor nodes due to the harsh environment of industrial plants. Sensor cables are easily damaged, which renders the monitoring system deployed to assure the machine's reliability itself unreliable. A wireless and powerless sensing node integrated with a MEMS (Micro Electro-Mechanical System) sensor, a signal processor, a communication module, and a self-powered generator was developed in this study for implementation of an easily mounted network sensor for monitoring motors. A specially designed communication module transmits a sequence of electromagnetic (EM) pulses in response to the sensor signals. The EM pulses can penetrate through the machine's metal case and delivers signals from the sensor inside the motor to the external data acquisition center. By using induction power, which is generated by the motor's shaft rotation, the sensor node is self-sustaining; therefore, no power line is required. A monitoring system, equipped with novel sensing nodes, was constructed to test its performance. The test results illustrate that, the novel sensing node developed in this study can effectively enhance the reliability of the motor monitoring system and it is expected to be a valuable technology, which will be available to the plant for implementation in a reliable motor management program. PMID:27873798

Variable word length encoder reduces TV bandwith requirements

NASA Technical Reports Server (NTRS)

Sivertson, W. E., Jr.

1965-01-01

Adaptive variable resolution encoding technique provides an adaptive compression pseudo-random noise signal processor for reducing television bandwidth requirements. Complementary processors are required in both the transmitting and receiving systems. The pretransmission processor is analog-to-digital, while the postreception processor is digital-to-analog.

System and method for programmable bank selection for banked memory subsystems

DOEpatents

Blumrich, Matthias A.; Chen, Dong; Gara, Alan G.; Giampapa, Mark E.; Hoenicke, Dirk; Ohmacht, Martin; Salapura, Valentina; Sugavanam, Krishnan

2010-09-07

A programmable memory system and method for enabling one or more processor devices access to shared memory in a computing environment, the shared memory including one or more memory storage structures having addressable locations for storing data. The system comprises: one or more first logic devices associated with a respective one or more processor devices, each first logic device for receiving physical memory address signals and programmable for generating a respective memory storage structure select signal upon receipt of pre-determined address bit values at selected physical memory address bit locations; and, a second logic device responsive to each of the respective select signal for generating an address signal used for selecting a memory storage structure for processor access. The system thus enables each processor device of a computing environment memory storage access distributed across the one or more memory storage structures.

Independent backup mode transfer and mechanism for digital control computers

NASA Technical Reports Server (NTRS)

Tulpule, Bhalchandra R. (Inventor); Oscarson, Edward M. (Inventor)

1992-01-01

An interrupt is provided to a signal processor having a non-maskable interrupt input, in response to the detection of a request for transfer to backup software. The signal processor provides a transfer signal to a transfer mechanism only after completion of the present machine cycle. Transfer to the backup software is initiated by the transfer mechanism only upon reception of the transfer signal.

Ash level meter for a fixed-bed coal gasifier

DOEpatents

Fasching, George E.

1984-01-01

An ash level meter for a fixed-bed coal gasifier is provided which utilizes the known ash level temperature profile to monitor the ash bed level. A bed stirrer which travels up and down through the extent of the bed ash level is modified by installing thermocouples to measure the bed temperature as the stirrer travels through the stirring cycle. The temperature measurement signals are transmitted to an electronic signal process system by an FM/FM telemetry system. The processing system uses the temperature signals together with an analog stirrer position signal, taken from a position transducer disposed to measure the stirrer position to compute the vertical location of the ash zone upper boundary. The circuit determines the fraction of each total stirrer cycle time the stirrer-derived bed temperature is below a selected set point, multiplies this fraction by the average stirrer signal level, multiplies this result by an appropriate constant and adds another constant such that a 1 to 5 volt signal from the processor corresponds to a 0 to 30 inch span of the ash upper boundary level. Three individual counters in the processor store clock counts that are representative of: (1) the time the stirrer temperature is below the set point (500.degree. F.), (2) the time duration of the corresponding stirrer travel cycle, and (3) the corresponding average stirrer vertical position. The inputs to all three counters are disconnected during any period that the stirrer is stopped, eliminating corruption of the measurement by stirrer stoppage.

A distributed fault-tolerant signal processor /FTSP/

NASA Astrophysics Data System (ADS)

Bonneau, R. J.; Evett, R. C.; Young, M. J.

1980-01-01

A digital fault-tolerant signal processor (FTSP), an example of a self-repairing programmable system is analyzed. The design configuration is discussed in terms of fault tolerance, system-level fault detection, isolation and common memory. Special attention is given to the FDIR (fault detection isolation and reconfiguration) logic, noting that the reconfiguration decisions are based on configuration, summary status, end-around tests, and north marker/synchro data. Several mechanisms of fault detection are described which initiate reconfiguration at different levels. It is concluded that the reliability of a signal processor can be significantly enhanced by the use of fault-tolerant techniques.

ALMA Correlator Real-Time Data Processor

NASA Astrophysics Data System (ADS)

Pisano, J.; Amestica, R.; Perez, J.

2005-10-01

The design of a real-time Linux application utilizing Real-Time Application Interface (RTAI) to process real-time data from the radio astronomy correlator for the Atacama Large Millimeter Array (ALMA) is described. The correlator is a custom-built digital signal processor which computes the cross-correlation function of two digitized signal streams. ALMA will have 64 antennas with 2080 signal streams each with a sample rate of 4 giga-samples per second. The correlator's aggregate data output will be 1 gigabyte per second. The software is defined by hard deadlines with high input and processing data rates, while requiring interfaces to non real-time external computers. The designed computer system - the Correlator Data Processor or CDP, consists of a cluster of 17 SMP computers, 16 of which are compute nodes plus a master controller node all running real-time Linux kernels. Each compute node uses an RTAI kernel module to interface to a 32-bit parallel interface which accepts raw data at 64 megabytes per second in 1 megabyte chunks every 16 milliseconds. These data are transferred to tasks running on multiple CPUs in hard real-time using RTAI's LXRT facility to perform quantization corrections, data windowing, FFTs, and phase corrections for a processing rate of approximately 1 GFLOPS. Highly accurate timing signals are distributed to all seventeen computer nodes in order to synchronize them to other time-dependent devices in the observatory array. RTAI kernel tasks interface to the timing signals providing sub-millisecond timing resolution. The CDP interfaces, via the master node, to other computer systems on an external intra-net for command and control, data storage, and further data (image) processing. The master node accesses these external systems utilizing ALMA Common Software (ACS), a CORBA-based client-server software infrastructure providing logging, monitoring, data delivery, and intra-computer function invocation. The software is being developed in tandem with the correlator hardware which presents software engineering challenges as the hardware evolves. The current status of this project and future goals are also presented.

Methods and Apparatus for Aggregation of Multiple Pulse Code Modulation Channels into a Signal Time Division Multiplexing Stream

NASA Technical Reports Server (NTRS)

Chang, Chen J. (Inventor); Liaghati, Jr., Amir L. (Inventor); Liaghati, Mahsa L. (Inventor)

2018-01-01

Methods and apparatus are provided for telemetry processing using a telemetry processor. The telemetry processor can include a plurality of communications interfaces, a computer processor, and data storage. The telemetry processor can buffer sensor data by: receiving a frame of sensor data using a first communications interface and clock data using a second communications interface, receiving an end of frame signal using a third communications interface, and storing the received frame of sensor data in the data storage. After buffering the sensor data, the telemetry processor can generate an encapsulated data packet including a single encapsulated data packet header, the buffered sensor data, and identifiers identifying telemetry devices that provided the sensor data. A format of the encapsulated data packet can comply with a Consultative Committee for Space Data Systems (CCSDS) standard. The telemetry processor can send the encapsulated data packet using a fourth and a fifth communications interfaces.

Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications

NASA Astrophysics Data System (ADS)

Chung, Wen-Yaw; Yang, Chung-Huang; Peng, Kang-Chu; Yeh, M. H.

2003-04-01

This paper presents a modular-based low-voltage analog-front-end processor design in a 0.5mm double-poly double-metal CMOS technology for Ion Sensitive Field Effect Transistor (ISFET)-based sensor and H+ sensing applications. To meet the potentiometric response of the ISFET that is proportional to various H+ concentrations, the constant-voltage and constant current (CVCS) testing configuration has been used. Low-voltage design skills such as bulk-driven input pair, folded-cascode amplifier, bootstrap switch control circuits have been designed and integrated for 1.5V supply and nearly rail-to-rail analog to digital signal processing. Core modules consist of an 8-bit two-step analog-digital converter and bulk-driven pre-amplifiers have been developed in this research. The experimental results show that the proposed circuitry has an acceptable linearity to 0.1 pH-H+ sensing conversions with the buffer solution in the range of pH2 to pH12. The processor has a potential usage in battery-operated and portable healthcare devices and environmental monitoring applications.

Human factors considerations in the evaluation of processor-based signal and train control systems

DOT National Transportation Integrated Search

2007-06-01

In August 2001, the Federal Railroad Administration issued the notice of proposed rulemaking: Standards for Development and : Use of Processor-Based Signal and Train Control Systems (49 Code of Federal Regulations Part 236). This proposed rule addres...

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

NASA Astrophysics Data System (ADS)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

Fuzzy logic electric vehicle regenerative antiskid braking and traction control system

DOEpatents

Cikanek, S.R.

1994-10-25

An regenerative antiskid braking and traction control system using fuzzy logic for an electric or hybrid vehicle having a regenerative braking system operatively connected to an electric traction motor, and a separate hydraulic braking system includes sensors for monitoring present vehicle parameters and a processor, responsive to the sensors, for calculating vehicle parameters defining the vehicle behavior not directly measurable by the sensor and determining if regenerative antiskid braking control, requiring hydraulic braking control, and requiring traction control are required. The processor then employs fuzzy logic based on the determined vehicle state and provides command signals to a motor controller to control operation of the electric traction motor and to the brake controller to control fluid pressure applied at each vehicle wheel to provide the appropriate regenerative braking control, hydraulic braking control, and traction control. 123 figs.

Electric vehicle regenerative antiskid braking and traction control system

DOEpatents

Cikanek, S.R.

1995-09-12

An antiskid braking and traction control system for an electric or hybrid vehicle having a regenerative braking system operatively connected to an electric traction motor, and a separate hydraulic braking system includes one or more sensors for monitoring present vehicle parameters and a processor, responsive to the sensors, for calculating vehicle parameters defining the vehicle behavior not directly measurable by the sensors and determining if regenerative antiskid braking control, requiring hydraulic braking control, or requiring traction control are required. The processor then employs a control strategy based on the determined vehicle state and provides command signals to a motor controller to control the operation of the electric traction motor and to a brake controller to control fluid pressure applied at each vehicle wheel to provide the appropriate regenerative antiskid braking control, hydraulic braking control, and traction control. 10 figs.

Electric vehicle regenerative antiskid braking and traction control system

DOEpatents

Cikanek, Susan R.

1995-01-01

An antiskid braking and traction control system for an electric or hybrid vehicle having a regenerative braking system operatively connected to an electric traction motor, and a separate hydraulic braking system includes one or more sensors for monitoring present vehicle parameters and a processor, responsive to the sensors, for calculating vehicle parameters defining the vehicle behavior not directly measurable by the sensors and determining if regenerative antiskid braking control, requiring hydrualic braking control, or requiring traction control are required. The processor then employs a control strategy based on the determined vehicle state and provides command signals to a motor controller to control the operation of the electric traction motor and to a brake controller to control fluid pressure applied at each vehicle wheel to provide the appropriate regenerative antiskid braking control, hydraulic braking control, and traction control.

Fuzzy logic electric vehicle regenerative antiskid braking and traction control system

DOEpatents

Cikanek, Susan R.

1994-01-01

An regenerative antiskid braking and traction control system using fuzzy logic for an electric or hybrid vehicle having a regenerative braking system operatively connected to an electric traction motor, and a separate hydraulic braking system includes sensors for monitoring present vehicle parameters and a processor, responsive to the sensors, for calculating vehicle parameters defining the vehicle behavior not directly measurable by the sensor and determining if regenerative antiskid braking control, requiring hydraulic braking control, and requiring traction control are required. The processor then employs fuzzy logic based on the determined vehicle state and provides command signals to a motor controller to control operation of the electric traction motor and to the brake controller to control fluid pressure applied at each vehicle wheel to provide the appropriate regenerative braking control, hydraulic braking control, and traction control.

Electronic clinical predictive thermometer using logarithm for temperature prediction

NASA Technical Reports Server (NTRS)

Cambridge, Vivien J. (Inventor); Koger, Thomas L. (Inventor); Nail, William L. (Inventor); Diaz, Patrick (Inventor)

1998-01-01

A thermometer that rapidly predicts body temperature based on the temperature signals received from a temperature sensing probe when it comes into contact with the body. The logarithms of the differences between the temperature signals in a selected time frame are determined. A line is fit through the logarithms and the slope of the line is used as a system time constant in predicting the final temperature of the body. The time constant in conjunction with predetermined additional constants are used to compute the predicted temperature. Data quality in the time frame is monitored and if unacceptable, a different time frame of temperature signals is selected for use in prediction. The processor switches to a monitor mode if data quality over a limited number of time frames is unacceptable. Determining the start time on which the measurement time frame for prediction is based is performed by summing the second derivatives of temperature signals over time frames. When the sum of second derivatives in a particular time frame exceeds a threshold, the start time is established.

Fluid leakage detector for vacuum applications

NASA Technical Reports Server (NTRS)

Nguyen, Bich Ngoc (Inventor); Farkas, Tibor (Inventor); Kim, Brian Byungkyu (Inventor)

2002-01-01

A leak detection system for use with a fluid conducting system in a vacuum environment, such as space, is described. The system preferably includes a mesh-like member substantially disposed about the fluid conducting system, and at least one sensor disposed within the mesh-like member. The sensor is capable of detecting a decrease in temperature of the mesh-like member when a leak condition causes the fluid of the fluid conducting system to freeze when exposed to the vacuum environment. Additionally, a signal processor in preferably in communication with the sensor. The sensor transmits an electrical signal to the signal processor such that the signal processor is capable of indicating the location of the fluid leak in the fluid conducting system.

Parallel Implementation of the Wideband DOA Algorithm on the IBM Cell BE Processor

DTIC Science & Technology

2010-05-01

Abstract—The Multiple Signal Classification ( MUSIC ) algorithm is a powerful technique for determining the Direction of Arrival (DOA) of signals...Broadband Engine Processor (Cell BE). The process of adapting the serial based MUSIC algorithm to the Cell BE will be analyzed in terms of parallelism and...using Multiple Signal Classification MUSIC algorithm [4] • Computation of Focus matrix • Computation of number of sources • Separation of Signal

Optical signal processing of spatially distributed sensor data in smart structures

NASA Technical Reports Server (NTRS)

Bennett, K. D.; Claus, R. O.; Murphy, K. A.; Goette, A. M.

1989-01-01

Smart structures which contain dense two- or three-dimensional arrays of attached or embedded sensor elements inherently require signal multiplexing and processing capabilities to permit good spatial data resolution as well as the adequately short calculation times demanded by real time active feedback actuator drive circuitry. This paper reports the implementation of an in-line optical signal processor and its application in a structural sensing system which incorporates multiple discrete optical fiber sensor elements. The signal processor consists of an array of optical fiber couplers having tailored s-parameters and arranged to allow gray code amplitude scaling of sensor inputs. The use of this signal processor in systems designed to indicate the location of distributed strain and damage in composite materials, as well as to quantitatively characterize that damage, is described. Extension of similar signal processing methods to more complicated smart materials and structures applications are discussed.

System-wide power management control via clock distribution network

DOEpatents

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

2015-05-19

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

An ultra-low power (ULP) bandage-type ECG sensor for efficient cardiac disease management.

PubMed

Shin, Kunsoo; Park, G G; Kim, J P; Lee, T H; Ko, B H; Kim, Y H

2013-01-01

This paper proposed an ultra-low power bandage-type ECG sensor (the size: 76 × 34 × 3 (mm(3)) and the power consumption: 1 mW) which allows for a continuous and real-time monitoring of a user's ECG signals over 24h during daily activities. For its compact size and lower power consumption, we designed the analog front-end, the SRP (Samsung Reconfigurable Processor) based DSP of 30 uW/MHz, and the ULP wireless RF of 1 nJ/bit. Also, to tackle motion artifacts(MA), a MA monitoring technique based on the HCP (Half-cell Potential) is proposed which resulted in the high correlation between the MA and the HCP, the correlation coefficient of 0.75 ± 0.18. To assess its feasibility and validity as a wearable health monitor, we performed the comparison of two ECG signals recorded form it and a conventional Holter device. As a result, the performance of the former is a little lower as compared with the latter, although showing no statistical significant difference (the quality of the signal: 94.3% vs 99.4%; the accuracy of arrhythmia detection: 93.7% vs 98.7%). With those results, it has been confirmed that it can be used as a wearable health monitor due to its comfortability, its long operation lifetime and the good quality of the measured ECG signal.

Fault-Tolerant, Radiation-Hard DSP

NASA Technical Reports Server (NTRS)

Czajkowski, David

2011-01-01

Commercial digital signal processors (DSPs) for use in high-speed satellite computers are challenged by the damaging effects of space radiation, mainly single event upsets (SEUs) and single event functional interrupts (SEFIs). Innovations have been developed for mitigating the effects of SEUs and SEFIs, enabling the use of very-highspeed commercial DSPs with improved SEU tolerances. Time-triple modular redundancy (TTMR) is a method of applying traditional triple modular redundancy on a single processor, exploiting the VLIW (very long instruction word) class of parallel processors. TTMR improves SEU rates substantially. SEFIs are solved by a SEFI-hardened core circuit, external to the microprocessor. It monitors the health of the processor, and if a SEFI occurs, forces the processor to return to performance through a series of escalating events. TTMR and hardened-core solutions were developed for both DSPs and reconfigurable field-programmable gate arrays (FPGAs). This includes advancement of TTMR algorithms for DSPs and reconfigurable FPGAs, plus a rad-hard, hardened-core integrated circuit that services both the DSP and FPGA. Additionally, a combined DSP and FPGA board architecture was fully developed into a rad-hard engineering product. This technology enables use of commercial off-the-shelf (COTS) DSPs in computers for satellite and other space applications, allowing rapid deployment at a much lower cost. Traditional rad-hard space computers are very expensive and typically have long lead times. These computers are either based on traditional rad-hard processors, which have extremely low computational performance, or triple modular redundant (TMR) FPGA arrays, which suffer from power and complexity issues. Even more frustrating is that the TMR arrays of FPGAs require a fixed, external rad-hard voting element, thereby causing them to lose much of their reconfiguration capability and in some cases significant speed reduction. The benefits of COTS high-performance signal processing include significant increase in onboard science data processing, enabling orders of magnitude reduction in required communication bandwidth for science data return, orders of magnitude improvement in onboard mission planning and critical decision making, and the ability to rapidly respond to changing mission environments, thus enabling opportunistic science and orders of magnitude reduction in the cost of mission operations through reduction of required staff. Additional benefits of COTS-based, high-performance signal processing include the ability to leverage considerable commercial and academic investments in advanced computing tools, techniques, and infra structure, and the familiarity of the science and IT community with these computing environments.

Portable obstructive sleep apnea detection and mobile monitoring

NASA Astrophysics Data System (ADS)

Demirkol ćakmak, Duygu; Eyüboǧlu, B. Murat

2017-05-01

Obstructive sleep apnea syndrome is becoming a prevalent disease for both adults and children. It is described as the cessation of breath for at least 10 seconds during sleep. Detecting sleep apnea is considered as a troublesome and timeconsuming method, which requires the patients to stay one or more nights in dedicated sleep disorder rooms with sensors physically attached to their body. Undiagnosed thereby untreated sleep apnea patients are under high risk of hypertension, heart attack, traffic accident through fatigue and sleeplessness. In this project, nasal and oral respiratory information is obtained with utilizing thermocouple and oxygen saturation in the blood is obtained with utilizing pulse oximeter. An analog hardware circuit is designed to readout thermocouple and pulse oximeter signals. According to this respiratory and pulse oximetry signals, obstructive sleep apnea is detected in real time with using a software implemented into an ARM based processor. An Android mobile application is developed to record and display the oxygen saturation, heart rate and respiratory signal data during sleep. ARM based processor and mobile application communication is established via Bluetooth interface to reduce cabling on the patient. In summary, a portable, low cost and user friendly device to detect obstructive sleep apnea which is able to share the necessary information to the patients and doctors for the duration of the whole sleep cycle is developed.

Fiber-Optic Sensor And Smart Structures Research At Florida Institute Of Technology

NASA Astrophysics Data System (ADS)

Grossman, Barry G.; Alavie, A. Tino; Ham, Fredric M.; Franke, Jorge E.; Thursby, Michael H.

1990-02-01

This paper discusses the fundamental issues being investigated by Florida Institute of Technology (F.I.T.) to implement the technology of smart structural systems for DoD, NASA, and commercial applications. Embedded sensors and actuators controlled by processors can provide a modification of the mechanical characteristics of composite structures to produce smart structures1-3. Recent advances in material science have spurred the development and use of composite materials in a wide range of applications from rotocraft blades and advanced tactical fighter aircraft to undersea and aerospace structures. Along with the advantages of an increased strength-to-weight ratio, the use of these materials has raised a number of questions related to understanding their failure mechanisms. Also, being able to predict structural failures far enough in advance to prevent them and to provide real-time structural health and damage monitoring has become a realistic possibility. Unfortunately, conventional sensors, actuators, and digital processors, although highly developed and well proven for other systems, may not be best suited for most smart structure applications. Our research has concentrated on few-mode and polarimetric single-fiber strain sensors4-7 and optically activated shape memory alloy (SMA) actuators controlled by artificial neural processors. We have constructed and characterized both few-mode and polarimetric sensors for a variety of fiber types, including standard single-mode, high-birefringence polarization preserving, and low-birefringence polarization insensitive fibers. We have investigated signal processing techniques for these sensors and have demonstrated active phase tracking for the high- and low-birefringence polarimetric sensors through the incorporation into the system of an electrooptic modulator designed and fabricated at F.I.T.. We have also started the design and testing of neural network architectures for processing the sensor signal outputs to calculate strain magnitude and actuator control signals for simple structures.

FERMILAB CRYOMODULE TEST STAND RF INTERLOCK SYSTEM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Petersen, Troy; Diamond, J. S.; McDowell, D.

2016-10-12

An interlock system has been designed for the Fermilab Cryo-module Test Stand (CMTS), a test bed for the cryo- modules to be used in the upcoming Linac Coherent Light Source 2 (LCLS-II) project at SLAC. The interlock system features 8 independent subsystems, one per superconducting RF cavity and solid state amplifier (SSA) pair. Each system monitors several devices to detect fault conditions such as arcing in the waveguides or quenching of the SRF system. Additionally each system can detect fault conditions by monitoring the RF power seen at the cavity coupler through a directional coupler. In the event of amore » fault condition, each system is capable of removing RF signal to the amplifier (via a fast RF switch) as well as turning off the SSA. Additionally, each input signal is available for re- mote viewing and recording via a Fermilab designed digitizer board and MVME 5500 processor.« less

A high-speed digital signal processor for atmospheric radar, part 7.3A

NASA Technical Reports Server (NTRS)

Brosnahan, J. W.; Woodard, D. M.

1984-01-01

The Model SP-320 device is a monolithic realization of a complex general purpose signal processor, incorporating such features as a 32-bit ALU, a 16-bit x 16-bit combinatorial multiplier, and a 16-bit barrel shifter. The SP-320 is designed to operate as a slave processor to a host general purpose computer in applications such as coherent integration of a radar return signal in multiple ranges, or dedicated FFT processing. Presently available is an I/O module conforming to the Intel Multichannel interface standard; other I/O modules will be designed to meet specific user requirements. The main processor board includes input and output FIFO (First In First Out) memories, both with depths of 4096 W, to permit asynchronous operation between the source of data and the host computer. This design permits burst data rates in excess of 5 MW/s.

An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

PubMed

Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

2014-01-01

This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

A wideband software reconfigurable modem

NASA Astrophysics Data System (ADS)

Turner, J. H., Jr.; Vickers, H.

A wideband modem is described which provides signal processing capability for four Lx-band signals employing QPSK, MSK and PPM waveforms and employs a software reconfigurable architecture for maximum system flexibility and graceful degradation. The current processor uses a 2901 and two 8086 microprocessors per channel and performs acquisition, tracking, and data demodulation for JITDS, GPS, IFF and TACAN systems. The next generation processor will be implemented using a VHSIC chip set employing a programmable complex array vector processor module, a GP computer module, customized gate array modules, and a digital array correlator. This integrated processor has application to a wide number of diverse system waveforms, and will bring the benefits of VHSIC technology insertion into avionic antijam communications systems.

Noncoherent parallel optical processor for discrete two-dimensional linear transformations.

PubMed

Glaser, I

1980-10-01

We describe a parallel optical processor, based on a lenslet array, that provides general linear two-dimensional transformations using noncoherent light. Such a processor could become useful in image- and signal-processing applications in which the throughput requirements cannot be adequately satisfied by state-of-the-art digital processors. Experimental results that illustrate the feasibility of the processor by demonstrating its use in parallel optical computation of the two-dimensional Walsh-Hadamard transformation are presented.

Spacewire on Earth orbiting scatterometers

NASA Technical Reports Server (NTRS)

Bachmann, Alex; Lang, Minh; Lux, James; Steffke, Richard

2002-01-01

The need for a high speed, reliable and easy to implement communication link has led to the development of a space flight oriented version of IEEE 1355 called SpaceWire. SpaceWire is based on high-speed (200 Mbps) serial point-to-point links using Low Voltage Differential Signaling (LVDS). SpaceWIre has provisions for routing messages between a large network of processors, using wormhole routing for low overhead and latency. {additionally, there are available space qualified hybrids, which provide the Link layer to the user's bus}. A test bed of multiple digital signal processor breadboards, demonstrating the ability to meet signal processing requirements for an orbiting scatterometer has been implemented using three Astrium MCM-DSPs, each breadboard consists of a Multi Chip Module (MCM) that combines a space qualified Digital Signal Processor and peripherals, including IEEE-1355 links. With the addition of appropriate physical layer interfaces and software on the DSP, the SpaceWire link is used to communicate between processors on the test bed, e.g. sending timing references, commands, status, and science data among the processors. Results are presented on development issues surrounding the use of SpaceWire in this environment, from physical layer implementation (cables, connectors, LVDS drivers) to diagnostic tools, driver firmware, and development methodology. The tools, methods, and hardware, software challenges and preliminary performance are investigated and discussed.

Evaluation of pH monitoring as a method of processor control.

PubMed

Stears, J G; Gray, J E; Winkler, N T

1979-01-01

Sensitometry and pH values of the developer solution were compared in controlled over-replenishment, developer depletion, fixer contamination experiments, and on a daily quality control basis. The purpose of these comparisons was to evaluate the potential of pH monitoring as a method of processor control, or a supplement to sensitometry as a method of quality control. Reasonable correlation was found between pH values and film density in two of the three experiments but little or no correlation was found in the third experiment and on a day-to-day basis. The conclusion drawn from these comparisons is that pH monitoring has several limitations which render it unsuitable as a method of daily processor quality control as either a primary or supplementary technique. Sensitometry takes into account all the variables encountered in film processing and is the clear method of choice for processor quality control.

Advanced satellite communication system

NASA Technical Reports Server (NTRS)

Staples, Edward J.; Lie, Sen

1992-01-01

The objective of this research program was to develop an innovative advanced satellite receiver/demodulator utilizing surface acoustic wave (SAW) chirp transform processor and coherent BPSK demodulation. The algorithm of this SAW chirp Fourier transformer is of the Convolve - Multiply - Convolve (CMC) type, utilizing off-the-shelf reflective array compressor (RAC) chirp filters. This satellite receiver, if fully developed, was intended to be used as an on-board multichannel communications repeater. The Advanced Communications Receiver consists of four units: (1) CMC processor, (2) single sideband modulator, (3) demodulator, and (4) chirp waveform generator and individual channel processors. The input signal is composed of multiple user transmission frequencies operating independently from remotely located ground terminals. This signal is Fourier transformed by the CMC Processor into a unique time slot for each user frequency. The CMC processor is driven by a waveform generator through a single sideband (SSB) modulator. The output of the coherent demodulator is composed of positive and negative pulses, which are the envelopes of the chirp transform processor output. These pulses correspond to the data symbols. Following the demodulator, a logic circuit reconstructs the pulses into data, which are subsequently differentially decoded to form the transmitted data. The coherent demodulation and detection of BPSK signals derived from a CMC chirp transform processor were experimentally demonstrated and bit error rate (BER) testing was performed. To assess the feasibility of such advanced receiver, the results were compared with the theoretical analysis and plotted for an average BER as a function of signal-to-noise ratio. Another goal of this SBIR program was the development of a commercial product. The commercial product developed was an arbitrary waveform generator. The successful sales have begun with the delivery of the first arbitrary waveform generator.

Self-Calibrating and Remote Programmable Signal Conditioning Amplifier System and Method

NASA Technical Reports Server (NTRS)

Medelius, Pedro J. (Inventor); Hallberg, Carl G. (Inventor); Simpson, Howard J., III (Inventor); Thayer, Stephen W. (Inventor)

1998-01-01

A self-calibrating, remote programmable signal conditioning amplifier system employs information read from a memory attached to a measurement transducer for automatic calibration. The signal conditioning amplifier is self-calibrated on a continuous basis through use of a dual input path arrangement, with each path containing a multiplexer and a programmable amplifier. A digital signal processor controls operation of the system such that a transducer signal is applied to one of the input paths, while one or more calibration signals are applied to the second input path. Once the second path is calibrated, the digital signal processor switches the transducer signal to the second path. and then calibrates the first path. This process is continually repeated so that each path is calibrated on an essentially continuous basis. Dual output paths are also employed which are calibrated in the same manner. The digital signal processor also allows the implementation of a variety of digital filters which are either programmed into the system or downloaded by an operator, and performs up to eighth order linearization.

New real-time algorithms for arbitrary, high precision function generation with applications to acoustic transducer excitation

NASA Astrophysics Data System (ADS)

Gaydecki, P.

2009-07-01

A system is described for the design, downloading and execution of arbitrary functions, intended for use with acoustic and low-frequency ultrasonic transducers in condition monitoring and materials testing applications. The instrumentation comprises a software design tool and a powerful real-time digital signal processor unit, operating at 580 million multiplication-accumulations per second (MMACs). The embedded firmware employs both an established look-up table approach and a new function interpolation technique to generate the real-time signals with very high precision and flexibility. Using total harmonic distortion (THD) analysis, the purity of the waveforms have been compared with those generated using traditional analogue function generators; this analysis has confirmed that the new instrument has a consistently superior signal-to-noise ratio.

Digital Parallel Processor Array for Optimum Path Planning

NASA Technical Reports Server (NTRS)

Kremeny, Sabrina E. (Inventor); Fossum, Eric R. (Inventor); Nixon, Robert H. (Inventor)

1996-01-01

The invention computes the optimum path across a terrain or topology represented by an array of parallel processor cells interconnected between neighboring cells by links extending along different directions to the neighboring cells. Such an array is preferably implemented as a high-speed integrated circuit. The computation of the optimum path is accomplished by, in each cell, receiving stimulus signals from neighboring cells along corresponding directions, determining and storing the identity of a direction along which the first stimulus signal is received, broadcasting a subsequent stimulus signal to the neighboring cells after a predetermined delay time, whereby stimulus signals propagate throughout the array from a starting one of the cells. After propagation of the stimulus signal throughout the array, a master processor traces back from a selected destination cell to the starting cell along an optimum path of the cells in accordance with the identity of the directions stored in each of the cells.

Diagnostic monitor for carbon fiber processing

DOEpatents

Paulauskas, Felix L.; Bigelow, Timothy S.; Meek, Thomas T.

2002-01-01

A method for monitoring characteristics of materials includes placing a material in an application zone, measuring a change in at least one property value of the application zone caused by placing the material in the application zone and relating changes in the property value of the application zone caused by the material to at least one characteristic of the material An apparatus for monitoring characteristics of a material includes a measuring device for measuring a property value resulting from applying a frequency signal to the application zone after placing a material in the application zone and a processor for relating changes in the property value caused by placement of the material in the application zone to at least one desired characteristic of the material. The application zone is preferably a resonant cavity.

DSP Implementation of the Retinex Image Enhancement Algorithm

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2004-01-01

The Retinex is a general-purpose image enhancement algorithm that is used to produce good visual representations of scenes. It performs a non-linear spatial/spectral transform that synthesizes strong local contrast enhancement and color constancy. A real-time, video frame rate implementation of the Retinex is required to meet the needs of various potential users. Retinex processing contains a relatively large number of complex computations, thus to achieve real-time performance using current technologies requires specialized hardware and software. In this paper we discuss the design and development of a digital signal processor (DSP) implementation of the Retinex. The target processor is a Texas Instruments TMS320C6711 floating point DSP. NTSC video is captured using a dedicated frame-grabber card, Retinex processed, and displayed on a standard monitor. We discuss the optimizations used to achieve real-time performance of the Retinex and also describe our future plans on using alternative architectures.

Software-defined reconfigurable microwave photonics processor.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

Limit characteristics of digital optoelectronic processor

NASA Astrophysics Data System (ADS)

Kolobrodov, V. G.; Tymchik, G. S.; Kolobrodov, M. S.

2018-01-01

In this article, the limiting characteristics of a digital optoelectronic processor are explored. The limits are defined by diffraction effects and a matrix structure of the devices for input and output of optical signals. The purpose of a present research is to optimize the parameters of the processor's components. The developed physical and mathematical model of DOEP allowed to establish the limit characteristics of the processor, restricted by diffraction effects and an array structure of the equipment for input and output of optical signals, as well as to optimize the parameters of the processor's components. The diameter of the entrance pupil of the Fourier lens is determined by the size of SLM and the pixel size of the modulator. To determine the spectral resolution, it is offered to use a concept of an optimum phase when the resolved diffraction maxima coincide with the pixel centers of the radiation detector.

LANDSAT-D flight segment operations manual. Appendix B: OBC software operations

NASA Technical Reports Server (NTRS)

Talipsky, R.

1981-01-01

The LANDSAT 4 satellite contains two NASA standard spacecraft computers and 65,536 words of memory. Onboard computer software is divided into flight executive and applications processors. Both applications processors and the flight executive use one or more of 67 system tables to obtain variables, constants, and software flags. Output from the software for monitoring operation is via 49 OBC telemetry reports subcommutated in the spacecraft telemetry. Information is provided about the flight software as it is used to control the various spacecraft operations and interpret operational OBC telemetry. Processor function descriptions, processor operation, software constraints, processor system tables, processor telemetry, and processor flow charts are presented.

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

NASA Technical Reports Server (NTRS)

Petrick, Dave

2014-01-01

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Through-the-earth radio

DOEpatents

Reagor, David [Los Alamos, NM; Vasquez-Dominguez, Jose [Los Alamos, NM

2006-05-09

A method and apparatus for effective through-the-earth communication involves a signal input device connected to a transmitter operating at a predetermined frequency sufficiently low to effectively penetrate useful distances through-the earth, and having an analog to digital converter receiving the signal input and passing the signal input to a data compression circuit that is connected to an encoding processor, the encoding processor output being provided to a digital to analog converter. An amplifier receives the analog output from the digital to analog converter for amplifying said analog output and outputting said analog output to an antenna. A receiver having an antenna receives the analog output passes the analog signal to a band pass filter whose output is connected to an analog to digital converter that provides a digital signal to a decoding processor whose output is connected to an data decompressor, the data decompressor providing a decompressed digital signal to a digital to analog converter. An audio output device receives the analog output form the digital to analog converter for producing audible output.

Multi-frequency communication system and method

DOEpatents

Carrender, Curtis Lee; Gilbert, Ronald W.

2004-06-01

A multi-frequency RFID remote communication system is provided that includes a plurality of RFID tags configured to receive a first signal and to return a second signal, the second signal having a first frequency component and a second frequency component, the second frequency component including data unique to each remote RFID tag. The system further includes a reader configured to transmit an interrogation signal and to receive remote signals from the tags. A first signal processor, preferably a mixer, removes an intermediate frequency component from the received signal, and a second processor, preferably a second mixer, analyzes the IF frequency component to output data that is unique to each remote tag.

Frequency domain laser velocimeter signal processor

NASA Technical Reports Server (NTRS)

Meyers, James F.; Murphy, R. Jay

1991-01-01

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a signal processor capable of operating in the frequency domain maximizing the information obtainable from each signal burst. This allows a sophisticated approach to signal detection and processing, with a more accurate measurement of the chirp frequency resulting in an eight-fold increase in measurable signals over the present high-speed burst counter technology. Further, the required signal-to-noise ratio is reduced by a factor of 32, allowing measurements within boundary layers of wind tunnel models. Measurement accuracy is also increased up to a factor of five.

VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal

NASA Astrophysics Data System (ADS)

Satheeskumaran, S.; Sabrigiriraj, M.

2016-06-01

Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.

Scalable Multiprocessor for High-Speed Computing in Space

NASA Technical Reports Server (NTRS)

Lux, James; Lang, Minh; Nishimoto, Kouji; Clark, Douglas; Stosic, Dorothy; Bachmann, Alex; Wilkinson, William; Steffke, Richard

2004-01-01

A report discusses the continuing development of a scalable multiprocessor computing system for hard real-time applications aboard a spacecraft. "Hard realtime applications" signifies applications, like real-time radar signal processing, in which the data to be processed are generated at "hundreds" of pulses per second, each pulse "requiring" millions of arithmetic operations. In these applications, the digital processors must be tightly integrated with analog instrumentation (e.g., radar equipment), and data input/output must be synchronized with analog instrumentation, controlled to within fractions of a microsecond. The scalable multiprocessor is a cluster of identical commercial-off-the-shelf generic DSP (digital-signal-processing) computers plus generic interface circuits, including analog-to-digital converters, all controlled by software. The processors are computers interconnected by high-speed serial links. Performance can be increased by adding hardware modules and correspondingly modifying the software. Work is distributed among the processors in a parallel or pipeline fashion by means of a flexible master/slave control and timing scheme. Each processor operates under its own local clock; synchronization is achieved by broadcasting master time signals to all the processors, which compute offsets between the master clock and their local clocks.

78 FR 70888 - Need for Agency Approval of a Railroad's Use of Certain Technology That Has Been Previously...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-11-27

... technologies, namely safety-critical processor-based signal or train control systems, including subsystems and... or train control system (including a subsystem or component thereof) that was in service as of June 6... processor-based signal or train control system, subsystem, or component.'' See 49 CFR 236.903. Under Subpart...

A general multiscroll Lorenz system family and its realization via digital signal processors.

PubMed

Yu, Simin; Lü, Jinhu; Tang, Wallace K S; Chen, Guanrong

2006-09-01

This paper proposes a general multiscroll Lorenz system family by introducing a novel parameterized nth-order polynomial transformation. Some basic dynamical behaviors of this general multiscroll Lorenz system family are then investigated, including bifurcations, maximum Lyapunov exponents, and parameters regions. Furthermore, the general multiscroll Lorenz attractors are physically verified by using digital signal processors.

Signal processor for processing ultrasonic receiver signals

DOEpatents

Fasching, George E.

1980-01-01

A signal processor is provided which uses an analog integrating circuit in conjunction with a set of digital counters controlled by a precision clock for sampling timing to provide an improved presentation of an ultrasonic transmitter/receiver signal. The signal is sampled relative to the transmitter trigger signal timing at precise times, the selected number of samples are integrated and the integrated samples are transferred and held for recording on a strip chart recorder or converted to digital form for storage. By integrating multiple samples taken at precisely the same time with respect to the trigger for the ultrasonic transmitter, random noise, which is contained in the ultrasonic receiver signal, is reduced relative to the desired useful signal.

Data processing techniques used with MST radars: A review

NASA Technical Reports Server (NTRS)

Rastogi, P. K.

1983-01-01

The data processing methods used in high power radar probing of the middle atmosphere are examined. The radar acts as a spatial filter on the small scale refractivity fluctuations in the medium. The characteristics of the received signals are related to the statistical properties of these fluctuations. A functional outline of the components of a radar system is given. Most computation intensive tasks are carried out by the processor. The processor computes a statistical function of the received signals, simultaneously for a large number of ranges. The slow fading of atmospheric signals is used to reduce the data input rate to the processor by coherent integration. The inherent range resolution of the radar experiments can be improved significant with the use of pseudonoise phase codes to modulate the transmitted pulses and a corresponding decoding operation on the received signals. Commutability of the decoding and coherent integration operations is used to obtain a significant reduction in computations. The limitations of the processors are outlined. At the next level of data reduction, the measured function is parameterized by a few spectral moments that can be related to physical processes in the medium. The problems encountered in estimating the spectral moments in the presence of strong ground clutter, external interference, and noise are discussed. The graphical and statistical analysis of the inferred parameters are outlined. The requirements for special purpose processors for MST radars are discussed.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

The design of an adaptive predictive coder using a single-chip digital signal processor

NASA Astrophysics Data System (ADS)

Randolph, M. A.

1985-01-01

A speech coding processor architecture design study has been performed in which Texas Instruments TMS32010 has been selected from among three commercially available digital signal processing integrated circuits and evaluated in an implementation study of real-time Adaptive Predictive Coding (APC). The TMS32010 has been compared with AR&T Bell Laboratories DSP I and Nippon Electric Co. PD7720 and was found to be most suitable for a single chip implementation of APC. A preliminary design system based on TMS32010 has been performed, and several of the hardware and software design issues are discussed. Particular attention was paid to the design of an external memory controller which permits rapid sequential access of external RAM. As a result, it has been determined that a compact hardware implementation of the APC algorithm is feasible based of the TSM32010. Originator-supplied keywords include: vocoders, speech compression, adaptive predictive coding, digital signal processing microcomputers, speech processor architectures, and special purpose processor.

Large-N in Volcano Settings: Volcanosri

NASA Astrophysics Data System (ADS)

Lees, J. M.; Song, W.; Xing, G.; Vick, S.; Phillips, D.

2014-12-01

We seek a paradigm shift in the approach we take on volcano monitoring where the compromise from high fidelity to large numbers of sensors is used to increase coverage and resolution. Accessibility, danger and the risk of equipment loss requires that we develop systems that are independent and inexpensive. Furthermore, rather than simply record data on hard disk for later analysis we desire a system that will work autonomously, capitalizing on wireless technology and in field network analysis. To this end we are currently producing a low cost seismic array which will incorporate, at the very basic level, seismological tools for first cut analysis of a volcano in crises mode. At the advanced end we expect to perform tomographic inversions in the network in near real time. Geophone (4 Hz) sensors connected to a low cost recording system will be installed on an active volcano where triggering earthquake location and velocity analysis will take place independent of human interaction. Stations are designed to be inexpensive and possibly disposable. In one of the first implementations the seismic nodes consist of an Arduino Due processor board with an attached Seismic Shield. The Arduino Due processor board contains an Atmel SAM3X8E ARM Cortex-M3 CPU. This 32 bit 84 MHz processor can filter and perform coarse seismic event detection on a 1600 sample signal in fewer than 200 milliseconds. The Seismic Shield contains a GPS module, 900 MHz high power mesh network radio, SD card, seismic amplifier, and 24 bit ADC. External sensors can be attached to either this 24-bit ADC or to the internal multichannel 12 bit ADC contained on the Arduino Due processor board. This allows the node to support attachment of multiple sensors. By utilizing a high-speed 32 bit processor complex signal processing tasks can be performed simultaneously on multiple sensors. Using a 10 W solar panel, second system being developed can run autonomously and collect data on 3 channels at 100Hz for 6 months with the installed 16Gb SD card. Initial designs and test results will be presented and discussed.

Digital Hardware Architecture Implementation

DTIC Science & Technology

1993-02-15

of micro - MOTOROLA 63.7 50MHZ 64 BIT 2092 N/A processors during quarterly re- INTEL 42 50MHz 64 BIT 1092 N/A views and monthly reports. The 186o XP...27 3.2.1 Signal Processor (SP) Analysis...31 3.2.1.11 MasPar Software Statements ........................................................ 32 3.2.2 Data Processor

Apparatus for and method of testing an electrical ground fault circuit interrupt device

DOEpatents

Andrews, L.B.

1998-08-18

An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined. 17 figs.

Apparatus for and method of testing an electrical ground fault circuit interrupt device

DOEpatents

Andrews, Lowell B.

1998-01-01

An apparatus for testing a ground fault circuit interrupt device includes a processor, an input device connected to the processor for receiving input from an operator, a storage media connected to the processor for storing test data, an output device connected to the processor for outputting information corresponding to the test data to the operator, and a calibrated variable load circuit connected between the processor and the ground fault circuit interrupt device. The ground fault circuit interrupt device is configured to trip a corresponding circuit breaker. The processor is configured to receive signals from the calibrated variable load circuit and to process the signals to determine a trip threshold current and/or a trip time. A method of testing the ground fault circuit interrupt device includes a first step of providing an identification for the ground fault circuit interrupt device. Test data is then recorded in accordance with the identification. By comparing test data from an initial test with test data from a subsequent test, a trend of performance for the ground fault circuit interrupt device is determined.

The Advanced Communication Technology Satellite and ISDN

NASA Technical Reports Server (NTRS)

Lowry, Peter A.

1996-01-01

This paper depicts the Advanced Communication Technology Satellite (ACTS) system as a global central office switch. The ground portion of the system is the collection of earth stations or T1-VSAT's (T1 very small aperture terminals). The control software for the T1-VSAT's resides in a single CPU. The software consists of two modules, the modem manager and the call manager. The modem manager (MM) controls the RF modem portion of the T1-VSAT. It processes the orderwires from the satellite or from signaling generated by the call manager (CM). The CM controls the Recom Laboratories MSPs by receiving signaling messages from the stacked MSP shelves ro units and sending appropriate setup commands to them. There are two methods used to setup and process calls in the CM; first by dialing up a circuit using a standard telephone handset or, secondly by using an external processor connected to the CPU's second COM port, by sending and receiving signaling orderwires. It is the use of the external processor which permits the ISDN (Integrated Services Digital Network) Signaling Processor to implement ISDN calls. In August 1993, the initial testing of the ISDN Signaling Processor was carried out at ACTS System Test at Lockheed Marietta, Princeton, NJ using the spacecraft in its test configuration on the ground.

Diurnal measurements with prototype CMOS Omega receivers

NASA Technical Reports Server (NTRS)

Burhans, R. W.

1976-01-01

Diurnal signals from eight omega channels have been monitored at 10.2 KHz for selected station pairs. All eight Omega stations have been received at least 50 percent of the time over a 24 hour period during the month of October 1976. The data presented confirm the expected performance of the CMOS omega sensor processor in being able to digsignals out of a noisy environment. Of particular interest are possibilities for use of antipodal reception phenomena and a need for some ways of correcting for multi-modal propagation effects.

Effects of input processing and type of personal frequency modulation system on speech-recognition performance of adults with cochlear implants.

PubMed

Wolfe, Jace; Schafer, Erin; Parkinson, Aaron; John, Andrew; Hudson, Mary; Wheeler, Julie; Mucci, Angie

2013-01-01

The objective of this study was to compare speech recognition in quiet and in noise for cochlear implant recipients using two different types of personal frequency modulation (FM) systems (directly coupled [direct auditory input] versus induction neckloop) with each of two sound processors (Cochlear Nucleus Freedom versus Cochlear Nucleus 5). Two different experiments were conducted within this study. In both these experiments, mixing of the FM signal within the Freedom processor was implemented via the same scheme used clinically for the Freedom sound processor. In Experiment 1, the aforementioned comparisons were conducted with the Nucleus 5 programmed so that the microphone and FM signals were mixed and then the mixed signals were subjected to autosensitivity control (ASC). In Experiment 2, comparisons between the two FM systems and processors were conducted again with the Nucleus 5 programmed to provide a more complex multistage implementation of ASC during the preprocessing stage. This study was a within-subject, repeated-measures design. Subjects were recruited from the patient population at the Hearts for Hearing Foundation in Oklahoma City, OK. Fifteen subjects participated in Experiment 1, and 16 subjects participated in Experiment 2. Subjects were adults who had used either unilateral or bilateral cochlear implants for at least 1 year. In this experiment, no differences were found in speech recognition in quiet obtained with the two different FM systems or the various sound-processor conditions. With each sound processor, speech recognition in noise was better with the directly coupled direct auditory input system relative to the neckloop system. The multistage ASC processing of the Nucleus 5 sound processor provided better performance than the single-stage approach for the Nucleus 5 and the Nucleus Freedom sound processor. Speech recognition in noise is substantially affected by the type of sound processor, FM system, and implementation of ASC used by a Cochlear implant recipient.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

PubMed

Töreyin, Hakan; Bhatti, Pamela T

2016-06-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis

PubMed Central

Töreyin, Hakan; Bhatti, Pamela T.

2017-01-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm2 and consumes 1.24 mW when supplied with ± 1.6 V. PMID:26800546

VLSI processors for signal detection in SETI

NASA Technical Reports Server (NTRS)

Duluk, J. F.; Linscott, I. R.; Peterson, A. M.; Burr, J.; Ekroot, B.; Twicken, J.

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

VLSI processors for signal detection in SETI.

PubMed

Duluk, J F; Linscott, I R; Peterson, A M; Burr, J; Ekroot, B; Twicken, J

1989-01-01

The objective of the Search for Extraterrestrial Intelligence (SETI) is to locate an artificially created signal coming from a distant star. This is done in two steps: (1) spectral analysis of an incoming radio frequency band, and (2) pattern detection for narrow-band signals. Both steps are computationally expensive and require the development of specially designed computer architectures. To reduce the size and cost of the SETI signal detection machine, two custom VLSI chips are under development. The first chip, the SETI DSP Engine, is used in the spectrum analyzer and is specially designed to compute Discrete Fourier Transforms (DFTs). It is a high-speed arithmetic processor that has two adders, one multiplier-accumulator, and three four-port memories. The second chip is a new type of Content-Addressable Memory. It is the heart of an associative processor that is used for pattern detection. Both chips incorporate many innovative circuits and architectural features.

An ultra low power ECG signal processor design for cardiovascular disease detection.

PubMed

Jain, Sanjeev Kumar; Bhaumik, Basabi

2015-08-01

This paper presents an ultra low power ASIC design based on a new cardiovascular disease diagnostic algorithm. This new algorithm based on forward search is designed for real time ECG signal processing. The algorithm is evaluated for Physionet PTB database from the point of view of cardiovascular disease diagnosis. The failed detection rate of QRS complex peak detection of our algorithm ranges from 0.07% to 0.26% for multi lead ECG signal. The ASIC is designed using 130-nm CMOS low leakage process technology. The area of ASIC is 1.21 mm(2). This ASIC consumes only 96 nW at an operating frequency of 1 kHz with a supply voltage of 0.9 V. Due to ultra low power consumption, our proposed ASIC design is most suitable for energy efficient wearable ECG monitoring devices.

Advances in optical information processing IV; Proceedings of the Meeting, Orlando, FL, Apr. 18-20, 1990

NASA Astrophysics Data System (ADS)

Pape, Dennis R.

1990-09-01

The present conference discusses topics in optical image processing, optical signal processing, acoustooptic spectrum analyzer systems and components, and optical computing. Attention is given to tradeoffs in nonlinearly recorded matched filters, miniature spatial light modulators, detection and classification using higher-order statistics of optical matched filters, rapid traversal of an image data base using binary synthetic discriminant filters, wideband signal processing for emitter location, an acoustooptic processor for autonomous SAR guidance, and sampling of Fresnel transforms. Also discussed are an acoustooptic RF signal-acquisition system, scanning acoustooptic spectrum analyzers, the effects of aberrations on acoustooptic systems, fast optical digital arithmetic processors, information utilization in analog and digital processing, optical processors for smart structures, and a self-organizing neural network for unsupervised learning.

The development of a power spectral density processor for C and L band airborne radar scatterometer sensor systems

NASA Technical Reports Server (NTRS)

Harrison, D. A., III; Chladek, J. T.

1983-01-01

A real-time signal processor was developed for the NASA/JSC L-and C-band airborne radar scatterometer sensor systems. The purpose of the effort was to reduce ground data processing costs. Conversion of two quadrature channels of data (like and cross polarized) was made to obtain Power Spectral Density (PSD) values. A chirp-z transform (CZT) approach was used to filter the Doppler return signal and improved high frequency and angular resolution was realized. The processors have been tested with record signals and excellent results were obtained. CZT filtering can be readily applied to scatterometers operating at other wavelengths by altering the sample frequency. The design of the hardware and software and the results of the performance tests are described in detail.

Dual-mode self-validating resistance/Johnson noise thermometer system

DOEpatents

Shepard, Robert L.; Blalock, Theron V.; Roberts, Michael J.

1993-01-01

A dual-mode Johnson noise and DC resistance thermometer capable of use in control systems where prompt indications of temperature changes and long term accuracy are needed. A resistance-inductance-capacitance (RLC) tuned circuit produces a continuous voltage signal for Johnson noise temperature measurement. The RLC circuit provides a mean-squared noise voltage that depends only on the capacitance used and the temperature of the sensor. The sensor has four leads for simultaneous coupling to a noise signal processor and to a DC resistance signal processor.

Application of convolve-multiply-convolve SAW processor for satellite communications

NASA Technical Reports Server (NTRS)

Lie, Y. S.; Ching, M.

1991-01-01

There is a need for a satellite communications receiver than can perform simultaneous multi-channel processing of single channel per carrier (SCPC) signals originating from various small (mobile or fixed) earth stations. The number of ground users can be as many as 1000. Conventional techniques of simultaneously processing these signals is by employing as many RF-bandpass filters as the number of channels. Consequently, such an approach would result in a bulky receiver, which becomes impractical for satellite applications. A unique approach utilizing a realtime surface acoustic wave (SAW) chirp transform processor is presented. The application of a Convolve-Multiply-Convolve (CMC) chirp transform processor is described. The CMC processor transforms each input channel into a unique timeslot, while preserving its modulation content (in this case QPSK). Subsequently, each channel is individually demodulated without the need of input channel filters. Circuit complexity is significantly reduced, because the output frequency of the CMC processor is common for all input channel frequencies. The results of theoretical analysis and experimental results are in good agreement.

Real-time phase correlation based integrated system for seizure detection

NASA Astrophysics Data System (ADS)

Romaine, James B.; Delgado-Restituto, Manuel; Leñero-Bardallo, Juan A.; Rodríguez-Vázquez, Ángel

2017-05-01

This paper reports a low area, low power, integer-based digital processor for the calculation of phase synchronization between two neural signals. The processor calculates the phase-frequency content of a signal by identifying the specific time periods associated with two consecutive minima. The simplicity of this phase-frequency content identifier allows for the digital processor to utilize only basic digital blocks, such as registers, counters, adders and subtractors, without incorporating any complex multiplication and or division algorithms. In fact, the processor, fabricated in a 0.18μm CMOS process, only occupies an area of 0.0625μm2 and consumes 12.5nW from a 1.2V supply voltage when operated at 128kHz. These low-area, low-power features make the proposed processor a valuable computing element in closed loop neural prosthesis for the treatment of neural diseases, such as epilepsy, or for extracting functional connectivity maps between different recording sites in the brain.

Self-checking self-repairing computer nodes using the mirror processor

NASA Technical Reports Server (NTRS)

Tamir, Yuval

1992-01-01

Circuitry added to fault-tolerant systems for concurrent error deduction usually reduces performance. Using a technique called micro rollback, it is possible to eliminate most of the performance penalty of concurrent error detection. Error detection is performed in parallel with intermodule communication, and erroneous state changes are later undone. The author reports on the design and implementation of a VLSI RISC microprocessor, called the Mirror Processor (MP), which is capable of micro rollback. In order to achieve concurrent error detection, two MP chips operate in lockstep, comparing external signals and a signature of internal signals every clock cycle. If a mismatch is detected, both processors roll back to the beginning of the cycle when the error occurred. In some cases the erroneous state is corrected by copying a value from the fault-free processor to the faulty processor. The architecture, microarchitecture, and VLSI implementation of the MP, emphasizing its error-detection, error-recovery, and self-diagnosis capabilities, are described.

RASSP signal processing architectures

NASA Astrophysics Data System (ADS)

Shirley, Fred; Bassett, Bob; Letellier, J. P.

1995-06-01

The rapid prototyping of application specific signal processors (RASSP) program is an ARPA/tri-service effort to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are specified, designed, documented, manufactured, and supported. The domain of embedded signal processing was chosen because it is important to a variety of military and commercial applications as well as for the challenge it presents in terms of complexity and performance demands. The principal effort is being performed by two major contractors, Lockheed Sanders (Nashua, NH) and Martin Marietta (Camden, NJ). For both, improvements in methodology are to be exercised and refined through the performance of individual 'Demonstration' efforts. The Lockheed Sanders' Demonstration effort is to develop an infrared search and track (IRST) processor. In addition, both contractors' results are being measured by a series of externally administered (by Lincoln Labs) six-month Benchmark programs that measure process improvement as a function of time. The first two Benchmark programs are designing and implementing a synthetic aperture radar (SAR) processor. Our demonstration team is using commercially available VME modules from Mercury Computer to assemble a multiprocessor system scalable from one to hundreds of Intel i860 microprocessors. Custom modules for the sensor interface and display driver are also being developed. This system implements either proprietary or Navy owned algorithms to perform the compute-intensive IRST function in real time in an avionics environment. Our Benchmark team is designing custom modules using commercially available processor ship sets, communication submodules, and reconfigurable logic devices. One of the modules contains multiple vector processors optimized for fast Fourier transform processing. Another module is a fiberoptic interface that accepts high-rate input data from the sensors and provides video-rate output data to a display. This paper discusses the impact of simulation on choosing signal processing algorithms and architectures, drawing from the experiences of the Demonstration and Benchmark inter-company teams at Lockhhed Sanders, Motorola, Hughes, and ISX.

Frequency domain laser velocimeter signal processor: A new signal processing scheme

NASA Technical Reports Server (NTRS)

Meyers, James F.; Clemmons, James I., Jr.

1987-01-01

A new scheme for processing signals from laser velocimeter systems is described. The technique utilizes the capabilities of advanced digital electronics to yield a smart instrument that is able to configure itself, based on the characteristics of the input signals, for optimum measurement accuracy. The signal processor is composed of a high-speed 2-bit transient recorder for signal capture and a combination of adaptive digital filters with energy and/or zero crossing detection signal processing. The system is designed to accept signals with frequencies up to 100 MHz with standard deviations up to 20 percent of the average signal frequency. Results from comparative simulation studies indicate measurement accuracies 2.5 times better than with a high-speed burst counter, from signals with as few as 150 photons per burst.

Compact self-contained electrical-to-optical converter/transmitter

DOEpatents

Seligmann, Daniel A.; Moss, William C.; Valk, Theodore C.; Conder, Alan D.

1995-01-01

A first optical receiver and a second optical receiver are provided for receiving a calibrate command and a power switching signal, respectively, from a remote processor. A third receiver is provided for receiving an analog electrical signal from a transducer. A calibrator generates a reference signal in response to the calibrate command. A combiner mixes the electrical signal with the reference signal to form a calibrated signal. A converter converts the calibrated signal to an optical signal. A transmitter transmits the optical signal to the remote processor. A primary battery supplies power to the calibrator, the combiner, the converter, and the transmitter. An optically-activated switch supplies power to the calibrator, the combiner, the converter, and the transmitter in response to the power switching signal. An auxiliary battery supplies power continuously to the switch.

Ultrasonic Device for Assessing the Quality of a Wire Crimp

NASA Technical Reports Server (NTRS)

Yost, William T. (Inventor); Perey, Daniel F. (Inventor); Cramer, Karl E. (Inventor)

2015-01-01

A system for determining the quality of an electrical wire crimp between a wire and ferrule includes an ultrasonically equipped crimp tool (UECT) configured to transmit an ultrasonic acoustic wave through a wire and ferrule, and a signal processor in communication with the UECT. The signal processor includes a signal transmitting module configured to transmit the ultrasonic acoustic wave via an ultrasonic transducer, signal receiving module configured to receive the ultrasonic acoustic wave after it passes through the wire and ferrule, and a signal analysis module configured to identify signal differences between the ultrasonic waves. The signal analysis module is then configured to compare the signal differences attributable to the wire crimp to a baseline, and to provide an output signal if the signal differences deviate from the baseline.

Plural-wavelength flame detector that discriminates between direct and reflected radiation

NASA Technical Reports Server (NTRS)

Hall, Gregory H. (Inventor); Barnes, Heidi L. (Inventor); Medelius, Pedro J. (Inventor); Simpson, Howard J. (Inventor); Smith, Harvey S. (Inventor)

1997-01-01

A flame detector employs a plurality of wavelength selective radiation detectors and a digital signal processor programmed to analyze each of the detector signals, and determine whether radiation is received directly from a small flame source that warrants generation of an alarm. The processor's algorithm employs a normalized cross-correlation analysis of the detector signals to discriminate between radiation received directly from a flame and radiation received from a reflection of a flame to insure that reflections will not trigger an alarm. In addition, the algorithm employs a Fast Fourier Transform (FFT) frequency spectrum analysis of one of the detector signals to discriminate between flames of different sizes. In a specific application, the detector incorporates two infrared (IR) detectors and one ultraviolet (UV) detector for discriminating between a directly sensed small hydrogen flame, and reflections from a large hydrogen flame. The signals generated by each of the detectors are sampled and digitized for analysis by the digital signal processor, preferably 250 times a second. A sliding time window of approximately 30 seconds of detector data is created using FIFO memories.

A comparison of five methods for monitoring the precision of automated x-ray film processors.

PubMed

Nickoloff, E L; Leo, F; Reese, M

1978-11-01

Five different methods for preparing sensitometric strips used to monitor the precision of automated film processors are compared. A method for determining the sensitivity of each system to processor variations is presented; the observed statistical variability is multiplied by the system response to temperature or chemical changes. Pre-exposed sensitometric strips required the use of accurate densitometers and stringent control limits to be effective. X-ray exposed sensitometric strips demonstrated large variations in the x-ray output (2 omega approximately equal to 8.0%) over a period of one month. Some light sensitometers were capable of detecting +/- 1.0 degrees F (+/- 0.6 degrees C) variations in developer temperature in the processor and/or about 10.0 ml of chemical contamination in the processor. Nevertheless, even the light sensitometers were susceptible to problems, e.g. film emulsion selection, line voltage variations, and latent image fading. Advantages and disadvantages of the various sensitometric methods are discussed.

Digital signal processor and processing method for GPS receivers

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1989-01-01

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

Direct match data flow machine apparatus and process for data driven computing

DOEpatents

Davidson, G.S.; Grafe, V.G.

1997-08-12

A data flow computer and method of computing are disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ``fire`` signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.

Data flow machine for data driven computing

DOEpatents

Davidson, G.S.; Grafe, V.G.

1988-07-22

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information from an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ''fire'' signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.

Data flow machine for data driven computing

DOEpatents

Davidson, George S.; Grafe, Victor G.

1995-01-01

A data flow computer which of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Direct match data flow machine apparatus and process for data driven computing

DOEpatents

Davidson, George S.; Grafe, Victor Gerald

1997-01-01

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status but to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Direct match data flow memory for data driven computing

DOEpatents

Davidson, George S.; Grafe, Victor Gerald

1997-01-01

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

Direct match data flow memory for data driven computing

DOEpatents

Davidson, G.S.; Grafe, V.G.

1997-10-07

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a ``fire`` signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor. 11 figs.

Integrated circuit for SAW and MEMS sensors

NASA Astrophysics Data System (ADS)

Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

2001-11-01

The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

Realization of a single image haze removal system based on DaVinci DM6467T processor

NASA Astrophysics Data System (ADS)

Liu, Zhuang

2014-10-01

Video monitoring system (VMS) has been extensively applied in domains of target recognition, traffic management, remote sensing, auto navigation and national defence. However the VMS has a strong dependence on the weather, for instance, in foggy weather, the quality of images received by the VMS are distinct degraded and the effective range of VMS is also decreased. All in all, the VMS performs terribly in bad weather. Thus the research of fog degraded images enhancement has very high theoretical and practical application value. A design scheme of a fog degraded images enhancement system based on the TI DaVinci processor is presented in this paper. The main function of the referred system is to extract and digital cameras capture images and execute image enhancement processing to obtain a clear image. The processor used in this system is the dual core TI DaVinci DM6467T - ARM@500MHz+DSP@1GH. A MontaVista Linux operating system is running on the ARM subsystem which handles I/O and application processing. The DSP handles signal processing and the results are available to the ARM subsystem in shared memory.The system benefits from the DaVinci processor so that, with lower power cost and smaller volume, it provides the equivalent image processing capability of a X86 computer. The outcome shows that the system in this paper can process images at 25 frames per second on D1 resolution.

Design and Performance of the Astro-E/XRS Signal Processing System

NASA Technical Reports Server (NTRS)

Boyce, Kevin R.; Audley, M. D.; Baker, R. G.; Dumonthier, J. J.; Fujimoto, R.; Gendreau, K. C.; Ishisaki, Y.; Kelley, R. L.; Stahle, C. K.; Szymkowiak, A. E.

1999-01-01

We describe the signal processing system of the Astro-E XRS instrument. The Calorimeter Analog Processor (CAP) provides bias and power for the detectors and amplifies the detector signals by a factor of 20,000. The Calorimeter Digital Processor (CDP) performs the digital processing of the calorimeter signals, detecting X-ray pulses and analyzing them by optimal filtering. We describe the operation of pulse detection, Pulse height analysis. and risetime determination. We also discuss performance, including the three event grades (hi-res mid-res, and low-res). anticoincidence detection, counting rate dependence, and noise rejection.

Electromagnetic versus electrical coupling of personal frequency modulation (FM) receivers to cochlear implant sound processors.

PubMed

Schafer, Erin C; Romine, Denise; Musgrave, Elizabeth; Momin, Sadaf; Huynh, Christy

2013-01-01

Previous research has suggested that electrically coupled frequency modulation (FM) systems substantially improved speech-recognition performance in noise in individuals with cochlear implants (CIs). However, there is limited evidence to support the use of electromagnetically coupled (neck loop) FM receivers with contemporary CI sound processors containing telecoils. The primary goal of this study was to compare speech-recognition performance in noise and subjective ratings of adolescents and adults using one of three contemporary CI sound processors coupled to electromagnetically and electrically coupled FM receivers from Oticon. A repeated-measures design was used to compare speech-recognition performance in noise and subjective ratings without and with the FM systems across three test sessions (Experiment 1) and to compare performance at different FM-gain settings (Experiment 2). Descriptive statistics were used in Experiment 3 to describe output differences measured through a CI sound processor. Experiment 1 included nine adolescents or adults with unilateral or bilateral Advanced Bionics Harmony (n = 3), Cochlear Nucleus 5 (n = 3), and MED-EL OPUS 2 (n = 3) CI sound processors. In Experiment 2, seven of the original nine participants were tested. In Experiment 3, electroacoustic output was measured from a Nucleus 5 sound processor when coupled to the electromagnetically coupled Oticon Arc neck loop and electrically coupled Oticon R2. In Experiment 1, participants completed a field trial with each FM receiver and three test sessions that included speech-recognition performance in noise and a subjective rating scale. In Experiment 2, participants were tested in three receiver-gain conditions. Results in both experiments were analyzed using repeated-measures analysis of variance. Experiment 3 involved electroacoustic-test measures to determine the monitor-earphone output of the CI alone and CI coupled to the two FM receivers. The results in Experiment 1 suggested that both FM receivers provided significantly better speech-recognition performance in noise than the CI alone; however, the electromagnetically coupled receiver provided significantly better speech-recognition performance in noise and better ratings in some situations than the electrically coupled receiver when set to the same gain. In Experiment 2, the primary analysis suggested significantly better speech-recognition performance in noise for the neck-loop versus electrically coupled receiver, but a second analysis, using the best performance across gain settings for each device, revealed no significant differences between the two FM receivers. Experiment 3 revealed monitor-earphone output differences in the Nucleus 5 sound processor for the two FM receivers when set to the +8 setting used in Experiment 1 but equal output when the electrically coupled device was set to a +16 gain setting and the electromagnetically coupled device was set to the +8 gain setting. Individuals with contemporary sound processors may show more favorable speech-recognition performance in noise electromagnetically coupled FM systems (i.e., Oticon Arc), which is most likely related to the input processing and signal processing pathway within the CI sound processor for direct input versus telecoil input. Further research is warranted to replicate these findings with a larger sample size and to develop and validate a more objective approach to fitting FM systems to CI sound processors. American Academy of Audiology.

A low power biomedical signal processor ASIC based on hardware software codesign.

PubMed

Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

2009-01-01

A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

Master/Programmable-Slave Computer

NASA Technical Reports Server (NTRS)

Smaistrla, David; Hall, William A.

1990-01-01

Unique modular computer features compactness, low power, mass storage of data, multiprocessing, and choice of various input/output modes. Master processor communicates with user via usual keyboard and video display terminal. Coordinates operations of as many as 24 slave processors, each dedicated to different experiment. Each slave circuit card includes slave microprocessor and assortment of input/output circuits for communication with external equipment, with master processor, and with other slave processors. Adaptable to industrial process control with selectable degrees of automatic control, automatic and/or manual monitoring, and manual intervention.

Photorefractive Integrators and Correlators

DTIC Science & Technology

1992-12-01

The use of photorefractive crystals as optically addressed time integrating spatial light modulators in acousto - optic signal processing applications...adaptive acousto - optic processor. These results demonstrated the feasibility of using photorefractives for such applications.... Photorefractive, Acousto - optic processor.

A Parallel Framework with Block Matrices of a Discrete Fourier Transform for Vector-Valued Discrete-Time Signals.

PubMed

Soto-Quiros, Pablo

2015-01-01

This paper presents a parallel implementation of a kind of discrete Fourier transform (DFT): the vector-valued DFT. The vector-valued DFT is a novel tool to analyze the spectra of vector-valued discrete-time signals. This parallel implementation is developed in terms of a mathematical framework with a set of block matrix operations. These block matrix operations contribute to analysis, design, and implementation of parallel algorithms in multicore processors. In this work, an implementation and experimental investigation of the mathematical framework are performed using MATLAB with the Parallel Computing Toolbox. We found that there is advantage to use multicore processors and a parallel computing environment to minimize the high execution time. Additionally, speedup increases when the number of logical processors and length of the signal increase.

Compact self-contained electrical-to-optical converter/transmitter

DOEpatents

Seligmann, D.A.; Moss, W.C.; Valk, T.C.; Conder, A.D.

1995-11-21

A first optical receiver and a second optical receiver are provided for receiving a calibrate command and a power switching signal, respectively, from a remote processor. A third receiver is provided for receiving an analog electrical signal from a transducer. A calibrator generates a reference signal in response to the calibrate command. A combiner mixes the electrical signal with the reference signal to form a calibrated signal. A converter converts the calibrated signal to an optical signal. A transmitter transmits the optical signal to the remote processor. A primary battery supplies power to the calibrator, the combiner, the converter, and the transmitter. An optically-activated switch supplies power to the calibrator, the combiner, the converter, and the transmitter in response to the power switching signal. An auxiliary battery supplies power continuously to the switch. 13 figs.

Health Monitor for Multitasking, Safety-Critical, Real-Time Software

NASA Technical Reports Server (NTRS)

Zoerner, Roger

2011-01-01

Health Manager can detect Bad Health prior to a failure occurring by periodically monitoring the application software by looking for code corruption errors, and sanity-checking each critical data value prior to use. A processor s memory can fail and corrupt the software, or the software can accidentally write to the wrong address and overwrite the executing software. This innovation will continuously calculate a checksum of the software load to detect corrupted code. This will allow a system to detect a failure before it happens. This innovation monitors each software task (thread) so that if any task reports "bad health," or does not report to the Health Manager, the system is declared bad. The Health Manager reports overall system health to the outside world by outputting a square wave signal. If the square wave stops, this indicates that system health is bad or hung and cannot report. Either way, "bad health" can be detected, whether caused by an error, corrupted data, or a hung processor. A separate Health Monitor Task is started and run periodically in a loop that starts and stops pending on a semaphore. Each monitored task registers with the Health Manager, which maintains a count for the task. The registering task must indicate if it will run more or less often than the Health Manager. If the task runs more often than the Health Manager, the monitored task calls a health function that increments the count and verifies it did not go over max-count. When the periodic Health Manager runs, it verifies that the count did not go over the max-count and zeroes it. If the task runs less often than the Health Manager, the periodic Health Manager will increment the count. The monitored task zeroes the count, and both the Health Manager and monitored task verify that the count did not go over the max-count.

Electro-optic voltage sensor for sensing voltage in an E-field

DOEpatents

Woods, G.K.; Renak, T.W.

1999-04-06

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages is disclosed. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam`s polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured. 18 figs.

Electro-optical voltage sensor head

DOEpatents

Woods, Gregory K.

1998-01-01

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Electro-optic voltage sensor for sensing voltage in an E-field

DOEpatents

Woods, Gregory K.; Renak, Todd W.

1999-01-01

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam's polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured.

Electro-optical voltage sensor head

DOEpatents

Woods, G.K.

1998-03-24

A miniature electro-optic voltage sensor system capable of accurate operation at high voltages is disclosed. The system employs a transmitter, a sensor disposed adjacent to but out of direct electrical contact with a conductor on which the voltage is to be measured, a detector, and a signal processor. The transmitter produces a beam of electromagnetic radiation which is routed into the sensor where the beam undergoes the Pockels electro-optic effect. The electro-optic effect causes phase shifting in the beam, which is in turn converted to a pair of independent beams, from which the voltage of a system based on its E-field is determined when the two beams are normalized by the signal processor. The sensor converts the beam by splitting the beam in accordance with the axes of the beam`s polarization state (an ellipse whose ellipticity varies between -1 and +1 in proportion to voltage) into at least two AM signals. These AM signals are fed into a signal processor and processed to determine the voltage between a ground conductor and the conductor on which voltage is being measured. 6 figs.

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

A simple integrative method for presenting head-contingent motion parallax and disparity cues on intel x86 processor-based machines.

PubMed

Szatmary, J; Hadani, I; Julesz, B

1997-01-01

Rogers and Graham (1979) developed a system to show that head-movement-contingent motion parallax produces monocular depth perception in random dot patterns. Their display system comprised an oscilloscope driven by function generators or a special graphics board that triggered the X and Y deflection of the raster scan signal. Replication of this system required costly hardware that is no longer on the market. In this paper the Rogers-Graham method is reproduced with an Intel processor based IBM PC compatible machine with no additional hardware cost. An adapted joystick sampled through the standard game-port can serve as a provisional head-movement sensor. Monitor resolution for displaying motion is effectively enhanced 16 times by the use of anti-aliasing, enabling the display of thousands of random dots in real-time with a refresh rate of 60 Hz or above. A color monitor enables the use of the anaglyph method, thus combining stereoscopic and monocular parallax on a single display without the loss of speed. The power of this system is demonstrated by a psychophysical measurement in which subjects nulled head-movement-contingent illusory parallax, evoked by a static stereogram, with real parallax. The amount of real parallax required to null the illusory stereoscopic parallax monotonically increased with disparity.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

NASA Astrophysics Data System (ADS)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Systems and methods for reconfiguring input devices

NASA Technical Reports Server (NTRS)

Lancaster, Jeff (Inventor); De Mers, Robert E. (Inventor)

2012-01-01

A system includes an input device having first and second input members configured to be activated by a user. The input device is configured to generate activation signals associated with activation of the first and second input members, and each of the first and second input members are associated with an input function. A processor is coupled to the input device and configured to receive the activation signals. A memory coupled to the processor, and includes a reconfiguration module configured to store the input functions assigned to the first and second input members and, upon execution of the processor, to reconfigure the input functions assigned to the input members when the first input member is inoperable.

Smart Rehabilitation Garment for posture monitoring.

PubMed

Wang, Q; Chen, W; Timmermans, A A A; Karachristos, C; Martens, J B; Markopoulos, P

2015-08-01

Posture monitoring and correction technologies can support prevention and treatment of spinal pain or can help detect and avoid compensatory movements during the neurological rehabilitation of upper extremities, which can be very important to ensure their effectiveness. We describe the design and development of Smart Rehabilitation Garment (SRG) a wearable system designed to support posture correction. The SRG combines a number of inertial measurement units (IMUs), controlled by an Arduino processor. It provides feedback with vibration on the garment, audible alarm signals and visual instruction through a Bluetooth connected smartphone. We discuss the placement of sensing modules, the garment design, the feedback design and the integration of smart textiles and wearable electronics which aimed at achieving wearability and ease of use. We report on the system's accuracy as compared to optical tracker method.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.; Hubbard, B.

1997-11-04

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a ``hardwired`` processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer. 19 figs.

Method and apparatus for digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Hubbard, Bradley

1997-01-01

A high speed, digitally based, signal processing system which accepts input data from a detector-preamplifier and produces a spectral analysis of the x-rays illuminating the detector. The system achieves high throughputs at low cost by dividing the required digital processing steps between a "hardwired" processor implemented in combinatorial digital logic, which detects the presence of the x-ray signals in the digitized data stream and extracts filtered estimates of their amplitudes, and a programmable digital signal processing computer, which refines the filtered amplitude estimates and bins them to produce the desired spectral analysis. One set of algorithms allow this hybrid system to match the resolution of analog systems while operating at much higher data rates. A second set of algorithms implemented in the processor allow the system to be self calibrating as well. The same processor also handles the interface to an external control computer.

Bi-Fi: an embedded sensor/system architecture for REMOTE biological monitoring.

PubMed

Farshchi, Shahin; Pesterev, Aleksey; Nuyujukian, Paul H; Mody, Istvan; Judy, Jack W

2007-11-01

Wireless-enabled processor modules intended for communicating low-frequency phenomena (i.e., temperature, humidity, and ambient light) have been enabled to acquire and transmit multiple biological signals in real time, which has been achieved by using computationally efficient data acquisition, filtering, and compression algorithms, and interfacing the modules with biological interface hardware. The sensor modules can acquire and transmit raw biological signals at a rate of 32 kb/s, which is near the hardware limit of the modules. Furthermore, onboard signal processing enables one channel, sampled at a rate of 4000 samples/s at 12-bit resolution, to be compressed via adaptive differential-pulse-code modulation (ADPCM) and transmitted in real time. In addition, the sensors can be configured to filter and transmit individual time-referenced "spike" waveforms, or to transmit the spike height and width for alleviating network traffic and increasing battery life. The system is capable of acquiring eight channels of analog signals as well as data via an asynchronous serial connection. A back-end server archives the biological data received via networked gateway sensors, and hosts them to a client application that enables users to browse recorded data. The system also acquires, filters, and transmits oxygen saturation and pulse rate via a commercial-off-the-shelf interface board. The system architecture can be configured for performing real-time nonobtrusive biological monitoring of humans or rodents. This paper demonstrates that low-power, computational, and bandwidth-constrained wireless-enabled platforms can indeed be leveraged for wireless biosignal monitoring.

[Improving speech comprehension using a new cochlear implant speech processor].

PubMed

Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

2009-06-01

The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg sentences in the clinical setting S(0)N(CI), with speech signal at 0 degrees and noise lateral to the CI at 90 degrees . With the convincing findings from our evaluations of this multicenter study cohort, a trial with the Freedom 24 sound processor for all suitable CI users is recommended. For evaluating the benefits of a new processor, the comparative assessment paradigm used in our study design would be considered ideal for use with individual patients.

Hexavalent chromium monitor

DOEpatents

Tao, Shiquan; Winstead, Christopher B.

2005-04-12

A monitor is provided for use in measuring the concentration of hexavalent chromium in a liquid, such as water. The monitor includes a sample cell, a light source, and a photodetector. The sample cell is in the form of a liquid-core waveguide, the sample cell defining an interior core and acting as a receiver for the liquid to be analyzed, the interior surface of the sample cell having a refractive index of less than 1.33. The light source is in communication with a first end of the sample cell for emitting radiation having a wavelength of about and between 350 to 390 nm into the interior core of the waveguide. The photodetector is in communication with a second end of the waveguide for measuring the absorption of the radiation emitted by the light source by the liquid in the sample cell. The monitor may also include a processor electronically coupled to the photodetector for receipt of an absorption signal to determine the concentration of hexavalent chromium in the liquid.

Autonomous Telemetry Collection for Single-Processor Small Satellites

NASA Technical Reports Server (NTRS)

Speer, Dave

2003-01-01

For the Space Technology 5 mission, which is being developed under NASA's New Millennium Program, a single spacecraft processor will be required to do on-board real-time computations and operations associated with attitude control, up-link and down-link communications, science data processing, solid-state recorder management, power switching and battery charge management, experiment data collection, health and status data collection, etc. Much of the health and status information is in analog form, and each of the analog signals must be routed to the input of an analog-to-digital converter, converted to digital form, and then stored in memory. If the micro-operations of the analog data collection process are implemented in software, the processor may use up a lot of time either waiting for the analog signal to settle, waiting for the analog-to-digital conversion to complete, or servicing a large number of high frequency interrupts. In order to off-load a very busy processor, the collection and digitization of all analog spacecraft health and status data will be done autonomously by a field-programmable gate array that can configure the analog signal chain, control the analog-to-digital converter, and store the converted data in memory.

Sequence information signal processor

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1999-01-01

An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

Multichannel signal enhancement

DOEpatents

Lewis, Paul S.

1990-01-01

A mixed adaptive filter is formulated for the signal processing problem where desired a priori signal information is not available. The formulation generates a least squares problem which enables the filter output to be calculated directly from an input data matrix. In one embodiment, a folded processor array enables bidirectional data flow to solve the recursive problem by back substitution without global communications. In another embodiment, a balanced processor array solves the recursive problem by forward elimination through the array. In a particular application to magnetoencephalography, the mixed adaptive filter enables an evoked response to an auditory stimulus to be identified from only a single trial.

Distributed digital signal processors for multi-body structures

NASA Technical Reports Server (NTRS)

Lee, Gordon K.

1990-01-01

Several digital filter designs were investigated which may be used to process sensor data from large space structures and to design digital hardware to implement the distributed signal processing architecture. Several experimental tests articles are available at NASA Langley Research Center to evaluate these designs. A summary of some of the digital filter designs is presented, an evaluation of their characteristics relative to control design is discussed, and candidate hardware microcontroller/microcomputer components are given. Future activities include software evaluation of the digital filter designs and actual hardware inplementation of some of the signal processor algorithms on an experimental testbed at NASA Langley.

Sequence information signal processor for local and global string comparisons

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1997-01-01

A sequence information signal processing integrated circuit chip designed to perform high speed calculation of a dynamic programming algorithm based upon the algorithm defined by Waterman and Smith. The signal processing chip of the present invention is designed to be a building block of a linear systolic array, the performance of which can be increased by connecting additional sequence information signal processing chips to the array. The chip provides a high speed, low cost linear array processor that can locate highly similar global sequences or segments thereof such as contiguous subsequences from two different DNA or protein sequences. The chip is implemented in a preferred embodiment using CMOS VLSI technology to provide the equivalent of about 400,000 transistors or 100,000 gates. Each chip provides 16 processing elements, and is designed to provide 16 bit, two's compliment operation for maximum score precision of between -32,768 and +32,767. It is designed to provide a comparison between sequences as long as 4,194,304 elements without external software and between sequences of unlimited numbers of elements with the aid of external software. Each sequence can be assigned different deletion and insertion weight functions. Each processor is provided with a similarity measure device which is independently variable. Thus, each processor can contribute to maximum value score calculation using a different similarity measure.

Direct RF A-O Processor Spectrum Analyzer.

DTIC Science & Technology

1981-08-01

The primary objective was to develop and demonstrate design approach, along with the associated processing technologies, for a wideband acousto optic Bragg...cell spectrum analyzer. The signal processor used to demonstrate feasibility of the technical approach consisted of two bulk wave acousto optic deflectors

Wireless remote monitoring of critical facilities

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tsai, Hanchung; Anderson, John T.; Liu, Yung Y.

A method, apparatus, and system are provided for monitoring environment parameters of critical facilities. A Remote Area Modular Monitoring (RAMM) apparatus is provided for monitoring environment parameters of critical facilities. The RAMM apparatus includes a battery power supply and a central processor. The RAMM apparatus includes a plurality of sensors monitoring the associated environment parameters and at least one communication module for transmitting one or more monitored environment parameters. The RAMM apparatus is powered by the battery power supply, controlled by the central processor operating a wireless sensor network (WSN) platform when the facility condition is disrupted. The RAMM apparatusmore » includes a housing prepositioned at a strategic location, for example, where a dangerous build-up of contamination and radiation may preclude subsequent manned entrance and surveillance.« less

Through-the-earth radio

DOEpatents

Reagor, David; Vasquez-Dominguez, Jose

2006-12-12

A through-the-earth communication system that includes a digital signal input device; a transmitter operating at a predetermined frequency sufficiently low to effectively penetrate useful distances through-the earth; a data compression circuit that is connected to an encoding processor; an amplifier that receives encoded output from the encoding processor for amplifying the output and transmitting the data to an antenna; and a receiver with an antenna, a band pass filter, a decoding processor, and a data decompressor.

A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

NASA Astrophysics Data System (ADS)

Veiga, Alejandro; Grunfeld, Christian

2016-02-01

The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

Reactor Operations Monitoring System

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hart, M.M.

1989-01-01

The Reactor Operations Monitoring System (ROMS) is a VME based, parallel processor data acquisition and safety action system designed by the Equipment Engineering Section and Reactor Engineering Department of the Savannah River Site. The ROMS will be analyzing over 8 million signal samples per minute. Sixty-eight microprocessors are used in the ROMS in order to achieve a real-time data analysis. The ROMS is composed of multiple computer subsystems. Four redundant computer subsystems monitor 600 temperatures with 2400 thermocouples. Two computer subsystems share the monitoring of 600 reactor coolant flows. Additional computer subsystems are dedicated to monitoring 400 signals from assortedmore » process sensors. Data from these computer subsystems are transferred to two redundant process display computer subsystems which present process information to reactor operators and to reactor control computers. The ROMS is also designed to carry out safety functions based on its analysis of process data. The safety functions include initiating a reactor scram (shutdown), the injection of neutron poison, and the loadshed of selected equipment. A complete development Reactor Operations Monitoring System has been built. It is located in the Program Development Center at the Savannah River Site and is currently being used by the Reactor Engineering Department in software development. The Equipment Engineering Section is designing and fabricating the process interface hardware. Upon proof of hardware and design concept, orders will be placed for the final five systems located in the three reactor areas, the reactor training simulator, and the hardware maintenance center.« less

SETI prototype system for NASA's Sky Survey microwave observing project - A progress report

NASA Technical Reports Server (NTRS)

Klein, M. J.; Gulkis, S.; Wilck, H. C.

1990-01-01

Two complementary search strategies, a Targeted Search and a Sky Survey, are part of NASA's SETI microwave observing project scheduled to begin in October of 1992. The current progress in the development of hardware and software elements of the JPL Sky Survey data processing system are presented. While the Targeted Search stresses sensitivity allowing the detection of either continuous or pulsed signals over the 1-3 GHz frequency range, the Sky Survey gives up sensitivity to survey the 99 percent of the sky that is not covered by the Targeted Search. The Sky Survey spans a larger frequency range from 1-10 GHz. The two searches will deploy special-purpose digital signal processing equipment designed and built to automate the observing and data processing activities. A two-million channel digital wideband spectrum analyzer and a signal processor system will serve as a prototype for the SETI Sky Survey processor. The design will permit future expansion to meet the SETI requirement that the processor concurrently search for left and right circularly polarized signals.

NCC Simulation Model: Simulating the operations of the network control center, phase 2

NASA Technical Reports Server (NTRS)

Benjamin, Norman M.; Paul, Arthur S.; Gill, Tepper L.

1992-01-01

The simulation of the network control center (NCC) is in the second phase of development. This phase seeks to further develop the work performed in phase one. Phase one concentrated on the computer systems and interconnecting network. The focus of phase two will be the implementation of the network message dialogues and the resources controlled by the NCC. These resources are requested, initiated, monitored and analyzed via network messages. In the NCC network messages are presented in the form of packets that are routed across the network. These packets are generated, encoded, decoded and processed by the network host processors that generate and service the message traffic on the network that connects these hosts. As a result, the message traffic is used to characterize the work done by the NCC and the connected network. Phase one of the model development represented the NCC as a network of bi-directional single server queues and message generating sources. The generators represented the external segment processors. The served based queues represented the host processors. The NCC model consists of the internal and external processors which generate message traffic on the network that links these hosts. To fully realize the objective of phase two it is necessary to identify and model the processes in each internal processor. These processes live in the operating system of the internal host computers and handle tasks such as high speed message exchanging, ISN and NFE interface, event monitoring, network monitoring, and message logging. Inter process communication is achieved through the operating system facilities. The overall performance of the host is determined by its ability to service messages generated by both internal and external processors.

Data processing with microcode designed with source coding

DOEpatents

McCoy, James A; Morrison, Steven E

2013-05-07

Programming for a data processor to execute a data processing application is provided using microcode source code. The microcode source code is assembled to produce microcode that includes digital microcode instructions with which to signal the data processor to execute the data processing application.

EGR distribution and fluctuation probe based on CO2 measurements

DOEpatents

Parks, II, James E.; Partridge, Jr., William P.; Yoo, Ji Hyung

2015-06-30

A diagnostic system having a laser, an EGR probe, a detector and a processor. The laser may be a swept-.lamda. laser having a sweep range including a significant CO.sub.2 feature and substantially zero absorption regions. The sweep range may extend from about 2.708 .mu.m to about 2.7085 .mu.m. The processor may determine CO.sub.2 concentration as a function of the detector output signal. The processor may normalize the output signal as a function of the zero absorption regions. The system may include a plurality of EGR probes receiving light from a single laser. The system may include a separate detector for each probe. Alternatively, the system may combine the light returning from the different probes into a composite beam that is measured by a single detector. A unique modulation characteristic may be introduced into each light beam before combination so that the processor can discriminate between them in the composite beam.

Use phase signals to promote lifetime extension for Windows PCs.

PubMed

Hickey, Stewart; Fitzpatrick, Colin; O'Connell, Maurice; Johnson, Michael

2009-04-01

This paper proposes a signaling methodology for personal computers. Signaling may be viewed as an ecodesign strategy that can positively influence the consumer to consumer (C2C) market process. A number of parameters are identified that can provide the basis for signal implementation. These include operating time, operating temperature, operating voltage, power cycle counts, hard disk drive (HDD) self-monitoring, and reporting technology (SMART) attributes and operating system (OS) event information. All these parameters are currently attainable or derivable via embedded technologies in modern desktop systems. A case study detailing a technical implementation of how the development of signals can be achieved in personal computers that incorporate Microsoft Windows operating systems is presented. Collation of lifetime temperature data from a system processor is demonstrated as a possible means of characterizing a usage profile for a desktop system. In addition, event log data is utilized for devising signals indicative of OS quality. The provision of lifetime usage data in the form of intuitive signals indicative of both hardware and software quality can in conjunction with consumer education facilitate an optimal remarketing strategy for used systems. This implementation requires no additional hardware.

Compact ion chamber based neutron detector

DOEpatents

Derzon, Mark S.; Galambos, Paul C.; Renzi, Ronald F.

2015-10-27

A directional neutron detector has an ion chamber formed in a dielectric material; a signal electrode and a ground electrode formed in the ion chamber; a neutron absorbing material filling the ion chamber; readout circuitry which is electrically coupled to the signal and ground electrodes; and a signal processor electrically coupled to the readout circuitry. The ion chamber has a pair of substantially planar electrode surfaces. The chamber pressure of the neutron absorbing material is selected such that the reaction particle ion trail length for neutrons absorbed by the neutron absorbing material is equal to or less than the distance between the electrode surfaces. The signal processor is adapted to determine a path angle for each absorbed neutron based on the rise time of the corresponding pulse in a time-varying detector signal.

Real Time Phase Noise Meter Based on a Digital Signal Processor

NASA Technical Reports Server (NTRS)

Angrisani, Leopoldo; D'Arco, Mauro; Greenhall, Charles A.; Schiano Lo Morille, Rosario

2006-01-01

A digital signal-processing meter for phase noise measurement on sinusoidal signals is dealt with. It enlists a special hardware architecture, made up of a core digital signal processor connected to a data acquisition board, and takes advantage of a quadrature demodulation-based measurement scheme, already proposed by the authors. Thanks to an efficient measurement process and an optimized implementation of its fundamental stages, the proposed meter succeeds in exploiting all hardware resources in such an effective way as to gain high performance and real-time operation. For input frequencies up to some hundreds of kilohertz, the meter is capable both of updating phase noise power spectrum while seamlessly capturing the analyzed signal into its memory, and granting as good frequency resolution as few units of hertz.

Method and system to synchronize acoustic therapy with ultrasound imaging

NASA Technical Reports Server (NTRS)

Hossack, James (Inventor); Owen, Neil (Inventor); Bailey, Michael R. (Inventor)

2009-01-01

Interference in ultrasound imaging when used in connection with high intensity focused ultrasound (HIFU) is avoided by employing a synchronization signal to control the HIFU signal. Unless the timing of the HIFU transducer is controlled, its output will substantially overwhelm the signal produced by ultrasound imaging system and obscure the image it produces. The synchronization signal employed to control the HIFU transducer is obtained without requiring modification of the ultrasound imaging system. Signals corresponding to scattered ultrasound imaging waves are collected using either the HIFU transducer or a dedicated receiver. A synchronization processor manipulates the scattered ultrasound imaging signals to achieve the synchronization signal, which is then used to control the HIFU bursts so as to substantially reduce or eliminate HIFU interference in the ultrasound image. The synchronization processor can alternatively be implemented using a computing device or an application-specific circuit.

The application of charge-coupled device processors in automatic-control systems

NASA Technical Reports Server (NTRS)

Mcvey, E. S.; Parrish, E. A., Jr.

1977-01-01

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

Real-time portable system for fabric defect detection using an ARM processor

NASA Astrophysics Data System (ADS)

Fernandez-Gallego, J. A.; Yañez-Puentes, J. P.; Ortiz-Jaramillo, B.; Alvarez, J.; Orjuela-Vargas, S. A.; Philips, W.

2012-06-01

Modern textile industry seeks to produce textiles as little defective as possible since the presence of defects can decrease the final price of products from 45% to 65%. Automated visual inspection (AVI) systems, based on image analysis, have become an important alternative for replacing traditional inspections methods that involve human tasks. An AVI system gives the advantage of repeatability when implemented within defined constrains, offering more objective and reliable results for particular tasks than human inspection. Costs of automated inspection systems development can be reduced using modular solutions with embedded systems, in which an important advantage is the low energy consumption. Among the possibilities for developing embedded systems, the ARM processor has been explored for acquisition, monitoring and simple signal processing tasks. In a recent approach we have explored the use of the ARM processor for defects detection by implementing the wavelet transform. However, the computation speed of the preprocessing was not yet sufficient for real time applications. In this approach we significantly improve the preprocessing speed of the algorithm, by optimizing matrix operations, such that it is adequate for a real time application. The system was tested for defect detection using different defect types. The paper is focused in giving a detailed description of the basis of the algorithm implementation, such that other algorithms may use of the ARM operations for fast implementations.

Real-time vibration measurement by a spatial phase-shifting technique with a tilted holographic interferogram.

PubMed

Nakadate, S; Isshiki, M

1997-01-01

Real-time vibration measurement by a tilted holographic interferogram is presented that utilizes the real-time digital fringe processor of a video signal. Three intensity data sampled at every one-third of the fringe spacing of the tilted fringes are used to calculate the modulation term of the fringe that is a function of a vibration amplitude. A three-dimensional lookup table performs the calculation in a TV repetition rate to give a new fringe profile that contours the vibration amplitude. Vibration modes at the resonant frequencies of a flat speaker were displayed on a monitor as changing the exciting frequency of vibration.

SAR calibration technology review

NASA Technical Reports Server (NTRS)

Walker, J. L.; Larson, R. W.

1981-01-01

Synthetic Aperture Radar (SAR) calibration technology including a general description of the primary calibration techniques and some of the factors which affect the performance of calibrated SAR systems are reviewed. The use of reference reflectors for measurement of the total system transfer function along with an on-board calibration signal generator for monitoring the temporal variations of the receiver to processor output is a practical approach for SAR calibration. However, preliminary error analysis and previous experimental measurements indicate that reflectivity measurement accuracies of better than 3 dB will be difficult to achieve. This is not adequate for many applications and, therefore, improved end-to-end SAR calibration techniques are required.

NbN A/D Conversion of IR Focal Plane Sensor Signal at 10 K

NASA Technical Reports Server (NTRS)

Eaton, L.; Durand, D.; Sandell, R.; Spargo, J.; Krabach, T.

1994-01-01

We are implementing a 12 bit SFQ counting ADC with parallel-to-serial readout using our established 10 K NbN capability. This circuit provides a key element of the analog signal processor (ASP) used in large infrared focal plane arrays. The circuit processes the signal data stream from a Si:As BIB detector array. A 10 mega samples per second (MSPS) pixel data stream flows from the chip at a 120 megabit bit rate in a format that is compatible with other superconductive time dependent processor (TDP) circuits being developed. We will discuss our planned ASP demonstration, the circuit design, and test results.

OPS MCC level B/C formulation requirements: Area targets and space volumes processor

NASA Technical Reports Server (NTRS)

Bishop, M. J., Jr.

1979-01-01

The level B/C mathematical specifications for the area targets and space volumes processor (ATSVP) are described. The processor is designed to compute the acquisition-of-signal (AOS) and loss-of-signal (LOS) times for area targets and space volumes. The characteristics of the area targets and space volumes are given. The mathematical equations necessary to determine whether the spacecraft lies within the area target or space volume are given. These equations provide a detailed model of the target geometry. A semianalytical technique for predicting the AOS and LOS time periods is disucssed. This technique was designed to bound the actual visibility period using a simplified target geometry model and unperturbed orbital motion. Functional overview of the ATSVP is presented and it's detailed logic flow is described.

On the efficacy of using the transfer-controlled procedure during periods of STP processor overloads in SS7 networks

NASA Astrophysics Data System (ADS)

Rumsewicz, Michael

1994-04-01

In this paper, we examine call completion performance, rather than message throughput, in a Common Channel Signaling network in which the processing resources, and not transmission resources, of a Signaling Transfer Point (STP) are overloaded. Specifically, we perform a transient analysis, via simulation, of a network consisting of a single Central Processor-based STP connecting many local exchanges. We consider the efficacy of using the Transfer Controlled (TFC) procedure when the network call attempt rate exceeds the processing capability of the STP. We find the following: (1) the success of the control depends critically on the rate at which TFC's are sent; (2) use of the TFC procedure in theevent of processor overload can provide reasonable call completion rates.

Airborne optical tracking control system design study

NASA Astrophysics Data System (ADS)

1992-09-01

The Kestrel LOS Tracking Program involves the development of a computer and algorithms for use in passive tracking of airborne targets from a high altitude balloon platform. The computer receivers track error signals from a video tracker connected to one of the imaging sensors. In addition, an on-board IRU (gyro), accelerometers, a magnetometer, and a two-axis inclinometer provide inputs which are used for initial acquisitions and course and fine tracking. Signals received by the control processor from the video tracker, IRU, accelerometers, magnetometer, and inclinometer are utilized by the control processor to generate drive signals for the payload azimuth drive, the Gimballed Mirror System (GMS), and the Fast Steering Mirror (FSM). The hardware which will be procured under the LOS tracking activity is the Controls Processor (CP), the IRU, and the FSM. The performance specifications for the GMS and the payload canister azimuth driver are established by the LOS tracking design team in an effort to achieve a tracking jitter of less than 3 micro-rad, 1 sigma for one axis.

76 FR 20626 - Submission for OMB Review; Comment Request

Federal Register 2010, 2011, 2012, 2013, 2014

2011-04-13

... communities and monitors the ``economic stability for harvesters, processors, and coastal communities.'' The... (BSAI) Crab Economic Data Reports. OMB Control Number: 0648-0518. Form Number(s): NA. Type of Request...: 132. Average Hours per Response: Catcher vessel and catcher/processor economic data reports (EDRs), 37...

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

DOE Office of Scientific and Technical Information (OSTI.GOV)

Barhen, Jacob; Kerekes, Ryan A; ST Charles, Jesse Lee

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlationmore » processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core performs the matrix-vector multiplications, where the nominal matrix size is 256x256. The system clock is 125MHz. At each clock cycle, 128K multiply-and-add operations per second (OPS) are carried out, which yields a peak performance of 16 TeraOPS. IBM Cell Broadband Engine. The Cell processor is the extraordinary resulting product of 5 years of sustained, intensive R&D collaboration (involving over $400M investment) between IBM, Sony, and Toshiba. Its architecture comprises one multithreaded 64-bit PowerPC processor element (PPE) with VMX capabilities and two levels of globally coherent cache, and 8 synergistic processor elements (SPEs). Each SPE consists of a processor (SPU) designed for streaming workloads, local memory, and a globally coherent direct memory access (DMA) engine. Computations are performed in 128-bit wide single instruction multiple data streams (SIMD). An integrated high-bandwidth element interconnect bus (EIB) connects the nine processors and their ports to external memory and to system I/O. The Applied Software Engineering Research (ASER) Group at the ORNL is applying the Cell to a variety of text and image analysis applications. Research on Cell-equipped PlayStation3 (PS3) consoles has led to the development of a correlation-based image recognition engine that enables a single PS3 to process images at more than 10X the speed of state-of-the-art single-core processors. NVIDIA Graphics Processing Units. The ASER group is also employing the latest NVIDIA graphical processing units (GPUs) to accelerate clustering of thousands of text documents using recently developed clustering algorithms such as document flocking and affinity propagation.« less

A seismic signal processor suitable for use with the NOAA/GOES satellite data collection system

NASA Technical Reports Server (NTRS)

Webster, W. J., Jr.; Miller, W. H.; Whitley, R.; Allenby, R. J.; Dennison, R. T.

1981-01-01

Because of the high data-rate requirements, a practical system capable of collecting seismic information in the field and relaying it, via satellite, to a central collection point is not yet available. A seismic signal processor has been developed and tested for use with the NOAA/GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of environmental noise and other non-seismic signals and that, with the use of solid state buffer memories, data can be acquired in many swarm situations. The design of a complete field data collection platform is discussed based on the prototype evaluation.

Portable laser speckle perfusion imaging system based on digital signal processor.

PubMed

Tang, Xuejun; Feng, Nengyun; Sun, Xiaoli; Li, Pengcheng; Luo, Qingming

2010-12-01

The ability to monitor blood flow in vivo is of major importance in clinical diagnosis and in basic researches of life science. As a noninvasive full-field technique without the need of scanning, laser speckle contrast imaging (LSCI) is widely used to study blood flow with high spatial and temporal resolution. Current LSCI systems are based on personal computers for image processing with large size, which potentially limit the widespread clinical utility. The need for portable laser speckle contrast imaging system that does not compromise processing efficiency is crucial in clinical diagnosis. However, the processing of laser speckle contrast images is time-consuming due to the heavy calculation for enormous high-resolution image data. To address this problem, a portable laser speckle perfusion imaging system based on digital signal processor (DSP) and the algorithm which is suitable for DSP is described. With highly integrated DSP and the algorithm, we have markedly reduced the size and weight of the system as well as its energy consumption while preserving the high processing speed. In vivo experiments demonstrate that our portable laser speckle perfusion imaging system can obtain blood flow images at 25 frames per second with the resolution of 640 × 480 pixels. The portable and lightweight features make it capable of being adapted to a wide variety of application areas such as research laboratory, operating room, ambulance, and even disaster site.

The GF-3 SAR Data Processor

PubMed Central

Han, Bing; Ding, Chibiao; Zhong, Lihua; Liu, Jiayin; Qiu, Xiaolan; Hu, Yuxin; Lei, Bin

2018-01-01

The Gaofen-3 (GF-3) data processor was developed as a workstation-based GF-3 synthetic aperture radar (SAR) data processing system. The processor consists of two vital subsystems of the GF-3 ground segment, which are referred to as data ingesting subsystem (DIS) and product generation subsystem (PGS). The primary purpose of DIS is to record and catalogue GF-3 raw data with a transferring format, and PGS is to produce slant range or geocoded imagery from the signal data. This paper presents a brief introduction of the GF-3 data processor, including descriptions of the system architecture, the processing algorithms and its output format. PMID:29534464

A novel speech-processing strategy incorporating tonal information for cochlear implants.

PubMed

Lan, N; Nie, K B; Gao, S K; Zeng, F G

2004-05-01

Good performance in cochlear implant users depends in large part on the ability of a speech processor to effectively decompose speech signals into multiple channels of narrow-band electrical pulses for stimulation of the auditory nerve. Speech processors that extract only envelopes of the narrow-band signals (e.g., the continuous interleaved sampling (CIS) processor) may not provide sufficient information to encode the tonal cues in languages such as Chinese. To improve the performance in cochlear implant users who speak tonal language, we proposed and developed a novel speech-processing strategy, which extracted both the envelopes of the narrow-band signals and the fundamental frequency (F0) of the speech signal, and used them to modulate both the amplitude and the frequency of the electrical pulses delivered to stimulation electrodes. We developed an algorithm to extract the fundatmental frequency and identified the general patterns of pitch variations of four typical tones in Chinese speech. The effectiveness of the extraction algorithm was verified with an artificial neural network that recognized the tonal patterns from the extracted F0 information. We then compared the novel strategy with the envelope-extraction CIS strategy in human subjects with normal hearing. The novel strategy produced significant improvement in perception of Chinese tones, phrases, and sentences. This novel processor with dynamic modulation of both frequency and amplitude is encouraging for the design of a cochlear implant device for sensorineurally deaf patients who speak tonal languages.

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

NASA Technical Reports Server (NTRS)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

Automatic film processors' quality control test in Greek military hospitals.

PubMed

Lymberis, C; Efstathopoulos, E P; Manetou, A; Poudridis, G

1993-04-01

The two major military radiology installations (Athens, Greece) using a total of 15 automatic film processors were assessed using the 21-step-wedge method. The results of quality control in all these processors are presented. The parameters measured under actual working conditions were base and fog, contrast and speed. Base and fog as well as speed displayed large variations with average values generally higher than acceptable, whilst contrast displayed greater stability. Developer temperature was measured daily during the test and was found to be outside the film manufacturers' recommended limits in nine of the 15 processors. In only one processor did film passing time vary on an every day basis and this was due to maloperation. Developer pH test was not part of the daily monitoring service being performed every 5 days for each film processor and found to be in the range 9-12; 10 of the 15 processors presented pH values outside the limits specified by the film manufacturers.

Pausing and activating thread state upon pin assertion by external logic monitoring polling loop exit time condition

DOEpatents

Chen, Dong; Giampapa, Mark; Heidelberger, Philip; Ohmacht, Martin; Satterfield, David L; Steinmacher-Burow, Burkhard; Sugavanam, Krishnan

2013-05-21

A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

Smart Sensor Network for Aircraft Corrosion Monitoring

DTIC Science & Technology

2010-02-01

Network Elements – Hub, Network capable application processor ( NCAP ) – Node, Smart transducer interface module (STIM)  Corrosion Sensing and...software Transducer software Network Protocol 1451.2 1451.3 1451.5 1451.6 1451.7 I/O Node -processor Power TEDS Smart Sensor Hub ( NCAP ) IEEE 1451.0 and

Apparatus and method for processing Korotkov sounds. [for blood pressure measurement

NASA Technical Reports Server (NTRS)

Golden, D. P., Jr.; Hoffler, G. W.; Wolthuis, R. A. (Inventor)

1974-01-01

A Korotkov sound processor, used in a noninvasive automatic blood measuring system where the brachial artery is occluded by an inflatable cuff, is disclosed. The Korotkoff sound associated with the systolic event is determined when the ratio of the absolute value of a voltage signal, representing Korotkov sounds in the range of 18 to 26 Hz to a maximum absolute peak value of the unfiltered signals, first equals or exceeds a value of 0.45. Korotkov sound associated with the diastolic event is determined when a ratio of the voltage signal of the Korotkov sounds in the range of 40 to 60 Hz to the absolute peak value of such signals within a single measurement cycle first falls below a value of 0.17. The processor signals the occurrence of the systolic and diastolic events and these signals can be used to control a recorder to record pressure values for these events.

Missile signal processing common computer architecture for rapid technology upgrade

NASA Astrophysics Data System (ADS)

Rabinkin, Daniel V.; Rutledge, Edward; Monticciolo, Paul

2004-10-01

Interceptor missiles process IR images to locate an intended target and guide the interceptor towards it. Signal processing requirements have increased as the sensor bandwidth increases and interceptors operate against more sophisticated targets. A typical interceptor signal processing chain is comprised of two parts. Front-end video processing operates on all pixels of the image and performs such operations as non-uniformity correction (NUC), image stabilization, frame integration and detection. Back-end target processing, which tracks and classifies targets detected in the image, performs such algorithms as Kalman tracking, spectral feature extraction and target discrimination. In the past, video processing was implemented using ASIC components or FPGAs because computation requirements exceeded the throughput of general-purpose processors. Target processing was performed using hybrid architectures that included ASICs, DSPs and general-purpose processors. The resulting systems tended to be function-specific, and required custom software development. They were developed using non-integrated toolsets and test equipment was developed along with the processor platform. The lifespan of a system utilizing the signal processing platform often spans decades, while the specialized nature of processor hardware and software makes it difficult and costly to upgrade. As a result, the signal processing systems often run on outdated technology, algorithms are difficult to update, and system effectiveness is impaired by the inability to rapidly respond to new threats. A new design approach is made possible three developments; Moore's Law - driven improvement in computational throughput; a newly introduced vector computing capability in general purpose processors; and a modern set of open interface software standards. Today's multiprocessor commercial-off-the-shelf (COTS) platforms have sufficient throughput to support interceptor signal processing requirements. This application may be programmed under existing real-time operating systems using parallel processing software libraries, resulting in highly portable code that can be rapidly migrated to new platforms as processor technology evolves. Use of standardized development tools and 3rd party software upgrades are enabled as well as rapid upgrade of processing components as improved algorithms are developed. The resulting weapon system will have a superior processing capability over a custom approach at the time of deployment as a result of a shorter development cycles and use of newer technology. The signal processing computer may be upgraded over the lifecycle of the weapon system, and can migrate between weapon system variants enabled by modification simplicity. This paper presents a reference design using the new approach that utilizes an Altivec PowerPC parallel COTS platform. It uses a VxWorks-based real-time operating system (RTOS), and application code developed using an efficient parallel vector library (PVL). A quantification of computing requirements and demonstration of interceptor algorithm operating on this real-time platform are provided.

Modulated FT- Raman Fiber-Optic Spectroscopy: A technique for Remotely Monitoring High-Temperature Reactions in Real-Time

NASA Technical Reports Server (NTRS)

Cooper, John B.; Wise, Kent L.; Jensen, Brian J.

1997-01-01

A modification to a commercial FT-Raman spectrometer is presented for the elimination of thermal backgrounds in FT-Raman spectra. The modification involves the use of a mechanical chopper to modulate the CW laser, remote collection of the signal via fiber optics, and connection of a dual-phase digital signal processor lock-in amplifier between the detector and the spectrometer's collection electronics to demodulate and filter the optical signals. The resulting modulated FT-Raman fiber-optic spectrometer is capable of completely eliminating thermal backgrounds at temperatures exceeding 370 C. In addition, the signal/noise of generated Raman spectra is greater than for spectra collected with the conventional FT-Raman under identical conditions and incident laser power. This is true for both room-temperature and hot samples. The method allows collection of data using preexisting spectrometer software. The total cost of the modification (excluding fiber optics) is approximately $3000 and requires less than 2 h to implement. This is the first report of Fr-Raman spectra collected at temperatures in excess of 300 C in the absence of thermal backgrounds.

Audio signal processor

NASA Technical Reports Server (NTRS)

Hymer, R. L.

1970-01-01

System provides automatic volume control for an audio amplifier or a voice communication system without introducing noise surges during pauses in the input, and without losing the initial signal when the input resumes.

Smoke detection

DOEpatents

Warmack, Robert J. Bruce; Wolf, Dennis A.; Frank, Steven Shane

2016-09-06

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDA training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.

Smoke detection

DOEpatents

Warmack, Robert J. Bruce; Wolf, Dennis A.; Frank, Steven Shane

2015-10-27

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDA training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.

A Framework for a Quality Control System for Vendor/Processor Contracts.

ERIC Educational Resources Information Center

Advanced Technology, Inc., Reston, VA.

A framework for monitoring quality control (QC) of processor contracts administered by the Department of Education's Office of Student Financial Assistance (OSFA) is presented and applied to the Pell Grant program. Guidelines for establishing QC measures and standards are included, and the uses of a sampling procedure in the QC system are…

Satellite on-board real-time SAR processor prototype

NASA Astrophysics Data System (ADS)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and size are reviewed.

Optical transient monitor

NASA Astrophysics Data System (ADS)

Bernas, Martin; Páta, Petr; Hudec, René; Soldán, Jan; Rezek, Tomáš; Castro-Tirado, Alberto J.

1998-05-01

Although there are several optical GRB follow-up systems in operation and/or in development, some of them with a very short response time, they will never be able to provide true simultaneous (no delay) and pre-burst optical data for GRBs. We report on the development and tests of a monitoring experiment expected to be put into test operation in 1998. The system should detect Optical Transients down to mag 6-7 (few seconds duration assumed) over a wide field of view. The system is based on the double CCD wide-field cameras ST8. For the real time evaluation of the signal from both cameras, two TMS 320C40 processors are used. Using two channels differing in spectral sensitivity and processing of temporal sequence of images allows us to eliminate man-made objects and defects of the CCD electronics. The system is controlled by a standard PC computer.

Laser Speckle Imaging of Cerebral Blood Flow

NASA Astrophysics Data System (ADS)

Luo, Qingming; Jiang, Chao; Li, Pengcheng; Cheng, Haiying; Wang, Zhen; Wang, Zheng; Tuchin, Valery V.

Monitoring the spatio-temporal characteristics of cerebral blood flow (CBF) is crucial for studying the normal and pathophysiologic conditions of brain metabolism. By illuminating the cortex with laser light and imaging the resulting speckle pattern, relative CBF images with tens of microns spatial and millisecond temporal resolution can be obtained. In this chapter, a laser speckle imaging (LSI) method for monitoring dynamic, high-resolution CBF is introduced. To improve the spatial resolution of current LSI, a modified LSI method is proposed. To accelerate the speed of data processing, three LSI data processing frameworks based on graphics processing unit (GPU), digital signal processor (DSP), and field-programmable gate array (FPGA) are also presented. Applications for detecting the changes in local CBF induced by sensory stimulation and thermal stimulation, the influence of a chemical agent on CBF, and the influence of acute hyperglycemia following cortical spreading depression on CBF are given.

Development of a real time bistatic radar receiver using signals of opportunity

NASA Astrophysics Data System (ADS)

Rainville, Nicholas

Passive bistatic radar remote sensing offers a novel method of monitoring the Earth's surface by observing reflected signals of opportunity. The Global Positioning System (GPS) has been used as a source of signals for these observations and the scattering properties of GPS signals from rough surfaces are well understood. Recent work has extended GPS signal reflection observations and scattering models to include communications signals such as XM radio signals. However the communication signal reflectometry experiments to date have relied on collecting raw, high data-rate signals which are then post-processed after the end of the experiment. This thesis describes the development of a communication signal bistatic radar receiver which computes a real time correlation waveform, which can be used to retrieve measurements of the Earth's surface. The real time bistatic receiver greatly reduces the quantity of data that must be stored to perform the remote sensing measurements, as well as offering immediate feedback. This expands the applications for the receiver to include space and bandwidth limited platforms such as aircraft and satellites. It also makes possible the adjustment of flight plans to the observed conditions. This real time receiver required the development of an FGPA based signal processor, along with the integration of commercial Satellite Digital Audio Radio System (SDARS) components. The resulting device was tested both in a lab environment as well on NOAA WP-3D and NASA WB-57 aircraft.

Health Monitoring of a Satellite System

NASA Technical Reports Server (NTRS)

Chen, Robert H.; Ng, Hok K.; Speyer, Jason L.; Guntur, Lokeshkumar S.; Carpenter, Russell

2004-01-01

A health monitoring system based on analytical redundancy is developed for satellites on elliptical orbits. First, the dynamics of the satellite including orbital mechanics and attitude dynamics is modelled as a periodic system. Then, periodic fault detection filters are designed to detect and identify the satellite's actuator and sensor faults. In addition, parity equations are constructed using the algebraic redundant relationship among the actuators and sensors. Furthermore, a residual processor is designed to generate the probability of each of the actuator and sensor faults by using a sequential probability test. Finally, the health monitoring system, consisting of periodic fault detection lters, parity equations and residual processor, is evaluated in the simulation in the presence of disturbances and uncertainty.

Multitask neurovision processor with extensive feedback and feedforward connections

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1991-11-01

A multi-task neuro-vision parameter which performs a variety of information processing operations associated with the early stages of biological vision is presented. The network architecture of this neuro-vision processor, called the positive-negative (PN) neural processor, is loosely based on the neural activity fields exhibited by thalamic and cortical nervous tissue layers. The computational operation performed by the processor arises from the strength of the recurrent feedback among the numerous positive and negative neural computing units. By adjusting the feedback connections it is possible to generate diverse dynamic behavior that may be used for short-term visual memory (STVM), spatio-temporal filtering (STF), and pulse frequency modulation (PFM). The information attributes that are to be processes may be regulated by modifying the feedforward connections from the signal space to the neural processor.

Systems and Methods for RFID-Enabled Pressure Sensing Apparatus

NASA Technical Reports Server (NTRS)

Kennedy, Timothy F. (Inventor); Lin, Gregory Y. (Inventor); Ngo, Phong H. (Inventor); Fink, Patrick W. (Inventor)

2017-01-01

Methods, apparatuses and systems for radio frequency identification (RFID)-enabled information collection are disclosed, including an enclosure, a collector coupled to the enclosure, an interrogator, a processor, and one or more RFID field sensors, each having an individual identification, disposed within the enclosure. In operation, the interrogator transmits an incident signal to the collector, causing the collector to generate an electromagnetic field within the enclosure. The electromagnetic field is affected by one or more influences. RFID sensors respond to the electromagnetic field by transmitting reflected signals containing the individual identifications of the responding RFID sensors to the interrogator. The interrogator receives the reflected signals, measures one or more returned signal strength indications ("RSSI") of the reflected signals and sends the RSSI measurements and identification of the responding RFID sensors to the processor to determine one or more facts about the influences. Other embodiments are also described.

Systems and Methods for RFID-Enabled Dispenser

NASA Technical Reports Server (NTRS)

Fink, Patrick W. (Inventor); Kennedy, Timothy F. (Inventor); Lin, Gregory Y. (Inventor); Ngo, Phong H. (Inventor); Byerly, Diane (Inventor)

2015-01-01

Methods, apparatuses and systems for radio frequency identification (RFID)-enabled information collection are disclosed, including an enclosure, a collector coupled to the enclosure, an interrogator, a processor, and one or more RFID field sensors, each having an individual identification, disposed within the enclosure. In operation, the interrogator transmits an incident signal to the collector, causing the collector to generate an electromagnetic field within the enclosure. The electromagnetic field is affected by one or more influences. RFID sensors respond to the electromagnetic field by transmitting reflected signals containing the individual identifications of the responding RFID sensors to the interrogator. The interrogator receives the reflected signals, measures one or more returned signal strength indications ("RSSI") of the reflected signals and sends the RSSI measurements and identification of the responding RFID sensors to the processor to determine one or more facts about the influences. Other embodiments are also described.

Systems and Methods for RFID-Enabled Pressure Sensing Apparatus

NASA Technical Reports Server (NTRS)

Lin, Gregory Y. (Inventor); Ngo, Phong H. (Inventor); Kennedy, Timothy F. (Inventor); Fink, Patrick W. (Inventor)

2016-01-01

Methods, apparatuses and systems for radio frequency identification (RFID)-enabled information collection are disclosed, including an enclosure, a collector coupled to the enclosure, an interrogator, a processor, and one or more RFID field sensors, each having an individual identification, disposed within the enclosure. In operation, the interrogator transmits an incident signal to the collector, causing the collector to generate an electromagnetic field within the enclosure. The electromagnetic field is affected by one or more influences. RFID sensors respond to the electromagnetic field by transmitting reflected signals containing the individual identifications of the responding RFID sensors to the interrogator. The interrogator receives the reflected signals, measures one or more returned signal strength indications ("RSSI") of the reflected signals and sends the RSSI measurements and identification of the responding RFID sensors to the processor to determine one or more facts about the influences. Other embodiments are also described.

System and Method for RFID-Enabled Information Collection

NASA Technical Reports Server (NTRS)

Fink, Patrick W. (Inventor); Kennedy, Timothy F. (Inventor); Lin, Gregory Y. (Inventor); Ngo, Phong H. (Inventor); Byerly, Diane (Inventor)

2016-01-01

Methods, apparatuses and systems for radio frequency identification (RFID)-enabled information collection are disclosed, including an enclosure, a collector coupled to the enclosure, an interrogator, a processor, and one or more RFID field sensors, each having an individual identification, disposed within the enclosure. In operation, the interrogator transmits an incident signal to the collector, causing the collector to generate an electromagnetic field within the enclosure. The electromagnetic field is affected by one or more influences. RFID sensors respond to the electromagnetic field by transmitting reflected signals containing the individual identifications of the responding RFID sensors to the interrogator. The interrogator receives the reflected signals, measures one or more returned signal strength indications ("RSSI") of the reflected signals and sends the RSSI measurements and identification of the responding RFID sensors to the processor to determine one or more facts about the influences. Other embodiments are also described.

Method of Enhancing On-Board State Estimation Using Communication Signals

NASA Technical Reports Server (NTRS)

Anzalone, Evan J. (Inventor); Chuang, Jason C. H. (Inventor)

2015-01-01

A method of enhancing on-board state estimation for a spacecraft utilizes a network of assets to include planetary-based assets and space-based assets. Communication signals transmitted from each of the assets into space are defined by a common protocol. Data is embedded in each communication signal transmitted by the assets. The data includes a time-of-transmission for a corresponding one of the communication signals and a position of a corresponding one of the assets at the time-of-transmission. A spacecraft is equipped to receive the communication signals, has a clock synchronized to the space-wide time reference frame, and has a processor programmed to generate state estimates of the spacecraft. Using its processor, the spacecraft determines a one-dimensional range from itself to at least one of the assets and then updates its state estimates using each one-dimensional range.

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

Traffic Monitor

NASA Technical Reports Server (NTRS)

1995-01-01

Intelligent Vision Systems, Inc. (InVision) needed image acquisition technology that was reliable in bad weather for its TDS-200 Traffic Detection System. InVision researchers used information from NASA Tech Briefs and assistance from Johnson Space Center to finish the system. The NASA technology used was developed for Earth-observing imaging satellites: charge coupled devices, in which silicon chips convert light directly into electronic or digital images. The TDS-200 consists of sensors mounted above traffic on poles or span wires, enabling two sensors to view an intersection; a "swing and sway" feature to compensate for movement of the sensors; a combination of electronic shutter and gain control; and sensor output to an image digital signal processor, still frame video and optionally live video.

A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities.

PubMed

Jafari, Ali; Buswell, Nathanael; Ghovanloo, Maysam; Mohsenin, Tinoosh

2018-02-01

This paper presents a low-power stand-alone tongue drive system (sTDS) used for individuals with severe disabilities to potentially control their environment such as computer, smartphone, and wheelchair using their voluntary tongue movements. A low-power local processor is proposed, which can perform signal processing to convert raw magnetic sensor signals to user-defined commands, on the sTDS wearable headset, rather than sending all raw data out to a PC or smartphone. The proposed sTDS significantly reduces the transmitter power consumption and subsequently increases the battery life. Assuming the sTDS user issues one command every 20 ms, the proposed local processor reduces the data volume that needs to be wirelessly transmitted by a factor of 64, from 9.6 to 0.15 kb/s. The proposed processor consists of three main blocks: serial peripheral interface bus for receiving raw data from magnetic sensors, external magnetic interference attenuation to attenuate external magnetic field from the raw magnetic signal, and a machine learning classifier for command detection. A proof-of-concept prototype sTDS has been implemented with a low-power IGLOO-nano field programmable gate array (FPGA), bluetooth low energy, battery and magnetic sensors on a headset, and tested. At clock frequency of 20 MHz, the processor takes 6.6 s and consumes 27 nJ for detecting a command with a detection accuracy of 96.9%. To further reduce power consumption, an application-specified integrated circuit processor for the sTDS is implemented at the postlayout level in 65-nm CMOS technology with 1-V power supply, and it consumes 0.43 mW, which is 10 lower than FPGA power consumption and occupies an area of only 0.016 mm.

Formulation of consumables management models: Mission planning processor payload interface definition

NASA Technical Reports Server (NTRS)

Torian, J. G.

1977-01-01

Consumables models required for the mission planning and scheduling function are formulated. The relation of the models to prelaunch, onboard, ground support, and postmission functions for the space transportation systems is established. Analytical models consisting of an orbiter planning processor with consumables data base is developed. A method of recognizing potential constraint violations in both the planning and flight operations functions, and a flight data file storage/retrieval of information over an extended period which interfaces with a flight operations processor for monitoring of the actual flights is presented.

A neuronal model of a global workspace in effortful cognitive tasks.

PubMed

Dehaene, S; Kerszberg, M; Changeux, J P

1998-11-24

A minimal hypothesis is proposed concerning the brain processes underlying effortful tasks. It distinguishes two main computational spaces: a unique global workspace composed of distributed and heavily interconnected neurons with long-range axons, and a set of specialized and modular perceptual, motor, memory, evaluative, and attentional processors. Workspace neurons are mobilized in effortful tasks for which the specialized processors do not suffice. They selectively mobilize or suppress, through descending connections, the contribution of specific processor neurons. In the course of task performance, workspace neurons become spontaneously coactivated, forming discrete though variable spatio-temporal patterns subject to modulation by vigilance signals and to selection by reward signals. A computer simulation of the Stroop task shows workspace activation to increase during acquisition of a novel task, effortful execution, and after errors. We outline predictions for spatio-temporal activation patterns during brain imaging, particularly about the contribution of dorsolateral prefrontal cortex and anterior cingulate to the workspace.

Fault-tolerant battery system employing intra-battery network architecture

DOEpatents

Hagen, Ronald A.; Chen, Kenneth W.; Comte, Christophe; Knudson, Orlin B.; Rouillard, Jean

2000-01-01

A distributed energy storing system employing a communications network is disclosed. A distributed battery system includes a number of energy storing modules, each of which includes a processor and communications interface. In a network mode of operation, a battery computer communicates with each of the module processors over an intra-battery network and cooperates with individual module processors to coordinate module monitoring and control operations. The battery computer monitors a number of battery and module conditions, including the potential and current state of the battery and individual modules, and the conditions of the battery's thermal management system. An over-discharge protection system, equalization adjustment system, and communications system are also controlled by the battery computer. The battery computer logs and reports various status data on battery level conditions which may be reported to a separate system platform computer. A module transitions to a stand-alone mode of operation if the module detects an absence of communication connectivity with the battery computer. A module which operates in a stand-alone mode performs various monitoring and control functions locally within the module to ensure safe and continued operation.

A method for compression of intra-cortically-recorded neural signals dedicated to implantable brain-machine interfaces.

PubMed

Shaeri, Mohammad Ali; Sodagar, Amir M

2015-05-01

This paper proposes an efficient data compression technique dedicated to implantable intra-cortical neural recording devices. The proposed technique benefits from processing neural signals in the Discrete Haar Wavelet Transform space, a new spike extraction approach, and a novel data framing scheme to telemeter the recorded neural information to the outside world. Based on the proposed technique, a 64-channel neural signal processor was designed and prototyped as a part of a wireless implantable extra-cellular neural recording microsystem. Designed in a 0.13- μ m standard CMOS process, the 64-channel neural signal processor reported in this paper occupies ∼ 0.206 mm(2) of silicon area, and consumes 94.18 μW when operating under a 1.2-V supply voltage at a master clock frequency of 1.28 MHz.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Warmack, Robert J. Bruce; Wolf, Dennis A.; Frank, Steven Shane

Various apparatus and methods for smoke detection are disclosed. In one embodiment, a method of training a classifier for a smoke detector comprises inputting sensor data from a plurality of tests into a processor. The sensor data is processed to generate derived signal data corresponding to the test data for respective tests. The derived signal data is assigned into categories comprising at least one fire group and at least one non-fire group. Linear discriminant analysis (LDA) training is performed by the processor. The derived signal data and the assigned categories for the derived signal data are inputs to the LDAmore » training. The output of the LDA training is stored in a computer readable medium, such as in a smoke detector that uses LDA to determine, based on the training, whether present conditions indicate the existence of a fire.« less

Optical stereo video signal processor

NASA Technical Reports Server (NTRS)

Craig, G. D. (Inventor)

1985-01-01

An otpical video signal processor is described which produces a two-dimensional cross-correlation in real time of images received by a stereo camera system. The optical image of each camera is projected on respective liquid crystal light valves. The images on the liquid crystal valves modulate light produced by an extended light source. This modulated light output becomes the two-dimensional cross-correlation when focused onto a video detector and is a function of the range of a target with respect to the stereo camera. Alternate embodiments utilize the two-dimensional cross-correlation to determine target movement and target identification.

Visualization of information with an established order

DOEpatents

Wong, Pak Chung [Richland, WA; Foote, Harlan P [Richmond, WA; Thomas, James J [Richland, WA; Wong, Kwong-Kwok [Sugar Land, TX

2007-02-13

Among the embodiments of the present invention is a system including one or more processors operable to access data representative of a biopolymer sequence of monomer units. The one or more processors are further operable to establish a pattern corresponding to at least one fractal curve and generate one or more output signals corresponding to a number of image elements each representative of one of the monomer units. Also included is a display device responsive to the one or more output signals to visualize the biopolymer sequence by displaying the image elements in accordance with the pattern.

Two-dimensional acousto-optic processor using circular antenna array with a Butler matrix

NASA Astrophysics Data System (ADS)

Lee, Jim P.

1992-09-01

A two-dimensional acousto-optic signal processor is shown to be useful for providing simultaneous spectrum analysis and direction finding of radar signals over an instantaneous field of view of 360 deg. A system analysis with emphasis on the direction-finding aspect of this new architecture is presented. The peak location of the optical pattern provides a direct measure of bearing, independent of signal frequency. In addition, the sidelobe levels of the pattern can be effectively reduced using amplitude weighting. Performance parameters, such as mainlobe beamwidth, peak-sidelobe level, and pointing error, are analyzed as a function of the Gaussian laser illumination profile and the number of channels. Finally, a comparison with a linear antenna array architecture is also discussed.

Aerospace Applications Conference, Steamboat Springs, CO, Feb. 1-8, 1986, Digest

NASA Astrophysics Data System (ADS)

The present conference considers topics concerning the projected NASA Space Station's systems, digital signal and data processing applications, and space science and microwave applications. Attention is given to Space Station video and audio subsystems design, clock error, jitter, phase error and differential time-of-arrival in satellite communications, automation and robotics in space applications, target insertion into synthetic background scenes, and a novel scheme for the computation of the discrete Fourier transform on a systolic processor. Also discussed are a novel signal parameter measurement system employing digital signal processing, EEPROMS for spacecraft applications, a unique concurrent processor architecture for high speed simulation of dynamic systems, a dual polarization flat plate antenna, Fresnel diffraction, and ultralinear TWTs for high efficiency satellite communications.

Power processor for a 30cm ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.

1974-01-01

A thermal vacuum power processor for the NASA Lewis 30cm Mercury Ion Engine was designed, fabricated and tested to determine compliance with electrical specifications. The power processor breadboard used the silicon controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to an ion engine. The power processor includes a digital interface unit to process all input commands and internal telemetry signals so that operation is compatible with a central computer system. The breadboard was tested in a thermal vacuum environment. Integration tests were performed with the ion engine and demonstrate operational compatibility and reliable operation without any component failures. Electromagnetic interference data were also recorded on the design to provide information on the interaction with total spacecraft.

Programmable DNA-Mediated Multitasking Processor.

PubMed

Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

2015-04-30

Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

Launching GUPPI: the Green Bank Ultimate Pulsar Processing Instrument

NASA Astrophysics Data System (ADS)

DuPlain, Ron; Ransom, Scott; Demorest, Paul; Brandt, Patrick; Ford, John; Shelton, Amy L.

2008-08-01

The National Radio Astronomy Observatory (NRAO) is launching the Green Bank Ultimate Pulsar Processing Instrument (GUPPI), a prototype flexible digital signal processor designed for pulsar observations with the Robert C. Byrd Green Bank Telescope (GBT). GUPPI uses field programmable gate array (FPGA) hardware and design tools developed by the Center for Astronomy Signal Processing and Electronics Research (CASPER) at the University of California, Berkeley. The NRAO has been concurrently developing GUPPI software and hardware using minimal software resources. The software handles instrument monitor and control, data acquisition, and hardware interfacing. GUPPI is currently an expert-only spectrometer, but supports future integration with the full GBT production system. The NRAO was able to take advantage of the unique flexibility of the CASPER FPGA hardware platform, develop hardware and software in parallel, and build a suite of software tools for monitoring, controlling, and acquiring data with a new instrument over a short timeline of just a few months. The NRAO interacts regularly with CASPER and its users, and GUPPI stands as an example of what reconfigurable computing and open-source development can do for radio astronomy. GUPPI is modular for portability, and the NRAO provides the results of development as an open-source resource.

Asynchronous parallel status comparator

DOEpatents

Arnold, Jeffrey W.; Hart, Mark M.

1992-01-01

Apparatus for matching asynchronously received signals and determining whether two or more out of a total number of possible signals match. The apparatus comprises, in one embodiment, an array of sensors positioned in discrete locations and in communication with one or more processors. The processors will receive signals if the sensors detect a change in the variable sensed from a nominal to a special condition and will transmit location information in the form of a digital data set to two or more receivers. The receivers collect, read, latch and acknowledge the data sets and forward them to decoders that produce an output signal for each data set received. The receivers also periodically reset the system following each scan of the sensor array. A comparator then determines if any two or more, as specified by the user, of the output signals corresponds to the same location. A sufficient number of matches produces a system output signal that activates a system to restore the array to its nominal condition.

Asynchronous parallel status comparator

DOEpatents

Arnold, J.W.; Hart, M.M.

1992-12-15

Disclosed is an apparatus for matching asynchronously received signals and determining whether two or more out of a total number of possible signals match. The apparatus comprises, in one embodiment, an array of sensors positioned in discrete locations and in communication with one or more processors. The processors will receive signals if the sensors detect a change in the variable sensed from a nominal to a special condition and will transmit location information in the form of a digital data set to two or more receivers. The receivers collect, read, latch and acknowledge the data sets and forward them to decoders that produce an output signal for each data set received. The receivers also periodically reset the system following each scan of the sensor array. A comparator then determines if any two or more, as specified by the user, of the output signals corresponds to the same location. A sufficient number of matches produces a system output signal that activates a system to restore the array to its nominal condition. 4 figs.

Modeling the response of a monopulse radar to impulsive jamming signals using the Block Oriented System Simulator (BOSS)

NASA Astrophysics Data System (ADS)

Long, Jeffrey K.

1989-09-01

This theses developed computer models of two types of amplitude comparison monopulse processors using the Block Oriented System Simulation (BOSS) software package and to determine the response to these models to impulsive input signals. This study was an effort to determine the susceptibility of monopulse tracking radars to impulsing jamming signals. Two types of amplitude comparison monopulse receivers were modeled, one using logarithmic amplifiers and the other using automatic gain control for signal normalization. Simulations of both types of systems were run under various conditions of gain or frequency imbalance between the two receiver channels. The resulting errors from the imbalanced simulations were compared to the outputs of similar, baseline simulations which had no electrical imbalances. The accuracy of both types of processors was directly affected by gain or frequency imbalances in their receiver channels. In most cases, it was possible to generate both positive and negative angular errors, dependent upon the type and degree of mismatch between the channels. The system most susceptible to induced errors was a frequency imbalanced processor which used AGC circuitry. Any errors introduced will be a function of the degree of mismatch between the channels and therefore would be difficult to exploit reliably.

Cochlear implant microphone location affects speech recognition in diffuse noise.

PubMed

Kolberg, Elizabeth R; Sheffield, Sterling W; Davis, Timothy J; Sunderhaus, Linsey W; Gifford, René H

2015-01-01

Despite improvements in cochlear implants (CIs), CI recipients continue to experience significant communicative difficulty in background noise. Many potential solutions have been proposed to help increase signal-to-noise ratio in noisy environments, including signal processing and external accessories. To date, however, the effect of microphone location on speech recognition in noise has focused primarily on hearing aid users. The purpose of this study was to (1) measure physical output for the T-Mic as compared with the integrated behind-the-ear (BTE) processor mic for various source azimuths, and (2) to investigate the effect of CI processor mic location for speech recognition in semi-diffuse noise with speech originating from various source azimuths as encountered in everyday communicative environments. A repeated-measures, within-participant design was used to compare performance across listening conditions. A total of 11 adults with Advanced Bionics CIs were recruited for this study. Physical acoustic output was measured on a Knowles Experimental Mannequin for Acoustic Research (KEMAR) for the T-Mic and BTE mic, with broadband noise presented at 0 and 90° (directed toward the implant processor). In addition to physical acoustic measurements, we also assessed recognition of sentences constructed by researchers at Texas Instruments, the Massachusetts Institute of Technology, and the Stanford Research Institute (TIMIT sentences) at 60 dBA for speech source azimuths of 0, 90, and 270°. Sentences were presented in a semi-diffuse restaurant noise originating from the R-SPACE 8-loudspeaker array. Signal-to-noise ratio was determined individually to achieve approximately 50% correct in the unilateral implanted listening condition with speech at 0°. Performance was compared across the T-Mic, 50/50, and the integrated BTE processor mic. The integrated BTE mic provided approximately 5 dB attenuation from 1500-4500 Hz for signals presented at 0° as compared with 90° (directed toward the processor). The T-Mic output was essentially equivalent for sources originating from 0 and 90°. Mic location also significantly affected sentence recognition as a function of source azimuth, with the T-Mic yielding the highest performance for speech originating from 0°. These results have clinical implications for (1) future implant processor design with respect to mic location, (2) mic settings for implant recipients, and (3) execution of advanced speech testing in the clinic. American Academy of Audiology.

THE ALLEN TELESCOPE ARRAY SEARCH FOR ELECTROSTATIC DISCHARGES ON MARS

DOE Office of Scientific and Technical Information (OSTI.GOV)

Anderson, Marin M.; Siemion, Andrew P. V.; Bower, Geoffrey C.

The Allen Telescope Array was used to monitor Mars between 2010 March 9 and June 2, over a total of approximately 30 hr, for radio emission indicative of electrostatic discharge. The search was motivated by the report from Ruf et al. of the detection of non-thermal microwave radiation from Mars characterized by peaks in the power spectrum of the kurtosis, or kurtstrum, at 10 Hz, coinciding with a large dust storm event on 2006 June 8. For these observations, we developed a wideband signal processor at the Center for Astronomy Signal Processing and Electronics Research. This 1024 channel spectrometer calculatesmore » the accumulated power and power-squared, from which the spectral kurtosis is calculated post-observation. Variations in the kurtosis are indicative of non-Gaussianity in the signal, which can be used to detect variable cosmic signals as well as radio frequency interference (RFI). During the three-month period of observations, dust activity occurred on Mars in the form of small-scale dust storms; however, no signals indicating lightning discharge were detected. Frequent signals in the kurtstrum that contain spectral peaks with an approximate 10 Hz fundamental were seen at both 3.2 and 8.0 GHz, but were the result of narrowband RFI with harmonics spread over a broad frequency range.« less

Broadband set-top box using MAP-CA processor

NASA Astrophysics Data System (ADS)

Bush, John E.; Lee, Woobin; Basoglu, Chris

2001-12-01

Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

Evaluation of commercial video-based intersection signal actuation systems.

DOT National Transportation Integrated Search

2008-12-01

Video cameras and computer image processors have come into widespread use for the detection of : vehicles for signal actuation at controlled intersections. Video is considered both a cost-saving and : convenient alternative to conventional stop-line ...

Adaptive and mobile ground sensor array.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holzrichter, Michael Warren; O'Rourke, William T.; Zenner, Jennifer

The goal of this LDRD was to demonstrate the use of robotic vehicles for deploying and autonomously reconfiguring seismic and acoustic sensor arrays with high (centimeter) accuracy to obtain enhancement of our capability to locate and characterize remote targets. The capability to accurately place sensors and then retrieve and reconfigure them allows sensors to be placed in phased arrays in an initial monitoring configuration and then to be reconfigured in an array tuned to the specific frequencies and directions of the selected target. This report reviews the findings and accomplishments achieved during this three-year project. This project successfully demonstrated autonomousmore » deployment and retrieval of a payload package with an accuracy of a few centimeters using differential global positioning system (GPS) signals. It developed an autonomous, multisensor, temporally aligned, radio-frequency communication and signal processing capability, and an array optimization algorithm, which was implemented on a digital signal processor (DSP). Additionally, the project converted the existing single-threaded, monolithic robotic vehicle control code into a multi-threaded, modular control architecture that enhances the reuse of control code in future projects.« less

Eight-Channel Digital Signal Processor and Universal Trigger Module

NASA Astrophysics Data System (ADS)

Skulski, Wojtek; Wolfs, Frank

2003-04-01

A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

System and method for resolving gamma-ray spectra

DOEpatents

Gentile, Charles A.; Perry, Jason; Langish, Stephen W.; Silber, Kenneth; Davis, William M.; Mastrovito, Dana

2010-05-04

A system for identifying radionuclide emissions is described. The system includes at least one processor for processing output signals from a radionuclide detecting device, at least one training algorithm run by the at least one processor for analyzing data derived from at least one set of known sample data from the output signals, at least one classification algorithm derived from the training algorithm for classifying unknown sample data, wherein the at least one training algorithm analyzes the at least one sample data set to derive at least one rule used by said classification algorithm for identifying at least one radionuclide emission detected by the detecting device.

Real time SAR processing

NASA Technical Reports Server (NTRS)

Premkumar, A. B.; Purviance, J. E.

1990-01-01

A simplified model for the SAR imaging problem is presented. The model is based on the geometry of the SAR system. Using this model an expression for the entire phase history of the received SAR signal is formulated. From the phase history, it is shown that the range and the azimuth coordinates for a point target image can be obtained by processing the phase information during the intrapulse and interpulse periods respectively. An architecture for a VLSI implementation for the SAR signal processor is presented which generates images in real time. The architecture uses a small number of chips, a new correlation processor, and an efficient azimuth correlation process.

A Versatile Multichannel Digital Signal Processing Module for Microcalorimeter Arrays

NASA Astrophysics Data System (ADS)

Tan, H.; Collins, J. W.; Walby, M.; Hennig, W.; Warburton, W. K.; Grudberg, P.

2012-06-01

Different techniques have been developed for reading out microcalorimeter sensor arrays: individual outputs for small arrays, and time-division or frequency-division or code-division multiplexing for large arrays. Typically, raw waveform data are first read out from the arrays using one of these techniques and then stored on computer hard drives for offline optimum filtering, leading not only to requirements for large storage space but also limitations on achievable count rate. Thus, a read-out module that is capable of processing microcalorimeter signals in real time will be highly desirable. We have developed multichannel digital signal processing electronics that are capable of on-board, real time processing of microcalorimeter sensor signals from multiplexed or individual pixel arrays. It is a 3U PXI module consisting of a standardized core processor board and a set of daughter boards. Each daughter board is designed to interface a specific type of microcalorimeter array to the core processor. The combination of the standardized core plus this set of easily designed and modified daughter boards results in a versatile data acquisition module that not only can easily expand to future detector systems, but is also low cost. In this paper, we first present the core processor/daughter board architecture, and then report the performance of an 8-channel daughter board, which digitizes individual pixel outputs at 1 MSPS with 16-bit precision. We will also introduce a time-division multiplexing type daughter board, which takes in time-division multiplexing signals through fiber-optic cables and then processes the digital signals to generate energy spectra in real time.

Method for operating a combustor in a fuel cell system

DOEpatents

Chalfant, Robert W.; Clingerman, Bruce J.

2002-01-01

A method of operating a combustor to heat a fuel processor in a fuel cell system, in which the fuel processor generates a hydrogen-rich stream a portion of which is consumed in a fuel cell stack and a portion of which is discharged from the fuel cell stack and supplied to the combustor, and wherein first and second streams are supplied to the combustor, the first stream being a hydrocarbon fuel stream and the second stream consisting of said hydrogen-rich stream, the method comprising the steps of monitoring the temperature of the fuel processor; regulating the quantity of the first stream to the combustor according to the temperature of the fuel processor; and comparing said quantity of said first stream to a predetermined value or range of predetermined values.

A portable magnetic induction measurement system (PIMS).

PubMed

Cordes, Axel; Foussier, Jérôme; Pollig, Daniel; Leonhardt, Steffen

2012-02-22

For contactless monitoring of ventilation and heart activity, magnetic induction measurements are applicable. As the technique is harmless for the human body, it is well suited for long-term monitoring solutions, e.g., bedside monitoring, monitoring of home care patients, and the monitoring of persons in critical occupations. For such settings, a two-channel portable magnetic induction system has been developed, which is small and light enough to be fitted in a chair or bed. Because demodulation, control, and filtering are implemented on a front-end digital signal processor, a PC is not required (except for visualization/data storage during research and development). The system can be connected to a local area network (LAN) or wireless network (WiFi), allowing to connect several devices to a large monitoring system, e.g., for a residential home for the elderly or a hospital with low-risk patients not requiring standard ECG monitoring. To visualize data streams, a Qt-based (Qt-framework by Nokia, Espoo, Finland) monitoring application has been developed, which runs on Netbook computers, laptops, or standard PCs. To induce and measure the magnetic fields, external coils and amplifiers are required. This article describes the system and presents results for monitoring respiration and heart activity in a (divan) bed and for respiration monitoring in a chair. Planar configurations and orthogonal coil setups were examined during the measurement procedures. The measurement data were streamed over a LAN to a monitoring PC running Matlab (The MathWorks Inc, Natick, MA, USA).

Hybrid ECG signal conditioner

NASA Technical Reports Server (NTRS)

Rinard, G. A.; Steffen, D. A.; Sturm, R. E.

1979-01-01

Circuit with high common-mode rejection has ability to filter and amplify accepted analog electrocardiogram (ECG) signals of varying amplitude, shape, and polarity. In addition, low power circuit develops standardized pulses that can be counted and averaged by heart/breath rate processor.

Determination of torque speed current characteristics of a brushless DC motor by utilizing back-EMF of non-energized phase

NASA Astrophysics Data System (ADS)

Jang, G. H.; Yeom, J. H.; Kim, M. G.

2007-03-01

This paper presents a method to determine the torque constant and the torque-speed-current characteristics of a brushless DC (BLDC) motor by utilizing back-EMF variation of nonenergized phase. It also develops a BLDC motor controller with a digital signal processor (DSP) to monitor its current, voltage and speed in real time. Torque-speed-current characteristics of a BLDC motor are determined by using the proposed method and the developed controller. They are compared with the torque-speed-current characteristics measured by dynamometer experimentally. This research shows that the proposed method is an effective method to determine the torque constant and the torque-speed-current characteristics of the BLDC motor without using dynamometer.

Controller and interface module for the High-Speed Data Acquisition System correlator/accumulator

NASA Technical Reports Server (NTRS)

Brokl, S. S.

1985-01-01

One complex channel of the High-Speed Data Acquisition System (a subsystem used in the Goldstone solar system radar), consisting of two correlator modules and one accumulator module, is operated by the controller and interface module interfaces are provided to the VAX UNIBUS for computer control, monitor, and test of the controller and correlator/accumulator. The correlator and accumulator modules controlled by this module are the key digital signal processing elements of the Goldstone High-Speed Data Acquisition System. This fully programmable unit provides for a wide variety of correlation and filtering functions operating on a three megaword/second data flow. Data flow is to the VAX by way of the I/O port of a FPS 5210 array processor.

Evaluation of MERIS products from Baltic Sea coastal waters rich in CDOM

NASA Astrophysics Data System (ADS)

Beltrán-Abaunza, J. M.; Kratzer, S.; Brockmann, C.

2013-11-01

In this study, retrievals of the medium resolution imaging spectrometer (MERIS) reflectances and water quality products using 4 different coastal processing algorithms freely available are assessed by comparison against sea-truthing data. The study is based on a pair-wise comparison using processor-dependent quality flags for the retrieval of valid common macro-pixels. This assessment is required in order to ensure the reliability of monitoring systems based on MERIS data, such as the Swedish coastal and lake monitoring system (http.vattenkvalitet.se). The results show that the pre-processing with the Improved Contrast between Ocean and Land (ICOL) processor, correcting for adjacency effects, improve the retrieval of spectral reflectance for all processors, Therefore, it is recommended that the ICOL processor should be applied when Baltic coastal waters are investigated. Chlorophyll was retrieved best using the FUB (Free University of Berlin) processing algorithm, although overestimations in the range 18-26.5%, dependent on the compared pairs, were obtained. At low chlorophyll concentrations (< 2.5 mg m-3), random errors dominated in the retrievals with the MEGS (MERIS ground segment processor) processor. The lowest bias and random errors were obtained with MEGS for suspended particulate matter, for which overestimations in te range of 8-16% were found. Only the FUB retrieved CDOM (Coloured Dissolved Organic Matter) correlate with in situ values. However, a large systematic underestimation appears in the estimates that nevertheless may be corrected for by using a~local correction factor. The MEGS has the potential to be used as an operational processing algorithm for the Himmerfjärden bay and adjacent areas, but it requires further improvement of the atmospheric correction for the blue bands and better definition at relatively low chlorophyll concentrations in presence of high CDOM attenuation.

Evaluation of MERIS products from Baltic Sea coastal waters rich in CDOM

NASA Astrophysics Data System (ADS)

Beltrán-Abaunza, J. M.; Kratzer, S.; Brockmann, C.

2014-05-01

In this study, retrievals of the medium resolution imaging spectrometer (MERIS) reflectances and water quality products using four different coastal processing algorithms freely available are assessed by comparison against sea-truthing data. The study is based on a pair-wise comparison using processor-dependent quality flags for the retrieval of valid common macro-pixels. This assessment is required in order to ensure the reliability of monitoring systems based on MERIS data, such as the Swedish coastal and lake monitoring system (http://vattenkvalitet.se). The results show that the pre-processing with the Improved Contrast between Ocean and Land (ICOL) processor, correcting for adjacency effects, improves the retrieval of spectral reflectance for all processors. Therefore, it is recommended that the ICOL processor should be applied when Baltic coastal waters are investigated. Chlorophyll was retrieved best using the FUB (Free University of Berlin) processing algorithm, although overestimations in the range 18-26.5%, dependent on the compared pairs, were obtained. At low chlorophyll concentrations (< 2.5 mg m-3), data dispersion dominated in the retrievals with the MEGS (MERIS ground segment processor) processor. The lowest bias and data dispersion were obtained with MEGS for suspended particulate matter, for which overestimations in the range of 8-16% were found. Only the FUB retrieved CDOM (coloured dissolved organic matter) correlate with in situ values. However, a large systematic underestimation appears in the estimates that nevertheless may be corrected for by using a local correction factor. The MEGS has the potential to be used as an operational processing algorithm for the Himmerfjärden bay and adjacent areas, but it requires further improvement of the atmospheric correction for the blue bands and better definition at relatively low chlorophyll concentrations in the presence of high CDOM attenuation.

Recognition of Speech from the Television with Use of a Wireless Technology Designed for Cochlear Implants.

PubMed

Duke, Mila Morais; Wolfe, Jace; Schafer, Erin

2016-05-01

Cochlear implant (CI) recipients often experience difficulty understanding speech in noise and speech that originates from a distance. Many CI recipients also experience difficulty understanding speech originating from a television. Use of hearing assistance technology (HAT) may improve speech recognition in noise and for signals that originate from more than a few feet from the listener; however, there are no published studies evaluating the potential benefits of a wireless HAT designed to deliver audio signals from a television directly to a CI sound processor. The objective of this study was to compare speech recognition in quiet and in noise of CI recipients with the use of their CI alone and with the use of their CI and a wireless HAT (Cochlear Wireless TV Streamer). A two-way repeated measures design was used to evaluate performance differences obtained in quiet and in competing noise (65 dBA) with the CI sound processor alone and with the sound processor coupled to the Cochlear Wireless TV Streamer. Sixteen users of Cochlear Nucleus 24 Freedom, CI512, and CI422 implants were included in the study. Participants were evaluated in four conditions including use of the sound processor alone and use of the sound processor with the wireless streamer in quiet and in the presence of competing noise at 65 dBA. Speech recognition was evaluated in each condition with two full lists of Computer-Assisted Speech Perception Testing and Training Sentence-Level Test sentences presented from a light-emitting diode television. Speech recognition in noise was significantly better with use of the wireless streamer compared to participants' performance with their CI sound processor alone. There was also a nonsignificant trend toward better performance in quiet with use of the TV Streamer. Performance was significantly poorer when evaluated in noise compared to performance in quiet when the TV Streamer was not used. Use of the Cochlear Wireless TV Streamer designed to stream audio from a television directly to a CI sound processor provides better speech recognition in quiet and in noise when compared to performance obtained with use of the CI sound processor alone. American Academy of Audiology.

A Real-Time Capable Software-Defined Receiver Using GPU for Adaptive Anti-Jam GPS Sensors

PubMed Central

Seo, Jiwon; Chen, Yu-Hsuan; De Lorenzo, David S.; Lo, Sherman; Enge, Per; Akos, Dennis; Lee, Jiyun

2011-01-01

Due to their weak received signal power, Global Positioning System (GPS) signals are vulnerable to radio frequency interference. Adaptive beam and null steering of the gain pattern of a GPS antenna array can significantly increase the resistance of GPS sensors to signal interference and jamming. Since adaptive array processing requires intensive computational power, beamsteering GPS receivers were usually implemented using hardware such as field-programmable gate arrays (FPGAs). However, a software implementation using general-purpose processors is much more desirable because of its flexibility and cost effectiveness. This paper presents a GPS software-defined radio (SDR) with adaptive beamsteering capability for anti-jam applications. The GPS SDR design is based on an optimized desktop parallel processing architecture using a quad-core Central Processing Unit (CPU) coupled with a new generation Graphics Processing Unit (GPU) having massively parallel processors. This GPS SDR demonstrates sufficient computational capability to support a four-element antenna array and future GPS L5 signal processing in real time. After providing the details of our design and optimization schemes for future GPU-based GPS SDR developments, the jamming resistance of our GPS SDR under synthetic wideband jamming is presented. Since the GPS SDR uses commercial-off-the-shelf hardware and processors, it can be easily adopted in civil GPS applications requiring anti-jam capabilities. PMID:22164116

A real-time capable software-defined receiver using GPU for adaptive anti-jam GPS sensors.

PubMed

Seo, Jiwon; Chen, Yu-Hsuan; De Lorenzo, David S; Lo, Sherman; Enge, Per; Akos, Dennis; Lee, Jiyun

2011-01-01

Due to their weak received signal power, Global Positioning System (GPS) signals are vulnerable to radio frequency interference. Adaptive beam and null steering of the gain pattern of a GPS antenna array can significantly increase the resistance of GPS sensors to signal interference and jamming. Since adaptive array processing requires intensive computational power, beamsteering GPS receivers were usually implemented using hardware such as field-programmable gate arrays (FPGAs). However, a software implementation using general-purpose processors is much more desirable because of its flexibility and cost effectiveness. This paper presents a GPS software-defined radio (SDR) with adaptive beamsteering capability for anti-jam applications. The GPS SDR design is based on an optimized desktop parallel processing architecture using a quad-core Central Processing Unit (CPU) coupled with a new generation Graphics Processing Unit (GPU) having massively parallel processors. This GPS SDR demonstrates sufficient computational capability to support a four-element antenna array and future GPS L5 signal processing in real time. After providing the details of our design and optimization schemes for future GPU-based GPS SDR developments, the jamming resistance of our GPS SDR under synthetic wideband jamming is presented. Since the GPS SDR uses commercial-off-the-shelf hardware and processors, it can be easily adopted in civil GPS applications requiring anti-jam capabilities.

Design and realization of the baseband processor in satellite navigation and positioning receiver

NASA Astrophysics Data System (ADS)

Zhang, Dawei; Hu, Xiulin; Li, Chen

2007-11-01

The content of this paper is focused on the Design and realization of the baseband processor in satellite navigation and positioning receiver. Baseband processor is the most important part of the satellite positioning receiver. The design covers baseband processor's main functions include multi-channel digital signal DDC, acquisition, code tracking, carrier tracking, demodulation, etc. The realization is based on an Altera's FPGA device, that makes the system can be improved and upgraded without modifying the hardware. It embodies the theory of software defined radio (SDR), and puts the theory of the spread spectrum into practice. This paper puts emphasis on the realization of baseband processor in FPGA. In the order of choosing chips, design entry, debugging and synthesis, the flow is presented detailedly. Additionally the paper detailed realization of Digital PLL in order to explain a method of reducing the consumption of FPGA. Finally, the paper presents the result of Synthesis. This design has been used in BD-1, BD-2 and GPS.

System on a chip with MPEG-4 capability

NASA Astrophysics Data System (ADS)

Yassa, Fathy; Schonfeld, Dan

2002-12-01

Current products supporting video communication applications rely on existing computer architectures. RISC processors have been used successfully in numerous applications over several decades. DSP processors have become ubiquitous in signal processing and communication applications. Real-time applications such as speech processing in cellular telephony rely extensively on the computational power of these processors. Video processors designed to implement the computationally intensive codec operations have also been used to address the high demands of video communication applications (e.g., cable set-top boxes and DVDs). This paper presents an overview of a system-on-chip (SOC) architecture used for real-time video in wireless communication applications. The SOC specifications answer to the system requirements imposed by the application environment. A CAM-based video processor is used to accelerate data intensive video compression tasks such as motion estimations and filtering. Other components are dedicated to system level data processing and audio processing. A rich set of I/Os allows the SOC to communicate with other system components such as baseband and memory subsystems.

Method and apparatus for reducing spacecraft instrument induced jitter via multifrequency cancellation

NASA Technical Reports Server (NTRS)

Liu, Ketao (Inventor); Uetrecht, David S. (Inventor)

2002-01-01

A method, apparatus, article of manufacture, and a memory structure for compensating for instrument induced spacecraft jitter is disclosed. The apparatus comprises a spacecraft control processor for producing an actuator command signal, a signal generator, for producing a cancellation signal having at least one harmonic having a frequency and an amplitude substantially equal to that of a disturbance harmonic interacting with a spacecraft structural resonance and a phase substantially out of phase with the disturbance harmonic interacting with the spacecraft structural resonance, and at least one spacecraft control actuator, communicatively coupled to the spacecraft control processor and the signal generator for inducing satellite motion according to the actuator command signal and the cancellation signal. The method comprises the steps of generating a cancellation signal having at least one harmonic having a frequency and an amplitude substantially equal to that of a disturbance harmonic interacting with a spacecraft structural resonance and a phase substantially out of phase with the disturbance harmonic interacting with the spacecraft structural resonance, and providing the cancellation signal to a spacecraft control actuator. The apparatus comprises a storage device tangibly embodying the method steps described above.

Multi-Velocity Component LDV

NASA Technical Reports Server (NTRS)

Johnson, Dennis A. (Inventor)

1996-01-01

A laser doppler velocimeter uses frequency shifting of a laser beam to provide signal information for each velocity component. A composite electrical signal generated by a light detector is digitized and a processor produces a discrete Fourier transform based on the digitized electrical signal. The transform includes two peak frequencies corresponding to the two velocity components.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Method of implementation of optoelectronic multiparametric signal processing systems based on multivalued-logic principles

NASA Astrophysics Data System (ADS)

Arestova, M. L.; Bykovskii, A. Yu

1995-10-01

An architecture is proposed for a specialised optoelectronic multivalued logic processor based on the Allen—Givone algebra. The processor is intended for multiparametric processing of data arriving from a large number of sensors or for tackling spectral analysis tasks. The processor architecture makes it possible to obtain an approximate general estimate of the state of an object being diagnosed on a p-level scale. Optoelectronic systems are proposed for MAXIMUM, MINIMUM, and LITERAL logic gates, based on optical-frequency encoding of logic levels. Corresponding logic gates form a complete set of logic functions in the Allen—Givone algebra.

Extended Logic Intelligent Processing System for a Sensor Fusion Processor Hardware

NASA Technical Reports Server (NTRS)

Stoica, Adrian; Thomas, Tyson; Li, Wei-Te; Daud, Taher; Fabunmi, James

2000-01-01

The paper presents the hardware implementation and initial tests from a low-power, highspeed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) is described, which combines rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor signals in compact low power VLSI. The development of the ELIPS concept is being done to demonstrate the interceptor functionality which particularly underlines the high speed and low power requirements. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Processing speeds of microseconds have been demonstrated using our test hardware.

Holo-Chidi video concentrator card

NASA Astrophysics Data System (ADS)

Nwodoh, Thomas A.; Prabhakar, Aditya; Benton, Stephen A.

2001-12-01

The Holo-Chidi Video Concentrator Card is a frame buffer for the Holo-Chidi holographic video processing system. Holo- Chidi is designed at the MIT Media Laboratory for real-time computation of computer generated holograms and the subsequent display of the holograms at video frame rates. The Holo-Chidi system is made of two sets of cards - the set of Processor cards and the set of Video Concentrator Cards (VCCs). The Processor cards are used for hologram computation, data archival/retrieval from a host system, and for higher-level control of the VCCs. The VCC formats computed holographic data from multiple hologram computing Processor cards, converting the digital data to analog form to feed the acousto-optic-modulators of the Media lab's Mark-II holographic display system. The Video Concentrator card is made of: a High-Speed I/O (HSIO) interface whence data is transferred from the hologram computing Processor cards, a set of FIFOs and video RAM used as buffer for data for the hololines being displayed, a one-chip integrated microprocessor and peripheral combination that handles communication with other VCCs and furnishes the card with a USB port, a co-processor which controls display data formatting, and D-to-A converters that convert digital fringes to analog form. The co-processor is implemented with an SRAM-based FPGA with over 500,000 gates and controls all the signals needed to format the data from the multiple Processor cards into the format required by Mark-II. A VCC has three HSIO ports through which up to 500 Megabytes of computed holographic data can flow from the Processor Cards to the VCC per second. A Holo-Chidi system with three VCCs has enough frame buffering capacity to hold up to thirty two 36Megabyte hologram frames at a time. Pre-computed holograms may also be loaded into the VCC from a host computer through the low- speed USB port. Both the microprocessor and the co- processor in the VCC can access the main system memory used to store control programs and data for the VCC. The Card also generates the control signals used by the scanning mirrors of Mark-II. In this paper we discuss the design of the VCC and its implementation in the Holo-Chidi system.

System and Method of Locating Lightning Strikes

NASA Technical Reports Server (NTRS)

Medelius, Pedro J. (Inventor); Starr, Stanley O. (Inventor)

2002-01-01

A system and method of determining locations of lightning strikes has been described. The system includes multiple receivers located around an area of interest, such as a space center or airport. Each receiver monitors both sound and electric fields. The detection of an electric field pulse and a sound wave are used to calculate an area around each receiver in which the lighting is detected. A processor is coupled to the receivers to accurately determine the location of the lighting strike. The processor can manipulate the receiver data to compensate for environmental variables such as wind, temperature, and humidity. Further, each receiver processor can discriminate between distant and local lightning strikes.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Cochlear Implant Microphone Location Affects Speech Recognition in Diffuse Noise

PubMed Central

Kolberg, Elizabeth R.; Sheffield, Sterling W.; Davis, Timothy J.; Sunderhaus, Linsey W.; Gifford, René H.

2015-01-01

Background Despite improvements in cochlear implants (CIs), CI recipients continue to experience significant communicative difficulty in background noise. Many potential solutions have been proposed to help increase signal-to-noise ratio in noisy environments, including signal processing and external accessories. To date, however, the effect of microphone location on speech recognition in noise has focused primarily on hearing aid users. Purpose The purpose of this study was to (1) measure physical output for the T-Mic as compared with the integrated behind-the-ear(BTE) processor mic for various source azimuths, and (2) to investigate the effect of CI processor mic location for speech recognition in semi-diffuse noise with speech originating from various source azimuths as encountered in everyday communicative environments. Research Design A repeated-measures, within-participant design was used to compare performance across listening conditions. Study Sample A total of 11 adults with Advanced Bionics CIs were recruited for this study. Data Collection and Analysis Physical acoustic output was measured on a Knowles Experimental Mannequin for Acoustic Research (KEMAR) for the T-Mic and BTE mic, with broadband noise presented at 0 and 90° (directed toward the implant processor). In addition to physical acoustic measurements, we also assessed recognition of sentences constructed by researchers at Texas Instruments, the Massachusetts Institute of Technology, and the Stanford Research Institute (TIMIT sentences) at 60 dBA for speech source azimuths of 0, 90, and 270°. Sentences were presented in a semi-diffuse restaurant noise originating from the R-SPACE 8-loudspeaker array. Signal-to-noise ratio was determined individually to achieve approximately 50% correct in the unilateral implanted listening condition with speech at 0°. Performance was compared across the T-Mic, 50/50, and the integrated BTE processor mic. Results The integrated BTE mic provided approximately 5 dB attenuation from 1500–4500 Hz for signals presented at 0° as compared with 90° (directed toward the processor). The T-Mic output was essentially equivalent for sources originating from 0 and 90°. Mic location also significantly affected sentence recognition as a function of source azimuth, with the T-Mic yielding the highest performance for speech originating from 0°. Conclusions These results have clinical implications for (1) future implant processor design with respect to mic location, (2) mic settings for implant recipients, and (3) execution of advanced speech testing in the clinic. PMID:25597460

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rodenbeck, Christopher T.; Young, Derek; Chou, Tina

A combined radar and telemetry system is described. The combined radar and telemetry system includes a processing unit that executes instructions, where the instructions define a radar waveform and a telemetry waveform. The processor outputs a digital baseband signal based upon the instructions, where the digital baseband signal is based upon the radar waveform and the telemetry waveform. A radar and telemetry circuit transmits, simultaneously, a radar signal and telemetry signal based upon the digital baseband signal.

Multichannel photonic Hilbert transformers based on complex modulated integrated Bragg gratings.

PubMed

Cheng, Rui; Chrostowski, Lukas

2018-03-01

Multichannel photonic Hilbert transformers (MPHTs) are reported. The devices are based on single compact spiral integrated Bragg gratings on silicon with coupling coefficients precisely modulated by the phase of each grating period. MPHTs with up to nine wavelength channels and a single-channel bandwidth of up to ∼625  GHz are achieved. The potential of the devices for multichannel single-sideband signal generation is suggested. The work offers a new possibility of utilizing wavelength as an extra degree of freedom in designing radio-frequency photonic signal processors. Such multichannel processors are expected to possess improved capacities and a potential to greatly benefit current widespread wavelength division multiplexed systems.

Interdisciplinary education in optics and photonics based on microcontrollers

NASA Astrophysics Data System (ADS)

Dreßler, Paul; Wielage, Heinz-Hermann; Haiss, Ulrich; Vauderwange, Oliver; Curticapean, Dan

2014-07-01

Not only is the number of new devices constantly increasing, but so is their application complexity and power. Most of their applications are in optics, photonics, acoustic and mobile devices. Working speed and functionality is achieved in most of media devices by strategic use of digital signal processors and microcontrollers of the new generation. Considering all these premises of media development dynamics, the authors present how to integrate microcontrollers and digital signal processors in the curricula of media technology lectures by using adequate content. This also includes interdisciplinary content that consists of using the acquired knowledge in media software. These entries offer a deeper understanding of photonics, acoustics and media engineering.

Analytical and experimental design and analysis of an optimal processor for image registration

NASA Technical Reports Server (NTRS)

Mcgillem, C. D. (Principal Investigator); Svedlow, M.; Anuta, P. E.

1976-01-01

The author has identified the following significant results. A quantitative measure of the registration processor accuracy in terms of the variance of the registration error was derived. With the appropriate assumptions, the variance was shown to be inversely proportional to the square of the effective bandwidth times the signal to noise ratio. The final expressions were presented to emphasize both the form and simplicity of their representation. In the situation where relative spatial distortions exist between images to be registered, expressions were derived for estimating the loss in output signal to noise ratio due to these spatial distortions. These results are in terms of a reduction factor.

A Cochlear Implant Signal Processing Lab: Exploration of a Problem-Based Learning Exercise

ERIC Educational Resources Information Center

Bhatti, P. T.; McClellan, J. H.

2011-01-01

This paper presents an introductory signal processing laboratory and examines this laboratory exercise in the context of problem-based learning (PBL). Centered in a real-world application, a cochlear implant, the exercise challenged students to demonstrate a working software-based signal processor. Partnering in groups of two or three, second-year…

Digital signal processing in microwave radiometers

NASA Technical Reports Server (NTRS)

Lawrence, R. W.; Stanley, W. D.; Harrington, R. F.

1980-01-01

A microprocessor based digital signal processing unit has been proposed to replace analog sections of a microwave radiometer. A brief introduction to the radiometer system involved and a description of problems encountered in the use of digital techniques in radiometer design are discussed. An analysis of the digital signal processor as part of the radiometer is then presented.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

49 CFR 236.921 - Training and qualification program, general.

Code of Federal Regulations, 2010 CFR

2010-10-01

... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.921 Training and qualification program..., wayside, or onboard subsystems; (2) Persons who dispatch train operations (issue or communicate any...

Radar transponder apparatus and signal processing technique

DOEpatents

Axline, Jr., Robert M.; Sloan, George R.; Spalding, Richard E.

1996-01-01

An active, phase-coded, time-grating transponder and a synthetic-aperture radar (SAR) and signal processor means, in combination, allow the recognition and location of the transponder (tag) in the SAR image and allow communication of information messages from the transponder to the SAR. The SAR is an illuminating radar having special processing modifications in an image-formation processor to receive an echo from a remote transponder, after the transponder receives and retransmits the SAR illuminations, and to enhance the transponder's echo relative to surrounding ground clutter by recognizing special transponder modulations from phase-shifted from the transponder retransmissions. The remote radio-frequency tag also transmits information to the SAR through a single antenna that also serves to receive the SAR illuminations. Unique tag-modulation and SAR signal processing techniques, in combination, allow the detection and precise geographical location of the tag through the reduction of interfering signals from ground clutter, and allow communication of environmental and status information from said tag to be communicated to said SAR.

Radar transponder apparatus and signal processing technique

DOEpatents

Axline, R.M. Jr.; Sloan, G.R.; Spalding, R.E.

1996-01-23

An active, phase-coded, time-grating transponder and a synthetic-aperture radar (SAR) and signal processor means, in combination, allow the recognition and location of the transponder (tag) in the SAR image and allow communication of information messages from the transponder to the SAR. The SAR is an illuminating radar having special processing modifications in an image-formation processor to receive an echo from a remote transponder, after the transponder receives and retransmits the SAR illuminations, and to enhance the transponder`s echo relative to surrounding ground clutter by recognizing special transponder modulations from phase-shifted from the transponder retransmissions. The remote radio-frequency tag also transmits information to the SAR through a single antenna that also serves to receive the SAR illuminations. Unique tag-modulation and SAR signal processing techniques, in combination, allow the detection and precise geographical location of the tag through the reduction of interfering signals from ground clutter, and allow communication of environmental and status information from said tag to be communicated to said SAR. 4 figs.

Adaptive Signal Processing Testbed: VME-based DSP board market survey

NASA Astrophysics Data System (ADS)

Ingram, Rick E.

1992-04-01

The Adaptive Signal Processing Testbed (ASPT) is a real-time multiprocessor system utilizing digital signal processor technology on VMEbus based printed circuit boards installed on a Sun workstation. The ASPT has specific requirements, particularly as regards to the signal excision application, with respect to interfacing with current and planned data generation equipment, processing of the data, storage to disk of final and intermediate results, and the development tools for applications development and integration into the overall EW/COM computing environment. A prototype ASPT was implemented using three VME-C-30 boards from Applied Silicon. Experience gained during the prototype development led to the conclusions that interprocessor communications capability is the most significant contributor to overall ASPT performance. In addition, the host involvement should be minimized. Boards using different processors were evaluated with respect to the ASPT system requirements, pricing, and availability. Specific recommendations based on various priorities are made as well as recommendations concerning the integration and interaction of various tools developed during the prototype implementation.

EGR distribution and fluctuation probe based on CO.sub.2 measurements

DOEpatents

Parks, II, James E; Partridge, Jr., William P; Yoo, Ji Hyung

2015-04-07

A diagnostic system having a single-port EGR probe and a method for using the same. The system includes a light source, an EGR probe, a detector and a processor. The light source may provide a combined light beam composed of light from a mid-infrared signal source and a mid-infrared reference source. The signal source may be centered at 4.2 .mu.m and the reference source may be centered at 3.8 .mu.m. The EGR probe may be a single-port probe with internal optics and a sampling chamber with two flow cells arranged along the light path in series. The optics may include a lens for focusing the light beam and a mirror for reflecting the light beam received from a pitch optical cable to a catch optical cable. The signal and reference sources are modulated at different frequencies, thereby allowing them to be separated and the signal normalized by the processor.

An LFMCW detector with new structure and FRFT based differential distance estimation method.

PubMed

Yue, Kai; Hao, Xinhong; Li, Ping

2016-01-01

This paper describes a linear frequency modulated continuous wave (LFMCW) detector which is designed for a collision avoidance radar. This detector can estimate distance between the detector and pedestrians or vehicles, thereby it will help to reduce the likelihood of traffic accidents. The detector consists of a transceiver and a signal processor. A novel structure based on the intermediate frequency signal (IFS) is designed for the transceiver which is different from the traditional LFMCW transceiver using the beat frequency signal (BFS) based structure. In the signal processor, a novel fractional Fourier transform (FRFT) based differential distance estimation (DDE) method is used to detect the distance. The new IFS based structure is beneficial for the FRFT based DDE method to reduce the computation complexity, because it does not need the scan of the optimal FRFT order. Low computation complexity ensures the feasibility of practical applications. Simulations are carried out and results demonstrate the efficiency of the detector designed in this paper.

An infrared search for extraterrestrial laser signals

NASA Technical Reports Server (NTRS)

Betz, A.

1986-01-01

The focus of project SETI is on microwave frequencies, where receivers fundamentally have the best sensitivity for the detection of narrow band signals. Such receivers, when coupled to existing radio telescopes, form an optimum system for broad area searches over the sky. Detection of narrow band infrared signals is best done with a laser heterodyne reciever similar in function to a microwave spectral line receiver. A receiver was built for astrophysical observations at 30 THz (10 microns) and the spectrometer is being adapted for SETI work. The receiver uses a small CO2 laser as the local oscillator, a HgCdTe diode as the photomixer, and a multichannel intermediate frequency (IF) filterbank. An advanced multichannel IF processor is now being built to detect infrared line radiation in 1000 spectral channels each 1 MHz wide. When completed this processor will be used with a ground based telescope next year for a survey of several hundred selected stars for narrow band CO2 laser signals at 30 THz.

Embedded DSP-based telehealth radar system for remote in-door fall detection.

PubMed

Garripoli, Carmine; Mercuri, Marco; Karsmakers, Peter; Jack Soh, Ping; Crupi, Giovanni; Vandenbosch, Guy A E; Pace, Calogero; Leroux, Paul; Schreurs, Dominique

2015-01-01

Telehealth systems and applications are extensively investigated nowadays to enhance the quality-of-care and, in particular, to detect emergency situations and to monitor the well-being of elderly people, allowing them to stay at home independently as long as possible. In this paper, an embedded telehealth system for continuous, automatic, and remote monitoring of real-time fall emergencies is presented and discussed. The system, consisting of a radar sensor and base station, represents a cost-effective and efficient healthcare solution. The implementation of the fall detection data processing technique, based on the least-square support vector machines, through a digital signal processor and the management of the communication between radar sensor and base station are detailed. Experimental tests, for a total of 65 mimicked fall incidents, recorded with 16 human subjects (14 men and two women) that have been monitored for 320 min, have been used to validate the proposed system under real circumstances. The subjects' weight is between 55 and 90 kg with heights between 1.65 and 1.82 m, while their age is between 25 and 39 years. The experimental results have shown a sensitivity to detect the fall events in real time of 100% without reporting false positives. The tests have been performed in an area where the radar's operation was not limited by practical situations, namely, signal power, coverage of the antennas, and presence of obstacles between the subject and the antennas.

A Bayesian sequential processor approach to spectroscopic portal system decisions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sale, K; Candy, J; Breitfeller, E

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waitingmore » for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.« less

A retrospective detection algorithm for extraction of weak targets in clutter and interference environments

NASA Astrophysics Data System (ADS)

Prengaman, R. J.; Thurber, R. E.; Bath, W. G.

The usefulness of radar systems depends on the ability to distinguish between signals returned from desired targets and noise. A retrospective processor uses all contacts (or 'plots') from several past radar scans, taking into account all possible target trajectories formed from stored contacts for each input detection. The processor eliminates many false alarms, while retaining those contacts describing resonable trajectories. The employment of a retrospective processor makes it, therefore, possible to obtain large improvements in detection sensitivity in certain important clutter environments. Attention is given to the retrospective processing concept, a theoretical analysis of the multiscan detection process, the experimental evaluation of retrospective data filter, and aspects of retrospective data filter hardware implementation.

One Way of Testing a Distributed Processor

NASA Technical Reports Server (NTRS)

Edstrom, R.; Kleckner, D.

1982-01-01

Launch processing for Space Shuttle is checked out, controlled, and monitored with new system. Entire system can be exercised by two computer programs--one in master console and other in each of operations consoles. Control program in each operations console detects change in status and begins task initiation. All of front-end processors are exercised from consoles through common data buffer, and all data are logged to processed-data recorder for posttest analysis.

Strong Motion Seismograph Based On MEMS Accelerometer

NASA Astrophysics Data System (ADS)

Teng, Y.; Hu, X.

2013-12-01

The MEMS strong motion seismograph we developed used the modularization method to design its software and hardware.It can fit various needs in different application situation.The hardware of the instrument is composed of a MEMS accelerometer,a control processor system,a data-storage system,a wired real-time data transmission system by IP network,a wireless data transmission module by 3G broadband,a GPS calibration module and power supply system with a large-volumn lithium battery in it. Among it,the seismograph's sensor adopted a three-axis with 14-bit high resolution and digital output MEMS accelerometer.Its noise level just reach about 99μg/√Hz and ×2g to ×8g dynamically selectable full-scale.Its output data rates from 1.56Hz to 800Hz. Its maximum current consumption is merely 165μA,and the device is so small that it is available in a 3mm×3mm×1mm QFN package. Furthermore,there is access to both low pass filtered data as well as high pass filtered data,which minimizes the data analysis required for earthquake signal detection. So,the data post-processing can be simplified. Controlling process system adopts a 32-bit low power consumption embedded ARM9 processor-S3C2440 and is based on the Linux operation system.The processor's operating clock at 400MHz.The controlling system's main memory is a 64MB SDRAM with a 256MB flash-memory.Besides,an external high-capacity SD card data memory can be easily added.So the system can meet the requirements for data acquisition,data processing,data transmission,data storage,and so on. Both wired and wireless network can satisfy remote real-time monitoring, data transmission,system maintenance,status monitoring or updating software.Linux was embedded and multi-layer designed conception was used.The code, including sensor hardware driver,the data acquisition,earthquake setting out and so on,was written on medium layer.The hardware driver consist of IIC-Bus interface driver, IO driver and asynchronous notification driver. The application program layer mainly concludes: earthquake parameter module, local database managing module, data transmission module, remote monitoring, FTP service and so on. The application layer adopted multi-thread process. The whole strong motion seismograph was encapsulated in a small aluminum box, which size is 80mm×120mm×55mm. The inner battery can work continuesly more than 24 hours. The MEMS accelerograph uses modular design for its software part and hardware part. It has remote software update function and can meet the following needs: a) Auto picking up the earthquake event; saving the data on wave-event files and hours files; It may be used for monitoring strong earthquake, explosion, bridge and house health. b) Auto calculate the earthquake parameters, and transferring those parameters by 3G wireless broadband network. This kind of seismograph has characteristics of low cost, easy installation. They can be concentrated in the urban region or areas need to specially care. We can set up a ground motion parameters quick report sensor network while large earthquake break out. Then high-resolution-fine shake-map can be easily produced for the need of emergency rescue. c) By loading P-wave detection program modules, it can be used for earthquake early warning for large earthquakes; d) Can easily construct a high-density layout seismic monitoring network owning remote control and modern intelligent earthquake sensor.

Methods for synchronizing a countdown routine of a timer key and electronic device

DOEpatents

Condit, Reston A.; Daniels, Michael A.; Clemens, Gregory P.; Tomberlin, Eric S.; Johnson, Joel A.

2015-06-02

A timer key relating to monitoring a countdown time of a countdown routine of an electronic device is disclosed. The timer key comprises a processor configured to respond to a countdown time associated with operation of the electronic device, a display operably coupled with the processor, and a housing configured to house at least the processor. The housing has an associated structure configured to engage with the electronic device to share the countdown time between the electronic device and the timer key. The processor is configured to begin a countdown routine based at least in part on the countdown time, wherein the countdown routine is at least substantially synchronized with a countdown routine of the electronic device when the timer key is removed from the electronic device. A system and method for synchronizing countdown routines of a timer key and an electronic device are also disclosed.

Apparatus, system, and method for synchronizing a timer key

DOEpatents

Condit, Reston A; Daniels, Michael A; Clemens, Gregory P; Tomberlin, Eric S; Johnson, Joel A

2014-04-22

A timer key relating to monitoring a countdown time of a countdown routine of an electronic device is disclosed. The timer key comprises a processor configured to respond to a countdown time associated with operation of the electronic device, a display operably coupled with the processor, and a housing configured to house at least the processor. The housing has an associated structure configured to engage with the electronic device to share the countdown time between the electronic device and the timer key. The processor is configured to begin a countdown routine based at least in part on the countdown time, wherein the countdown routine is at least substantially synchronized with a countdown routine of the electronic device when the timer key is removed from the electronic device. A system and method for synchronizing countdown routines of a timer key and an electronic device are also disclosed.

TOGA - A GNSS Reflections Instrument for Remote Sensing Using Beamforming

NASA Technical Reports Server (NTRS)

Esterhuizen, S.; Meehan, T. K.; Robison, D.

2009-01-01

Remotely sensing the Earth's surface using GNSS signals as bi-static radar sources is one of the most challenging applications for radiometric instrument design. As part of NASA's Instrument Incubator Program, our group at JPL has built a prototype instrument, TOGA (Time-shifted, Orthometric, GNSS Array), to address a variety of GNSS science needs. Observing GNSS reflections is major focus of the design/development effort. The TOGA design features a steerable beam antenna array which can form a high-gain antenna pattern in multiple directions simultaneously. Multiple FPGAs provide flexible digital signal processing logic to process both GPS and Galileo reflections. A Linux OS based science processor serves as experiment scheduler and data post-processor. This paper outlines the TOGA design approach as well as preliminary results of reflection data collected from test flights over the Pacific ocean. This reflections data demonstrates observation of the GPS L1/L2C/L5 signals.

Modeling of the ground-to-SSFMB link networking features using SPW

NASA Technical Reports Server (NTRS)

Watson, John C.

1993-01-01

This report describes the modeling and simulation of the networking features of the ground-to-Space Station Freedom manned base (SSFMB) link using COMDISCO signal processing work-system (SPW). The networking features modeled include the implementation of Consultative Committee for Space Data Systems (CCSDS) protocols in the multiplexing of digitized audio and core data into virtual channel data units (VCDU's) in the control center complex and the demultiplexing of VCDU's in the onboard baseband signal processor. The emphasis of this work has been placed on techniques for modeling the CCSDS networking features using SPW. The objectives for developing the SPW models are to test the suitability of SPW for modeling networking features and to develop SPW simulation models of the control center complex and space station baseband signal processor for use in end-to-end testing of the ground-to-SSFMB S-band single access forward (SSAF) link.

SPP: A data base processor data communications protocol

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1983-01-01

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Automated mass spectrometer analysis system

NASA Technical Reports Server (NTRS)

Giffin, Charles E. (Inventor); Kuppermann, Aron (Inventor); Dreyer, William J. (Inventor); Boettger, Heinz G. (Inventor)

1982-01-01

An automated mass spectrometer analysis system is disclosed, in which samples are automatically processed in a sample processor and converted into volatilizable samples, or their characteristic volatilizable derivatives. Each volatilizable sample is sequentially volatilized and analyzed in a double focusing mass spectrometer, whose output is in the form of separate ion beams all of which are simultaneously focused in a focal plane. Each ion beam is indicative of a different sample component or different fragments of one or more sample components and the beam intensity is related to the relative abundance of the sample component. The system includes an electro-optical ion detector which automatically and simultaneously converts the ion beams, first into electron beams which in turn produce a related image which is transferred to the target of a vilicon unit. The latter converts the images into electrical signals which are supplied to a data processor, whose output is a list of the components of the analyzed sample and their abundances. The system is under the control of a master control unit, which in addition to monitoring and controlling various power sources, controls the automatic operation of the system under expected and some unexpected conditions and further protects various critical parts of the system from damage due to particularly abnormal conditions.

Automated mass spectrometer analysis system

NASA Technical Reports Server (NTRS)

Boettger, Heinz G. (Inventor); Giffin, Charles E. (Inventor); Dreyer, William J. (Inventor); Kuppermann, Aron (Inventor)

1978-01-01

An automated mass spectrometer analysis system is disclosed, in which samples are automatically processed in a sample processor and converted into volatilizable samples, or their characteristic volatilizable derivatives. Each volatizable sample is sequentially volatilized and analyzed in a double focusing mass spectrometer, whose output is in the form of separate ion beams all of which are simultaneously focused in a focal plane. Each ion beam is indicative of a different sample component or different fragments of one or more sample components and the beam intensity is related to the relative abundance of the sample component. The system includes an electro-optical ion detector which automatically and simultaneously converts the ion beams, first into electron beams which in turn produce a related image which is transferred to the target of a vidicon unit. The latter converts the images into electrical signals which are supplied to a data processor, whose output is a list of the components of the analyzed sample and their abundances. The system is under the control of a master control unit, which in addition to monitoring and controlling various power sources, controls the automatic operation of the system under expected and some unexpected conditions and further protects various critical parts of the system from damage due to particularly abnormal conditions.

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2013 CFR

2013-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2014 CFR

2014-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2010 CFR

2010-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2012 CFR

2012-10-01

..., INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements..., inspection, testing, and operating tasks that must be performed on a railroad's products. This includes the...

Smart Fan Modules And System

DOEpatents

Cipolla, Thomas M.; Kaufman, Richard I.; Mok, Lawrence S.

2003-07-15

A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals. A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

Advanced Beamformers for Cochlear Implant Users: Acute Measurement of Speech Perception in Challenging Listening Conditions

PubMed Central

Buechner, Andreas; Dyballa, Karl-Heinz; Hehrmann, Phillipp; Fredelake, Stefan; Lenarz, Thomas

2014-01-01

Objective To investigate the performance of monaural and binaural beamforming technology with an additional noise reduction algorithm, in cochlear implant recipients. Method This experimental study was conducted as a single subject repeated measures design within a large German cochlear implant centre. Twelve experienced users of an Advanced Bionics HiRes90K or CII implant with a Harmony speech processor were enrolled. The cochlear implant processor of each subject was connected to one of two bilaterally placed state-of-the-art hearing aids (Phonak Ambra) providing three alternative directional processing options: an omnidirectional setting, an adaptive monaural beamformer, and a binaural beamformer. A further noise reduction algorithm (ClearVoice) was applied to the signal on the cochlear implant processor itself. The speech signal was presented from 0° and speech shaped noise presented from loudspeakers placed at ±70°, ±135° and 180°. The Oldenburg sentence test was used to determine the signal-to-noise ratio at which subjects scored 50% correct. Results Both the adaptive and binaural beamformer were significantly better than the omnidirectional condition (5.3 dB±1.2 dB and 7.1 dB±1.6 dB (p<0.001) respectively). The best score was achieved with the binaural beamformer in combination with the ClearVoice noise reduction algorithm, with a significant improvement in SRT of 7.9 dB±2.4 dB (p<0.001) over the omnidirectional alone condition. Conclusions The study showed that the binaural beamformer implemented in the Phonak Ambra hearing aid could be used in conjunction with a Harmony speech processor to produce substantial average improvements in SRT of 7.1 dB. The monaural, adaptive beamformer provided an averaged SRT improvement of 5.3 dB. PMID:24755864

Development Of A Three-Dimensional Circuit Integration Technology And Computer Architecture

NASA Astrophysics Data System (ADS)

Etchells, R. D.; Grinberg, J.; Nudd, G. R.

1981-12-01

This paper is the first of a series 1,2,3 describing a range of efforts at Hughes Research Laboratories, which are collectively referred to as "Three-Dimensional Microelectronics." The technology being developed is a combination of a unique circuit fabrication/packaging technology and a novel processing architecture. The packaging technology greatly reduces the parasitic impedances associated with signal-routing in complex VLSI structures, while simultaneously allowing circuit densities orders of magnitude higher than the current state-of-the-art. When combined with the 3-D processor architecture, the resulting machine exhibits a one- to two-order of magnitude simultaneous improvement over current state-of-the-art machines in the three areas of processing speed, power consumption, and physical volume. The 3-D architecture is essentially that commonly referred to as a "cellular array", with the ultimate implementation having as many as 512 x 512 processors working in parallel. The three-dimensional nature of the assembled machine arises from the fact that the chips containing the active circuitry of the processor are stacked on top of each other. In this structure, electrical signals are passed vertically through the chips via thermomigrated aluminum feedthroughs. Signals are passed between adjacent chips by micro-interconnects. This discussion presents a broad view of the total effort, as well as a more detailed treatment of the fabrication and packaging technologies themselves. The results of performance simulations of the completed 3-D processor executing a variety of algorithms are also presented. Of particular pertinence to the interests of the focal-plane array community is the simulation of the UNICORNS nonuniformity correction algorithms as executed by the 3-D architecture.

Smart Sensors: Why and when the origin was and why and where the future will be

NASA Astrophysics Data System (ADS)

Corsi, C.

2013-12-01

Smart Sensors is a technique developed in the 70's when the processing capabilities, based on readout integrated with signal processing, was still far from the complexity needed in advanced IR surveillance and warning systems, because of the enormous amount of noise/unwanted signals emitted by operating scenario especially in military applications. The Smart Sensors technology was kept restricted within a close military environment exploding in applications and performances in the 90's years thanks to the impressive improvements in the integrated signal read-out and processing achieved by CCD-CMOS technologies in FPA. In fact the rapid advances of "very large scale integration" (VLSI) processor technology and mosaic EO detector array technology allowed to develop new generations of Smart Sensors with much improved signal processing by integrating microcomputers and other VLSI signal processors. inside the sensor structure achieving some basic functions of living eyes (dynamic stare, non-uniformity compensation, spatial and temporal filtering). New and future technologies (Nanotechnology, Bio-Organic Electronics, Bio-Computing) are lightning a new generation of Smart Sensors extending the Smartness from the Space-Time Domain to Spectroscopic Functional Multi-Domain Signal Processing. History and future forecasting of Smart Sensors will be reported.

Embedded neural recording with TinyOS-based wireless-enabled processor modules.

PubMed

Farshchi, Shahin; Pesterev, Aleksey; Nuyujukian, Paul; Guenterberg, Eric; Mody, Istvan; Judy, Jack W

2010-04-01

To create a wireless neural recording system that can benefit from the continuous advancements being made in embedded microcontroller and communications technologies, an embedded-system-based architecture for wireless neural recording has been designed, fabricated, and tested. The system consists of commercial-off-the-shelf wireless-enabled processor modules (motes) for communicating the neural signals, and a back-end database server and client application for archiving and browsing the neural signals. A neural-signal-acquisition application has been developed to enable the mote to either acquire neural signals at a rate of 4000 12-bit samples per second, or detect and transmit spike heights and widths sampled at a rate of 16670 12-bit samples per second on a single channel. The motes acquire neural signals via a custom low-noise neural-signal amplifier with adjustable gain and high-pass corner frequency that has been designed, and fabricated in a 1.5-microm CMOS process. In addition to browsing acquired neural data, the client application enables the user to remotely toggle modes of operation (real-time or spike-only), as well as amplifier gain and high-pass corner frequency.

A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

In this paper we present a formal model of asynchronous communication as a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into the signal stream consumed by an independently clocked processor. This transformation 'blurs' edges and 'dilates' time due to differences in the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on asynchronous communications at ISO protocol level 1 (physical level). We develop part of the reusable formal theory that permits the convenient application of the model. We use the theory to show that a biphase mark protocol can be used to send messages of arbitrary length between two asynchronous processors. We study two versions of the protocol, a conventional one which uses cells of size 32 cycles and an unconventional one which uses cells of size 18. We conjecture that the protocol can be proved to work under our model for smaller cell sizes and more divergent clock rates but the proofs would be harder.

Design and evaluation of an architecture for a digital signal processor for instrumentation applications

NASA Astrophysics Data System (ADS)

Fellman, Ronald D.; Kaneshiro, Ronald T.; Konstantinides, Konstantinos

1990-03-01

The authors present the design and evaluation of an architecture for a monolithic, programmable, floating-point digital signal processor (DSP) for instrumentation applications. An investigation of the most commonly used algorithms in instrumentation led to a design that satisfies the requirements for high computational and I/O (input/output) throughput. In the arithmetic unit, a 16- x 16-bit multiplier and a 32-bit accumulator provide the capability for single-cycle multiply/accumulate operations, and three format adjusters automatically adjust the data format for increased accuracy and dynamic range. An on-chip I/O unit is capable of handling data block transfers through a direct memory access port and real-time data streams through a pair of parallel I/O ports. I/O operations and program execution are performed in parallel. In addition, the processor includes two data memories with independent addressing units, a microsequencer with instruction RAM, and multiplexers for internal data redirection. The authors also present the structure and implementation of a design environment suitable for the algorithmic, behavioral, and timing simulation of a complete DSP system. Various benchmarking results are reported.

Uses of DARPA Materials Sciences Technology in DoD Systems.

DTIC Science & Technology

1996-05-01

and Lasers NUMBER: University of Central Florida 4000 Central Florida Blvd. P.O. Box 162700 Orlando, FL 32816-2700 9. S PONSO RIN GMO NITO RING AGENCY...course of the program. These advances were communicated to the industry through seminars and workshops, individual plant and agency visits, videotapes on...1995) • P3 ISAR Radar Processor * Digital Signal Processor for OH-58D helicopter * Motorola building a GaAs IC plant for IRIDIUM 26 GALLIUM ARSENIDE

Design and implementation of highly parallel pipelined VLSI systems

NASA Astrophysics Data System (ADS)

Delange, Alphonsus Anthonius Jozef

A methodology and its realization as a prototype CAD (Computer Aided Design) system for the design and analysis of complex multiprocessor systems is presented. The design is an iterative process in which the behavioral specifications of the system components are refined into structural descriptions consisting of interconnections and lower level components etc. A model for the representation and analysis of multiprocessor systems at several levels of abstraction and an implementation of a CAD system based on this model are described. A high level design language, an object oriented development kit for tool design, a design data management system, and design and analysis tools such as a high level simulator and graphics design interface which are integrated into the prototype system and graphics interface are described. Procedures for the synthesis of semiregular processor arrays, and to compute the switching of input/output signals, memory management and control of processor array, and sequencing and segmentation of input/output data streams due to partitioning and clustering of the processor array during the subsequent synthesis steps, are described. The architecture and control of a parallel system is designed and each component mapped to a module or module generator in a symbolic layout library, compacted for design rules of VLSI (Very Large Scale Integration) technology. An example of the design of a processor that is a useful building block for highly parallel pipelined systems in the signal/image processing domains is given.

Single-Scale Retinex Using Digital Signal Processors

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2005-01-01

The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.

Noise reduction technologies implemented in head-worn preprocessors for improving cochlear implant performance in reverberant noise fields.

PubMed

Chung, King; Nelson, Lance; Teske, Melissa

2012-09-01

The purpose of this study was to investigate whether a multichannel adaptive directional microphone and a modulation-based noise reduction algorithm could enhance cochlear implant performance in reverberant noise fields. A hearing aid was modified to output electrical signals (ePreprocessor) and a cochlear implant speech processor was modified to receive electrical signals (eProcessor). The ePreprocessor was programmed to flat frequency response and linear amplification. Cochlear implant listeners wore the ePreprocessor-eProcessor system in three reverberant noise fields: 1) one noise source with variable locations; 2) three noise sources with variable locations; and 3) eight evenly spaced noise sources from 0° to 360°. Listeners' speech recognition scores were tested when the ePreprocessor was programmed to omnidirectional microphone (OMNI), omnidirectional microphone plus noise reduction algorithm (OMNI + NR), and adaptive directional microphone plus noise reduction algorithm (ADM + NR). They were also tested with their own cochlear implant speech processor (CI_OMNI) in the three noise fields. Additionally, listeners rated overall sound quality preferences on recordings made in the noise fields. Results indicated that ADM+NR produced the highest speech recognition scores and the most preferable rating in all noise fields. Factors requiring attention in the hearing aid-cochlear implant integration process are discussed. Copyright © 2012 Elsevier B.V. All rights reserved.

Interactive digital signal processor

NASA Technical Reports Server (NTRS)

Mish, W. H.; Wenger, R. M.; Behannon, K. W.; Byrnes, J. B.

1982-01-01

The Interactive Digital Signal Processor (IDSP) is examined. It consists of a set of time series analysis Operators each of which operates on an input file to produce an output file. The operators can be executed in any order that makes sense and recursively, if desired. The operators are the various algorithms used in digital time series analysis work. User written operators can be easily interfaced to the sysatem. The system can be operated both interactively and in batch mode. In IDSP a file can consist of up to n (currently n=8) simultaneous time series. IDSP currently includes over thirty standard operators that range from Fourier transform operations, design and application of digital filters, eigenvalue analysis, to operators that provide graphical output, allow batch operation, editing and display information.

NSWC-NADC interactive communication links for AN/UYS-1 loadtape creation and retrieval

NASA Astrophysics Data System (ADS)

Greathouse, D. M.

1984-09-01

This report contains an alternative method of communication (interactive vs. remote batch) with the Naval Air Development Center for the creation and retrieval of AN/UYS-1 Advanced Signal Processor (ASP) operational software loadtapes. Operational software for the Digital Acoustic Sensor Simulator (DASS) program is developed and maintained at the Naval Air Development Center (NADC). The Facility for Automated Software Production (FASP), an NADC-resident software generation facility, provides the support tools necessary for data base creation, software development and maintenance, and loadtape generation. Once a loadtape file is generated at NADC, it must be retrieved via telephone transmission and placed in a format suitable for loading into the AN/UYS-1 Advanced Signal Processor (ASP).

Functional relevance of neurotransmitter receptor heteromers in the central nervous system.

PubMed

Ferré, Sergi; Ciruela, Francisco; Woods, Amina S; Lluis, Carme; Franco, Rafael

2007-09-01

The existence of neurotransmitter receptor heteromers is becoming broadly accepted and their functional significance is being revealed. Heteromerization of neurotransmitter receptors produces functional entities that possess different biochemical characteristics with respect to the individual components of the heteromer. Neurotransmitter receptor heteromers can function as processors of computations that modulate cell signaling. Thus, the quantitative or qualitative aspects of the signaling generated by stimulation of any of the individual receptor units in the heteromer are different from those obtained during coactivation. Furthermore, recent studies demonstrate that some neurotransmitter receptor heteromers can exert an effect as processors of computations that directly modulate both pre- and postsynaptic neurotransmission. This is illustrated by the analysis of striatal receptor heteromers that control striatal glutamatergic neurotransmission.

Miniature Intelligent Sensor Module

NASA Technical Reports Server (NTRS)

Beech, Russell S.

2007-01-01

An electronic unit denoted the Miniature Intelligent Sensor Module performs sensor-signal-conditioning functions and local processing of sensor data. The unit includes four channels of analog input/output circuitry, a processor, volatile and nonvolatile memory, and two Ethernet communication ports, all housed in a weathertight enclosure. The unit accepts AC or DC power. The analog inputs provide programmable gain, offset, and filtering as well as shunt calibration and auto-zeroing. Analog outputs include sine, square, and triangular waves having programmable frequencies and amplitudes, as well as programmable amplitude DC. One innovative aspect of the design of this unit is the integration of a relatively powerful processor and large amount of memory along with the sensor-signalconditioning circuitry so that sophisticated computer programs can be used to acquire and analyze sensor data and estimate and track the health of the overall sensor-data-acquisition system of which the unit is a part. The unit includes calibration, zeroing, and signalfeedback circuitry to facilitate health monitoring. The processor is also integrated with programmable logic circuitry in such a manner as to simplify and enhance acquisition of data and generation of analog outputs. A notable unique feature of the unit is a cold-junction compensation circuit in the back shell of a sensor connector. This circuit makes it possible to use Ktype thermocouples without compromising a housing seal. Replicas of this unit may prove useful in industrial and manufacturing settings - especially in such large outdoor facilities as refineries. Two features can be expected to simplify installation: the weathertight housings should make it possible to mount the units near sensors, and the Ethernet communication capability of the units should facilitate establishment of communication connections for the units.

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2013 CFR

2013-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2011 CFR

2011-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2012 CFR

2012-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2010 CFR

2010-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.925 - Training specific to control office personnel.

Code of Federal Regulations, 2014 CFR

2014-10-01

... concerning the interface between the computer-aided dispatching system and the train control system, with... INSTALLATION, INSPECTION, MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.925 Training specific to control office...

49 CFR 236.901 - Purpose and scope.

Code of Federal Regulations, 2010 CFR

2010-10-01

... control systems, subsystems, and components that are safety-critical products, as defined in § 236.903..., MAINTENANCE, AND REPAIR OF SIGNAL AND TRAIN CONTROL SYSTEMS, DEVICES, AND APPLIANCES Standards for Processor-Based Signal and Train Control Systems § 236.901 Purpose and scope. (a) What is the purpose of this...

A miniature batteryless health and usage monitoring system based on hybrid energy harvesting

NASA Astrophysics Data System (ADS)

Huang, Chenling; Chakrabartty, Shantanu

2011-04-01

The cost and size of the state-of-the-art health and usage monitoring systems (HUMS) are determined by capacity of on-board energy storage which limits their large scale deployment. In this paper, we present a miniature low-cost mechanical HUMS integrated circuit (IC) based on the concept of hybrid energy harvesting where continuous monitoring is achieved by self-powering, where as the programming, localization and communication with the sensor is achieved using remote RF powering. The self-powered component of the proposed HUMS is based on our previous result which used a controllable hot electron injection on floatinggate transistor as an ultra-low power signal processor. We show that the HUMS IC can seamlessly switch between different energy harvesting modes based on the availability of ambient RF power and that the configuration, programming and communication functions can be remotely performed without physically accessing the HUMS device. All the measured results presented in this paper have been obtained from prototypes fabricated in a 0.5 micron standard CMOS process and the entire system has been successfully integrated on a 1.5cm x 1.5cm package.

Glucose monitoring system using nanopellets.

PubMed

Rajasekaran, C; Nirmala, Madian; Jayanthi, K B

2017-02-01

The combination of the fields of software engineering, gadgets, and science has stood out among the most revolutionary future innovations. Health issues have been the focus of various engaging and explanatory studies. One such health-related dilemma is diabetes. Diabetes at its serious stage results in impaired vision. Increase in the glucose level is a critical parameter that could result in hyperglycaemia, hypoglycaemia, massive heart attack, strokes, and aneurysms. Monitoring the glucose level in blood is one of the control measures for diabetes in the affected population. A glucose monitoring framework interminably measures and screens the glucose level in blood. A novel framework for measuring the glucose level is proposed in this study. This study employs nanopellets that evaluate the glucose level. When the glucose level increases or decreases, it is continuously recorded and displayed using a microcontroller (mixed signal processor (MSP) 430). The data are then sent to the physician through global system for mobile communication. The typical blood glucose level of human being ranges from 70 to 110 mg/dl. When the insulin level builds up to certain point, hyperglycaemia occurs. When decreases, hypoglycaemia occurs. Hyperglycaemia leads to cataracts, oedema, hypertension, polyuria, and polydipsia. Hypoglycaemia causes perplexity, energy, insensateness, coma, and death.

Behavior-Based Fault Monitoring

DTIC Science & Technology

1990-12-03

processor targeted for avionics and space applications . It appears that the signature monitoring technique can be extended to detect computer viruses as...most common approach is structural duplication. Although effective, duplication is too expensive for all but a few applications . Redundancy can also be...Signature Monitoring and Encryption," Int. Conf. on Dependable Computing for Critical Applications , August 1989. 7. K.D. Wilken and J.P. Shen

Adaptive linear predictor FIR filter based on the Cyclone V FPGA with HPS to reduce narrow band RFI in AERA radio detection of cosmic rays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Szadkowski, Zbigniew

We present the new approach to a filtering of radio frequency interferences (RFI) in the Auger Engineering Radio Array (AERA) which study the electromagnetic part of the Extensive Air Showers. The radio stations can observe radio signals caused by coherent emissions due to geomagnetic radiation and charge excess processes. AERA observes frequency band from 30 to 80 MHz. This range is highly contaminated by human-made RFI. In order to improve the signal to noise ratio RFI filters are used in AERA to suppress this contamination. The first kind of filter used by AERA was the Median one, based on themore » Fast Fourier Transform (FFT) technique. The second one, which is currently in use, is the infinite impulse response (IIR) notch filter. The proposed new filter is a finite impulse response (FIR) filter based on a linear prediction (LP). A periodic contamination hidden in a registered signal (digitized in the ADC) can be extracted and next subtracted to make signal cleaner. The FIR filter requires a calculation of n=32, 64 or even 128 coefficients (dependent on a required speed or accuracy) by solving of n linear equations with coefficients built from the covariance Toeplitz matrix. This matrix can be solved by the Levinson recursion, which is much faster than the Gauss procedure. The filter has been already tested in the real AERA radio stations on Argentinean pampas with a very successful results. The linear equations were solved either in the virtual soft-core NIOSR processor (implemented in the FPGA chip as a net of logic elements) or in the external Voipac PXA270M ARM processor. The NIOS processor is relatively slow (50 MHz internal clock), calculations performed in an external processor consume a significant amount of time for data exchange between the FPGA and the processor. Test showed a very good efficiency of the RFI suppression for stationary (long-term) contaminations. However, we observed a short-time contaminations, which could not be suppressed either by the IIR-notch filter or by the FIR filter based on the linear predictions. For the LP FIR filter the refreshment time of the filter coefficients was to long and filter did not keep up with the changes of a contamination structure, mainly due to a long calculation time in a slow processors. We propose to use the Cyclone V SE chip with embedded micro-controller operating with 925 MHz internal clock to significantly reduce a refreshment time of the FIR coefficients. The lab results are promising. (authors)« less

Development of the SEASIS instrument for SEDSAT

NASA Technical Reports Server (NTRS)

Maier, Mark W.

1996-01-01

Two SEASIS experiment objectives are key: take images that allow three axis attitude determination and take multi-spectral images of the earth. During the tether mission it is also desirable to capture images for the recoiling tether from the endmass perspective (which has never been observed). SEASIS must store all its imagery taken during the tether mission until the earth downlink can be established. SEASIS determines attitude with a panoramic camera and performs earth observation with a telephoto lens camera. Camera video is digitized, compressed, and stored in solid state memory. These objectives are addressed through the following architectural choices: (1) A camera system using a Panoramic Annular Lens (PAL). This lens has a 360 deg. azimuthal field of view by a +45 degree vertical field measured from a plan normal to the lens boresight axis. It has been shown in Mr. Mark Steadham's UAH M.S. thesis that his camera can determine three axis attitude anytime the earth and one other recognizable celestial object (for example, the sun) is in the field of view. This will be essentially all the time during tether deployment. (2) A second camera system using telephoto lens and filter wheel. The camera is a black and white standard video camera. The filters are chosen to cover the visible spectral bands of remote sensing interest. (3) A processor and mass memory arrangement linked to the cameras. Video signals from the cameras are digitized, compressed in the processor, and stored in a large static RAM bank. The processor is a multi-chip module consisting of a T800 Transputer and three Zoran floating point Digital Signal Processors. This processor module was supplied under ARPA contract by the Space Computer Corporation to demonstrate its use in space.

High coherence plane breaking packaging for superconducting qubits.

PubMed

Bronn, Nicholas T; Adiga, Vivekananda P; Olivadese, Salvatore B; Wu, Xian; Chow, Jerry M; Pappas, David P

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

High coherence plane breaking packaging for superconducting qubits

NASA Astrophysics Data System (ADS)

Bronn, Nicholas T.; Adiga, Vivekananda P.; Olivadese, Salvatore B.; Wu, Xian; Chow, Jerry M.; Pappas, David P.

2018-04-01

We demonstrate a pogo pin package for a superconducting quantum processor specifically designed with a nontrivial layout topology (e.g., a center qubit that cannot be accessed from the sides of the chip). Two experiments on two nominally identical superconducting quantum processors in pogo packages, which use commercially available parts and require modest machining tolerances, are performed at low temperature (10 mK) in a dilution refrigerator and both found to behave comparably to processors in standard planar packages with wirebonds where control and readout signals come in from the edges. Single- and two-qubit gate errors are also characterized via randomized benchmarking, exhibiting similar error rates as in standard packages, opening the possibility of integrating pogo pin packaging with extensible qubit architectures.

Design of a system based on DSP and FPGA for video recording and replaying

NASA Astrophysics Data System (ADS)

Kang, Yan; Wang, Heng

2013-08-01

This paper brings forward a video recording and replaying system with the architecture of Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). The system achieved encoding, recording, decoding and replaying of Video Graphics Array (VGA) signals which are displayed on a monitor during airplanes and ships' navigating. In the architecture, the DSP is a main processor which is used for a large amount of complicated calculation during digital signal processing. The FPGA is a coprocessor for preprocessing video signals and implementing logic control in the system. In the hardware design of the system, Peripheral Device Transfer (PDT) function of the External Memory Interface (EMIF) is utilized to implement seamless interface among the DSP, the synchronous dynamic RAM (SDRAM) and the First-In-First-Out (FIFO) in the system. This transfer mode can avoid the bottle-neck of the data transfer and simplify the circuit between the DSP and its peripheral chips. The DSP's EMIF and two level matching chips are used to implement Advanced Technology Attachment (ATA) protocol on physical layer of the interface of an Integrated Drive Electronics (IDE) Hard Disk (HD), which has a high speed in data access and does not rely on a computer. Main functions of the logic on the FPGA are described and the screenshots of the behavioral simulation are provided in this paper. In the design of program on the DSP, Enhanced Direct Memory Access (EDMA) channels are used to transfer data between the FIFO and the SDRAM to exert the CPU's high performance on computing without intervention by the CPU and save its time spending. JPEG2000 is implemented to obtain high fidelity in video recording and replaying. Ways and means of acquiring high performance for code are briefly present. The ability of data processing of the system is desirable. And smoothness of the replayed video is acceptable. By right of its design flexibility and reliable operation, the system based on DSP and FPGA for video recording and replaying has a considerable perspective in analysis after the event, simulated exercitation and so forth.

Spectral Structure Of Phase-Induced Intensity Noise In Recirculating Delay Lines

NASA Astrophysics Data System (ADS)

Tur, M.; Moslehi, B.; Bowers, J. E.; Newton, S. A.; Jackson, K. P.; Goodman, J. W.; Cutler, C. C.; Shaw, H. J.

1983-09-01

The dynamic range of fiber optic signal processors driven by relatively incoherent multimode semiconductor lasers is shown to be severely limited by laser phase-induced noise. It is experimentally demonstrated that while the noise power spectrum of differential length fiber filters is approximately flat, processors with recirculating loops exhibit noise with a periodically structured power spectrum with notches at zero frequency as well as at all other multiples of 1/(loop delay). The experimental results are aug-mented by a theoretical analysis.

FANTOM: Algorithm-Architecture Codesign for High-Performance Embedded Signal and Image Processing Systems

DTIC Science & Technology

2013-05-25

graphics processors by IBM, AMD, and nVIDIA . They are between general-purpose pro- cessors and special-purpose processors. In Phase II. 3.10 Measure of...particular, Dr. Kevin Irick started a company Silicon Scapes and he has been the CEO. 5 Implications for Related/Future Research We speculate that...final project report in Jan. 2011. At the test and validation stage of the project. FANTOM’s partner at Raytheon quit from his company and hence from

Power estimation on functional level for programmable processors

NASA Astrophysics Data System (ADS)

Schneider, M.; Blume, H.; Noll, T. G.

2004-05-01

In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input parameters of the Correspondence to: H. Blume (blume@eecs.rwth-aachen.de) arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. This approach is exemplarily demonstrated and evaluated applying two modern digital signal processors and a variety of basic algorithms of digital signal processing. The resulting estimation values for the inspected algorithms are compared to physically measured values. A resulting maximum estimation error of 3% is achieved.

Vestibular receptor cells and signal detection: bioaccelerometers and the hexagonal sampling of two-dimensional signals

NASA Technical Reports Server (NTRS)

Mugler, D. H.; Ross, M. D.

1990-01-01

The inner ear contains sensory organs which signal changes in head movement. The vestibular sacs, in particular, are sensitive to linear accelerations. Electron microscopic images have revealed the structure of tiny sensory hair bundles, whose mechanical deformation results in the initiation of neuronal activity and the transmission of electrical signals to the brain. The structure of the hair bundles is shown in this paper to be that of the most efficient two-dimensional phased-array signal processors.

The Effects of High-Altitude Electromagnetic Pulse (HEMP) on Telecommunications Assets

DTIC Science & Technology

1988-06-01

common to a whole class of switches. 5ESS switch software controls the operating system, call processing, and system administration andgmaintenance...LEVEL (ky/rn)3 (a). Mean Fraction of Preset Calls Dropped Due to Induced Transients3 1.0 W -o35kVhM (36 EVENTS) 5-40 kV/M (13 EVENTS) IAUTOMATIC ...eel PERIPHRAL UNIT BUS,IMNA The entire 4ESS system is controlled by the 1A processor. The processor monitors and controls the operation of the

Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals

DOEpatents

Balasubramonian, Rajeev [Sandy, UT; Dwarkadas, Sandhya [Rochester, NY; Albonesi, David [Ithaca, NY

2009-02-10

In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used until the next phase change is detected. The optimum instruction interval is determined by starting with a minimum interval and doubling it until a low stability factor is reached.

49 CFR 234.275 - Processor-based systems.

Code of Federal Regulations, 2011 CFR

2011-10-01

... new or novel technology, or which provide safety-critical data to a railroad signal or train control... requirements. New or novel technology refers to a technology not previously recognized for use as of March 7... but which provides safety-critical data to a signal or train control system shall be included in the...

49 CFR 234.275 - Processor-based systems.

Code of Federal Regulations, 2010 CFR

2010-10-01

... new or novel technology, or which provide safety-critical data to a railroad signal or train control... requirements. New or novel technology refers to a technology not previously recognized for use as of March 7... but which provides safety-critical data to a signal or train control system shall be included in the...

Video signal processing system uses gated current mode switches to perform high speed multiplication and digital-to-analog conversion

NASA Technical Reports Server (NTRS)

Gilliland, M. G.; Rougelot, R. S.; Schumaker, R. A.

1966-01-01

Video signal processor uses special-purpose integrated circuits with nonsaturating current mode switching to accept texture and color information from a digital computer in a visual spaceflight simulator and to combine these, for display on color CRT with analog information concerning fading.

Role of a transductional-transcriptional processor complex involving MyD88 and IRF-7 in Toll-like receptor signaling

PubMed Central

Honda, Kenya; Yanai, Hideyuki; Mizutani, Tatsuaki; Negishi, Hideo; Shimada, Naoya; Suzuki, Nobutaka; Ohba, Yusuke; Takaoka, Akinori; Yeh, Wen-Chen; Taniguchi, Tadatsugu

2004-01-01

Toll-like receptor (TLR) activation is central to immunity, wherein the activation of the TLR9 subfamily members TLR9 and TLR7 results in the robust induction of type I IFNs (IFN-α/β) by means of the MyD88 adaptor protein. However, it remains unknown how the TLR signal “input” can be processed through MyD88 to “output” the induction of the IFN genes. Here, we demonstrate that the transcription factor IRF-7 interacts with MyD88 to form a complex in the cytoplasm. We provide evidence that this complex also involves IRAK4 and TRAF6 and provides the foundation for the TLR9-dependent activation of the IFN genes. The complex defined in this study represents an example of how the coupling of the signaling adaptor and effector kinase molecules together with the transcription factor regulate the processing of an extracellular signal to evoke its versatile downstream transcriptional events in a cell. Thus, we propose that this molecular complex may function as a cytoplasmic transductional-transcriptional processor. PMID:15492225

Real-Time Neural Signals Decoding onto Off-the-Shelf DSP Processors for Neuroprosthetic Applications.

PubMed

Pani, Danilo; Barabino, Gianluca; Citi, Luca; Meloni, Paolo; Raspopovic, Stanisa; Micera, Silvestro; Raffo, Luigi

2016-09-01

The control of upper limb neuroprostheses through the peripheral nervous system (PNS) can allow restoring motor functions in amputees. At present, the important aspect of the real-time implementation of neural decoding algorithms on embedded systems has been often overlooked, notwithstanding the impact that limited hardware resources have on the efficiency/effectiveness of any given algorithm. Present study is addressing the optimization of a template matching based algorithm for PNS signals decoding that is a milestone for its real-time, full implementation onto a floating-point digital signal processor (DSP). The proposed optimized real-time algorithm achieves up to 96% of correct classification on real PNS signals acquired through LIFE electrodes on animals, and can correctly sort spikes of a synthetic cortical dataset with sufficiently uncorrelated spike morphologies (93% average correct classification) comparably to the results obtained with top spike sorter (94% on average on the same dataset). The power consumption enables more than 24 h processing at the maximum load, and latency model has been derived to enable a fair performance assessment. The final embodiment demonstrates the real-time performance onto a low-power off-the-shelf DSP, opening to experiments exploiting the efferent signals to control a motor neuroprosthesis.

The design of infrared information collection circuit based on embedded technology

NASA Astrophysics Data System (ADS)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

A scalable SIMD digital signal processor for high-quality multifunctional printer systems

NASA Astrophysics Data System (ADS)

Kang, Hyeong-Ju; Choi, Yongwoo; Kim, Kimo; Park, In-Cheol; Kim, Jung-Wook; Lee, Eul-Hwan; Gahang, Goo-Soo

2005-01-01

This paper describes a high-performance scalable SIMD digital signal processor (DSP) developed for multifunctional printer systems. The DSP supports a variable number of datapaths to cover a wide range of performance and maintain a RISC-like pipeline structure. Many special instructions suitable for image processing algorithms are included in the DSP. Quad/dual instructions are introduced for 8-bit or 16-bit data, and bit-field extraction/insertion instructions are supported to process various data types. Conditional instructions are supported to deal with complex relative conditions efficiently. In addition, an intelligent DMA block is integrated to align data in the course of data reading. Experimental results show that the proposed DSP outperforms a high-end printer-system DSP by at least two times.

An autonomous receiver/digital signal processor applied to ground-based and rocket-borne wave experiments

NASA Astrophysics Data System (ADS)

Dombrowski, M. P.; LaBelle, J.; McGaw, D. G.; Broughton, M. C.

2016-07-01

The programmable combined receiver/digital signal processor platform presented in this article is designed for digital downsampling and processing of general waveform inputs with a 66 MHz initial sampling rate and multi-input synchronized sampling. Systems based on this platform are capable of fully autonomous low-power operation, can be programmed to preprocess and filter the data for preselection and reduction, and may output to a diverse array of transmission or telemetry media. We describe three versions of this system, one for deployment on sounding rockets and two for ground-based applications. The rocket system was flown on the Correlation of High-Frequency and Auroral Roar Measurements (CHARM)-II mission launched from Poker Flat Research Range, Alaska, in 2010. It measured auroral "roar" signals at 2.60 MHz. The ground-based systems have been deployed at Sondrestrom, Greenland, and South Pole Station, Antarctica. The Greenland system synchronously samples signals from three spaced antennas providing direction finding of 0-5 MHz waves. It has successfully measured auroral signals and man-made broadcast signals. The South Pole system synchronously samples signals from two crossed antennas, providing polarization information. It has successfully measured the polarization of auroral kilometric radiation-like signals as well as auroral hiss. Further systems are in development for future rocket missions and for installation in Antarctic Automatic Geophysical Observatories.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ringbus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection arid the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Optical interconnection using polyimide waveguide for multichip module

NASA Astrophysics Data System (ADS)

Koyanagi, Mitsumasa

1996-01-01

We have developed a parallel processor system with 152 RISC processor chips specific for Monte-Carlo analysis. This system has the ring-bus architecture. The performance of several Gflops is expected in this system according to the computer simulation. However, it was revealed that the data transfer speed of the bus has to be increased more dramatically in order to further increase the performance. Then, we propose to introduce the optical interconnection into the parallel processor system to increase the data transfer speed of the buses. The double ring-bus architecture is employed in this new parallel processor system with optical interconnection. The free-space optical interconnection and the optical waveguide are used for the optical ring-bus. Thin polyimide film was used to form the optical waveguide. A relatively low propagation loss was achieved in the polyimide optical waveguide. In addition, it was confirmed that the propagation direction of signal light can be easily changed by using a micro-mirror.

Real-Time Spatio-Temporal Twice Whitening for MIMO Energy Detector

DOE Office of Scientific and Technical Information (OSTI.GOV)

Humble, Travis S; Mitra, Pramita; Barhen, Jacob

2010-01-01

While many techniques exist for local spectrum sensing of a primary user, each represents a computationally demanding task to secondary user receivers. In software-defined radio, computational complexity lengthens the time for a cognitive radio to recognize changes in the transmission environment. This complexity is even more significant for spatially multiplexed receivers, e.g., in SIMO and MIMO, where the spatio-temporal data sets grow in size with the number of antennae. Limits on power and space for the processor hardware further constrain SDR performance. In this report, we discuss improvements in spatio-temporal twice whitening (STTW) for real-time local spectrum sensing by demonstratingmore » a form of STTW well suited for MIMO environments. We implement STTW on the Coherent Logix hx3100 processor, a multicore processor intended for low-power, high-throughput software-defined signal processing. These results demonstrate how coupling the novel capabilities of emerging multicore processors with algorithmic advances can enable real-time, software-defined processing of large spatio-temporal data sets.« less

Developing infrared array controller with software real time operating system

NASA Astrophysics Data System (ADS)

Sako, Shigeyuki; Miyata, Takashi; Nakamura, Tomohiko; Motohara, Kentaro; Uchimoto, Yuka Katsuno; Onaka, Takashi; Kataza, Hirokazu

2008-07-01

Real-time capabilities are required for a controller of a large format array to reduce a dead-time attributed by readout and data transfer. The real-time processing has been achieved by dedicated processors including DSP, CPLD, and FPGA devices. However, the dedicated processors have problems with memory resources, inflexibility, and high cost. Meanwhile, a recent PC has sufficient resources of CPUs and memories to control the infrared array and to process a large amount of frame data in real-time. In this study, we have developed an infrared array controller with a software real-time operating system (RTOS) instead of the dedicated processors. A Linux PC equipped with a RTAI extension and a dual-core CPU is used as a main computer, and one of the CPU cores is allocated to the real-time processing. A digital I/O board with DMA functions is used for an I/O interface. The signal-processing cores are integrated in the OS kernel as a real-time driver module, which is composed of two virtual devices of the clock processor and the frame processor tasks. The array controller with the RTOS realizes complicated operations easily, flexibly, and at a low cost.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

50 CFR 648.206 - Framework provisions.

Code of Federal Regulations, 2011 CFR

2011-10-01

... deducted when determining specifications; (8) Distribution of the ACL; (9) Gear restrictions (such as mesh... and bycatch monitoring; (27) Requirements for a herring processor survey; (28) ACL set-aside amounts...

50 CFR 648.206 - Framework provisions.

Code of Federal Regulations, 2013 CFR

2013-10-01

... deducted when determining specifications; (8) Distribution of the ACL; (9) Gear restrictions (such as mesh... and bycatch monitoring; (27) Requirements for a herring processor survey; (28) ACL set-aside amounts...

50 CFR 648.206 - Framework provisions.

Code of Federal Regulations, 2014 CFR

2014-10-01

... deducted when determining specifications; (8) Distribution of the ACL; (9) Gear restrictions (such as mesh... and bycatch monitoring; (27) Requirements for a herring processor survey; (28) ACL set-aside amounts...

50 CFR 648.206 - Framework provisions.

Code of Federal Regulations, 2012 CFR

2012-10-01

... deducted when determining specifications; (8) Distribution of the ACL; (9) Gear restrictions (such as mesh... and bycatch monitoring; (27) Requirements for a herring processor survey; (28) ACL set-aside amounts...

Neutron multiplicity counting: Confidence intervals for reconstruction parameters

DOE PAGES

Verbeke, Jerome M.

2016-03-09

From nuclear materials accountability to homeland security, the need for improved nuclear material detection, assay, and authentication has grown over the past decades. Starting in the 1940s, neutron multiplicity counting techniques have enabled quantitative evaluation of masses and multiplications of fissile materials. In this paper, we propose a new method to compute uncertainties on these parameters using a model-based sequential Bayesian processor, resulting in credible regions in the fissile material mass and multiplication space. These uncertainties will enable us to evaluate quantitatively proposed improvements to the theoretical fission chain model. Additionally, because the processor can calculate uncertainties in real time,more » it is a useful tool in applications such as portal monitoring: monitoring can stop as soon as a preset confidence of non-threat is reached.« less

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy.

PubMed

Mehta, M M; Chandrasekhar, V

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

NASA Astrophysics Data System (ADS)

Mehta, M. M.; Chandrasekhar, V.

2014-01-01

Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

PubMed

He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

2015-07-14

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

Embedded Implementation of VHR Satellite Image Segmentation

PubMed Central

Li, Chao; Balla-Arabé, Souleymane; Ginhac, Dominique; Yang, Fan

2016-01-01

Processing and analysis of Very High Resolution (VHR) satellite images provide a mass of crucial information, which can be used for urban planning, security issues or environmental monitoring. However, they are computationally expensive and, thus, time consuming, while some of the applications, such as natural disaster monitoring and prevention, require high efficiency performance. Fortunately, parallel computing techniques and embedded systems have made great progress in recent years, and a series of massively parallel image processing devices, such as digital signal processors or Field Programmable Gate Arrays (FPGAs), have been made available to engineers at a very convenient price and demonstrate significant advantages in terms of running-cost, embeddability, power consumption flexibility, etc. In this work, we designed a texture region segmentation method for very high resolution satellite images by using the level set algorithm and the multi-kernel theory in a high-abstraction C environment and realize its register-transfer level implementation with the help of a new proposed high-level synthesis-based design flow. The evaluation experiments demonstrate that the proposed design can produce high quality image segmentation with a significant running-cost advantage. PMID:27240370

A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

PubMed Central

He, Diwei; Morgan, Stephen P.; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R.

2015-01-01

Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring. PMID:26184225

Real-time optical signal processors employing optical feedback: amplitude and phase control.

PubMed

Gallagher, N C

1976-04-01

The development of real-time coherent optical signal processors has increased the appeal of optical computing techniques in signal processing applications. A major limitation of these real-time systems is the. fact that the optical processing material is generally of a phase-only type. The result is that the spatial filters synthesized with these systems must be either phase-only filters or amplitude-only filters. The main concern of this paper is the application of optical feedback techniques to obtain simultaneous and independent amplitude and phase control of the light passing through the system. It is shown that optical feedback techniques may be employed with phase-only spatial filters to obtain this amplitude and phase control. The feedback system with phase-only filters is compared with other feedback systems that employ combinations of phase-only and amplitude-only filters; it is found that the phase-only system is substantially more flexible than the other two systems investigated.

Compact lidar system using laser diode, binary continuous wave power modulation, and an avalanche photodiode-based receiver controlled by a digital signal processor

NASA Astrophysics Data System (ADS)

Ardanuy, Antoni; Comerón, Adolfo

2018-04-01

We analyze the practical limits of a lidar system based on the use of a laser diode, random binary continuous wave power modulation, and an avalanche photodiode (APD)-based photereceiver, combined with the control and computing power of the digital signal processors (DSP) currently available. The target is to design a compact portable lidar system made all in semiconductor technology, with a low-power demand and an easy configuration of the system, allowing change in some of its features through software. Unlike many prior works, we emphasize the use of APDs instead of photomultiplier tubes to detect the return signal and the application of the system to measure not only hard targets, but also medium-range aerosols and clouds. We have developed an experimental prototype to evaluate the behavior of the system under different environmental conditions. Experimental results provided by the prototype are presented and discussed.

Method and apparatus for combinatorial logic signal processor in a digitally based high speed x-ray spectrometer

DOEpatents

Warburton, William K.; Zhou, Zhiquing

1999-01-01

A high speed, digitally based, signal processing system which accepts a digitized input signal and detects the presence of step-like pulses in the this data stream, extracts filtered estimates of their amplitudes, inspects for pulse pileup, and records input pulse rates and system livetime. The system has two parallel processing channels: a slow channel, which filters the data stream with a long time constant trapezoidal filter for good energy resolution; and a fast channel which filters the data stream with a short time constant trapezoidal filter, detects pulses, inspects for pileups, and captures peak values from the slow channel for good events. The presence of a simple digital interface allows the system to be easily integrated with a digital processor to produce accurate spectra at high count rates and allow all spectrometer functions to be fully automated. Because the method is digitally based, it allows pulses to be binned based on time related values, as well as on their amplitudes, if desired.

Acousto-optic time- and space-integrating spotlight-mode SAR processor

NASA Astrophysics Data System (ADS)

Haney, Michael W.; Levy, James J.; Michael, Robert R., Jr.

1993-09-01

The technical approach and recent experimental results for the acousto-optic time- and space- integrating real-time SAR image formation processor program are reported. The concept overcomes the size and power consumption limitations of electronic approaches by using compact, rugged, and low-power analog optical signal processing techniques for the most computationally taxing portions of the SAR imaging problem. Flexibility and performance are maintained by the use of digital electronics for the critical low-complexity filter generation and output image processing functions. The results include a demonstration of the processor's ability to perform high-resolution spotlight-mode SAR imaging by simultaneously compensating for range migration and range/azimuth coupling in the analog optical domain, thereby avoiding a highly power-consuming digital interpolation or reformatting operation usually required in all-electronic approaches.

Design and test of a regenerative satellite transmultiplexer

NASA Astrophysics Data System (ADS)

Hung, Kenny King-Ming

1993-05-01

In a multiple access scheme for regenerative satellite communications, the bulk frequency division multiple access (FDMA) uplink signal is demodulated on board the satellite and then remodulated for time division multiplexing (TDM) downlink transmission. Conversion from frequency to time division multiplex format requires that the uplink signal be frequency demultiplexed and each individual carrier be subsequently demodulated. For thin-route application which consists of a large number of channels with fixed data rate, multicarrier demodulation can be accomplished efficiently by a digital transmultiplexer (TMUX) using a fast Fourier transform processor followed by a bank of per-channel processors. A time domain description of the TMUX algorithm is derived which elucidates how the TMUX functions. The per-channel processor performs timing and carrier recovery for optimum and coherent data detection. Timing recovery is necessarily achieved asynchronously by a filter coefficient interpolation. Carrier recovery is performed using an all-digital phase-locked loop. The combination of both timing and carrier loops is investigated for a multi-user system. The performance of the overall system is assessed over a multi-user, additive white Gaussian noise channel for a bit energy to noise power spectral density ratio down to zero dB.

Implementation of a level 1 trigger system using high speed serial (VXS) techniques for the 12GeV high luminosity experimental programs at Thomas Jefferson National Accelerator Facility

DOE Office of Scientific and Technical Information (OSTI.GOV)

C. Cuevas, B. Raydo, H. Dong, A. Gupta, F.J. Barbosa, J. Wilson, W.M. Taylor, E. Jastrzembski, D. Abbott

We will demonstrate a hardware and firmware solution for a complete fully pipelined multi-crate trigger system that takes advantage of the elegant high speed VXS serial extensions for VME. This trigger system includes three sections starting with the front end crate trigger processor (CTP), a global Sub-System Processor (SSP) and a Trigger Supervisor that manages the timing, synchronization and front end event readout. Within a front end crate, trigger information is gathered from each 16 Channel, 12 bit Flash ADC module at 4 nS intervals via the VXS backplane, to a Crate Trigger Processor (CTP). Each Crate Trigger Processor receivesmore » these 500 MB/S VXS links from the 16 FADC-250 modules, aligns skewed data inherent of Aurora protocol, and performs real time crate level trigger algorithms. The algorithm results are encoded using a Reed-Solomon technique and transmission of this Level 1 trigger data is sent to the SSP using a multi-fiber link. The multi-fiber link achieves an aggregate trigger data transfer rate to the global trigger at 8 Gb/s. The SSP receives and decodes Reed-Solomon error correcting transmission from each crate, aligns the data, and performs the global level trigger algorithms. The entire trigger system is synchronous and operates at 250 MHz with the Trigger Supervisor managing not only the front end event readout, but also the distribution of the critical timing clocks, synchronization signals, and the global trigger signals to each front end readout crate. These signals are distributed to the front end crates on a separate fiber link and each crate is synchronized using a unique encoding scheme to guarantee that each front end crate is synchronous with a fixed latency, independent of the distance between each crate. The overall trigger signal latency is <3 uS, and the proposed 12GeV experiments at Jefferson Lab require up to 200KHz Level 1 trigger rate.« less

Generalized Monitoring Facility. Users Manual.

DTIC Science & Technology

1982-05-01

based monitor. The RMC will sample system queues and tables on a 30-second time interval. The data captured from these queues and cells are written...period, only the final change will be reported. The following communication region cells are constantly monitored for changes, since a processor...is reported as zeros in WW6.4. When GMC terminates, it writes a record containing information read from communication region cells and information

The automatic control system and stand-by facilities of the TDMA-40 equipment

NASA Astrophysics Data System (ADS)

Gudenko, D. V.; Pankov, G. Kh.; Pauk, A. G.; Tsirlin, V. M.

1980-10-01

When a controlling station in a satellite communications system is out of order, a complex algorithm must be carried out for automatic operation of the stand-by equipment. A processor has been developed to perform this algorithm, as well as operations involving the stand-by facilities of the receiving-transmitting equipment of the station. The design principles and solutions to problems in developing the equipment for the monitoring and controlling systems are described. These systems are based on multistation access using time division multiplexing. Algorithms are presented for the operation of the synchronizing processor and the control processor of the equipment. The automatic control system and stand-by facilities make it possible to reduce the service personnel and to design an unattended station.

A Digital Signal Processor for Doppler Radar Sensing of Vital Signs

DTIC Science & Technology

2001-10-25

shows a small spike halfway each heartbeat. This is known as the dicrotic notch , which signifies a sudden drop in pressure after systolic contraction...It is caused by a small reflux flow of blood back into the aortic valve and coronary vessels. This dicrotic notch in the heart signal is clipped...signal, and amax was the maximum amplitude of the signal in the specified window. The user could set the factor k, and it determined the threshold at

Initial in vitro and in vivo evaluation of a self-monitoring prosthetic bypass graft.

PubMed

Neville, Richard F; Gupta, Samit K; Kuraguntla, David J

2017-06-01

Prosthetic grafts used for lower extremity revascularization and dialysis access fail because of hyperplastic stenosis and thrombosis. Graft surveillance is advocated to monitor function; however, graft failure can occur between episodic examinations. An innovative sensor with wireless, microchip technology allows automated surveillance with assessment of graft function using a "cloud"-based algorithm. We performed proof-of-concept experiments with in vitro and in vivo models to assess the feasibility such a real-time graft surveillance system. A self-monitoring graft system was evaluated consisting of a prosthetic conduit of expanded polytetrafluoroethylene and a sensor unit, and a microsensor, microelectronics, battery, and remote processor with a monitor. The sensor unit was integrated on the extraluminal surface of expanded polytetrafluoroethylene grafts without compromise to the lumen of the conduit. The grafts were tested in vitro in a pulsatile, recirculating flow system under physiologic flow parameters. The hemodynamic parameters were varied to assess the ability to obtain wireless signal acquisition reflecting real-time flow properties in vitro. Segments of custom tubing with reduced diameters were inserted into the model to mimic stenosis proximal and distal to the grafts. After characterization of the initial data, the self-monitoring grafts were implanted in an ovine carotid model to assess proof of concept in vivo with 30-day follow-up of signal acquisition as well as arteriographic and histologic analysis. In vitro flow data demonstrated the device was able to determine factors related to prosthetic graft function under varied hemodynamic flow conditions. Wireless signal acquisition using Bluetooth technology (Bluetooth SIG, Inc, Kirkland, Wash) allowed remote data analysis reflecting graft flow parameters through changes in microsensor voltage and frequency. Waveform analysis was applied to construct an algorithm using proprietary software and determine a parameter for graft flow characteristics. This algorithm allowed determination of the degree of stenosis and location of stenosis location (proximal or distal) for display on a remote monitor in real time. Subsequent in vivo experiments confirmed the ability of the system to generate signal acquisition through skin and soft tissue under biologic conditions with no arteriographic stenosis and a favorable healing response at 30-day harvest. Initial in vitro and in vivo experiments demonstrate the ability for a self-monitoring graft system to remotely monitor hemodynamic parameters reflecting graft function using wireless data transmission. This automated system shows promise to deliver real-time data that can be analyzed by cloud-based algorithms alerting the clinician of a change in graft function or development of stenosis for further diagnostic study or intervention before graft failure. Copyright © 2016 Society for Vascular Surgery. Published by Elsevier Inc. All rights reserved.

75 FR 68177 - Airworthiness Directives; The Boeing Company Model 757 and 767 Airplanes

Federal Register 2010, 2011, 2012, 2013, 2014

2010-11-05

... and FUEL CONFIG discrete signals from the fuel quantity processor unit, and alerts the flightcrew of a... the FUEL CONFIG discrete signal, which disables both the FUEL CONFIG and LOW FUEL messages. Such... depleted below the minimum of 2,200 pounds. The EICAS receives both the LOW FUEL and FUEL CONFIG discrete...

Emergency product generation for disaster management using RISAT and DMSAR quick look SAR processors

NASA Astrophysics Data System (ADS)

Desai, Nilesh; Sharma, Ritesh; Kumar, Saravana; Misra, Tapan; Gujraty, Virendra; Rana, SurinderSingh

2006-12-01

Since last few years, ISRO has embarked upon the development of two complex Synthetic Aperture Radar (SAR) missions, viz. Spaceborne Radar Imaging Satellite (RISAT) and Airborne SAR for Disaster Mangement (DMSAR), as a capacity building measure under country's Disaster Management Support (DMS) Program, for estimating the extent of damage over large areas (~75 Km) and also assess the effectiveness of the relief measures undertaken during natural disasters such as cyclones, epidemics, earthquakes, floods and landslides, forest fires, crop diseases etc. Synthetic Aperture Radar (SAR) has an unique role to play in mapping and monitoring of large areas affected by natural disasters especially floods, owing to its unique capability to see through clouds as well as all-weather imaging capability. The generation of SAR images with quick turn around time is very essential to meet the above DMS objectives. Thus the development of SAR Processors, for these two SAR systems poses considerable challenges and design efforts. Considering the growing user demand and inevitable necessity for a full-fledged high throughput processor, to process SAR data and generate image in real or near-real time, the design and development of a generic SAR Processor has been taken up and evolved, which will meet the SAR processing requirements for both Airborne and Spaceborne SAR systems. This hardware SAR processor is being built, to the extent possible, using only Commercial-Off-The-Shelf (COTS) DSP and other hardware plug-in modules on a Compact PCI (cPCI) platform. Thus, the major thrust has been on working out Multi-processor Digital Signal Processor (DSP) architecture and algorithm development and optimization rather than hardware design and fabrication. For DMSAR, this generic SAR Processor operates as a Quick Look SAR Processor (QLP) on-board the aircraft to produce real time full swath DMSAR images and as a ground based Near-Real Time high precision full swath Processor (NRTP). It will generate full-swath (6 to 75 Kms) DMSAR images in 1m / 3m / 5m / 10m / 30m resolution SAR operating modes. For RISAT mission, this generic Quick Look SAR Processor will be mainly used for browse product generation at NRSA-Shadnagar (SAN) ground receive station. RISAT QLP/NRTP is also proposed to provide an alternative emergency SAR product generation chain. For this, the S/C aux data appended in Onboard SAR Frame Format (x, y, z, x', y', z', roll, pitch, yaw) and predicted orbit from previous days Orbit Determination data will be used. The QLP / NRTP will produce ground range images in real / near real time. For emergency data product generation, additional Off-line tasks like geo-tagging, masking, QC etc needs to be performed on the processed image. The QLP / NRTP would generate geo-tagged images from the annotation data available from the SAR P/L data itself. Since the orbit & attitude information are taken as it is, the location accuracy will be poorer compared to the product generated using ADIF, where smoothened attitude and orbit are made available. Additional tasks like masking, output formatting and Quality checking of the data product will be carried out at Balanagar, NRSA after the image annotated data from QLP / NRTP is sent to Balanagar. The necessary interfaces to the QLP/NRTP for Emergency product generation are also being worked out. As is widely acknowledged, QLP/NRTP for RISAT and DMSAR is an ambitious effort and the technology of future. It is expected that by the middle of next decade, the next generation SAR missions worldwide will have onboard SAR Processors of varying capabilities and generate SAR Data products and Information products onboard instead of SAR raw data. Thus, it is also envisaged that these activities related to QLP/NRTP implementation for RISAT ground segment and DMSAR will be a significant step which will directly feed into the development of onboard real time processing systems for ISRO's future space borne SAR missions. This paper describes the design requirements, configuration details and salient features, apart from highlighting the utility of these Quick Look SAR processors for RISAT and DMSAR, for generation of emergency products for Disaster management.

Instrumentation System Diagnoses a Thermocouple

NASA Technical Reports Server (NTRS)

Perotti, Jose; Santiago, Josephine; Mata, Carlos; Vokrot, Peter; Zavala, Carlos; Burns, Bradley

2008-01-01

An improved self-validating thermocouple (SVT) instrumentation system not only acquires readings from a thermocouple but is also capable of detecting deterioration and a variety of discrete faults in the thermocouple and its lead wires. Prime examples of detectable discrete faults and deterioration include open- and short-circuit conditions and debonding of the thermocouple junction from the object, the temperature of which one seeks to measure. Debonding is the most common cause of errors in thermocouple measurements, but most prior SVT instrumentation systems have not been capable of detecting debonding. The improved SVT instrumentation system includes power circuitry, a cold-junction compensator, signal-conditioning circuitry, pulse-width-modulation (PWM) thermocouple-excitation circuitry, an analog-to-digital converter (ADC), a digital data processor, and a universal serial bus (USB) interface. The system can operate in any of the following three modes: temperature measurement, thermocouple validation, and bonding/debonding detection. The software running in the processor includes components that implement statistical algorithms to evaluate the state of the thermocouple and the instrumentation system. When the power is first turned on, the user can elect to start a diagnosis/ monitoring sequence, in which the PWM is used to estimate the characteristic times corresponding to the correct configuration. The user also has the option of using previous diagnostic values, which are stored in an electrically erasable, programmable read-only memory so that they are available every time the power is turned on.

DRACULA: Dynamic range control for broadcasting and other applications

NASA Astrophysics Data System (ADS)

Gilchrist, N. H. C.

The BBC has developed a digital processor which is capable of reducing the dynamic range of audio in an unobtrusive manner. It is ideally suited to the task of controlling the level of musical programs. Operating as a self-contained dynamic range controller, the processor is suitable for controlling levels in conventional AM or FM broadcasting, or for applications such as the compression of program material for in-flight entertainment. It can, alternatively, be used to provide a supplementary signal in DAB (digital audio broadcasting) for optional dynamic compression in the receiver.

Feasibility study of a microprocessor based oculometer system

NASA Technical Reports Server (NTRS)

Varanasi, M. R.

1981-01-01

The elimination of redundancy in data to maximize processing speed and minimize storage requirements were objectives in a feasibility study of a microprocessor based oculometer system that would be portable in size and flexible in use. The appropriate architectural design of the signal processor, improved optics, and the reduction of size, weight, and power to the system were investigated. A flow chart is presented showing the strategy of the design. The simulation for developing microroutines for the high speed algorithmic processor subsystem is discussed as well as the Karhunen-Loeve transform technique for data compression.

SIGPROC: Pulsar Signal Processing Programs

NASA Astrophysics Data System (ADS)

Lorimer, D. R.

2011-07-01

SIGPROC is a package designed to standardize the initial analysis of the many types of fast-sampled pulsar data. Currently recognized machines are the Wide Band Arecibo Pulsar Processor (WAPP), the Penn State Pulsar Machine (PSPM), the Arecibo Observatory Fourier Transform Machine (AOFTM), the Berkeley Pulsar Processors (BPP), the Parkes/Jodrell 1-bit filterbanks (SCAMP) and the filterbank at the Ooty radio telescope (OOTY). The SIGPROC tools should help users look at their data quickly, without the need to write (yet) another routine to read data or worry about big/little endian compatibility (byte swapping is handled automatically).

Is complex signal processing for bone conduction hearing aids useful?

PubMed

Kompis, Martin; Kurz, Anja; Pfiffner, Flurin; Senn, Pascal; Arnold, Andreas; Caversaccio, Marco

2014-05-01

To establish whether complex signal processing is beneficial for users of bone anchored hearing aids. Review and analysis of two studies from our own group, each comparing a speech processor with basic digital signal processing (either Baha Divino or Baha Intenso) and a processor with complex digital signal processing (either Baha BP100 or Baha BP110 power). The main differences between basic and complex signal processing are the number of audiologist accessible frequency channels and the availability and complexity of the directional multi-microphone noise reduction and loudness compression systems. Both studies show a small, statistically non-significant improvement of speech understanding in quiet with the complex digital signal processing. The average improvement for speech in noise is +0.9 dB, if speech and noise are emitted both from the front of the listener. If noise is emitted from the rear and speech from the front of the listener, the advantage of the devices with complex digital signal processing as opposed to those with basic signal processing increases, on average, to +3.2 dB (range +2.3 … +5.1 dB, p ≤ 0.0032). Complex digital signal processing does indeed improve speech understanding, especially in noise coming from the rear. This finding has been supported by another study, which has been published recently by a different research group. When compared to basic digital signal processing, complex digital signal processing can increase speech understanding of users of bone anchored hearing aids. The benefit is most significant for speech understanding in noise.

Wireless Source Localization and Signal Collection from an Airborne Symmetric Line Array Sensor Network

DTIC Science & Technology

2014-09-01

band signal samples by taking the ratio of (166) and (165) as     2 2 /2 /2 sin sin coscos g g g g gg cQ cI eE n E n e...processors,” EEE Trans. Acoust. Speech Signal Process., vol. 31, no. 6, pp. 1378–1393, Dec. 1983. [10] J. Li, P. Stoica and Z. Wang, “On robust

An Intrinsically Digital Amplification Scheme for Hearing Aids

NASA Astrophysics Data System (ADS)

Blamey, Peter J.; Macfarlane, David S.; Steele, Brenton R.

2005-12-01

Results for linear and wide-dynamic range compression were compared with a new 64-channel digital amplification strategy in three separate studies. The new strategy addresses the requirements of the hearing aid user with efficient computations on an open-platform digital signal processor (DSP). The new amplification strategy is not modeled on prior analog strategies like compression and linear amplification, but uses statistical analysis of the signal to optimize the output dynamic range in each frequency band independently. Using the open-platform DSP processor also provided the opportunity for blind trial comparisons of the different processing schemes in BTE and ITE devices of a high commercial standard. The speech perception scores and questionnaire results show that it is possible to provide improved audibility for sound in many narrow frequency bands while simultaneously improving comfort, speech intelligibility in noise, and sound quality.

Software for embedded processors: Problems and solutions

NASA Astrophysics Data System (ADS)

Bogaerts, J. A. C.

1990-08-01

Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I/O bandwidth, the traditional key parameters of a HEP data acquisition system. Software engineering and real time system simulation tools are becoming indispensible for the design of future data acquisition systems.

A Micro-Processor Based System as a Teaching Tool.

ERIC Educational Resources Information Center

Spero, Samuel W.

1979-01-01

Two instructional strategies incorporating a microprocessor-based computer system are described. These are the use of the system to drive a television monitor, and the system's use in generating problem sets. (MP)

Perfmon2: a leap forward in performance monitoring

NASA Astrophysics Data System (ADS)

Jarp, S.; Jurga, R.; Nowak, A.

2008-07-01

This paper describes the software component, perfmon2, that is about to be added to the Linux kernel as the standard interface to the Performance Monitoring Unit (PMU) on common processors, including x86 (AMD and Intel), Sun SPARC, MIPS, IBM Power and Intel Itanium. It also describes a set of tools for doing performance monitoring in practice and details how the CERN openlab team has participated in the testing and development of these tools.

An on-line monitoring system for oil-film, pressure and temperature distributions in large-scale hydro-generator bearings

NASA Astrophysics Data System (ADS)

Höbel, M.; Haffner, K.

1999-05-01

Instrumentation that allows the behaviour of a hydro-generator thrust bearing to be monitored during operation is described. The measurement system was developed at the Asea Brown Boveri corporate research centre in Switzerland and was tested under realistic operating conditions at the Harbin Electric Machinery Company bearing-testing facility in the People's Republic of China. Newly developed fibre-optical proximity probes were used for the on-line monitoring of the thin oil film between the static and rotating parts of the bearing. These sensors are based on a back-reflection technique and can be used for various target materials such as Babbitt and Teflon. The monitoring system comprises about 120 temperature sensors, four pressure sensors and five optical oil-film thickness sensors. Temperature sensors are installed at specific static locations, whereas pressure and oil-film sensors are positioned in the runner and generate data during rotation. A special feature of the monitoring equipment is its on-line processing capability. Digital signal processors operating in parallel handle pressure and oil-film thickness data. Important measurement parameters such as the maximum pressure, maximum temperature and minimum oil-film thickness are displayed on-line. Detailed three-dimensional temperature information on one of the load segments can be obtained from subsequent off-line data analysis. The system also calculates two-dimensional plots of the oil-film thickness and pressure for most of the 12 load segments.

An Architecture for On-Line Measurement of the Tip Clearance and Time of Arrival of a Bladed Disk of an Aircraft Engine

PubMed Central

Solís, Alejandro; Aranguren, Gerardo; Zubia, Joseba

2017-01-01

Safety and performance of the turbo-engine in an aircraft is directly affected by the health of its blades. In recent years, several improvements to the sensors have taken place to monitor the blades in a non-intrusive way. The parameters that are usually measured are the distance between the blade tip and the casing, and the passing time at a given point. Simultaneously, several techniques have been developed that allow for the inference—from those parameters and under certain conditions—of the amplitude and frequency of the blade vibration. These measurements are carried out on engines set on a rig, before being installed in an airplane. In order to incorporate these methods during the regular operation of the engine, signal processing that allows for the monitoring of those parameters at all times should be developed. This article introduces an architecture, based on a trifurcated optic sensor and a hardware processor, that fulfills this need. The proposed architecture is scalable and allows several sensors to be simultaneously monitored at different points around a bladed disk. Furthermore, the results obtained by the electronic system will be compared with the results obtained by the validation of the optic sensor. PMID:28934105

Continuous on-line steam quality monitoring system of the Bacman Geothermal Production Field, Philippines

DOE Office of Scientific and Technical Information (OSTI.GOV)

Solis, R.P.; Chavez, F.C.; Garcia, S.E.

1997-12-31

In any operating geothermal power plant, steam quality is one of the most important parameters being monitored. In the Bacon-Manito Geothermal Production Field (BGPF), an online steam quality monitoring system have been installed in two operating power plants which provides an accurate, efficient and continuous real-time data which is more responsive to the various requirements of the field operation. The system utilizes sodium as an indicator of steam purity. Sodium concentration is read by the flame photometer located at the interface after aspirating a sample of the condensed steam through a continuous condensate sampler. The condensate has been degassed throughmore » a condensate-NCG separator. The flame photometer analog signal is then converted by a voltage-to-current converter/transmitter and relayed to the processor which is located at the control center through electrical cable to give a digital sodium concentration read-out at the control panel. The system features a high and high-high sodium level alarm, a continuous strip-chart recorder and a central computer for data capture, retrieval, and processing for further interpretation. Safety devices, such as the flame-off indicator at the control center and the automatic fuel cut-off device along the fuel line, are incorporated in the system.« less

An Architecture for On-Line Measurement of the Tip Clearance and Time of Arrival of a Bladed Disk of an Aircraft Engine.

PubMed

Gil-García, José Miguel; Solís, Alejandro; Aranguren, Gerardo; Zubia, Joseba

2017-09-21

Safety and performance of the turbo-engine in an aircraft is directly affected by the health of its blades. In recent years, several improvements to the sensors have taken place to monitor the blades in a non-intrusive way. The parameters that are usually measured are the distance between the blade tip and the casing, and the passing time at a given point. Simultaneously, several techniques have been developed that allow for the inference-from those parameters and under certain conditions-of the amplitude and frequency of the blade vibration. These measurements are carried out on engines set on a rig, before being installed in an airplane. In order to incorporate these methods during the regular operation of the engine, signal processing that allows for the monitoring of those parameters at all times should be developed. This article introduces an architecture, based on a trifurcated optic sensor and a hardware processor, that fulfills this need. The proposed architecture is scalable and allows several sensors to be simultaneously monitored at different points around a bladed disk. Furthermore, the results obtained by the electronic system will be compared with the results obtained by the validation of the optic sensor.

Diode-Laser-Based Spectrometer for Sensing Gases

NASA Technical Reports Server (NTRS)

Silver, Joel A.

2005-01-01

A diode-laser-based spectrometer has been developed for measuring concentrations of gases and is intended particularly for use in analyzing and monitoring combustion processes under microgravitational conditions in a drop tower or a spacecraft. This instrument is also well suited for use on Earth in combustion experiments and for such related purposes as fire-safety monitoring and monitoring toxic and flammable gases in industrial settings. Of the gas-sensing spectrometers available prior to the development of this instrument, those that were sensitive enough for measuring the combustion gases of interest were too large, required critical optical alignments, used far too much electrical power, and were insufficiently rugged for use under the severe conditions of spacecraft launch and space flight. In contrast, the present instrument is compact, consumes relatively little power, and is rugged enough to withstand launch vibrations and space flight. In addition, this instrument is characterized by long-term stability, accuracy, and reliability. The diode laser in this spectrometer is operated in a wavelength-modulation mode. Different gases to be measured can be selected by changing modular laser units. The operation of the laser is controlled by customized, low-power electronic circuitry built around a digital signal-processor board. This customized circuitry also performs acquisition and analysis of data, controls communications, and manages errors.

A telehealth architecture for networked embedded systems: a case study in in vivo health monitoring.

PubMed

Dabiri, Foad; Massey, Tammara; Noshadi, Hyduke; Hagopian, Hagop; Lin, C K; Tan, Robert; Schmidt, Jacob; Sarrafzadeh, Majid

2009-05-01

The improvement in processor performance through continuous breakthroughs in transistor technology has resulted in the proliferation of lightweight embedded systems. Advances in wireless technology and embedded systems have enabled remote healthcare and telemedicine. While medical examinations could previously extract only localized symptoms through snapshots, now continuous monitoring can discretely analyze how a patient's lifestyle affects his/her physiological conditions and if additional symptoms occur under various stimuli. We demonstrate how medical applications in particular benefit from a hierarchical networking scheme that will improve the quantity and quality of ubiquitous data collection. Our Telehealth networking infrastructure provides flexibility in terms of functionality and the type of applications that it supports. We specifically present a case study that demonstrates the effectiveness of our networked embedded infrastructure in an in vivo pressure application. Experimental results of the in vivo system demonstrate how it can wirelessly transmit pressure readings measuring from 0 to 1.5 lbf/in (2) with an accuracy of 0.02 lbf/in (2). The challenges in biocompatible packaging, transducer drift, power management, and in vivo signal transmission are also discussed. This research brings researchers a step closer to continuous, real-time systemic monitoring that will allow one to analyze the dynamic human physiology.

Multi-channel time-reversal receivers for multi and 1-bit implementations

DOEpatents

Candy, James V.; Chambers, David H.; Guidry, Brian L.; Poggio, Andrew J.; Robbins, Christopher L.

2008-12-09

A communication system for transmitting a signal through a channel medium comprising digitizing the signal, time-reversing the digitized signal, and transmitting the signal through the channel medium. In one embodiment a transmitter is adapted to transmit the signal, a multiplicity of receivers are adapted to receive the signal, a digitizer digitizes the signal, and a time-reversal signal processor is adapted to time-reverse the digitized signal. An embodiment of the present invention includes multi bit implementations. Another embodiment of the present invention includes 1-bit implementations. Another embodiment of the present invention includes a multiplicity of receivers used in the step of transmitting the signal through the channel medium.

Design and simulation of programmable relational optoelectronic time-pulse coded processors as base elements for sorting neural networks

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Nikolsky, Alexander I.; Lazarev, Alexander A.; Lazareva, Maria V.

2010-05-01

In the paper we show that the biologically motivated conception of time-pulse encoding usage gives a set of advantages (single methodological basis, universality, tuning simplicity, learning and programming et al) at creation and design of sensor systems with parallel input-output and processing for 2D structures hybrid and next generations neuro-fuzzy neurocomputers. We show design principles of programmable relational optoelectronic time-pulse encoded processors on the base of continuous logic, order logic and temporal waves processes. We consider a structure that execute analog signal extraction, analog and time-pulse coded variables sorting. We offer optoelectronic realization of such base relational order logic element, that consists of time-pulse coded photoconverters (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutation blocks. We make technical parameters estimations of devices and processors on such base elements by simulation and experimental research: optical input signals power 0.2 - 20 uW, processing time 1 - 10 us, supply voltage 1 - 3 V, consumption power 10 - 100 uW, extended functional possibilities, learning possibilities. We discuss some aspects of possible rules and principles of learning and programmable tuning on required function, relational operation and realization of hardware blocks for modifications of such processors. We show that it is possible to create sorting machines, neural networks and hybrid data-processing systems with untraditional numerical systems and pictures operands on the basis of such quasiuniversal hardware simple blocks with flexible programmable tuning.

Laser velocimetry: A state-of-the-art overview

NASA Technical Reports Server (NTRS)

Stevenson, W. H.

1982-01-01

General systems design and optical and signal processing requirements for laser velocimetric measurement of flows are reviewed. Bias errors which occur in measurements using burst (counter) processors are discussed and particle seeding requirements are suggested.

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

DOEpatents

Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

2012-03-20

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

Electric prototype power processor for a 30cm ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

An electrical prototype power processor unit was designed, fabricated and tested with a 30 cm mercury ion engine for primary space propulsion. The power processor unit used the thyristor series resonant inverter as the basic power stage for the high power beam and discharge supplies. A transistorized series resonant inverter processed the remaining power for the low power outputs. The power processor included a digital interface unit to process all input commands and internal telemetry signals so that electric propulsion systems could be operated with a central computer system. The electrical prototype unit included design improvement in the power components such as thyristors, transistors, filters and resonant capacitors, and power transformers and inductors in order to reduce component weight, to minimize losses, and to control the component temperature rise. A design analysis for the electrical prototype is also presented on the component weight, losses, part count and reliability estimate. The electrical prototype was tested in a thermal vacuum environment. Integration tests were performed with a 30 cm ion engine and demonstrated operational compatibility. Electromagnetic interference data was also recorded on the design to provide information for spacecraft integration.

Assessment of mammographic film processor performance in a hospital and mobile screening unit.

PubMed

Murray, J G; Dowsett, D J; Laird, O; Ennis, J T

1992-12-01

In contrast to the majority of mammographic breast screening programmes, film processing at this centre occurs on site in both hospital and mobile trailer units. Initial (1989) quality control (QC) sensitometric tests revealed a large variation in film processor performance in the mobile unit. The clinical significance of these variations was assessed and acceptance limits for processor performance determined. Abnormal mammograms were used as reference material and copied using high definition 35 mm film over a range of exposure settings. The copies were than matched with QC film density variation from the mobile unit. All films were subsequently ranked for spatial and contrast resolution. Optimal values for processing time of 2 min (equivalent to film transit time 3 min and developer time 46 s) and temperature of 36 degrees C were obtained. The widespread anomaly of reporting film transit time as processing time is highlighted. Use of mammogram copies as a means of measuring the influence of film processor variation is advocated. Careful monitoring of the mobile unit film processor performance has produced stable quality comparable with the hospital based unit. The advantages of on site film processing are outlined. The addition of a sensitometric step wedge to all mammography film stock as a means of assessing image quality is recommended.

Signal Detection Theory-Based Information Processing for the Detection of Breast Cancer at Microwave Frequencies

DTIC Science & Technology

2002-08-01

the measurement noise, as well as the physical model of the forward scattered electric field. The Bayesian algorithms for the Uncertain Permittivity...received at multiple sensors. In this research project a tissue- model -based signal-detection theory approach for the detection of mammary tumors in the...oriented information processors. In this research project a tissue- model - based signal detection theory approach for the detection of mammary tumors in the

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring

NASA Astrophysics Data System (ADS)

Iwato, Hirofumi; Sakanushi, Keishi; Takeuchi, Yoshinori; Imai, Masaharu

To measure the detrusor pressure for diagnosing lower urinary tract symptoms, we designed a small-area and low-power System on a Chip (SoC). The SoC should be small and low power because it is encapsulated in tiny air-tight capsules which are simultaneously inserted in the urinary bladder and rectum for several days. Since the SoC is also required to be programmable, we designed an Application Specific Instruction set Processor (ASIP) for pressure measurement and wireless communication, and implemented almost required functions on the ASIP. The SoC was fabricated using a 0.18µm CMOS mixed-signal process and the chip size is 2.5×2.5mm2. Evaluation results show that the power consumption of the SoC is 93.5µW, and that it can operate the capsule for seven days with a tiny battery.

Digital optical tomography system for dynamic breast imaging

NASA Astrophysics Data System (ADS)

Flexman, Molly L.; Khalil, Michael A.; Al Abdi, Rabah; Kim, Hyun K.; Fong, Christopher J.; Desperito, Elise; Hershman, Dawn L.; Barbour, Randall L.; Hielscher, Andreas H.

2011-07-01

Diffuse optical tomography has shown promising results as a tool for breast cancer screening and monitoring response to chemotherapy. Dynamic imaging of the transient response of the breast to an external stimulus, such as pressure or a respiratory maneuver, can provide additional information that can be used to detect tumors. We present a new digital continuous-wave optical tomography system designed to simultaneously image both breasts at fast frame rates and with a large number of sources and detectors. The system uses a master-slave digital signal processor-based detection architecture to achieve a dynamic range of 160 dB and a frame rate of 1.7 Hz with 32 sources, 64 detectors, and 4 wavelengths per breast. Included is a preliminary study of one healthy patient and two breast cancer patients showing the ability to identify an invasive carcinoma based on the hemodynamic response to a breath hold.

Automatic Carbon Dioxide-Methane Gas Sensor Based on the Solubility of Gases in Water

PubMed Central

Cadena-Pereda, Raúl O.; Rivera-Muñoz, Eric M.; Herrera-Ruiz, Gilberto; Gomez-Melendez, Domingo J.; Anaya-Rivera, Ely K.

2012-01-01

Biogas methane content is a relevant variable in anaerobic digestion processing where knowledge of process kinetics or an early indicator of digester failure is needed. The contribution of this work is the development of a novel, simple and low cost automatic carbon dioxide-methane gas sensor based on the solubility of gases in water as the precursor of a sensor for biogas quality monitoring. The device described in this work was used for determining the composition of binary mixtures, such as carbon dioxide-methane, in the range of 0–100%. The design and implementation of a digital signal processor and control system into a low-cost Field Programmable Gate Array (FPGA) platform has permitted the successful application of data acquisition, data distribution and digital data processing, making the construction of a standalone carbon dioxide-methane gas sensor possible. PMID:23112626

Raster Scan Computer Image Generation (CIG) System Based On Refresh Memory

NASA Astrophysics Data System (ADS)

Dichter, W.; Doris, K.; Conkling, C.

1982-06-01

A full color, Computer Image Generation (CIG) raster visual system has been developed which provides a high level of training sophistication by utilizing advanced semiconductor technology and innovative hardware and firmware techniques. Double buffered refresh memory and efficient algorithms eliminate the problem of conventional raster line ordering by allowing the generated image to be stored in a random fashion. Modular design techniques and simplified architecture provide significant advantages in reduced system cost, standardization of parts, and high reliability. The major system components are a general purpose computer to perform interfacing and data base functions; a geometric processor to define the instantaneous scene image; a display generator to convert the image to a video signal; an illumination control unit which provides final image processing; and a CRT monitor for display of the completed image. Additional optional enhancements include texture generators, increased edge and occultation capability, curved surface shading, and data base extensions.

Automatic carbon dioxide-methane gas sensor based on the solubility of gases in water.

PubMed

Cadena-Pereda, Raúl O; Rivera-Muñoz, Eric M; Herrera-Ruiz, Gilberto; Gomez-Melendez, Domingo J; Anaya-Rivera, Ely K

2012-01-01

Biogas methane content is a relevant variable in anaerobic digestion processing where knowledge of process kinetics or an early indicator of digester failure is needed. The contribution of this work is the development of a novel, simple and low cost automatic carbon dioxide-methane gas sensor based on the solubility of gases in water as the precursor of a sensor for biogas quality monitoring. The device described in this work was used for determining the composition of binary mixtures, such as carbon dioxide-methane, in the range of 0-100%. The design and implementation of a digital signal processor and control system into a low-cost Field Programmable Gate Array (FPGA) platform has permitted the successful application of data acquisition, data distribution and digital data processing, making the construction of a standalone carbon dioxide-methane gas sensor possible.

Biomedical Wireless Ambulatory Crew Monitor

NASA Technical Reports Server (NTRS)

Chmiel, Alan; Humphreys, Brad

2009-01-01

A compact, ambulatory biometric data acquisition system has been developed for space and commercial terrestrial use. BioWATCH (Bio medical Wireless and Ambulatory Telemetry for Crew Health) acquires signals from biomedical sensors using acquisition modules attached to a common data and power bus. Several slots allow the user to configure the unit by inserting sensor-specific modules. The data are then sent real-time from the unit over any commercially implemented wireless network including 802.11b/g, WCDMA, 3G. This system has a distributed computing hierarchy and has a common data controller on each sensor module. This allows for the modularity of the device along with the tailored ability to control the cards using a relatively small master processor. The distributed nature of this system affords the modularity, size, and power consumption that betters the current state of the art in medical ambulatory data acquisition. A new company was created to market this technology.

Advanced Signal Conditioners for Data-Acquisition Systems

NASA Technical Reports Server (NTRS)

Lucena, Angel; Perotti, Jose; Eckhoff, Anthony; Medelius, Pedro

2004-01-01

Signal conditioners embodying advanced concepts in analog and digital electronic circuitry and software have been developed for use in data-acquisition systems that are required to be compact and lightweight, to utilize electric energy efficiently, and to operate with high reliability, high accuracy, and high power efficiency, without intervention by human technicians. These signal conditioners were originally intended for use aboard spacecraft. There are also numerous potential terrestrial uses - especially in the fields of aeronautics and medicine, wherein it is necessary to monitor critical functions. Going beyond the usual analog and digital signal-processing functions of prior signal conditioners, the new signal conditioner performs the following additional functions: It continuously diagnoses its own electronic circuitry, so that it can detect failures and repair itself (as described below) within seconds. It continuously calibrates itself on the basis of a highly accurate and stable voltage reference, so that it can continue to generate accurate measurement data, even under extreme environmental conditions. It repairs itself in the sense that it contains a micro-controller that reroutes signals among redundant components as needed to maintain the ability to perform accurate and stable measurements. It detects deterioration of components, predicts future failures, and/or detects imminent failures by means of a real-time analysis in which, among other things, data on its present state are continuously compared with locally stored historical data. It minimizes unnecessary consumption of electric energy. The design architecture divides the signal conditioner into three main sections: an analog signal section, a digital module, and a power-management section. The design of the analog signal section does not follow the traditional approach of ensuring reliability through total redundancy of hardware: Instead, following an approach called spare parts tool box, the reliability of each component is assessed in terms of such considerations as risks of damage, mean times between failures, and the effects of certain failures on the performance of the signal conditioner as a whole system. Then, fewer or more spares are assigned for each affected component, pursuant to the results of this analysis, in order to obtain the required degree of reliability of the signal conditioner as a whole system. The digital module comprises one or more processors and field-programmable gate arrays, the number of each depending on the results of the aforementioned analysis. The digital module provides redundant control, monitoring, and processing of several analog signals. It is designed to minimize unnecessary consumption of electric energy, including, when possible, going into a low-power "sleep" mode that is implemented in firmware. The digital module communicates with external equipment via a personal-computer serial port. The digital module monitors the "health" of the rest of the signal conditioner by processing defined measurements and/or trends. It automatically makes adjustments to respond to channel failures, compensate for effects of temperature, and maintain calibration.

Analog Ranging Modem Code Processor and Generator

DOT National Transportation Integrated Search

1974-05-01

The report details technical development efforts to implement an analog ranging modem using recently developed linear integrated circuits where possible. The breadboard hardware is capable of acquiring frequency and phase of a weak signal in a high n...

Advanced electronics for the CTF MEG system.

PubMed

McCubbin, J; Vrba, J; Spear, P; McKenzie, D; Willis, R; Loewen, R; Robinson, S E; Fife, A A

2004-11-30

Development of the CTF MEG system has been advanced with the introduction of a computer processing cluster between the data acquisition electronics and the host computer. The advent of fast processors, memory, and network interfaces has made this innovation feasible for large data streams at high sampling rates. We have implemented tasks including anti-alias filter, sample rate decimation, higher gradient balancing, crosstalk correction, and optional filters with a cluster consisting of 4 dual Intel Xeon processors operating on up to 275 channel MEG systems at 12 kHz sample rate. The architecture is expandable with additional processors to implement advanced processing tasks which may include e.g., continuous head localization/motion correction, optional display filters, coherence calculations, or real time synthetic channels (via beamformer). We also describe an electronics configuration upgrade to provide operator console access to the peripheral interface features such as analog signal and trigger I/O. This allows remote location of the acoustically noisy electronics cabinet and fitting of the cabinet with doors for improved EMI shielding. Finally, we present the latest performance results available for the CTF 275 channel MEG system including an unshielded SEF (median nerve electrical stimulation) measurement enhanced by application of an adaptive beamformer technique (SAM) which allows recognition of the nominal 20-ms response in the unaveraged signal.

Design of video processing and testing system based on DSP and FPGA

NASA Astrophysics Data System (ADS)

Xu, Hong; Lv, Jun; Chen, Xi'ai; Gong, Xuexia; Yang, Chen'na

2007-12-01

Based on high speed Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA), a video capture, processing and display system is presented, which is of miniaturization and low power. In this system, a triple buffering scheme was used for the capture and display, so that the application can always get a new buffer without waiting; The Digital Signal Processor has an image process ability and it can be used to test the boundary of workpiece's image. A video graduation technology is used to aim at the position which is about to be tested, also, it can enhance the system's flexibility. The character superposition technology realized by DSP is used to display the test result on the screen in character format. This system can process image information in real time, ensure test precision, and help to enhance product quality and quality management.

System for Suppressing Vibration in Turbomachine Components

NASA Technical Reports Server (NTRS)

Morrison, Carlos R. (Inventor); Provenza, Andrew J. (Inventor); Choi, Benjamin B. (Inventor); Bakhle, Milind A. (Inventor); Min, James B (Inventor); Stefko, George L. (Inventor); Kussmann, John A (Inventor); Fougere, Alan J (Inventor)

2013-01-01

Disclosed is a system for suppressing vibration and noise mitigation in structures such as blades in turbomachinery. The system includes flexible piezoelectric patches which are secured on or imbedded in turbomachinery blades which, in one embodiment, comprises eight (8) fan blades. The system further includes a capacitor plate coupler and a power transfer apparatus, which may both be arranged into one assembly, that respectively transfer data and power. Each of the capacitive plate coupler and power transfer apparatus is configured so that one part is attached to a fixed member while another part is attached to a rotatable member with an air gap there between. The system still further includes a processor that has 16 channels, eight of which serve as sensor channels, and the remaining eight, serving as actuation channels. The processor collects and analyzes the sensor signals and, in turn, outputs corrective signals for vibration/noise suppression of the turbine blades.

[Feasibility Study on Digital Signal Processor and Gear Pump of Uroflowmeter Calibration Device].

PubMed

Yuan, Qing; Ji, Jun; Gao, Jiashuo; Wang, Lixin; Xiao, Hong

2016-08-01

It will cause hidden trouble on clinical application if the uroflowmeter is out of control.This paper introduces a scheme of uroflowmeter calibration device based on digital signal processor(DSP)and gear pump and shows studies of its feasibility.According to the research plan,we analyzed its stability,repeatability and linearity by building a testing system and carried out experiments on it.The flow test system is composed of DSP,gear pump and other components.The test results showed that the system could produce a stable water flow with high precision of repeated measurement and different flow rate.The test system can calibrate the urine flow rate well within the range of 9~50mL/s which has clinical significance,and the flow error is less than 1%,which meets the technical requirements of the calibration apparatus.The research scheme of uroflowmeter calibration device on DSP and gear pump is feasible.

Single Event Upset Analysis: On-orbit performance of the Alpha Magnetic Spectrometer Digital Signal Processor Memory aboard the International Space Station

NASA Astrophysics Data System (ADS)

Li, Jiaqiang; Choutko, Vitaly; Xiao, Liyi

2018-03-01

Based on the collection of error data from the Alpha Magnetic Spectrometer (AMS) Digital Signal Processors (DSP), on-orbit Single Event Upsets (SEUs) of the DSP program memory are analyzed. The daily error distribution and time intervals between errors are calculated to evaluate the reliability of the system. The particle density distribution of International Space Station (ISS) orbit is presented and the effects from the South Atlantic Anomaly (SAA) and the geomagnetic poles are analyzed. The impact of solar events on the DSP program memory is carried out combining data analysis and Monte Carlo simulation (MC). From the analysis and simulation results, it is concluded that the area corresponding to the SAA is the main source of errors on the ISS orbit. Solar events can also cause errors on DSP program memory, but the effect depends on the on-orbit particle density.

Texas Instruments-Digital Signal Processor(TI-DSP)SMJ320F20 SEL Testing

NASA Technical Reports Server (NTRS)

Sanders, Anthony B.; Poivey, C.; Kim, H. S.; Gee, George B.

2006-01-01

This viewgraph presentation reviews the testing of the Texas Instrument Digital Signal Processor(TI-DSP)SMJ320F20. Tests were performed to screen for susceptibility to Single Event Latchup (SEL) and measure sensitivity as a function of Linear Energy Transfer (LET) for an application specific test setup. The Heavy Ion Testing of two TI-DSP SMJ320F240 devices experienced Single Event Latchup (SEL) conditions at an LET of 1.8 MeV/(mg/square cm) The devices were exposed from a fluence of 1.76 x l0(exp 3) to 5.00 x 10(exp 6) particles/square cm of the Neon, Argon and Krypton ion beams. For DI(sub DD) an average latchup current occurred at about 700mA, which is a magnitude of 10 over the nominal current of 700mA.

Feasibility of an ultra-low power digital signal processor platform as a basis for a fully implantable brain-computer interface system.

PubMed

Wang, Po T; Gandasetiawan, Keulanna; McCrimmon, Colin M; Karimi-Bidhendi, Alireza; Liu, Charles Y; Heydari, Payam; Nenadic, Zoran; Do, An H

2016-08-01

A fully implantable brain-computer interface (BCI) can be a practical tool to restore independence to those affected by spinal cord injury. We envision that such a BCI system will invasively acquire brain signals (e.g. electrocorticogram) and translate them into control commands for external prostheses. The feasibility of such a system was tested by implementing its benchtop analogue, centered around a commercial, ultra-low power (ULP) digital signal processor (DSP, TMS320C5517, Texas Instruments). A suite of signal processing and BCI algorithms, including (de)multiplexing, Fast Fourier Transform, power spectral density, principal component analysis, linear discriminant analysis, Bayes rule, and finite state machine was implemented and tested in the DSP. The system's signal acquisition fidelity was tested and characterized by acquiring harmonic signals from a function generator. In addition, the BCI decoding performance was tested, first with signals from a function generator, and subsequently using human electroencephalogram (EEG) during eyes opening and closing task. On average, the system spent 322 ms to process and analyze 2 s of data. Crosstalk (<;-65 dB) and harmonic distortion (~1%) were minimal. Timing jitter averaged 49 μs per 1000 ms. The online BCI decoding accuracies were 100% for both function generator and EEG data. These results show that a complex BCI algorithm can be executed on an ULP DSP without compromising performance. This suggests that the proposed hardware platform may be used as a basis for future, fully implantable BCI systems.

Direction-sensitive smart monitoring of structures using heterogeneous smartphone sensor data and coordinate system transformation

NASA Astrophysics Data System (ADS)

Ozer, Ekin; Feng, Maria Q.

2017-04-01

Mobile, heterogeneous, and smart sensor networks produce pervasive structural health monitoring (SHM) information. With various embedded sensors, smartphones have emerged to innovate SHM by empowering citizens to serve as sensors. By default, smartphones meet the fundamental smart sensor criteria, thanks to the built-in processor, memory, wireless communication units and mobile operating system. SHM using smartphones, however, faces technical challenges due to citizen-induced uncertainties, undesired sensor-structure integration, and lack of control over the sensing platform. Previously, the authors presented successful applications of smartphone accelerometers for structural vibration measurement and proposed a monitoring framework under citizen-induced spatiotemporal uncertainties. This study aims at extending the capabilities of smartphone-based SHM with a special focus on the lack of control over the sensor (i.e., the phone) positioning by citizens resulting in unknown sensor orientations. Using smartphone gyroscope, accelerometer, and magnetometer; instantaneous sensor orientation can be obtained with respect to gravitational and magnetic north directions. Using these sensor data, mobile operating system frameworks return processed features such as attitude and heading that can be used to correct misaligned sensor signals. For this purpose, a coordinate transformation procedure is proposed and illustrated on a two-story laboratory structural model and real-scale bridges with various sensor positioning examples. The proposed method corrects the sensor signals by tracking their orientations and improves measurement accuracy. Moreover, knowing structure’s coordinate system a priori, even the data from arbitrarily positioned sensors can automatically be transformed to the structural coordinates. In addition, this paper also touches some secondary mobile and heterogeneous data issues including imperfect sampling and geolocation services. The coordinate system transformation methods proposed in this study can be implemented in other non-smartphone-based SHM systems as long as similar instrumentation is available.

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

NASA Technical Reports Server (NTRS)

1977-01-01

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

Processor Would Find Best Paths On Map

NASA Technical Reports Server (NTRS)

Eberhardt, Silvio P.

1990-01-01

Proposed very-large-scale integrated (VLSI) circuit image-data processor finds path of least cost from specified origin to any destination on map. Cost of traversal assigned to each picture element of map. Path of least cost from originating picture element to every other picture element computed as path that preserves as much as possible of signal transmitted by originating picture element. Dedicated microprocessor at each picture element stores cost of traversal and performs its share of computations of paths of least cost. Least-cost-path problem occurs in research, military maneuvers, and in planning routes of vehicles.

A Micro-Computer Computational Unit for an IR-CCD Intrusion Detection System.

DTIC Science & Technology

1980-10-01

signal processor. In the laboratory this processor has met or exceeded all its design goals. LYN H. SKOLNIK Project Engineer i, viii AMONO I...4 +* * SEPIKY LANL ITINE’-10. - 4. 1 4* This section of :ode containrs all assembly lasosiae rotinec ft - used in the IRCCD tntruton 4eector rm r s...In arra -B47- -I- here o, ’t , ’ retore A0I o.- .tmp2,r! rotetre r5t jr t o I 00 to r.9ioter restore ro-tine THRESH - routix, for set.ing J thres

Method and apparatus for combinatorial logic signal processor in a digitally based high speed x-ray spectrometer

DOEpatents

Warburton, W.K.

1999-02-16

A high speed, digitally based, signal processing system is disclosed which accepts a digitized input signal and detects the presence of step-like pulses in the this data stream, extracts filtered estimates of their amplitudes, inspects for pulse pileup, and records input pulse rates and system lifetime. The system has two parallel processing channels: a slow channel, which filters the data stream with a long time constant trapezoidal filter for good energy resolution; and a fast channel which filters the data stream with a short time constant trapezoidal filter, detects pulses, inspects for pileups, and captures peak values from the slow channel for good events. The presence of a simple digital interface allows the system to be easily integrated with a digital processor to produce accurate spectra at high count rates and allow all spectrometer functions to be fully automated. Because the method is digitally based, it allows pulses to be binned based on time related values, as well as on their amplitudes, if desired. 31 figs.

Low-power wireless ECG acquisition and classification system for body sensor networks.

PubMed

Lee, Shuenn-Yuh; Hong, Jia-Hua; Hsieh, Cheng-Han; Liang, Ming-Chun; Chang Chien, Shih-Yu; Lin, Kuang-Hao

2015-01-01

A low-power biosignal acquisition and classification system for body sensor networks is proposed. The proposed system consists of three main parts: 1) a high-pass sigma delta modulator-based biosignal processor (BSP) for signal acquisition and digitization, 2) a low-power, super-regenerative on-off keying transceiver for short-range wireless transmission, and 3) a digital signal processor (DSP) for electrocardiogram (ECG) classification. The BSP and transmitter circuits, which are the body-end circuits, can be operated for over 80 days using two 605 mAH zinc-air batteries as the power supply; the power consumption is 586.5 μW. As for the radio frequency receiver and DSP, which are the receiving-end circuits that can be integrated in smartphones or personal computers, power consumption is less than 1 mW. With a wavelet transform-based digital signal processing circuit and a diagnosis control by cardiologists, the accuracy of beat detection and ECG classification are close to 99.44% and 97.25%, respectively. All chips are fabricated in TSMC 0.18-μm standard CMOS process.

21 CFR 123.12 - Special requirements for imported products.

Code of Federal Regulations, 2010 CFR

2010-04-01

... the HACCP and sanitation monitoring records required by this part that relate to the specific lot of...) Maintaining on file a copy, in English, of the foreign processor's HACCP plan, and a written guarantee from...

21 CFR 123.12 - Special requirements for imported products.

Code of Federal Regulations, 2011 CFR

2011-04-01

... the HACCP and sanitation monitoring records required by this part that relate to the specific lot of...) Maintaining on file a copy, in English, of the foreign processor's HACCP plan, and a written guarantee from...

MICROPROCESSOR CONTROL OF ROTOGRAVURE AIRFLOWS

EPA Science Inventory

The report discusses the technical and economic viability of using micro-processor-based control technology to collect volatile organic compound (VOC) emissions from a paper coating operation. The microprocessor-based control system monitors and controls both the airflow rate and...

Apparatus and method for temperature mapping a turbine component in a high temperature combustion environment

DOEpatents

Baleine, Erwan; Sheldon, Danny M

2014-06-10

Method and system for calibrating a thermal radiance map of a turbine component in a combustion environment. At least one spot (18) of material is disposed on a surface of the component. An infrared (IR) imager (14) is arranged so that the spot is within a field of view of the imager to acquire imaging data of the spot. A processor (30) is configured to process the imaging data to generate a sequence of images as a temperature of the combustion environment is increased. A monitor (42, 44) may be coupled to the processor to monitor the sequence of images of to determine an occurrence of a physical change of the spot as the temperature is increased. A calibration module (46) may be configured to assign a first temperature value to the surface of the turbine component when the occurrence of the physical change of the spot is determined.

FPGA-Based, Self-Checking, Fault-Tolerant Computers

NASA Technical Reports Server (NTRS)

Some, Raphael; Rennels, David

2004-01-01

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

Advanced Physiological Estimation of Cognitive Status. Part 2

DTIC Science & Technology

2011-05-24

Neurofeedback Algorithms and Gaze Controller EEG Sensor System g.USBamp *, ** • internal 24-bit ADC and digital signal processor • 16 channels (expandable...SUBJECT TERMS EEG eye-tracking mental state estimation machine learning Leonard J. Trejo Pacific Development and Technology LLC 999 Commercial St. Palo...fatigue, overload) Technology Transfer Opportunity Technology from PDT – Methods to acquire various physiological signals ( EEG , EOG, EMG, ECG, etc

Systolic Signal Processor/High Frequency Direction Finding

DTIC Science & Technology

1990-10-01

MUSIC ) algorithm and the finite impulse response (FIR) filter onto the testbed hardware was supported by joint sponsorship of the block and major bid...computational throughput. The systolic implementations of a four-channel finite impulse response (FIR) filter and multiple signal classification ( MUSIC ... MUSIC ) algorithm was mated to a bank of finite impulse response (FIR) filters and a four-channel data acquisition subsystem. A complete description

Experimental system for computer network via satellite /CS/. III - Network control processor

NASA Astrophysics Data System (ADS)

Kakinuma, Y.; Ito, A.; Takahashi, H.; Uchida, K.; Matsumoto, K.; Mitsudome, H.

1982-03-01

A network control processor (NCP) has the functions of generating traffics, the control of links and the control of transmitting bursts. The NCP executes protocols, monitors of experiments, gathering and compiling data of measurements, of which programs are loaded on a minicomputer (MELCOM 70/40) with 512KB of memories. The NCP acts as traffic generators, instead of a host computer, in the experiment. For this purpose, 15 fake stations are realized by the software in each user station. This paper describes the configuration of the NCP and the implementation of the protocols for the experimental system.

PCI-based WILDFIRE reconfigurable computing engines

NASA Astrophysics Data System (ADS)

Fross, Bradley K.; Donaldson, Robert L.; Palmer, Douglas J.

1996-10-01

WILDFORCE is the first PCI-based custom reconfigurable computer that is based on the Splash 2 technology transferred from the National Security Agency and the Institute for Defense Analyses, Supercomputing Research Center (SRC). The WILDFORCE architecture has many of the features of the WILDFIRE computer, such as field- programmable gate array (FPGA) based processing elements, linear array and crossbar interconnection, and high- performance memory and I/O subsystems. New features introduced in the PCI-based WILDFIRE systems include memory/processor options that can be added to any processing element. These options include static and dynamic memory, digital signal processors (DSPs), FPGAs, and microprocessors. In addition to memory/processor options, many different application specific connectors can be used to extend the I/O capabilities of the system, including systolic I/O, camera input and video display output. This paper also discusses how this new PCI-based reconfigurable computing engine is used for rapid-prototyping, real-time video processing and other DSP applications.

Multinode reconfigurable pipeline computer

NASA Technical Reports Server (NTRS)

Nosenchuck, Daniel M. (Inventor); Littman, Michael G. (Inventor)

1989-01-01

A multinode parallel-processing computer is made up of a plurality of innerconnected, large capacity nodes each including a reconfigurable pipeline of functional units such as Integer Arithmetic Logic Processors, Floating Point Arithmetic Processors, Special Purpose Processors, etc. The reconfigurable pipeline of each node is connected to a multiplane memory by a Memory-ALU switch NETwork (MASNET). The reconfigurable pipeline includes three (3) basic substructures formed from functional units which have been found to be sufficient to perform the bulk of all calculations. The MASNET controls the flow of signals from the memory planes to the reconfigurable pipeline and vice versa. the nodes are connectable together by an internode data router (hyperspace router) so as to form a hypercube configuration. The capability of the nodes to conditionally configure the pipeline at each tick of the clock, without requiring a pipeline flush, permits many powerful algorithms to be implemented directly.

Reconfigurable L-Band Radar

NASA Technical Reports Server (NTRS)

Rincon, Rafael F.

2008-01-01

The reconfigurable L-Band radar is an ongoing development at NASA/GSFC that exploits the capability inherently in phased array radar systems with a state-of-the-art data acquisition and real-time processor in order to enable multi-mode measurement techniques in a single radar architecture. The development leverages on the L-Band Imaging Scatterometer, a radar system designed for the development and testing of new radar techniques; and the custom-built DBSAR processor, a highly reconfigurable, high speed data acquisition and processing system. The radar modes currently implemented include scatterometer, synthetic aperture radar, and altimetry; and plans to add new modes such as radiometry and bi-static GNSS signals are being formulated. This development is aimed at enhancing the radar remote sensing capabilities for airborne and spaceborne applications in support of Earth Science and planetary exploration This paper describes the design of the radar and processor systems, explains the operational modes, and discusses preliminary measurements and future plans.

An acceleration framework for synthetic aperture radar algorithms

NASA Astrophysics Data System (ADS)

Kim, Youngsoo; Gloster, Clay S.; Alexander, Winser E.

2017-04-01

Algorithms for radar signal processing, such as Synthetic Aperture Radar (SAR) are computationally intensive and require considerable execution time on a general purpose processor. Reconfigurable logic can be used to off-load the primary computational kernel onto a custom computing machine in order to reduce execution time by an order of magnitude as compared to kernel execution on a general purpose processor. Specifically, Field Programmable Gate Arrays (FPGAs) can be used to accelerate these kernels using hardware-based custom logic implementations. In this paper, we demonstrate a framework for algorithm acceleration. We used SAR as a case study to illustrate the potential for algorithm acceleration offered by FPGAs. Initially, we profiled the SAR algorithm and implemented a homomorphic filter using a hardware implementation of the natural logarithm. Experimental results show a linear speedup by adding reasonably small processing elements in Field Programmable Gate Array (FPGA) as opposed to using a software implementation running on a typical general purpose processor.

Micromechanical Signal Processors

NASA Astrophysics Data System (ADS)

Nguyen, Clark Tu-Cuong

Completely monolithic high-Q micromechanical signal processors constructed of polycrystalline silicon and integrated with CMOS electronics are described. The signal processors implemented include an oscillator, a bandpass filter, and a mixer + filter--all of which are components commonly required for up- and down-conversion in communication transmitters and receivers, and all of which take full advantage of the high Q of micromechanical resonators. Each signal processor is designed, fabricated, then studied with particular attention to the performance consequences associated with miniaturization of the high-Q element. The fabrication technology which realizes these components merges planar integrated circuit CMOS technologies with those of polysilicon surface micromachining. The technologies are merged in a modular fashion, where the CMOS is processed in the first module, the microstructures in a following separate module, and at no point in the process sequence are steps from each module intermixed. Although the advantages of such modularity include flexibility in accommodating new module technologies, the developed process constrained the CMOS metallization to a high temperature refractory metal (tungsten metallization with TiSi _2 contact barriers) and constrained the micromachining process to long-term temperatures below 835^circC. Rapid-thermal annealing (RTA) was used to relieve residual stress in the mechanical structures. To reduce the complexity involved with developing this merged process, capacitively transduced resonators are utilized. High-Q single resonator and spring-coupled micromechanical resonator filters are also investigated, with particular attention to noise performance, bandwidth control, and termination design. The noise in micromechanical filters is found to be fairly high due to poor electromechanical coupling on the micro-scale with present-day technologies. Solutions to this high series resistance problem are suggested, including smaller electrode-to-resonator gaps to increase the coupling capacitance. Active Q-control techniques are demonstrated which control the bandwidth of micromechanical filters and simulate filter terminations with little passband distortion. Noise analysis shows that these active techniques are relatively quiet when compared with other resistive techniques. Modulation techniques are investigated whereby a single resonator or a filter constructed from several such resonators can provide both a mixing and a filtering function, or a filtering and amplitude modulation function. These techniques center around the placement of a carrier signal on the micromechanical resonator. Finally, micro oven stabilization is investigated in an attempt to null the temperature coefficient of a polysilicon micromechanical resonator. Here, surface micromachining procedures are utilized to fabricate a polysilicon resonator on a microplatform--two levels of suspension--equipped with heater and temperature sensing resistors, which are then imbedded in a feedback loop to control the platform (and resonator) temperature. (Abstract shortened by UMI.).

Spinoff 2013

NASA Technical Reports Server (NTRS)

2014-01-01

Topics covered include: Innovative Software Tools Measure Behavioral Alertness; Miniaturized, Portable Sensors Monitor Metabolic Health; Patient Simulators Train Emergency Caregivers; Solar Refrigerators Store Life-Saving Vaccines; Monitors Enable Medication Management in Patients' Homes; Handheld Diagnostic Device Delivers Quick Medical Readings; Experiments Result in Safer, Spin-Resistant Aircraft; Interfaces Visualize Data for Airline Safety, Efficiency; Data Mining Tools Make Flights Safer, More Efficient; NASA Standards Inform Comfortable Car Seats; Heat Shield Paves the Way for Commercial Space; Air Systems Provide Life Support to Miners; Coatings Preserve Metal, Stone, Tile, and Concrete; Robots Spur Software That Lends a Hand; Cloud-Based Data Sharing Connects Emergency Managers; Catalytic Converters Maintain Air Quality in Mines; NASA-Enhanced Water Bottles Filter Water on the Go; Brainwave Monitoring Software Improves Distracted Minds; Thermal Materials Protect Priceless, Personal Keepsakes; Home Air Purifiers Eradicate Harmful Pathogens; Thermal Materials Drive Professional Apparel Line; Radiant Barriers Save Energy in Buildings; Open Source Initiative Powers Real-Time Data Streams; Shuttle Engine Designs Revolutionize Solar Power; Procedure-Authoring Tool Improves Safety on Oil Rigs; Satellite Data Aid Monitoring of Nation's Forests; Mars Technologies Spawn Durable Wind Turbines; Programs Visualize Earth and Space for Interactive Education; Processor Units Reduce Satellite Construction Costs; Software Accelerates Computing Time for Complex Math; Simulation Tools Prevent Signal Interference on Spacecraft; Software Simplifies the Sharing of Numerical Models; Virtual Machine Language Controls Remote Devices; Micro-Accelerometers Monitor Equipment Health; Reactors Save Energy, Costs for Hydrogen Production; Cameras Monitor Spacecraft Integrity to Prevent Failures; Testing Devices Garner Data on Insulation Performance; Smart Sensors Gather Information for Machine Diagnostics; Oxygen Sensors Monitor Bioreactors and Ensure Health and Safety; Vision Algorithms Catch Defects in Screen Displays; and Deformable Mirrors Capture Exoplanet Data, Reflect Lasers.

Multisensor data fusion for integrated maritime surveillance

NASA Astrophysics Data System (ADS)

Premji, A.; Ponsford, A. M.

1995-01-01

A prototype Integrated Coastal Surveillance system has been developed on Canada's East Coast to provide effective surveillance out to and beyond the 200 nautical mile Exclusive Economic Zone. The system has been designed to protect Canada's natural resources, and to monitor and control the coastline for smuggling, drug trafficking, and similar illegal activity. This paper describes the Multiple Sensor - Multiple Target data fusion system that has been developed. The fusion processor has been developed around the celebrated Multiple Hypothesis Tracking algorithm which accommodates multiple targets, new targets, false alarms, and missed detections. This processor performs four major functions: plot-to-track association to form individual radar tracks; fusion of radar tracks with secondary sensor reports; track identification and tagging using secondary reports; and track level fusion to form common tracks. Radar data from coherent and non-coherent radars has been used to evaluate the performance of the processor. This paper presents preliminary results.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

A cylindrical SPECT camera with de-centralized readout scheme

NASA Astrophysics Data System (ADS)

Habte, F.; Stenström, P.; Rillbert, A.; Bousselham, A.; Bohm, C.; Larsson, S. A.

2001-09-01

An optimized brain single photon emission computed tomograph (SPECT) camera is being designed at Stockholm University and Karolinska Hospital. The design goal is to achieve high sensitivity, high-count rate and high spatial resolution. The sensitivity is achieved by using a cylindrical crystal, which gives a closed geometry with large solid angles. A de-centralized readout scheme where only a local environment around the light excitation is readout supports high-count rates. The high resolution is achieved by using an optimized crystal configuration. A 12 mm crystal plus 12 mm light guide combination gave an intrinsic spatial resolution better than 3.5 mm (140 keV) in a prototype system. Simulations show that a modified configuration can improve this value. A cylindrical configuration with a rotating collimator significantly simplifies the mechanical design of the gantry. The data acquisition and control system uses early digitization and subsequent digital signal processing to extract timing and amplitude information, and monitors the position of the collimator. The readout system consists of 12 or more modules each based on programmable logic and a digital signal processor. The modules send data to a PC file server-reconstruction engine via a Firewire (IEEE-1394) network.

Programmed optoelectronic time-pulse coded relational processor as base element for sorting neural networks

NASA Astrophysics Data System (ADS)

Krasilenko, Vladimir G.; Bardachenko, Vitaliy F.; Nikolsky, Alexander I.; Lazarev, Alexander A.

2007-04-01

In the paper we show that the biologically motivated conception of the use of time-pulse encoding gives the row of advantages (single methodological basis, universality, simplicity of tuning, training and programming et al) at creation and designing of sensor systems with parallel input-output and processing, 2D-structures of hybrid and neuro-fuzzy neurocomputers of next generations. We show principles of construction of programmable relational optoelectronic time-pulse coded processors, continuous logic, order logic and temporal waves processes, that lie in basis of the creation. We consider structure that executes extraction of analog signal of the set grade (order), sorting of analog and time-pulse coded variables. We offer optoelectronic realization of such base relational elements of order logic, which consists of time-pulse coded phototransformers (pulse-width and pulse-phase modulators) with direct and complementary outputs, sorting network on logical elements and programmable commutations blocks. We make estimations of basic technical parameters of such base devices and processors on their basis by simulation and experimental research: power of optical input signals - 0.200-20 μW, processing time - microseconds, supply voltage - 1.5-10 V, consumption power - hundreds of microwatts per element, extended functional possibilities, training possibilities. We discuss some aspects of possible rules and principles of training and programmable tuning on the required function, relational operation and realization of hardware blocks for modifications of such processors. We show as on the basis of such quasiuniversal hardware simple block and flexible programmable tuning it is possible to create sorting machines, neural networks and hybrid data-processing systems with the untraditional numerical systems and pictures operands.

An ultra-low-power pulse oximeter implemented with an energy-efficient transimpedance amplifier.

PubMed

Tavakoli, M; Turicchia, L; Sarpeshkar, R

2010-02-01

Pulse oximeters are ubiquitous in modern medicine to noninvasively measure the percentage of oxygenated hemoglobin in a patient's blood by comparing the transmission characteristics of red and infrared light-emitting diode light through the patient's finger with a photoreceptor. We present an analog single-chip pulse oximeter with 4.8-mW total power dissipation, which is an order of magnitude below our measurements on commercial implementations. The majority of this power reduction is due to the use of a novel logarithmic transimpedance amplifier with inherent contrast sensitivity, distributed amplification, unilateralization, and automatic loop gain control. The transimpedance amplifier, together with a photodiode current source, form a high-performance photoreceptor with characteristics similar to those found in nature, which allows LED power to be reduced. Therefore, our oximeter is well suited for portable medical applications, such as continuous home-care monitoring for elderly or chronic patients, emergency patient transport, remote soldier monitoring, and wireless medical sensing. Furthermore, our design obviates the need for an A-to-D and digital signal processor and leads to a small single-chip solution. We outline how extensions of our work could lead to submilliwatt oximeters.

Cardiorespiratory system monitoring using a developed acoustic sensor.

PubMed

Abbasi-Kesbi, Reza; Valipour, Atefeh; Imani, Khadije

2018-02-01

This Letter proposes a wireless acoustic sensor for monitoring heartbeat and respiration rate based on phonocardiogram (PCG). The developed sensor comprises a processor, a transceiver which operates at industrial, scientific and medical band and the frequency of 2.54 GHz as well as two capacitor microphones which one for recording the heartbeat and another one for respiration rate. To evaluate the precision of the presented sensor in estimating heartbeat and respiration rate, the sensor is tested on the different volunteers and the obtained results are compared with a gold standard as a reference. The results reveal that root-mean-square error are determined <2.27 beats/min and 0.92 breaths/min for the heartbeat and respiration rate in turn. While the standard deviation of the error is obtained <1.26 and 0.63 for heartbeat and respiration rate, respectively. Also, the sensor estimate sounds of [Formula: see text] to [Formula: see text] obtained PCG signal with sensitivity and specificity 98.1% and 98.3% in turn that make 3% improvement than previous works. The results prove that the sensor can be appropriate candidate for recognising abnormal condition in the cardiorespiratory system.

Improved multi-stage neonatal seizure detection using a heuristic classifier and a data-driven post-processor.

PubMed

Ansari, A H; Cherian, P J; Dereymaeker, A; Matic, V; Jansen, K; De Wispelaere, L; Dielman, C; Vervisch, J; Swarte, R M; Govaert, P; Naulaers, G; De Vos, M; Van Huffel, S

2016-09-01

After identifying the most seizure-relevant characteristics by a previously developed heuristic classifier, a data-driven post-processor using a novel set of features is applied to improve the performance. The main characteristics of the outputs of the heuristic algorithm are extracted by five sets of features including synchronization, evolution, retention, segment, and signal features. Then, a support vector machine and a decision making layer remove the falsely detected segments. Four datasets including 71 neonates (1023h, 3493 seizures) recorded in two different university hospitals, are used to train and test the algorithm without removing the dubious seizures. The heuristic method resulted in a false alarm rate of 3.81 per hour and good detection rate of 88% on the entire test databases. The post-processor, effectively reduces the false alarm rate by 34% while the good detection rate decreases by 2%. This post-processing technique improves the performance of the heuristic algorithm. The structure of this post-processor is generic, improves our understanding of the core visually determined EEG features of neonatal seizures and is applicable for other neonatal seizure detectors. The post-processor significantly decreases the false alarm rate at the expense of a small reduction of the good detection rate. Copyright © 2016 International Federation of Clinical Neurophysiology. Published by Elsevier Ireland Ltd. All rights reserved.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Polymer-Based Dense Fluidic Networks for High Throughput Screening with Ultrasensitive Fluorescence Detection

PubMed Central

Okagbare, Paul I.; Soper, Steven A.

2011-01-01

Microfluidics represents a viable platform for performing High Throughput Screening (HTS) due to its ability to automate fluid handling and generate fluidic networks with high number densities over small footprints appropriate for the simultaneous optical interrogation of many screening assays. While most HTS campaigns depend on fluorescence, readers typically use point detection and serially address the assay results significantly lowering throughput or detection sensitivity due to a low duty cycle. To address this challenge, we present here the fabrication of a high density microfluidic network packed into the imaging area of a large field-of-view (FoV) ultrasensitive fluorescence detection system. The fluidic channels were 1, 5 or 10 μm (width), 1 μm (depth) with a pitch of 1–10 μm and each fluidic processor was individually addressable. The fluidic chip was produced from a molding tool using hot embossing and thermal fusion bonding to enclose the fluidic channels. A 40X microscope objective (numerical aperture = 0.75) created a FoV of 200 μm, providing the ability to interrogate ~25 channels using the current fluidic configuration. An ultrasensitive fluorescence detection system with a large FoV was used to transduce fluorescence signals simultaneously from each fluidic processor onto the active area of an electron multiplying charge-coupled device (EMCCD). The utility of these multichannel networks for HTS was demonstrated by carrying out the high throughput monitoring of the activity of an enzyme, APE1, used as a model screening assay. PMID:20872611

Wake Vortex Avoidance System and Method

NASA Technical Reports Server (NTRS)

Shams, Qamar A. (Inventor); Zuckerwar, Allan J. (Inventor); Knight, Howard K. (Inventor)

2017-01-01

A wake vortex avoidance system includes a microphone array configured to detect low frequency sounds. A signal processor determines a geometric mean coherence based on the detected low frequency sounds. A display displays wake vortices based on the determined geometric mean coherence.

Modis, SeaWIFS, and Pathfinder funded activities

NASA Technical Reports Server (NTRS)

Evans, Robert H.

1995-01-01

MODIS (Moderate Resolution Imaging Spectrometer), SeaWIFS (Sea-viewing Wide Field Sensor), Pathfinder, and DSP (Digital Signal Processor) objectives are summarized. An overview of current progress is given for the automatic processing database, client/server status, matchup database, and DSP support.

Real-time signal processing of accelerometer data for wearable medical patient monitoring devices.

PubMed

Van Wieringen, Matt; Eklund, J

2008-01-01

Elderly and other people who live at home but required some physical assistance to do so are often more susceptible injury causing falls in and around their place of residence. In the event that a fall does occur, as a direct result of a previous medical condition or the fall itself, these people are typically less likely to be able to seek timely medical help without assistance. The goal of this research is to develop a wearable sensor device that uses an accelerometer for monitoring the movement of the person to detect falls after they have occurred in order to enable timely medical assistance. The data coming from the accelerometer is processed in real-time in the device and sent to a remote monitoring station where operators can attempt to make contact with the person and/or notify medical personnel of the situation. The ADXL330 accelerometer is contained within a Nintendo WiiMote controller, which forms the basis of the wearable medical sensor. The accelerometer data can then be sent via Bluetooth connection and processed by a local gateway processor. If a fall is detected, the gateway will then contact a remote monitoring station, on a cellular network, for example, via satellite, and/or through a hardwired phone or Internet connection. To detect the occurrence of ta fall, the accelerometer data is passed through a matched filter and the data is compared to benchmark analysis data that will define the conditions that represents the occurrence of a fall.

Very Large Scale Integrated Circuits for Military Systems.

DTIC Science & Technology

1981-01-01

ABBREVIATIONS A/D Analog-to-digital C AGC Automatic Gain Control A A/J Anti-jam ASP Advanced Signal Processor AU Arithmetic Units C.AD Computer-Aided...ESM) equipments (Ref. 23); in lieu of an adequate automatic proces- sing capability, the function is now performed manually (Ref. 24), which involves...a human operator, displays, etc., and a sacrifice in performance (acquisition speed, saturation signal density). Various automatic processing

National Radar Conference, Los Angeles, CA, March 12, 13, 1986, Proceedings

NASA Astrophysics Data System (ADS)

The topics discussed include radar systems, radar subsystems, and radar signal processing. Papers are presented on millimeter wave radar for proximity fuzing of smart munitions, a solid state low pulse power ground surveillance radar, and the Radarsat prototype synthetic-aperture radar signal processor. Consideration is also given to automatic track quality assessment in ADT radar systems instrumentation of RCS measurements of modulation spectra of aircraft blades.

SKA CSP controls: technological challenges

NASA Astrophysics Data System (ADS)

Baffa, C.; Giani, E.; Vrcic, S.; Vela Nuñez, M.

2016-07-01

The Square Kilometer Array (SKA) project is an international effort to build the world's largest radio telescope, with eventually over a square kilometer of collecting area. For SKA Phase 1, Australia will host the low-frequency instrument with more than 500 stations, each containing around 250 individual antennas, whilst South Africa will host an array of close to 200 dishes. The scale of the SKA represents a huge leap forward in both engineering and research and development towards building and delivering a unique instrument, with the detailed design and preparation now well under way. As one of the largest scientific endeavors in history, the SKA will brings together close to 100 organizations from 20 countries. Every aspect of the design and development of such a large and complex instrument requires state-of-the-art technology and innovative approach. This poster (or paper) addresses some aspects of the SKA monitor and control system, and in particular describes the development and test results of the CSP Local Monitoring and Control prototype. At the SKA workshop held in April 2015, the SKA monitor and control community has chosen TANGO Control System as a framework, for the implementation of the SKA monitor and control. This decision will have a large impact on Monitor an Control development of SKA. As work is on the way to incorporate TANGO Control System in SKA is in progress, we started to development a prototype for the SKA Central Signal Processor to mitigate the associated risks. In particular we now have developed a uniform class schema proposal for the sub-Element systems of the SKA-CSP.

FPGA implementation of digital down converter using CORDIC algorithm

NASA Astrophysics Data System (ADS)

Agarwal, Ashok; Lakshmi, Boppana

2013-01-01

In radio receivers, Digital Down Converters (DDC) are used to translate the signal from Intermediate Frequency level to baseband. It also decimates the oversampled signal to a lower sample rate, eliminating the need of a high end digital signal processors. In this paper we have implemented architecture for DDC employing CORDIC algorithm, which down converts an IF signal of 70MHz (3G) to 200 KHz baseband GSM signal, with an SFDR greater than 100dB. The implemented architecture reduces the hardware resource requirements by 15 percent when compared with other architecture available in the literature due to elimination of explicit multipliers and a quadrature phase shifter for mixing.

Universal sensor interface module (USIM)

NASA Astrophysics Data System (ADS)

King, Don; Torres, A.; Wynn, John

1999-01-01

A universal sensor interface model (USIM) is being developed by the Raytheon-TI Systems Company for use with fields of unattended distributed sensors. In its production configuration, the USIM will be a multichip module consisting of a set of common modules. The common module USIM set consists of (1) a sensor adapter interface (SAI) module, (2) digital signal processor (DSP) and associated memory module, and (3) a RF transceiver model. The multispectral sensor interface is designed around a low-power A/D converted, whose input/output interface consists of: -8 buffered, sampled inputs from various devices including environmental, acoustic seismic and magnetic sensors. The eight sensor inputs are each high-impedance, low- capacitance, differential amplifiers. The inputs are ideally suited for interface with discrete or MEMS sensors, since the differential input will allow direct connection with high-impedance bridge sensors and capacitance voltage sources. Each amplifier is connected to a 22-bit (Delta) (Sigma) A/D converter to enable simultaneous samples. The low power (Delta) (Sigma) converter provides 22-bit resolution at sample frequencies up to 142 hertz (used for magnetic sensors) and 16-bit resolution at frequencies up to 1168 hertz (used for acoustic and seismic sensors). The video interface module is based around the TMS320C5410 DSP. It can provide sensor array addressing, video data input, data calibration and correction. The processor module is based upon a MPC555. It will be used for mode control, synchronization of complex sensors, sensor signal processing, array processing, target classification and tracking. Many functions of the A/D, DSP and transceiver can be powered down by using variable clock speeds under software command or chip power switches. They can be returned to intermediate or full operation by DSP command. Power management may be based on the USIM's internal timer, command from the USIM transceiver, or by sleep mode processing management. The low power detection mode is implemented by monitoring any of the sensor analog outputs at lower sample rates for detection over a software controllable threshold.

Signal processing for smart cards

NASA Astrophysics Data System (ADS)

Quisquater, Jean-Jacques; Samyde, David

2003-06-01

In 1998, Paul Kocher showed that when a smart card computes cryptographic algorithms, for signatures or encryption, its consumption or its radiations leak information. The keys or the secrets hidden in the card can then be recovered using a differential measurement based on the intercorrelation function. A lot of silicon manufacturers use desynchronization countermeasures to defeat power analysis. In this article we detail a new resynchronization technic. This method can be used to facilitate the use of a neural network to do the code recognition. It becomes possible to reverse engineer a software code automatically. Using data and clock separation methods, we show how to optimize the synchronization using signal processing. Then we compare these methods with watermarking methods for 1D and 2D signal. The very last watermarking detection improvements can be applied to signal processing for smart cards with very few modifications. Bayesian processing is one of the best ways to do Differential Power Analysis, and it is possible to extract a PIN code from a smart card in very few samples. So this article shows the need to continue to set up effective countermeasures for cryptographic processors. Although the idea to use advanced signal processing operators has been commonly known for a long time, no publication explains that results can be obtained. The main idea of differential measurement is to use the cross-correlation of two random variables and to repeat consumption measurements on the processor to be analyzed. We use two processors clocked at the same external frequency and computing the same data. The applications of our design are numerous. Two measurements provide the inputs of a central operator. With the most accurate operator we can improve the signal noise ratio, re-synchronize the acquisition clock with the internal one, or remove jitter. The analysis based on consumption or electromagnetic measurements can be improved using our structure. At first sight the same results can be obtained with only one smart card, but this idea is not completely true because the statistical properties of the signal are not the same. As the two smart cards are submitted to the same external noise during the measurement, it is more easy to reduce the influence of perturbations. This paper shows the importance of accurate countermeasures against differential analysis.

Final report : mobile surveillance and wireless communication systems field operational test. Volume 1, Executive summary

DOT National Transportation Integrated Search

1999-03-01

This study focused on assessing the application of traffic monitoring and management systems which use transportable surveillance and ramp meter trailers, video image processors, and wireless communications. The mobile surveillance and wireless commu...

Review of crop growth and soil moisture monitoring from a ground-based instrument implementing the Interference Pattern GNSS-R Technique

NASA Astrophysics Data System (ADS)

Rodriguez-Alvarez, N.; Bosch-Lluis, X.; Camps, A.; Aguasca, A.; Vall-Llossera, M.; Valencia, E.; Ramos-Perez, I.; Park, H.

2011-12-01

Reflectometry using Global Navigation Satellite Systems signals (GNSSR) has been the focus of many studies during the past few years for a number of applications over different scenarios as land, ocean or snow and ice surfaces. In the past decade, its potential has increased yearly, with improved receivers and signal processors, from generic GNSS receivers whose signals were recorded in magnetic tapes to instruments that measure full Delay Doppler Maps (the power distribution of the reflected GNSS signal over the 2-D space of delay offsets and Doppler shifts) in real time. At present, these techniques are considered to be promising tools to retrieve geophysical parameters such as soil moisture, vegetation height, topography, altimetry, sea state and ice and snow thickness, among others. This paper focuses on the land geophysical retrievals (topography, vegetation height and soil moisture) performed from a ground-based instrument using the Interference Pattern Technique (IPT). This technique consists of the measurement of the power fluctuations of the interference signal resulting from the simultaneous reception of the direct and the reflected GNSS signals. The latest experiment performed using this technique over a maize field is shown in this paper. After a review of the previous results, this paper presents the latest experiment performed using this technique over a maize field. This new study provides a deeper analysis on the soil moisture retrieval by observing three irrigation-drying cycles and comparing them to different depths soil moisture probes. Furthermore, the height of the maize, almost 300 cm, has allowed testing the capabilities of the technique over dense and packed vegetation layers, with high vegetation water content.

Instrumentation, performance visualization, and debugging tools for multiprocessors

NASA Technical Reports Server (NTRS)

Yan, Jerry C.; Fineman, Charles E.; Hontalas, Philip J.

1991-01-01

The need for computing power has forced a migration from serial computation on a single processor to parallel processing on multiprocessor architectures. However, without effective means to monitor (and visualize) program execution, debugging, and tuning parallel programs becomes intractably difficult as program complexity increases with the number of processors. Research on performance evaluation tools for multiprocessors is being carried out at ARC. Besides investigating new techniques for instrumenting, monitoring, and presenting the state of parallel program execution in a coherent and user-friendly manner, prototypes of software tools are being incorporated into the run-time environments of various hardware testbeds to evaluate their impact on user productivity. Our current tool set, the Ames Instrumentation Systems (AIMS), incorporates features from various software systems developed in academia and industry. The execution of FORTRAN programs on the Intel iPSC/860 can be automatically instrumented and monitored. Performance data collected in this manner can be displayed graphically on workstations supporting X-Windows. We have successfully compared various parallel algorithms for computational fluid dynamics (CFD) applications in collaboration with scientists from the Numerical Aerodynamic Simulation Systems Division. By performing these comparisons, we show that performance monitors and debuggers such as AIMS are practical and can illuminate the complex dynamics that occur within parallel programs.

Advanced Health Management System for the Space Shuttle Main Engine

NASA Technical Reports Server (NTRS)

Davidson, Matt; Stephens, John; Rodela, Chris

2006-01-01

Pratt & Whitney Rocketdyne, Inc., in cooperation with NASA-Marshall Space Flight Center (MSFC), has developed a new Advanced Health Management System (AHMS) controller for the Space Shuttle Main Engine (SSME) that will increase the probability of successfully placing the shuttle into the intended orbit and increase the safety of the Space Transportation System (STS) launches. The AHMS is an upgrade o the current Block II engine controller whose primary component is an improved vibration monitoring system called the Real-Time Vibration Monitoring System (RTVMS) that can effectively and reliably monitor the state of the high pressure turbomachinery and provide engine protection through a new synchronous vibration redline which enables engine shutdown if the vibration exceeds predetermined thresholds. The introduction of this system required improvements and modification to the Block II controller such as redesigning the Digital Computer Unit (DCU) memory and the Flight Accelerometer Safety Cut-Off System (FASCOS) circuitry, eliminating the existing memory retention batteries, installation of the Digital Signal Processor (DSP) technology, and installation of a High Speed Serial Interface (HSSI) with accompanying outside world connectors. Test stand hot-fire testing along with lab testing have verified successful implementation and is expected to reduce the probability of catastrophic engine failures during the shuttle ascent phase and improve safely by about 23% according to the Quantitative Risk Assessment System (QRAS), leading to a safer and more reliable SSME.

Adaptive runtime for a multiprocessing API

DOEpatents

Antao, Samuel F.; Bertolli, Carlo; Eichenberger, Alexandre E.; O'Brien, John K.

2016-11-15

A computer-implemented method includes selecting a runtime for executing a program. The runtime includes a first combination of feature implementations, where each feature implementation implements a feature of an application programming interface (API). Execution of the program is monitored, and the execution uses the runtime. Monitor data is generated based on the monitoring. A second combination of feature implementations are selected, by a computer processor, where the selection is based at least in part on the monitor data. The runtime is modified by activating the second combination of feature implementations to replace the first combination of feature implementations.

Adaptive runtime for a multiprocessing API

DOEpatents

Antao, Samuel F.; Bertolli, Carlo; Eichenberger, Alexandre E.; O'Brien, John K.

2016-10-11

A computer-implemented method includes selecting a runtime for executing a program. The runtime includes a first combination of feature implementations, where each feature implementation implements a feature of an application programming interface (API). Execution of the program is monitored, and the execution uses the runtime. Monitor data is generated based on the monitoring. A second combination of feature implementations are selected, by a computer processor, where the selection is based at least in part on the monitor data. The runtime is modified by activating the second combination of feature implementations to replace the first combination of feature implementations.

49 CFR 236.923 - Task analysis and basic requirements.

Code of Federal Regulations, 2011 CFR

2011-10-01

... classroom, simulator, computer-based, hands-on, or other formally structured training and testing, except... for Processor-Based Signal and Train Control Systems § 236.923 Task analysis and basic requirements...) Based on a formal task analysis, identify the installation, maintenance, repair, modification...

Development of a Receiver Processor For UAV Video Signal Acquisition and Tracking Using Digital Phased Array Antenna

DTIC Science & Technology

2010-09-01

53 Figure 26. Image of the phased array antenna...................................................................54...69 Figure 38. Computation of correction angle from array factor and sum/difference beams...71 Figure 39. Front panel of the tracking algorithm

Instrument front-ends at Fermilab during Run II

NASA Astrophysics Data System (ADS)

Meyer, T.; Slimmer, D.; Voy, D.

2011-11-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor. Work supported by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the United States Department of Energy.

Experiments with recursive estimation in astronomical image processing

NASA Technical Reports Server (NTRS)

Busko, I.

1992-01-01

Recursive estimation concepts were applied to image enhancement problems since the 70's. However, very few applications in the particular area of astronomical image processing are known. These concepts were derived, for 2-dimensional images, from the well-known theory of Kalman filtering in one dimension. The historic reasons for application of these techniques to digital images are related to the images' scanned nature, in which the temporal output of a scanner device can be processed on-line by techniques borrowed directly from 1-dimensional recursive signal analysis. However, recursive estimation has particular properties that make it attractive even in modern days, when big computer memories make the full scanned image available to the processor at any given time. One particularly important aspect is the ability of recursive techniques to deal with non-stationary phenomena, that is, phenomena which have their statistical properties variable in time (or position in a 2-D image). Many image processing methods make underlying stationary assumptions either for the stochastic field being imaged, for the imaging system properties, or both. They will underperform, or even fail, when applied to images that deviate significantly from stationarity. Recursive methods, on the contrary, make it feasible to perform adaptive processing, that is, to process the image by a processor with properties tuned to the image's local statistical properties. Recursive estimation can be used to build estimates of images degraded by such phenomena as noise and blur. We show examples of recursive adaptive processing of astronomical images, using several local statistical properties to drive the adaptive processor, as average signal intensity, signal-to-noise and autocorrelation function. Software was developed under IRAF, and as such will be made available to interested users.

Designing a Virtual-Memory Implementation Using the Motorola MC68010 16- Bit Microprocessor with Multi-Processor Capability Interfaced to the VMEbus

DTIC Science & Technology

1990-06-01

RAM and ROM output enable signals. Figure C.7 shows the logic for the interrupt priority level (IPLO* through IPL2 *) and the interrupt acknowledge...IACK681* signal is sent to the DUART when a level one interrupt acknowledge is output by the CPU. The logic for the IACK681* and the IPLO* through IPL2 ...signals are actually implemented with an EPLD. Listing D.4 in Appendix D presents the Abel description of the IACK681* and IPLO* through IPL2

Modulated Fourier Transform Raman Fiber-Optic Spectroscopy

NASA Technical Reports Server (NTRS)

Jensen, Brian J. (Inventor); Cooper, John B. (Inventor); Wise, Kent L. (Inventor)

2000-01-01

A modification to a commercial Fourier Transform (FT) Raman spectrometer is presented for the elimination of thermal backgrounds in the FT Raman spectra. The modification involves the use of a mechanical optical chopper to modulate the continuous wave laser, remote collection of the signal via fiber optics, and connection of a dual-phase digital-signal-processor (DSP) lock-in amplifier between the detector and the spectrometer's collection electronics to demodulate and filter the optical signals. The resulting Modulated Fourier Transform Raman Fiber-Optic Spectrometer is capable of completely eliminating thermal backgrounds at temperatures exceeding 300 C.

Applications of satellite data relay to problems of field seismology

NASA Technical Reports Server (NTRS)

Webster, W. J., Jr.; Miller, W. H.; Whitley, R.; Allenby, R. J.; Dennison, R. T.

1980-01-01

A seismic signal processor was developed and tested for use with the NOAA-GOES satellite data collection system. Performance tests on recorded, as well as real time, short period signals indicate that the event recognition technique used is nearly perfect in its rejection of cultural signals and that data can be acquired in many swarm situations with the use of solid state buffer memories. Detailed circuit diagrams are provided. The design of a complete field data collection platform is discussed and the employment of data collection platforms in seismic network is reviewed.

SIG: a general-purpose signal processing program. User's manual. Revision 1

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lager, D.; Azevedo, S.

1985-05-09

SIG is a general-purpose signal processing, analysis, and display program. Its main purpose is to perform manipulations on time-domain and frequenccy-domain signals. The manual contains a complete description of the SIG program from the user's stand-point. A brief exercise in using SIG is shown. Complete descriptions are given of each command in the SIG core. General information about the SIG structure, command processor, and graphics options are provided. An example usage of SIG for solving a problem is developed, and error message formats are briefly discussed. (LEW)

Acoustic system for communication in pipelines

DOEpatents

Martin, II, Louis Peter; Cooper, John F [Oakland, CA

2008-09-09

A system for communication in a pipe, or pipeline, or network of pipes containing a fluid. The system includes an encoding and transmitting sub-system connected to the pipe, or pipeline, or network of pipes that transmits a signal in the frequency range of 3-100 kHz into the pipe, or pipeline, or network of pipes containing a fluid, and a receiver and processor sub-system connected to the pipe, or pipeline, or network of pipes containing a fluid that receives said signal and uses said signal for a desired application.

A bunch to bucket phase detector for the RHIC LLRF upgrade platform

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, K.S.; Harvey, M.; Hayes, T.

2011-03-28

As part of the overall development effort for the RHIC LLRF Upgrade Platform [1,2,3], a generic four channel 16 bit Analog-to-Digital Converter (ADC) daughter module was developed to provide high speed, wide dynamic range digitizing and processing of signals from DC to several hundred megahertz. The first operational use of this card was to implement the bunch to bucket phase detector for the RHIC LLRF beam control feedback loops. This paper will describe the design and performance features of this daughter module as a bunch to bucket phase detector, and also provide an overview of its place within the overallmore » LLRF platform architecture as a high performance digitizer and signal processing module suitable to a variety of applications. In modern digital control and signal processing systems, ADCs provide the interface between the analog and digital signal domains. Once digitized, signals are then typically processed using algorithms implemented in field programmable gate array (FPGA) logic, general purpose processors (GPPs), digital signal processors (DSPs) or a combination of these. For the recently developed and commissioned RHIC LLRF Upgrade Platform, we've developed a four channel ADC daughter module based on the Linear Technology LTC2209 16 bit, 160 MSPS ADC and the Xilinx V5FX70T FPGA. The module is designed to be relatively generic in application, and with minimal analog filtering on board, is capable of processing signals from DC to 500 MHz or more. The module's first application was to implement the bunch to bucket phase detector (BTB-PD) for the RHIC LLRF system. The same module also provides DC digitizing of analog processed BPM signals used by the LLRF system for radial feedback.« less

Block Copolymers as Templates for Arrays of Carbon Nanotubes

NASA Technical Reports Server (NTRS)

Bronikowski, Michael; Hunt, Brian

2003-01-01

A method of manufacturing regular arrays of precisely sized, shaped, positioned, and oriented carbon nanotubes has been proposed. Arrays of carbon nanotubes could prove useful in such diverse applications as communications (especially for filtering of signals), biotechnology (for sequencing of DNA and separation of chemicals), and micro- and nanoelectronics (as field emitters and as signal transducers and processors). The method is expected to be suitable for implementation in standard semiconductor-device fabrication facilities.

Analysis of Acoustic Depth Sounder Signals with Artificial Neural Networks

DTIC Science & Technology

1991-04-01

battery pack, processor, and mode switches and (2) a stainless steel shaft 1 meter long and 27 millimeters in diameter, containing 8 milliCurie of...returned signal which is not used in conventional depth sounders due to lack of real-time tools for interpreting the 36 information. The shape and...develop some software tools for conducting the research. Commercial programs for neural network implementation were available, but were "black box" in

Digital Intermediate Frequency Receiver Module For Use In Airborne Sar Applications

DOEpatents

Tise, Bertice L.; Dubbert, Dale F.

2005-03-08

A digital IF receiver (DRX) module directly compatible with advanced radar systems such as synthetic aperture radar (SAR) systems. The DRX can combine a 1 G-Sample/sec 8-bit ADC with high-speed digital signal processor, such as high gate-count FPGA technology or ASICs to realize a wideband IF receiver. DSP operations implemented in the DRX can include quadrature demodulation and multi-rate, variable-bandwidth IF filtering. Pulse-to-pulse (Doppler domain) filtering can also be implemented in the form of a presummer (accumulator) and an azimuth prefilter. An out of band noise source can be employed to provide a dither signal to the ADC, and later be removed by digital signal processing. Both the range and Doppler domain filtering operations can be implemented using a unique pane architecture which allows on-the-fly selection of the filter decimation factor, and hence, the filter bandwidth. The DRX module can include a standard VME-64 interface for control, status, and programming. An interface can provide phase history data to the real-time image formation processors. A third front-panel data port (FPDP) interface can send wide bandwidth, raw phase histories to a real-time phase history recorder for ground processing.

Energy consumption estimation of an OMAP-based Android operating system

NASA Astrophysics Data System (ADS)

González, Gabriel; Juárez, Eduardo; Castro, Juan José; Sanz, César

2011-05-01

System-level energy optimization of battery-powered multimedia embedded systems has recently become a design goal. The poor operational time of multimedia terminals makes computationally demanding applications impractical in real scenarios. For instance, the so-called smart-phones are currently unable to remain in operation longer than several hours. The OMAP3530 processor basically consists of two processing cores, a General Purpose Processor (GPP) and a Digital Signal Processor (DSP). The former, an ARM Cortex-A8 processor, is aimed to run a generic Operating System (OS) while the latter, a DSP core based on the C64x+, has architecture optimized for video processing. The BeagleBoard, a commercial prototyping board based on the OMAP processor, has been used to test the Android Operating System and measure its performance. The board has 128 MB of SDRAM external memory, 256 MB of Flash external memory and several interfaces. Note that the clock frequency of the ARM and DSP OMAP cores is 600 MHz and 430 MHz, respectively. This paper describes the energy consumption estimation of the processes and multimedia applications of an Android v1.6 (Donut) OS on the OMAP3530-Based BeagleBoard. In addition, tools to communicate the two processing cores have been employed. A test-bench to profile the OS resource usage has been developed. As far as the energy estimates concern, the OMAP processor energy consumption model provided by the manufacturer has been used. The model is basically divided in two energy components. The former, the baseline core energy, describes the energy consumption that is independent of any chip activity. The latter, the module active energy, describes the energy consumed by the active modules depending on resource usage.