[Design and Implementation of a Novel Networked Sleep Monitoring System].

PubMed

Tian, Yu; Yan, Zhuangzhi; Tao, Jia'an

2015-03-01

To meet the need of cost-effective multi-biosignal monitoring devices nowadays, we designed a system based on super low power MCU. It can collect, record and transfer several signals including ECG, Oxygen saturation, thoracic and abdominal wall expansion, oronasal airflow signal. The data files can be stored on a flash chip and transferred to a computer by a USB module. In addition, the sensing data can be sent wirelessly in real time. Considering that long term work of wireless module consumes much energy, we present a low-power optimization method based on delay constraint. Lower energy consumption comes at the cost of little delay. Experimental results show that it can effectively decrease the energy consumption without changing wireless module and transfer protocol. Besides, our system is powered by two dry batteries and can work at least 8 hours throughout a whole night.

Single-Chip T/R Module for 1.2 GHz

NASA Technical Reports Server (NTRS)

Moussessian, Alina; Mojarradi, Mohammad; Johnson, Travis; Davis, John; Grigorian, Edwin; Hoffman, James; Caro, Edward; Kuhn, William

2006-01-01

A single-chip CMOS-based (complementary-metal-oxide-semiconductorbased) transmit/receive (T/R) module is being developed for L-band radar systems. Previous T/R module implementations required multiple chips employing different technologies (GaAs, Si, and others) combined with off-chip transmission lines and discrete components including circulators. The new design eliminates the bulky circulator, significantly reducing the size and mass of the T/R module. Compared to multi-chip designs, the single-chip CMOS can be implemented with lower cost. These innovations enable cost-effective realization of advanced phased array and synthetic aperture radar systems that require integration of thousands of T/R modules. The circulator is a ferromagnetic device that directs the flow of the RF (radio frequency) power during transmission and reception. During transmission, the circulator delivers the transmitted power from the amplifier to the antenna, while preventing it from damaging the sensitive receiver circuitry. During reception, the circulator directs the energy from the antenna to the low-noise amplifier (LNA) while isolating the output of the power amplifier (PA). In principle, a circulator could be replaced by series transistors acting as electronic switches. However, in practice, the integration of conventional series transistors into a T/R chip introduces significant losses and noise. The prototype single-chip T/R module contains integrated transistor switches, but not connected in series; instead, they are connected in a shunt configuration with resonant circuits (see figure). The shunt/resonant circuit topology not only reduces the losses associated with conventional semiconductor switches but also provides beneficial transformation of impedances for the PA and the LNA. It provides full singlepole/ double-throw switching for the antenna, isolating the LNA from the transmitted signal and isolating the PA from the received signal. During reception, the voltage on control line RX/TX (raised bar) is high, causing the field-effect transistor (FET) switch S1 to be closed, forming a parallel resonant tank circuit L1||C1. This circuit presents high impedance to the left of the antenna, so that the received signal is coupled to the LNA. At the same time, FET switches S2 and S3 are open, so that C2 is removed from the circuit (except for a small parasitic capacitance). The combination of L2 and C3 forms a matching network that transforms the antenna impedance of 50 ohms to a higher value from the perspective of the LNA input terminal. This transformation of impedance improves LNA noise figure by increasing the received voltage delivered to the input transistor. This allows lower transconductance and therefore a smaller transistor, which makes it possible to design the CMOS LNA for low power consumption. During transmission, the voltage on control line RX/TX (raised bar) is low, causing switch S1 to be open. In this configuration, the combination of L1 and C1 transforms the antenna impedance to a lower value from the perspective of the PA. This low impedance is helpful in producing a relatively high output power compatible with the low CMOS operating potential. At the same time, switches S2 and S3 are closed, forming the parallel resonant tank circuit L2||C2. This circuit presents high impedance to the right of the antenna, directing the PA output signal to the antenna and away from the LNA. During this time, S3 presents a short circuit across the LNA input terminals to guarantee that the voltage seen by the LNA is small enough to prevent damage.

Multi-scale reflection modulator-based optical interconnects

NASA Astrophysics Data System (ADS)

Nair, Rohit

This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

A System-on-Chip Solution for Point-of-Care Ultrasound Imaging Systems: Architecture and ASIC Implementation.

PubMed

Kang, Jeeun; Yoon, Changhan; Lee, Jaejin; Kye, Sang-Bum; Lee, Yongbae; Chang, Jin Ho; Kim, Gi-Duck; Yoo, Yangmo; Song, Tai-kyong

2016-04-01

In this paper, we present a novel system-on-chip (SOC) solution for a portable ultrasound imaging system (PUS) for point-of-care applications. The PUS-SOC includes all of the signal processing modules (i.e., the transmit and dynamic receive beamformer modules, mid- and back-end processors, and color Doppler processors) as well as an efficient architecture for hardware-based imaging methods (e.g., dynamic delay calculation, multi-beamforming, and coded excitation and compression). The PUS-SOC was fabricated using a UMC 130-nm NAND process and has 16.8 GFLOPS of computing power with a total equivalent gate count of 12.1 million, which is comparable to a Pentium-4 CPU. The size and power consumption of the PUS-SOC are 27×27 mm(2) and 1.2 W, respectively. Based on the PUS-SOC, a prototype hand-held US imaging system was implemented. Phantom experiments demonstrated that the PUS-SOC can provide appropriate image quality for point-of-care applications with a compact PDA size ( 200×120×45 mm(3)) and 3 hours of battery life.

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

NASA Astrophysics Data System (ADS)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse-with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on-ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.

Integrated RGB laser light module for autostereoscopic outdoor displays

NASA Astrophysics Data System (ADS)

Reitterer, Jörg; Fidler, Franz; Hambeck, Christian; Saint Julien-Wallsee, Ferdinand; Najda, Stephen; Perlin, Piotr; Stanczyk, Szymon; Czernecki, Robert; McDougall, Stewart D.; Meredith, Wyn; Vickers, Garrie; Landles, Kennedy; Schmid, Ulrich

2015-02-01

We have developed highly compact RGB laser light modules to be used as light sources in multi-view autostereoscopic outdoor displays and projection devices. Each light module consists of an AlGaInP red laser diode, a GaInN blue laser diode, a GaInN green laser diode, as well as a common cylindrical microlens. The plano-convex microlens is a so-called "fast axis collimator", which is widely used for collimating light beams emitted from high-power laser diode bars, and has been optimized for polychromatic RGB laser diodes. The three light beams emitted from the red, green, and blue laser diodes are collimated in only one transverse direction, the so-called "fast axis", and in the orthogonal direction, the so-called "slow axis", the beams pass the microlens uncollimated. In the far field of the integrated RGB light module this produces Gaussian beams with a large ellipticity which are required, e.g., for the application in autostereoscopic outdoor displays. For this application only very low optical output powers of a few milliwatts per laser diode are required and therefore we have developed tailored low-power laser diode chips with short cavity lengths of 250 μm for red and 300 μm for blue. Our RGB laser light module including the three laser diode chips, associated monitor photodiodes, the common microlens, as well as the hermetically sealed package has a total volume of only 0.45 cm³, which to our knowledge is the smallest RGB laser light source to date.

Multi-LED parallel transmission for long distance underwater VLC system with one SPAD receiver

NASA Astrophysics Data System (ADS)

Wang, Chao; Yu, Hong-Yi; Zhu, Yi-Jun; Wang, Tao; Ji, Ya-Wei

2018-03-01

In this paper, a multiple light emitting diode (LED) chips parallel transmission (Multi-LED-PT) scheme for underwater visible light communication system with one photon-counting single photon avalanche diode (SPAD) receiver is proposed. As the lamp always consists of multi-LED chips, the data rate could be improved when we drive these multi-LED chips parallel by using the interleaver-division-multiplexing technique. For each chip, the on-off-keying modulation is used to reduce the influence of clipping. Then a serial successive interference cancellation detection algorithm based on ideal Poisson photon-counting channel by the SPAD is proposed. Finally, compared to the SPAD-based direct current-biased optical orthogonal frequency division multiplexing system, the proposed Multi-LED-PT system could improve the error-rate performance and anti-nonlinearity performance significantly under the effects of absorption, scattering and weak turbulence-induced channel fading together.

High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

NASA Technical Reports Server (NTRS)

Shalkhauser, K. A.; Li, K.; Shih, Y. C.

1992-01-01

Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, Anthony F.; Contolini, Robert J.; Malba, Vincent; Riddle, Robert A.

1997-01-01

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder.

Improving the -3 dB bandwidth of medium power GaN-based LEDs through periodic micro via-holes for visible light communications

NASA Astrophysics Data System (ADS)

Zhou, Zheng; Yan, Bing; Teng, Dongdong; Liu, Lilin; Wang, Gang

2017-06-01

Medium power GaN-based light emitting diode (LED) chips with periodic micro via-holes are designed and fabricated. The active area of each chip is 200 μm×800 μm and the diameter of each micro via-hole is 50 μm. For comparison, an LED chip with only one big via-hole (Diameter=86.6 μm) is also fabricated under the same conditions as the control partner. Both kinds of LED chips have an equal effective PN junction area. Experimentally, the LED with periodic via-holes exhibits higher output optical power and the -3 dB modulation bandwidth by about 33% and 48%, respectively, than the LED with only one bigger via-hole. The method of concurrently improving modulation and optical performances of power-type LED chips through periodic micro via-holes take the advantages of easy fabrication, suitable for mass-production.

Photonic-chip-based all-optical ultra-wideband pulse generation via XPM and birefringence in a chalcogenide waveguide.

PubMed

Tan, Kang; Marpaung, David; Pant, Ravi; Gao, Feng; Li, Enbang; Wang, Jian; Choi, Duk-Yong; Madden, Steve; Luther-Davies, Barry; Sun, Junqiang; Eggleton, Benjamin J

2013-01-28

We report a photonic-chip-based scheme for all-optical ultra-wideband (UWB) pulse generation using a novel all-optical differentiator that exploits cross-phase modulation and birefringence in an As₂S₃ chalcogenide rib waveguide. Polarity-switchable UWB monocycles and doublets were simultaneously obtained with single optical carrier operation. Moreover, transmission over 40-km fiber of the generated UWB doublets is demonstrated with good dispersion tolerance. These results indicate that the proposed approach has potential applications in multi-shape, multi-modulation and long-distance UWB-over-fiber communication systems.

Low cost high efficiency GaAs monolithic RF module for SARSAT distress beacons

NASA Technical Reports Server (NTRS)

Petersen, W. C.; Siu, D. P.; Cook, H. F.

1991-01-01

Low cost high performance (5 Watts output) 406 MHz beacons are urgently needed to realize the maximum utilization of the Search and Rescue Satellite-Aided Tracking (SARSAT) system spearheaded in the U.S. by NASA. Although current technology can produce beacons meeting the output power requirement, power consumption is high due to the low efficiency of available transmitters. Field performance is currently unsatisfactory due to the lack of safe and reliable high density batteries capable of operation at -40 C. Low cost production is also a crucial but elusive requirement for the ultimate wide scale utilization of this system. Microwave Monolithics Incorporated (MMInc.) has proposed to make both the technical and cost goals for the SARSAT beacon attainable by developing a monolithic GaAs chip set for the RF module. This chip set consists of a high efficiency power amplifier and a bi-phase modulator. In addition to implementing the RF module in Monolithic Microwave Integrated Circuit (MMIC) form to minimize ultimate production costs, the power amplifier has a power-added efficiency nearly twice that attained with current commercial technology. A distress beacon built using this RF module chip set will be significantly smaller in size and lighter in weight due to a smaller battery requirement, since the 406 MHz signal source and the digital controller have far lower power consumption compared to the 5 watt power amplifier. All the program tasks have been successfully completed. The GaAs MMIC RF module chip set has been designed to be compatible with the present 406 MHz signal source and digital controller. A complete high performance low cost SARSAT beacon can be realized with only additional minor iteration and systems integration.

A miniature on-chip multi-functional ECG signal processor with 30 µW ultra-low power consumption.

PubMed

Liu, Xin; Zheng, Yuan Jin; Phyu, Myint Wai; Zhao, Bin; Je, Minkyu; Yuan, Xiao Jun

2010-01-01

In this paper, a miniature low-power Electrocardiogram (ECG) signal processing application specific integrated circuit (ASIC) chip is proposed. This chip provides multiple critical functions for ECG analysis using a systematic wavelet transform algorithm and a novel SRAM-based ASIC architecture, while achieves low cost and high performance. Using 0.18 µm CMOS technology and 1 V power supply, this ASIC chip consumes only 29 µW and occupies an area of 3 mm(2). This on-chip ECG processor is highly suitable for reliable real-time cardiac status monitoring applications.

Design of an MR image processing module on an FPGA chip

NASA Astrophysics Data System (ADS)

Li, Limin; Wyrwicz, Alice M.

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments.

Design of an MR image processing module on an FPGA chip

PubMed Central

Li, Limin; Wyrwicz, Alice M.

2015-01-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128 × 128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. PMID:25909646

High reliability level on single-mode 980nm-1060 nm diode lasers for telecommunication and industrial applications

NASA Astrophysics Data System (ADS)

Van de Casteele, J.; Bettiati, M.; Laruelle, F.; Cargemel, V.; Pagnod-Rossiaux, P.; Garabedian, P.; Raymond, L.; Laffitte, D.; Fromy, S.; Chambonnet, D.; Hirtz, J. P.

2008-02-01

We demonstrate very high reliability level on 980-1060nm high-power single-mode lasers through multi-cell tests. First, we show how our chip design and technology enables high reliability levels. Then, we aged 758 devices during 9500 hours among 6 cells with high current (0.8A-1.2A) and high submount temperature (65°C-105°C) for the reliability demonstration. Sudden catastrophic failure is the main degradation mechanism observed. A statistical failure rate model gives an Arrhenius thermal activation energy of 0.51eV and a power law forward current acceleration factor of 5.9. For high-power submarine applications (360mW pump module output optical power), this model exhibits a failure rate as low as 9 FIT at 13°C, while ultra-high power terrestrial modules (600mW) lie below 220 FIT at 25°C. Wear-out phenomena is observed only for very high current level without any reliability impact under 1.1A. For the 1060nm chip, step-stress tests were performed and a set of devices were aged during more than 2000 hours in different stress conditions. First results are in accordance with 980nm product with more than 100khours estimated MTTF. These reliability and performance features of 980-1060nm laser diodes will make high-power single-mode emitters the best choice for a number of telecommunication and industrial applications in the next few years.

Repairable chip bonding/interconnect process

DOEpatents

Bernhardt, A.F.; Contolini, R.J.; Malba, V.; Riddle, R.A.

1997-08-05

A repairable, chip-to-board interconnect process which addresses cost and testability issues in the multi-chip modules is disclosed. This process can be carried out using a chip-on-sacrificial-substrate technique, involving laser processing. This process avoids the curing/solvent evolution problems encountered in prior approaches, as well is resolving prior plating problems and the requirements for fillets. For repairable high speed chip-to-board connection, transmission lines can be formed on the sides of the chip from chip bond pads, ending in a gull wing at the bottom of the chip for subsequent solder. 10 figs.

The design of high performance, low power triple-track magnetic sensor chip.

PubMed

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-07-09

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

PubMed Central

Wu, Xiulong; Li, Minghua; Lin, Zhiting; Xi, Mengyuan; Chen, Junning

2013-01-01

This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target. PMID:23839231

Design of an MR image processing module on an FPGA chip.

PubMed

Li, Limin; Wyrwicz, Alice M

2015-06-01

We describe the design and implementation of an image processing module on a single-chip Field-Programmable Gate Array (FPGA) for real-time image processing. We also demonstrate that through graphical coding the design work can be greatly simplified. The processing module is based on a 2D FFT core. Our design is distinguished from previously reported designs in two respects. No off-chip hardware resources are required, which increases portability of the core. Direct matrix transposition usually required for execution of 2D FFT is completely avoided using our newly-designed address generation unit, which saves considerable on-chip block RAMs and clock cycles. The image processing module was tested by reconstructing multi-slice MR images from both phantom and animal data. The tests on static data show that the processing module is capable of reconstructing 128×128 images at speed of 400 frames/second. The tests on simulated real-time streaming data demonstrate that the module works properly under the timing conditions necessary for MRI experiments. Copyright © 2015 Elsevier Inc. All rights reserved.

Research on Control System of Three - phase Brushless DC Motor for Electric Vehicle

NASA Astrophysics Data System (ADS)

Wang, Zhiwei; Jin, Hai; Guo, Jie; Su, Jie; Wang, Miao

2017-12-01

In order to study the three-phase brushless motor control system of electric vehicle, Freescale9S12XS128 chip is used as the control core, and the power MOSFET is used as the inverter device. The software is compiled by Codewarrior software. The speed control link adopts open-loop control, and the control chip collects the external sensor signal voltage Change control PWM signal output control three-phase brushless DC motor speed. The whole system consists of Hall position detection module, current detection module, power drive module and voltage detection module. The basic functions of three-phase brushless DC motor drive control are realized.

Modulation-frequency encoded multi-color fluorescent DNA analysis in an optofluidic chip.

PubMed

Dongre, Chaitanya; van Weerd, Jasper; Besselink, Geert A J; Vazquez, Rebeca Martinez; Osellame, Roberto; Cerullo, Giulio; van Weeghel, Rob; van den Vlekkert, Hans H; Hoekstra, Hugo J W M; Pollnau, Markus

2011-02-21

We introduce a principle of parallel optical processing to an optofluidic lab-on-a-chip. During electrophoretic separation, the ultra-low limit of detection achieved with our set-up allows us to record fluorescence from covalently end-labeled DNA molecules. Different sets of exclusively color-labeled DNA fragments-otherwise rendered indistinguishable by spatio-temporal coincidence-are traced back to their origin by modulation-frequency-encoded multi-wavelength laser excitation, fluorescence detection with a single ultrasensitive, albeit color-blind photomultiplier, and Fourier analysis decoding. As a proof of principle, fragments obtained by multiplex ligation-dependent probe amplification from independent human genomic segments, associated with genetic predispositions to breast cancer and anemia, are simultaneously analyzed.

A Low Cost Single Chip VDL Compatible Transceiver ASIC

NASA Technical Reports Server (NTRS)

Becker, Robert

2004-01-01

Recent trends in commercial communications system components have focussed almost exclusively on cellular telephone technology. As many of the traditional sources of receiver components have discontinued non-cellular telephone products, the designers of avionics and other low volume radio applications find themselves increasingly unable to find highly integrated components. This is particularly true for low power, low cost applications which cannot afford the lavish current consumption of the software defined radio approach increasingly taken by certified device manufacturers. In this paper, we describe a low power transceiver chip targeting applications from low VHF to low UHF frequencies typical of avionics systems. The chip encompasses a selectable single or double conversion design for the receiver and a low power IF upconversion transmitter. All local oscillators are synthesized and integrated into the chip. An on-chip I-Q modulator and demodulator provide baseband modulation and demodulation capability allowing the use of low power, fixed point signal processing components for signal demodulation. The goal of this program is to demonstrate a low cost VDL mode-3 transceiver using this chip to receive text weather information sent using 4-slot TDMA with no support for voice. The data will be sent from an experimental ground station. This work is funded by NASA Glenn Research Center.

Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect

NASA Astrophysics Data System (ADS)

Belfiore, Guido; Szilagyi, Laszlo; Henker, Ronny; Ellinger, Frank

2015-09-01

This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm2. The driver can achieve an error-free (BER < 10 -12) electrical data-rate of 25 Gbit/s using a pseudo random bit sequence of 27 -1. When the driver is connected to the VCSEL module an open optical eye is reported at 15 Gbit/s. In the tested bias point the VCSEL module has a measured bandwidth of 10.7 GHz.

Investigation of the thermal and optical performance of a spatial light modulator with high average power picosecond laser exposure for materials processing applications

NASA Astrophysics Data System (ADS)

Zhu, G.; Whitehead, D.; Perrie, W.; Allegre, O. J.; Olle, V.; Li, Q.; Tang, Y.; Dawson, K.; Jin, Y.; Edwardson, S. P.; Li, L.; Dearden, G.

2018-03-01

Spatial light modulators (SLMs) addressed with computer generated holograms (CGHs) can create structured light fields on demand when an incident laser beam is diffracted by a phase CGH. The power handling limitations of these devices based on a liquid crystal layer has always been of some concern. With careful engineering of chip thermal management, we report the detailed optical phase and temperature response of a liquid cooled SLM exposed to picosecond laser powers up to 〈P〉  =  220 W at 1064 nm. This information is critical for determining device performance at high laser powers. SLM chip temperature rose linearly with incident laser exposure, increasing by only 5 °C at 〈P〉  =  220 W incident power, measured with a thermal imaging camera. Thermal response time with continuous exposure was 1-2 s. The optical phase response with incident power approaches 2π radians with average power up to 〈P〉  =  130 W, hence the operational limit, while above this power, liquid crystal thickness variations limit phase response to just over π radians. Modelling of the thermal and phase response with exposure is also presented, supporting experimental observations well. These remarkable performance characteristics show that liquid crystal based SLM technology is highly robust when efficiently cooled. High speed, multi-beam plasmonic surface micro-structuring at a rate R  =  8 cm2 s-1 is achieved on polished metal surfaces at 〈P〉  =  25 W exposure while diffractive, multi-beam surface ablation with average power 〈P〉  =100 W on stainless steel is demonstrated with ablation rate of ~4 mm3 min-1. However, above 130 W, first order diffraction efficiency drops significantly in accord with the observed operational limit. Continuous exposure for a period of 45 min at a laser power of 〈P〉  =  160 W did not result in any detectable drop in diffraction efficiency, confirmed afterwards by the efficient parallel beam processing at 〈P〉  =  100 W. Hence, no permanent changes in SLM phase response characteristics have been detected. This research work will help to accelerate the use of liquid crystal spatial light modulators for both scientific and ultra high throughput laser-materials micro-structuring applications.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

NASA Astrophysics Data System (ADS)

Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

1995-02-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

Comparison of microrings and microdisks for high-speed optical modulation in silicon photonics

NASA Astrophysics Data System (ADS)

Ying, Zhoufeng; Wang, Zheng; Zhao, Zheng; Dhar, Shounak; Pan, David Z.; Soref, Richard; Chen, Ray T.

2018-03-01

The past several decades have witnessed the gradual transition from electrical to optical interconnects, ranging from long-haul telecommunication to chip-to-chip interconnects. As one type of key component in integrated optical interconnect and high-performance computing, optical modulators have been well developed these past few years, including ultrahigh-speed microring and microdisk modulators. In this paper, a comparison between microring and microdisk modulators is well analyzed in terms of dimensions, static and dynamic power consumption, and fabrication tolerance. The results show that microdisks have advantages over microrings in these aspects, which gives instructions to the chip design of high-density integrated systems for optical interconnects and optical computing.

Spacecraft computer technology at Southwest Research Institute

NASA Technical Reports Server (NTRS)

Shirley, D. J.

1993-01-01

Southwest Research Institute (SwRI) has developed and delivered spacecraft computers for a number of different near-Earth-orbit spacecraft including shuttle experiments and SDIO free-flyer experiments. We describe the evolution of the basic SwRI spacecraft computer design from those weighing in at 20 to 25 lb and using 20 to 30 W to newer models weighing less than 5 lb and using only about 5 W, yet delivering twice the processing throughput. Because of their reduced size, weight, and power, these newer designs are especially applicable to planetary instrument requirements. The basis of our design evolution has been the availability of more powerful processor chip sets and the development of higher density packaging technology, coupled with more aggressive design strategies in incorporating high-density FPGA technology and use of high-density memory chips. In addition to reductions in size, weight, and power, the newer designs also address the necessity of survival in the harsh radiation environment of space. Spurred by participation in such programs as MSTI, LACE, RME, Delta 181, Delta Star, and RADARSAT, our designs have evolved in response to program demands to be small, low-powered units, radiation tolerant enough to be suitable for both Earth-orbit microsats and for planetary instruments. Present designs already include MIL-STD-1750 and Multi-Chip Module (MCM) technology with near-term plans to include RISC processors and higher-density MCM's. Long term plans include development of whole-core processors on one or two MCM's.

Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

NASA Astrophysics Data System (ADS)

Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

2018-02-01

The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

Advanced Materials for High Temperature, High Performance, Wide Bandgap Power Modules

NASA Astrophysics Data System (ADS)

O'Neal, Chad B.; McGee, Brad; McPherson, Brice; Stabach, Jennifer; Lollar, Richard; Liederbach, Ross; Passmore, Brandon

2016-01-01

Advanced packaging materials must be utilized to take full advantage of the benefits of the superior electrical and thermal properties of wide bandgap power devices in the development of next generation power electronics systems. In this manuscript, the use of advanced materials for key packaging processes and components in multi-chip power modules will be discussed. For example, to date, there has been significant development in silver sintering paste as a high temperature die attach material replacement for conventional solder-based attach due to the improved thermal and mechanical characteristics as well as lower processing temperatures. In order to evaluate the bond quality and performance of this material, shear strength, thermal characteristics, and void quality for a number of silver sintering paste materials were analyzed as a die attach alternative to solder. In addition, as high voltage wide bandgap devices shift from engineering samples to commercial components, passivation materials become key in preventing premature breakdown in power modules. High temperature, high dielectric strength potting materials were investigated to be used to encapsulate and passivate components internal to a power module. The breakdown voltage up to 30 kV and corresponding leakage current for these materials as a function of temperature is also presented. Lastly, high temperature plastic housing materials are important for not only discrete devices but also for power modules. As the operational temperature of the device and/or ambient temperature increases, the mechanical strength and dielectric properties are dramatically reduced. Therefore, the electrical characteristics such as breakdown voltage and leakage current as a function of temperature for housing materials are presented.

Integrated Thermal Modules for Cooling Silicon and Silicon Carbide Power Modules

DTIC Science & Technology

2007-06-11

analyses, bench tests, and motor tests comprise the program. The ITMs, in place of standard heatsinks, use a highly conductive pyrolytic graphite to...passively cool power modules. Initial results show that even simple ITMs can lower chip temperatures by 20 deg. C and 10 deg. C with engine oil and

Smart substrates: Making multi-chip modules smarter

NASA Astrophysics Data System (ADS)

Wunsch, T. F.; Treece, R. K.

1995-05-01

A novel multi-chip module (MCM) design and manufacturing methodology which utilizes active CMOS circuits in what is normally a passive substrate realizes the 'smart substrate' for use in highly testable, high reliability MCMS. The active devices are used to test the bare substrate, diagnose assembly errors or integrated circuit (IC) failures that require rework, and improve the testability of the final MCM assembly. A static random access memory (SRAM) MCM has been designed and fabricated in Sandia Microelectronics Development Laboratory in order to demonstrate the technical feasibility of this concept and to examine design and manufacturing issues which will ultimately determine the economic viability of this approach. The smart substrate memory MCM represents a first in MCM packaging. At the time the first modules were fabricated, no other company or MCM vendor had incorporated active devices in the substrate to improve manufacturability and testability, and thereby improve MCM reliability and reduce cost.

Next Generation Space Telescope Integrated Science Module Data System

NASA Technical Reports Server (NTRS)

Schnurr, Richard G.; Greenhouse, Matthew A.; Jurotich, Matthew M.; Whitley, Raymond; Kalinowski, Keith J.; Love, Bruce W.; Travis, Jeffrey W.; Long, Knox S.

1999-01-01

The Data system for the Next Generation Space Telescope (NGST) Integrated Science Module (ISIM) is the primary data interface between the spacecraft, telescope, and science instrument systems. This poster includes block diagrams of the ISIM data system and its components derived during the pre-phase A Yardstick feasibility study. The poster details the hardware and software components used to acquire and process science data for the Yardstick instrument compliment, and depicts the baseline external interfaces to science instruments and other systems. This baseline data system is a fully redundant, high performance computing system. Each redundant computer contains three 150 MHz power PC processors. All processors execute a commercially available real time multi-tasking operating system supporting, preemptive multi-tasking, file management and network interfaces. These six processors in the system are networked together. The spacecraft interface baseline is an extension of the network, which links the six processors. The final selection for Processor busses, processor chips, network interfaces, and high-speed data interfaces will be made during mid 2002.

Practical system for the generation of pulsed quantum frequency combs.

PubMed

Roztocki, Piotr; Kues, Michael; Reimer, Christian; Wetzel, Benjamin; Sciara, Stefania; Zhang, Yanbing; Cino, Alfonso; Little, Brent E; Chu, Sai T; Moss, David J; Morandotti, Roberto

2017-08-07

The on-chip generation of large and complex optical quantum states will enable low-cost and accessible advances for quantum technologies, such as secure communications and quantum computation. Integrated frequency combs are on-chip light sources with a broad spectrum of evenly-spaced frequency modes, commonly generated by four-wave mixing in optically-excited nonlinear micro-cavities, whose recent use for quantum state generation has provided a solution for scalable and multi-mode quantum light sources. Pulsed quantum frequency combs are of particular interest, since they allow the generation of single-frequency-mode photons, required for scaling state complexity towards, e.g., multi-photon states, and for quantum information applications. However, generation schemes for such pulsed combs have, to date, relied on micro-cavity excitation via lasers external to the sources, being neither versatile nor power-efficient, and impractical for scalable realizations of quantum technologies. Here, we introduce an actively-modulated, nested-cavity configuration that exploits the resonance pass-band characteristic of the micro-cavity to enable a mode-locked and energy-efficient excitation. We demonstrate that the scheme allows the generation of high-purity photons at large coincidence-to-accidental ratios (CAR). Furthermore, by increasing the repetition rate of the excitation field via harmonic mode-locking (i.e. driving the cavity modulation at harmonics of the fundamental repetition rate), we managed to increase the pair production rates (i.e. source efficiency), while maintaining a high CAR and photon purity. Our approach represents a significant step towards the realization of fully on-chip, stable, and versatile sources of pulsed quantum frequency combs, crucial for the development of accessible quantum technologies.

MO detector (MOD): a dual-function optical modulator-detector for on-chip communication

NASA Astrophysics Data System (ADS)

Sun, Shuai; Zhang, Ruoyu; Peng, Jiaxin; Narayana, Vikram K.; Dalir, Hamed; El-Ghazawi, Tarek; Sorger, Volker J.

2018-04-01

Physical challenges at the device and interconnect level limit both network and computing energy efficiency. While photonics is being considered to address interconnect bottlenecks, optical routing is still limited by electronic circuitry, requiring substantial overhead for optical-electrical-optical conversion. Here we show a novel design of an integrated broadband photonic-plasmonic hybrid device termed MODetector featuring dual light modulation and detection function to act as an optical transceiver in the photonic network-on-chip. With over 10 dB extinction ratio and 0.8 dB insertion loss at the modulation state, this MODetector provides 0.7 W/A responsivity in the detection state with 36 ps response time. This multi-functional device: (i) eliminates OEO conversion, (ii) reduces optical losses from photodetectors when not needed, and (iii) enables cognitive routing strategies for network-on-chips.

Development of 20 GHz monolithic transmit modules

NASA Technical Reports Server (NTRS)

Higgins, J. A.

1988-01-01

The history of the development of a transmit module for the band 17.7 to 20.2 GHz is presented. The module was to monolithically combine, on one chip, five bits of phase shift, a buffer amplifier and a power amplifier to produce 200 mW to the antenna element. The approach taken was MESFET ion implanted device technology. A common pinch-off voltage was decided upon for each application. The beginning of the total integration phases revealed hitherto unencountered hazards of large microwave circuit integration which were successfully overcome. Yield and customer considerations finally led to two separate chips, one containing the power amplifiers and the other containing the complete five bit phase shifter.

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs.

PubMed

Lin, Tingyou; Ho, Yingchieh; Su, Chauchin

2017-06-15

This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 μm HV BCD processes, and total area is 900 × 914 μm². The maximal temperature variation among the eight banks can reduce to 2.8 °C by the proposed thermal balancing system from 9.5 °C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.

LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs

PubMed Central

Lin, Tingyou; Ho, Yingchieh; Su, Chauchin

2017-01-01

This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 μm HV BCD processes, and total area is 900 × 914 μm2. The maximal temperature variation among the eight banks can reduce to 2.8 °C by the proposed thermal balancing system from 9.5 °C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%. PMID:28617346

T/R Multi-Chip MMIC Modules for 150 GHz

NASA Technical Reports Server (NTRS)

Samoska, Lorene A.; Pukala, David M.; Soria, Mary M.; Sadowy, Gregory A.

2009-01-01

Modules containing multiple monolithic microwave integrated-circuit (MMIC) chips have been built as prototypes of transmitting/receiving (T/R) modules for millimeter-wavelength radar systems, including phased-array radar systems to be used for diverse purposes that could include guidance and avoidance of hazards for landing spacecraft, imaging systems for detecting hidden weapons, and hazard-avoidance systems for automobiles. Whereas prior landing radar systems have operated at frequencies around 35 GHz, the integrated circuits in this module operate in a frequency band centered at about 150 GHz. The higher frequency (and, hence, shorter wavelength), is expected to make it possible to obtain finer spatial resolution while also using smaller antennas and thereby reducing the sizes and masses of the affected systems.

High Speed Terahertz Modulator on the Chip Based on Tunable Terahertz Slot Waveguide

PubMed Central

Singh, P. K.; Sonkusale, S.

2017-01-01

This paper presents an on-chip device that can perform gigahertz-rate amplitude modulation and switching of broadband terahertz electromagnetic waves. The operation of the device is based on the interaction of confined THz waves in a novel slot waveguide with an electronically tunable two dimensional electron gas (2DEG) that controls the loss of the THz wave propagating through this waveguide. A prototype device is fabricated which shows THz intensity modulation of 96% at 0.25 THz carrier frequency with low insertion loss and device length as small as 100 microns. The demonstrated modulation cutoff frequency exceeds 14 GHz indicating potential for the high-speed modulation of terahertz waves. The entire device operates at room temperature with low drive voltage (<2 V) and zero DC power consumption. The device architecture has potential for realization of the next generation of on-chip modulators and switches at THz frequencies. PMID:28102306

Photodiodes integration on a suspended ridge structure VOA using 2-step flip-chip bonding method

NASA Astrophysics Data System (ADS)

Kim, Seon Hoon; Kim, Tae Un; Ki, Hyun Chul; Kim, Doo Gun; Kim, Hwe Jong; Lim, Jung Woon; Lee, Dong Yeol; Park, Chul Hee

2015-01-01

In this works, we have demonstrated a VOA integrated with mPDs, based on silica-on-silicon PLC and flip-chip bonding technologies. The suspended ridge structure was applied to reduce the power consumption. It achieves the attenuation of 30dB in open loop operation with the power consumption of below 30W. We have applied two-step flipchip bonding method using passive alignment to perform high density multi-chip integration on a VOA with eutectic AuSn solder bumps. The average bonding strength of the two-step flip-chip bonding method was about 90gf.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

PubMed

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

PubMed Central

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A.; Wu, Wen-Jung; Lin, Chih-Ting

2014-01-01

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems. PMID:24859027

Pattern manipulation via on-chip phase modulation between orbital angular momentum beams

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Huanlu; School of Engineering, University of Glasgow, Rankine Building, Oakfield Avenue, Glasgow G12 8LP; Strain, Michael J.

2015-08-03

An integrated approach to thermal modulation of relative phase between two optical vortices with opposite chirality has been demonstrated on a silicon-on-insulator substrate. The device consists of a silicon-integrated optical vortex emitter and a phase controlled 3 dB coupler. The relative phase between two optical vortices can be actively modulated on chip by applying a voltage on the integrated heater. The phase shift is shown to be linearly proportional to applied electrical power, and the rotation angle of the interference pattern is observed to be inversely proportional to topological charge. This scheme can be used in lab-on-chip, communications and sensing applications.more » It can be intentionally implemented with other modulation elements to achieve more complicated applications.« less

Electroabsorption-modulated widely tunable DBR laser transmitter for WDM-PONs.

PubMed

Han, Liangshun; Liang, Song; Wang, Huitao; Qiao, Lijun; Xu, Junjie; Zhao, Lingjuan; Zhu, Hongliang; Wang, Baojun; Wang, Wei

2014-12-01

We present an InP based distributed Bragg reflector (DBR) laser transmitter which has a wide wavelength tuning range and a high chip output power for wavelength division multiplexing passive optical network (WDM-PON) applications. By butt-jointing InGaAsP with 1.45 µm emission wavelength as the material of the grating section, the laser wavelength can be tuned for over 13 nm by the DBR current. Accompanied by varying the chip temperature, the tuning range can be further enlarged to 16 nm. With the help of the integrated semiconductor optical amplifier (SOA), the largest chip output power is over 30 mW. The electroabsorption modulator (EAM) is integrated into the device by the selective-area growth (SAG) technique. The 3 dB small signal modulation bandwidth of the EAM is over 13 GHz. The device has both a simple tuning scheme and a simple fabrication procedure, making it suitable for low cost massive production which is desirable for WDM-PON uses.

Monolithically integrated InGaAsP/InP laser/modulator using identical layer approach for opto-electronic oscillator

NASA Astrophysics Data System (ADS)

Wu, Chi; Keo, Sam A.; Yao, X. S.; Turner, Tasha E.; Davis, Lawrence J.; Young, Martin G.; Maleki, Lute; Forouhar, Siamak

1998-08-01

The microwave optoelectronic oscillator (OEO) has been demonstrated on a breadboard. The future trend is to integrate the whole OEO on a chip, which requires the development of high power and high efficiency integrated photonic components. In this paper, we will present the design and fabrication of an integrated semiconductor laser/modulator using the identical active layer approach on InGaAsP/InP material. The best devices have threshold currents of 50-mA at room temperature for CW operation. The device length is approximately 3-mm, resulting in a mode spacing of 14 GHz. For only 5-dBm microwave power applied to the modulator section, modulation response with 30 dB resonate enhancement has been observed. This work shows the promise for an on-chip integrated OEO.

A Fully Integrated Wireless Compressed Sensing Neural Signal Acquisition System for Chronic Recording and Brain Machine Interface.

PubMed

Liu, Xilin; Zhang, Milin; Xiong, Tao; Richardson, Andrew G; Lucas, Timothy H; Chin, Peter S; Etienne-Cummings, Ralph; Tran, Trac D; Van der Spiegel, Jan

2016-07-18

Reliable, multi-channel neural recording is critical to the neuroscience research and clinical treatment. However, most hardware development of fully integrated, multi-channel wireless neural recorders to-date, is still in the proof-of-concept stage. To be ready for practical use, the trade-offs between performance, power consumption, device size, robustness, and compatibility need to be carefully taken into account. This paper presents an optimized wireless compressed sensing neural signal recording system. The system takes advantages of both custom integrated circuits and universal compatible wireless solutions. The proposed system includes an implantable wireless system-on-chip (SoC) and an external wireless relay. The SoC integrates 16-channel low-noise neural amplifiers, programmable filters and gain stages, a SAR ADC, a real-time compressed sensing module, and a near field wireless power and data transmission link. The external relay integrates a 32 bit low-power microcontroller with Bluetooth 4.0 wireless module, a programming interface, and an inductive charging unit. The SoC achieves high signal recording quality with minimized power consumption, while reducing the risk of infection from through-skin connectors. The external relay maximizes the compatibility and programmability. The proposed compressed sensing module is highly configurable, featuring a SNDR of 9.78 dB with a compression ratio of 8×. The SoC has been fabricated in a 180 nm standard CMOS technology, occupying 2.1 mm × 0.6 mm silicon area. A pre-implantable system has been assembled to demonstrate the proposed paradigm. The developed system has been successfully used for long-term wireless neural recording in freely behaving rhesus monkey.

High-brightness 800nm fiber-coupled laser diodes

NASA Astrophysics Data System (ADS)

Berk, Yuri; Levy, Moshe; Rappaport, Noam; Tessler, Renana; Peleg, Ophir; Shamay, Moshe; Yanson, Dan; Klumel, Genadi; Dahan, Nir; Baskin, Ilya; Shkedi, Lior

2014-03-01

Fiber-coupled laser diodes have become essential sources for fiber laser pumping and direct energy applications. Single emitters offer reliable multi-watt output power from a 100 m lateral emission aperture. By their combination and fiber coupling, pump powers up to 100 W can be achieved from a low-NA fiber pigtail. Whilst in the 9xx nm spectral range the single emitter technology is very mature with <10W output per chip, at 800nm the reliable output power from a single emitter is limited to 4 W - 5 W. Consequently, commercially available fiber coupled modules only deliver 5W - 15W at around 800nm, almost an order of magnitude down from the 9xx range pumps. To bridge this gap, we report our advancement in the brightness and reliability of 800nm single emitters. By optimizing the wafer structure, laser cavity and facet passivation process we have demonstrated QCW device operation up to 19W limited by catastrophic optical damage to the 100 μm aperture. In CW operation, the devices reach 14 W output followed by a reversible thermal rollover and a complete device shutdown at high currents, with the performance fully rebounded after cooling. We also report the beam properties of our 800nm single emitters and provide a comparative analysis with the 9xx nm single emitter family. Pump modules integrating several of these emitters with a 105 μm / 0.15 NA delivery fiber reach 35W in CW at 808 nm. We discuss the key opto-mechanical parameters that will enable further brightness scaling of multi-emitter pump modules.

An ultra-compact processor module based on the R3000

NASA Astrophysics Data System (ADS)

Mullenhoff, D. J.; Kaschmitter, J. L.; Lyke, J. C.; Forman, G. A.

1992-08-01

Viable high density packaging is of critical importance for future military systems, particularly space borne systems which require minimum weight and size and high mechanical integrity. A leading, emerging technology for high density packaging is multi-chip modules (MCM). During the 1980's, a number of different MCM technologies have emerged. In support of Strategic Defense Initiative Organization (SDIO) programs, Lawrence Livermore National Laboratory (LLNL) has developed, utilized, and evaluated several different MCM technologies. Prior LLNL efforts include modules developed in 1986, using hybrid wafer scale packaging, which are still operational in an Air Force satellite mission. More recent efforts have included very high density cache memory modules, developed using laser pantography. As part of the demonstration effort, LLNL and Phillips Laboratory began collaborating in 1990 in the Phase 3 Multi-Chip Module (MCM) technology demonstration project. The goal of this program was to demonstrate the feasibility of General Electric's (GE) High Density Interconnect (HDI) MCM technology. The design chosen for this demonstration was the processor core for a MIPS R3000 based reduced instruction set computer (RISC), which has been described previously. It consists of the R3000 microprocessor, R3010 floating point coprocessor and 128 Kbytes of cache memory.

Portable low-power thermal cycler with dual thin-film Pt heaters for a polymeric PCR chip.

PubMed

Jeong, Sangdo; Lim, Juhun; Kim, Mi-Young; Yeom, JiHye; Cho, Hyunmin; Lee, Hyunjung; Shin, Yong-Beom; Lee, Jong-Hyun

2018-01-29

Polymerase chain reaction (PCR) has been widely used for major definite diagnostic tool, but very limited its place used only indoor such as hospital or diagnosis lab. For the rapid on-site detection of pathogen in an outdoor environment, a low-power cordless polymerase chain reaction (PCR) thermal cycler is crucial module. At this point of view, we proposed a low-power PCR thermal cycler that could be operated in an outdoor anywhere. The disposable PCR chip was made of a polymeric (PI/PET) film to reduce the thermal mass. A dual arrangement of the Pt heaters, which were positioned on the top and bottom of the PCR chip, improved the temperature uniformity. The temperature sensor, which was made of the same material as the heater, utilized the temperature dependence of the Pt resistor to ensure simple fabrication of the temperature sensor. Cooling the PCR chip using dual blower fans enabled thermal cycling to operate with a lower power than that of a Peltier element with a high power consumption. The PCR components were electrically connected to a control module that could be operated with a Li-ion battery (12 V), and the PCR conditions (temperature, time, cycle, etc.) were inputted on a touch screen. For 30 PCR cycles, the accumulated power consumption of heating and cooling was 7.3 Wh, which is easily available from a compact battery. Escherichia coli genomic DNA (510 bp) was amplified using the proposed PCR thermal cycler and the disposable PCR chip. A similar DNA amplification capability was confirmed using the proposed portable and low-power thermal cycler compared with a conventional thermal cycler.

Scaling vectors of attoJoule per bit modulators

NASA Astrophysics Data System (ADS)

Sorger, Volker J.; Amin, Rubab; Khurgin, Jacob B.; Ma, Zhizhen; Dalir, Hamed; Khan, Sikandar

2018-01-01

Electro-optic modulation performs the conversion between the electrical and optical domain with applications in data communication for optical interconnects, but also for novel optical computing algorithms such as providing nonlinearity at the output stage of optical perceptrons in neuromorphic analog optical computing. While resembling an optical transistor, the weak light-matter-interaction makes modulators 105 times larger compared to their electronic counterparts. Since the clock frequency for photonics on-chip has a power-overhead sweet-spot around tens of GHz, ultrafast modulation may only be required in long-distance communication, not for short on-chip links. Hence, the search is open for power-efficient on-chip modulators beyond the solutions offered by foundries to date. Here, we show scaling vectors towards atto-Joule per bit efficient modulators on-chip as well as some experimental demonstrations of novel plasmonic modulators with sub-fJ/bit efficiencies. Our parametric study of placing different actively modulated materials into plasmonic versus photonic optical modes shows that 2D materials overcompensate their miniscule modal overlap by their unity-high index change. Furthermore, we reveal that the metal used in plasmonic-based modulators not only serves as an electrical contact, but also enables low electrical series resistances leading to near-ideal capacitors. We then discuss the first experimental demonstration of a photon-plasmon-hybrid graphene-based electro-absorption modulator on silicon. The device shows a sub-1 V steep switching enabled by near-ideal electrostatics delivering a high 0.05 dB V-1 μm-1 performance requiring only 110 aJ/bit. Improving on this demonstration, we discuss a plasmonic slot-based graphene modulator design, where the polarization of the plasmonic mode aligns with graphene’s in-plane dimension; where a push-pull dual-gating scheme enables 2 dB V-1 μm-1 efficient modulation allowing the device to be just 770 nm short for 3 dB small signal modulation. Lastly, comparing the switching energy of transistors to modulators shows that modulators based on emerging materials and plasmonic-silicon hybrid integration perform on-par relative to their electronic counter parts. This in turn allows for a device-enabled two orders-of-magnitude improvement of electrical-optical co-integrated network-on-chips over electronic-only architectures. The latter opens technological opportunities in cognitive computing, dynamic data-driven applications systems, and optical analog computer engines including neuromorphic photonic computing.

Josephson junction microwave modulators for qubit control

NASA Astrophysics Data System (ADS)

Naaman, O.; Strong, J. A.; Ferguson, D. G.; Egan, J.; Bailey, N.; Hinkey, R. T.

2017-02-01

We demonstrate Josephson junction based double-balanced mixer and phase shifter circuits operating at 6-10 GHz and integrate these components to implement both a monolithic amplitude/phase vector modulator and an I/Q quadrature mixer. The devices are actuated by flux signals, dissipate no power on chip, exhibit input saturation powers in excess of 1 nW, and provide cryogenic microwave modulation solutions for integrated control of superconducting qubits.

Researching the 915 nm high-power and high-brightness semiconductor laser single chip coupling module

NASA Astrophysics Data System (ADS)

Wang, Xin; Wang, Cuiluan; Wu, Xia; Zhu, Lingni; Jing, Hongqi; Ma, Xiaoyu; Liu, Suping

2017-02-01

Based on the high-speed development of the fiber laser in recent years, the development of researching 915 nm semiconductor laser as main pumping sources of the fiber laser is at a high speed. Because the beam quality of the laser diode is very poor, the 915 nm laser diode is generally based on optical fiber coupling module to output the laser. Using the beam-shaping and fiber-coupling technology to improve the quality of output beam light, we present a kind of high-power and high-brightness semiconductor laser module, which can output 13.22 W through the optical fiber. Based on 915 nm GaAs semiconductor laser diode which has output power of 13.91 W, we describe a thoroughly detailed procedure for reshaping the beam output from the semiconductor laser diode and coupling the beam into the optical fiber of which the core diameter is 105 μm and the numerical aperture is 0.18. We get 13.22 W from the output fiber of the module at 14.5 A, the coupling efficiency of the whole module is 95.03% and the brightness is 1.5 MW/cm2 -str. The output power of the single chip semiconductor laser module achieves the advanced level in the domestic use.

Ultrasound phase rotation beamforming on multi-core DSP.

PubMed

Ma, Jieming; Karadayi, Kerem; Ali, Murtaza; Kim, Yongmin

2014-01-01

Phase rotation beamforming (PRBF) is a commonly-used digital receive beamforming technique. However, due to its high computational requirement, it has traditionally been supported by hardwired architectures, e.g., application-specific integrated circuits (ASICs) or more recently field-programmable gate arrays (FPGAs). In this study, we investigated the feasibility of supporting software-based PRBF on a multi-core DSP. To alleviate the high computing requirement, the analog front-end (AFE) chips integrating quadrature demodulation in addition to analog-to-digital conversion were defined and used. With these new AFE chips, only delay alignment and phase rotation need to be performed by DSP, substantially reducing the computational load. We implemented the delay alignment and phase rotation modules on a Texas Instruments C6678 DSP with 8 cores. We found it takes 200 μs to beamform 2048 samples from 64 channels using 2 cores. With 4 cores, 20 million samples can be beamformed in one second. Therefore, ADC frequencies up to 40 MHz with 2:1 decimation in AFE chips or up to 20 MHz with no decimation can be supported as long as the ADC-to-DSP I/O requirement can be met. The remaining 4 cores can work on back-end processing tasks and applications, e.g., color Doppler or ultrasound elastography. One DSP being able to handle both beamforming and back-end processing could lead to low-power and low-cost ultrasound machines, benefiting ultrasound imaging in general, particularly portable ultrasound machines. Copyright © 2013 Elsevier B.V. All rights reserved.

Ultralow power trapping and fluorescence detection of single particles on an optofluidic chip.

PubMed

Kühn, S; Phillips, B S; Lunt, E J; Hawkins, A R; Schmidt, H

2010-01-21

The development of on-chip methods to manipulate particles is receiving rapidly increasing attention. All-optical traps offer numerous advantages, but are plagued by large required power levels on the order of hundreds of milliwatts and the inability to act exclusively on individual particles. Here, we demonstrate a fully integrated electro-optical trap for single particles with optical excitation power levels that are five orders of magnitude lower than in conventional optical force traps. The trap is based on spatio-temporal light modulation that is implemented using networks of antiresonant reflecting optical waveguides. We demonstrate the combination of on-chip trapping and fluorescence detection of single microorganisms by studying the photobleaching dynamics of stained DNA in E. coli bacteria. The favorable size scaling facilitates the trapping of single nanoparticles on integrated optofluidic chips.

Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS

NASA Astrophysics Data System (ADS)

Park, Chester Sungchung; Park, Sungkyung

2018-07-01

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6 ps and the typical settling time is <30 μs. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2 V single supply. The overall PLL draws about 1.1 mA from the supply.

Modulation response characteristics of optical injection-locked cascaded microring laser

NASA Astrophysics Data System (ADS)

Yu, Shaowei; Pei, Li; Liu, Chao; Wang, Yiqun; Weng, Sijun

2014-09-01

Modulation bandwidth and frequency chirping of the optical injection-locked (OIL) microring laser (MRL) in the cascaded configuration are investigated. The unidirectional operation of the MRL under strong injection allows simple and cost-saving monolithic integration of the OIL system on one chip as it does not need the use of isolators between the master and slave lasers. Two cascading schemes are discussed in detail by focusing on the tailorable modulation response. The chip-to-power ratio of the cascaded optical injection-locked configuration has decreased by up to two orders of magnitude, compared with the single optical injection-locked configuration.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Ultra-Compact, Superconducting Spectrometer-on-a-Chip at Submillimeter Wavelengths

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Zmuidzinas, Jonas; Bradford, Charles M.; Leduc, Henry G.; Day, Peter K.; Swenson, Loren; Hailey-Dunsheath, Steven; O'Brient, Roger C.; Padin, Stephen; Shirokoff, Erik D.;

A Wireless Biomedical Signal Interface System-on-Chip for Body Sensor Networks.

PubMed

Lei Wang; Guang-Zhong Yang; Jin Huang; Jinyong Zhang; Li Yu; Zedong Nie; Cumming, D R S

2010-04-01

Recent years have seen the rapid development of biosensor technology, system-on-chip design, wireless technology. and ubiquitous computing. When assembled into an autonomous body sensor network (BSN), the technologies become powerful tools in well-being monitoring, medical diagnostics, and personal connectivity. In this paper, we describe the first demonstration of a fully customized mixed-signal silicon chip that has most of the attributes required for use in a wearable or implantable BSN. Our intellectual-property blocks include low-power analog sensor interface for temperature and pH, a data multiplexing and conversion module, a digital platform based around an 8-b microcontroller, data encoding for spread-spectrum wireless transmission, and a RF section requiring very few off-chip components. The chip has been fully evaluated and tested by connection to external sensors, and it satisfied typical system requirements.

Demonstration of a Submillimeter-Wave HEMT Oscillator Module at 330 GHz

NASA Technical Reports Server (NTRS)

Radisic, Vesna; Deal, W. R.; Mei, X. B.; Yoshida, Wayne; Liu, P. H.; Uyeda, Jansen; Lai, Richard; Samoska, Lorene; Fung, King Man; Gaier, Todd;

Thin-film decoupling capacitors for multi-chip modules

NASA Astrophysics Data System (ADS)

Dimos, D.; Lockwood, S. J.; Schwartz, R. W.; Rogers, M. S.

Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multi-chip modules. These thin-film decoupling capacitors are intended to replace multi-layer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved high-speed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants ((var epsilon) greater than or equal to 900), low dielectric losses (tan(delta) = 0.01), excellent insulation resistances (rho greater than 10(exp 13) (Omega)-cm at 125 C), and good breakdown field strengths (E(sub B) = 900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 micron thick, which results in a large capacitance/area (8-9 nF/sq mm). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components.

Cooperative Microsystems and Neural Interfaces

DTIC Science & Technology

2009-03-04

polyimide coil for wireless power/data transfer F. Solzbacher, University of Utah – K. Shenoy, Stanford • Demonstrated wireless operation of implanted...Approach: Collapse cable into a single biocompatible optical fiber. Challenge: develop and demonstrate low power multi-channel data acquisition chip

Microchannel cooling of face down bonded chips

DOEpatents

Bernhardt, A.F.

1993-06-08

Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multi chip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

High-power, format-flexible, 885-nm vertical-cavity surface-emitting laser arrays

NASA Astrophysics Data System (ADS)

Wang, Chad; Talantov, Fedor; Garrett, Henry; Berdin, Glen; Cardellino, Terri; Millenheft, David; Geske, Jonathan

2013-03-01

High-power, format flexible, 885 nm vertical-cavity surface-emitting laser (VCSEL) arrays have been developed for solid-state pumping and illumination applications. In this approach, a common VCSEL size format was designed to enable tiling into flexible formats and operating configurations. The fabrication of a common chip size on ceramic submount enables low-cost volume manufacturing of high-power VCSEL arrays. This base VCSEL chip was designed to be 5x3.33 mm2, and produced up to 50 Watts of peak continuous wave (CW) power. To scale to higher powers, multiple chips can be tiled into a combination of series or parallel configurations tailored to the application driver conditions. In actively cooled CW operation, the VCSEL array chips were packaged onto a single water channel cooler, and we have demonstrated 0.5x1, 1x1, and 1x3 cm2 formats, producing 150, 250, and 500 Watts of peak power, respectively, in under 130 A operating current. In QCW operation, the 1x3 cm2 VCSEL module, which contains 18 VCSEL array chips packaged on a single water cooler, produced over 1.3 kW of peak power. In passively cooled packages, multiple chip configurations have been developed for illumination applications, producing over 300 Watts of peak power in QCW operating conditions. These VCSEL chips use a substrate-removed structure to allow for efficient thermal heatsinking to enable high-power operation. This scalable, format flexible VCSEL architecture can be applied to wavelengths ranging from 800 to 1100 nm, and can be used to tailor emission spectral widths and build high-power hyperspectral sources.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Grisi, Marco, E-mail: marco.grisi@epfl.ch; Gualco, Gabriele; Boero, Giovanni

In this article, we present an integrated broadband complementary metal-oxide semiconductor single-chip transceiver suitable for the realization of multi-nuclear pulsed nuclear magnetic resonance (NMR) probes. The realized single-chip transceiver can be interfaced with on-chip integrated microcoils or external LC resonators operating in the range from 1 MHz to 1 GHz. The dimension of the chip is about 1 mm{sup 2}. It consists of a radio-frequency (RF) power amplifier, a low-noise RF preamplifier, a frequency mixer, an audio-frequency amplifier, and fully integrated transmit-receive switches. As specific example, we show its use for multi-nuclear NMR spectroscopy. With an integrated coil of aboutmore » 150 μm external diameter, a {sup 1}H spin sensitivity of about 1.5 × 10{sup 13} spins/Hz{sup 1/2} is achieved at 7 T.« less

40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

NASA Astrophysics Data System (ADS)

Chen, Chin-Hui; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Sato, Tomonari; Kawaguchi, Yoshihiro; Notomi, Masaya; Matsuo, Shinji

2011-08-01

CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

A Self-Sustained Wireless Multi-Sensor Platform Integrated with Printable Organic Sensors for Indoor Environmental Monitoring

PubMed Central

Wu, Chun-Chang; Chuang, Wen-Yu; Wu, Ching-Da; Su, Yu-Cheng; Huang, Yung-Yang; Huang, Yang-Jing; Peng, Sheng-Yu; Yu, Shih-An; Lin, Chih-Ting; Lu, Shey-Shi

2017-01-01

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO2 detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO2 sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO2/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations. PMID:28353680

A Self-Sustained Wireless Multi-Sensor Platform Integrated with Printable Organic Sensors for Indoor Environmental Monitoring.

PubMed

Wu, Chun-Chang; Chuang, Wen-Yu; Wu, Ching-Da; Su, Yu-Cheng; Huang, Yung-Yang; Huang, Yang-Jing; Peng, Sheng-Yu; Yu, Shih-An; Lin, Chih-Ting; Lu, Shey-Shi

2017-03-29

A self-sustained multi-sensor platform for indoor environmental monitoring is proposed in this paper. To reduce the cost and power consumption of the sensing platform, in the developed platform, organic materials of PEDOT:PSS and PEDOT:PSS/EB-PANI are used as the sensing films for humidity and CO₂ detection, respectively. Different from traditional gas sensors, these organic sensing films can operate at room temperature without heating processes or infrared transceivers so that the power consumption of the developed humidity and the CO₂ sensors can be as low as 10 μW and 5 μW, respectively. To cooperate with these low-power sensors, a Complementary Metal-Oxide-Semiconductor (CMOS) system-on-chip (SoC) is designed to amplify and to read out multiple sensor signals with low power consumption. The developed SoC includes an analog-front-end interface circuit (AFE), an analog-to-digital convertor (ADC), a digital controller and a power management unit (PMU). Scheduled by the digital controller, the sensing circuits are power gated with a small duty-cycle to reduce the average power consumption to 3.2 μW. The designed PMU converts the power scavenged from a dye sensitized solar cell (DSSC) module into required supply voltages for SoC circuits operation under typical indoor illuminance conditions. To our knowledge, this is the first multiple environmental parameters (Temperature/CO₂/Humidity) sensing platform that demonstrates a true self-powering functionality for long-term operations.

Latest generation of ASICs for photodetector readout

NASA Astrophysics Data System (ADS)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

Simulation of cooling efficiency via miniaturised channels in multilayer LTCC for power electronics

NASA Astrophysics Data System (ADS)

Pietrikova, Alena; Girasek, Tomas; Lukacs, Peter; Welker, Tilo; Müller, Jens

2017-03-01

The aim of this paper is detailed investigation of thermal resistance, flow analysis and distribution of coolant as well as thermal distribution inside multilayer LTCC substrates with embedded channels for power electronic devices by simulation software. For this reason four various structures of internal channels in the multilayer LTCC substrates were designed and simulated. The impact of the volume flow, structures of channels, and power loss of chip was simulated, calculated and analyzed by using the simulation software Mentor Graphics FloEFDTM. The structure, size and location of channels have the significant impact on thermal resistance, pressure of coolant as well as the effectivity of cooling power components (chips) that can be placed on the top of LTCC substrate. The main contribution of this paper is thermal analyze, optimization and impact of 4 various cooling channels embedded in LTCC multilayer structure. Paper investigate, the effect of volume flow in cooling channels for achieving the least thermal resistance of LTCC substrate that is loaded by power thermal chips. Paper shows on the impact of the first chips thermal load on the second chip as well as. This possible new technology could ensure in the case of practical realization effective cooling and increasing reliability of high power modules.

Narrow linewidth diode laser modules for quantum optical sensor applications in the field and in space

NASA Astrophysics Data System (ADS)

Wicht, A.; Bawamia, A.; Krüger, M.; Kürbis, Ch.; Schiemangk, M.; Smol, R.; Peters, A.; Tränkle, G.

2017-02-01

We present the status of our efforts to develop very compact and robust diode laser modules specifically suited for quantum optics experiments in the field and in space. The paper describes why hybrid micro-integration and GaAs-diode laser technology is best suited to meet the needs of such applications. The electro-optical performance achieved with hybrid micro-integrated, medium linewidth, high power distributed-feedback master-oscillator-power-amplifier modules and with medium power, narrow linewidth extended cavity diode lasers emitting at 767 nm and 780 nm are briefly described and the status of space relevant stress tests and space heritage is summarized. We also describe the performance of an ECDL operating at 1070 nm. Further, a novel and versatile technology platform is introduced that allows for integration of any type of laser system or electro-optical module that can be constructed from two GaAs chips. This facilitates, for the first time, hybrid micro-integration, e.g. of extended cavity diode laser master-oscillator-poweramplifier modules, of dual-stage optical amplifiers, or of lasers with integrated, chip-based phase modulator. As an example we describe the implementation of an ECDL-MOPA designed for experiments on ultra-cold rubidium and potassium atoms on board a sounding rocket and give basic performance parameters.

Vertically aligned carbon nanofiber as nano-neuron interface for monitoring neural function

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ericson, Milton Nance; McKnight, Timothy E; Melechko, Anatoli Vasilievich

2012-01-01

Neural chips, which are capable of simultaneous, multi-site neural recording and stimulation, have been used to detect and modulate neural activity for almost 30 years. As a neural interface, neural chips provide dynamic functional information for neural decoding and neural control. By improving sensitivity and spatial resolution, nano-scale electrodes may revolutionize neural detection and modulation at cellular and molecular levels as nano-neuron interfaces. We developed a carbon-nanofiber neural chip with lithographically defined arrays of vertically aligned carbon nanofiber electrodes and demonstrated its capability of both stimulating and monitoring electrophysiological signals from brain tissues in vitro and monitoring dynamic information ofmore » neuroplasticity. This novel nano-neuron interface can potentially serve as a precise, informative, biocompatible, and dual-mode neural interface for monitoring of both neuroelectrical and neurochemical activity at the single cell level and even inside the cell.« less

Dry-film polymer waveguide for silicon photonics chip packaging.

PubMed

Hsu, Hsiang-Han; Nakagawa, Shigeru

2014-09-22

Polymer waveguide made by dry film process is demonstrated for silicon photonics chip packaging. With 8 μm × 11.5 μm core waveguide, little penalty is observed up to 25 Gbps before or after the light propagate through a 10-km long single-mode fiber (SMF). Coupling loss to SMF is 0.24 dB and 1.31 dB at the polymer waveguide input and output ends, respectively. Alignment tolerance for 0.5 dB loss increase is +/- 1.0 μm along both vertical and horizontal directions for the coupling from the polymer waveguide to SMF. The dry-film polymer waveguide demonstrates promising performance for silicon photonics chip packaging used in next generation optical multi-chip module.

Design of intelligent vehicle control system based on single chip microcomputer

NASA Astrophysics Data System (ADS)

Zhang, Congwei

2018-06-01

The smart car microprocessor uses the KL25ZV128VLK4 in the Freescale series of single-chip microcomputers. The image sampling sensor uses the CMOS digital camera OV7725. The obtained track data is processed by the corresponding algorithm to obtain track sideline information. At the same time, the pulse width modulation control (PWM) is used to control the motor and servo movements, and based on the digital incremental PID algorithm, the motor speed control and servo steering control are realized. In the project design, IAR Embedded Workbench IDE is used as the software development platform to program and debug the micro-control module, camera image processing module, hardware power distribution module, motor drive and servo control module, and then complete the design of the intelligent car control system.

A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission

NASA Astrophysics Data System (ADS)

Wu, Chang-Hsi; You, Hong-Cheng; Huang, Shun-Zhao

2018-02-01

An architecture of 5.2/5.8-GHz dual-band on-off keying (DBOOK) modulated transmitter is designed in a 0.18-μm CMOS technology. The proposed DBOOK transmitter is used in the biosignal transmission system with high power efficiency and small area. To reduce power consumption and enhance output swing, two pairs of center-tapped transformers are used as both LC tank and source grounding choke for the designed voltage controlled oscillator (VCO). Switching capacitances are used to achieve dual band operations, and a complemented power combiner is used to merge the differential output power of VCO to a single-ended output. Besides, the linearizer circuits are used in the proposed power amplifier with wideband output matching to improve the linearity both at 5.2/5.8-GHz bands. The designed DBOOK transmitter is implemented by dividing it into two chips. One chip implements the dual-band switching VCO and power combiner, and the other chip implements a linear power amplifier including dual-band operation. The first chip drives an output power of 2.2mW with consuming power of 5.13 mW from 1.1 V supply voltage. With the chip size including pad of 0.61 × 0.91 m2, the measured data rate and transmission efficiency attained are 100 Mb/s and 51 pJ/bit, respectively. The second chip, for power enhanced mode, exhibits P1 dB of -9 dBm, IIP3 of 1 dBm, the output power 1 dB compression point of 12.42 dBm, OIP3 of about 21 dBm, maximum output power of 17.02/16.18 dBm, and power added efficiency of 17.13/16.95% for 5.2/ 5.8 GHz. The chip size including pads is 0:693 × 1:084mm2.

A Low Power, Parallel Wearable Multi-Sensor System for Human Activity Evaluation.

PubMed

Li, Yuecheng; Jia, Wenyan; Yu, Tianjian; Luan, Bo; Mao, Zhi-Hong; Zhang, Hong; Sun, Mingui

2015-04-01

In this paper, the design of a low power heterogeneous wearable multi-sensor system, built with Zynq System-on-Chip (SoC), for human activity evaluation is presented. The powerful data processing capability and flexibility of this SoC represent significant improvements over our previous ARM based system designs. The new system captures and compresses multiple color images and sensor data simultaneously. Several strategies are adopted to minimize power consumption. Our wearable system provides a new tool for the evaluation of human activity, including diet, physical activity and lifestyle.

A low power on-chip class-E power amplifier for remotely powered implantable sensor systems

NASA Astrophysics Data System (ADS)

Ture, Kerim; Kilinc, Enver G.; Dehollain, Catherine

2015-06-01

This paper presents a low power fully integrated class-E power amplifier and its integration with remotely powered sensor system. The class-E power amplifier is suitable solution for low-power applications due to its high power efficiency. However, the required high inductance values which make the on-chip integration of the power amplifier difficult. The designed power amplifier is fully integrated in the remotely powered sensor system and fabricated in 0.18 μm CMOS process. The power is transferred to the implantable sensor system at 13.56 MHz by using an inductively coupled remote powering link. The induced AC voltage on the implant coil is converted into a DC voltage by a passive full-wave rectifier. A voltage regulator is used to suppress the ripples and create a clean and stable 1.8 V supply voltage for the sensor and communication blocks. The data collected from the sensors is transmitted by on-off keying modulated low-power transmitter at 1.2 GHz frequency. The transmitter is composed of a LC tank oscillator and a fully on-chip class-E power amplifier. An additional output network is used for the power amplifier which makes the integration of the power amplifier fully on-chip. The integrated power amplifier with 0.2 V supply voltage has a drain efficiency of 31.5% at -10 dBm output power for 50 Ω load. The measurement results verify the functionality of the power amplifier and the remotely powered implantable sensor system. The data communication is also verified by using a commercial 50 Ω chip antenna and has 600 kbps data rate at 1 m communication distance.

Design, fabrication, and packaging of an integrated, wirelessly-powered optrode array for optogenetics application

PubMed Central

Kwon, Ki Yong; Lee, Hyung-Min; Ghovanloo, Maysam; Weber, Arthur; Li, Wen

2015-01-01

The recent development of optogenetics has created an increased demand for advancing engineering tools for optical modulation of neural circuitry. This paper details the design, fabrication, integration, and packaging procedures of a wirelessly-powered, light emitting diode (LED) coupled optrode neural interface for optogenetic studies. The LED-coupled optrode array employs microscale LED (μLED) chips and polymer-based microwaveguides to deliver light into multi-level cortical networks, coupled with microelectrodes to record spontaneous changes in neural activity. An integrated, implantable, switched-capacitor based stimulator (SCS) system provides high instantaneous power to the μLEDs through an inductive link to emit sufficient light and evoke neural activities. The presented system is mechanically flexible, biocompatible, miniaturized, and lightweight, suitable for chronic implantation in small freely behaving animals. The design of this system is scalable and its manufacturing is cost effective through batch fabrication using microelectromechanical systems (MEMS) technology. It can be adopted by other groups and customized for specific needs of individual experiments. PMID:25999823

NASA Tech Briefs, June 2009

NASA Technical Reports Server (NTRS)

2009-01-01

Topics covered include: Device for Measuring Low Flow Speed in a Duct, Measuring Thermal Conductivity of a Small Insulation Sample, Alignment Jig for the Precise Measurement of THz Radiation, Autoignition Chamber for Remote Testing of Pyrotechnic Devices, Microwave Power Combiners for Signals of Arbitrary Amplitude, Synthetic Foveal Imaging Technology, Airborne Antenna System for Minimum-Cycle-Slip GPS Reception, Improved Starting Materials for Back-Illuminated Imagers, Multi-Modulator for Bandwidth-Efficient Communication, Some Improvements in Utilization of Flash Memory Devices, GPS/MEMS IMU/Microprocessor Board for Navigation, T/R Multi-Chip MMIC Modules for 150 GHz, Pneumatic Haptic Interfaces, Device Acquires and Retains Rock or Ice Samples, Cryogenic Feedthrough Test Rig, Improved Assembly for Gas Shielding During Welding or Brazing, Two-Step Plasma Process for Cleaning Indium Bonding Bumps, Tool for Crimping Flexible Circuit Leads, Yb14MnSb11 as a High-Efficiency Thermoelectric Material, Polyimide-Foam/Aerogel Composites for Thermal Insulation, Converting CSV Files to RKSML Files, Service Management Database for DSN Equipment, Chemochromic Hydrogen Leak Detectors, Compatibility of Segments of Thermoelectric Generators, Complementary Barrier Infrared Detector, JPL Greenland Moulin Exploration Probe, Ultra-Lightweight Self-Deployable Nanocomposite Structure for Habitat Applications, and Room-Temperature Ionic Liquids for Electrochemical Capacitors.

Thermal management and light extraction in multi-chip and high-voltage LEDs by cup-shaped copper heat spreader technology

NASA Astrophysics Data System (ADS)

Horng, Ray-Hua; Hu, Hung-Lieh; Tang, Li-Shen; Ou, Sin-Liang

2013-03-01

For LEDs with original structure and copper heat spreader, the highest surface temperatures of 3×3 array LEDs modules were 52.6 and 42.67 °C (with 1050 mA injection current), while the highest surface temperatures of 4×4 array LEDs modules were 58.55 and 48.85 °C (with 1400 mA injection current), respectively. As the 5×5 array LEDs modules with original structure and copper heat spreader were fabricated, the highest surface temperatures at 1750 mA injection current were 68.51 and 56.73 °C, respectively. The thermal resistance of optimal LEDs array module with copper heat spreader on heat sink using compound solder is reduced obviously. On the other hand, the output powers of 3×3, 4×4 and 5×5 array LEDs modules with original structure were 3621.7, 6346.3 and 9760.4 mW at injection currents of 1050, 1400 and 1750 mA, respectively. Meanwhile, the output powers of these samples with copper heat spreader can be improved to 4098.5, 7150.3 and 10919.6 mW, respectively. The optical and thermal characteristics of array LEDs module have been improved significantly using the cup-shaped copper structure. Furthermore, various types of epoxy-packaged LEDs with cup-shaped structure were also fabricated. It is found that the light extraction efficiency of LED with semicircle package has 55% improvement as compared to that of LED with flat package. The cup-shaped copper structure was contacted directly with sapphire to enhance heat dissipation. In addition to efficient heat dissipation, the light extraction of the lateral emitting in high-power LEDs can be improved.

Technology transfer of military space microprocessor developments

NASA Astrophysics Data System (ADS)

Gorden, C.; King, D.; Byington, L.; Lanza, D.

1999-01-01

Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

NANOSPACE-1: the Impacts of the First Swedish Nanosatellite on Spacecraft Architecture and Design

NASA Astrophysics Data System (ADS)

Bruhn, F.; Köhler, J.; Stenmark, L.

2002-01-01

NanoSpace-1 (NS-1), due to be launched in late 2003 or early 2004 will test highly advanced Micro Systems Technology (MST) for space applications. These devices are highly miniaturized and optimized complete systems in the sense that all parts of the system are processed with MST and integrated as Multifunctional Microsystems (MMS). The very high level of miniaturization and multifunctionallity in the MMS, will enable easier access to space for nanosatellites to perform better scientific research. This new class of high performing small satellites will open areas for research that before only could be done with much larger and costly satellites. Many institutions, universities, and small countries will benefit greatly as that nanosatellites become more capable per mass unit and volume unit than other spacecraft. These new MMS/MST satellites will provide the ground for a better and less expensive exploration of space. NS-1 will be the first high-performing nanosatellite by using MST/MMS to many subsystems and modules. The whole spacecraft will be built around MMS and will include multifunctional 3D-Multi Chip Modules (3D-MCM), a 3D thin film solar sensor, thin film coating for passive thermal control, variable emittance panels, microwave MEMS patch antennas, micromechanical thermal switches, thin film solar cells with record high efficiency and finally silicon as multifunctional active structure elements. The complete spacecraft will weigh about 7 kg and have dimensions of 32x32x15 cm. The overall mission for NS-1 is to test the new technologies mentioned above, and to collect experiences in the field of MMS architecture. However, new technologies in itself will not take us to a new generation spacecraft. Deeply integrated within the structure of the NanoSpace program are new system designs and multifunctional systems thinking. Distributed and autonomous subsystems are very important when incorporating new technologies with high redundancy. Autonomous systems also reduce the complexity of the overall spacecraft design since many functions can be placed in multifunctional multichip modules. This implies an increase of the complexity at the spacecraft subsystem level. NanoSpace-1 will test several new autonomous, distributed, and miniaturized multifunctional systems, including large memories modules, house keeping modules, RF- MEMS, and power conditioning modules. The MMS concept comprises several features, for instance, all 3D-multi chip modules are part of the spacecraft structure itself. The use of 3D-MCM modules as a large part of the spacecraft hull is a direct application of MMS thinking; the modules are load taking structure elements, and also contain many subsystems of the spacecraft. The MMS thinking is illustrated by the RF-MEMS 3D-MCM module. All other modules will be further presented in the paper. The RF-MEMS module comprises micro strips, patch-antennas, solid state power amplifiers, thermal control, micromechanical switches, power conditioning, radiation shields, and command interfaces. The size of the RF-module is 68x68x5 mm and has a weight of less than 70g. The module is designed to handle different frequencies, only by changing the top wafers and the mixer chip. MST and MMS integrated modules pose at least two major challenges compared to conventional technology. First, the processes cannot be changed half way to the product. Any substantial change in the process will almost certainly require a complete redesign of the whole system. Secondly, qualification and product assurance becomes more important since the processes in MMS tend to be long and complicated. The Ångström Space Technology Centre (ÅSTC) is a center for development of Micro Systems Technologies (MST) for Space Applications at the department of Materials Science at Uppsala University in Sweden. The center is now taking the next step in the ongoing Nanosatellite program, called the NanoSpace program. Backed by funding from the Swedish National Space Board (SNSB), the European Space Agency (ESA), and the European Commission (EC), the ÅSTC will begin developing nanosatellites to demonstrate the next generation spacecraft. The Nanosatellite program is built around a launch every 2nd year to test, verify and qualify new MST technologies for space. The Nanosatellite effort is a solid and well founded program with a backbone of technology research and Multifunctional Microsystems (MMS) thinking.

Modular multi-element high energy particle detector

DOEpatents

Coon, D.D.; Elliott, J.P.

1990-01-02

Multi-element high energy particle detector modules comprise a planar heavy metal carrier of tungsten alloy with planar detector units uniformly distributed over one planar surface. The detector units are secured to the heavy metal carrier by electrically conductive adhesive so that the carrier serves as a common ground. The other surface of each planar detector unit is electrically connected to a feedthrough electrical terminal extending through the carrier for front or rear readout. The feedthrough electrical terminals comprise sockets at one face of the carrier and mating pins projecting from the other face, so that any number of modules may be plugged together to create a stack of modules of any desired number of radiation lengths. The detector units each comprise four, preferably rectangular, p-i-n diode chips arranged around the associated feedthrough terminal to form a square detector unit providing at least 90% detector element coverage of the carrier. Integral spacers projecting from the carriers extend at least partially along the boundaries between detector units to space the p-i-n diode chips from adjacent carriers in a stack. The spacers along the perimeters of the modules are one-half the width of the interior spacers so that when stacks of modules are arranged side by side to form a large array of any size or shape, distribution of the detector units is uniform over the entire array. 5 figs.

Modular multi-element high energy particle detector

DOEpatents

Coon, Darryl D.; Elliott, John P.

1990-01-02

Multi-element high energy particle detector modules comprise a planar heavy metal carrier of tungsten alloy with planar detector units uniformly distributed over one planar surface. The detector units are secured to the heavy metal carrier by electrically conductive adhesive so that the carrier serves as a common ground. The other surface of each planar detector unit is electrically connected to a feedthrough electrical terminal extending through the carrier for front or rear readout. The feedthrough electrical terminals comprise sockets at one face of the carrier and mating pins porjecting from the other face, so that any number of modules may be plugged together to create a stack of modules of any desired number of radiation lengths. The detector units each comprise four, preferably rectangular, p-i-n diode chips arranged around the associated feedthrough terminal to form a square detector unit providing at least 90% detector element coverage of the carrier. Integral spacers projecting from the carriers extend at least partially along the boundaries between detector units to space the p-i-n diode chips from adjacent carriers in a stack. The spacers along the perimeters of the modules are one-half the width of the interior spacers so that when stacks of modules are arranged side by side to form a large array of any size or shape, distribution of the detector units is uniform over the entire array.

Simultaneous detection of multiple HPV DNA via bottom-well microfluidic chip within an infra-red PCR platform.

PubMed

Liu, Wenjia; Warden, Antony; Sun, Jiahui; Shen, Guangxia; Ding, Xianting

2018-03-01

Portable Polymerase Chain Reaction (PCR) devices combined with microfluidic chips or lateral flow stripes have shown great potential in the field of point-of-need testing (PoNT) as they only require a small volume of patient sample and are capable of presenting results in a short time. However, the detection for multiple targets in this field leaves much to be desired. Herein, we introduce a novel PCR platform by integrating a bottom-well microfluidic chip with an infra-red (IR) excited temperature control method and fluorescence co-detection of three PCR products. Microfluidic chips are utilized to partition different samples into individual bottom-wells. The oil phase in the main channel contains multi-walled carbon nanotubes which were used as a heat transfer medium that absorbs energy from the IR-light-emitting diode (LED) and transfers heat to the water phase below. Cyclical rapid heating and cooling necessary for PCR are achieved by alternative power switching of the IR-LED and Universal Serial Bus (USB) mini-fan with a pulse width modulation scheme. This design of the IR-LED PCR platform is economic, compact, and fully portable, making it a promising application in the field of PoNT. The bottom-well microfluidic chip and IR-LED PCR platform were combined to fulfill a three-stage thermal cycling PCR for 40 cycles within 90 min for Human Papilloma Virus (HPV) detection. The PCR fluorescent signal was successfully captured at the end of each cycle. The technique introduced here has broad applications in nucleic acid amplification and PoNT devices.

Power-efficient dual-rate optical transceiver.

PubMed

Zuo, Yongrong; Kiamiley, Fouad E; Wang, Xiaoqing; Gui, Ping; Ekman, Jeremy; Wang, Xingle; McFadden, Michael J; Haney, Michael W

2005-11-20

A dual-rate (2 Gbit/s and 100 Mbit/s) optical transceiver designed for power-efficient connections within and between modern high-speed digital systems is described. The transceiver can dynamically adjust its data rate according to performance requirements, allowing for power-on-demand operation. Dynamic power management permits energy saving and lowers device operating temperatures, improving the reliability and lifetime of optoelectronic-devices such as vertical-cavity surface-emitting lasers (VCSELs). To implement dual-rate functionality, we include in the transmitter and receiver circuits separate high-speed and low-power data path modules. The high-speed module is designed for gigabit operation to achieve high bandwidth. A simpler low-power module is designed for megabit data transmission with low power consumption. The transceiver is fabricated in a 0.5 microm silicon-on-sapphire complementary metal-oxide semiconductor. The VCSEL and photodetector devices are attached to the transceiver's integrated circuit by flip-chip bonding. A free-space optical link system is constructed to demonstrate correct dual-rate functionality. Experimental results show reliable link operation at 2 Gbit/s and 100 Mbit/s data transfer rates with approximately 104 and approximately 9 mW power consumption, respectively. The transceiver's switching time between these two data rates is demonstrated as 10 micros, which is limited by on-chip register reconfiguration time. Improvement of this switching time can be obtained by use of dedicated input-output pads for dual-rate control signals.

3D packaging of a microfluidic system with sensory applications

NASA Astrophysics Data System (ADS)

Morrissey, Anthony; Kelly, Gerard; Alderman, John C.

1997-09-01

Among the main benefits of microsystem technology are its contributions to cost reductio, reliability and improved performance. however, the packaging of microsystems, and particularly microsensor, has proven to be one of the biggest limitations to their commercialization and the packaging of silicon sensor devices can be the most costly part of their fabrication. This paper describes the integration of 3D packaging of a microsystem. Central to the operation of the 3D demonstrator is a micromachined silicon membrane pump to supply fluids to a sensing chamber constructed about the active area of a sensor chip. This chip carries ISFET based chemical sensors, pressure sensors and thermal sensors. The electronics required for controlling and regulating the activity of the various sensors ar also available on this chip and as other chips in the 3D assembly. The demonstrator also contains a power supply module with optical fiber interconnections. All of these modules are integrated into a single plastic- encapsulated 3D vertical multichip module. The reliability of such a structure, initially proposed by Val was demonstrated by Barrett et al. An additional module available for inclusion in some of our assemblies is a test chip capable of measuring the packaging-induced stress experienced during and after assembly. The packaging process described produces a module with very high density and utilizes standard off-the-shelf components to minimize costs. As the sensor chip and micropump include micromachined silicon membranes and microvalves, the packaging of such structures has to allow consideration for the minimization of the packaging-induced stresses. With this in mind, low stress techniques, including the use of soft glob-top materials, were employed.

A multi-channel isolated power supply in non-equipotential circuit

NASA Astrophysics Data System (ADS)

Li, Xiang; Zhao, Bo-Wen; Zhang, Yan-Chi; Xie, Da

2018-04-01

A multi-channel isolation power supply is designed for the problems of different MOSFET or IGBT in the non-equipotential circuit in this paper. It mainly includes the square wave generation circuit, the high-frequency transformer and the three-terminal stabilized circuit. The first part is used to generate the 24V square wave, and as the input of the magnetic ring transformer. In the second part, the magnetic ring transformer consists of one input and three outputs to realize multi-channel isolation output. The third part can output different potential and realize non-equal potential function through the three-terminal stabilized chip. In addition, the multi-channel isolation power source proposed in this paper is Small size, high reliability and low price, and it is convenient for power electronic switches that operate on multiple different potentials. Therefore, the research on power supply of power electronic circuit has practical significance.

Silicon photonics: some remaining challenges

NASA Astrophysics Data System (ADS)

Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

2016-03-01

This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

Materials Research for GHz Multi-Chip Modules

DTIC Science & Technology

1993-09-30

Publications: Laursen, K., Hertling, D., Berry, N., Bidstrup, S.A., Kohl, P., and Arroz , A., "Measurement of the Electrical Properties of Hligh Performance...Materials, Fall 1992. Herding, D.R., Laursen, K., Bidstrup, S.A., Kohl, P.A., Arroz , G.S.., "Measurement of the Electrical Properties of High

A multi-channel instrumentation system for biosignal recording.

PubMed

Yu, Hong; Li, Pengfei; Xiao, Zhiming; Peng, Chung-Ching; Bashirullah, Rizwan

2008-01-01

This paper reports a highly integrated battery operated multi-channel instrumentation system intended for physiological signal recording. The mixed signal IC has been fabricated in standard 0.5microm 5V 3M-2P CMOS process and features 32 instrumentation amplifiers, four 8b SAR ADCs, a wireless power interface with Li-ion battery charger, low power bidirectional telemetry and FSM controller with power gating control for improved energy efficiency. The chip measures 3.2mm by 4.8mm and dissipates approximately 2.1mW when fully operational.

A portable optical reader and wall projector towards enumeration of bio-conjugated beads or cells

PubMed Central

McArdle, Niamh A.; Kendlin, Jane L.; O’Connell, Triona M.; Ducrée, Jens

2017-01-01

Measurement of the height of a packed column of cells or beads, which can be direclty related to the number of cells or beads present in a chamber, is an important step in a number of diagnostic assays. For example, haematocrit measurements may rapidly identify anemia or polycthemia. Recently, user-friendly and cost-efficient Lab-on-a-Chip devices have been developed towards isolating and counting cell sub-populations for diagnostic purposes. In this work, we present a low-cost optical module for estimating the filling level of packed magnetic beads within a Lab-on-a-Chip device. The module is compatible with a previously introduced, disposable microfluidic chip for rapid determination of CD4+ cell counts. The device is a simple optical microscope module is manufactured by 3D printing. An objective lens directly interrogates the height of packed beads which are efficiently isolated on the finger-actuated chip. Optionally, an inexpensive, battery-powered Light Emitting Diode may project a shadow of the microfluidic chip at approximately 50-fold magnification onto a nearby surface. The reader is calibrated with the filling levels of known concentrations of paramagnetic beads within the finger actuated chip. Results in direct and projector mode are compared to measurements from a conventional, inverted white-light microscope. All three read-out methods indicate a maximum variation of 6.5% between methods. PMID:29267367

A CMOS One-chip Wireless Camera with Digital Image Transmission Function for Capsule Endoscopes

NASA Astrophysics Data System (ADS)

Itoh, Shinya; Kawahito, Shoji; Terakawa, Susumu

This paper presents the design and implementation of a one-chip camera device for capsule endoscopes. This experimental chip integrates functional circuits required for capsule endoscopes and digital image transmission function. The integrated functional blocks include an image array, a timing generator, a clock generator, a voltage regulator, a 10b cyclic A/D converter, and a BPSK modulator. It can be operated autonomously with 3 pins (VDD, GND, and DATAOUT). A prototype image sensor chip which has 320x240 effective pixels was fabricated using 0.25μm CMOS image sensor process and the autonomous imaging was demonstrated. The chip size is 4.84mmx4.34mm. With a 2.0 V power supply, the analog part consumes 950μW and the total power consumption at 2 frames per second (fps) is 2.6mW. Error-free image transmission over a distance of 48cm at 2.5Mbps corresponding to 2fps has been succeeded with inductive coupling.

Direct cooled power electronics substrate

DOEpatents

Wiles, Randy H [Powell, TN; Wereszczak, Andrew A [Oak Ridge, TN; Ayers, Curtis W [Kingston, TN; Lowe, Kirk T [Knoxville, TN

2010-09-14

The disclosure describes directly cooling a three-dimensional, direct metallization (DM) layer in a power electronics device. To enable sufficient cooling, coolant flow channels are formed within the ceramic substrate. The direct metallization layer (typically copper) may be bonded to the ceramic substrate, and semiconductor chips (such as IGBT and diodes) may be soldered or sintered onto the direct metallization layer to form a power electronics module. Multiple modules may be attached to cooling headers that provide in-flow and out-flow of coolant through the channels in the ceramic substrate. The modules and cooling header assembly are preferably sized to fit inside the core of a toroidal shaped capacitor.

Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

PubMed

Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

2014-01-01

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

VLSI design of lossless frame recompression using multi-orientation prediction

NASA Astrophysics Data System (ADS)

Lee, Yu-Hsuan; You, Yi-Lun; Chen, Yi-Guo

2016-01-01

Pursuing an experience of high-end visual quality drives human to demand a higher display resolution and a higher frame rate. Hence, a lot of powerful coding tools are aggregated together in emerging video coding standards to improve coding efficiency. This also makes video coding standards suffer from two design challenges: heavy computation and tremendous memory bandwidth. The first issue can be properly solved by a careful hardware architecture design with advanced semiconductor processes. Nevertheless, the second one becomes a critical design bottleneck for a modern video coding system. In this article, a lossless frame recompression using multi-orientation prediction technique is proposed to overcome this bottleneck. This work is realised into a silicon chip with the technology of TSMC 0.18 µm CMOS process. Its encoding capability can reach full-HD (1920 × 1080)@48 fps. The chip power consumption is 17.31 mW@100 MHz. Core area and chip area are 0.83 × 0.83 mm2 and 1.20 × 1.20 mm2, respectively. Experiment results demonstrate that this work exhibits an outstanding performance on lossless compression ratio with a competitive hardware performance.

Gigascale Silicon Photonic Transmitters Integrating HBT-based Carrier-injection Electroabsorption Modulator Structures

NASA Astrophysics Data System (ADS)

Fu, Enjin

Demand for more bandwidth is rapidly increasing, which is driven by data intensive applications such as high-definition (HD) video streaming, cloud storage, and terascale computing applications. Next-generation high-performance computing systems require power efficient chip-to-chip and intra-chip interconnect yielding densities on the order of 1Tbps/cm2. The performance requirements of such system are the driving force behind the development of silicon integrated optical interconnect, providing a cost-effective solution for fully integrated optical interconnect systems on a single substrate. Compared to conventional electrical interconnect, optical interconnects have several advantages, including frequency independent insertion loss resulting in ultra wide bandwidth and link latency reduction. For high-speed optical transmitter modules, the optical modulator is a key component of the optical I/O channel. This thesis presents a silicon integrated optical transmitter module design based on a novel silicon HBT-based carrier injection electroabsorption modulator (EAM), which has the merits of wide optical bandwidth, high speed, low power, low drive voltage, small footprint, and high modulation efficiency. The structure, mechanism, and fabrication of the modulator structure will be discussed which is followed by the electrical modeling of the post-processed modulator device. The design and realization of a 10Gbps monolithic optical transmitter module integrating the driver circuit architecture and the HBT-based EAM device in a 130nm BiCMOS process is discussed. For high power efficiency, a 6Gbps ultra-low power driver IC implemented in a 130nm BiCMOS process is presented. The driver IC incorporates an integrated 27-1 pseudo-random bit sequence (PRBS) generator for reliable high-speed testing, and a driver circuit featuring digitally-tuned pre-emphasis signal strength. With outstanding drive capability, the driver module can be applied to a wide range of carrier injection modulators and light-emitting diodes (LED) with drive voltage requirements below 1.5V. Measurement results show an optical link based on a 70MHz red LED work well at 300Mbps by using the pre-emphasis driver module. A traveling wave electrode (TWE) modulator structure is presented, including a novel design methodology to address process limitations imposed by a commercial silicon fabrication technology. Results from 3D full wave EM simulation demonstrate the application of the design methodology to achieve specifications, including phase velocity matching, insertion loss, and impedance matching. Results show the HBT-based TWE-EAM system has the bandwidth higher than 60GHz.

High Performance Power Module for Hall Effect Thrusters

NASA Technical Reports Server (NTRS)

Pinero, Luis R.; Peterson, Peter Y.; Bowers, Glen E.

2002-01-01

Previous efforts to develop power electronics for Hall thruster systems have targeted the 1 to 5 kW power range and an output voltage of approximately 300 V. New Hall thrusters are being developed for higher power, higher specific impulse, and multi-mode operation. These thrusters require up to 50 kW of power and a discharge voltage in excess of 600 V. Modular power supplies can process more power with higher efficiency at the expense of complexity. A 1 kW discharge power module was designed, built and integrated with a Hall thruster. The breadboard module has a power conversion efficiency in excess of 96 percent and weighs only 0.765 kg. This module will be used to develop a kW, multi-kW, and high voltage power processors.

Compact silicon photonics-based multi laser module for sensing

NASA Astrophysics Data System (ADS)

Ayotte, S.; Costin, F.; Babin, A.; Paré-Olivier, G.; Morin, M.; Filion, B.; Bédard, K.; Chrétien, P.; Bilodeau, G.; Girard-Deschênes, E.; Perron, L.-P.; Davidson, C.-A.; D'Amato, D.; Laplante, M.; Blanchet-Létourneau, J.

2018-02-01

A compact three-laser source for optical sensing is presented. It is based on a low-noise implementation of the Pound Drever-Hall method and comprises high-bandwidth optical phase-locked loops. The outputs from three semiconductor distributed feedback lasers, mounted on thermo-electric coolers (TEC), are coupled with micro-lenses into a silicon photonics (SiP) chip that performs beat note detection and several other functions. The chip comprises phase modulators, variable optical attenuators, multi-mode-interference couplers, variable ratio tap couplers, integrated photodiodes and optical fiber butt-couplers. Electrical connections between a metallized ceramic and the TECs, lasers and SiP chip are achieved by wirebonds. All these components stand within a 35 mm by 35 mm package which is interfaced with 90 electrical pins and two fiber pigtails. One pigtail carries the signals from a master and slave lasers, while another carries that from a second slave laser. The pins are soldered to a printed circuit board featuring a micro-processor that controls and monitors the system to ensure stable operation over fluctuating environmental conditions. This highly adaptable multi-laser source can address various sensing applications requiring the tracking of up to three narrow spectral features with a high bandwidth. It is used to sense a fiber-based ring resonator emulating a resonant fiber optics gyroscope. The master laser is locked to the resonator with a loop bandwidth greater than 1 MHz. The slave lasers are offset frequency locked to the master laser with loop bandwidths greater than 100 MHz. This high performance source is compact, automated, robust, and remains locked for days.

Packaging of a large capacity magnetic bubble domain spacecraft recorder

NASA Technical Reports Server (NTRS)

Becker, F. J.; Stermer, R. L.

1977-01-01

A Solid State Spacecraft Data Recorder (SSDR), based on bubble domain technology, having a storage capacity of 10 to the 8th power bits, was designed and is being tested. The recorder consists of two memory modules each having 32 cells, each cell containing sixteen 100 kilobit serial bubble memory chips. The memory modules are interconnected to a Drive and Control Unit (DCU) module containing four microprocessors, 500 integrated circuits, a RAM core memory and two PROM's. The two memory modules and DCU are housed in individual machined aluminum frames, are stacked in brick fashion and through bolted to a base plate assembly which also houses the power supply.

Examination of a Thermally Viable Structure for an Unconventional Uni-Leg Mg2Si Thermoelectric Power Generator

NASA Astrophysics Data System (ADS)

Sakamoto, Tatsuya; Iida, Tsutomu; Taguchi, Yutaka; Kurosaki, Shota; Hayatsu, Yusuke; Nishio, Keishi; Kogo, Yasuo; Takanashi, Yoshifumi

2012-06-01

We have fabricated an unconventional uni-leg structure thermoelectric generator (TEG) element using quad thermoelectric (TE) chips of Sb-doped n-Mg2Si, which were prepared by a plasma-activated sintering process. The power curve characteristics, the effect of aging up to 500 h, and the thermal gradients at several points on the module were investigated. The observed maximum output power with the heat source at 975 K and the heat sink at 345 K was 341 mW, from which the Δ T for the TE chip was calculated to be about 333 K. In aging testing in air ambient, a remarkable feature of the results was that there was no notable change from the initial resistance of the TEG module for as long as 500 h. The thermal distribution for the fabricated uni-leg TEG element was analyzed by finite-element modeling using ANSYS software. To tune the calculation parameters of ANSYS, such as the thermal conductance properties of the corresponding coupled materials in the module, precise measurements of the temperature at various probe points on the module were made. Then, meticulous verification between the measured temperature values and the results calculated by ANSYS was carried out to optimize the parameters.

Design of Simple Landslide Monitoring System

NASA Astrophysics Data System (ADS)

Meng, Qingjia; Cai, Lingling

2018-01-01

The simple landslide monitoring system is mainly designed for slope, collapse body and surface crack. In the harsh environment, the dynamic displacement data of the disaster body is transmitted to the terminal acquisition system in real time. The main body of the system adopt is PIC32MX795F512. This chip is to realize low power design, wakes the system up through the clock chip, and turns on the switching power supply at set time, which makes the wireless transmission module running during the interval to ensure the maximum battery consumption, so that the system can be stable long term work.

Design of a High-Speed and Compact Electro-Optic Modulator using Silicon-Germanium HBT

NASA Astrophysics Data System (ADS)

Neogi, Tuhin Guha

Optical interconnects between electronics systems have attracted significant attention and development for a number of years because optical links have demonstrated potential advantages for high-speed, low-power, and interference immunity. With increasing system speed and greater bandwidth requirements, the distance over which optical communication is useful has continually decreased to chip-to-chip and on-chip levels. Monolithic integration of photonics and electronics will significantly reduce the cost of optical components and further combine the functionalities of chips on the same or different boards or systems. Modulators are one of the fundamental building blocks for optical interconnects. High-speed modulation and low driving voltage are the keys for the device's practical use. In this study two separate designs show that using a graded base SiGe HBT we can modulate light at high speeds with moderate length and dynamic power consumption. The first design analyzes the terminal characteristics of the HBT and a close match is obtained in comparison with npn HBTs using IBM.s 8HP technology. This suggests that the modulator can be manufactured using the IBM 8HP fabrication process. At a sub-collector depth of 0.4 mum and at a base-emitter swing of 0 V to 1.1 V, this model predicts a bit rate of 80 Gbit/s. Optical simulations predict a pi phase shift length (Lpi) of 240.8 mum with an extinction ratio of 7.5 dB at a wavelength of 1.55 mum. Additionally, the trade-off between the switching speed, Lpi and propagation loss with a thinner sub-collector is analyzed and reported. The dynamic power consumption is reported to be 3.6 pJ /bit. The second design examine a theoretical aggressively-scaled SiGe HBT that may approximate a device that is two device generations more advanced than available today. At a base-emitter swing of 0 V to 1.0 V, this model predicts a bit rate of 250 Gbit/s. Optical simulations predict a pi phase shift length (Lpi) of 204 mum, with an extinction ratio of 13.2 dB at a wavelength of 1.55 mum. The dynamic power consumption is reported to be 2.01 pJ /bit. This study also discusses the design of driver circuitry at 80 Gbit/s with voltage swing levels of 1.03V. Finally the use of slow wave structures and use of SiGe HBT as a linear analog modulator is introduced.

Optical design of a street lamp based on dual-module chip-on-board LED arrays.

PubMed

Ge, Aiming; Cai, Jinlin; Chen, Dehua; Shu, Hongyun; Qiu, Peng; Wang, Junwei; Zhu, Ling

2014-09-01

We design and propose a compact street lamp based on dual-module chip-on-board LED. The street lamp is composed of six faceted reflectors. It can direct the luminous flux and form uniform illumination on the target area, and it effectively reduces power consumption. We have conducted both simulations and prototype measurements. The test results show good optical performance in that the uniformity of luminance reaches 0.58 for LED lamp zigzag arrangements and 0.60 for LED lamp double-side arrangements. The average luminance can fulfill the requirements in Chinese road lighting Standard CJJ45-2006.

Ultrasound neuro-modulation chip: activation of sensory neurons in Caenorhabditis elegans by surface acoustic waves.

PubMed

Zhou, Wei; Wang, Jingjing; Wang, Kaiyue; Huang, Bin; Niu, Lili; Li, Fei; Cai, Feiyan; Chen, Yan; Liu, Xin; Zhang, Xiaoyan; Cheng, Hankui; Kang, Lijun; Meng, Long; Zheng, Hairong

2017-05-16

Ultrasound neuro-modulation has gained increasing attention as a non-invasive method. In this paper, we present an ultrasound neuro-modulation chip, capable of initiating reversal behaviour and activating neurons of C. elegans under the stimulation of a single-shot, short-pulsed ultrasound. About 85.29% ± 6.17% of worms respond to the ultrasound stimulation exhibiting reversal behaviour. Furthermore, the worms can adapt to the ultrasound stimulation with a lower acoustic pulse duration of stimulation. In vivo calcium imaging shows that the activity of ASH, a polymodal sensory neuron in C. elegans, can be directly evoked by the ultrasound stimulation. On the other hand, AFD, a thermal sensitive neuron, cannot be activated by the ultrasound stimulation using the same parameter and the temperature elevation during the stimulation process is relatively small. Consistent with the calcium imaging results, the tax-4 mutants, which are insensitive to temperature increase, do not show a significant difference in avoidance probability compared to the wild type. Therefore, the mechanical effects induced by ultrasound are the main reason for neural and behavioural modulation of C. elegans. With the advantages of confined acoustic energy on the surface, compatible with standard calcium imaging, this neuro-modulation chip could be a powerful tool for revealing the molecular mechanisms of ultrasound neuro-modulation.

Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

NASA Astrophysics Data System (ADS)

Zhang, Liping; Sawchuk, Alexander A.

2001-12-01

We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

Tunable All-Solid-State Local Oscillators to 1900 GHz

NASA Technical Reports Server (NTRS)

Ward, John; Chattopadhyay, Goutam; Maestrini, Alain; Schlecht, Erich; Gill, John; Javadi, Hamid; Pukala, David; Maiwald, Frank; Mehdi, Imran

2004-01-01

We present a status report of an ongoing effort to develop robust tunable all-solid-state sources up to 1900 GHz for the Heterodyne Instrument for the Far Infrared (HIFI) on the Herschel Space Observatory. GaAs based multi-chip power amplifier modules at W-band are used to drive cascaded chains of multipliers. We have demonstrated performance from chains comprised of four doublers up to 1600 GHz as well as from a x2x3x3 chain to 1900 GHz. Measured peak output power of 23 (micro)W at 1782 GHz and 2.6 (micro)W at 1900 GHz has been achieved when the multipliers are cooled to 120K. The 1900 GHz tripler was pumped with a four anode tripler that produces a peak of 4 mW at 630 GHz when cooled to 120 K. We believe that these sources can now be used to pump hot electron bolometer (HEB) heterodyne mixers.ter (HEB) heterodyne mixers.

Design of a Closed-Loop, Bidirectional Brain Machine Interface System With Energy Efficient Neural Feature Extraction and PID Control.

PubMed

Liu, Xilin; Zhang, Milin; Richardson, Andrew G; Lucas, Timothy H; Van der Spiegel, Jan

2017-08-01

This paper presents a bidirectional brain machine interface (BMI) microsystem designed for closed-loop neuroscience research, especially experiments in freely behaving animals. The system-on-chip (SoC) consists of 16-channel neural recording front-ends, neural feature extraction units, 16-channel programmable neural stimulator back-ends, in-channel programmable closed-loop controllers, global analog-digital converters (ADC), and peripheral circuits. The proposed neural feature extraction units includes 1) an ultra low-power neural energy extraction unit enabling a 64-step natural logarithmic domain frequency tuning, and 2) a current-mode action potential (AP) detection unit with time-amplitude window discriminator. A programmable proportional-integral-derivative (PID) controller has been integrated in each channel enabling a various of closed-loop operations. The implemented ADCs include a 10-bit voltage-mode successive approximation register (SAR) ADC for the digitization of the neural feature outputs and/or local field potential (LFP) outputs, and an 8-bit current-mode SAR ADC for the digitization of the action potential outputs. The multi-mode stimulator can be programmed to perform monopolar or bipolar, symmetrical or asymmetrical charge balanced stimulation with a maximum current of 4 mA in an arbitrary channel configuration. The chip has been fabricated in 0.18 μ m CMOS technology, occupying a silicon area of 3.7 mm 2 . The chip dissipates 56 μW/ch on average. General purpose low-power microcontroller with Bluetooth module are integrated in the system to provide wireless link and SoC configuration. Methods, circuit techniques and system topology proposed in this work can be used in a wide range of relevant neurophysiology research, especially closed-loop BMI experiments.

Coherent Fiber Optic Links

DTIC Science & Technology

1990-12-01

since drift is common to both signal and local oscillator. However because of the Fabry - Perot cavity of the phase -6.9- Electrical delay 5.429077 ns___...Phase modulation gives intensity modulation of the guided light of .13dB max. This is due to formation of a Fabry - Perot cavity between the two fibre/chip...modulation sidebands using an optical spectrum analyser (scanning a Fabry - Perot interferometer), while monitoring the r.f. drive power incident on the

A Multi-Cycle Q-Modulation for Dynamic Optimization of Inductive Links.

PubMed

Lee, Byunghun; Yeon, Pyungwoo; Ghovanloo, Maysam

2016-08-01

This paper presents a new method, called multi-cycle Q-modulation, which can be used in wireless power transmission (WPT) to modulate the quality factor (Q) of the receiver (Rx) coil and dynamically optimize the load impedance to maximize the power transfer efficiency (PTE) in two-coil links. A key advantage of the proposed method is that it can be easily implemented using off-the-shelf components without requiring fast switching at or above the carrier frequency, which is more suitable for integrated circuit design. Moreover, the proposed technique does not need any sophisticated synchronization between the power carrier and Q-modulation switching pulses. The multi-cycle Q-modulation is analyzed theoretically by a lumped circuit model, and verified in simulation and measurement using an off-the-shelf prototype. Automatic resonance tuning (ART) in the Rx, combined with multi-cycle Q-modulation helped maximizing PTE of the inductive link dynamically in the presence of environmental and loading variations, which can otherwise significantly degrade the PTE in multi-coil settings. In the prototype conventional 2-coil link, the proposed method increased the power amplifier (PA) plus inductive link efficiency from 4.8% to 16.5% at ( R L = 1 kΩ, d 23 = 3 cm), and from 23% to 28.2% at ( R L = 100 Ω, d 23 = 3 cm) after 11% change in the resonance capacitance, while delivering 168.1 mW to the load (PDL).

A reconfigurable multicarrier demodulator architecture

NASA Technical Reports Server (NTRS)

Kwatra, S. C.; Jamali, M. M.

1991-01-01

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference.

Consortia for Known Good Die (KGD), phase 1

NASA Astrophysics Data System (ADS)

Andrews, Marshall; Carey, David; Fellows, Mary M.; Gilg, Larry; Murphy, Cindy; Noddings, Chad; Pitts, Greg; Rathmell, Claude; Spooner, Charles

1994-02-01

This report describes the results of Phase 1 of the Infrastructure for KGD program at MCC. The objective of the work is to resolve the issues for supplying and procuring Known Good Die (KGD) in a way that fosters industry acceptance and confidence in Application Specific Electronic Modules (ASEM's for military systems) and MultiChip Modules (MCM's for commercial systems). This report is divided into four sections. Section 1 describes the technical assessment of proposed industry approaches to KGD implementation. Section 2 of the report contains an outline for the plan for industry and government cooperation for the demonstration, validation, and implementation of KGD methodologies identified in this Phase 1 study. Section 3 of the report contains the industry-generated requirements for KGD implementation. Section IV of the report contains the KGD specifications for TAB and flip chip IC's.

NASA Tech Briefs, February 2007

NASA Technical Reports Server (NTRS)

2007-01-01

Topics covered include: Calibration Test Set for a Phase-Comparison Digital Tracker; Wireless Acoustic Measurement System; Spiral Orbit Tribometer; Arrays of Miniature Microphones for Aeroacoustic Testing; Predicting Rocket or Jet Noise in Real Time; Computational Workbench for Multibody Dynamics; High-Power, High-Efficiency Ka-Band Space Traveling-Wave Tube; Gratings and Random Reflectors for Near-Infrared PIN Diodes; Optically Transparent Split-Ring Antennas for 1 to 10 GHz; Ice-Penetrating Robot for Scientific Exploration; Power-Amplifier Module for 145 to 165 GHz; Aerial Videography From Locally Launched Rockets; SiC Multi-Chip Power Modules as Power-System Building Blocks; Automated Design of Restraint Layer of an Inflatable Vessel; TMS for Instantiating a Knowledge Base With Incomplete Data; Simulating Flights of Future Launch Vehicles and Spacecraft; Control Code for Bearingless Switched- Reluctance Motor; Machine Aided Indexing and the NASA Thesaurus; Arbitrating Control of Control and Display Units; Web-Based Software for Managing Research; Driver Code for Adaptive Optics; Ceramic Paste for Patching High-Temperature Insulation; Fabrication of Polyimide-Matrix/Carbon and Boron-Fiber Tape; Protective Skins for Aerogel Monoliths; Code Assesses Risks Posed by Meteoroids and Orbital Debris; Asymmetric Bulkheads for Cylindrical Pressure Vessels; Self-Regulating Water-Separator System for Fuel Cells; Self-Advancing Step-Tap Drills; Array of Bolometers for Submillimeter- Wavelength Operation; Delta-Doped CCDs as Detector Arrays in Mass Spectrometers; Arrays of Bundles of Carbon Nanotubes as Field Emitters; Staggering Inflation To Stabilize Attitude of a Solar Sail; and Bare Conductive Tether for Decelerating a Spacecraft.

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

NASA Astrophysics Data System (ADS)

Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

2018-04-01

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Comparison of performance of high-power mid-IR QCL modules in actively and passively cooled mode

NASA Astrophysics Data System (ADS)

Münzhuber, F.; Denzel, H.; Tholl, H. D.

2017-10-01

We report on the effects of active and passive cooling on the performance of high power mid-IR QCL modules (λ ≈ 3.9 μm) in quasi-cw mode. In active cooling mode, a thermo-electrical cooler attached with its hot side to a heat sink of constant temperature, a local thermometer in close proximity to the QCL chip (epi-down mounted) as well as a control unit has been used for temperature control of the QCL submount. In contrast, the passive cooling was performed by attaching the QCL module solely to the heat sink. Electro-optical light-current- (L-I-) curves are measured in a quasi-cw mode, from which efficiencies can be deduced. Waiving of the active cooling elements results in a drop of the maximum intensity of less than 5 %, compared to the case wherein the temperature of the submount is stabilized to the temperature of the heat sink. The application of a model of electro-optical performance to the data shows good agreement and captures the relevant observations. We further determine the heat resistance of the module and demonstrate that the system performance is not limited by the packaging of the module, but rather by the heat dissipation on the QCL chip itself.

Multi-dimensional spatial light communication made with on-chip InGaN photonic integration

NASA Astrophysics Data System (ADS)

Yang, Yongchao; Zhu, Bingcheng; Shi, Zheng; Wang, Jinyuan; Li, Xin; Gao, Xumin; Yuan, Jialei; Li, Yuanhang; Jiang, Yan; Wang, Yongjin

2017-04-01

Here, we propose, fabricate and characterize suspended photonic integration of InGaN multiple-quantum-well light-emitting diode (MQW-LED), waveguide and InGaN MQW-photodetector on a single chip. The unique light emission property of InGaN MQW-LED makes it feasible to establish multi-dimensional spatial data transmission using visible light. The in-plane light communication system is comprised of InGaN MQW-LED, waveguide and InGaN MQW-photodetector, and the out-of-plane data transmission is realized by detecting the free-space light emission via a commercial photodiode module. Moreover, a full-duplex light communication is experimentally demonstrated at a data transmission rate of 50 Mbps when both InGaN MQW-diodes operate under simultaneous light emission and detection mode. The in-plane superimposed signals are able to be extracted through the self-interference cancellation method, and the out-of-plane superimposed signals are in good agreement with the calculated signals according to the extracted transmitted signals. These results are promising for the development of on-chip InGaN photonic integration for diverse applications.

High density, multi-range analog output Versa Module Europa board for control system applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, Kundan, E-mail: kundan@iuac.res.in; Das, Ajit Lal

2014-01-15

A new VMEDAC64, 12-bit 64 channel digital-to-analog converter, a Versa Module Europa (VME) module, features 64 analog voltage outputs with user selectable multiple ranges, has been developed for control system applications at Inter University Accelerator Centre. The FPGA (Field Programmable Gate Array) is the module's core, i.e., it implements the DAC control logic and complexity of VMEbus slave interface logic. The VMEbus slave interface and DAC control logic are completely designed and implemented on a single FPGA chip to achieve high density of 64 channels in a single width VME module and will reduce the module count in the controlmore » system applications, and hence will reduce the power consumption and cost of overall system. One of our early design goals was to develop the VME interface such that it can be easily integrated with the peripheral devices and satisfy the timing specifications of VME standard. The modular design of this module reduces the amount of time required to develop other custom modules for control system. The VME slave interface is written as a single component inside FPGA which will be used as a basic building block for any VMEbus interface project. The module offers multiple output voltage ranges depending upon the requirement. The output voltage range can be reduced or expanded by writing range selection bits in the control register. The module has programmable refresh rate and by default hold capacitors in the sample and hold circuit for each channel are charged periodically every 7.040 ms (i.e., update frequency 284 Hz). Each channel has software controlled output switch which disconnects analog output from the field. The modularity in the firmware design on FPGA makes the debugging very easy. On-board DC/DC converters are incorporated for isolated power supply for the analog section of the board.« less

Design of resolution/power controllable Asynchronous Sigma-Delta Modulator

NASA Astrophysics Data System (ADS)

Deshmukh, Anita Arvind; Deshmukh, Raghvendra B.

2016-12-01

This paper presents the design of a Programmable Asynchronous Modulator (PAM) with field control of resolution and power. A novel variable hysteresis Schmitt Trigger (ST) is used for external programmability. Asynchronous Sigma-Delta Modulator (ASDM) implementation with external control voltages is proposed to supervise the resolution and power. This architecture with reduced circuit complexity considerably improves the earlier realizations by eliminating multiple current sources as well switched capacitor circuits and results in power saving up to 87 %. Proposed PAM design demonstrates an improved SNDR of 115 dB, DR of 96 dB, and power consumption below 280 μW. It illustrates Effective Number of Bits (ENOB) to 18.81 and Figure of Merit (FoM) to 0.15 fJ/conversion step. Modulator is implemented in Cadence UMC Hspice 0.18 μm CMOS analog technology. Off-chip PAM control for resolution/power performance has potential applications in battery operated ultra low power applications like IoT; where ADC is one of the major power consuming components. It offers the promise for an efficient performance with power saving.

Development and fabrication of S-band chip varactor parametric amplifier

NASA Technical Reports Server (NTRS)

Kramer, E.

1974-01-01

A noncryogenic, S-band parametric amplifier operating in the 2.2 to 2.3 GHz band and having an average input noise temperature of less than 30 K was built and tested. The parametric amplifier module occupies a volume of less than 1-1/4 cubic feet and weighs less than 60 pounds. The module is designed for use in various NASA ground stations to replace larger, more complex cryogenic units which require considerably more maintenance because of the cryogenic refrigeration system employed. The amplifier can be located up to 15 feet from the power supply unit. Optimum performance was achieved through the use of high-quality unpackaged (chip) varactors in the amplifier design.

FInal Technical Repot of the Project: Design and Implementation of Low-Power 10Gb/s/channel Laser/Silicon Photonics Modulator Drivers with SEU Tolerance for HL-LHC

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gui, Ping

During the funding period of this award from May 1, 2014 through March 30, 2016, we have accomplished the design, implementation and measurement results of two laser driver chips: LpGBLD10+ which is a low-power single-channel 10Gb/s laser driver IC, and LDQ10P, which is a 4x10Gb/s driver array chip for High Energy Physics (HEP) applications. With new circuit techniques, the driver consumes a record-low power consumption, 31 mW @10Gb/s/channel and occupies a small area of 400 µm × 1750 µm for the single-channel driver IC and 1900umx1700um for the LDQ10P chip. These characteristics allow for both the LpGBLD10+ ICs and LDQ10P suitable candidatemore » for the Versatile Link PLUS (VL+) project, offering flexibility in configuring multiple Transmitters and receivers.« less

Few-fJ/bit data transmissions using directly modulated lambda-scale embedded active region photonic-crystal lasers

NASA Astrophysics Data System (ADS)

Takeda, Koji; Sato, Tomonari; Shinya, Akihiko; Nozaki, Kengo; Kobayashi, Wataru; Taniyama, Hideaki; Notomi, Masaya; Hasebe, Koichi; Kakitsuka, Takaaki; Matsuo, Shinji

2013-07-01

A low operating energy is needed for nanocavity lasers designed for on-chip photonic network applications. On-chip nanocavity lasers must be driven by current because they act as light sources driven by electronic circuits. Here, we report the high-speed direct modulation of a lambda-scale embedded active region photonic-crystal (LEAP) laser that holds three records for any type of laser operated at room temperature: a low threshold current of 4.8 µA, a modulation current efficiency of 2.0 GHz µA-0.5 and an operating energy of 4.4 fJ bit-1. Five major technologies make this performance possible: a compact buried heterostructure, a photonic-crystal nanocavity, a lateral p-n junction realized by ion implantation and thermal diffusion, an InAlAs sacrificial layer and current-blocking trenches. We believe that an output power of 2.17 µW and an operating energy of 4.4 fJ bit-1 will enable us to realize on-chip photonic networks in combination with the recently developed highly sensitive receivers.

Diode lasers optimized in brightness for fiber laser pumping

NASA Astrophysics Data System (ADS)

Kelemen, M.; Gilly, J.; Friedmann, P.; Hilzensauer, S.; Ogrodowski, L.; Kissel, H.; Biesenbach, J.

2018-02-01

In diode laser applications for fiber laser pumping and fiber-coupled direct diode laser systems high brightness becomes essential in the last years. Fiber coupled modules benefit from continuous improvements of high-power diode lasers on chip level regarding output power, efficiency and beam characteristics resulting in record highbrightness values and increased pump power. To gain high brightness not only output power must be increased, but also near field widths and far field angles have to be below a certain value for higher power levels because brightness is proportional to output power divided by beam quality. While fast axis far fields typically show a current independent behaviour, for broadarea lasers far-fields in the slow axis suffer from a strong current and temperature dependence, limiting the brightness and therefore their use in fibre coupled modules. These limitations can be overcome by carefully optimizing chip temperature, thermal lensing and lateral mode structure by epitaxial and lateral resonator designs and processing. We present our latest results for InGaAs/AlGaAs broad-area single emitters with resonator lengths of 4mm emitting at 976nm and illustrate the improvements in beam quality over the last years. By optimizing the diode laser design a record value of the brightness for broad-area lasers with 4mm resonator length of 126 MW/cm2sr has been demonstrated with a maximum wall-plug efficiency of more than 70%. From these design also pump modules based on 9 mini-bars consisting of 5 emitters each have been realized with 360W pump power.

An Attachable Electromagnetic Energy Harvester Driven Wireless Sensing System Demonstrating Milling-Processes and Cutter-Wear/Breakage-Condition Monitoring.

PubMed

Chung, Tien-Kan; Yeh, Po-Chen; Lee, Hao; Lin, Cheng-Mao; Tseng, Chia-Yung; Lo, Wen-Tuan; Wang, Chieh-Min; Wang, Wen-Chin; Tu, Chi-Jen; Tasi, Pei-Yuan; Chang, Jui-Wen

2016-02-23

An attachable electromagnetic-energy-harvester driven wireless vibration-sensing system for monitoring milling-processes and cutter-wear/breakage-conditions is demonstrated. The system includes an electromagnetic energy harvester, three single-axis Micro Electro-Mechanical Systems (MEMS) accelerometers, a wireless chip module, and corresponding circuits. The harvester consisting of magnets with a coil uses electromagnetic induction to harness mechanical energy produced by the rotating spindle in milling processes and consequently convert the harnessed energy to electrical output. The electrical output is rectified by the rectification circuit to power the accelerometers and wireless chip module. The harvester, circuits, accelerometer, and wireless chip are integrated as an energy-harvester driven wireless vibration-sensing system. Therefore, this completes a self-powered wireless vibration sensing system. For system testing, a numerical-controlled machining tool with various milling processes is used. According to the test results, the system is fully self-powered and able to successfully sense vibration in the milling processes. Furthermore, by analyzing the vibration signals (i.e., through analyzing the electrical outputs of the accelerometers), criteria are successfully established for the system for real-time accurate simulations of the milling-processes and cutter-conditions (such as cutter-wear conditions and cutter-breaking occurrence). Due to these results, our approach can be applied to most milling and other machining machines in factories to realize more smart machining technologies.

An Attachable Electromagnetic Energy Harvester Driven Wireless Sensing System Demonstrating Milling-Processes and Cutter-Wear/Breakage-Condition Monitoring

PubMed Central

Chung, Tien-Kan; Yeh, Po-Chen; Lee, Hao; Lin, Cheng-Mao; Tseng, Chia-Yung; Lo, Wen-Tuan; Wang, Chieh-Min; Wang, Wen-Chin; Tu, Chi-Jen; Tasi, Pei-Yuan; Chang, Jui-Wen

2016-01-01

An attachable electromagnetic-energy-harvester driven wireless vibration-sensing system for monitoring milling-processes and cutter-wear/breakage-conditions is demonstrated. The system includes an electromagnetic energy harvester, three single-axis Micro Electro-Mechanical Systems (MEMS) accelerometers, a wireless chip module, and corresponding circuits. The harvester consisting of magnets with a coil uses electromagnetic induction to harness mechanical energy produced by the rotating spindle in milling processes and consequently convert the harnessed energy to electrical output. The electrical output is rectified by the rectification circuit to power the accelerometers and wireless chip module. The harvester, circuits, accelerometer, and wireless chip are integrated as an energy-harvester driven wireless vibration-sensing system. Therefore, this completes a self-powered wireless vibration sensing system. For system testing, a numerical-controlled machining tool with various milling processes is used. According to the test results, the system is fully self-powered and able to successfully sense vibration in the milling processes. Furthermore, by analyzing the vibration signals (i.e., through analyzing the electrical outputs of the accelerometers), criteria are successfully established for the system for real-time accurate simulations of the milling-processes and cutter-conditions (such as cutter-wear conditions and cutter-breaking occurrence). Due to these results, our approach can be applied to most milling and other machining machines in factories to realize more smart machining technologies. PMID:26907297

Scalable InP integrated wavelength selector based on binary search.

PubMed

Calabretta, Nicola; Stabile, Ripalta; Albores-Mejia, Aaron; Williams, Kevin A; Dorren, Harm J S

2011-10-01

We present an InP monolithically integrated wavelength selector that implements a binary search for selecting one from N modulated wavelengths. The InP chip requires only log(2)N optical filters and log(2)N optical switches. Experimental results show nanosecond reconfiguration and error-free wavelength selection of four modulated wavelengths with 2 dB of power penalty. © 2011 Optical Society of America

Single-chip fully integrated direct-modulation CMOS RF transmitters for short-range wireless applications.

PubMed

El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed; Deen, M Jamal

2013-08-02

Ultra-low power radio frequency (RF) transceivers used in short-range application such as wireless sensor networks (WSNs) require efficient, reliable and fully integrated transmitter architectures with minimal building blocks. This paper presents the design, implementation and performance evaluation of single-chip, fully integrated 2.4 GHz and 433 MHz RF transmitters using direct-modulation power voltage-controlled oscillators (PVCOs) in addition to a 2.0 GHz phase-locked loop (PLL) based transmitter. All three RF transmitters have been fabricated in a standard mixed-signal CMOS 0.18 µm technology. Measurement results of the 2.4 GHz transmitter show an improvement in drain efficiency from 27% to 36%. The 2.4 GHz and 433 MHz transmitters deliver an output power of 8 dBm with a phase noise of -122 dBc/Hz at 1 MHz offset, while drawing 15.4 mA of current and an output power of 6.5 dBm with a phase noise of -120 dBc/Hz at 1 MHz offset, while drawing 20.8 mA of current from 1.5 V power supplies, respectively. The PLL transmitter delivers an output power of 9 mW with a locking range of 128 MHz and consumes 26 mA from 1.8 V power supply. The experimental results demonstrate that the RF transmitters can be efficiently used in low power WSN applications.

ChIP-re-ChIP: Co-occupancy Analysis by Sequential Chromatin Immunoprecipitation.

PubMed

Beischlag, Timothy V; Prefontaine, Gratien G; Hankinson, Oliver

2018-01-01

Chromatin immunoprecipitation (ChIP) exploits the specific interactions between DNA and DNA-associated proteins. It can be used to examine a wide range of experimental parameters. A number of proteins bound at the same genomic location can identify a multi-protein chromatin complex where several proteins work together to regulate gene transcription or chromatin configuration. In many instances, this can be achieved using sequential ChIP; or simply, ChIP-re-ChIP. Whether it is for the examination of specific transcriptional or epigenetic regulators, or for the identification of cistromes, the ability to perform a sequential ChIP adds a higher level of power and definition to these analyses. In this chapter, we describe a simple and reliable method for the sequential ChIP assay.

Integrated microsystems packaging approach with LCP

NASA Astrophysics Data System (ADS)

Jaynes, Paul; Shacklette, Lawrence W.

2006-05-01

Within the government communication market there is an increasing push to further miniaturize systems with the use of chip-scale packages, flip-chip bonding, and other advances over traditional packaging techniques. Harris' approach to miniaturization includes these traditional packaging advances, but goes beyond this level of miniaturization by combining the functional and structural elements of a system, thus creating a Multi-Functional Structural Circuit (MFSC). An emerging high-frequency, near hermetic, thermoplastic electronic substrate material, Liquid Crystal Polymer (LCP), is the material that will enable the combination of the electronic circuit and the physical structure of the system. The first embodiment of this vision for Harris is the development of a battlefield acoustic sensor module. This paper will introduce LCP and its advantages for MFSC, present an example of the work that Harris has performed, and speak to LCP MFSCs' potential benefits to miniature communications modules and sensor platforms.

Performance Comparison of 112-Gb/s DMT, Nyquist PAM4, and Partial-Response PAM4 for Future 5G Ethernet-Based Fronthaul Architecture

NASA Astrophysics Data System (ADS)

Eiselt, Nicklas; Muench, Daniel; Dochhan, Annika; Griesser, Helmut; Eiselt, Michael; Olmos, Juan Jose Vegas; Monroy, Idelfonso Tafur; Elbers, Joerg-Peter

2018-05-01

For a future 5G Ethernet-based fronthaul architecture, 100G trunk lines of a transmission distance up to 10 km standard single mode fiber (SSMF) in combination with cheap grey optics to daisy chain cell site network interfaces are a promising cost- and power-efficient solution. For such a scenario, different intensity modulation and direct detect (IMDD) Formats at a data rate of 112 Gb/s, namely Nyquist four-level pulse amplitude modulation (PAM4), discrete multi-tone Transmission (DMT) and partial-response (PR) PAM4 are experimentally investigated, using a low-cost electro-absorption modulated laser (EML), a 25G driver and current state-of-the-art high Speed 84 GS/s CMOS digital-to-analog converter (DAC) and analog-to-digital converter (ADC) test chips. Each modulation Format is optimized independently for the desired scenario and their digital signal processing (DSP) requirements are investigated. The performance of Nyquist PAM4 and PR PAM4 depend very much on the efficiency of pre- and post-equalization. We show the necessity for at least 11 FFE-taps for pre-emphasis and up to 41 FFE coefficients at the receiver side. In addition, PR PAM4 requires an MLSE with four states to decode the signal back to a PAM4 signal. On the contrary, bit- and power-loading (BL, PL) is crucial for DMT and an FFT length of at least 512 is necessary. With optimized parameters, all Modulation formats result in a very similar performances, demonstrating a transmission distance of up to 10 km over SSMF with bit error rates (BERs) below a FEC threshold of 4.4E-3, allowing error free transmission.

Nanoparticle embedded p-type electrodes for GaN-based flip-chip light emitting diodes.

PubMed

Kwak, Joon Seop; Song, J O; Seong, T Y; Kim, B I; Cho, J; Sone, C; Park, Y

2006-11-01

We have investigated high-quality ohmic contacts for flip-chip light emitting diodes using Zn-Ni nanoparticles/Ag schemes. The Zn-Ni nanoparticles/Ag contacts produce specific contact resistances of 10(-5)-10(-6) omegacm2 when annealed at temperatures of 330-530 degrees C for 1 min in air ambient, which are much better than those obtained from the Ag contacts. It is shown that blue InGaN/GaN multi-quantum well light emitting diodes fabricated with the annealed Zn-Ni nanoparticles/Ag contacts give much lower forward-bias voltages at 20 mA compared with those of the multi-quantum well light emitting diodes made with the as-deposited Ag contacts. It is further presented that the multi-quantum well light emitting diodes made with the Zn-Ni nanoparticles/Ag contacts show similar output power compared to those fabricated with the Ag contact layers.

Lower-Order Compensation Chain Threshold-Reduction Technique for Multi-Stage Voltage Multipliers.

PubMed

Dell' Anna, Francesco; Dong, Tao; Li, Ping; Wen, Yumei; Azadmehr, Mehdi; Casu, Mario; Berg, Yngvar

2018-04-17

This paper presents a novel threshold-compensation technique for multi-stage voltage multipliers employed in low power applications such as passive and autonomous wireless sensing nodes (WSNs) powered by energy harvesters. The proposed threshold-reduction technique enables a topological design methodology which, through an optimum control of the trade-off among transistor conductivity and leakage losses, is aimed at maximizing the voltage conversion efficiency (VCE) for a given ac input signal and physical chip area occupation. The conducted simulations positively assert the validity of the proposed design methodology, emphasizing the exploitable design space yielded by the transistor connection scheme in the voltage multiplier chain. An experimental validation and comparison of threshold-compensation techniques was performed, adopting 2N5247 N-channel junction field effect transistors (JFETs) for the realization of the voltage multiplier prototypes. The attained measurements clearly support the effectiveness of the proposed threshold-reduction approach, which can significantly reduce the chip area occupation for a given target output performance and ac input signal.

Integrated circuit for SAW and MEMS sensors

NASA Astrophysics Data System (ADS)

Fischer, Wolf-Joachim; Koenig, Peter; Ploetner, Matthias; Hermann, Rudiger; Stab, Helmut

2001-11-01

The sensor processor circuit has been developed for hand-held devices used in industrial and environmental applications, such as on-line process monitoring. Thereby devices with SAW sensors or MEMS resonators will benefit from this processor especially. Up to 8 sensors can be connected to the circuit as multisensors or sensor arrays. Two sensor processors SP1 and SP2 for different applications are presented in this paper. The SP-1 chip has a PCMCIA interface which can be used for the program and data transfer. SAW sensors which are working in the frequency range from 80 MHz to 160 MHz can be connected to the processor directly. It is possible to use the new SP-2 chip fabricated in a 0.5(mu) CMOS process for SAW devices with a maximum frequency of 600 MHz. An on-chip analog-digital-converter (ADC) and 6 PWM modules support the development of high-miniaturized intelligent sensor systems We have developed a multi-SAW sensor system with this ASIC that manages the requirements on control as well as signal generation and storage and provides an interface to the PC and electronic devices on the board. Its low power consumption and its PCMCIA plug fulfil the requirements of small size and mobility. For this application sensors have been developed to detect hazardous gases in ambient air. Sensors with differently modified copper-phthalocyanine films are capable of detecting NO2 and O3, whereas those with a hyperbranched polyester film respond to NH3.

Bubble memory module

NASA Technical Reports Server (NTRS)

Bohning, O. D.; Becker, F. J.

1980-01-01

Design, fabrication and test of partially populated prototype recorder using 100 kilobit serial chips is described. Electrical interface, operating modes, and mechanical design of several module configurations are discussed. Fabrication and test of the module demonstrated the practicality of multiplexing resulting in lower power, weight, and volume. This effort resulted in the completion of a module consisting of a fully engineered printed circuit storage board populated with 5 of 8 possible cells and a wire wrapped electronics board. Interface of the module is 16 bits parallel at a maximum of 1.33 megabits per second data rate on either of two interface buses.

Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

NASA Technical Reports Server (NTRS)

Elbuluk, Malik E.; Gerber, Scott; Hammoud, Ahmad; Patterson, Richard; Overton, Eric

2001-01-01

The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

Reliability study of high-brightness multiple single emitter diode lasers

NASA Astrophysics Data System (ADS)

Zhu, Jing; Yang, Thomas; Zhang, Cuipeng; Lang, Chao; Jiang, Xiaochen; Liu, Rui; Gao, Yanyan; Guo, Weirong; Jiang, Yuhua; Liu, Yang; Zhang, Luyan; Chen, Louisa

2015-03-01

In this study the chip bonding processes for various chips from various chip suppliers around the world have been optimized to achieve reliable chip on sub-mount for high performance. These chip on sub-mounts, for examples, includes three types of bonding, 8xx nm-1.2W/10.0W Indium bonded lasers, 9xx nm 10W-20W AuSn bonded lasers and 1470 nm 6W Indium bonded lasers will be reported below. The MTTF@25 of 9xx nm chip on sub-mount (COS) is calculated to be more than 203,896 hours. These chips from various chip suppliers are packaged into many multiple single emitter laser modules, using similar packaging techniques from 2 emitters per module to up to 7 emitters per module. A reliability study including aging test is performed on those multiple single emitter laser modules. With research team's 12 years' experienced packaging design and techniques, precise optical and fiber alignment processes and superior chip bonding capability, we have achieved a total MTTF exceeding 177,710 hours of life time with 60% confidence level for those multiple single emitter laser modules. Furthermore, a separated reliability study on wavelength stabilized laser modules have shown this wavelength stabilized module packaging process is reliable as well.

Integrated power passives

NASA Technical Reports Server (NTRS)

Xie, Huikai (Inventor); Ngo, Khai D. T. (Inventor)

2013-01-01

A multi-layer film-stack and method for forming the multilayer film-stack is given where a series of alternating layers of conducting and dielectric materials are deposited such that the conducting layers can be selectively addressed. The use of the method to form integratable high capacitance density capacitors and complete the formation of an integrated power system-on-a-chip device including transistors, conductors, inductors, and capacitors is also given.

Broadband Sources in the 1-3 THz Range

NASA Technical Reports Server (NTRS)

Mehdi, Imran; Ward, John; Maestrini, Alain; Chattopadhyay, Goutam; Schlecht, Erich; Thomas, Bertrand; Lin, Robert; Lee, Choonsup; Gill, John

2009-01-01

Broadband electronically tunable sources in the terahertz range are a critical technology for enabling space-borne as well as ground-based applications. By power-combining MMIC amplifier and frequency tripler chips, we have recently demonstrated >1 mW of output power at 900 GHz. This source provides a stepping stone to enable sources in the 2-3 THz range than can sufficiently pump multi-pixel imaging arrays.

High-Temperature, Wirebondless, Ultracompact Wide Bandgap Power Semiconductor Modules

NASA Technical Reports Server (NTRS)

Elmes, John

2015-01-01

Silicon carbide (SiC) and other wide bandgap semiconductors offer great promise of high power rating, high operating temperature, simple thermal management, and ultrahigh power density for both space and commercial power electronic systems. However, this great potential is seriously limited by the lack of reliable high-temperature device packaging technology. This Phase II project developed an ultracompact hybrid power module packaging technology based on the use of double lead frames and direct lead frame-to-chip transient liquid phase (TLP) bonding that allows device operation up to 450 degC. The new power module will have a very small form factor with 3-5X reduction in size and weight from the prior art, and it will be capable of operating from 450 degC to -125 degC. This technology will have a profound impact on power electronics and energy conversion technologies and help to conserve energy and the environment as well as reduce the nation's dependence on fossil fuels.

Wireless Low-Power Integrated Basal-Body-Temperature Detection Systems Using Teeth Antennas in the MedRadio Band.

PubMed

Yang, Chin-Lung; Zheng, Gou-Tsun

2015-11-20

This study proposes using wireless low power thermal sensors for basal-body-temperature detection using frequency modulated telemetry devices. A long-term monitoring sensor requires low-power circuits including a sampling circuit and oscillator. Moreover, temperature compensated technologies are necessary because the modulated frequency might have additional frequency deviations caused by the varying temperature. The temperature compensated oscillator is composed of a ring oscillator and a controlled-steering current source with temperature compensation, so the output frequency of the oscillator does not drift with temperature variations. The chip is fabricated in a standard Taiwan Semiconductor Manufacturing Company (TSMC) 0.18-μm complementary metal oxide semiconductor (CMOS) process, and the chip area is 0.9 mm². The power consumption of the sampling amplifier is 128 µW. The power consumption of the voltage controlled oscillator (VCO) core is less than 40 µW, and the output is -3.04 dBm with a buffer stage. The output voltage of the bandgap reference circuit is 1 V. For temperature measurements, the maximum error is 0.18 °C with a standard deviation of ±0.061 °C, which is superior to the required specification of 0.1 °C.

Novel multi-telescopes beam combiners for next generation instruments (FIRST/SUBARU)

NASA Astrophysics Data System (ADS)

Martin, G.; Pugnat, T.; Gardillou, F.; Cassagnettes, C.; Barbier, D.; Guyot, C.; Hauden, J.; Huby, E.; Lacour, S.

2016-07-01

Integrated optic devices are nowadays achieving extremely good performances in the field of astronomical interferometry, as shown by PIONIER or GRAVITY silica/silicon-based instruments, already installed at VLTI. In order to address other wavelengths, increase the number of apertures to be combined and eventually ensure on-chip phase modulation, we are working on a novel generation of beam combiners, based on the hybridization of glass waveguides, that can ensure very sharp bend radius, high confinement and low propagation losses, together with lithium niobate phase modulators and channel waveguides that can achieve on-chip, fast (<100kHz) phase modulation. The work presented here has been realized in collaboration with our technological partners TeemPhotonics for glass waveguides and iXBlue-PSD for lithium niobate phase modulators. We will present our results on a hybrid glass/niobate (passive/active) beam combiner that has been developed in the context of FIRST/SUBARU 9T beam combiner. The combiner is structured in three parts: a) the first stage (passive glass) achieves beam splitting from one input to eight outputs, and that for nine input fibers coming from the sub-apertures of the Subaru telescope; b) the second stage consists on a 72 channel waveguides lithium niobate phase modulator in a push-pull configuration that allows to modify on-chip the relative phase between the 36 pairs of waveguides; c) a final recombination system of Y-junctions (passive glass) that allows to obtain combination of each input to every other one. The aim of this presentation is to discuss different issues of the combiners, such as transmission, birefringence, half-wave voltage modulation and spectral range.

Active C4 Electrodes for Local Field Potential Recording Applications

PubMed Central

Wang, Lu; Freedman, David; Sahin, Mesut; Ünlü, M. Selim; Knepper, Ronald

2016-01-01

Extracellular neural recording, with multi-electrode arrays (MEAs), is a powerful method used to study neural function at the network level. However, in a high density array, it can be costly and time consuming to integrate the active circuit with the expensive electrodes. In this paper, we present a 4 mm × 4 mm neural recording integrated circuit (IC) chip, utilizing IBM C4 bumps as recording electrodes, which enable a seamless active chip and electrode integration. The IC chip was designed and fabricated in a 0.13 μm BiCMOS process for both in vitro and in vivo applications. It has an input-referred noise of 4.6 μVrms for the bandwidth of 10 Hz to 10 kHz and a power dissipation of 11.25 mW at 2.5 V, or 43.9 μW per input channel. This prototype is scalable for implementing larger number and higher density electrode arrays. To validate the functionality of the chip, electrical testing results and acute in vivo recordings from a rat barrel cortex are presented. PMID:26861324

Improved light extraction efficiency of InGaN-based multi-quantum well light emitting diodes by using a single die growth.

PubMed

Park, Min Joo; Kwon, K W; Kim, Y H; Park, S H; Kwak, Joon Seop

2011-05-01

We have demonstrated that the light extraction efficiency of the InGaN based multi-quantum well light-emitting diodes (LEDs) can be improved by using a single die growth (SDG) method. The SDG was performed by patterning the n-GaN and sapphire substrate with a size of single chip (600 x 250 microm2) by using a laser scriber, followed by the regrowth of the n-GaN and LED structures on the laser patterned n-GaN. We fabricated lateral LED chips having the SDG structures (SDG-LEDs), in which the thickness of the regrown n-GaN was varied from 2 to 6 microm. For comparison, we also fabricated conventional LED chips without the SDG structures. The SDG-LEDs showed lower operating voltage when compared to the conventional LEDs. In addition, the output power of the SDG-LEDs was significantly higher than that of the conventional LEDs. From optical ray tracing simulations, the increase in the thickness and sidewall angle of the regrown n-GaN and LED structures may enhance photon escapes from the tilted facets of the regrown n-GaN, followed by the increase in light output power and extraction efficiency of the SDG-LEDs.

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

III-nitride integration on ferroelectric materials of lithium niobate by molecular beam epitaxy

NASA Astrophysics Data System (ADS)

Namkoong, Gon; Lee, Kyoung-Keun; Madison, Shannon M.; Henderson, Walter; Ralph, Stephen E.; Doolittle, W. Alan

2005-10-01

Integration of III-nitride electrical devices on the ferroelectric material lithium niobate (LiNbO3) has been demonstrated. As a ferroelectric material, lithium niobate has a polarization which may provide excellent control of the polarity of III-nitrides. However, while high temperature, 1000°C, thermal treatments produce atomically smooth surfaces, improving adhesion of GaN epitaxial layers on lithium niobate, repolarization of the substrate in local domains occurs. These effects result in multi domains of mixed polarization in LiNbO3, producing inversion domains in subsequent GaN epilayers. However, it is found that AlN buffer layers suppress inversion domains of III-nitrides. Therefore, two-dimensional electron gases in AlGaN /GaN heterojunction structures are obtained. Herein, the demonstration of the monolithic integration of high power devices with ferroelectric materials presents possibilities to control LiNbO3 modulators on compact optoelectronic/electronic chips.

An accuracy aware low power wireless EEG unit with information content based adaptive data compression.

PubMed

Tolbert, Jeremy R; Kabali, Pratik; Brar, Simeranjit; Mukhopadhyay, Saibal

2009-01-01

We present a digital system for adaptive data compression for low power wireless transmission of Electroencephalography (EEG) data. The proposed system acts as a base-band processor between the EEG analog-to-digital front-end and RF transceiver. It performs a real-time accuracy energy trade-off for multi-channel EEG signal transmission by controlling the volume of transmitted data. We propose a multi-core digital signal processor for on-chip processing of EEG signals, to detect signal information of each channel and perform real-time adaptive compression. Our analysis shows that the proposed approach can provide significant savings in transmitter power with minimal impact on the overall signal accuracy.

Differential pulse amplitude modulation for multiple-input single-output OWVLC

NASA Astrophysics Data System (ADS)

Yang, S. H.; Kwon, D. H.; Kim, S. J.; Son, Y. H.; Han, S. K.

2015-01-01

White light-emitting diodes (LEDs) are widely used for lighting due to their energy efficiency, eco-friendly, and small size than previously light sources such as incandescent, fluorescent bulbs and so on. Optical wireless visible light communication (OWVLC) based on LED merges lighting and communications in applications such as indoor lighting, traffic signals, vehicles, and underwater communications because LED can be easily modulated. However, physical bandwidth of LED is limited about several MHz by slow time constant of the phosphor and characteristics of device. Therefore, using the simplest modulation format which is non-return-zero on-off-keying (NRZ-OOK), the data rate reaches only to dozens Mbit/s. Thus, to improve the transmission capacity, optical filtering and pre-, post-equalizer are adapted. Also, high-speed wireless connectivity is implemented using spectrally efficient modulation methods: orthogonal frequency division multiplexing (OFDM) or discrete multi-tone (DMT). However, these modulation methods need additional digital signal processing such as FFT and IFFT, thus complexity of transmitter and receiver is increasing. To reduce the complexity of transmitter and receiver, we proposed a novel modulation scheme which is named differential pulse amplitude modulation. The proposed modulation scheme transmits different NRZ-OOK signals with same amplitude and unit time delay using each LED chip, respectively. The `N' parallel signals from LEDs are overlapped and directly detected at optical receiver. Received signal is demodulated by power difference between unit time slots. The proposed scheme can overcome the bandwidth limitation of LEDs and data rate can be improved according to number of LEDs without complex digital signal processing.

A 0.18 μm CMOS low-power radiation sensor for asynchronous event-driven UWB wireless transmission

NASA Astrophysics Data System (ADS)

Bastianini, S.; Crepaldi, M.; Demarchi, D.; Gabrielli, A.; Lolli, M.; Margotti, A.; Villani, G.; Zhang, Z.; Zoccoli, G.

2013-12-01

The paper describes the design of a readout element, proposed as a radiation monitor, which implements an embedded sensor based on a floating-gate transistor. The paper shows the design of a microelectronic circuit composed of a sensor, an oscillator, a modulator, a transmitter and an integrated antenna. A prototype chip has recently been fabricated and tested exploiting a commercial 180 nm, four metal CMOS technology. Simulation results of the entire behavior of the circuit before submission are presented along with some measurements of the actual chip response. In addition, preliminary tests of the performance of the Ultra-Wide Band transmission via the integrated antenna are summarized. As the complete chip prototype area is less than 1 mm2, the chip fits a large variety of applications, from spot radiation monitoring systems in medicine to punctual measurements of radiation level in High-Energy Physics experiments. A sensitivity of 1 mV/rad was estimated within an absorbed dose range up to 10 krad and a total power consumption of about 165 μW.

Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

PubMed

Chen, Guanyu; Yu, Yu; Zhang, Xinliang

2016-08-01

We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

A multi-modal stereo microscope based on a spatial light modulator.

PubMed

Lee, M P; Gibson, G M; Bowman, R; Bernet, S; Ritsch-Marte, M; Phillips, D B; Padgett, M J

2013-07-15

Spatial Light Modulators (SLMs) can emulate the classic microscopy techniques, including differential interference (DIC) contrast and (spiral) phase contrast. Their programmability entails the benefit of flexibility or the option to multiplex images, for single-shot quantitative imaging or for simultaneous multi-plane imaging (depth-of-field multiplexing). We report the development of a microscope sharing many of the previously demonstrated capabilities, within a holographic implementation of a stereo microscope. Furthermore, we use the SLM to combine stereo microscopy with a refocusing filter and with a darkfield filter. The instrument is built around a custom inverted microscope and equipped with an SLM which gives various imaging modes laterally displaced on the same camera chip. In addition, there is a wide angle camera for visualisation of a larger region of the sample.

High-speed highly temperature stable 980 nm VCSELs operating at 25 Gb/s at up to 85 °C for short reach optical interconnects

NASA Astrophysics Data System (ADS)

Mutig, Alex; Lott, James A.; Blokhin, Sergey A.; Moser, Philip; Wolf, Philip; Hofmann, Werner; Nadtochiy, Alexey M.; Bimberg, Dieter

2011-03-01

The progressive penetration of optical communication links into traditional copper interconnect markets greatly expands the applications of vertical cavity surface emitting lasers (VCSELs) for the next-generation of board-to-board, moduleto- module, chip-to-chip, and on-chip optical interconnects. Stability of the VCSEL parameters at high temperatures is indispensable for such applications, since these lasers typically reside directly on or near integrated circuit chips. Here we present 980 nm oxide-confined VCSELs operating error-free at bit rates up to 25 Gbit/s at temperatures as high as 85 °C without adjustment of the drive current and peak-to-peak modulation voltage. The driver design is therefore simplified and the power consumption of the driver electronics is lowered, reducing the production and operational costs. Small and large signal modulation experiments at various temperatures from 20 up to 85 °C for lasers with different oxide aperture diameters are presented in order to analyze the physical processes controlling the performance of the VCSELs. Temperature insensitive maximum -3 dB bandwidths of around 13-15 GHz for VCSELs with aperture diameters of 10 μm and corresponding parasitic cut-off frequencies exceeding 22 GHz are observed. Presented results demonstrate the suitability of our VCSELs for practical high speed and high temperature stable short-reach optical links.

Flow-cytometric identification of vinegars using a multi-parameter analysis optical detection module

NASA Astrophysics Data System (ADS)

Verschooten, T.; Ottevaere, H.; Vervaeke, M.; Van Erps, J.; Callewaert, M.; De Malsche, W.; Thienpont, H.

2015-09-01

We show a proof-of-concept demonstration of a multi-parameter analysis low-cost optical detection system for the flowcytometric identification of vinegars. This multi-parameter analysis system can simultaneously measure laser induced fluorescence, absorption and scattering excited by two time-multiplexed lasers of different wavelengths. To our knowledge no other polymer optofluidic chip based system offers more simultaneous measurements. The design of the optofluidic channels is aimed at countering the effects that viscous fingering, air bubbles, and emulsion samples can have on the correct operation of such a detection system. Unpredictable variations in viscosity and refractive index of the channel content can be turned into a source of information. The sample is excited by two laser diodes that are driven by custom made low-cost laser drivers. The optofluidic chip is built to be robust and easy to handle and is reproducible using hot embossing. We show a custom optomechanical holder for the optofluidic chip that ensures correct alignment and automatic connection to the external fluidic system. We show an experiment in which 92 samples of vinegar are measured. We are able to identify 9 different kinds of vinegar with an accuracy of 94%. Thus we show an alternative approach to the classic optical spectroscopy solution at a lowered. Furthermore, we have shown the possibility of predicting the viscosity and turbidity of vinegars with a goodness-of-fit R2 over 0.947.

New Technology for Microfabrication and Testing of a Thermoelectric Device for Generating Mobile Electrical Power

NASA Technical Reports Server (NTRS)

Prasad, Narashimha S.; Taylor, Patrick J.; Trivedi, Sudhir B.; Kutcher, Susan

2010-01-01

We report the results of fabrication and testing of a thermoelectric power generation module. The module was fabricated using a new "flip-chip" module assembly technique that is scalable and modular. This technique results in a low value of contact resistivity ( < or = 10(exp 5) Ohms-sq cm). It can be used to leverage new advances in thin-film and nanostructured materials for the fabrication of new miniature thermoelectric devices. It may also enable monolithic integration of large devices or tandem arrays of devices on flexible or curved surfaces. Under mild testing, a power of 22 mW/sq cm was obtained from small (<100 K) temperature differences. At higher, more realistic temperature differences, approx.500 K, where the efficiency of these materials greatly improves, this power density would scale to between 0.5 and 1 Watt/cm2. These results highlight the excellent potential for the generation and scavenging of electrical power of practical and usable magnitude for remote applications using thermoelectric power generation technologies.

Design of mini-multi-gas monitoring system based on IR absorption

NASA Astrophysics Data System (ADS)

Tan, Qiu-lin; Zhang, Wen-dong; Xue, Chen-yang; Xiong, Ji-jun; Ma, You-chun; Wen, Fen

2008-07-01

In this paper, a novel non-dispersive infrared ray (IR) gas detection system is described. Conventional devices typically include several primary components: a broadband source (usually an incandescent filament), a rotating chopper shutter, a narrow-band filter, a sample tube and a detector. But we mainly use the mini-multi-channel detector, electrical modulation means and mini-gas-cell structure. To solve the problems of gas accidents in coal mines, and for family safety that results from using gas, this new IR detection system with integration, miniaturization and non-moving parts has been developed. It is based on the principle that certain gases absorb infrared radiation at specific (and often unique) wavelengths. The infrared detection optics principle used in developing this system is mainly analyzed. The idea of multi-gas detection is introduced and guided through the analysis of the single-gas detection. Through researching the design of cell structure, a cell with integration and miniaturization has been devised. By taking a single-chip microcomputer (SCM) as intelligence handling, the functional block diagram of a gas detection system is designed with the analyzing and devising of its hardware and software system. The way of data transmission on a controller area network (CAN) bus and wireless data transmission mode is explained. This system has reached the technology requirement of lower power consumption, mini-volume, wide measure range, and is able to realize multi-gas detection.

[Intelligent watch system for health monitoring based on Bluetooth low energy technology].

PubMed

Wang, Ji; Guo, Hailiang; Ren, Xiaoli

2017-08-01

According to the development status of wearable technology and the demand of intelligent health monitoring, we studied the multi-function integrated smart watches solution and its key technology. First of all, the sensor technology with high integration density, Bluetooth low energy (BLE) and mobile communication technology were integrated and used in develop practice. Secondly, for the hardware design of the system in this paper, we chose the scheme with high integration density and cost-effective computer modules and chips. Thirdly, we used real-time operating system FreeRTOS to develop the friendly graphical interface interacting with touch screen. At last, the high-performance application software which connected with BLE hardware wirelessly and synchronized data was developed based on android system. The function of this system included real-time calendar clock, telephone message, address book management, step-counting, heart rate and sleep quality monitoring and so on. Experiments showed that the collecting data accuracy of various sensors, system data transmission capacity, the overall power consumption satisfy the production standard. Moreover, the system run stably with low power consumption, which could realize intelligent health monitoring effectively.

Quantum dot SOA/silicon external cavity multi-wavelength laser.

PubMed

Zhang, Yi; Yang, Shuyu; Zhu, Xiaoliang; Li, Qi; Guan, Hang; Magill, Peter; Bergman, Keren; Baehr-Jones, Thomas; Hochberg, Michael

2015-02-23

We report a hybrid integrated external cavity, multi-wavelength laser for high-capacity data transmission operating near 1310 nm. This is the first demonstration of a single cavity multi-wavelength laser in silicon to our knowledge. The device consists of a quantum dot reflective semiconductor optical amplifier and a silicon-on-insulator chip with a Sagnac loop mirror and microring wavelength filter. We show four major lasing peaks from a single cavity with less than 3 dB power non-uniformity and demonstrate error-free 4 × 10 Gb/s data transmission.

Preliminary design for a standard 10 sup 7 bit Solid State Memory (SSM)

NASA Technical Reports Server (NTRS)

Hayes, P. J.; Howle, W. M., Jr.; Stermer, R. L., Jr.

1978-01-01

A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.

Reliable, Low-Cost, Low-Weight, Non-Hermetic Coating for MCM Applications

NASA Technical Reports Server (NTRS)

Jones, Eric W.; Licari, James J.

2000-01-01

Through an Air Force Research Laboratory sponsored STM program, reliable, low-cost, low-weight, non-hermetic coatings for multi-chip-module(MCK applications were developed. Using the combination of Sandia Laboratory ATC-01 test chips, AvanTeco's moisture sensor chips(MSC's), and silicon slices, we have shown that organic and organic/inorganic overcoatings are reliable and practical non-hermetic moisture and oxidation barriers. The use of the MSC and unpassivated ATC-01 test chips provided rapid test results and comparison of moisture barrier quality of the overcoatings. The organic coatings studied were Parylene and Cyclotene. The inorganic coatings were Al2O3 and SiO2. The choice of coating(s) is dependent on the environment that the device(s) will be exposed to. We have defined four(4) classes of environments: Class I(moderate temperature/moderate humidity). Class H(high temperature/moderate humidity). Class III(moderate temperature/high humidity). Class IV(high temperature/high humidity). By subjecting the components to adhesion, FTIR, temperature-humidity(TH), pressure cooker(PCT), and electrical tests, we have determined that it is possible to reduce failures 50-70% for organic/inorganic coated components compared to organic coated components. All materials and equipment used are readily available commercially or are standard in most semiconductor fabrication lines. It is estimated that production cost for the developed technology would range from $1-10/module, compared to $20-200 for hermetically sealed packages.

SPAD array based TOF SoC design for unmanned vehicle

NASA Astrophysics Data System (ADS)

Pan, An; Xu, Yuan; Xie, Gang; Huang, Zhiyu; Zheng, Yanghao; Shi, Weiwei

2018-03-01

As for the requirement of unmanned-vehicle mobile Lidar system, this paper presents a SoC design based on pulsed TOF depth image sensor. This SoC has a detection range of 300m and detecting resolution of 1.5cm. Pixels are made of SPAD. Meanwhile, SoC adopts a structure of multi-pixel sharing TDC, which significantly reduces chip area and improve the fill factor of light-sensing surface area. SoC integrates a TCSPC module to achieve the functionality of receiving each photon, measuring photon flight time and processing depth information in one chip. The SOC is designed in the SMIC 0.13μm CIS CMOS technology

A multi-staining chip using hydrophobic valves for exfoliative cytology in cancer

NASA Astrophysics Data System (ADS)

Lee, Tae Hee; Bu, Jiyoon; Moon, Jung Eun; Kim, Young Jun; Kang, Yoon-Tae; Cho, Young-Ho; Kim, In Sik

2017-07-01

Exfoliative cytology is a highly established technique for the diagnosis of tumors. Various microfluidic devices have been developed to minimize the sample numbers by conjugating multiple antibodies in a single sample. However, the previous multi-staining devices require complex control lines and valves operated by external power sources, to deliver multiple antibodies separately for a single sample. In addition, most of these devices are composed of hydrophobic materials, causing unreliable results due to the non-specific binding of antibodies. Here, we present a multi-staining chip using hydrophobic valves, which is formed by the partial treatment of 2-hydroxyethyl methacrylate (HEMA). Our chip consists of a circular chamber, divided into six equal fan-shaped regions. Switchable injection ports are located at the center of the chamber and at the middle of the arc of each fan-shaped zone. Thus, our device is beneficial for minimizing the control lines, since pre-treatment solutions flow from the center to outer ports, while six different antibodies are introduced oppositely from the outer ports. Furthermore, hydrophobic narrow channels, connecting the central region and each of the six fan-shaped zones, are closed by capillary effect, thus preventing the fluidic mixing without external power sources. Meanwhile, HEMA treatment on the exterior region results in hydrophobic-to-hydrophilic transition and prevents the non-specific binding of antibodies. For the application, we measured the expression of six different antibodies in a single sample using our device. The expression levels of each antibody highly matched the conventional immunocytochemistry results. Our device enables cancer screening with a small number of antibodies for a single sample.

The Level 0 Pixel Trigger system for the ALICE experiment

NASA Astrophysics Data System (ADS)

Aglieri Rinella, G.; Kluge, A.; Krivda, M.; ALICE Silicon Pixel Detector project

2007-01-01

The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper.

Chip-scale integrated optical interconnects: a key enabler for future high-performance computing

NASA Astrophysics Data System (ADS)

Haney, Michael; Nair, Rohit; Gu, Tian

2012-01-01

High Performance Computing (HPC) systems are putting ever-increasing demands on the throughput efficiency of their interconnection fabrics. In this paper, the limits of conventional metal trace-based inter-chip interconnect fabrics are examined in the context of state-of-the-art HPC systems, which currently operate near the 1 GFLOPS/W level. The analysis suggests that conventional metal trace interconnects will limit performance to approximately 6 GFLOPS/W in larger HPC systems that require many computer chips to be interconnected in parallel processing architectures. As the HPC communications bottlenecks push closer to the processing chips, integrated Optical Interconnect (OI) technology may provide the ultra-high bandwidths needed at the inter- and intra-chip levels. With inter-chip photonic link energies projected to be less than 1 pJ/bit, integrated OI is projected to enable HPC architecture scaling to the 50 GFLOPS/W level and beyond - providing a path to Peta-FLOPS-level HPC within a single rack, and potentially even Exa-FLOPSlevel HPC for large systems. A new hybrid integrated chip-scale OI approach is described and evaluated. The concept integrates a high-density polymer waveguide fabric directly on top of a multiple quantum well (MQW) modulator array that is area-bonded to the Silicon computing chip. Grayscale lithography is used to fabricate 5 μm x 5 μm polymer waveguides and associated novel small-footprint total internal reflection-based vertical input/output couplers directly onto a layer containing an array of GaAs MQW devices configured to be either absorption modulators or photodetectors. An external continuous wave optical "power supply" is coupled into the waveguide links. Contrast ratios were measured using a test rider chip in place of a Silicon processing chip. The results suggest that sub-pJ/b chip-scale communication is achievable with this concept. When integrated into high-density integrated optical interconnect fabrics, it could provide a seamless interconnect fabric spanning the intra-

DOE Office of Scientific and Technical Information (OSTI.GOV)

Horowitz, Kelsey A; Bench Reese, Samantha R; Remo, Timothy W

This brochure, published as an annual research highlight of the Clean Energy Manufacturing Analysis Center (CEMAC), summarizes CEMAC analysis of silicon carbide (SiC) power electronics for variable frequency motor drives. The key finding presented is that variations in manufacturing expertise, yields, and access to existing facilities impact regional costs and manufacturing location decisions for SiC ingots, wafers, chips, and power modules more than do core country-specific factors such as labor and electricity costs.

Design and implementation of quadrature bandpass sigma-delta modulator used in low-IF RF receiver

NASA Astrophysics Data System (ADS)

Ge, Binjie; Li, Yan; Yu, Hang; Feng, Xiaoxing

2018-05-01

This paper presents the design and implementation of quadrature bandpass sigma-delta modulator. A pole movement method for transforming real sigma-delta modulator to a quadrature one is proposed by detailed study of the relationship of noise-shaping center frequency and integrator pole position in sigma-delta modulator. The proposed modulator uses sampling capacitor sharing switched capacitor integrator, and achieves a very small feedback coefficient by a series capacitor network, and those two techniques can dramatically reduce capacitor area. Quantizer output-dependent dummy capacitor load for reference voltage buffer can compensate signal-dependent noise that is caused by load variation. This paper designs a quadrature bandpass Sigma-Delta modulator for 2.4 GHz low IF receivers that achieve 69 dB SNDR at 1 MHz BW and -1 MHz IF with 48 MHz clock. The chip is fabricated with SMIC 0.18 μm CMOS technology, it achieves a total power current of 2.1 mA, and the chip area is 0.48 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61471245, U1201256), the Guangdong Province Foundation (No. 2014B090901031), and the Shenzhen Foundation (Nos. JCYJ20160308095019383, JSGG20150529160945187).

Powerful actuation of magnetized microtools by focused magnetic field for particle sorting in a chip.

PubMed

Yamanishi, Yoko; Sakuma, Shinya; Onda, Kazuhisa; Arai, Fumihito

2010-08-01

This paper describes a novel powerful noncontact actuation of a magnetically driven microtool (MMT), achieved by magnetization of the MMT and focusing of the magnetic field in a microfluidic chip for particle sorting. The following are the highlights of this study: (1) an MMT was successfully fabricated from a mixture of neodymium powder and polydimethylsiloxane; the MMT was magnetized such that it acted as an elastic micromagnet with a magnetic flux density that increased by about 100 times after magnetization, and (2) a pair of sharp magnetic needles was fabricated adjacent to a microchannel in a chip by electroplating, in order to focus the magnetic flux density generated by the electromagnetic coils below the biochip; these needles contribute to miniaturization of an actuation module that would enable the integration of multiple functions in the limited area of a chip. FEM analysis of the magnetic flux density around the MMT showed that the magnetic flux density in the setup with the magnetic needles was around 8 times better than that in the setup without the needles. By magnetization, the drive frequency of the MMT improved by about 10 times--from 18 Hz to 180 Hz. We successfully demonstrated the separation of copolymer beads of a particular size in a chip by image sensing.

Molded underfill (MUF) encapsulation for flip-chip package: A numerical investigation

NASA Astrophysics Data System (ADS)

Azmi, M. A.; Abdullah, M. K.; Abdullah, M. Z.; Ariff, Z. M.; Saad, Abdullah Aziz; Hamid, M. F.; Ismail, M. A.

2017-07-01

This paper presents the numerical simulation of epoxy molding compound (EMC) filling in multi flip-chip packages during encapsulation process. The empty and a group flip chip packages were considered in the mold cavity in order to study the flow profile of the EMC. SOLIDWORKS software was used for three-dimensional modeling and it was incorporated into fluid analysis software namely as ANSYS FLUENT. The volume of fluid (VOF) technique was used for capturing the flow front profiles and Power Law model was applied for its rheology model. The numerical result are compared and discussed with previous experimental and it was shown a good conformity for model validation. The prediction of flow front was observed and analyzed at different filling time. The possibility and visual of void formation in the package is captured and the number of flip-chip is one factor that contributed to the void formation.

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder.

PubMed

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive.

A Bidirectional Brain-Machine Interface Featuring a Neuromorphic Hardware Decoder

PubMed Central

Boi, Fabio; Moraitis, Timoleon; De Feo, Vito; Diotalevi, Francesco; Bartolozzi, Chiara; Indiveri, Giacomo; Vato, Alessandro

2016-01-01

Bidirectional brain-machine interfaces (BMIs) establish a two-way direct communication link between the brain and the external world. A decoder translates recorded neural activity into motor commands and an encoder delivers sensory information collected from the environment directly to the brain creating a closed-loop system. These two modules are typically integrated in bulky external devices. However, the clinical support of patients with severe motor and sensory deficits requires compact, low-power, and fully implantable systems that can decode neural signals to control external devices. As a first step toward this goal, we developed a modular bidirectional BMI setup that uses a compact neuromorphic processor as a decoder. On this chip we implemented a network of spiking neurons built using its ultra-low-power mixed-signal analog/digital circuits. On-chip on-line spike-timing-dependent plasticity synapse circuits enabled the network to learn to decode neural signals recorded from the brain into motor outputs controlling the movements of an external device. The modularity of the BMI allowed us to tune the individual components of the setup without modifying the whole system. In this paper, we present the features of this modular BMI and describe how we configured the network of spiking neuron circuits to implement the decoder and to coordinate it with the encoder in an experimental BMI paradigm that connects bidirectionally the brain of an anesthetized rat with an external object. We show that the chip learned the decoding task correctly, allowing the interfaced brain to control the object's trajectories robustly. Based on our demonstration, we propose that neuromorphic technology is mature enough for the development of BMI modules that are sufficiently low-power and compact, while being highly computationally powerful and adaptive. PMID:28018162

Transient thermal characteristics of high-temperature SiC power module enhanced with Al-bump technology

NASA Astrophysics Data System (ADS)

Tanisawa, Hidekazu; Kato, Fumiki; Koui, Kenichi; Sato, Shinji; Watanabe, Kinuyo; Takahashi, Hiroki; Murakami, Yoshinori; Sato, Hiroshi

2018-04-01

In this paper, we demonstrate a mounting technology that improves the tolerance to transient power loss by adding a heat capacity near the device. Silicon carbide (SiC) power devices can operate at high temperatures, up to 250 °C, at which silicon (Si) power devices cannot. Therefore, it is possible to allow a large temperature difference between the device and ambient air. Thus, the size of a power converter equipped with an SiC power module is reduced by simplifying the cooling system. The temperature of the power module is important not only in the steady state, but in transient loads as well. Therefore, we developed the Al-bump flip-chip mounting technology to increase heat capacity near the device. With this proposed structure, the heat capacity per device increased by 1.7% compared with the total heat capacity of the conventional structure using wire bonding. The reduction in transient thermal impedance is observed from 0.003 to 3 s, and we confirmed that the transient thermal impedance is reduced very efficiently by 15% at the maximum, compared with the conventional structure.

Lab-on-a-chip modules for detection of highly pathogenic bacteria: from sample preparation to detection

NASA Astrophysics Data System (ADS)

Julich, S.; Kopinč, R.; Hlawatsch, N.; Moche, C.; Lapanje, A.; Gärtner, C.; Tomaso, H.

2014-05-01

Lab-on-a-chip systems are innovative tools for the detection and identification of microbial pathogens in human and veterinary medicine. The major advantages are small sample volume and a compact design. Several fluidic modules have been developed to transform analytical procedures into miniaturized scale including sampling, sample preparation, target enrichment, and detection procedures. We present evaluation data for single modules that will be integrated in a chip system for the detection of pathogens. A microfluidic chip for purification of nucleic acids was established for cell lysis using magnetic beads. This assay was evaluated with spiked environmental aerosol and swab samples. Bacillus thuringiensis was used as simulant for Bacillus anthracis, which is closely related but non-pathogenic for humans. Stationary PCR and a flow-through PCR chip module were investigated for specific detection of six highly pathogenic bacteria. The conventional PCR assays could be transferred into miniaturized scale using the same temperature/time profile. We could demonstrate that the microfluidic chip modules are suitable for the respective purposes and are promising tools for the detection of bacterial pathogens. Future developments will focus on the integration of these separate modules to an entire lab-on-a-chip system.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

NASA Astrophysics Data System (ADS)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2017-04-01

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Ultrasensitive NO2 gas sensors using hybrid heterojunctions of multi-walled carbon nanotubes and on-chip grown SnO2 nanowires

NASA Astrophysics Data System (ADS)

Nguyet, Quan Thi Minh; Van Duy, Nguyen; Manh Hung, Chu; Hoa, Nguyen Duc; Van Hieu, Nguyen

2018-04-01

Hybrid heterojunction devices are designed for ultrahigh response to NO2 toxic gas. The devices were constructed by assembling multi-walled carbon nanotubes (MWCNTs) on a microelectrode chip bridged bare Pt-electrode and a Pt-electrode with pre-grown SnO2 nanowires (NWs). All heterojunction devices were realized using different types of MWCNTs, which exhibit ultrahigh response to sub-ppm NO2 gas at 50 °C operated in the reverse bias mode. The response to 1 ppm NO2 gas reaches 11300, which is about 100 times higher than that of a back-to-back heterojunction device fabricated from SnO2 NWs and MWCNTs. In addition, the present device exhibits an ultralow detection limit of about 0.68 ppt. The modulation of trap-assisted tunneling current under reverse bias is the main gas-sensing mechanism. This principle device presents a concept for developing gas sensors made of a hybrid between semiconductor metal oxide NWs and CNTs.

Possibilities for mixed mode chip manufacturing in EUROPRACTICE

NASA Astrophysics Data System (ADS)

Das, C.

1997-02-01

EUROPRACTICE is an EC initiative under the ESPRIT programme which aims to stimulate the wider exploitation of state-of-the-art microelectronics technologies by European industry and to enhance European industrial competitiveness in the global market-place. Through EUROPRACTICE, the EC has created a range of Basic Services that offer users a cost-effective and flexible means of accessing three main microelectronics-based technologies: Application Specific Integrated Circuit (ASICs), Multi-Chip Modules (MCMs) and Microsystems. EUROPRACTICE Basic Services reduce the cost and risk for companies wishing to begin using these technologies. EUROPRACTICE offers a fully supported, low cost route for companies to design and fabricate ASICs for their individual applications. Low cost is achieved by consolidating designs from many users onto a single semiconductor wafer (MPW: Multi Project Wafer). The EUROPRACTICE IC Manufacturing Service (ICMS) offers a broad range of fabrication technologies including CMOS, BiCMOS and GaAs. The Service extends from enabling users to produce prototype ASICs for testing and evaluation, through to low-volume production runs.

Test systems of the STS-XYTER2 ASIC: from wafer-level to in-system verification

NASA Astrophysics Data System (ADS)

Kasinski, Krzysztof; Zubrzycka, Weronika

2016-09-01

The STS/MUCH-XYTER2 ASIC is a full-size prototype chip for the Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the new fixed-target experiment Compressed Baryonic Matter (CBM) at FAIR-center, Darmstadt, Germany. The STS assembly includes more than 14000 ASICs. The complicated, time-consuming, multi-step assembly process of the detector building blocks and tight quality assurance requirements impose several intermediate testing to be performed for verifying crucial assembly steps (e.g. custom microcable tab-bonding before wire-bonding to the PCB) and - if necessary - identifying channels or modules for rework. The chip supports the multi-level testing with different probing / contact methods (wafer probe-card, pogo-probes, in-system tests). A huge number of ASICs to be tested restricts the number and kind of tests possible to be performed within a reasonable time. The proposed architectures of test stand equipment and a brief summary of methodologies are presented in this paper.

System on chip (SOC) wi-fi microcontroller for multistation measurement of water surface level using ultrasonic sensor

NASA Astrophysics Data System (ADS)

Suryono, Suryono; Purnomo Putro, Sapto; Widowati; Adhy, Satriyo

2018-05-01

Experimental results of data acquisition and transmission of water surface level from the field using System on Chip (SOC) Wi-Fi microcontroller are described here. System on Chip (SOC) Wi-Fi microcontroller is useful in dealing with limitations of in situ measurement by people. It is expected to address the problem of field instrumentation such as complexities in electronic circuit, power supply, efficiency, and automation of digital data acquisition. The system developed here employs five (5) nodes consisting of ultrasonic water surface level sensor using (SOC) Wi-Fi microcontroller. The five nodes are connected to a Wi-Fi router as the gateway to send multi-station data to a computer host. Measurement of water surface level using SOC Wi-Fi microcontroller manages conduct multi-station communication via database service programming that is capable of inputting every data sent to the database record according to the identity of data sent. The system here has a measurement error of 0.65 cm, while in terms of range, communication between data node to gateway varies in distance from 25 m to 45 m. Communication has been successfully conducted from one Wi-Fi gateway to the other that further improvement for its multi-station range is a certain possibility.

Adjustment of multi-CCD-chip-color-camera heads

NASA Astrophysics Data System (ADS)

Guyenot, Volker; Tittelbach, Guenther; Palme, Martin

1999-09-01

The principle of beam-splitter-multi-chip cameras consists in splitting an image into differential multiple images of different spectral ranges and in distributing these onto separate black and white CCD-sensors. The resulting electrical signals from the chips are recombined to produce a high quality color picture on the monitor. Because this principle guarantees higher resolution and sensitivity in comparison to conventional single-chip camera heads, the greater effort is acceptable. Furthermore, multi-chip cameras obtain the compete spectral information for each individual object point while single-chip system must rely on interpolation. In a joint project, Fraunhofer IOF and STRACON GmbH and in future COBRA electronic GmbH develop methods for designing the optics and dichroitic mirror system of such prism color beam splitter devices. Additionally, techniques and equipment for the alignment and assembly of color beam splitter-multi-CCD-devices on the basis of gluing with UV-curable adhesives have been developed, too.

Optical interconnection networks for high-performance computing systems

NASA Astrophysics Data System (ADS)

Biberman, Aleksandr; Bergman, Keren

2012-04-01

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rey, D.; Ryan, W.; Ross, M.

A method for more efficiently utilizing the frequency bandwidth allocated for data transmission is presented. Current space and range communication systems use modulation and coding schemes that transmit 0.5 to 1.0 bits per second per Hertz of radio frequency bandwidth. The goal in this LDRD project is to increase the bandwidth utilization by employing advanced digital communications techniques. This is done with little or no increase in the transmit power which is usually very limited on airborne systems. Teaming with New Mexico State University, an implementation of trellis coded modulation (TCM), a coding and modulation scheme pioneered by Ungerboeck, wasmore » developed for this application and simulated on a computer. TCM provides a means for reliably transmitting data while simultaneously increasing bandwidth efficiency. The penalty is increased receiver complexity. In particular, the trellis decoder requires high-speed, application-specific digital signal processing (DSP) chips. A system solution based on the QualComm Viterbi decoder and the Graychip DSP receiver chips is presented.« less

A High Performance Delta-Sigma Modulator for Neurosensing

PubMed Central

Xu, Jian; Zhao, Menglian; Wu, Xiaobo; Islam, Md. Kafiul; Yang, Zhi

2015-01-01

Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-μm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 μW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors. PMID:26262623

A programmable microsystem using system-on-chip for real-time biotelemetry.

PubMed

Wang, Lei; Johannessen, Erik A; Hammond, Paul A; Cui, Li; Reid, Stuart W J; Cooper, Jonathan M; Cumming, David R S

2005-07-01

A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm x 5 mm silicon chip using a 0.6 microm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm x 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10(-3) using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power.

Ten-channel InP-based large-scale photonic integrated transmitter fabricated by SAG technology

NASA Astrophysics Data System (ADS)

Zhang, Can; Zhu, Hongliang; Liang, Song; Cui, Xiao; Wang, Huitao; Zhao, Lingjuan; Wang, Wei

2014-12-01

A 10-channel InP-based large-scale photonic integrated transmitter was fabricated by selective area growth (SAG) technology combined with butt-joint regrowth (BJR) technology. The SAG technology was utilized to fabricate the electroabsorption modulated distributed feedback (DFB) laser (EML) arrays at the same time. The design of coplanar electrodes for electroabsorption modulator (EAM) was used for the flip-chip bonding package. The lasing wavelength of DFB laser could be tuned by the integrated micro-heater to match the ITU grids, which only needs one electrode pad. The average output power of each channel is 250 μW with an injection current of 200 mA. The static extinction ratios of the EAMs for 10 channels tested are ranged from 15 to 27 dB with a reverse bias of 6 V. The frequencies of 3 dB bandwidth of the chip for each channel are around 14 GHz. The novel design and simple fabrication process show its enormous potential in reducing the cost of large-scale photonic integrated circuit (LS-PIC) transmitter with high chip yields.

Biwavelength transceiver module for parallel simultaneous bidirectional optical interconnections

NASA Astrophysics Data System (ADS)

Nguyen, Nga T. H.; Ukaegbu, Ikechi A.; Sangirov, Jamshid; Cho, Mu-Hee; Lee, Tae-Woo; Park, Hyo-Hoon

2013-12-01

The design of a biwavelength transceiver (TRx) module for parallel simultaneous bidirectional optical interconnects is described. The TRx module has been implemented using two different wavelengths, 850 and 1060 nm, to send and receive signals simultaneously through a common optical interface while optimizing cost and performance. Filtering mirrors are formed in the optical fibers which are embedded on a V-grooved silicon substrate for reflecting and filtering optical signals from/to vertical-cavity surface-emitting laser (VCSEL)/photodiode (PD). The VCSEL and PD are flip-chip bonded on individual silicon optical benches, which are attached on the silicon substrate for optical signal coupling from the VCSEL to fiber and from fiber to the PD. A high-speed and low-loss ceramic printed circuit board, which has a compact size of 0.033 cc, has been designed to carry transmitter and receiver chips for easy packaging of the TRx module. Applied for quad small form-factor pluggable applications at 40-Gbps operation, the four-channel biwavelength TRx module showed clear eye diagrams with a bit error rate (BER) of 10-12 at input powers of -5 and -5.8 dBm for 1060 and 850 nm operation modes, respectively.

Design Trade-off Between Performance and Fault-Tolerance of Space Onboard Computers

NASA Astrophysics Data System (ADS)

Gorbunov, M. S.; Antonov, A. A.

2017-01-01

It is well known that there is a trade-off between performance and power consumption in onboard computers. The fault-tolerance is another important factor affecting performance, chip area and power consumption. Involving special SRAM cells and error-correcting codes is often too expensive with relation to the performance needed. We discuss the possibility of finding the optimal solutions for modern onboard computer for scientific apparatus focusing on multi-level cache memory design.

Energy Neutral Wireless Bolt for Safety Critical Fastening

PubMed Central

Seyoum, Biruk B.

2017-01-01

Thermoelectric generators (TEGs) are now capable of powering the abundant low power electronics from very small (just a few degrees Celsius) temperature gradients. This factor along with the continuously lowering cost and size of TEGs, has contributed to the growing number of miniaturized battery-free sensor modules powered by TEGs. In this article, we present the design of an ambient-powered wireless bolt for high-end electro-mechanical systems. The bolt is equipped with a temperature sensor and a low power RF chip powered from a TEG. A DC-DC converter interfacing the TEG with the RF chip is used to step-up the low TEG voltage. The work includes the characterizations of different TEGs and DC-DC converters to determine the optimal design based on the amount of power that can be generated from a TEG under different loads and at temperature gradients typical of industrial environments. A prototype system was implemented and the power consumption of this system under different conditions was also measured. Results demonstrate that the power generated by the TEG at very low temperature gradients is sufficient to guarantee continuous wireless monitoring of the critical fasteners in critical systems such as avionics, motorsport and aerospace. PMID:28954432

Energy Neutral Wireless Bolt for Safety Critical Fastening.

PubMed

Seyoum, Biruk B; Rossi, Maurizio; Brunelli, Davide

2017-09-26

Thermoelectric generators (TEGs) are now capable of powering the abundant low power electronics from very small (just a few degrees Celsius) temperature gradients. This factor along with the continuously lowering cost and size of TEGs, has contributed to the growing number of miniaturized battery-free sensor modules powered by TEGs. In this article, we present the design of an ambient-powered wireless bolt for high-end electro-mechanical systems. The bolt is equipped with a temperature sensor and a low power RF chip powered from a TEG. A DC-DC converter interfacing the TEG with the RF chip is used to step-up the low TEG voltage. The work includes the characterizations of different TEGs and DC-DC converters to determine the optimal design based on the amount of power that can be generated from a TEG under different loads and at temperature gradients typical of industrial environments. A prototype system was implemented and the power consumption of this system under different conditions was also measured. Results demonstrate that the power generated by the TEG at very low temperature gradients is sufficient to guarantee continuous wireless monitoring of the critical fasteners in critical systems such as avionics, motorsport and aerospace.

Custom chipset and compact module design for a 75-110 GHz laboratory signal source

NASA Astrophysics Data System (ADS)

Morgan, Matthew A.; Boyd, Tod A.; Castro, Jason J.

2016-12-01

We report on the development and characterization of a compact, full-waveguide bandwidth (WR-10) signal source for general-purpose testing of mm-wave components. The monolithic microwave integrated circuit (MMIC) based multichip module is designed for compactness and ease-of-use, especially in size-constrained test sets such as a wafer probe station. It takes as input a cm-wave continuous-wave (CW) reference and provides a factor of three frequency multiplication as well as amplification, output power adjustment, and in situ output power monitoring. It utilizes a number of custom MMIC chips such as a Schottky-diode limiter and a broadband mm-wave detector, both designed explicitly for this module, as well as custom millimeter-wave multipliers and amplifiers reported in previous papers.

Ultra-low-power wireless transmitter for neural prostheses with modified pulse position modulation.

PubMed

Goodarzy, Farhad; Skafidas, Stan E

2014-01-01

An ultra-low-power wireless transmitter for embedded bionic systems is proposed, which achieves 40 pJ/b energy efficiency and delivers 500 kb/s data using the medical implant communication service frequency band (402-405 MHz). It consumes a measured peak power of 200 µW from a 1.2 V supply while occupying an active area of 0.0016 mm(2) in a 130 nm technology. A modified pulse position modulation technique called saturated amplified signal is proposed and implemented, which can reduce the overall and per bit transferred power consumption of the transmitter while reducing the complexity of the transmitter architectures, and hence potentially shrinking the size of the implemented circuitry. The design is capable of being fully integrated on single-chip solutions for surgically implanted bionic systems, wearable devices and neural embedded systems.

Si Thermoelectric Power Generator with an Unconventional Structure

NASA Astrophysics Data System (ADS)

Sakamoto, Tatsuya; Iida, Tsutomu; Ohno, Yota; Ishikawa, Masashi; Kogo, Yasuo; Hirayama, Naomi; Arai, Koya; Nakamura, Takashi; Nishio, Keishi; Takanashi, Yoshifumi

2014-06-01

We examine the mechanical stability of an unconventional Mg2Si thermoelectric generator (TEG) structure. In this structure, the angle θ between the thermoelectric (TE) chips and the heat sink is less than 90°. We examined the tolerance to an external force of various Mg2Si TEG structures using a finite-element method (FEM) with the ANSYS code. The output power of the TEGs was also measured. First, for the FEM analysis, the mechanical properties of sintered Mg2Si TE chips, such as the bending strength and Young's modulus, were measured. Then, two-dimensional (2D) TEG models with various values of θ (90°, 75°, 60°, 45°, 30°, 15°, and 0°) were constructed in ANSYS. The x and y axes were defined as being in the horizontal and vertical directions of the substrate, respectively. In the analysis, the maximum tensile stress in the chip when a constant load was applied to the TEG model in the x direction was determined. Based on the analytical results, an appropriate structure was selected and a module fabricated. For the TEG fabrication, eight TE chips, each with dimensions of 3 mm × 3 mm × 10 mm and consisting of Sb-doped n-Mg2Si prepared by a plasma-activated sintering process, were assembled such that two chips were connected in parallel, and four pairs of these were connected in series on a footprint of 46 mm × 12 mm. The measured power generation characteristics and temperature distribution with temperature differences between 873 K and 373 K are discussed.

Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power Chips

PubMed Central

Feng, Shuang-Tao; Mei, Yun-Hui; Chen, Gang; Li, Xin; Lu, Guo-Quan

2016-01-01

Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30–35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future. PMID:28773686

Characterizations of Rapid Sintered Nanosilver Joint for Attaching Power Chips.

PubMed

Feng, Shuang-Tao; Mei, Yun-Hui; Chen, Gang; Li, Xin; Lu, Guo-Quan

2016-07-12

Sintering of nanosilver paste has been extensively studied as a lead-free die-attach solution for bonding semiconductor power chips, such as the power insulated gated bipolar transistor (IGBT). However, for the traditional method of bonding IGBT chips, an external pressure of a few MPa is reported necessary for the sintering time of ~1 h. In order to shorten the processing duration time, we developed a rapid way to sinter nanosilver paste for bonding IGBT chips in less than 5 min using pulsed current. In this way, we firstly dried as-printed paste at about 100 °C to get rid of many volatile solvents because they may result in defects or voids during the out-gassing from the paste. Then, the pre-dried paste was further heated by pulse current ranging from 1.2 kA to 2.4 kA for several seconds. The whole procedure was less than 3 min and did not require any gas protection. We could obtain robust sintered joint with shear strength of 30-35 MPa for bonding 1200-V, 25-A IGBT and superior thermal properties. Static and dynamic electrical performance of the as-bonded IGBT assemblies was also characterized to verify the feasibility of this rapid sintering method. The results indicate that the electrical performance is comparable or even partially better than that of commercial IGBT modules. The microstructure evolution of the rapid sintered joints was also studied by scanning electron microscopy (SEM). This work may benefit the wide usage of nanosilver paste for rapid bonding IGBT chips in the future.

Self-phase-modulation induced spectral broadening in silicon waveguides

NASA Astrophysics Data System (ADS)

Boyraz, Ozdal; Indukuri, Tejaswi; Jalali, Bahram

2004-03-01

The prospect for generating supercontinuum pulses on a silicon chip is studied. Using ~4ps optical pulses with 2.2GW/cm2 peak power, a 2 fold spectral broadening is obtained. Theoretical calculations, that include the effect of two-photon-absorption, indicate up to 5 times spectral broadening is achievable at 10x higher peak powers. Representing a nonlinear loss mechanism at high intensities, TPA limits the maximum optical bandwidth that can be generated.

Self-phase-modulation induced spectral broadening in silicon waveguides.

PubMed

Boyraz, Ozdal; Indukuri, Tejaswi; Jalali, Bahram

2004-03-08

The prospect for generating supercontinuum pulses on a silicon chip is studied. Using ~4ps optical pulses with 2.2GW/cm(2) peak power, a 2 fold spectral broadening is obtained. Theoretical calculations, that include the effect of two-photon-absorption, indicate up to 5 times spectral broadening is achievable at 10x higher peak powers. Representing a nonlinear loss mechanism at high intensities, TPA limits the maximum optical bandwidth that can be generated.

Integrated sample-to-detection chip for nucleic acid test assays.

PubMed

Prakash, R; Pabbaraju, K; Wong, S; Tellier, R; Kaler, K V I S

2016-06-01

Nucleic acid based diagnostic techniques are routinely used for the detection of infectious agents. Most of these assays rely on nucleic acid extraction platforms for the extraction and purification of nucleic acids and a separate real-time PCR platform for quantitative nucleic acid amplification tests (NATs). Several microfluidic lab on chip (LOC) technologies have been developed, where mechanical and chemical methods are used for the extraction and purification of nucleic acids. Microfluidic technologies have also been effectively utilized for chip based real-time PCR assays. However, there are few examples of microfluidic systems which have successfully integrated these two key processes. In this study, we have implemented an electro-actuation based LOC micro-device that leverages multi-frequency actuation of samples and reagents droplets for chip based nucleic acid extraction and real-time, reverse transcription (RT) PCR (qRT-PCR) amplification from clinical samples. Our prototype micro-device combines chemical lysis with electric field assisted isolation of nucleic acid in a four channel parallel processing scheme. Furthermore, a four channel parallel qRT-PCR amplification and detection assay is integrated to deliver the sample-to-detection NAT chip. The NAT chip combines dielectrophoresis and electrostatic/electrowetting actuation methods with resistive micro-heaters and temperature sensors to perform chip based integrated NATs. The two chip modules have been validated using different panels of clinical samples and their performance compared with standard platforms. This study has established that our integrated NAT chip system has a sensitivity and specificity comparable to that of the standard platforms while providing up to 10 fold reduction in sample/reagent volumes.

120W, NA_0.15 fiber coupled LD module with 125-μm clad/NA 0.22 fiber by spatial coupling method

NASA Astrophysics Data System (ADS)

Ishige, Yuta; Kaji, Eisaku; Katayama, Etsuji; Ohki, Yutaka; Gajdátsy, Gábor; Cserteg, András.

2018-02-01

We have fabricated a fiber coupled semiconductor laser diode module by means of spatial beam combining of single emitter broad area semiconductor laser diode chips in the 9xx nm band. In the spatial beam multiplexing method, the numerical aperture of the output light from the optical fiber increases by increasing the number of laser diodes coupled into the fiber. To reduce it, we have tried the approach to improving assembly process technology. As a result, we could fabricate laser diode modules having a light output power of 120W or more and 95% power within NA of 0.15 or less from a single optical fiber with 125-μm cladding diameter. Furthermore, we have obtained that the laser diode module maintaining high coupling efficiency can be realized even around the fill factor of 0.95. This has been achieved by improving the optical alignment method regarding the fast axis stack pitch of the laser diodes in the laser diode module. Therefore, without using techniques such as polarization combining and wavelength combining, high output power was realized while keeping small numerical aperture. This contributes to a reduction in unit price per light output power of the pumping laser diode module.

InP on SOI devices for optical communication and optical network on chip

NASA Astrophysics Data System (ADS)

Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

2011-01-01

For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

Wireless Sensor Node for Autonomous Monitoring and Alerts in Remote Environments

NASA Technical Reports Server (NTRS)

Panangadan, Anand V. (Inventor); Monacos, Steve P. (Inventor)

2015-01-01

A method, apparatus, system, and computer program products provides personal alert and tracking capabilities using one or more nodes. Each node includes radio transceiver chips operating at different frequency ranges, a power amplifier, sensors, a display, and embedded software. The chips enable the node to operate as either a mobile sensor node or a relay base station node while providing a long distance relay link between nodes. The power amplifier enables a line-of-sight communication between the one or more nodes. The sensors provide a GPS signal, temperature, and accelerometer information (used to trigger an alert condition). The embedded software captures and processes the sensor information, provides a multi-hop packet routing protocol to relay the sensor information to and receive alert information from a command center, and to display the alert information on the display.

Holographic Patterning of High Performance on-chip 3D Lithium-ion Microbatteries

DOE PAGES

Ning, Hailong; Pikul, James H.; Wang, Runyu; ...

2015-05-11

As sensors, wireless communication devices, personal health monitoring systems, and autonomous microelectromechanical systems (MEMS) become distributed and smaller, there is an increasing demand for miniaturized integrated power sources. Although thin-film batteries are well-suited for on-chip integration, their energy and power per unit area are limited. Three-dimensional electrode designs have potential to offer much greater power and energy per unit area; however, efforts to date to realize 3D microbatteries have led to prototypes with solid electrodes (and therefore low power) or mesostructured electrodes not compatible with manufacturing or on-chip integration. Here in this paper, we demonstrate an on-chip compatible method tomore » fabricate high energy density (6.5 μWh cm -2∙μm -1) 3D mesostructured Li-ion microbatteries based on LiMnO 2 cathodes, and NiSn anodes that possess supercapacitor-like power (3,600 μW cm(-2)∙μm(-1) peak). The mesostructured electrodes are fabricated by combining 3D holographic lithography with conventional photolithography, enabling deterministic control of both the internal electrode mesostructure and the spatial distribution of the electrodes on the substrate. The resultant full cells exhibit impressive performances, for example a conventional light-emitting diode (LED) is driven with a 500-μA peak current (600-C discharge) from a 10-μm-thick microbattery with an area of 4 mm 2 for 200 cycles with only 12% capacity fade. Lastly, a combined experimental and modeling study where the structural parameters of the battery are modulated illustrates the unique design flexibility enabled by 3D holographic lithography and provides guidance for optimization for a given application.« less

Holographic patterning of high-performance on-chip 3D lithium-ion microbatteries

PubMed Central

Ning, Hailong; Pikul, James H.; Zhang, Runyu; Li, Xuejiao; Xu, Sheng; Wang, Junjie; Rogers, John A.; King, William P.; Braun, Paul V.

2015-01-01

As sensors, wireless communication devices, personal health monitoring systems, and autonomous microelectromechanical systems (MEMS) become distributed and smaller, there is an increasing demand for miniaturized integrated power sources. Although thin-film batteries are well-suited for on-chip integration, their energy and power per unit area are limited. Three-dimensional electrode designs have potential to offer much greater power and energy per unit area; however, efforts to date to realize 3D microbatteries have led to prototypes with solid electrodes (and therefore low power) or mesostructured electrodes not compatible with manufacturing or on-chip integration. Here, we demonstrate an on-chip compatible method to fabricate high energy density (6.5 μWh cm−2⋅μm−1) 3D mesostructured Li-ion microbatteries based on LiMnO2 cathodes, and NiSn anodes that possess supercapacitor-like power (3,600 μW cm−2⋅μm−1 peak). The mesostructured electrodes are fabricated by combining 3D holographic lithography with conventional photolithography, enabling deterministic control of both the internal electrode mesostructure and the spatial distribution of the electrodes on the substrate. The resultant full cells exhibit impressive performances, for example a conventional light-emitting diode (LED) is driven with a 500-μA peak current (600-C discharge) from a 10-μm-thick microbattery with an area of 4 mm2 for 200 cycles with only 12% capacity fade. A combined experimental and modeling study where the structural parameters of the battery are modulated illustrates the unique design flexibility enabled by 3D holographic lithography and provides guidance for optimization for a given application. PMID:25964360

Mapping power-law rheology of living cells using multi-frequency force modulation atomic force microscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Takahashi, Ryosuke; Okajima, Takaharu, E-mail: okajima@ist.hokudai.ac.jp

We present multi-frequency force modulation atomic force microscopy (AFM) for mapping the complex shear modulus G* of living cells as a function of frequency over the range of 50–500 Hz in the same measurement time as the single-frequency force modulation measurement. The AFM technique enables us to reconstruct image maps of rheological parameters, which exhibit a frequency-dependent power-law behavior with respect to G{sup *}. These quantitative rheological measurements reveal a large spatial variation in G* in this frequency range for single cells. Moreover, we find that the reconstructed images of the power-law rheological parameters are much different from those obtained inmore » force-curve or single-frequency force modulation measurements. This indicates that the former provide information about intracellular mechanical structures of the cells that are usually not resolved with the conventional force measurement methods.« less

Multi-element germanium detectors for synchrotron applications

NASA Astrophysics Data System (ADS)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; Vernon, E.; Pinelli, D.; Dooryhee, E.; Ghose, S.; Caswell, T.; Siddons, D. P.; Miceli, A.; Baldwin, J.; Almer, J.; Okasinski, J.; Quaranta, O.; Woods, R.; Krings, T.; Stock, S.

2018-04-01

We have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. We will discuss the technical details of the systems, and present some of the results from them.

Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

PubMed

Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

2011-12-19

We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

Algorithms for a very high speed universal noiseless coding module

NASA Technical Reports Server (NTRS)

Rice, Robert F.; Yeh, Pen-Shu

1991-01-01

The algorithmic definitions and performance characterizations are presented for a high performance adaptive coding module. Operation of at least one of these (single chip) implementations is expected to exceed 500 Mbits/s under laboratory conditions. Operation of a companion decoding module should operate at up to half the coder's rate. The module incorporates a powerful noiseless coder for Standard Form Data Sources (i.e., sources whose symbols can be represented by uncorrelated non-negative integers where the smaller integers are more likely than the larger ones). Performance close to data entropies can be expected over a Dynamic Range of from 1.5 to 12 to 14 bits/sample (depending on the implementation).

Microvalve controlled multi-functional microfluidic chip for divisional cell co-culture.

PubMed

Li, Rui; Zhang, Xingjian; Lv, Xuefei; Geng, Lina; Li, Yongrui; Qin, Kuiwei; Deng, Yulin

2017-12-15

Pneumatic micro-valve controlled microfluidic chip provides precise fluidic control for cell manipulation. In this paper, a multi-functional microfluidic chip was designed for three separate experiments: 1. Different cell lines were dispensed and cultured; 2. Three transfected SH-SY5Y cells were introduced and treated with methyl-phenyl-pyridinium (MPP + ) as drug delivery mode; 3. Specific protection and interaction were observed among cell co-culture after nerve damage. The outcomes revealed the potential and practicability of our entire multi-functional pneumatic chip system on different cell biology applications. Copyright © 2017. Published by Elsevier Inc.

Apollo 11 Command Service Module

NASA Technical Reports Server (NTRS)

1969-01-01

A close-up view of the Apollo 11 command service module ready to be mated with the spacecraft LEM adapter of the third stage. The towering 363-foot Saturn V was a multi-stage, multi-engine launch vehicle standing taller than the Statue of Liberty. Altogether, the Saturn V engines produced as much power as 85 Hoover Dams.

Multi-beam and single-chip LIDAR with discrete beam steering by digital micromirror device

NASA Astrophysics Data System (ADS)

Rodriguez, Joshua; Smith, Braden; Hellman, Brandon; Gin, Adley; Espinoza, Alonzo; Takashima, Yuzuru

2018-02-01

A novel Digital Micromirror Device (DMD) based beam steering enables a single chip Light Detection and Ranging (LIDAR) system for discrete scanning points. We present increasing number of scanning point by using multiple laser diodes for Multi-beam and Single-chip DMD-based LIDAR.

Multi-mode multi-band power amplifier module with high low-power efficiency

NASA Astrophysics Data System (ADS)

Xuguang, Zhang; Jie, Jin

2015-10-01

Increasingly, mobile communications standards require high power efficiency and low currents in the low power mode. This paper proposes a fully-integrated multi-mode and multi-band power amplifier module (PAM) to meet these requirements. A dual-path PAM is designed for high-power mode (HPM), medium-power mode (MPM), and low-power mode (LPM) operations without any series switches for different mode selection. Good performance and significant current saving can be achieved by using an optimized load impedance design for each power mode. The PAM is tapeout with the InGaP/GaAs heterojunction bipolar transistor (HBT) process and the 0.18-μm complementary metal-oxide semiconductor (CMOS) process. The test results show that the PAM achieves a very low quiescent current of 3 mA in LPM. Meanwhile, across the 1.7-2.0 GHz frequency, the PAM performs well. In HPM, the output power is 28 dBm with at least 39.4% PAE and -40 dBc adjacent channel leakage ratio 1 (ACLR1). In MPM, the output power is 17 dBm, with at least 21.3% PAE and -43 dBc ACLR1. In LPM, the output power is 8 dBm, with at least 18.2% PAE and -40 dBc ACLR1. Project supported by the National Natural Science Foundation of China (No. 61201244).

NASA Tech Briefs, December 2011

NASA Technical Reports Server (NTRS)

2011-01-01

Topics covered include: 1) SNE Industrial Fieldbus Interface; 2) Composite Thermal Switch; 3) XMOS XC-2 Development Board for Mechanical Control and Data Collection; 4) Receiver Gain Modulation Circuit; 5) NEXUS Scalable and Distributed Next-Generation Avionics Bus for Space Missions; 6) Digital Interface Board to Control Phase and Amplitude of Four Channels; 7) CoNNeCT Baseband Processor Module; 8) Cryogenic 160-GHz MMIC Heterodyne Receiver Module; 9) Ka-Band, Multi-Gigabit-Per-Second Transceiver; 10) All-Solid-State 2.45-to-2.78-THz Source; 11) Onboard Interferometric SAR Processor for the Ka-Band Radar Interferometer (KaRIn); 12) Space Environments Testbed; 13) High-Performance 3D Articulated Robot Display; 14) Athena; 15) In Situ Surface Characterization; 16) Ndarts; 17) Cryo-Etched Black Silicon for Use as Optical Black; 18) Advanced CO2 Removal and Reduction System; 19) Correcting Thermal Deformations in an Active Composite Reflector; 20) Umbilical Deployment Device; 21) Space Mirror Alignment System; 22) Thermionic Power Cell To Harness Heat Energies for Geothermal Applications; 23) Graph Theory Roots of Spatial Operators for Kinematics and Dynamics; 24) Spacesuit Soft Upper Torso Sizing Systems; 25) Radiation Protection Using Single-Wall Carbon Nanotube Derivatives; 26) PMA-PhyloChip DNA Microarray to Elucidate Viable Microbial Community Structure; 27) Lidar Luminance Quantizer; 28) Distributed Capacitive Sensor for Sample Mass Measurement; 29) Base Flow Model Validation; 30) Minimum Landing Error Powered-Descent Guidance for Planetary Missions; 31) Framework for Integrating Science Data Processing Algorithms Into Process Control Systems; 32) Time Synchronization and Distribution Mechanisms for Space Networks; 33) Local Estimators for Spacecraft Formation Flying; 34) Software-Defined Radio for Space-to-Space Communications; 35) Reflective Occultation Mask for Evaluation of Occulter Designs for Planet Finding; and 36) Molecular Adsorber Coating

Fault-Tolerant, Real-Time, Multi-Core Computer System

NASA Technical Reports Server (NTRS)

Gostelow, Kim P.

2012-01-01

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

Maisotsenko cycle applications in multi-stage ejector recycling module for chemical production

NASA Astrophysics Data System (ADS)

Levchenko, D. O.; Artyukhov, A. E.; Yurko, I. V.

2017-08-01

The article is devoted to the theoretical bases of multistage (multi-level) utilization modules as part of chemical plants (on the example of the technological line for obtaining nitrogen fertilizers). The possibility of recycling production waste (ammonia vapors, dust and substandard nitrogen fertilizers) using ejection devices and waste heat using Maisotsenko cycle technology (Maisotsenko heat and mass exchanger (HMX), Maisotsenko power cycles and recuperators, etc.) is substantiated. The principle of operation of studied recycling module and prospects for its implementation are presented. An improved technological scheme for obtaining granular fertilizers and granules with porous structure with multistage (multi-level) recycling module is proposed.

Pulsed depressed collector

DOEpatents

Kemp, Mark A

2015-11-03

A high power RF device has an electron beam cavity, a modulator, and a circuit for feed-forward energy recovery from a multi-stage depressed collector to the modulator. The electron beam cavity include a cathode, an anode, and the multi-stage depressed collector, and the modulator is configured to provide pulses to the cathode. Voltages of the electrode stages of the multi-stage depressed collector are allowed to float as determined by fixed impedances seen by the electrode stages. The energy recovery circuit includes a storage capacitor that dynamically biases potentials of the electrode stages of the multi-stage depressed collector and provides recovered energy from the electrode stages of the multi-stage depressed collector to the modulator. The circuit may also include a step-down transformer, where the electrode stages of the multi-stage depressed collector are electrically connected to separate taps on the step-down transformer.

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

NASA Technical Reports Server (NTRS)

Suarez, George; DuMonthier, Jeffrey J.; Sheikh, Salman S.; Powell, Wesley A.; King, Robyn L.

2012-01-01

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

A Novel Silicon Micromachined Integrated MCM Thermal Management System

NASA Technical Reports Server (NTRS)

Kazmierczak, M. J.; Henderson, H. T.; Gerner, F. M.

1997-01-01

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Image processing using Gallium Arsenide (GaAs) technology

NASA Technical Reports Server (NTRS)

Miller, Warner H.

1989-01-01

The need to increase the information return from space-borne imaging systems has increased in the past decade. The use of multi-spectral data has resulted in the need for finer spatial resolution and greater spectral coverage. Onboard signal processing will be necessary in order to utilize the available Tracking and Data Relay Satellite System (TDRSS) communication channel at high efficiency. A generally recognized approach to the increased efficiency of channel usage is through data compression techniques. The compression technique implemented is a differential pulse code modulation (DPCM) scheme with a non-uniform quantizer. The need to advance the state-of-the-art of onboard processing was recognized and a GaAs integrated circuit technology was chosen. An Adaptive Programmable Processor (APP) chip set was developed which is based on an 8-bit slice general processor. The reason for choosing the compression technique for the Multi-spectral Linear Array (MLA) instrument is described. Also a description is given of the GaAs integrated circuit chip set which will demonstrate that data compression can be performed onboard in real time at data rate in the order of 500 Mb/s.

Electric-field-controlled interface dipole modulation for Si-based memory devices.

PubMed

Miyata, Noriyuki

2018-05-31

Various nonvolatile memory devices have been investigated to replace Si-based flash memories or emulate synaptic plasticity for next-generation neuromorphic computing. A crucial criterion to achieve low-cost high-density memory chips is material compatibility with conventional Si technologies. In this paper, we propose and demonstrate a new memory concept, interface dipole modulation (IDM) memory. IDM can be integrated as a Si field-effect transistor (FET) based memory device. The first demonstration of this concept employed a HfO 2 /Si MOS capacitor where the interface monolayer (ML) TiO 2 functions as a dipole modulator. However, this configuration is unsuitable for Si-FET-based devices due to its large interface state density (D it ). Consequently, we propose, a multi-stacked amorphous HfO 2 /1-ML TiO 2 /SiO 2 IDM structure to realize a low D it and a wide memory window. Herein we describe the quasi-static and pulse response characteristics of multi-stacked IDM MOS capacitors and demonstrate flash-type and analog memory operations of an IDM FET device.

High density electronic circuit and process for making

DOEpatents

Morgan, William P.

1999-01-01

High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.

High-Responsivity Graphene-Boron Nitride Photodetector and Autocorrelator in a Silicon Photonic Integrated Circuit.

PubMed

Shiue, Ren-Jye; Gao, Yuanda; Wang, Yifei; Peng, Cheng; Robertson, Alexander D; Efetov, Dmitri K; Assefa, Solomon; Koppens, Frank H L; Hone, James; Englund, Dirk

2015-11-11

Graphene and other two-dimensional (2D) materials have emerged as promising materials for broadband and ultrafast photodetection and optical modulation. These optoelectronic capabilities can augment complementary metal-oxide-semiconductor (CMOS) devices for high-speed and low-power optical interconnects. Here, we demonstrate an on-chip ultrafast photodetector based on a two-dimensional heterostructure consisting of high-quality graphene encapsulated in hexagonal boron nitride. Coupled to the optical mode of a silicon waveguide, this 2D heterostructure-based photodetector exhibits a maximum responsivity of 0.36 A/W and high-speed operation with a 3 dB cutoff at 42 GHz. From photocurrent measurements as a function of the top-gate and source-drain voltages, we conclude that the photoresponse is consistent with hot electron mediated effects. At moderate peak powers above 50 mW, we observe a saturating photocurrent consistent with the mechanisms of electron-phonon supercollision cooling. This nonlinear photoresponse enables optical on-chip autocorrelation measurements with picosecond-scale timing resolution and exceptionally low peak powers.

Increasing security in inter-chip communication

DOE Office of Scientific and Technical Information (OSTI.GOV)

Edwards, Nathan J.; Hamlet, Jason; Bauer, Todd

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Increasing security in inter-chip communication

DOEpatents

Edwards, Nathan J; Hamlet, Jason; Bauer, Todd; Helinski, Ryan

2014-10-28

An apparatus for increasing security in inter-chip communication includes a sending control module, a communication bus, and a receiving control module. The communication bus is coupled between the sending control module and the receiving control module. The sending control module operates to send data on the communication bus, disable the communication bus when threats are detected, or both.

Orientation-selective aVLSI spiking neurons.

PubMed

Liu, S C; Kramer, J; Indiveri, G; Delbrück, T; Burg, T; Douglas, R

2001-01-01

We describe a programmable multi-chip VLSI neuronal system that can be used for exploring spike-based information processing models. The system consists of a silicon retina, a PIC microcontroller, and a transceiver chip whose integrate-and-fire neurons are connected in a soft winner-take-all architecture. The circuit on this multi-neuron chip approximates a cortical microcircuit. The neurons can be configured for different computational properties by the virtual connections of a selected set of pixels on the silicon retina. The virtual wiring between the different chips is effected by an event-driven communication protocol that uses asynchronous digital pulses, similar to spikes in a neuronal system. We used the multi-chip spike-based system to synthesize orientation-tuned neurons using both a feedforward model and a feedback model. The performance of our analog hardware spiking model matched the experimental observations and digital simulations of continuous-valued neurons. The multi-chip VLSI system has advantages over computer neuronal models in that it is real-time, and the computational time does not scale with the size of the neuronal network.

78 FR 24234 - Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same; Notice...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-24

... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-819] Certain Semiconductor Chips With DRAM Circuitry, and Modules and Products Containing Same; Notice of Request for Statements on the... order barring the entry of unlicensed DRAM semiconductor chips manufactured by Nanya Technology...

Distillation and detection of SO2 using a microfluidic chip.

PubMed

Ju, Wei-Jhong; Fu, Lung-Ming; Yang, Ruey-Jen; Lee, Chia-Lun

2012-02-07

A miniaturized distillation system is presented for separating sulfurous acid (H(2)SO(3)) into sulfur dioxide (SO(2)) and water (H(2)O). The major components of the proposed system include a microfluidic distillation chip, a power control module, and a carrier gas pressure control module. The microfluidic chip is patterned using a commercial CO(2) laser and comprises a serpentine channel, a heating zone, a buffer zone, a cooling zone, and a collection tank. In the proposed device, the H(2)SO(3) solution is injected into the microfluidic chip and is separated into SO(2) and H(2)O via an appropriate control of the distillation time and temperature. The gaseous SO(2) is then transported into the collection chamber by the carrier gas and is mixed with DI water. Finally, the SO(2) concentration is deduced from the absorbance measurements obtained using a spectrophotometer. The experimental results show that a correlation coefficient of R(2) = 0.9981 and a distillation efficiency as high as 94.6% are obtained for H(2)SO(3) solutions with SO(2) concentrations in the range of 100-500 ppm. The SO(2) concentrations of two commercial red wines are successfully detected using the developed device. Overall, the results presented in this study show that the proposed system provides a compact and reliable tool for SO(2) concentration measurement purposes.

Oxide-confined 2D VCSEL arrays for high-density inter/intra-chip interconnects

NASA Astrophysics Data System (ADS)

King, Roger; Michalzik, Rainer; Jung, Christian; Grabherr, Martin; Eberhard, Franz; Jaeger, Roland; Schnitzer, Peter; Ebeling, Karl J.

1998-04-01

We have designed and fabricated 4 X 8 vertical-cavity surface-emitting laser (VCSEL) arrays intended to be used as transmitters in short-distance parallel optical interconnects. In order to meet the requirements of 2D, high-speed optical links, each of the 32 laser diodes is supplied with two individual top contacts. The metallization scheme allows flip-chip mounting of the array modules junction-side down on silicon complementary metal oxide semiconductor (CMOS) chips. The optical and electrical characteristics across the arrays with device pitch of 250 micrometers are quite homogeneous. Arrays with 3 micrometers , 6 micrometers and 10 micrometers active diameter lasers have been investigated. The small devices show threshold currents of 600 (mu) A, single-mode output powers as high as 3 mW and maximum wavelength deviations of only 3 nm. The driving characteristics of all arrays are fully compatible to advanced 3.3 V CMOS technology. Using these arrays, we have measured small-signal modulation bandwidths exceeding 10 GHz and transmitted pseudo random data at 8 Gbit/s channel over 500 m graded index multimode fiber. This corresponds to a data transmission rate of 256 Gbit/s per array of 1 X 2 mm2 footprint area.

Chip-carrier thermal barrier and its impact on lateral thermal lens profile and beam parameter product in high power broad area lasers

NASA Astrophysics Data System (ADS)

Rieprich, J.; Winterfeldt, M.; Kernke, R.; Tomm, J. W.; Crump, P.

2018-03-01

High power broad area diode lasers with high optical power density in a small focus spot are in strong commercial demand. For this purpose, the beam quality, quantified via the beam parameter product (BPP), has to be improved. Previous studies have shown that the BPP is strongly affected by current-induced heating and the associated thermal lens formed within the laser stripe. However, the chip structure and module-assembly related factors that regulate the size and the shape of the thermal lens are not well known. An experimental infrared thermographic technique is used to quantify the thermal lens profile in diode lasers operating at an emission wavelength of 910 nm, and the results are compared with finite element method simulations. The analysis indicates that the measured thermal profiles can best be explained when a thermal barrier is introduced between the chip and the carrier, which is shown to have a substantial impact on the BPP and the thermal resistance. Comparable results are observed in further measurements of samples from multiple vendors, and the barrier is only observed for junction-down (p-down) mounting, consistent with the barrier being associated with the GaAs-metal transition.

A battery-free multichannel digital neural/EMG telemetry system for flying insects.

PubMed

Thomas, Stewart J; Harrison, Reid R; Leonardo, Anthony; Reynolds, Matthew S

2012-10-01

This paper presents a digital neural/EMG telemetry system small enough and lightweight enough to permit recording from insects in flight. It has a measured flight package mass of only 38 mg. This system includes a single-chip telemetry integrated circuit (IC) employing RF power harvesting for battery-free operation, with communication via modulated backscatter in the UHF (902-928 MHz) band. An on-chip 11-bit ADC digitizes 10 neural channels with a sampling rate of 26.1 kSps and 4 EMG channels at 1.63 kSps, and telemeters this data wirelessly to a base station. The companion base station transceiver includes an RF transmitter of +36 dBm (4 W) output power to wirelessly power the telemetry IC, and a digital receiver with a sensitivity of -70 dBm for 10⁻⁵ BER at 5.0 Mbps to receive the data stream from the telemetry IC. The telemetry chip was fabricated in a commercial 0.35 μ m 4M1P (4 metal, 1 poly) CMOS process. The die measures 2.36 × 1.88 mm, is 250 μm thick, and is wire bonded into a flex circuit assembly measuring 4.6 × 6.8 mm.

Wavelength locking of single emitters and multi-emitter modules: simulation and experiments

NASA Astrophysics Data System (ADS)

Yanson, Dan; Rappaport, Noam; Peleg, Ophir; Berk, Yuri; Dahan, Nir; Klumel, Genady; Baskin, Ilya; Levy, Moshe

2016-03-01

Wavelength-stabilized high-brightness single emitters are commonly used in fiber-coupled laser diode modules for pumping Yb-doped lasers at 976 nm, and Nd-doped ones at 808 nm. We investigate the spectral behavior of single emitters under wavelength-selective feedback from a volume Bragg (or hologram) grating (VBG) in a multi-emitter module. By integrating a full VBG model as a multi-layer thin film structure with commercial raytracing software, we simulated wavelength locking conditions as a function of beam divergence and angular alignment tolerances. Good correlation between the simulated VBG feedback strength and experimentally measured locking ranges, in both VBG misalignment angle and laser temperature, is demonstrated. The challenges of assembling multi-emitter modules based on beam-stacked optical architectures are specifically addressed, where the wavelength locking conditions must be achieved simultaneously with high fiber coupling efficiency for each emitter in the module. It is shown that angular misorientation between fast and slow-axis collimating optics can have a dramatic effect on the spectral and power performance of the module. We report the development of our NEON-S wavelength-stabilized fiber laser pump module, which uses a VBG to provide wavelength-selective optical feedback in the collimated portion of the beam. Powered by our purpose-developed high-brightness single emitters, the module delivers 47 W output at 11 A from an 0.15 NA fiber and a 0.3 nm linewidth at 976 nm. Preliminary wavelength-locking results at 808 nm are also presented.

Development of multichannel analyzer using sound card ADC for nuclear spectroscopy system

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ibrahim, Maslina Mohd; Yussup, Nolida; Lombigit, Lojius

This paper describes the development of Multi-Channel Analyzer (MCA) using sound card analogue to digital converter (ADC) for nuclear spectroscopy system. The system was divided into a hardware module and a software module. Hardware module consist of detector NaI (Tl) 2” by 2”, Pulse Shaping Amplifier (PSA) and a build in ADC chip from readily available in any computers’ sound system. The software module is divided into two parts which are a pre-processing of raw digital input and the development of the MCA software. Band-pass filter and baseline stabilization and correction were implemented for the pre-processing. For the MCA development,more » the pulse height analysis method was used to process the signal before displaying it using histogram technique. The development and tested result for using the sound card as an MCA are discussed.« less

Demonstration of multi-wavelength tunable fiber lasers based on a digital micromirror device processor.

PubMed

Ai, Qi; Chen, Xiao; Tian, Miao; Yan, Bin-bin; Zhang, Ying; Song, Fei-jun; Chen, Gen-xiang; Sang, Xin-zhu; Wang, Yi-quan; Xiao, Feng; Alameh, Kamal

2015-02-01

Based on a digital micromirror device (DMD) processor as the multi-wavelength narrow-band tunable filter, we demonstrate a multi-port tunable fiber laser through experiments. The key property of this laser is that any lasing wavelength channel from any arbitrary output port can be switched independently over the whole C-band, which is only driven by single DMD chip flexibly. All outputs display an excellent tuning capacity and high consistency in the whole C-band with a 0.02 nm linewidth, 0.055 nm wavelength tuning step, and side-mode suppression ratio greater than 60 dB. Due to the automatic power control and polarization design, the power uniformity of output lasers is less than 0.008 dB and the wavelength fluctuation is below 0.02 nm within 2 h at room temperature.

Towards an optofluidic pump?

NASA Astrophysics Data System (ADS)

Emile, Olivier; Emile, Janine

2016-12-01

Most of the vibrating mechanisms of optofluidic systems are based on local heating of membranes that induces liquid flow.We report here a new type of diaphragm pump in a liquid film based on the optical radiation pressure force. We modulate a low power laser that generates, at resonance, a symmetric vibration of a free standing soap film. The film lifetime strongly varies from 56 s at low power (2 mW) to 2 s at higher power (70 mW). Since the laser beam only acts mechanically on the interfaces, such a pump could be easily implemented on delicate microequipment on chips or in biological systems.

A deterministic guide for material and mode dependence of on-chip electro-optic modulator performance

NASA Astrophysics Data System (ADS)

Amin, Rubab; Suer, Can; Ma, Zhizhen; Sarpkaya, Ibrahim; Khurgin, Jacob B.; Agarwal, Ritesh; Sorger, Volker J.

2017-10-01

Electro-optic modulation is a key function in optical data communication and possible future optical computing engines. The performance of modulators intricately depends on the interaction between the actively modulated material and the propagating waveguide mode. While high-performing modulators were demonstrated before, the approaches were taken as ad-hoc. Here we show the first systematic investigation to incorporate a holistic analysis for high-performance and ultra-compact electro-optic modulators on-chip. We show that intricate interplay between active modulation material and optical mode plays a key role in the device operation. Based on physical tradeoffs such as index modulation, loss, optical confinement factors and slow-light effects, we find that bias-material-mode regions exist where high phase modulation and high loss (absorption) modulation is found. This work paves the way for a holistic design rule of electro-optic modulators for on-chip integration.

Thermo-mechanical behavior of power electronic packaging assemblies: From characterization to predictive simulation of lifetimes

NASA Astrophysics Data System (ADS)

Dalverny, O.; Alexis, J.

2018-02-01

This article deals with thermo-mechanical behavior of power electronic modules used in several transportation applications as railway, aeronautic or automotive systems. Due to a multi-layered structures, involving different materials with a large variation of coefficient of thermal expansion, temperature variations originated from active or passive cycling (respectively from die dissipation or environmental constraint) induces strain and stresses field variations, giving fatigue phenomenon of the system. The analysis of the behavior of these systems and their dimensioning require the implementation of complex modeling strategies by both the multi-physical and the multi-scale character of the power modules. In this paper we present some solutions for studying the thermomechanical behavior of brazed assemblies as well as taking into account the interfaces represented by the numerous metallizations involved in the process assembly.

Research on accuracy analysis of laser transmission system based on Zemax and Matlab

NASA Astrophysics Data System (ADS)

Chen, Haiping; Liu, Changchun; Ye, Haixian; Xiong, Zhao; Cao, Tingfen

2017-05-01

Laser transmission system is important in high power solid-state laser facilities and its function is to transfer and focus the light beam in accordance with the physical function of the facility. This system is mainly composed of transmission mirror modules and wedge lens module. In order to realize the precision alignment of the system, the precision alignment of the system is required to be decomposed into the allowable range of the calibration error of each module. The traditional method is to analyze the error factors of the modules separately, and then the linear synthesis is carried out, and the influence of the multi-module and multi-factor is obtained. In order to analyze the effect of the alignment error of each module on the beam center and focus more accurately, this paper aims to combine with the Monte Carlo random test and ray tracing, analyze influence of multi-module and multi-factor on the center of the beam, and evaluate and optimize the results of accuracy decomposition.

GaAs MMIC elements in phased-array antennas

NASA Technical Reports Server (NTRS)

Leonard, Regis F.

1988-01-01

Over the last six years NASA Lewis Research Center has carried out a program aimed at the development of advanced monolithic microwave integrated circuit technology, principally for use in phased-array antenna applications. Arising out of the Advanced Communications Technology Satellite (ACTS) program, the initial targets of the program were chips which operated at 30 and 20 GHz. Included in this group of activities were monolithic power modules with an output of 2 watts at GHz, variable phase shifters at both 20 and 30 GHz, low noise technology at 30 GHz, and a fully integrated (phase shifter, variable gain amplifier, power amplifier) transmit module at 20 GHz. Subsequent developments are centered on NASA mission requirements, particularly Space Station communications systems and deep space data communications.

Technology modules from micro- and nano-electronics for the life sciences.

PubMed

Birkholz, M; Mai, A; Wenger, C; Meliani, C; Scholz, R

2016-05-01

The capabilities of modern semiconductor manufacturing offer remarkable possibilities to be applied in life science research as well as for its commercialization. In this review, the technology modules available in micro- and nano-electronics are exemplarily presented for the case of 250 and 130 nm technology nodes. Preparation procedures and the different transistor types as available in complementary metal-oxide-silicon devices (CMOS) and BipolarCMOS (BiCMOS) technologies are introduced as key elements of comprehensive chip architectures. Techniques for circuit design and the elements of completely integrated bioelectronics systems are outlined. The possibility for life scientists to make use of these technology modules for their research and development projects via so-called multi-project wafer services is emphasized. Various examples from diverse fields such as (1) immobilization of biomolecules and cells on semiconductor surfaces, (2) biosensors operating by different principles such as affinity viscosimetry, impedance spectroscopy, and dielectrophoresis, (3) complete systems for human body implants and monitors for bioreactors, and (4) the combination of microelectronics with microfluidics either by chip-in-polymer integration as well as Si-based microfluidics are demonstrated from joint developments with partners from biotechnology and medicine. WIREs Nanomed Nanobiotechnol 2016, 8:355-377. doi: 10.1002/wnan.1367 For further resources related to this article, please visit the WIREs website. © 2015 Wiley Periodicals, Inc.

Research on Optical Transmitter and Receiver Module Used for High-Speed Interconnection between CPU and Memory

NASA Astrophysics Data System (ADS)

He, Huimin; Liu, Fengman; Li, Baoxia; Xue, Haiyun; Wang, Haidong; Qiu, Delong; Zhou, Yunyan; Cao, Liqiang

2016-11-01

With the development of the multicore processor, the bandwidth and capacity of the memory, rather than the memory area, are the key factors in server performance. At present, however, the new architectures, such as fully buffered DIMM (FBDIMM), hybrid memory cube (HMC), and high bandwidth memory (HBM), cannot be commercially applied in the server. Therefore, a new architecture for the server is proposed. CPU and memory are separated onto different boards, and optical interconnection is used for the communication between them. Each optical module corresponds to each dual inline memory module (DIMM) with 64 channels. Compared to the previous technology, not only can the architecture realize high-capacity and wide-bandwidth memory, it also can reduce power consumption and cost, and be compatible with the existing dynamic random access memory (DRAM). In this article, the proposed module with system-in-package (SiP) integration is demonstrated. In the optical module, the silicon photonic chip is included, which is a promising technology to be applied in the next-generation data exchanging centers. And due to the bandwidth-distance performance of the optical interconnection, SerDes chips are introduced to convert the 64-bit data at 800 Mbps from/to 4-channel data at 12.8 Gbps after/before they are transmitted though optical fiber. All the devices are packaged on cheap organic substrates. To ensure the performance of the whole system, several optimization efforts have been performed on the two modules. High-speed interconnection traces have been designed and simulated with electromagnetic simulation software. Steady-state thermal characteristics of the transceiver module have been evaluated by ANSYS APLD based on finite-element methodology (FEM). Heat sinks are placed at the hotspot area to ensure the reliability of all working chips. Finally, this transceiver system based on silicon photonics is measured, and the eye diagrams of data and clock signals are verified.

Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails

NASA Astrophysics Data System (ADS)

Hashida, Takushi; Nagata, Makoto

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100Mbps. A pair of transceivers consumes 1.35mA from 3.3V, at 130Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50dB.

Behavior of stress generated in semiconductor chips with high-temperature joints: Influence of mechanical properties of joint materials

NASA Astrophysics Data System (ADS)

Ito, H.; Kuwahara, M.; Ohta, R.; Usui, M.

2018-04-01

High-temperature joint materials are indispensable to realizing next-generation power modules with high-output performance. However, crack initiation resulting from stress concentration in semiconductor chips joined with high-temperature joint materials remains a critical problem in high-temperature operation. Therefore, clarifying the quantitative influence of joint materials on the stress generated in chips is essential. This study investigates the stress behavior of chips joined by Ni-Sn solid-liquid interdiffusion (SLID), which results in a high-temperature joint material likely to generate cracks after joining or when under thermal cycling. The results are compared with those fabricated using three types of solders, Pb-10%Sn, Sn-0.7%Cu, and Sn-10%Sb (mass %), which are conventional joint materials with different melting points and mechanical properties. Using Ni-Sn SLID results in the generation of high compressive stress (500 MPa) without stress relaxation after the joining process in contrast to the case of solders in which the compressive stresses are low (<300 MPa) and decrease to still lower levels (<250 MPa). In addition, no stress relaxation occurs during thermal cycling when using Ni-Sn SLID, whereas stress relaxation is clearly observed during heating to 200 °C using solders. Different stress behaviors between Ni-Sn SLID and other joint materials are illustrated by their mechanical strength and resistance against plastic and creep deformation. These results suggest that stress relaxation in a chip is key in suppressing crack initiation in highly reliable modules during high-temperature operation.

Improvement in reduced-mode (REM) diodes enable 315 W from 105-μm 0.15-NA fiber-coupled modules

NASA Astrophysics Data System (ADS)

Kanskar, M.; Bao, L.; Chen, Z.; Dawson, D.; DeVito, M.; Dong, W.; Grimshaw, M.; Guan, X.; Hemenway, M.; Martinsen, R.; Urbanek, W.; Zhang, S.

2018-02-01

High-power, high-brightness diode lasers have been pursued for many applications including fiber laser pumping, materials processing, solid-state laser pumping, and consumer electronics manufacturing. In particular, 915 nm - and 976 nm diodes are of interest as diode pumps for the kilowatt CW fiber lasers. As a result, there have been many technical thrusts for driving the diode lasers to have both high power and high brightness to achieve high-performance and reduced manufacturing costs. This paper presents our continued progress in the development of high brightness fiber-coupled product platform, nLIGHT element®. In the past decade, the power coupled into a single 105 μm and 0.15 NA fiber has increased by over a factor of ten through improved diode laser brightness and the development of techniques for efficiently coupling multiple emitters. In this paper, we demonstrate further brightness improvement and power-scaling enabled by both the rise in chip brightness/power and the increase in number of chips coupled into a given numerical aperture. We report a new chip technology using x-REM design with brightness as high as 4.3 W/mm-mrad at a BPP of 3 mm-mrad. We also report record 315 W output from a 2×12 nLIGHT element with 105 μm diameter fiber using x-REM diodes and these diodes will allow next generation of fiber-coupled product capable of 250W output power from 105 μm/0.15 NA beam at 915 nm.

A CMOS Self-Contained Quadrature Signal Generator for SoC Impedance Spectroscopy.

PubMed

Márquez, Alejandro; Pérez-Bailón, Jorge; Calvo, Belén; Medrano, Nicolás; Martínez, Pedro A

2018-04-30

This paper presents a low-power fully integrated quadrature signal generator for system-on-chip (SoC) impedance spectroscopy applications. It has been designed in a 0.18 μm-1.8 V CMOS technology as a self-contained oscillator, without the need for an external reference clock. The frequency can be digitally tuned from 10 to 345 kHz with 12-bit accuracy and a relative mean error below 1.7%, thus supporting a wide range of impedance sensing applications. The proposal is experimentally validated in two impedance spectrometry examples, achieving good magnitude and phase recovery results compared to the results obtained using a commercial LCR-meter. Besides the wide frequency tuning range, the proposed programmable oscillator features a total power consumption lower than 0.77 mW and an active area of 0.129 mm², thus constituting a highly suitable choice as stimulation module for instrument-on-a-chip devices.

Precision control of multiple quantum cascade lasers for calibration systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taubman, Matthew S., E-mail: Matthew.Taubman@pnnl.gov; Myers, Tanya L.; Pratt, Richard M.

We present a precision, 1-A, digitally interfaced current controller for quantum cascade lasers, with demonstrated temperature coefficients for continuous and 40-kHz full-depth square-wave modulated operation, of 1–2 ppm/ °C and 15 ppm/ °C, respectively. High precision digital to analog converters (DACs) together with an ultra-precision voltage reference produce highly stable, precision voltages, which are selected by a multiplexer (MUX) chip to set output currents via a linear current regulator. The controller is operated in conjunction with a power multiplexing unit, allowing one of three lasers to be driven by the controller, while ensuring protection of controller and all lasers during operation, standby,more » and switching. Simple ASCII commands sent over a USB connection to a microprocessor located in the current controller operate both the controller (via the DACs and MUX chip) and the power multiplexer.« less

Precision Control of Multiple Quantum Cascade Lasers for Calibration Systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Taubman, Matthew S.; Myers, Tanya L.; Pratt, Richard M.

We present a precision, digitally interfaced current controller for quantum cascade lasers, with demonstrated DC and modulated temperature coefficients of 1- 2 ppm/ºC and 15 ppm/ºC respectively. High linearity digital to analog converters (DACs) together with an ultra-precision voltage reference, produce highly stable, precision voltages. These are in turn selected by a low charge-injection multiplexer (MUX) chip, which are then used to set output currents via a linear current regulator. The controller is operated in conjunction with a power multiplexing unit, allowing one of three lasers to be driven by the controller while ensuring protection of controller and all lasersmore » during operation, standby and switching. Simple ASCII commands sent over a USB connection to a microprocessor located in the current controller operate both the controller (via the DACs and MUX chip) and the power multiplexer.« less

Maximizing Computational Capability with Minimal Power

DTIC Science & Technology

2009-03-01

Chip -Scale Energy and Power... and Heat Report Documentation Page Form ApprovedOMB No. 0704-0188 Public reporting burden for the collection of...OpticalBench Mounting Posts Imager Chip LCDinterfaced withthecomputer P o l a r i z e r P o l a r i z e r XYZ Translator Optical Slide VMM Computational Pixel...Signal routing power / memory: ? Power does not include comm off chip (i.e. accessing memory) Power = ½ C Vdd2 f for CMOS Chip to Chip (10pF load min

In-Situ Measurement of Power Loss for Crystalline Silicon Modules Undergoing Thermal Cycling and Mechanical Loading Stress Testing: Preprint

DOE Office of Scientific and Technical Information (OSTI.GOV)

Spataru, Sergiu; Hacke, Pater; Sera, Dezso

2015-09-15

We analyze the degradation of multi-crystalline silicon photovoltaic modules undergoing simultaneous thermal, mechanical, and humidity stress testing to develop a dark environmental chamber in-situ measurement procedure for determining module power loss. From the analysis we determine three main categories of failure modes associated with the module degradation consisting of: shunting, recombination losses, increased series resistance losses, and current mismatch losses associated with a decrease in photo-current generation by removal of some cell areas due to cell fractures. Based on the analysis, we propose an in-situ module power loss monitoring procedure that relies on dark current-voltage measurements taken during the stressmore » test, and initial and final module flash testing, to determine the power degradation characteristic of the module.« less

Multilevel photonic modules for millimeter-wave phased-array antennas

NASA Astrophysics Data System (ADS)

Paolella, Arthur C.; Bauerle, Athena; Joshi, Abhay M.; Wright, James G.; Coryell, Louis A.

2000-09-01

Millimeter wave phased array systems have antenna element sizes and spacings similar to MMIC chip dimensions by virtue of the operating wavelength. Designing modules in traditional planar packaing techniques are therefore difficult to implement. An advantageous way to maintain a small module footprint compatible with Ka-Band and high frequency systems is to take advantage of two leading edge technologies, opto- electronic integrated circuits (OEICs) and multilevel packaging technology. Under a Phase II SBIR these technologies are combined to form photonic modules for optically controlled millimeter wave phased array antennas. The proposed module, consisting of an OEIC integrated with a planar antenna array will operate on the 40GHz region. The OEIC consists of an InP based dual-depletion PIN photodetector and distributed amplifier. The multi-level module will be fabricated using an enhanced circuit processing thick film process. Since the modules are batch fabricated using an enhanced circuit processing thick film process. Since the modules are batch fabricated, using standard commercial processes, it has the potential to be low cost while maintaining high performance, impacting both military and commercial communications systems.

Universal lab-on-a-chip platform for complex, perfused 3D cell cultures

NASA Astrophysics Data System (ADS)

Sonntag, F.; Schmieder, F.; Ströbel, J.; Grünzner, S.; Busek, M.; Günther, K.; Steege, T.; Polk, C.; Klotzbach, U.

2016-03-01

The miniaturization, rapid prototyping and automation of lab-on-a-chip technology play nowadays a very important role. Lab-on-a-chip technology is successfully implemented not only for environmental analysis and medical diagnostics, but also as replacement of animals used for the testing of substances in the pharmaceutical and cosmetics industries. For that purpose the Fraunhofer IWS and partners developed a lab-on-a-chip platform for perfused cell-based assays in the last years, which includes different micropumps, valves, channels, reservoirs and customized cell culture modules. This technology is already implemented for the characterization of different human cell cultures and organoids, like skin, liver, endothelium, hair follicle and nephron. The advanced universal lab-on-a-chip platform for complex, perfused 3D cell cultures is divided into a multilayer basic chip with integrated micropump and application-specific 3D printed cell culture modules. Moreover a technology for surface modification of the printed cell culture modules by laser micro structuring and a complex and flexibly programmable controlling device based on an embedded Linux system was developed. A universal lab-on-a-chip platform with an optional oxygenator and a cell culture module for cubic scaffolds as well as first cell culture experiments within the cell culture device will be presented. The module is designed for direct interaction with robotic dispenser systems. This offers the opportunity to combine direct organ printing of cells and scaffolds with the microfluidic cell culture module. The characterization of the developed system was done by means of Micro-Particle Image Velocimetry (μPIV) and an optical oxygen measuring system.

Multi-reactor power system configurations for multimegawatt nuclear electric propulsion

NASA Technical Reports Server (NTRS)

George, Jeffrey A.

1991-01-01

A modular, multi-reactor power system and vehicle configuration for piloted nuclear electric propulsion (NEP) missions to Mars is presented. Such a design could provide enhanced system and mission reliability, allowing a comfortable safety margin for early manned flights, and would allow a range of piloted and cargo missions to be performed with a single power system design. Early use of common power modules for cargo missions would also provide progressive flight experience and validation of standardized systems for use in later piloted applications. System and mission analysis are presented to compare single and multi-reactor configurations for piloted Mars missions. A conceptual design for the Hydra modular multi-reactor NEP vehicle is presented.

Modulation and coding for throughput-efficient optical free-space links

NASA Technical Reports Server (NTRS)

Georghiades, Costas N.

1993-01-01

Optical direct-detection systems are currently being considered for some high-speed inter-satellite links, where data-rates of a few hundred megabits per second are evisioned under power and pulsewidth constraints. In this paper we investigate the capacity, cutoff-rate and error-probability performance of uncoded and trellis-coded systems for various modulation schemes and under various throughput and power constraints. Modulation schemes considered are on-off keying (OOK), pulse-position modulation (PPM), overlapping PPM (OPPM) and multi-pulse (combinatorial) PPM (MPPM).

Using Ant Colony Optimization for Routing in VLSI Chips

NASA Astrophysics Data System (ADS)

Arora, Tamanna; Moses, Melanie

2009-04-01

Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. A frequent problem in the design of such high performance and high density VLSI layouts is that of routing wires that connect such large numbers of components. Most wire-routing problems are computationally hard. The quality of any routing algorithm is judged by the extent to which it satisfies routing constraints and design objectives. Some of the broader design objectives include minimizing total routed wire length, and minimizing total capacitance induced in the chip, both of which serve to minimize power consumed by the chip. Ant Colony Optimization algorithms (ACO) provide a multi-agent framework for combinatorial optimization by combining memory, stochastic decision and strategies of collective and distributed learning by ant-like agents. This paper applies ACO to the NP-hard problem of finding optimal routes for interconnect routing on VLSI chips. The constraints on interconnect routing are used by ants as heuristics which guide their search process. We found that ACO algorithms were able to successfully incorporate multiple constraints and route interconnects on suite of benchmark chips. On an average, the algorithm routed with total wire length 5.5% less than other established routing algorithms.

High power diode lasers emitting from 639 nm to 690 nm

NASA Astrophysics Data System (ADS)

Bao, L.; Grimshaw, M.; DeVito, M.; Kanskar, M.; Dong, W.; Guan, X.; Zhang, S.; Patterson, J.; Dickerson, P.; Kennedy, K.; Li, S.; Haden, J.; Martinsen, R.

2014-03-01

There is increasing market demand for high power reliable red lasers for display and cinema applications. Due to the fundamental material system limit at this wavelength range, red diode lasers have lower efficiency and are more temperature sensitive, compared to 790-980 nm diode lasers. In terms of reliability, red lasers are also more sensitive to catastrophic optical mirror damage (COMD) due to the higher photon energy. Thus developing higher power-reliable red lasers is very challenging. This paper will present nLIGHT's released red products from 639 nm to 690nm, with established high performance and long-term reliability. These single emitter diode lasers can work as stand-alone singleemitter units or efficiently integrate into our compact, passively-cooled Pearl™ fiber-coupled module architectures for higher output power and improved reliability. In order to further improve power and reliability, new chip optimizations have been focused on improving epitaxial design/growth, chip configuration/processing and optical facet passivation. Initial optimization has demonstrated promising results for 639 nm diode lasers to be reliably rated at 1.5 W and 690nm diode lasers to be reliably rated at 4.0 W. Accelerated life-test has started and further design optimization are underway.

WDM mid-board optics for chip-to-chip wavelength routing interconnects in the H2020 ICT-STREAMS

NASA Astrophysics Data System (ADS)

Kanellos, G. T.; Pleros, N.

2017-02-01

Multi-socket server boards have emerged to increase the processing power density on the board level and further flatten the data center networks beyond leaf-spine architectures. Scaling however the number of processors per board puts current electronic technologies into challenge, as it requires high bandwidth interconnects and high throughput switches with increased number of ports that are currently unavailable. On-board optical interconnection has proved the potential to efficiently satisfy the bandwidth needs, but their use has been limited to parallel links without performing any smart routing functionality. With CWDM optical interconnects already a commodity, cyclical wavelength routing proposed to fit the datacom for rack-to-rack and board-to-board communication now becomes a promising on-board routing platform. ICT-STREAMS is a European research project that aims to combine WDM parallel on-board transceivers with a cyclical AWGR, in order to create a new board-level, chip-to-chip interconnection paradigm that will leverage WDM parallel transmission to a powerful wavelength routing platform capable to interconnect multiple processors with unprecedented bandwidth and throughput capacity. Direct, any-to-any, on-board interconnection of multiple processors will significantly contribute to further flatten the data centers and facilitate east-west communication. In the present communication, we present ICT-STREAMS on-board wavelength routing architecture for multiple chip-to-chip interconnections and evaluate the overall system performance in terms of throughput and latency for several schemes and traffic profiles. We also review recent advances of the ICT-STREAMS platform key-enabling technologies that span from Si in-plane lasers and polymer based electro-optical circuit boards to silicon photonics transceivers and photonic-crystal amplifiers.

65 nm LP/GP mix low cost platform for multi-media wireless and consumer applications

NASA Astrophysics Data System (ADS)

Tavel, B.; Duriez, B.; Gwoziecki, R.; Basso, M. T.; Julien, C.; Ortolland, C.; Laplanche, Y.; Fox, R.; Sabouret, E.; Detcheverry, C.; Boeuf, F.; Morin, P.; Barge, D.; Bidaud, M.; Biénacel, J.; Garnier, P.; Cooper, K.; Chapon, J. D.; Trouiller, Y.; Belledent, J.; Broekaart, M.; Gouraud, P.; Denais, M.; Huard, V.; Rochereau, K.; Difrenza, R.; Planes, N.; Marin, M.; Boret, S.; Gloria, D.; Vanbergue, S.; Abramowitz, P.; Vishnubhotla, L.; Reber, D.; Stolk, P.; Woo, M.; Arnaud, F.

2006-04-01

A complete 65 nm CMOS platform, called LP/GP Mix, has been developed employing thick oxide transistor (IO), Low Power (LP) and General Purpose (GP) devices on the same chip. Dedicated to wireless multi-media and consumer applications, this new triple gate oxide platform is low cost (+1mask only) and saves over 35% of dynamic power with the use of the low operating voltage GP. The LP/GP mix shows competitive digital performance with a ring oscillator (FO = 1) speed equal to 7 ps per stage (GP) and 6T-SRAM static power lower than 10 pA/cell (LP). Compatible with mixed-signal design requirements, transistors show high voltage gain, low mismatch factor and low flicker noise. Moreover, to address mobile phone demands, excellent RF performance has been achieved with FT = 160 GHz for LP and 280 GHz for GP nMOS transistors.

Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions

NASA Technical Reports Server (NTRS)

Samoska, Lorene; Chattopadhyay, Goutam; Pukala, David; Gaier, Todd; Soria, Mary; ManFung, King; Deal, William; Mei, Gerry; Radisic, Vesna; Lai, Richard

2009-01-01

To increase the usefulness of monolithic millimeter-wave integrated circuit (MMIC) components at submillimeter-wave frequencies, a chip has been designed that incorporates two integrated, radial E-plane probes with an MMIC amplifier in between, thus creating a fully integrated waveguide module. The integrated amplifier chip has been fabricated in 35-nm gate length InP high-electron-mobility-transistor (HEMT) technology. The radial probes were mated to grounded coplanar waveguide input and output lines in the internal amplifier. The total length of the internal HEMT amplifier is 550 m, while the total integrated chip length is 1,085 m. The chip thickness is 50 m with the chip width being 320 m. The internal MMIC amplifier is biased through wire-bond connections to the gates and drains of the chip. The chip has 3 stages, employing 35-nm gate length transistors in each stage. Wire bonds from the DC drain and gate pads are connected to off-chip shunt 51-pF capacitors, and additional off-chip capacitors and resistors are added to the gate and drain bias lines for low-frequency stability of the amplifier. Additionally, bond wires to the grounded coplanar waveguide pads at the RF input and output of the internal amplifier are added to ensure good ground connections to the waveguide package. The S-parameters of the module, not corrected for input or output waveguide loss, are measured at the waveguide flange edges. The amplifier module has over 10 dB of gain from 290 to 330 GHz, with a peak gain of over 14 dB at 307 GHz. The WR2.2 waveguide cutoff is again observed at 268 GHz. The module is biased at a drain current of 27 mA, a drain voltage of 1.24 V, and a gate voltage of +0.21 V. Return loss of the module is very good between 5 to 25 dB. This result illustrates the usefulness of the integrated radial probe transition, and the wide (over 10-percent) bandwidth that one can expect for amplifier modules with integrated radial probes in the submillimeter-regime (>300 GHz).

Evaluation of a Programmable Voltage-Controlled MEMS Oscillator, Type SiT3701, Over a Wide Temperature Range

NASA Technical Reports Server (NTRS)

Patterson, Richard; Hammoud, Ahmad

2009-01-01

Semiconductor chips based on MEMS (Micro-Electro-Mechanical Systems) technology, such as sensors, transducers, and actuators, are becoming widely used in today s electronics due to their high performance, low power consumption, tolerance to shock and vibration, and immunity to electro-static discharge. In addition, the MEMS fabrication process allows for the miniaturization of individual chips as well as the integration of various electronic circuits into one module, such as system-on-a-chip. These measures would simplify overall system design, reduce parts count and interface, improve reliability, and reduce cost; and they would meet requirements of systems destined for use in space exploration missions. In this work, the performance of a recently-developed MEMS voltage-controlled oscillator was evaluated under a wide temperature range. Operation of this new commercial-off-the-shelf (COTS) device was also assessed under thermal cycling to address some operational conditions of the space environment

A monolithic integrated photonic microwave filter

NASA Astrophysics Data System (ADS)

Fandiño, Javier S.; Muñoz, Pascual; Doménech, David; Capmany, José

2017-02-01

Meeting the increasing demand for capacity in wireless networks requires the harnessing of higher regions in the radiofrequency spectrum, reducing cell size, as well as more compact, agile and power-efficient base stations that are capable of smoothly interfacing the radio and fibre segments. Fully functional microwave photonic chips are promising candidates in attempts to meet these goals. In recent years, many integrated microwave photonic chips have been reported in different technologies. To the best of our knowledge, none has monolithically integrated all the main active and passive optoelectronic components. Here, we report the first demonstration of a tunable microwave photonics filter that is monolithically integrated into an indium phosphide chip. The reconfigurable radiofrequency photonic filter includes all the necessary elements (for example, lasers, modulators and photodetectors), and its response can be tuned by means of control electric currents. This is an important step in demonstrating the feasibility of integrated and programmable microwave photonic processors.

The realization of an SVGA OLED-on-silicon microdisplay driving circuit

NASA Astrophysics Data System (ADS)

Bohua, Zhao; Ran, Huang; Fei, Ma; Guohua, Xie; Zhensong, Zhang; Huan, Du; Jiajun, Luo; Yi, Zhao

2012-03-01

An 800 × 600 pixel organic light-emitting diode-on-silicon (OLEDoS) driving circuit is proposed. The pixel cell circuit utilizes a subthreshold-voltage-scaling structure which can modulate the pixel current between 170 pA and 11.4 nA. In order to keep the voltage of the column bus at a relatively high level, the sample-and-hold circuits adopt a ping-pong operation. The driving circuit is fabricated in a commercially available 0.35 μm two-poly four-metal 3.3 V mixed-signal CMOS process. The pixel cell area is 15 × 15 μm2 and the total chip occupies 15.5 × 12.3 mm2. Experimental results show that the chip can work properly at a frame frequency of 60 Hz and has a 64 grayscale (monochrome) display. The total power consumption of the chip is about 85 mW with a 3.3V supply voltage.

JPRS Report: Science & Technology - Europe.

DTIC Science & Technology

1992-12-21

in the aero- nautical industry—through the use of hybrids, ASICs [application-specific integrated circuits ], etc. "The system will also have an... Module ], the cylinder-shaped pressurized cabin that can be firmly attached to the international space station), which is to be launched in 1999...34] [Excerpt] Two hundred scientists and $1 billion to design the chip of the future, an integrated circuit (IC) giving microcomputers power

μOrgano: A Lego®-Like Plug & Play System for Modular Multi-Organ-Chips.

PubMed

Loskill, Peter; Marcus, Sivan G; Mathur, Anurag; Reese, Willie Mae; Healy, Kevin E

2015-01-01

Human organ-on-a-chip systems for drug screening have evolved as feasible alternatives to animal models, which are unreliable, expensive, and at times erroneous. While chips featuring single organs can be of great use for both pharmaceutical testing and basic organ-level studies, the huge potential of the organ-on-a-chip technology is revealed by connecting multiple organs on one chip to create a single integrated system for sophisticated fundamental biological studies and devising therapies for disease. Furthermore, since most organ-on-a-chip systems require special protocols with organ-specific media for the differentiation and maturation of the tissues, multi-organ systems will need to be temporally customizable and flexible in terms of the time point of connection of the individual organ units. We present a customizable Lego®-like plug & play system, μOrgano, which enables initial individual culture of single organ-on-a-chip systems and subsequent connection to create integrated multi-organ microphysiological systems. As a proof of concept, the μOrgano system was used to connect multiple heart chips in series with excellent cell viability and spontaneously physiological beat rates.

μOrgano: A Lego®-Like Plug & Play System for Modular Multi-Organ-Chips

PubMed Central

Loskill, Peter; Marcus, Sivan G.; Mathur, Anurag; Reese, Willie Mae; Healy, Kevin E.

2015-01-01

Human organ-on-a-chip systems for drug screening have evolved as feasible alternatives to animal models, which are unreliable, expensive, and at times erroneous. While chips featuring single organs can be of great use for both pharmaceutical testing and basic organ-level studies, the huge potential of the organ-on-a-chip technology is revealed by connecting multiple organs on one chip to create a single integrated system for sophisticated fundamental biological studies and devising therapies for disease. Furthermore, since most organ-on-a-chip systems require special protocols with organ-specific media for the differentiation and maturation of the tissues, multi-organ systems will need to be temporally customizable and flexible in terms of the time point of connection of the individual organ units. We present a customizable Lego®-like plug & play system, μOrgano, which enables initial individual culture of single organ-on-a-chip systems and subsequent connection to create integrated multi-organ microphysiological systems. As a proof of concept, the μOrgano system was used to connect multiple heart chips in series with excellent cell viability and spontaneously physiological beat rates. PMID:26440672

Six-port optical switch for cluster-mesh photonic network-on-chip

NASA Astrophysics Data System (ADS)

Jia, Hao; Zhou, Ting; Zhao, Yunchou; Xia, Yuhao; Dai, Jincheng; Zhang, Lei; Ding, Jianfeng; Fu, Xin; Yang, Lin

2018-05-01

Photonic network-on-chip for high-performance multi-core processors has attracted substantial interest in recent years as it offers a systematic method to meet the demand of large bandwidth, low latency and low power dissipation. In this paper we demonstrate a non-blocking six-port optical switch for cluster-mesh photonic network-on-chip. The architecture is constructed by substituting three optical switching units of typical Spanke-Benes network to optical waveguide crossings. Compared with Spanke-Benes network, the number of optical switching units is reduced by 20%, while the connectivity of routing path is maintained. By this way the footprint and power consumption can be reduced at the expense of sacrificing the network latency performance in some cases. The device is realized by 12 thermally tuned silicon Mach-Zehnder optical switching units. Its theoretical spectral responses are evaluated by establishing a numerical model. The experimental spectral responses are also characterized, which indicates that the optical signal-to-noise ratios of the optical switch are larger than 13.5 dB in the wavelength range from 1525 nm to 1565 nm. Data transmission experiment with the data rate of 32 Gbps is implemented for each optical link.

Label-free silicon photonic biosensor system with integrated detector array.

PubMed

Yan, Rongjin; Mestas, Santano P; Yuan, Guangwei; Safaisini, Rashid; Dandy, David S; Lear, Kevin L

2009-08-07

An integrated, inexpensive, label-free photonic waveguide biosensor system with multi-analyte capability has been implemented on a silicon photonics integrated circuit from a commercial CMOS line and tested with nanofilms. The local evanescent array coupled (LEAC) biosensor is based on a new physical phenomenon that is fundamentally different from the mechanisms of other evanescent field sensors. Increased local refractive index at the waveguide's upper surface due to the formation of a biological nanofilm causes local modulation of the evanescent field coupled into an array of photodetectors buried under the waveguide. The planar optical waveguide biosensor system exhibits sensitivity of 20%/nm photocurrent modulation in response to adsorbed bovine serum albumin (BSA) layers less than 3 nm thick. In addition to response to BSA, an experiment with patterned photoresist as well as beam propagation method simulations support the evanescent field shift principle. The sensing mechanism enables the integration of all optical and electronic components for a multi-analyte biosensor system on a chip.

Label-free silicon photonic biosensor system with integrated detector array

PubMed Central

Yan, Rongjin; Mestas, Santano P.; Yuan, Guangwei; Safaisini, Rashid; Dandy, David S.

2010-01-01

An integrated, inexpensive, label-free photonic waveguide biosensor system with multi-analyte capability has been implemented on a silicon photonics integrated circuit from a commercial CMOS line and tested with nanofilms. The local evanescent array coupled (LEAC) biosensor is based on a new physical phenomenon that is fundamentally different from the mechanisms of other evanescent field sensors. Increased local refractive index at the waveguide’s upper surface due to the formation of a biological nanofilm causes local modulation of the evanescent field coupled into an array of photodetectors buried under the waveguide. The planar optical waveguide biosensor system exhibits sensitivity of 20%/nm photocurrent modulation in response to adsorbed bovine serum albumin (BSA) layers less than 3 nm thick. In addition to response to BSA, an experiment with patterned photoresist as well as beam propagation method simulations support the evanescent field shift principle. The sensing mechanism enables the integration of all optical and electronic components for a multi-analyte biosensor system on a chip. PMID:19606292

Space platform power system hardware testbed

NASA Technical Reports Server (NTRS)

Sable, D.; Patil, A.; Sizemore, T.; Deuty, S.; Noon, J.; Cho, B. H.; Lee, F. C.

1991-01-01

The scope of the work on the NASA Space Platform includes the design of a multi-module, multi-phase boost regulator, and a voltage-fed, push-pull autotransformer converter for the battery discharger. A buck converter was designed for the charge regulator. Also included is the associated mode control electronics for the charger and discharger, as well as continued development of a comprehensive modeling and simulation tool for the system. The design of the multi-module boost converter is discussed for use as a battery discharger. An alternative battery discharger design is discussed using a voltage-fed, push-pull autotransformer converter. The design of the charge regulator is explained using a simple buck converter. The design of the mode controller and effects of locating the bus filter capacitor bank 20 feet away from the power ORU are discussed. A brief discussion of some alternative topologies for battery charging and discharging is included. The power system modeling is described.

Ultrahigh-speed Si-integrated on-chip laser with tailored dynamic characteristics

NASA Astrophysics Data System (ADS)

Park, Gyeong Cheol; Xue, Weiqi; Piels, Molly; Zibar, Darko; Mørk, Jesper; Semenova, Elizaveta; Chung, Il-Sug

2016-12-01

For on-chip interconnects, an ideal light source should have an ultralow energy consumption per bandwidth (operating en-ergy) as well as sufficient output power for error-free detection. Nanocavity lasers have been considered the most ideal for smaller operating energy. However, they have a challenge in obtaining a sufficient output power. Here, as an alternative, we propose an ultrahigh-speed microcavity laser structure, based on a vertical cavity with a high-contrast grating (HCG) mirror for transverse magnetic (TM) polarisation. By using the TM HCG, a very small mode volume and an un-pumped compact optical feedback structure can be realised, which together tailor the frequency response function for achieving a very high speed at low injection currents. Furthermore, light can be emitted laterally into a Si waveguide. From an 1.54-μm optically-pumped laser, a 3-dB frequency of 27 GHz was obtained at a pumping level corresponding to sub-mA. Using measured 3-dB frequen-cies and calculated equivalent currents, the modulation current efficiency factor (MCEF) is estimated to be 42.1 GHz/mA1/2, which is superior among microcavity lasers. This shows a high potential for a very high speed at low injection currents or avery small heat generation at high bitrates, which are highly desirable for both on-chip and off-chip applications.

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

NASA Technical Reports Server (NTRS)

Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

1994-01-01

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

DESIGN NOTE: Microcontroller-based multi-sensor apparatus for temperature control and thermal conductivity measurement

NASA Astrophysics Data System (ADS)

Mukaro, R.; Gasseller, M.; Kufazvinei, C.; Olumekor, L.; Taele, B. M.

2003-08-01

A microcontroller-based multi-sensor temperature measurement and control system that uses a steady-state one-dimensional heat-flow technique for absolute determination of thermal conductivity of a rigid poor conductor using the guarded hot-plate method is described. The objective of this project was to utilize the latest powerful, yet inexpensive, technological developments, sensors, data acquisition and control system, computer and application software, for research and teaching by example. The system uses an ST6220 microcontroller and LM335 temperature sensors for temperature measurement and control. The instrument interfaces to a computer via the serial port using a Turbo C++ programme. LM335Z silicon semiconductor temperature sensors located at different axial locations in the heat source were calibrated and used to measure temperature in the range from room temperature (about 293 K) to 373 K. A zero and span circuit was used in conjunction with an eight-to-one-line data multiplexer to scale the LM335 output signals to fit the 0 5.0 V full-scale input of the microcontroller's on-chip ADC and to sequentially measure temperature at the different locations. Temperature control is achieved by using software-generated pulse-width-modulated signals that control power to the heater. This article emphasizes the apparatus's instrumentation, the computerized data acquisition design, operation and demonstration of the system as a purposeful measurement system that could be easily adopted for use in the undergraduate laboratory. Measurements on a 10 mm thick sample of polyurethane foam at different temperature gradients gave a thermal conductivity of 0.026 +/- 0.004 W m-1 K-1.

Protein–Protein Interactions Modulate the Docking-Dependent E3-Ubiquitin Ligase Activity of Carboxy-Terminus of Hsc70-Interacting Protein (CHIP)*

PubMed Central

Narayan, Vikram; Landré, Vivien; Ning, Jia; Hernychova, Lenka; Muller, Petr; Verma, Chandra; Walkinshaw, Malcolm D.; Blackburn, Elizabeth A.; Ball, Kathryn L.

2015-01-01

CHIP is a tetratricopeptide repeat (TPR) domain protein that functions as an E3-ubiquitin ligase. As well as linking the molecular chaperones to the ubiquitin proteasome system, CHIP also has a docking-dependent mode where it ubiquitinates native substrates, thereby regulating their steady state levels and/or function. Here we explore the effect of Hsp70 on the docking-dependent E3-ligase activity of CHIP. The TPR-domain is revealed as a binding site for allosteric modulators involved in determining CHIP's dynamic conformation and activity. Biochemical, biophysical and modeling evidence demonstrate that Hsp70-binding to the TPR, or Hsp70-mimetic mutations, regulate CHIP-mediated ubiquitination of p53 and IRF-1 through effects on U-box activity and substrate binding. HDX-MS was used to establish that conformational-inhibition-signals extended from the TPR-domain to the U-box. This underscores inter-domain allosteric regulation of CHIP by the core molecular chaperones. Defining the chaperone-associated TPR-domain of CHIP as a manager of inter-domain communication highlights the potential for scaffolding modules to regulate, as well as assemble, complexes that are fundamental to protein homeostatic control. PMID:26330542

Neuromorphic VLSI vision system for real-time texture segregation.

PubMed

Shimonomura, Kazuhiro; Yagi, Tetsuya

2008-10-01

The visual system of the brain can perceive an external scene in real-time with extremely low power dissipation, although the response speed of an individual neuron is considerably lower than that of semiconductor devices. The neurons in the visual pathway generate their receptive fields using a parallel and hierarchical architecture. This architecture of the visual cortex is interesting and important for designing a novel perception system from an engineering perspective. The aim of this study is to develop a vision system hardware, which is designed inspired by a hierarchical visual processing in V1, for real time texture segregation. The system consists of a silicon retina, orientation chip, and field programmable gate array (FPGA) circuit. The silicon retina emulates the neural circuits of the vertebrate retina and exhibits a Laplacian-Gaussian-like receptive field. The orientation chip selectively aggregates multiple pixels of the silicon retina in order to produce Gabor-like receptive fields that are tuned to various orientations by mimicking the feed-forward model proposed by Hubel and Wiesel. The FPGA circuit receives the output of the orientation chip and computes the responses of the complex cells. Using this system, the neural images of simple cells were computed in real-time for various orientations and spatial frequencies. Using the orientation-selective outputs obtained from the multi-chip system, a real-time texture segregation was conducted based on a computational model inspired by psychophysics and neurophysiology. The texture image was filtered by the two orthogonally oriented receptive fields of the multi-chip system and the filtered images were combined to segregate the area of different texture orientation with the aid of FPGA. The present system is also useful for the investigation of the functions of the higher-order cells that can be obtained by combining the simple and complex cells.

Multi-Kilowatt Power Module for High-Power Hall Thrusters

NASA Technical Reports Server (NTRS)

Pinero, Luis R.; Bowers, Glen E.

2005-01-01

Future NASA missions will require high-performance electric propulsion systems. Hall thrusters are being developed at NASA Glenn for high-power, high-specific impulse operation. These thrusters operate at power levels up to 50 kW of power and discharge voltages in excess of 600 V. A parallel effort is being conducted to develop power electronics for these thrusters that push the technology beyond the 5kW state-of-the-art power level. A 10 kW power module was designed to produce an output of 500 V and 20 A from a nominal 100 V input. Resistive load tests revealed efficiencies in excess of 96 percent. Load current share and phase synchronization circuits were designed and tested that will allow connecting multiple modules in parallel to process higher power.

Flip-chip replacement within the constraints imposed by multilayer ceramic (MLC) modules

NASA Astrophysics Data System (ADS)

Puttlitz, Karl J.

1984-01-01

Economics often dictates that suitable module rework procedures be established to replace solder bump devices (flip chips) reflowed to multichip carriers. These operations are complicated, owing to various constraints such as the substrate's physical and mechanical properties, close proximity of surface features, etc. This paper describes the constraints and the methods to circumvent them. An order of preference based upon the degree of constraint is recommended to achieve device removal and subsequent site dress of the residual solder left on the substrate. It has been determined that rework (device replacement) can be successfully achieved in even highly constricted situations. This is illustrated by the example of utilizing a localized heating technique, hot gas, to remove solder from microsockets from which chips were previously removed. Microsockets are areas to which chips are reflowed to the top surface of IBM's densely populated multilayer ceramic (MLC) modules, thus forming the so-called controlled collapse chip connection or C-4. The microsocket patterns are thus identical to the chip footprint.

Backside illuminated CMOS-TDI line scanner for space applications

NASA Astrophysics Data System (ADS)

Cohen, O.; Ben-Ari, N.; Nevo, I.; Shiloah, N.; Zohar, G.; Kahanov, E.; Brumer, M.; Gershon, G.; Ofer, O.

2017-09-01

A new multi-spectral line scanner CMOS image sensor is reported. The backside illuminated (BSI) image sensor was designed for continuous scanning Low Earth Orbit (LEO) space applications including A custom high quality CMOS Active Pixels, Time Delayed Integration (TDI) mechanism that increases the SNR, 2-phase exposure mechanism that increases the dynamic Modulation Transfer Function (MTF), very low power internal Analog to Digital Converters (ADC) with resolution of 12 bit per pixel and on chip controller. The sensor has 4 independent arrays of pixels where each array is arranged in 2600 TDI columns with controllable TDI depth from 8 up to 64 TDI levels. A multispectral optical filter with specific spectral response per array is assembled at the package level. In this paper we briefly describe the sensor design and present some electrical and electro-optical recent measurements of the first prototypes including high Quantum Efficiency (QE), high MTF, wide range selectable Full Well Capacity (FWC), excellent linearity of approximately 1.3% in a signal range of 5-85% and approximately 1.75% in a signal range of 2-95% out of the signal span, readout noise of approximately 95 electrons with 64 TDI levels, negligible dark current and power consumption of less than 1.5W total for 4 bands sensor at all operation conditions .

Low energy CMOS for space applications

NASA Technical Reports Server (NTRS)

Panwar, Ramesh; Alkalaj, Leon

1992-01-01

The current focus of NASA's space flight programs reflects a new thrust towards smaller, less costly, and more frequent space missions, when compared to missions such as Galileo, Magellan, or Cassini. Recently, the concept of a microspacecraft was proposed. In this concept, a small, compact spacecraft that weighs tens of kilograms performs focused scientific objectives such as imaging. Similarly, a Mars Lander micro-rover project is under study that will allow miniature robots weighing less than seven kilograms to explore the Martian surface. To bring the microspacecraft and microrover ideas to fruition, one will have to leverage compact 3D multi-chip module-based multiprocessors (MCM) technologies. Low energy CMOS will become increasingly important because of the thermodynamic considerations in cooling compact 3D MCM implementations and also from considerations of the power budget for space applications. In this paper, we show how the operating voltage is related to the threshold voltage of the CMOS transistors for accomplishing a task in VLSI with minimal energy. We also derive expressions for the noise margins at the optimal operating point. We then look at a low voltage CMOS (LVCMOS) technology developed at Stanford University which improves the power consumption over conventional CMOS by a couple of orders of magnitude and consider the suitability of the technology for space applications by characterizing its SEU immunity.

High density electronic circuit and process for making

DOEpatents

Morgan, W.P.

1999-06-29

High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.

Multi-kilowatt modularized spacecraft power processing system development

NASA Technical Reports Server (NTRS)

Andrews, R. E.; Hayden, J. H.; Hedges, R. T.; Rehmann, D. W.

1975-01-01

A review of existing information pertaining to spacecraft power processing systems and equipment was accomplished with a view towards applicability to the modularization of multi-kilowatt power processors. Power requirements for future spacecraft were determined from the NASA mission model-shuttle systems payload data study which provided the limits for modular power equipment capabilities. Three power processing systems were compared to evaluation criteria to select the system best suited for modularity. The shunt regulated direct energy transfer system was selected by this analysis for a conceptual design effort which produced equipment specifications, schematics, envelope drawings, and power module configurations.

A Low Power IoT Sensor Node Architecture for Waste Management Within Smart Cities Context.

PubMed

Cerchecci, Matteo; Luti, Francesco; Mecocci, Alessandro; Parrino, Stefano; Peruzzi, Giacomo; Pozzebon, Alessandro

2018-04-21

This paper focuses on the realization of an Internet of Things (IoT) architecture to optimize waste management in the context of Smart Cities. In particular, a novel typology of sensor node based on the use of low cost and low power components is described. This node is provided with a single-chip microcontroller, a sensor able to measure the filling level of trash bins using ultrasounds and a data transmission module based on the LoRa LPWAN (Low Power Wide Area Network) technology. Together with the node, a minimal network architecture was designed, based on a LoRa gateway, with the purpose of testing the IoT node performances. Especially, the paper analyzes in detail the node architecture, focusing on the energy saving technologies and policies, with the purpose of extending the batteries lifetime by reducing power consumption, through hardware and software optimization. Tests on sensor and radio module effectiveness are also presented.

A Low Power IoT Sensor Node Architecture for Waste Management Within Smart Cities Context

PubMed Central

Cerchecci, Matteo; Luti, Francesco; Mecocci, Alessandro; Parrino, Stefano; Peruzzi, Giacomo

2018-01-01

This paper focuses on the realization of an Internet of Things (IoT) architecture to optimize waste management in the context of Smart Cities. In particular, a novel typology of sensor node based on the use of low cost and low power components is described. This node is provided with a single-chip microcontroller, a sensor able to measure the filling level of trash bins using ultrasounds and a data transmission module based on the LoRa LPWAN (Low Power Wide Area Network) technology. Together with the node, a minimal network architecture was designed, based on a LoRa gateway, with the purpose of testing the IoT node performances. Especially, the paper analyzes in detail the node architecture, focusing on the energy saving technologies and policies, with the purpose of extending the batteries lifetime by reducing power consumption, through hardware and software optimization. Tests on sensor and radio module effectiveness are also presented. PMID:29690552

LDQ10: a compact ultra low-power radiation-hard 4 × 10 Gb/s driver array

DOE PAGES

Zeng, Z.; Zhang, T.; Wang, G.; ...

2017-02-28

Here, a High-speed and low-power VCSEL driver is an important component of the Versatile Link for the high-luminosity LHC (HL-LHC) experiments. A compact low-power radiation-hard 4 × 10 Gb/s VCSEL driver array (LDQ10) has been developed in 65 nm CMOS technology. Each channel in LDQ10 can provide a modulation current up to 8 mA and bias current up to 12 mA. Edge pre-emphasis is employed to compensate for the bandwidth limitations due to parasitic and the turn-on delay of VCSEL devices. LDQ10 occupies a chip area of 1900 μm × 1700 μm and consumes 130 mW power for typical currentmore » settings. The modulation amplitude degrades less than 5% after 300 Mrad total ionizing dose. LDQ10 can be directly wire-bonded to the VCSEL array and it is a suitable candidate for the Versatile Link.« less

Miniaturized module for the wireless transmission of measurements with Bluetooth.

PubMed

Roth, H; Schwaibold, M; Moor, C; Schöchlin, J; Bolz, A

2002-01-01

The wiring of patients for obtaining medical measurements has many disadvantages. In order to limit these, a miniaturized module was developed which digitalizes analog signals and sends the signal wirelessly to the receiver using Bluetooth. Bluetooth is especially suitable for this application because distances of up to 10 m are possible with low power consumption and robust transmission with encryption. The module consists of a Bluetooth chip, which is initialized in such a way by a microcontroller that connections from other bluetooth receivers can be accepted. The signals are then transmitted to the distant end. The maximum bit rate of the 23 mm x 30 mm module is 73.5 kBit/s. At 4.7 kBit/s, the current consumption is 12 mA.

On-chip integratable all-optical quantizer using strong cross-phase modulation in a silicon-organic hybrid slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Sang, Xinzhu; Wang, Kuiru; Wu, Qiang; Yan, Binbin; Li, Feng; Zhou, Xian; Zhong, Kangping; Zhou, Guiyao; Yu, Chongxiu; Farrell, Gerald; Lu, Chao; Yaw Tam, Hwa; Wai, P. K. A.

2016-01-01

High performance all-optical quantizer based on silicon waveguide is believed to have significant applications in photonic integratable optical communication links, optical interconnection networks, and real-time signal processing systems. In this paper, we propose an integratable all-optical quantizer for on-chip and low power consumption all-optical analog-to-digital converters. The quantization is realized by the strong cross-phase modulation and interference in a silicon-organic hybrid (SOH) slot waveguide based Mach-Zehnder interferometer. By carefully designing the dimension of the SOH waveguide, large nonlinear coefficients up to 16,000 and 18,069 W−1/m for the pump and probe signals can be obtained respectively, along with a low pulse walk-off parameter of 66.7 fs/mm, and all-normal dispersion in the wavelength regime considered. Simulation results show that the phase shift of the probe signal can reach 8π at a low pump pulse peak power of 206 mW and propagation length of 5 mm such that a 4-bit all-optical quantizer can be realized. The corresponding signal-to-noise ratio is 23.42 dB and effective number of bit is 3.89-bit. PMID:26777054

High-Responsivity Graphene–Boron Nitride Photodetector and Autocorrelator in a Silicon Photonic Integrated Circuit

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shiue, Ren-Jye; Gao, Yuanda; Wang, Yifei

2015-11-11

Graphene and other two-dimensional (2D) materials have emerged as promising materials for broadband and ultrafast photodetection and optical modulation. These optoelectronic capabilities can augment complementary metal–oxide–semiconductor (CMOS) devices for high-speed and low-power optical interconnects. Here, we demonstrate an on-chip ultrafast photodetector based on a two-dimensional heterostructure consisting of high-quality graphene encapsulated in hexagonal boron nitride. Coupled to the optical mode of a silicon waveguide, this 2D heterostructure-based photodetector exhibits a maximum responsivity of 0.36 A/W and high-speed operation with a 3 dB cutoff at 42 GHz. From photocurrent measurements as a function of the top-gate and source-drain voltages, we concludemore » that the photoresponse is consistent with hot electron mediated effects. At moderate peak powers above 50 mW, we observe a saturating photocurrent consistent with the mechanisms of electron–phonon supercollision cooling. This nonlinear photoresponse enables optical on-chip autocorrelation measurements with picosecond-scale timing resolution and exceptionally low peak powers.« less

Multi-element germanium detectors for synchrotron applications

DOE PAGES

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.; ...

2018-04-27

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

Multi-element germanium detectors for synchrotron applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Rumaiz, A. K.; Kuczewski, A. J.; Mead, J.

In this paper, we have developed a series of monolithic multi-element germanium detectors, based on sensor arrays produced by the Forschungzentrum Julich, and on Application-specific integrated circuits (ASICs) developed at Brookhaven. Devices have been made with element counts ranging from 64 to 384. These detectors are being used at NSLS-II and APS for a range of diffraction experiments, both monochromatic and energy-dispersive. Compact and powerful readout systems have been developed, based on the new generation of FPGA system-on-chip devices, which provide closely coupled multi-core processors embedded in large gate arrays. Finally, we will discuss the technical details of the systems,more » and present some of the results from them.« less

The all-optical modulator in dielectric-loaded waveguide with graphene-silicon heterojunction structure

NASA Astrophysics Data System (ADS)

Sun, Feiying; Xia, Liangping; Nie, Changbin; Shen, Jun; Zou, Yixuan; Cheng, Guiyu; Wu, Hao; Zhang, Yong; Wei, Dongshan; Yin, Shaoyun; Du, Chunlei

2018-04-01

All-optical modulators based on graphene show great promise for on-chip optical interconnects. However, the modulation performance of all-optical modulators is usually based on the interaction between graphene and the fiber, limiting their potential in high integration. Based on this point, an all-optical modulator in a dielectric-loaded waveguide (DLW) with a graphene-silicon heterojunction structure (GSH) is proposed. The DLW raises the waveguide mode, which provides a strong light-graphene interaction. Sufficient tuning of the graphene Fermi energy beyond the Pauli blocking effect is obtained with the presented GSH structure. Under the modulation light with a wavelength of 532 nm and a power of 60 mW, a modulation efficiency of 0.0275 dB µm-1 is achieved for light with a communication wavelength of 1.55 µm in the experiment. This modulator has the advantage of having a compact footprint, which may make it a candidate for achieving a highly integrated all-optical modulator.

A multi-year survey of stem-end chip defect in chipping potatoes (Solanum tuberosum L.)

USDA-ARS?s Scientific Manuscript database

One of the most serious tuber quality concerns of US chip potato growers is stem-end chip defect, which is defined as a localized post-fry discoloration in and adjacent to the vasculature on the stem end portion of potato chips. The incidence and severity of stem-end chip defect vary with growing lo...

Remote multi-function fire alarm system based on internet of things

NASA Astrophysics Data System (ADS)

Wang, Lihui; Zhao, Shuai; Huang, Jianqing; Ji, Jianyu

2018-05-01

This project uses MCU STC15W408AS (stable, energy saving, high speed), temperature sensor DS18B20 (cheap, high efficiency, stable), MQ2 resistance type semiconductor smog sensor (high stability, fast response and economy) and NRF24L01 wireless transmitting and receiving module (energy saving, small volume, reliable) as the main body to achieve concentration temperature data presentation, intelligent voice alarming and short distance wireless transmission. The whole system is safe, reliable, cheap, quick reaction and good performance. This project uses the MCU STM32F103RCT6 as the main control chip, and use WIFI module ESP8266, wireless module NRF24L01 to make the gateway. Users can remotely check and control the related devices in real-time on smartphones or computers. We can also realize the functions of intelligent fire monitoring, remote fire extinguishing, cloud data storage through the third party server Big IOT.

3D Printing and Assay Development for Point-of-Care Applications

NASA Astrophysics Data System (ADS)

Jagadeesh, Shreesha

Existing centralized labs do not serve patients adequately in remote areas. To enable universal timely healthcare, there is a need to develop low cost, portable systems that can diagnose multiple disease (Point-of-Care (POC) devices). Future POC diagnostics can be more multi-functional if medical device vendors can develop interoperability standards. This thesis developed the following medical diagnostic modules: Plasma from 25 microl blood was extracted through a filter membrane to demonstrate a 3D printed sample preparation module. Sepsis biomarker, C - reactive protein, was quantified through adsorption on nylon beads to demonstrate bead-based assay suitable for 3D printed disposable cartridge module. Finally, a modular fluorescent detection kit was built using 3D printed parts to detect CD4 cells in a disposable cartridge from ChipCare Corp. Due to the modularity enabled by 3D printing technique, the developed units can be easily adapted to detect other diseases.

Flexible manufacturing for photonics device assembly

NASA Technical Reports Server (NTRS)

Lu, Shin-Yee; Pocha, Michael D.; Strand, Oliver T.; Young, K. David

1994-01-01

The assembly of photonics devices such as laser diodes, optical modulators, and opto-electronics multi-chip modules (OEMCM), usually requires the placement of micron size devices such as laser diodes, and sub-micron precision attachment between optical fibers and diodes or waveguide modulators (usually referred to as pigtailing). This is a very labor intensive process. Studies done by the opto-electronics (OE) industry have shown that 95 percent of the cost of a pigtailed photonic device is due to the use of manual alignment and bonding techniques, which is the current practice in industry. At Lawrence Livermore National Laboratory, we are working to reduce the cost of packaging OE devices through the use of automation. Our efforts are concentrated on several areas that are directly related to an automated process. This paper will focus on our progress in two of those areas, in particular, an automated fiber pigtailing machine and silicon micro-technology compatible with an automated process.

Design and Performance of a Miniature Radar L-Band Transceiver

NASA Technical Reports Server (NTRS)

McWatters, D.; Price, D.; Edelstein, W.

2004-01-01

Radar electronics developed for past JPL space missions historically had been custom designed and as such, given budgetary, time, and risk constraints, had not been optimized for maximum flexibility or miniaturization. To help reduce cost and risk of future radar missions, a generic radar module was conceived. The module includes a 1.25-GHz (L-band) transceiver and incorporates miniature high-density packaging of integrated circuits in die/chip form. The technology challenges include overcoming the effect of miniaturization and high packaging density to achieve the performance, reliability, and environmental ruggedness required for space missions. The module was chosen to have representative (generic) functionality most likely required from an L-band radar. For very large aperture phased-array spaceborne radar missions, the large dimensions of the array suggest the benefit of distributing the radar electronics into the antenna array. For such applications, this technology is essential in order to bring down the cost, mass, and power of the radar electronics module replicated in each panel of the array. For smaller sized arrays, a single module can be combined with the central radar controller and still provide the bene.ts of configuration .exibility, low power, and low mass. We present the design approach for the radar electronics module and the test results for its radio frequency (RF) portion: a miniature, low-power, radiation-hard L-band transceiver.

Trellis phase codes for power-bandwith efficient satellite communications

NASA Technical Reports Server (NTRS)

Wilson, S. G.; Highfill, J. H.; Hsu, C. D.; Harkness, R.

1981-01-01

Support work on improved power and spectrum utilization on digital satellite channels was performed. Specific attention is given to the class of signalling schemes known as continuous phase modulation (CPM). The specific work described in this report addresses: analytical bounds on error probability for multi-h phase codes, power and bandwidth characterization of 4-ary multi-h codes, and initial results of channel simulation to assess the impact of band limiting filters and nonlinear amplifiers on CPM performance.

Micromechanical Switches on GaAs for Microwave Applications

NASA Technical Reports Server (NTRS)

Randall, John N.; Goldsmith, Chuck; Denniston, David; Lin, Tsen-Hwang

1995-01-01

In this presentation, we describe the fabrication of micro-electro-mechanical system (MEMS) devices, in particular, of low-frequency multi-element electrical switches using SiO2 cantilevers. The switches discussed are related to micromechanical membrane structures used to perform switching of optical signals on silicon substrates. These switches use a thin metal membrane which is actuated by an electrostatic potential, causing the switch to make or break contact. The advantages include: superior isolation, high power handling capabilities, high radiation hardening, very low power operations, and the ability to integrate onto GaAs monolithic microwave integrated circuit (MMIC) chips.

Test scheduling optimization for 3D network-on-chip based on cloud evolutionary algorithm of Pareto multi-objective

NASA Astrophysics Data System (ADS)

Xu, Chuanpei; Niu, Junhao; Ling, Jing; Wang, Suyan

2018-03-01

In this paper, we present a parallel test strategy for bandwidth division multiplexing under the test access mechanism bandwidth constraint. The Pareto solution set is combined with a cloud evolutionary algorithm to optimize the test time and power consumption of a three-dimensional network-on-chip (3D NoC). In the proposed method, all individuals in the population are sorted in non-dominated order and allocated to the corresponding level. Individuals with extreme and similar characteristics are then removed. To increase the diversity of the population and prevent the algorithm from becoming stuck around local optima, a competition strategy is designed for the individuals. Finally, we adopt an elite reservation strategy and update the individuals according to the cloud model. Experimental results show that the proposed algorithm converges to the optimal Pareto solution set rapidly and accurately. This not only obtains the shortest test time, but also optimizes the power consumption of the 3D NoC.

Low Noise Titanium Nitride KIDs for SuperSpec: A Millimeter-Wave On-Chip Spectrometer

NASA Astrophysics Data System (ADS)

Hailey-Dunsheath, S.; Shirokoff, E.; Barry, P. S.; Bradford, C. M.; Chapman, S.; Che, G.; Glenn, J.; Hollister, M.; Kovács, A.; LeDuc, H. G.; Mauskopf, P.; McKenney, C.; O'Brient, R.; Padin, S.; Reck, T.; Shiu, C.; Tucker, C. E.; Wheeler, J.; Williamson, R.; Zmuidzinas, J.

2016-07-01

SuperSpec is a novel on-chip spectrometer we are developing for multi-object, moderate resolution (R = 100-500), large bandwidth ({˜ }1.65:1), submillimeter and millimeter survey spectroscopy of high-redshift galaxies. The spectrometer employs a filter bank architecture, and consists of a series of half-wave resonators formed by lithographically-patterned superconducting transmission lines. The signal power admitted by each resonator is detected by a lumped element titanium nitride (TiN) kinetic inductance detector operating at 100-200 MHz. We have tested a new prototype device that achieves the targeted R=100 resolving power, and has better detector sensitivity and optical efficiency than previous devices. We employ a new method for measuring photon noise using both coherent and thermal sources of radiation to cleanly separate the contributions of shot and wave noise. We report an upper limit to the detector NEP of 1.4× 10^{-17} W Hz^{-1/2}, within 10 % of the photon noise-limited NEP for a ground-based R=100 spectrometer.

Thermal Hotspots in CPU Die and It's Future Architecture

NASA Astrophysics Data System (ADS)

Wang, Jian; Hu, Fu-Yuan

Owing to the increasing core frequency and chip integration and the limited die dimension, the power densities in CPU chip have been increasing fastly. The high temperature on chip resulted by power densities threats the processor's performance and chip's reliability. This paper analyzed the thermal hotspots in die and their properties. A new architecture of function units in die - - hot units distributed architecture is suggested to cope with the problems of high power densities for future processor chip.

Universal sensor interface module (USIM)

NASA Astrophysics Data System (ADS)

King, Don; Torres, A.; Wynn, John

1999-01-01

A universal sensor interface model (USIM) is being developed by the Raytheon-TI Systems Company for use with fields of unattended distributed sensors. In its production configuration, the USIM will be a multichip module consisting of a set of common modules. The common module USIM set consists of (1) a sensor adapter interface (SAI) module, (2) digital signal processor (DSP) and associated memory module, and (3) a RF transceiver model. The multispectral sensor interface is designed around a low-power A/D converted, whose input/output interface consists of: -8 buffered, sampled inputs from various devices including environmental, acoustic seismic and magnetic sensors. The eight sensor inputs are each high-impedance, low- capacitance, differential amplifiers. The inputs are ideally suited for interface with discrete or MEMS sensors, since the differential input will allow direct connection with high-impedance bridge sensors and capacitance voltage sources. Each amplifier is connected to a 22-bit (Delta) (Sigma) A/D converter to enable simultaneous samples. The low power (Delta) (Sigma) converter provides 22-bit resolution at sample frequencies up to 142 hertz (used for magnetic sensors) and 16-bit resolution at frequencies up to 1168 hertz (used for acoustic and seismic sensors). The video interface module is based around the TMS320C5410 DSP. It can provide sensor array addressing, video data input, data calibration and correction. The processor module is based upon a MPC555. It will be used for mode control, synchronization of complex sensors, sensor signal processing, array processing, target classification and tracking. Many functions of the A/D, DSP and transceiver can be powered down by using variable clock speeds under software command or chip power switches. They can be returned to intermediate or full operation by DSP command. Power management may be based on the USIM's internal timer, command from the USIM transceiver, or by sleep mode processing management. The low power detection mode is implemented by monitoring any of the sensor analog outputs at lower sample rates for detection over a software controllable threshold.

Circulating polymerase chain reaction chips utilizing multiple-membrane activation

NASA Astrophysics Data System (ADS)

Wang, Chih-Hao; Chen, Yi-Yu; Liao, Chia-Sheng; Hsieh, Tsung-Min; Luo, Ching-Hsing; Wu, Jiunn-Jong; Lee, Huei-Huang; Lee, Gwo-Bin

2007-02-01

This paper reports a new micromachined, circulating, polymerase chain reaction (PCR) chip for nucleic acid amplification. The PCR chip is comprised of a microthermal control module and a polydimethylsiloxane (PDMS)-based microfluidic control module. The microthermal control modules are formed with three individual heating and temperature-sensing sections, each modulating a specific set temperature for denaturation, annealing and extension processes, respectively. Micro-pneumatic valves and multiple-membrane activations are used to form the microfluidic control module to transport sample fluids through three reaction regions. Compared with other PCR chips, the new chip is more compact in size, requires less time for heating and cooling processes, and has the capability to randomly adjust time ratios and cycle numbers depending on the PCR process. Experimental results showed that detection genes for two pathogens, Streptococcus pyogenes (S. pyogenes, 777 bps) and Streptococcus pneumoniae (S. pneumoniae, 273 bps), can be successfully amplified using the new circulating PCR chip. The minimum number of thermal cycles to amplify the DNA-based S. pyogenes for slab gel electrophoresis is 20 cycles with an initial concentration of 42.5 pg µl-1. Experimental data also revealed that a high reproducibility up to 98% could be achieved if the initial template concentration of the S. pyogenes was higher than 4 pg µl-1. The preliminary results of the current paper were presented at the 19th IEEE International Conference on Micro Electro Mechanical Systems (IEEE MEMS 2006), Istanbul, Turkey, 22-26 January, 2006.

Advanced system on a chip microelectronics for spacecraft and science instruments

NASA Astrophysics Data System (ADS)

Paschalidis, Nikolaos P.

2003-01-01

The explosive growth of the modern microelectronics field opens new horizons for the development of new lightweight, low power, and smart spacecraft and science instrumentation systems in the new millennium explorations. Although this growth is mostly driven by the commercial need for low power, portable and computationally intensive products, the applicability is obvious in the space sector. The additional difficulties needed to be overcome for applicability in space include radiation hardness for total ionizing dose and single event effects (SEE), and reliability. Additionally, this new capability introduces a whole new philosophy of design and R&D, with strong implications in organizational and inter-agency program management. One key component specifically developed towards low power, small size, highly autonomous spacecraft systems, is the smart sensor remote input/output (TRIO) chip. TRIO can interface to 32 transducers with current sources/sinks and voltage sensing. It includes front-end analog signal processing, a 10-bit ADC, memory, and standard serial and parallel I/Os. These functions are very useful for spacecraft and subsystems health and status monitoring, and control actions. The key contributions of the TRIO are feasibility of modular architectures, elimination of several miles of wire harnessing, and power savings by orders of magnitude. TRIO freely operates from a single power supply 2.5- 5.5 V with power dissipation <10 mW. This system on a chip device rapidly becomes a NASA and Commercial Space standard as it is already selected by thousands in several new millennium missions, including Europa Orbiter, Mars Surveyor Program, Solar Probe, Pluto Express, Stereo, Contour, Messenger, etc. In the Science Instrumentation field common instruments that can greatly take advantage of the new technologies are: energetic-particle/plasma and wave instruments, imagers, mass spectrometers, X-ray and UV spectrographs, magnetometers, laser rangefinding instruments, etc. Common measurements that apply to many of these instruments are precise time interval measurement and high resolution read-out of solid state detectors. A precise time interval measurement chip was specially developed that achieves ˜100 ps (×10 improvement) time resolution at a power dissipation ˜20 mW (×50 improvement), dead time ˜1.5 μs (×20 improvement), and chip die size 5 mm×5 mm versus two 20 cm×20 cm doubled sided boards. This device is selected as a key enabling technology for several NASA particle, delay line imaging, and laser range finding instruments onboard (NASA Image, Messenger, etc. missions). Another device with universal application is radiation energy read-out from solid state detectors. Multi-channel low-power and end-to-end sensor input—digital output is key for the new generation instruments. The readout channel comprises of a Charge Sensitive Preamplifier with a target sensitivity of ˜1 KeV FWHM at 20 pf detector capacitance, a Shaper Amplifier with programmable time constant/gain, and an ADC. The read-out chip together with the precise time interval chip comprises the essential elements of a common particle spectroscopy instrument. To mention some more applications fast-signal acquisition—and digitization is a very useful function for a category of instrument such as mass spectroscopy and profile laser rangefinding. The single chip approach includes a high bandwidth preamplifier, fast sampling ˜5 ns, analog memory ˜10K locations, 12-bit ADC and serial/parallel I/Os. The wealth of the applications proves the advanced microelectronics field as a key enabling technology for the new millennium space exploration.

Packaging and testing of multi-wavelength DFB laser array using REC technology

NASA Astrophysics Data System (ADS)

Ni, Yi; Kong, Xuan; Gu, Xiaofeng; Chen, Xiangfei; Zheng, Guanghui; Luan, Jia

2014-02-01

Packaging of distributed feedback (DFB) laser array based on reconstruction-equivalent-chirp (REC) technology is a bridge from chip to system, and influences the practical process of REC chip. In this paper, DFB laser arrays of 4-channel @1310 nm and 8-channel @1550 nm are packaged. Our experimental results show that both these laser arrays have uniform wavelength spacing and larger than 35 dB average Side Mode Suppression Ratio (SMSR). When I=35 mA, we obtain the total output power of 1 mW for 4-channel @1310 nm, and 227 μw for 8-channel @1550 nm respectively. The high frequency characteristics of the packaged chips are also obtained, and the requirements for 4×10 G or even 8×10 G systems can be reached. Our results demonstrate the practical and low cost performance of REC technology and indicate its potential in the future fiber-to-the-home (FTTH) application.

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems

PubMed Central

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G.; Blaauw, David; Dutta, Prabal

2015-01-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized—yet reusable—components with an interconnect that permits tiny, ultra-low power systems. In contrast to today’s interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus, a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two “shoot-through” rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient’s power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus’s feature set. PMID:26855555

MBus: An Ultra-Low Power Interconnect Bus for Next Generation Nanopower Systems.

PubMed

Pannuto, Pat; Lee, Yoonmyung; Kuo, Ye-Sheng; Foo, ZhiYoong; Kempke, Benjamin; Kim, Gyouho; Dreslinski, Ronald G; Blaauw, David; Dutta, Prabal

2015-06-01

As we show in this paper, I/O has become the limiting factor in scaling down size and power toward the goal of invisible computing. Achieving this goal will require composing optimized and specialized-yet reusable-components with an interconnect that permits tiny, ultra-low power systems. In contrast to today's interconnects which are limited by power-hungry pull-ups or high-overhead chip-select lines, our approach provides a superset of common bus features but at lower power, with fixed area and pin count, using fully synthesizable logic, and with surprisingly low protocol overhead. We present MBus , a new 4-pin, 22.6 pJ/bit/chip chip-to-chip interconnect made of two "shoot-through" rings. MBus facilitates ultra-low power system operation by implementing automatic power-gating of each chip in the system, easing the integration of active, inactive, and activating circuits on a single die. In addition, we introduce a new bus primitive: power oblivious communication, which guarantees message reception regardless of the recipient's power state when a message is sent. This disentangles power management from communication, greatly simplifying the creation of viable, modular, and heterogeneous systems that operate on the order of nanowatts. To evaluate the viability, power, performance, overhead, and scalability of our design, we build both hardware and software implementations of MBus and show its seamless operation across two FPGAs and twelve custom chips from three different semiconductor processes. A three-chip, 2.2 mm 3 MBus system draws 8 nW of total system standby power and uses only 22.6 pJ/bit/chip for communication. This is the lowest power for any system bus with MBus's feature set.

Architectured Materials to Improve the Reliability of Power Electronics Modules: Substrate and Lead-Free Solder

NASA Astrophysics Data System (ADS)

Kaabi, Abderrahmen; Bienvenu, Yves; Ryckelynck, David; Pierre, Bertrand

2014-03-01

Power electronics modules (>100 A, >500 V) are essential components for the development of electrical and hybrid vehicles. These modules are formed from silicon chips (transistors and diodes) assembled on copper substrates by soldering. Owing to the fact that the assembly is heterogeneous, and because of thermal gradients, shear stresses are generated in the solders and cause premature damage to such electronics modules. This work focuses on architectured materials for the substrate and on lead-free solders to reduce the mechanical effects of differential expansion, improve the reliability of the assembly, and achieve a suitable operating temperature (<175°C). These materials are composites whose thermomechanical properties have been optimized by numerical simulation and validated experimentally. The substrates have good thermal conductivity (>280 W m-1 K-1) and a macroscopic coefficient of thermal expansion intermediate between those of Cu and Si, as well as limited structural evolution in service conditions. An approach combining design, optimization, and manufacturing of new materials has been followed in this study, leading to improved thermal cycling behavior of the component.

Nanomechanical silicon resonators with intrinsic tunable gain and sub-nW power consumption.

PubMed

Bartsch, Sebastian T; Lovera, Andrea; Grogg, Daniel; Ionescu, Adrian M

2012-01-24

Nanoelectromechanical systems (NEMS) as integrated components for ultrasensitive sensing, time keeping, or radio frequency applications have driven the search for scalable nanomechanical transduction on-chip. Here, we present a hybrid silicon-on-insulator platform for building NEM oscillators in which fin field effect transistors (FinFETs) are integrated into nanomechanical silicon resonators. We demonstrate transistor amplification and signal mixing, coupled with mechanical motion at very high frequencies (25-80 MHz). By operating the transistor in the subthreshold region, the power consumption of resonators can be reduced to record-low nW levels, opening the way for the parallel operation of hundreds of thousands of NEM oscillators. The electromechanical charge modulation due to the field effect in a resonant transistor body constitutes a scalable nanomechanical motion detection all-on-chip and at room temperature. The new class of tunable NEMS represents a major step toward their integration in resonator arrays for applications in sensing and signal processing. © 2011 American Chemical Society

Whole-Cell Electrical Activity Under Direct Mechanical Stimulus by AFM Cantilever Using Planar Patch Clamp Chip Approach

PubMed Central

Upadhye, Kalpesh V.; Candiello, Joseph E.; Davidson, Lance A.; Lin, Hai

2011-01-01

Patch clamp is a powerful tool for studying the properties of ion-channels and cellular membrane. In recent years, planar patch clamp chips have been fabricated from various materials including glass, quartz, silicon, silicon nitride, polydimethyl-siloxane (PDMS), and silicon dioxide. Planar patch clamps have made automation of patch clamp recordings possible. However, most planar patch clamp chips have limitations when used in combination with other techniques. Furthermore, the fabrication methods used are often expensive and require specialized equipments. An improved design as well as fabrication and characterization of a silicon-based planar patch clamp chip are described in this report. Fabrication involves true batch fabrication processes that can be performed in most common microfabrication facilities using well established MEMS techniques. Our planar patch clamp chips can form giga-ohm seals with the cell plasma membrane with success rate comparable to existing patch clamp techniques. The chip permits whole-cell voltage clamp recordings on variety of cell types including Chinese Hamster Ovary (CHO) cells and pheochromocytoma (PC12) cells, for times longer than most available patch clamp chips. When combined with a custom microfluidics chamber, we demonstrate that it is possible to perfuse the extra-cellular as well as intra-cellular buffers. The chamber design allows integration of planar patch clamp with atomic force microscope (AFM). Using our planar patch clamp chip and microfluidics chamber, we have recorded whole-cell mechanosensitive (MS) currents produced by directly stimulating human keratinocyte (HaCaT) cells using an AFM cantilever. Our results reveal the spatial distribution of MS ion channels and temporal details of the responses from MS channels. The results show that planar patch clamp chips have great potential for multi-parametric high throughput studies of ion channel proteins. PMID:22174731

A New Clinical HIFU System (Teleson II)

NASA Astrophysics Data System (ADS)

Ma, Yixin; Symonds-Tayler, Richard; Rivens, Ian H.; ter Haar, Gail R.

2007-05-01

Previous clinical trials with our first prototype HIFU system (Teleson I) for the treatment of liver tumors, demonstrated a major challenge to be treatment of those tumors located behind the ribs. We have designed a new multi-element transducer for rib sparing. Initial simulation and experimental results (using a single channel power amplifier) are very encouraging. A new clinical HIFU system which can drive the multi-element transducer and control each channel independently is being designed and constructed. This second version of a clinical prototype HIFU system consists of a 3D motorised gantry, a multi-channel signal generator, a multi-channel power amplifier, a user interface PC, an embedded controller and auxiliary circuits for real-time interleaving/synchronization control and a to-be-implemented safety monitoring and data logging unit. For multi-element transducers, each element can be individually switched on and off for rib sparing, and phase and amplitude modulated for potential phased array applications. The multi-channel power amplifier can be switched on/off very rapidly at required intervals to interleave with ultrasound B-Scan imaging for HIFU monitoring or radiation force elastography imaging via a dedicated interleaving/timing module. The gantry movement can also be synchronised with power amplifier on/off and phase/amplitude updating for lesion generation under a wide variety of conditions including single lesions, lesion arrays and lesions "tracks" created whilst translating the active transducer. Results from testing the system using excised tissue will be presented.

Low-cost optical interconnect module for parallel optical data links

NASA Astrophysics Data System (ADS)

Noddings, Chad; Hirsch, Tom J.; Olla, M.; Spooner, C.; Yu, Jason J.

1995-04-01

We have designed, fabricated, and tested a prototype parallel ten-channel unidirectional optical data link. When scaled to production, we project that this technology will satisfy the following market penetration requirements: (1) up to 70 meters transmission distance, (2) at least 1 gigabyte/second data rate, and (3) 0.35 to 0.50 MByte/second volume selling price. These goals can be achieved by means of the assembly innovations described in this paper: a novel alignment method that is integrated with low-cost, few chip module packaging techniques, yielding high coupling and reducing the component count. Furthermore, high coupling efficiency increases projected reliability reducing the driver's power requirements.

Bypass diode integration

NASA Technical Reports Server (NTRS)

Shepard, N. F., Jr.

1981-01-01

Protective bypass diodes and mounting configurations which are applicable for use with photovoltaic modules having power dissipation requirements in the 5 to 50 watt range were investigated. Using PN silicon and Schottky diode characterization data on packaged diodes and diode chips, typical diodes were selected as representative for each range of current carrying capacity, an appropriate heat dissipating mounting concept along with its environmental enclosure was defined, and a thermal analysis relating junction temperature as a function of power dissipation was performed. In addition, the heat dissipating mounting device dimensions were varied to determine the effect on junction temperature. The results of the analysis are presented as a set of curves indicating junction temperature as a function of power dissipation for each diode package.

Optimized holographic femtosecond laser patterning method towards rapid integration of high-quality functional devices in microchannels.

PubMed

Zhang, Chenchu; Hu, Yanlei; Du, Wenqiang; Wu, Peichao; Rao, Shenglong; Cai, Ze; Lao, Zhaoxin; Xu, Bing; Ni, Jincheng; Li, Jiawen; Zhao, Gang; Wu, Dong; Chu, Jiaru; Sugioka, Koji

2016-09-13

Rapid integration of high-quality functional devices in microchannels is in highly demand for miniature lab-on-a-chip applications. This paper demonstrates the embellishment of existing microfluidic devices with integrated micropatterns via femtosecond laser MRAF-based holographic patterning (MHP) microfabrication, which proves two-photon polymerization (TPP) based on spatial light modulator (SLM) to be a rapid and powerful technology for chip functionalization. Optimized mixed region amplitude freedom (MRAF) algorithm has been used to generate high-quality shaped focus field. Base on the optimized parameters, a single-exposure approach is developed to fabricate 200 × 200 μm microstructure arrays in less than 240 ms. Moreover, microtraps, QR code and letters are integrated into a microdevice by the advanced method for particles capture and device identification. These results indicate that such a holographic laser embellishment of microfluidic devices is simple, flexible and easy to access, which has great potential in lab-on-a-chip applications of biological culture, chemical analyses and optofluidic devices.

Optimized holographic femtosecond laser patterning method towards rapid integration of high-quality functional devices in microchannels

NASA Astrophysics Data System (ADS)

Zhang, Chenchu; Hu, Yanlei; Du, Wenqiang; Wu, Peichao; Rao, Shenglong; Cai, Ze; Lao, Zhaoxin; Xu, Bing; Ni, Jincheng; Li, Jiawen; Zhao, Gang; Wu, Dong; Chu, Jiaru; Sugioka, Koji

2016-09-01

Rapid integration of high-quality functional devices in microchannels is in highly demand for miniature lab-on-a-chip applications. This paper demonstrates the embellishment of existing microfluidic devices with integrated micropatterns via femtosecond laser MRAF-based holographic patterning (MHP) microfabrication, which proves two-photon polymerization (TPP) based on spatial light modulator (SLM) to be a rapid and powerful technology for chip functionalization. Optimized mixed region amplitude freedom (MRAF) algorithm has been used to generate high-quality shaped focus field. Base on the optimized parameters, a single-exposure approach is developed to fabricate 200 × 200 μm microstructure arrays in less than 240 ms. Moreover, microtraps, QR code and letters are integrated into a microdevice by the advanced method for particles capture and device identification. These results indicate that such a holographic laser embellishment of microfluidic devices is simple, flexible and easy to access, which has great potential in lab-on-a-chip applications of biological culture, chemical analyses and optofluidic devices.

Integrated on-chip inductors with electroplated magnetic yokes (invited)

NASA Astrophysics Data System (ADS)

Wang, Naigang; O'Sullivan, Eugene J.; Herget, Philipp; Rajendran, Bipin; Krupp, Leslie E.; Romankiw, Lubomyr T.; Webb, Bucknell C.; Fontana, Robert; Duch, Elizabeth A.; Joseph, Eric A.; Brown, Stephen L.; Hu, Xiaolin; Decad, Gary M.; Sturcken, Noah; Shepard, Kenneth L.; Gallagher, William J.

2012-04-01

Thin-film ferromagnetic inductors show great potential as the energy storage element for integrated circuits containing on-chip power management. In order to achieve the high energy storage required for power management, on-chip inductors require relatively thick magnetic yoke materials (several microns or more), which can be readily deposited by electroplating through a photoresist mask as demonstrated in this paper, the yoke material of choice being Ni45Fe55, whose properties of relatively high moment and electrical resistivity make it an attractive model yoke material for inductors. Inductors were designed with a variety of yoke geometries, and included both single-turn and multi-turn coil designs, which were fabricated on 200 mm silicon wafers in a CMOS back-end-of-line (BEOL) facility. Each inductor consisted of electroplated copper coils enclosed by the electroplated Ni45Fe55 yokes; aspects of the fabrication of the inductors are discussed. Magnetic properties of the electroplated yoke materials are described, including high frequency permeability measurements. The inductance of 2-turn coil inductors, for example, was enhanced up to about 6 times over the air core equivalent, with an inductance density of 130 nH/mm2 being achieved. The resistance of these non-laminated inductors was relatively large at high frequency due to magnetic and eddy current losses but is expected to improve as the yoke material/structure is further optimized, making electroplated yoke-containing inductors attractive for dc-dc power converters.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

PubMed

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

PubMed Central

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-01-01

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

Partition resampling and extrapolation averaging: approximation methods for quantifying gene expression in large numbers of short oligonucleotide arrays.

PubMed

Goldstein, Darlene R

2006-10-01

Studies of gene expression using high-density short oligonucleotide arrays have become a standard in a variety of biological contexts. Of the expression measures that have been proposed to quantify expression in these arrays, multi-chip-based measures have been shown to perform well. As gene expression studies increase in size, however, utilizing multi-chip expression measures is more challenging in terms of computing memory requirements and time. A strategic alternative to exact multi-chip quantification on a full large chip set is to approximate expression values based on subsets of chips. This paper introduces an extrapolation method, Extrapolation Averaging (EA), and a resampling method, Partition Resampling (PR), to approximate expression in large studies. An examination of properties indicates that subset-based methods can perform well compared with exact expression quantification. The focus is on short oligonucleotide chips, but the same ideas apply equally well to any array type for which expression is quantified using an entire set of arrays, rather than for only a single array at a time. Software implementing Partition Resampling and Extrapolation Averaging is under development as an R package for the BioConductor project.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kapusta, P.; Kisielewski, B.

In this paper the overvoltage protection modules (OVP) for the power supply (PS) system of the Belle II pixel detector (PXD) are described. The aim of the OVP is to protect the detector and associated electronics against overvoltage conditions. Most critical in the system are voltages supplying the front-end ASICs. The PXD detector consists of the DEPFET sensor modules with integrated chips like the Drain Current Digitizer, the Switcher and the Data Handling Processor. These chips, implemented in modern sub-micron technologies, are quite vulnerable to variations in the supply voltages. The PXD will be placed in the Belle II experimentmore » as close as possible to the interaction point, where access during experiment is very limited or even impossible, thus the PS and OVP systems exploit the remote-sensing method. Overvoltage conditions are due to failures of the PS itself, wrong setting of the output voltages or transient voltages coming out of hard noisy environment of the experiment. The OVP modules are parts of the PS modules. For powering the PXD 40 PS modules are placed 15 m outside the Belle II spectrometer. Each one is equipped with the OVP board. All voltages (22) are grouped in 4 domains: Analog, Digital, Steering and Gate which have independent grounds. The OVP boards are designed from integrated circuits from Linear Technology. All configurations were simulated with the Spice program. The control electronics is designed in a Xilinx CPLD. Two types of integrated circuits were used. LT4356 surge stopper protects loads from high voltage transients. The output voltages are limited to a safe value and also protect loads against over current faults. For less critical voltages, the LTC2912 voltage monitors are used that detect under-voltage and overvoltage events. It has to be noted that the OVP system is working independently of any other protection of the PS system, which increases its overall reliability. (authors)« less

Low-power, transparent optical network interface for high bandwidth off-chip interconnects.

PubMed

Liboiron-Ladouceur, Odile; Wang, Howard; Garg, Ajay S; Bergman, Keren

2009-04-13

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Wireless Power Transfer for Autonomous Wearable Neurotransmitter Sensors.

PubMed

Nguyen, Cuong M; Kota, Pavan Kumar; Nguyen, Minh Q; Dubey, Souvik; Rao, Smitha; Mays, Jeffrey; Chiao, J-C

2015-09-23

In this paper, we report a power management system for autonomous and real-time monitoring of the neurotransmitter L-glutamate (L-Glu). A low-power, low-noise, and high-gain recording module was designed to acquire signal from an implantable flexible L-Glu sensor fabricated by micro-electro-mechanical system (MEMS)-based processes. The wearable recording module was wirelessly powered through inductive coupling transmitter antennas. Lateral and angular misalignments of the receiver antennas were resolved by using a multi-transmitter antenna configuration. The effective coverage, over which the recording module functioned properly, was improved with the use of in-phase transmitter antennas. Experimental results showed that the recording system was capable of operating continuously at distances of 4 cm, 7 cm and 10 cm. The wireless power management system reduced the weight of the recording module, eliminated human intervention and enabled animal experimentation for extended durations.

Wireless Power Transfer for Autonomous Wearable Neurotransmitter Sensors

PubMed Central

Nguyen, Cuong M.; Kota, Pavan Kumar; Nguyen, Minh Q.; Dubey, Souvik; Rao, Smitha; Mays, Jeffrey; Chiao, J.-C.

2015-01-01

In this paper, we report a power management system for autonomous and real-time monitoring of the neurotransmitter L-glutamate (L-Glu). A low-power, low-noise, and high-gain recording module was designed to acquire signal from an implantable flexible L-Glu sensor fabricated by micro-electro-mechanical system (MEMS)-based processes. The wearable recording module was wirelessly powered through inductive coupling transmitter antennas. Lateral and angular misalignments of the receiver antennas were resolved by using a multi-transmitter antenna configuration. The effective coverage, over which the recording module functioned properly, was improved with the use of in-phase transmitter antennas. Experimental results showed that the recording system was capable of operating continuously at distances of 4 cm, 7 cm and 10 cm. The wireless power management system reduced the weight of the recording module, eliminated human intervention and enabled animal experimentation for extended durations. PMID:26404311

High-volume production of single and compound emulsions in a microfluidic parallelization arrangement coupled with coaxial annular world-to-chip interfaces.

PubMed

Nisisako, Takasi; Ando, Takuya; Hatsuzawa, Takeshi

2012-09-21

This study describes a microfluidic platform with coaxial annular world-to-chip interfaces for high-throughput production of single and compound emulsion droplets, having controlled sizes and internal compositions. The production module consists of two distinct elements: a planar square chip on which many copies of a microfluidic droplet generator (MFDG) are arranged circularly, and a cubic supporting module with coaxial annular channels for supplying fluids evenly to the inlets of the mounted chip, assembled from blocks with cylinders and holes. Three-dimensional flow was simulated to evaluate the distribution of flow velocity in the coaxial multiple annular channels. By coupling a 1.5 cm × 1.5 cm microfluidic chip with parallelized 144 MFDGs and a supporting module with two annular channels, for example, we could produce simple oil-in-water (O/W) emulsion droplets having a mean diameter of 90.7 μm and a coefficient of variation (CV) of 2.2% at a throughput of 180.0 mL h(-1). Furthermore, we successfully demonstrated high-throughput production of Janus droplets, double emulsions and triple emulsions, by coupling 1.5 cm × 1.5 cm - 4.5 cm × 4.5 cm microfluidic chips with parallelized 32-128 MFDGs of various geometries and supporting modules with 3-4 annular channels.

Advanced flight computer. Special study

NASA Technical Reports Server (NTRS)

Coo, Dennis

1995-01-01

This report documents a special study to define a 32-bit radiation hardened, SEU tolerant flight computer architecture, and to investigate current or near-term technologies and development efforts that contribute to the Advanced Flight Computer (AFC) design and development. An AFC processing node architecture is defined. Each node may consist of a multi-chip processor as needed. The modular, building block approach uses VLSI technology and packaging methods that demonstrate a feasible AFC module in 1998 that meets that AFC goals. The defined architecture and approach demonstrate a clear low-risk, low-cost path to the 1998 production goal, with intermediate prototypes in 1996.

A photonic chip based frequency discriminator for a high performance microwave photonic link.

PubMed

Marpaung, David; Roeloffzen, Chris; Leinse, Arne; Hoekman, Marcel

2010-12-20

We report a high performance phase modulation direct detection microwave photonic link employing a photonic chip as a frequency discriminator. The photonic chip consists of five optical ring resonators (ORRs) which are fully programmable using thermo-optical tuning. In this discriminator a drop-port response of an ORR is cascaded with a through response of another ORR to yield a linear phase modulation (PM) to intensity modulation (IM) conversion. The balanced photonic link employing the PM to IM conversion exhibits high second-order and third-order input intercept points of + 46 dBm and + 36 dBm, respectively, which are simultaneously achieved at one bias point.

Apparatus and methods for packaging integrated circuit chips with antenna modules providing closed electromagnetic environment for integrated antennas

NASA Technical Reports Server (NTRS)

Gaucher, Brian P. (Inventor); Grzyb, Janusz (Inventor); Liu, Duixian (Inventor); Pfeiffer, Ullrich R. (Inventor)

2008-01-01

Apparatus and methods are provided for packaging IC chips together with integrated antenna modules designed to provide a closed EM (electromagnetic) environment for antenna radiators, thereby allowing antennas to be designed independent from the packaging technology.

Layout finishing of a 28nm, 3 billions transistors, multi-core processor

NASA Astrophysics Data System (ADS)

Morey-Chaisemartin, Philippe; Beisser, Eric

2013-06-01

Designing a fully new 256 cores processor is a great challenge for a fabless startup. In addition to all architecture, functionalities and timing issues, the layout by itself is a bottleneck due to all the process constraints of a 28nm technology. As developers of advanced layout finishing solutions, we were involved in the design flow of this huge chip with its 3 billions transistors. We had to face the issue of dummy patterns instantiation with respect to design constraints. All the design rules to generate the "dummies" are clearly defined in the Design Rule Manual, and some automatic procedures are provided by the foundry itself, but these routines don't take care of the designer requests. Such a chip, embeds both digital parts and analog modules for clock and power management. These two different type of designs have each their own set of constraints. In both cases, the insertion of dummies should not introduce unexpected variations leading to malfunctions. For example, on digital parts were signal race conditions are critical on long wires or bus, introduction of uncontrolled parasitic along these nets are highly critical. For analog devices such as high frequency and high sensitivity comparators, the exact symmetry of the two parts of a current mirror generator should be guaranteed. Thanks to the easily customizable features of our dummies insertion tool, we were able to configure it in order to meet all the designer requirements as well as the process constraints. This paper will present all these advanced key features as well as the layout tricks used to fulfill all requirements.

[3D-TV health assessment system by the multi-modal physiological signals].

PubMed

Li, Zhongqiang; Xing, Lidong; Qian, Zhiyu; Wang, Xiao; Yu, Defei; Liu, Baoyu; Jin, Shuai

2014-03-01

In order to meet the requirements of the multi-physiological signal measurement of the 3D-TV health assessment, try to find the suitable biological acquisition chips and design the hardware system which can detect different physiological signals in real time. The systems mainly uses ARM11/S3C6410 microcontroller to control the EEG/EOG acquisition chip RHA2116 and the ECG acquisition chip ADS1298, and then the microcontroller transfer the data collected by the chips to the PC software by the USB port which can display and save the experimental data in real time, then use the Matlab software for further processing of the data, finally make a final health assessment. In the meantime, for the different varieties in the different brain regions of watching 3D-TV, developed the special brain electrode placement and the experimental data processing methods, then effectively disposed the multi-signal data in the multilevel.

Advanced techniques and technology for efficient data storage, access, and transfer

NASA Technical Reports Server (NTRS)

Rice, Robert F.; Miller, Warner

1991-01-01

Advanced techniques for efficiently representing most forms of data are being implemented in practical hardware and software form through the joint efforts of three NASA centers. These techniques adapt to local statistical variations to continually provide near optimum code efficiency when representing data without error. Demonstrated in several earlier space applications, these techniques are the basis of initial NASA data compression standards specifications. Since the techniques clearly apply to most NASA science data, NASA invested in the development of both hardware and software implementations for general use. This investment includes high-speed single-chip very large scale integration (VLSI) coding and decoding modules as well as machine-transferrable software routines. The hardware chips were tested in the laboratory at data rates as high as 700 Mbits/s. A coding module's definition includes a predictive preprocessing stage and a powerful adaptive coding stage. The function of the preprocessor is to optimally process incoming data into a standard form data source that the second stage can handle.The built-in preprocessor of the VLSI coder chips is ideal for high-speed sampled data applications such as imaging and high-quality audio, but additionally, the second stage adaptive coder can be used separately with any source that can be externally preprocessed into the 'standard form'. This generic functionality assures that the applicability of these techniques and their recent high-speed implementations should be equally broad outside of NASA.

High-Temperature High-Power Packaging Techniques for HEV Traction Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Elshabini, Aicha; Barlow, Fred D.

A key issue associated with the wider adoption of hybrid-electric vehicles (HEV) and plug in hybrid-electric vehicles (PHEV) is the implementation of the power electronic systems that are required in these products. One of the primary industry goals is the reduction in the price of these vehicles relative to the cost of traditional gasoline powered vehicles. Today these systems, such as the Prius, utilize one coolant loop for the engine at approximately 100 C coolant temperatures, and a second coolant loop for the inverter at 65 C. One way in which significant cost reduction of these systems could be achievedmore » is through the use of a single coolant loop for both the power electronics as well as the internal combustion engine (ICE). This change in coolant temperature significantly increases the junction temperatures of the devices and creates a number of challenges for both device fabrication and the assembly of these devices into inverters and converters for HEV and PHEV applications. Traditional power modules and the state-of-the-art inverters in the current HEV products, are based on chip and wire assembly and direct bond copper (DBC) on ceramic substrates. While a shift to silicon carbide (SiC) devices from silicon (Si) devices would allow the higher operating temperatures required for a single coolant loop, it also creates a number of challenges for the assembly of these devices into power inverters. While this traditional packaging technology can be extended to higher temperatures, the key issues are the substrate material and conductor stability, die bonding material, wire bonds, and bond metallurgy reliability as well as encapsulation materials that are stable at high operating temperatures. The larger temperature differential during power cycling, which would be created by higher coolant temperatures, places tremendous stress on traditional aluminum wire bonds that are used to interconnect power devices. Selection of the bond metallurgy and wire bond geometry can play a key role in mitigating this stress. An alternative solution would be to eliminate the wire bonds completely through a fundamentally different method of forming a reliable top side interconnect. Similarly, the solders used in most power modules exhibit too low of a liquidus to be viable solutions for maximum junction temperatures of 200 C. Commonly used encapsulation materials, such as silicone gels, also suffer from an inability to operate at 200 C for extended periods of time. Possible solutions to these problems exist in most cases but require changes to the traditional manufacturing process used in these modules. In addition, a number of emerging technologies such as Si nitride, flip-chip assembly methods, and the elimination of base-plates would allow reliable module development for operation of HEV and PHEV inverters at elevated junction temperatures.« less

Assembly of opto-electronic module with improved heat sink

DOEpatents

Chan, Benson; Fortier, Paul Francis; Freitag, Ladd William; Galli, Gary T.; Guindon, Francois; Johnson, Glen Walden; Letourneau, Martial; Sherman, John H.; Tetreault, Real

2004-11-23

A heat sink for a transceiver optoelectronic module including dual direct heat paths and a structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

A 1-1/2-level on-chip-decoding bubble memory chip design

NASA Technical Reports Server (NTRS)

Chen, T. T.

1975-01-01

Design includes multi-channel replicator which can reduce chip-writing requirement, selective annihilating switch which can effectively annihilate bubbles with minimum delay, and modified transfer switch which can be used as selective steering-type decoder.

Hierarchical MFMO Circuit Modules for an Energy-Efficient SDR DBF

NASA Astrophysics Data System (ADS)

Mar, Jeich; Kuo, Chi-Cheng; Wu, Shin-Ru; Lin, You-Rong

The hierarchical multi-function matrix operation (MFMO) circuit modules are designed using coordinate rotations digital computer (CORDIC) algorithm for realizing the intensive computation of matrix operations. The paper emphasizes that the designed hierarchical MFMO circuit modules can be used to develop a power-efficient software-defined radio (SDR) digital beamformer (DBF). The formulas of the processing time for the scalable MFMO circuit modules implemented in field programmable gate array (FPGA) are derived to allocate the proper logic resources for the hardware reconfiguration. The hierarchical MFMO circuit modules are scalable to the changing number of array branches employed for the SDR DBF to achieve the purpose of power saving. The efficient reuse of the common MFMO circuit modules in the SDR DBF can also lead to energy reduction. Finally, the power dissipation and reconfiguration function in the different modes of the SDR DBF are observed from the experiment results.

Powering embedded electronics for wind turbine monitoring using multi-source energy harvesting techniques

NASA Astrophysics Data System (ADS)

Anton, S. R.; Taylor, S. G.; Raby, E. Y.; Farinholt, K. M.

2013-03-01

With a global interest in the development of clean, renewable energy, wind energy has seen steady growth over the past several years. Advances in wind turbine technology bring larger, more complex turbines and wind farms. An important issue in the development of these complex systems is the ability to monitor the state of each turbine in an effort to improve the efficiency and power generation. Wireless sensor nodes can be used to interrogate the current state and health of wind turbine structures; however, a drawback of most current wireless sensor technology is their reliance on batteries for power. Energy harvesting solutions present the ability to create autonomous power sources for small, low-power electronics through the scavenging of ambient energy; however, most conventional energy harvesting systems employ a single mode of energy conversion, and thus are highly susceptible to variations in the ambient energy. In this work, a multi-source energy harvesting system is developed to power embedded electronics for wind turbine applications in which energy can be scavenged simultaneously from several ambient energy sources. Field testing is performed on a full-size, residential scale wind turbine where both vibration and solar energy harvesting systems are utilized to power wireless sensing systems. Two wireless sensors are investigated, including the wireless impedance device (WID) sensor node, developed at Los Alamos National Laboratory (LANL), and an ultra-low power RF system-on-chip board that is the basis for an embedded wireless accelerometer node currently under development at LANL. Results indicate the ability of the multi-source harvester to successfully power both sensors.

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zeng, Zhiyao; Sun, Kexu; Wang, Guanhua

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/smore » operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.« less

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology

DOE PAGES

Zeng, Zhiyao; Sun, Kexu; Wang, Guanhua; ...

2017-05-08

This article presents a compact low-power 4 x 10 Gb/s quad-driver module for Vertical-Cavity Surface-Emitting Laser (VCSEL) arrays in a 65 nm CMOS technology. The side-by-side drivers can be directly wire bonded to the VCSEL diode array, supporting up to 4 channels. To increase the bandwidth of the driver, an internal feed-forward path is added for pole-zero cancellation, without increasing the power consumption. An edge-configurable pre-emphasis technique is proposed to achieve high bandwidth and minimize the asymmetry of the fall and rise times of the driver output current. Measurement results demonstrate a RMS jitter of 0.68 ps for 10 Gb/smore » operation. Tests demonstrate negligible crosstalk between channels. Under irradiation, the modulation amplitude degrades less than 5% up to 300 Mrad ionizing dose. Finally, the area of the quaddriver array is 500 μm by 1000 μm and the total power consumption for the entire driver array chip is 130 mW for the typical current setting.« less

Multimode fiber for high-density optical interconnects

NASA Astrophysics Data System (ADS)

Bickham, Scott R.; Ripumaree, Radawan; Chalk, Julie A.; Paap, Mark T.; Hurley, William C.; McClure, Randy L.

2017-02-01

Data centers (DCs) are facing the challenge of delivering more capacity over longer distances. As line rates increase to 25 Gb/s and higher, DCs are being challenged with signal integrity issues due to the long electrical traces that require retiming. In addition, the density of interconnects on the front panel is limited by the size and power dissipation requirements of the pluggable modules. One proposal to overcome these issues is to use embedded optical transceivers in which optical fibers are used to transport data to and from the front panel. These embedded modules will utilize arrays of VCSEL or silicon-photonic transceivers, and in both cases, the capacity may be limited by the density of the optical connections on the chip. To address this constraint, we have prototyped optical fibers in which the glass and coating diameters are reduced to 80 and 125 microns, respectively. These smaller diameters enable twice as many optical interconnects in the same footprint, and this in turn will allow the transceiver arrays to be collinearly located on small chips with dimensions on the order of (5x5mm2)1,2. We have also incorporated these reduced diameter fibers into small, flexible 8-fiber ribbon cables which can simplify routing constraints inside modules and optical backplanes.

Integrated Multi-process Microfluidic Systems for Automating Analysis

PubMed Central

Yang, Weichun; Woolley, Adam T.

2010-01-01

Microfluidic technologies have been applied extensively in rapid sample analysis. Some current challenges for standard microfluidic systems are relatively high detection limits, and reduced resolving power and peak capacity compared to conventional approaches. The integration of multiple functions and components onto a single platform can overcome these separation and detection limitations of microfluidics. Multiplexed systems can greatly increase peak capacity in multidimensional separations and can increase sample throughput by analyzing many samples simultaneously. On-chip sample preparation, including labeling, preconcentration, cleanup and amplification, can all serve to speed up and automate processes in integrated microfluidic systems. This paper summarizes advances in integrated multi-process microfluidic systems for automated analysis, their benefits and areas for needed improvement. PMID:20514343

Modular microfluidic systems using reversibly attached PDMS fluid control modules

NASA Astrophysics Data System (ADS)

Skafte-Pedersen, Peder; Sip, Christopher G.; Folch, Albert; Dufva, Martin

2013-05-01

The use of soft lithography-based poly(dimethylsiloxane) (PDMS) valve systems is the dominating approach for high-density microscale fluidic control. Integrated systems enable complex flow control and large-scale integration, but lack modularity. In contrast, modular systems are attractive alternatives to integration because they can be tailored for different applications piecewise and without redesigning every element of the system. We present a method for reversibly coupling hard materials to soft lithography defined systems through self-aligning O-ring features thereby enabling easy interfacing of complex-valve-based systems with simpler detachable units. Using this scheme, we demonstrate the seamless interfacing of a PDMS-based fluid control module with hard polymer chips. In our system, 32 self-aligning O-ring features protruding from the PDMS fluid control module form chip-to-control module interconnections which are sealed by tightening four screws. The interconnection method is robust and supports complex fluidic operations in the reversibly attached passive chip. In addition, we developed a double-sided molding method for fabricating PDMS devices with integrated through-holes. The versatile system facilitates a wide range of applications due to the modular approach, where application specific passive chips can be readily attached to the flow control module.

Widely Tunable Mode-Hop-Free External-Cavity Quantum Cascade Laser

NASA Technical Reports Server (NTRS)

Wysocki, Gerard; Curl, Robert F.; Tittel, Frank K.

2010-01-01

The external-cavity quantum cascade laser (EC-QCL) system is based on an optical configuration of the Littrow type. It is a room-temperature, continuous wave, widely tunable, mode-hop-free, mid-infrared, EC-QCL spectroscopic source. It has a single-mode tuning range of 155 cm(exp -1) (approximately equal to 8% of the center wavelength) with a maximum power of 11.1 mW and 182 cm(exp -1) (approximately equal to 15% of the center wavelength), and a maximum power of 50 mW as demonstrated for 5.3 micron and 8.4 micron EC-QCLs, respectively. This technology is particularly suitable for high-resolution spectroscopic applications, multi-species tracegas detection, and spectroscopic measurements of broadband absorbers. Wavelength tuning of EC-QCL spectroscopic source can be implemented by varying three independent parameters of the laser: (1) the optical length of the gain medium (which, in this case, is equivalent to QCL injection current modulation), (2) the length of the EC (which can be independently varied in the Rice EC-QCL setup), and (3) the angle of beam incidence at the diffraction grating (frequency tuning related directly to angular dispersion of the grating). All three mechanisms of frequency tuning have been demonstrated and are required to obtain a true mode-hop-free laser frequency tuning. The precise frequency tuning characteristics of the EC-QCL output have been characterized using a variety of diagnostic tools available at Rice University (e.g., a monochromator, FTIR spectrometer, and a Fabry-Perot spectrometer). Spectroscopic results were compared with available databases (such as HITRAN, PNNL, EPA, and NIST). These enable precision verification of complete spectral parameters of the EC-QCL, such as wavelength, tuning range, tuning characteristics, and line width. The output power of the EC-QCL is determined by the performance of the QC laser chip, its operating conditions, and parameters of the QC laser cavity such as mirror reflectivity or intracavity losses. In order to maximize the output power, an analysis and optimization of the EC laser parameters has been performed. The parameters of the beam emitted from the gain medium, such as divergence angle, beam profile, and astigmatism, have been investigated. The gain medium has been fully characterized before and after each stage of modification. The main modification steps are coating one facet of the gain chip with a high reflectivity mirror and the other facet with an anti-reflection layer. Then the chip is mounted in the EC-QCL. The optomechanical design has been reviewed and improved to provide for precise collimation of the strongly divergent beam of the QCL and the tuning diffraction grating.

Assessing the Power of Exome Chips.

PubMed

Page, Christian Magnus; Baranzini, Sergio E; Mevik, Bjørn-Helge; Bos, Steffan Daniel; Harbo, Hanne F; Andreassen, Bettina Kulle

2015-01-01

Genotyping chips for rare and low-frequent variants have recently gained popularity with the introduction of exome chips, but the utility of these chips remains unclear. These chips were designed using exome sequencing data from mainly American-European individuals, enriched for a narrow set of common diseases. In addition, it is well-known that the statistical power of detecting associations with rare and low-frequent variants is much lower compared to studies exclusively involving common variants. We developed a simulation program adaptable to any exome chip design to empirically evaluate the power of the exome chips. We implemented the main properties of the Illumina HumanExome BeadChip array. The simulated data sets were used to assess the power of exome chip based studies for varying effect sizes and causal variant scenarios. We applied two widely-used statistical approaches for rare and low-frequency variants, which collapse the variants into genetic regions or genes. Under optimal conditions, we found that a sample size between 20,000 to 30,000 individuals were needed in order to detect modest effect sizes (0.5% < PAR > 1%) with 80% power. For small effect sizes (PAR <0.5%), 60,000-100,000 individuals were needed in the presence of non-causal variants. In conclusion, we found that at least tens of thousands of individuals are necessary to detect modest effects under optimal conditions. In addition, when using rare variant chips on cohorts or diseases they were not originally designed for, the identification of associated variants or genes will be even more challenging.

Solar power generation system for reducing leakage current

NASA Astrophysics Data System (ADS)

Wu, Jinn-Chang; Jou, Hurng-Liahng; Hung, Chih-Yi

2018-04-01

This paper proposes a transformer-less multi-level solar power generation system. This solar power generation system is composed of a solar cell array, a boost power converter, an isolation switch set and a full-bridge inverter. A unipolar pulse-width modulation (PWM) strategy is used in the full-bridge inverter to attenuate the output ripple current. Circuit isolation is accomplished by integrating the isolation switch set between the solar cell array and the utility, to suppress the leakage current. The isolation switch set also determines the DC bus voltage for the full-bridge inverter connecting to the solar cell array or the output of the boost power converter. Accordingly, the proposed transformer-less multi-level solar power generation system generates a five-level voltage, and the partial power of the solar cell array is also converted to AC power using only the full-bridge inverter, so the power efficiency is increased. A prototype is developed to validate the performance of the proposed transformer-less multi-level solar power generation system.

DOE Office of Scientific and Technical Information (OSTI.GOV)

STADLER, MICHAEL; MASHAYEKH, SALMAN; DEFOREST, NICHOLAS

The ODC Microgrid Controller is an optimization-based model predicative microgrid controller (MPMC) to minimize operation cost (and/or CO2 emissions) in a microgrid in the grid-connected mode. It is composed of several modules, including a) forecasting, b) optimization, c) data exchange and d) power balancing modules. In the presence of a multi-layered control system architecture, these modules will reside in the supervisory control layer.

Asymmetric Multilevel Outphasing (AMO): A New Architecture for All-Silicon mm-Wave Transmitter ICs

DTIC Science & Technology

2015-06-12

power-amplifiers for mobile basestation infrastructure and handsets. NanoSemi Inc. designs linearization solutions for analog front-ends such as...ward flexible, multi-standard radio chips, increases the need for high-precision, high-throughput and energy-efficient backend processing. The desire...peak PAE is affected by less than 1% (46 mW/(46 mW 1.8 W/0.4)) by this 64-QAM capable AMO SCS backend . 378 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48

Flip-chip fabrication of integrated micromirror arrays using a novel latching off-chip hinge mechanism

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper presents the design, fabrication, modeling, and testing of various arrays of cantilever micromirror devices integrated atop CMOS control electronics. The upper layers of the arrays are prefabricated in the MUMPs process and then flip-chip transferred to CMOS receiving modules using a novel latching off-chip hinge mechanism. This mechanism allows the micromirror arrays to be released, rotated off the edge of the host module and then bonded to the receiving module using a standard probe station. The hinge mechanism supports the arrays by tethers that are severed to free the arrays once bonded. The resulting devices are inherently planarized since the bottom of the first releasable MUMPs layer becomes the surface of the integrated mirror. The working devices are formed by mirror surfaces bonded to address electrodes fabricated above static memory cells on the CMOS module. These arrays demonstrate highly desirable features such as compatible address potentials, less than 2 nm of RMS roughness, approximately 1 micrometers of lateral position accuracy and the unique ability to metallize reflective surfaces without masking. Ultimately, the off-chip hinge mechanism enables very low-cost, simple, reliable, repeatable and accurate assembly of advanced MEMS and integrated microsystems without specialized equipment or complex procedures.

A three channel telemetry system

NASA Technical Reports Server (NTRS)

Lesho, Jeffery C.; Eaton, Harry A. C.

1993-01-01

A three channel telemetry system intended for biomedical applications is described. The transmitter is implemented in a single chip using a 2 micron BiCMOS processes. The operation of the system and the test results from the latest chip are discussed. One channel is always dedicated to temperature measurement while the other two channels are generic. The generic channels carry information from transducers that are interfaced to the system through on-chip general purpose operational amplifiers. The generic channels have different bandwidths: one from dc to 250 Hz and the other from dc to 1300 Hz. Each generic channel modulates a current controlled oscillator to produce a frequency modulated signal. The two frequency modulated signals are summed and used to amplitude modulate the temperature signal which acts as a carrier. A near-field inductive link telemeters the combined signals over a short distance. The chip operates on a supply voltage anywhere from 2.5 to 3.6 Volts and draws less than 1 mA when transmitting a signal. The chip can be incorporated into ingestible, implantable and other configurations. The device can free the patient from tethered data collection systems and reduces the possibility of infection from subcutaneous leads. Data telemetry can increase patient comfort leading to a greater acceptance of monitoring.

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips

NASA Astrophysics Data System (ADS)

Yu, Thomas Edison; Yoneda, Tomokazu; Chakrabarty, Krishnendu; Fujiwara, Hideo

Rapid advances in semiconductor manufacturing technology have led to higher chip power densities, which places greater emphasis on packaging and temperature control during testing. For system-on-chips, peak power-based scheduling algorithms have been used to optimize tests under specified power constraints. However, imposing power constraints does not always solve the problem of overheating due to the non-uniform distribution of power across the chip. This paper presents a TAM/Wrapper co-design methodology for system-on-chips that ensures thermal safety while still optimizing the test schedule. The method combines a simplified thermal-cost model with a traditional bin-packing algorithm to minimize test time while satisfying temperature constraints. Furthermore, for temperature checking, thermal simulation is done using cycle-accurate power profiles for more realistic results. Experiments show that even a minimal sacrifice in test time can yield a considerable decrease in test temperature as well as the possibility of further lowering temperatures beyond those achieved using traditional power-based test scheduling.

Surface acoustic wave coding for orthogonal frequency coded devices

NASA Technical Reports Server (NTRS)

Malocha, Donald (Inventor); Kozlovski, Nikolai (Inventor)

2011-01-01

Methods and systems for coding SAW OFC devices to mitigate code collisions in a wireless multi-tag system. Each device producing plural stepped frequencies as an OFC signal with a chip offset delay to increase code diversity. A method for assigning a different OCF to each device includes using a matrix based on the number of OFCs needed and the number chips per code, populating each matrix cell with OFC chip, and assigning the codes from the matrix to the devices. The asynchronous passive multi-tag system includes plural surface acoustic wave devices each producing a different OFC signal having the same number of chips and including a chip offset time delay, an algorithm for assigning OFCs to each device, and a transceiver to transmit an interrogation signal and receive OFC signals in response with minimal code collisions during transmission.

Applications of multi-walled carbon nanotube in electronic packaging

PubMed Central

2012-01-01

Thermal management of integrated circuit chip is an increasing important challenge faced today. Heat dissipation of the chip is generally achieved through the die attach material and solders. With the temperature gradients in these materials, high thermo-mechanical stress will be developed in them, and thus they must also be mechanically strong so as to provide a good mechanical support to the chip. The use of multi-walled carbon nanotube to enhance the thermal conductivity, and the mechanical strength of die attach epoxy and Pb-free solder is demonstrated in this work. PMID:22405035

VLSI design of an RSA encryption/decryption chip using systolic array based architecture

NASA Astrophysics Data System (ADS)

Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

2016-09-01

This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

Towards Terabit Memories

NASA Astrophysics Data System (ADS)

Hoefflinger, Bernd

Memories have been the major yardstick for the continuing validity of Moore's law. In single-transistor-per-Bit dynamic random-access memories (DRAM), the number of bits per chip pretty much gives us the number of transistors. For decades, DRAM's have offered the largest storage capacity per chip. However, DRAM does not scale any longer, both in density and voltage, severely limiting its power efficiency to 10 fJ/b. A differential DRAM would gain four-times in density and eight-times in energy. Static CMOS RAM (SRAM) with its six transistors/cell is gaining in reputation because it scales well in cell size and operating voltage so that its fundamental advantage of speed, non-destructive read-out and low-power standby could lead to just 2.5 electrons/bit in standby and to a dynamic power efficiency of 2aJ/b. With a projected 2020 density of 16 Gb/cm², the SRAM would be as dense as normal DRAM and vastly better in power efficiency, which would mean a major change in the architecture and market scenario for DRAM versus SRAM. Non-volatile Flash memory have seen two quantum jumps in density well beyond the roadmap: Multi-Bit storage per transistor and high-density TSV (through-silicon via) technology. The number of electrons required per Bit on the storage gate has been reduced since their first realization in 1996 by more than an order of magnitude to 400 electrons/Bit in 2010 for a complexity of 32Gbit per chip at the 32 nm node. Chip stacking of eight chips with TSV has produced a 32GByte solid-state drive (SSD). A stack of 32 chips with 2 b/cell at the 16 nm node will reach a density of 2.5 Terabit/cm². Non-volatile memory with a density of 10 × 10 nm²/Bit is the target for widespread development. Phase-change memory (PCM) and resistive memory (RRAM) lead in cell density, and they will reach 20 Gb/cm² in 2D and higher with 3D chip stacking. This is still almost an order-of-magnitude less than Flash. However, their read-out speed is ~10-times faster, with as yet little data on their energy/b. As a read-out memory with unparalleled retention and lifetime, the ROM with electron-beam direct-write-lithography (Chap. 8) should be considered for its projected 2D density of 250 Gb/cm², a very small read energy of 0.1 μW/Gb/s. The lithography write-speed 10 ms/Terabit makes this ROM a serious contentender for the optimum in non-volatile, tamper-proof storage.

On-Chip Power-Combining for High-Power Schottky Diode-Based Frequency Multipliers

NASA Technical Reports Server (NTRS)

Chattopadhyay, Goutam; Mehdi, Imran; Schlecht, Erich T.; Lee, Choonsup; Siles, Jose V.; Maestrini, Alain E.; Thomas, Bertrand; Jung, Cecile D.

2013-01-01

A 1.6-THz power-combined Schottky frequency tripler was designed to handle approximately 30 mW input power. The design of Schottky-based triplers at this frequency range is mainly constrained by the shrinkage of the waveguide dimensions with frequency and the minimum diode mesa sizes, which limits the maximum number of diodes that can be placed on the chip to no more than two. Hence, multiple-chip power-combined schemes become necessary to increase the power-handling capabilities of high-frequency multipliers. The design presented here overcomes difficulties by performing the power-combining directly on-chip. Four E-probes are located at a single input waveguide in order to equally pump four multiplying structures (featuring two diodes each). The produced output power is then recombined at the output using the same concept.

Heat-driven liquid metal cooling device for the thermal management of a computer chip

NASA Astrophysics Data System (ADS)

Ma, Kun-Quan; Liu, Jing

2007-08-01

The tremendous heat generated in a computer chip or very large scale integrated circuit raises many challenging issues to be solved. Recently, liquid metal with a low melting point was established as the most conductive coolant for efficiently cooling the computer chip. Here, by making full use of the double merits of the liquid metal, i.e. superior heat transfer performance and electromagnetically drivable ability, we demonstrate for the first time the liquid-cooling concept for the thermal management of a computer chip using waste heat to power the thermoelectric generator (TEG) and thus the flow of the liquid metal. Such a device consumes no external net energy, which warrants it a self-supporting and completely silent liquid-cooling module. Experiments on devices driven by one or two stage TEGs indicate that a dramatic temperature drop on the simulating chip has been realized without the aid of any fans. The higher the heat load, the larger will be the temperature decrease caused by the cooling device. Further, the two TEGs will generate a larger current if a copper plate is sandwiched between them to enhance heat dissipation there. This new method is expected to be significant in future thermal management of a desk or notebook computer, where both efficient cooling and extremely low energy consumption are of major concern.

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE Office of Scientific and Technical Information (OSTI.GOV)

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI

DOE PAGES

Chen, Man-Chia; Perez, Aldo Pena; Kothapalli, Sri-Rajasekhar; ...

2017-10-16

This study presents a pixel pitch-matched readout chip for 3-D photoacoustic (PA) imaging, featuring a dedicated signal conditioning and delta-sigma modulation integrated within a pixel area of 250 μm by 250 μm. The proof-of-concept receiver was implemented in an STMicroelectronics's 28-nm Fully Depleted Silicon On Insulator technology, and interfaces to a 4 × 4 subarray of capacitive micromachined ultrasound transducers (CMUTs). The front-end signal conditioning in each pixel employs a coarse/fine gain tuning architecture to fulfill the 90-dB dynamic range requirement of the application. The employed delta-sigma beamforming architecture obviates the need for area-consuming Nyquist ADCs and thereby enables anmore » efficient in-pixel A/D conversion. The per-pixel switched-capacitor ΔΣ modulator leverages slewing-dominated and area-optimized inverter-based amplifiers. It occupies only 1/4th of the pixel, and its area compares favorably with state-of-the-art designs that offer the same SNR and bandwidth. The modulator's measured peak signal-to-noise-and-distortion ratio is 59.9 dB for a 10-MHz input bandwidth, and it consumes 6.65 mW from a 1V supply. The overall subarray beamforming approach improves the area per channel by 7.4 times and the single-channel SNR by 8 dB compared to prior art with similar delay resolution and power dissipation. Finally, the functionality of the designed chip was evaluated within a PA imaging experiment, employing a flip-chip bonded 2-D CMUT array.« less

Intelligent microchip networks: an agent-on-chip synthesis framework for the design of smart and robust sensor networks

NASA Astrophysics Data System (ADS)

Bosse, Stefan

2013-05-01

Sensorial materials consisting of high-density, miniaturized, and embedded sensor networks require new robust and reliable data processing and communication approaches. Structural health monitoring is one major field of application for sensorial materials. Each sensor node provides some kind of sensor, electronics, data processing, and communication with a strong focus on microchip-level implementation to meet the goals of miniaturization and low-power energy environments, a prerequisite for autonomous behaviour and operation. Reliability requires robustness of the entire system in the presence of node, link, data processing, and communication failures. Interaction between nodes is required to manage and distribute information. One common interaction model is the mobile agent. An agent approach provides stronger autonomy than a traditional object or remote-procedure-call based approach. Agents can decide for themselves, which actions are performed, and they are capable of flexible behaviour, reacting on the environment and other agents, providing some degree of robustness. Traditionally multi-agent systems are abstract programming models which are implemented in software and executed on program controlled computer architectures. This approach does not well scale to micro-chip level and requires full equipped computers and communication structures, and the hardware architecture does not consider and reflect the requirements for agent processing and interaction. We propose and demonstrate a novel design paradigm for reliable distributed data processing systems and a synthesis methodology and framework for multi-agent systems implementable entirely on microchip-level with resource and power constrained digital logic supporting Agent-On-Chip architectures (AoC). The agent behaviour and mobility is fully integrated on the micro-chip using pipelined communicating processes implemented with finite-state machines and register-transfer logic. The agent behaviour, interaction (communication), and mobility features are modelled and specified on a machine-independent abstract programming level using a state-based agent behaviour language (APL). With this APL a high-level agent compiler is able to synthesize a hardware model (RTL, VHDL), a software model (C, ML), or a simulation model (XML) suitable to simulate a multi-agent system using the SeSAm simulator framework. Agent communication is provided by a simple tuple-space database implemented on node level providing fault tolerant access of global data. A novel synthesis development kit (SynDK) based on a graph-structured database approach is introduced to support the rapid development of compilers and synthesis tools, used for example for the design and implementation of the APL compiler.

Flexible feature-space-construction architecture and its VLSI implementation for multi-scale object detection

NASA Astrophysics Data System (ADS)

Luo, Aiwen; An, Fengwei; Zhang, Xiangyu; Chen, Lei; Huang, Zunkai; Jürgen Mattausch, Hans

2018-04-01

Feature extraction techniques are a cornerstone of object detection in computer-vision-based applications. The detection performance of vison-based detection systems is often degraded by, e.g., changes in the illumination intensity of the light source, foreground-background contrast variations or automatic gain control from the camera. In order to avoid such degradation effects, we present a block-based L1-norm-circuit architecture which is configurable for different image-cell sizes, cell-based feature descriptors and image resolutions according to customization parameters from the circuit input. The incorporated flexibility in both the image resolution and the cell size for multi-scale image pyramids leads to lower computational complexity and power consumption. Additionally, an object-detection prototype for performance evaluation in 65 nm CMOS implements the proposed L1-norm circuit together with a histogram of oriented gradients (HOG) descriptor and a support vector machine (SVM) classifier. The proposed parallel architecture with high hardware efficiency enables real-time processing, high detection robustness, small chip-core area as well as low power consumption for multi-scale object detection.

A reconfigurable multi-mode multi-band transmitter with integrated frequency synthesizer for short-range wireless communication

NASA Astrophysics Data System (ADS)

Nan, Qi; Fan, Chen; Lingwei, Zhang; Xiaoman, Wang; Baoyong, Chi

2013-09-01

A reconfigurable multi-mode direct-conversion transmitter (TX) with integrated frequency synthesizer (FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620-920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and -126 dBc/Hz at a 1 MHz offset. The transmitter features a + 10.2 dBm peak output power with a +9.5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.

Effect of modulation p-doping level on multi-state lasing in InAs/InGaAs quantum dot lasers having different external loss

NASA Astrophysics Data System (ADS)

Korenev, V. V.; Savelyev, A. V.; Maximov, M. V.; Zubov, F. I.; Shernyakov, Yu. M.; Kulagina, M. M.; Zhukov, A. E.

2017-09-01

The influence of the modulation p-doping level on multi-state lasing in InAs/InGaAs quantum dot (QD) lasers is studied experimentally for devices having various external losses. It is shown that in the case of short cavities (high external loss), there is an increase in the lasing power component corresponding to the ground-state optical transitions of QDs as the p-doping level grows. However, in the case of long cavities (small external loss), higher dopant concentrations may have an opposite effect on the output power. Based on these observations, an optimal design of laser geometry and an optimal doping level are discussed.

Terabit optical OFDM superchannel transmission via coherent carriers of a hybrid chip-scale soliton frequency comb

NASA Astrophysics Data System (ADS)

Geng, Yong; Huang, Xiatao; Cui, Wenwen; Ling, Yun; Xu, Bo; Zhang, Jin; Yi, Xingwen; Wu, Baojian; Huang, Shu-Wei; Qiu, Kun; Wong, Chee Wei; Zhou, Heng

2018-05-01

We demonstrate seamless channel multiplexing and high bitrate superchannel transmission of coherent optical orthogonal-frequency-division-multiplexing (CO-OFDM) data signals utilizing a dissipative Kerr soliton (DKS) frequency comb generated in an on-chip microcavity. Aided by comb line multiplication through Nyquist pulse modulation, the high stability and mutual coherence among mode-locked Kerr comb lines are exploited for the first time to eliminate the guard intervals between communication channels and achieve full spectral density bandwidth utilization. Spectral efficiency as high as 2.625 bit/Hz/s is obtained for 180 CO-OFDM bands encoded with 12.75 Gbaud 8-QAM data, adding up to total bitrate of 6.885 Tb/s within 2.295 THz frequency comb bandwidth. Our study confirms that high coherence is the key superiority of Kerr soliton frequency combs over independent laser diodes, as a multi-spectral coherent laser source for high-bandwidth high-spectral-density transmission networks.

A 16 x 16-pixel retinal-prosthesis vision chip with in-pixel digital image processing in a frequency domain by use of a pulse-frequency-modulation photosensor

NASA Astrophysics Data System (ADS)

Kagawa, Keiichiro; Furumiya, Tetsuo; Ng, David C.; Uehara, Akihiro; Ohta, Jun; Nunoshita, Masahiro

2004-06-01

We are exploring the application of pulse-frequency-modulation (PFM) photosensor to retinal prosthesis for the blind because behavior of PFM photosensors is similar to retinal ganglion cells, from which visual data are transmitted from the retina toward the brain. We have developed retinal-prosthesis vision chips that reshape the output pulses of the PFM photosensor to biphasic current pulses suitable for electric stimulation of retinal cells. In this paper, we introduce image-processing functions to the pixel circuits. We have designed a 16x16-pixel retinal-prosthesis vision chip with several kinds of in-pixel digital image processing such as edge enhancement, edge detection, and low-pass filtering. This chip is a prototype demonstrator of the retinal prosthesis vision chip applicable to in-vitro experiments. By utilizing the feature of PFM photosensor, we propose a new scheme to implement the above image processing in a frequency domain by digital circuitry. Intensity of incident light is converted to a 1-bit data stream by a PFM photosensor, and then image processing is executed by a 1-bit image processor based on joint and annihilation of pulses. The retinal prosthesis vision chip is composed of four blocks: a pixels array block, a row-parallel stimulation current amplifiers array block, a decoder block, and a base current generators block. All blocks except PFM photosensors and stimulation current amplifiers are embodied as digital circuitry. This fact contributes to robustness against noises and fluctuation of power lines. With our vision chip, we can control photosensitivity and intensity and durations of stimulus biphasic currents, which are necessary for retinal prosthesis vision chip. The designed dynamic range is more than 100 dB. The amplitude of the stimulus current is given by a base current, which is common for all pixels, multiplied by a value in an amplitude memory of pixel. Base currents of the negative and positive pulses are common for the all pixels, and they are set in a linear manner. Otherwise, the value in the amplitude memory of the pixel is presented in an exponential manner to cover the wide range. The stimulus currents are put out column by column by scanning. The pixel size is 240um x 240um. Each pixel has a bonding pad on which stimulus electrode is to be formed. We will show the experimental results of the test chip.

a Mini Multi-Gas Detection System Based on Infrared Principle

NASA Astrophysics Data System (ADS)

Zhijian, Xie; Qiulin, Tan

2006-12-01

To counter the problems of gas accidents in coal mines, family safety resulted from using gas, a new infrared detection system with integration and miniaturization has been developed. The infrared detection optics principle used in developing this system is mainly analyzed. The idea that multi gas detection is introduced and guided through analyzing single gas detection is got across. Through researching the design of cell structure, the cell with integration and miniaturization has been devised. The way of data transmission on Controller Area Network (CAN) bus is explained. By taking Single-Chip Microcomputer (SCM) as intelligence handling, the functional block diagram of gas detection system is designed with its hardware and software system analyzed and devised. This system designed has reached the technology requirement of lower power consumption, mini-volume, big measure range, and able to realize multi-gas detection.

FM-UWB: Towards a Robust, Low-Power Radio for Body Area Networks

PubMed Central

Kopta, Vladimir; Farserotu, John; Enz, Christian

2017-01-01

The Frequency Modulated Ultra-Wideband (FM-UWB) is known as a low-power, low-complexity modulation scheme targeting low to moderate data rates in applications such as wireless body area networks. In this paper, a thorough review of all FM-UWB receivers and transmitters reported in literature is presented. The emphasis is on trends in power reduction that exhibit an improvement by a factor 20 over the past eight years, showing the high potential of FM-UWB. The main architectural and circuit techniques that have led to this improvement are highlighted. Seldom explored potential of using higher data rates and more complex modulations is demonstrated as a way to increase energy efficiency of FM-UWB. Multi-user communication over a single Radio Frequency (RF) channel is explored in more depth and multi-channel transmission is proposed as an extension of standard FM-UWB. The two techniques provide means of decreasing network latency, improving performance, and allow the FM-UWB to accommodate the increasing number of sensor nodes in the emerging applications such as High-Density Wireless Sensor Networks. PMID:28481248

An 81.6 μW FastICA processor for epileptic seizure detection.

PubMed

Yang, Chia-Hsiang; Shih, Yi-Hsin; Chiueh, Herming

2015-02-01

To improve the performance of epileptic seizure detection, independent component analysis (ICA) is applied to multi-channel signals to separate artifacts and signals of interest. FastICA is an efficient algorithm to compute ICA. To reduce the energy dissipation, eigenvalue decomposition (EVD) is utilized in the preprocessing stage to reduce the convergence time of iterative calculation of ICA components. EVD is computed efficiently through an array structure of processing elements running in parallel. Area-efficient EVD architecture is realized by leveraging the approximate Jacobi algorithm, leading to a 77.2% area reduction. By choosing proper memory element and reduced wordlength, the power and area of storage memory are reduced by 95.6% and 51.7%, respectively. The chip area is minimized through fixed-point implementation and architectural transformations. Given a latency constraint of 0.1 s, an 86.5% area reduction is achieved compared to the direct-mapped architecture. Fabricated in 90 nm CMOS, the core area of the chip is 0.40 mm(2). The FastICA processor, part of an integrated epileptic control SoC, dissipates 81.6 μW at 0.32 V. The computation delay of a frame of 256 samples for 8 channels is 84.2 ms. Compared to prior work, 0.5% power dissipation, 26.7% silicon area, and 3.4 × computation speedup are achieved. The performance of the chip was verified by human dataset.

Integrated application of combined cooling, heating and power poly-generation PV radiant panel system of zero energy buildings

NASA Astrophysics Data System (ADS)

Yin, Baoquan

2018-02-01

A new type of combined cooling, heating and power of photovoltaic radiant panel (PV/R) module was proposed, and applied in the zero energy buildings in this paper. The energy system of this building is composed of PV/R module, low temperature difference terminal, energy storage, multi-source heat pump, energy balance control system. Radiant panel is attached on the backside of the PV module for cooling the PV, which is called PV/R module. During the daytime, the PV module was cooled down with the radiant panel, as the temperature coefficient influence, the power efficiency was increased by 8% to 14%, the radiant panel solar heat collecting efficiency was about 45%. Through the nocturnal radiant cooling, the PV/R cooling capacity could be 50 W/m2. For the multifunction energy device, the system shows the versatility during the heating, cooling and power used of building utilization all year round.

Functionalization and Characterization of Nanomaterial Gated Field-Effect Transistor-Based Biosensors and the Design of a Multi-Analyte Implantable Biosensing Platform

NASA Astrophysics Data System (ADS)

Croce, Robert A., Jr.

Advances in semiconductor research and complementary-metal-oxide semiconductor fabrication allow for the design and implementation of miniaturized metabolic monitoring systems, as well as advanced biosensor design. The first part of this dissertation will focus on the design and fabrication of nanomaterial (single-walled carbon nanotube and quantum dot) gated field-effect transistors configured as protein sensors. These novel device structures have been functionalized with single-stranded DNA aptamers, and have shown sensor operation towards the protein Thrombin. Such advanced transistor-based sensing schemes present considerable advantages over traditional sensing methodologies in view of its miniaturization, low cost, and facile fabrication, paving the way for the ultimate realization of a multi-analyte lab-on-chip. The second part of this dissertation focuses on the design and fabrication of a needle-implantable glucose sensing platform which is based solely on photovoltaic powering and optical communication. By employing these powering and communication schemes, this design negates the need for bulky on-chip RF-based transmitters and batteries in an effort to attain extreme miniaturization required for needle-implantable/extractable applications. A complete single-sensor system coupled with a miniaturized amperometric glucose sensor has been demonstrated to exhibit reality of this technology. Furthermore, an optical selection scheme of multiple potentiostats for four different analytes (glucose, lactate, O 2 and CO2) as well as the optical transmission of sensor data has been designed for multi-analyte applications. The last part of this dissertation will focus on the development of a computational model for the amperometric glucose sensors employed in the aforementioned implantable platform. This model has been applied to single-layer single-enzyme systems, as well as multi-layer (single enzyme) systems utilizing glucose flux limiting layer-by-layer assembled outer membranes. The concentration of glucose and hydrogen peroxide within the sensor geometry, the transient response and the device response time has been simulated for both systems.

Fabrication of multi-well chips for spheroid cultures and implantable constructs through rapid prototyping techniques.

PubMed

Lopa, Silvia; Piraino, Francesco; Kemp, Raymond J; Di Caro, Clelia; Lovati, Arianna B; Di Giancamillo, Alessia; Moroni, Lorenzo; Peretti, Giuseppe M; Rasponi, Marco; Moretti, Matteo

2015-07-01

Three-dimensional (3D) culture models are widely used in basic and translational research. In this study, to generate and culture multiple 3D cell spheroids, we exploited laser ablation and replica molding for the fabrication of polydimethylsiloxane (PDMS) multi-well chips, which were validated using articular chondrocytes (ACs). Multi-well ACs spheroids were comparable or superior to standard spheroids, as revealed by glycosaminoglycan and type-II collagen deposition. Moreover, the use of our multi-well chips significantly reduced the operation time for cell seeding and medium refresh. Exploiting a similar approach, we used clinical-grade fibrin to generate implantable multi-well constructs allowing for the precise distribution of multiple cell types. Multi-well fibrin constructs were seeded with ACs generating high cell density regions, as shown by histology and cell fluorescent staining. Multi-well constructs were compared to standard constructs with homogeneously distributed ACs. After 7 days in vitro, expression of SOX9, ACAN, COL2A1, and COMP was increased in both constructs, with multi-well constructs expressing significantly higher levels of chondrogenic genes than standard constructs. After 5 weeks in vivo, we found that despite a dramatic size reduction, the cell distribution pattern was maintained and glycosaminoglycan content per wet weight was significantly increased respect to pre-implantation samples. In conclusion, multi-well chips for the generation and culture of multiple cell spheroids can be fabricated by low-cost rapid prototyping techniques. Furthermore, these techniques can be used to generate implantable constructs with defined architecture and controlled cell distribution, allowing for in vitro and in vivo investigation of cell interactions in a 3D environment. © 2015 Wiley Periodicals, Inc.

Backside illuminated CMOS-TDI line scan sensor for space applications

NASA Astrophysics Data System (ADS)

Cohen, Omer; Ofer, Oren; Abramovich, Gil; Ben-Ari, Nimrod; Gershon, Gal; Brumer, Maya; Shay, Adi; Shamay, Yaron

2018-05-01

A multi-spectral backside illuminated Time Delayed Integration Radiation Hardened line scan sensor utilizing CMOS technology was designed for continuous scanning Low Earth Orbit small satellite applications. The sensor comprises a single silicon chip with 4 independent arrays of pixels where each array is arranged in 2600 columns with 64 TDI levels. A multispectral optical filter whose spectral responses per array are adjustable per system requirement is assembled at the package level. A custom 4T Pixel design provides the required readout speed, low-noise, very low dark current, and high conversion gains. A 2-phase internally controlled exposure mechanism improves the sensor's dynamic MTF. The sensor high level of integration includes on-chip 12 bit per pixel analog to digital converters, on-chip controller, and CMOS compatible voltage levels. Thus, the power consumption and the weight of the supporting electronics are reduced, and a simple electrical interface is provided. An adjustable gain provides a Full Well Capacity ranging from 150,000 electrons up to 500,000 electrons per column and an overall readout noise per column of less than 120 electrons. The imager supports line rates ranging from 50 to 10,000 lines/sec, with power consumption of less than 0.5W per array. Thus, the sensor is characterized by a high pixel rate, a high dynamic range and a very low power. To meet a Latch-up free requirement RadHard architecture and design rules were utilized. In this paper recent electrical and electro-optical measurements of the sensor's Flight Models will be presented for the first time.

Low-power chip-level optical interconnects based on bulk-silicon single-chip photonic transceivers

NASA Astrophysics Data System (ADS)

Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Kim, Sun Ae; Oh, Jin Hyuk; Park, Jaegyu; Kim, Sanggi

2016-03-01

We present new scheme for chip-level photonic I/Os, based on monolithically integrated vertical photonic devices on bulk silicon, which increases the integration level of PICs to a complete photonic transceiver (TRx) including chip-level light source. A prototype of the single-chip photonic TRx based on a bulk silicon substrate demonstrated 20 Gb/s low power chip-level optical interconnects between fabricated chips, proving that this scheme can offer compact low-cost chip-level I/O solutions and have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, 3D-IC, and LAN/SAN/data-center and network applications.

CHIP: A new modulator of human malignant disorders

PubMed Central

Shao, Qianqian; Yang, Gang; Zheng, Lianfang; Zhang, Taiping; Zhao, Yupei

2016-01-01

Carboxyl terminus of Hsc70-interacting protein (CHIP) is known as a chaperone-associated E3 for a variety of protein substrates. It acts as a link between molecular chaperones and ubiquitin–proteasome system. Involved in the process of protein clearance, CHIP plays a critical role in maintaining protein homeostasis in diverse conditions. Here, we provide a comprehensive review of our current understanding of CHIP and summarize recent advances in CHIP biology, with a focus on CHIP in the setting of malignancies. PMID:27007160

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation

DOE PAGES

Bender, Michael A.; Berry, Jonathan W.; Hammond, Simon D.; ...

2017-01-03

A challenge in computer architecture is that processors often cannot be fed data from DRAM as fast as CPUs can consume it. Therefore, many applications are memory-bandwidth bound. With this motivation and the realization that traditional architectures (with all DRAM reachable only via bus) are insufficient to feed groups of modern processing units, vendors have introduced a variety of non-DDR 3D memory technologies (Hybrid Memory Cube (HMC),Wide I/O 2, High Bandwidth Memory (HBM)). These offer higher bandwidth and lower power by stacking DRAM chips on the processor or nearby on a silicon interposer. We will call these solutions “near-memory,” andmore » if user-addressable, “scratchpad.” High-performance systems on the market now offer two levels of main memory: near-memory on package and traditional DRAM further away. In the near term we expect the latencies near-memory and DRAM to be similar. Here, it is natural to think of near-memory as another module on the DRAM level of the memory hierarchy. Vendors are expected to offer modes in which the near memory is used as cache, but we believe that this will be inefficient.« less

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

PubMed

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-03-03

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter

PubMed Central

Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

2016-01-01

This paper presents the first low noise complementary metal oxide semiconductor (CMOS) terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31×31 focal plane array has been fully integrated in a 0.13μm standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0.2μV RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz. PMID:26950131

Modular high-voltage bias generator powered by dual-looped self-adaptive wireless power transmission.

PubMed

Xie, Kai; Huang, An-Feng; Li, Xiao-Ping; Guo, Shi-Zhong; Zhang, Han-Lu

2015-04-01

We proposed a modular high-voltage (HV) bias generator powered by a novel transmitter-sharing inductive coupled wireless power transmission technology, aimed to extend the generator's flexibility and configurability. To solve the problems caused through an uncertain number of modules, a dual-looped self-adaptive control method is proposed that is capable of tracking resonance frequency while maintaining a relatively stable induction voltage for each HV module. The method combines a phase-locked loop and a current feedback loop, which ensures an accurate resonance state and a relatively constant boost ratio for each module, simplifying the architecture of the boost stage and improving the total efficiency. The prototype was built and tested. The input voltage drop of each module is less than 14% if the module number varies from 3 to 10; resonance tracking is completed within 60 ms. The efficiency of the coupling structure reaches up to 95%, whereas the total efficiency approaches 73% for a rated output. Furthermore, this technology can be used in various multi-load wireless power supply applications.

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End

PubMed Central

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2015-01-01

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP). PMID:27069422

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End.

PubMed

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2016-01-15

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm 2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP).

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide

PubMed Central

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P. K. A.

2014-01-01

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W−1/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems. PMID:25417847

CMOS-compatible 2-bit optical spectral quantization scheme using a silicon-nanocrystal-based horizontal slot waveguide.

PubMed

Kang, Zhe; Yuan, Jinhui; Zhang, Xianting; Wu, Qiang; Sang, Xinzhu; Farrell, Gerald; Yu, Chongxiu; Li, Feng; Tam, Hwa Yaw; Wai, P K A

2014-11-24

All-optical analog-to-digital converters based on the third-order nonlinear effects in silicon waveguide are a promising candidate to overcome the limitation of electronic devices and are suitable for photonic integration. In this paper, a 2-bit optical spectral quantization scheme for on-chip all-optical analog-to-digital conversion is proposed. The proposed scheme is realized by filtering the broadened and split spectrum induced by the self-phase modulation effect in a silicon horizontal slot waveguide filled with silicon-nanocrystal. Nonlinear coefficient as high as 8708 W(-1)/m is obtained because of the tight mode confinement of the horizontal slot waveguide and the high nonlinear refractive index of the silicon-nanocrystal, which provides the enhanced nonlinear interaction and accordingly low power threshold. The results show that a required input peak power level less than 0.4 W can be achieved, along with the 1.98-bit effective-number-of-bit and Gray code output. The proposed scheme can find important applications in on-chip all-optical digital signal processing systems.

Thermal and Power Challenges in High Performance Computing Systems

NASA Astrophysics Data System (ADS)

Natarajan, Venkat; Deshpande, Anand; Solanki, Sudarshan; Chandrasekhar, Arun

2009-05-01

This paper provides an overview of the thermal and power challenges in emerging high performance computing platforms. The advent of new sophisticated applications in highly diverse areas such as health, education, finance, entertainment, etc. is driving the platform and device requirements for future systems. The key ingredients of future platforms are vertically integrated (3D) die-stacked devices which provide the required performance characteristics with the associated form factor advantages. Two of the major challenges to the design of through silicon via (TSV) based 3D stacked technologies are (i) effective thermal management and (ii) efficient power delivery mechanisms. Some of the key challenges that are articulated in this paper include hot-spot superposition and intensification in a 3D stack, design/optimization of thermal through silicon vias (TTSVs), non-uniform power loading of multi-die stacks, efficient on-chip power delivery, minimization of electrical hotspots etc.

A modular microfluidic architecture for integrated biochemical analysis.

PubMed

Shaikh, Kashan A; Ryu, Kee Suk; Goluch, Edgar D; Nam, Jwa-Min; Liu, Juewen; Thaxton, C Shad; Chiesl, Thomas N; Barron, Annelise E; Lu, Yi; Mirkin, Chad A; Liu, Chang

2005-07-12

Microfluidic laboratory-on-a-chip (LOC) systems based on a modular architecture are presented. The architecture is conceptualized on two levels: a single-chip level and a multiple-chip module (MCM) system level. At the individual chip level, a multilayer approach segregates components belonging to two fundamental categories: passive fluidic components (channels and reaction chambers) and active electromechanical control structures (sensors and actuators). This distinction is explicitly made to simplify the development process and minimize cost. Components belonging to these two categories are built separately on different physical layers and can communicate fluidically via cross-layer interconnects. The chip that hosts the electromechanical control structures is called the microfluidic breadboard (FBB). A single LOC module is constructed by attaching a chip comprised of a custom arrangement of fluid routing channels and reactors (passive chip) to the FBB. Many different LOC functions can be achieved by using different passive chips on an FBB with a standard resource configuration. Multiple modules can be interconnected to form a larger LOC system (MCM level). We demonstrated the utility of this architecture by developing systems for two separate biochemical applications: one for detection of protein markers of cancer and another for detection of metal ions. In the first case, free prostate-specific antigen was detected at 500 aM concentration by using a nanoparticle-based bio-bar-code protocol on a parallel MCM system. In the second case, we used a DNAzyme-based biosensor to identify the presence of Pb(2+) (lead) at a sensitivity of 500 nM in <1 nl of solution.

Optical modulation techniques for analog signal processing and CMOS compatible electro-optic modulation

NASA Astrophysics Data System (ADS)

Gill, Douglas M.; Rasras, Mahmoud; Tu, Kun-Yii; Chen, Young-Kai; White, Alice E.; Patel, Sanjay S.; Carothers, Daniel; Pomerene, Andrew; Kamocsai, Robert; Beattie, James; Kopa, Anthony; Apsel, Alyssa; Beals, Mark; Mitchel, Jurgen; Liu, Jifeng; Kimerling, Lionel C.

2008-02-01

Integrating electronic and photonic functions onto a single silicon-based chip using techniques compatible with mass-production CMOS electronics will enable new design paradigms for existing system architectures and open new opportunities for electro-optic applications with the potential to dramatically change the management, cost, footprint, weight, and power consumption of today's communication systems. While broadband analog system applications represent a smaller volume market than that for digital data transmission, there are significant deployments of analog electro-optic systems for commercial and military applications. Broadband linear modulation is a critical building block in optical analog signal processing and also could have significant applications in digital communication systems. Recently, broadband electro-optic modulators on a silicon platform have been demonstrated based on the plasma dispersion effect. The use of the plasma dispersion effect within a CMOS compatible waveguide creates new challenges and opportunities for analog signal processing since the index and propagation loss change within the waveguide during modulation. We will review the current status of silicon-based electrooptic modulators and also linearization techniques for optical modulation.

Holistic design in high-speed optical interconnects

NASA Astrophysics Data System (ADS)

Saeedi, Saman

Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The receiver sensitivity is measured to be -8.8dBm at 32Gb/s. Next, on the optical transmitter side, three new techniques will be presented. First one is a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop. As a first proof of concept, a prototype has been fabricated and measured up to 10Gb/s. The second technique is thermal stabilization of micro-ring resonator modulators through direct measurement of temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. A prototype is fabricated and a closed-loop feedback system is demonstrated to operate at 20Gb/s in the presence of temperature fluctuations. The third technique is a switched-capacitor based pre-emphasis technique designed to extend the inherently low bandwidth of carrier injection micro-ring modulators. A measured prototype of the optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit based on the monolithic PTAT sensor consumes 0.29mW. Lastly, a first-order frequency synthesizer that is suitable for high-speed on-chip clock generation will be discussed. The proposed design features an architecture combining an LC quadrature VCO, two sample-and-holds, a PI, digital coarse-tuning, and rotational frequency detection for fine-tuning. In addition to an electrical reference clock, as an extra feature, the prototype chip is capable of receiving a low jitter optical reference clock generated by a high-repetition-rate mode-locked laser. The output clock at 8GHz has an integrated RMS jitter of 490fs, peak-to-peak periodic jitter of 2.06ps, and total RMS jitter of 680fs. The reference spurs are measured to be 64.3dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

Optimized holographic femtosecond laser patterning method towards rapid integration of high-quality functional devices in microchannels

PubMed Central

Zhang, Chenchu; Hu, Yanlei; Du, Wenqiang; Wu, Peichao; Rao, Shenglong; Cai, Ze; Lao, Zhaoxin; Xu, Bing; Ni, Jincheng; Li, Jiawen; Zhao, Gang; Wu, Dong; Chu, Jiaru; Sugioka, Koji

2016-01-01

Rapid integration of high-quality functional devices in microchannels is in highly demand for miniature lab-on-a-chip applications. This paper demonstrates the embellishment of existing microfluidic devices with integrated micropatterns via femtosecond laser MRAF-based holographic patterning (MHP) microfabrication, which proves two-photon polymerization (TPP) based on spatial light modulator (SLM) to be a rapid and powerful technology for chip functionalization. Optimized mixed region amplitude freedom (MRAF) algorithm has been used to generate high-quality shaped focus field. Base on the optimized parameters, a single-exposure approach is developed to fabricate 200 × 200 μm microstructure arrays in less than 240 ms. Moreover, microtraps, QR code and letters are integrated into a microdevice by the advanced method for particles capture and device identification. These results indicate that such a holographic laser embellishment of microfluidic devices is simple, flexible and easy to access, which has great potential in lab-on-a-chip applications of biological culture, chemical analyses and optofluidic devices. PMID:27619690

Optical continuum generation on a silicon chip

NASA Astrophysics Data System (ADS)

Jalali, Bahram; Boyraz, Ozdal; Koonath, Prakash; Raghunathan, Varun; Indukuri, Tejaswi; Dimitropoulos, Dimitri

2005-08-01

Although the Raman effect is nearly two orders of magnitude stronger than the electronic Kerr nonlinearity in silicon, under pulsed operation regime where the pulse width is shorter than the phonon response time, Raman effect is suppressed and Kerr nonlinearity dominates. Continuum generation, made possible by the non-resonant Kerr nonlinearity, offers a technologically and economically appealing path to WDM communication at the inter-chip or intra-chip levels. We have studied this phenomenon experimentally and theoretically. Experimentally, a 2 fold spectral broadening is obtained by launching ~4ps optical pulses with 2.2GW/cm2 peak power into a conventional silicon waveguide. Theoretical calculations, that include the effect of two-photon-absorption, free carrier absorption and refractive index change indicate that up to >30 times spectral broadening is achievable in an optimized device. The broadening is due to self phase modulation and saturates due to two photon absorption. Additionally, we find that free carrier dynamics also contributes to the spectral broadening and cause the overall spectrum to be asymmetric with respect to the pump wavelength.

Optical Interconnections for VLSI Computational Systems Using Computer-Generated Holography.

NASA Astrophysics Data System (ADS)

Feldman, Michael Robert

Optical interconnects for VLSI computational systems using computer generated holograms are evaluated in theory and experiment. It is shown that by replacing particular electronic connections with free-space optical communication paths, connection of devices on a single chip or wafer and between chips or modules can be improved. Optical and electrical interconnects are compared in terms of power dissipation, communication bandwidth, and connection density. Conditions are determined for which optical interconnects are advantageous. Based on this analysis, it is shown that by applying computer generated holographic optical interconnects to wafer scale fine grain parallel processing systems, dramatic increases in system performance can be expected. Some new interconnection networks, designed to take full advantage of optical interconnect technology, have been developed. Experimental Computer Generated Holograms (CGH's) have been designed, fabricated and subsequently tested in prototype optical interconnected computational systems. Several new CGH encoding methods have been developed to provide efficient high performance CGH's. One CGH was used to decrease the access time of a 1 kilobit CMOS RAM chip. Another was produced to implement the inter-processor communication paths in a shared memory SIMD parallel processor array.

Lab-on-a-chip in vitro compartmentalization technologies for protein studies.

PubMed

Zhu, Yonggang; Power, Barbara E

2008-01-01

In vitro compartmentalization (IVC) is a powerful tool for studying protein-protein reactions, due to its high capacity and the versatility of droplet technologies. IVC bridges the gap between chemistry and biology as it enables the incorporation of unnatural amino acids with modifications into biological systems, through protein transcription and translation reactions, in a cell-like microdrop environment. The quest for the ultimate chip for protein studies using IVC is the drive for the development of various microfluidic droplet technologies to enable these unusual biochemical reactions to occur. These techniques have been shown to generate precise microdrops with a controlled size. Various chemical and physical phenomena have been utilized for on-chip manipulation to allow the droplets to be generated, fused, and split. Coupled with detection techniques, droplets can be sorted and selected. These capabilities allow directed protein evolution to be carried out on a microchip. With further technological development of the detection module, factors such as addressable storage, transport and interfacing technologies, could be integrated and thus provide platforms for protein studies with high efficiency and accuracy that conventional laboratories cannot achieve.

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability.

PubMed

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U

2015-03-06

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle.

An Ultra-Low Power CMOS Image Sensor with On-Chip Energy Harvesting and Power Management Capability

PubMed Central

Cevik, Ismail; Huang, Xiwei; Yu, Hao; Yan, Mei; Ay, Suat U.

2015-01-01

An ultra-low power CMOS image sensor with on-chip energy harvesting and power management capability is introduced in this paper. The photodiode pixel array can not only capture images but also harvest solar energy. As such, the CMOS image sensor chip is able to switch between imaging and harvesting modes towards self-power operation. Moreover, an on-chip maximum power point tracking (MPPT)-based power management system (PMS) is designed for the dual-mode image sensor to further improve the energy efficiency. A new isolated P-well energy harvesting and imaging (EHI) pixel with very high fill factor is introduced. Several ultra-low power design techniques such as reset and select boosting techniques have been utilized to maintain a wide pixel dynamic range. The chip was designed and fabricated in a 1.8 V, 1P6M 0.18 µm CMOS process. Total power consumption of the imager is 6.53 µW for a 96 × 96 pixel array with 1 V supply and 5 fps frame rate. Up to 30 μW of power could be generated by the new EHI pixels. The PMS is capable of providing 3× the power required during imaging mode with 50% efficiency allowing energy autonomous operation with a 72.5% duty cycle. PMID:25756863

Shrink-film microfluidic education modules: Complete devices within minutes.

PubMed

Nguyen, Diep; McLane, Jolie; Lew, Valerie; Pegan, Jonathan; Khine, Michelle

2011-06-01

As advances in microfluidics continue to make contributions to diagnostics and life sciences, broader awareness of this expanding field becomes necessary. By leveraging low-cost microfabrication techniques that require no capital equipment or infrastructure, simple, accessible, and effective educational modules can be made available for a broad range of educational needs from middle school demonstrations to college laboratory classes. These modules demonstrate key microfluidic concepts such as diffusion and separation as well as "laboratory on-chip" applications including chemical reactions and biological assays. These modules are intended to provide an interdisciplinary hands-on experience, including chip design, fabrication of functional devices, and experiments at the microscale. Consequently, students will be able to conceptualize physics at small scales, gain experience in computer-aided design and microfabrication, and perform experiments-all in the context of addressing real-world challenges by making their own lab-on-chip devices.

Active Metamaterials for Terahertz Communication and Imaging

NASA Astrophysics Data System (ADS)

Rout, Saroj

In recent years there has been significant interest in terahertz (THz) systems mostly due to their unique applications in communication and imaging. One of the primary reason for this resurgence is the use of metamaterials to design THz devices due to lack of natural materials that can respond to this electromagnetic spectrum, the so-called ''THz gap''. Even after years of intense research, THz systems are complex and expensive, unsuitable for mainstream applications. This work focuses on bridging this gap by building all solid-state THz devices for imaging and communication applications in a commercial integrated circuit (IC) technology. One such canonical device is a THz wave modulator that can be used in THz wireless communication devices and as spatial light modulator (SLM) for THz imaging systems. The key contribution of this thesis is a metamaterial based THz wave modulator fabricated in a commercial gallium arsenide (GaAs) process resonant at 0.46 THz using a novel approach of embedding pseudomorphic high electron mobility transistors (pHEMTs) in metamaterial and demonstrate modulation values over 30%, and THz modulation at frequencies up to 10 MHz. Using the THz wave modulator, we fabricated and experimentally demonstrated an all solid-state metamaterial based THz spatial light modulator (SLM) as a 2x2 pixel array operating around 0.46 THz, by raster scanning an occluded metal object in polystyrene using a single-pixel imaging setup. This was an important step towards building an low-voltage (1V), low power, on-chip integrable THz imaging device. Using the characterization result from the THz SLM, we computationally demonstrated a multi-level amplitude shift keying (ASK) terahertz wireless communication system using spatial light modulation instead of traditional voltage mode modulation, achieving higher spectral efficiency for high speed communication. We show two orders of magnitude improvement in symbol error rate (SER) for a degradation of 20 dB in transmit signal-to-noise ratio (SNR). We have computationally demonstrated a novel pictorial modulation technique showing N/log2(N) improvement in bandwidth using a N-tile SLM compared to standard spatial modulation using a single-pixel detector. Finally, we demonstrate a path to realize a terahertz focal plane array (FPA) using a commercial 0.18 mum CMOS foundry process. Through EM simulation and circuit simulation we have demonstrated a metamaterial based THz detectors at 230-325 GHz that can be used in a focal plane array.

Programmable Bio-Nano-Chip Systems for Serum CA125 Quantification: Towards Ovarian Cancer Diagnostics at the Point-of-Care

PubMed Central

Raamanathan, Archana; Simmons, Glennon W.; Christodoulides, Nicolaos; Floriano, Pierre N.; Furmaga, Wieslaw B.; Redding, Spencer W.; Lu, Karen H.; Bast, Robert C.; McDevitt, John T.

2013-01-01

Point-of-care (POC) implementation of early detection and screening methodologies for ovarian cancer may enable improved survival rates through early intervention. Current laboratory-confined immunoanalyzers have long turnaround times and are often incompatible with multiplexing and POC implementation. Rapid, sensitive and multiplexable POC diagnostic platforms compatible with promising early detection approaches for ovarian cancer are needed. To this end, we report the adaptation of the programmable bio-nano-chip (p-BNC), an integrated, microfluidic, modular (Programmable) platform for CA125 serum quantitation, a biomarker prominently implicated in multi-modal and multi-marker screening approaches. In the p-BNC, CA125 from diseased sera (Bio) is sequestered and assessed with a fluorescence-based sandwich immunoassay, completed in the nano-nets (Nano) of sensitized agarose microbeads localized in individually addressable wells (Chip), housed in a microfluidic module, capable of integrating multiple sample, reagent and biowaste processing and handling steps. Antibody pairs that bind to distinct epitopes on CA125 were screened. To permit efficient biomarker sequestration in a 3-D microfluidic environment, the p-BNC operating variables (incubation times, flow rates and reagent concentrations) were tuned to deliver optimal analytical performance under 45 minutes. With short analysis times, competitive analytical performance (Inter- and intra-assay precision of 1.2% and 1.9% and LODs of 1.0 U/mL) was achieved on this mini-sensor ensemble. Further validation with sera of ovarian cancer patients (n=20) demonstrated excellent correlation (R2 = 0.97) with gold-standard ELISA. Building on the integration capabilities of novel microfluidic systems programmed for ovarian cancer, the rapid, precise and sensitive miniaturized p-BNC system shows strong promise for ovarian cancer diagnostics. PMID:22490510

WAT-on-a-chip: A physiologically relevant microfluidic system incorporating white adipose tissue

PubMed Central

Loskill, Peter; Sezhian, Thiagarajan; Tharp, Kevin; Lee-Montiel, Felipe T.; Jeeawoody, Shaheen; Reese, Willie Mae; Zushin, Pete-James H.; Stahl, Andreas; Healy, Kevin E.

2017-01-01

Organ-on-a-chip systems possess a promising future as drug screening assays and as testbeds for disease modeling in the context of both single-organ systems and multi-organ-chips. Although it comprises approximately one fourth of the body weight of a healthy human, an organ frequently overlooked in this context is white adipose tissue (WAT). WAT-on-a-chip systems are required to create safety profiles of a large number of drugs due to their interactions with adipose tissue and other organs via paracrine signals, fatty acid release, and drug levels through sequestration. We report a WAT-on-a-chip system with a footprint of less than 1 mm2 consisting of a separate media channel and WAT chamber connected via small micropores. Analogous to the in vivo blood circulation, convective transport is thereby confined to the vasculature-like structures and the tissues protected from shear stresses. Numerical and analytical modeling revealed that the flow rates in the WAT chambers are less than 1/100 of the input flow rate. Using optimized injection parameters, we were able to inject pre-adipocytes, which subsequently formed adipose tissue featuring fully functional lipid metabolism. The physiologically relevant microfluidic environment of the WAT-chip supported long term culture of the functional adipose tissue for more than two weeks. Due to its physiological, highly controlled, and computationally predictable character, the system has the potential to be a powerful tool for the study of adipose tissue associated diseases such as obesity and type 2 diabetes. PMID:28418430

Saturn Apollo Program

NASA Image and Video Library

1969-01-01

A close-up view of the Apollo 11 command service module ready to be mated with the spacecraft LEM adapter of the third stage. The towering 363-foot Saturn V was a multi-stage, multi-engine launch vehicle standing taller than the Statue of Liberty. Altogether, the Saturn V engines produced as much power as 85 Hoover Dams.

Design considerations for FET-gated power transistors

NASA Technical Reports Server (NTRS)

Chen, D. Y.; Chin, S. A.

1983-01-01

An FET-bipolar combinational power transistor configuration (tested up to 300 V, 20 A at 100 kHz) is described. The critical parameters for integrating the chips in hybrid form are examined, and an effort to optimize the overall characteristics of the configuration is discussed. Chip considerations are examined with respect to the voltage and current rating of individual chips, the FET surge capability, the choice of triple diffused transistor or epitaxial transistor for the bipolar element, the current tailing effect, and the implementation of the bipolar transistor and an FET as single chip or separate chips. Package considerations are discussed with respect to package material and geometry, surge current capability of bipolar base terminal bonding, and power losses distribution.

Open-systems Architecture of a Standardized Command Interface Chip-set for Switching and Control of a Spacecraft Power Bus

NASA Technical Reports Server (NTRS)

Ruiz, B. Ian; Burke, Gary R.; Lung, Gerald; Whitaker, William D.; Nowicki, Robert M.

2004-01-01

This viewgraph presentation reviews the architecture of the The CIA-AlA chip-set is a set of mixed-signal ASICs that provide a flexible high level interface between the spacecraft's command and data handling (C&DH) electronics and lower level functions in other spacecraft subsystems. Due to the open-systems architecture of the chip-set including an embedded micro-controller a variety of applications are possible. The chip-set was developed for the missions to the outer planets. The chips were developed to provide a single solution for both the switching and regulation of a spacecraft power bus. The Open-Systems Architecture allows for other powerful applications.

Optically powered oil tank multichannel detection system with optical fiber link

NASA Astrophysics Data System (ADS)

Yu, Zhijing

1998-08-01

A novel oil tanks integrative parameters measuring system with optically powered are presented. To realize optical powered and micro-power consumption multiple channels and parameters detection, the system has taken the PWM/PPM modulation, ratio measurement, time division multiplexing and pulse width division multiplexing techniques. Moreover, the system also used special pulse width discriminator and single-chip microcomputer to accomplish signal pulse separation, PPM/PWM signal demodulation, the error correction of overlapping pulse and data processing. This new transducer has provided with high characteristics: experimental transmitting distance is 500m; total consumption of the probes is less than 150 (mu) W; measurement error: +/- 0.5 degrees C and +/- 0.2 percent FS. The measurement accuracy of the liquid level and reserves is mainly determined by the pressure accuracy. Finally, some points of the experiment are given.

An ultrasound transient elastography system with coded excitation.

PubMed

Diao, Xianfen; Zhu, Jing; He, Xiaonian; Chen, Xin; Zhang, Xinyu; Chen, Siping; Liu, Weixiang

2017-06-28

Ultrasound transient elastography technology has found its place in elastography because it is safe and easy to operate. However, it's application in deep tissue is limited. The aim of this study is to design an ultrasound transient elastography system with coded excitation to obtain greater detection depth. The ultrasound transient elastography system requires tissue vibration to be strictly synchronous with ultrasound detection. Therefore, an ultrasound transient elastography system with coded excitation was designed. A central component of this transient elastography system was an arbitrary waveform generator with multi-channel signals output function. This arbitrary waveform generator was used to produce the tissue vibration signal, the ultrasound detection signal and the synchronous triggering signal of the radio frequency data acquisition system. The arbitrary waveform generator can produce different forms of vibration waveform to induce different shear wave propagation in the tissue. Moreover, it can achieve either traditional pulse-echo detection or a phase-modulated or a frequency-modulated coded excitation. A 7-chip Barker code and traditional pulse-echo detection were programmed on the designed ultrasound transient elastography system to detect the shear wave in the phantom excited by the mechanical vibrator. Then an elasticity QA phantom and sixteen in vitro rat livers were used for performance evaluation of the two detection pulses. The elasticity QA phantom's results show that our system is effective, and the rat liver results show the detection depth can be increased more than 1 cm. In addition, the SNR (signal-to-noise ratio) is increased by 15 dB using the 7-chip Barker coded excitation. Applying 7-chip Barker coded excitation technique to the ultrasound transient elastography can increase the detection depth and SNR. Using coded excitation technology to assess the human liver, especially in obese patients, may be a good choice.

A 220-GHz SIS Mixer Tightly Integrated With a Sub-Hundred-Microwatt SiGe IF Amplifier

NASA Astrophysics Data System (ADS)

Montazeri, Shirin; Grimes, Paul K.; Tong, Cheuk-Yu Edward; Bardin, Joseph C.

2016-01-01

Future kilopixel-scale heterodyne focal plane arrays based on superconductor-insulator-superconductor (SIS) mixers will require submilliwatt power consumption low-noise amplifiers (LNAs) which are tightly integrated with the mixers. In this paper, an LNA that is optimized for direct connection to a 220-GHz SIS mixer chip and requires less than 100 μW of dc power is reported. The amplifier design process is described, and measurement results are presented. It is shown that, when pumped at local oscillator frequencies between 214 and 226 GHz, the mixer/amplifier module achieves a double-sideband system noise temperature between 35 and 50 K over the 3.3-6 GHz IF frequency range while requiring just 90 μW of dc power. Moreover, the potential to further reduce the power consumption is explored and successful operation is demonstrated for LNA power consumption as low as 60 μW.

Design and prototyping of a chip-based multi-micro-organoid culture system for substance testing, predictive to human (substance) exposure.

PubMed

Sonntag, Frank; Schilling, Niels; Mader, Katja; Gruchow, Mathias; Klotzbach, Udo; Lindner, Gerd; Horland, Reyk; Wagner, Ilka; Lauster, Roland; Howitz, Steffen; Hoffmann, Silke; Marx, Uwe

2010-07-01

Dynamic miniaturized human multi-micro-organ bioreactor systems are envisaged as a possible solution for the embarrassing gap of predictive substance testing prior to human exposure. A rational approach was applied to simulate and design dynamic long-term cultures of the smallest possible functional human organ units, human "micro-organoids", on a chip the shape of a microscope slide. Each chip contains six identical dynamic micro-bioreactors with three different micro-organoid culture segments each, a feed supply and waste reservoirs. A liver, a brain cortex and a bone marrow micro-organoid segment were designed into each bioreactor. This design was translated into a multi-layer chip prototype and a routine manufacturing procedure was established. The first series of microscopable, chemically resistant and sterilizable chip prototypes was tested for matrix compatibility and primary cell culture suitability. Sterility and long-term human cell survival could be shown. Optimizing the applied design approach and prototyping tools resulted in a time period of only 3 months for a single design and prototyping cycle. This rapid prototyping scheme now allows for fast adjustment or redesign of inaccurate architectures. The designed chip platform is thus ready to be evaluated for the establishment and maintenance of the human liver, brain cortex and bone marrow micro-organoids in a systemic microenvironment. Copyright (c) 2010 Elsevier B.V. All rights reserved.

The Biolink Implantable Telemetry System

NASA Technical Reports Server (NTRS)

Betancourt-Zamora, Rafael J.

1999-01-01

Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS process. Measured phase noise for a 1.5mW, 200MHz ring oscillator VCO is -80dBc/Hz at 100KHZ offset, showing good agreement with the theory. We also propose a novel superregenerative receiver architecture for implementing the command receiver. The superregenerative receiver's simplicity, low cost, and low power consumption has made it the receiver of choice for short-distance data communications, remote control and home automation. We present the design of a superregenerative AM receiver implemented in a 0.5um CMOS technology that operates at 433.92MHz and dissipates only 300uW. Further work entails detailed transistor-level design of the FLL and superregenerative receiver and a monolithic implementation of an implantable transceiver in 0.5um CMOS technology.

Prototyping of Silicon Strip Detectors for the Inner Tracker of the ALICE Experiment

NASA Astrophysics Data System (ADS)

Sokolov, Oleksiy

2006-04-01

The ALICE experiment at CERN will study heavy ion collisions at a center-of-mass energy 5.5˜TeV per nucleon. Particle tracking around the interaction region at radii r<45 cm is done by the Inner Tracking System (ITS), consisting of six cylindrical layers of silicon detectors. The outer two layers of the ITS use double-sided silicon strip detectors. This thesis focuses on testing of these detectors and performance studies of the detector module prototypes at the beam test. Silicon strip detector layers will require about 20 thousand HAL25 front-end readout chips and about 3.5 thousand hybrids each containing 6 HAL25 chips. During the assembly procedure, chips are bonded on a patterned TAB aluminium microcables which connect to all the chip input and output pads, and then the chips are assembled on the hybrids. Bonding failures at the chip or hybrid level may either render the component non-functional or deteriorate its the performance such that it can not be used for the module production. After each bonding operation, the component testing is done to reject the non-functional or poorly performing chips and hybrids. The LabView-controlled test station for this operation has been built at Utrecht University and was successfully used for mass production acceptance tests of chips and hybrids at three production labs. The functionality of the chip registers, bonding quality and analogue functionality of the chips and hybrids are addressed in the test. The test routines were optimized to minimize the testing time to make sure that testing is not a bottleneck of the mass production. For testing of complete modules the laser scanning station with 1060 nm diode laser has been assembled at Utrecht University. The testing method relies of the fact that a response of the detector module to a short collimated laser beam pulse resembles a response to a minimum ionizing particle. A small beam spot size (˜7 μm ) allows to deposit the charge in a narrow region and measure the response of individual detector channels. First several module prototypes have been studied with this setup, the strip gain and charge sharing function have been measured, the later is compared with the model predictions. It was also shown that for a laser beam of a high monochromaticity, interference in the sensor bulk significantly modulates the deposited charge and introduces a systematic error of the gain measurement. Signatures of disconnected strips and pinholes defects have been observed, the response of the disconnected strips to the laser beam has been correlated with the noise measurements. Beam test of four prototype modules have been carried out at PS accelerator at CERN using 7 GeV/c pions. It was demonstrated that the modules provide an excellent signal-to-noise ratio in the range 40-75. The estimated spatial resolution for the normally incident tracks is about 18 μm using the center-of-gravity cluster reconstruction method. A non-iterative method for spatial resolution determination was developed, it was shown that in order to determine the resolution of each individual detector in the telescope, the telescope should consist of at least 5 detectors. The detectors showed high detection efficiency, in the order 99%. It was shown that the particle loss occurs mostly in the defected regions near the noisy strips or strips with a very low gain. The efficiency of the sensor area with nominal characteristics is consistent with 100%.

Small-scale heat detection using catalytic microengines irradiated by laser

NASA Astrophysics Data System (ADS)

Liu, Zhaoqian; Li, Jinxing; Wang, Jiao; Huang, Gaoshan; Liu, Ran; Mei, Yongfeng

2013-01-01

We demonstrate a novel approach to modulating the motion speed of catalytic microtubular engines via laser irradiation/heating with regard to small-scale heat detection. Laser irradiation on the engines leads to a thermal heating effect and thus enhances the engine speed. During a laser on/off period, the motion behaviour of a microengine can be repeatable and reversible, demonstrating a regulation of motion speeds triggered by laser illumination. Also, the engine velocity exhibits a linear dependence on laser power in various fuel concentrations, which implies an application potential as local heat sensors. Our work may hold great promise in applications such as lab on a chip, micro/nano factories, and environmental detection.We demonstrate a novel approach to modulating the motion speed of catalytic microtubular engines via laser irradiation/heating with regard to small-scale heat detection. Laser irradiation on the engines leads to a thermal heating effect and thus enhances the engine speed. During a laser on/off period, the motion behaviour of a microengine can be repeatable and reversible, demonstrating a regulation of motion speeds triggered by laser illumination. Also, the engine velocity exhibits a linear dependence on laser power in various fuel concentrations, which implies an application potential as local heat sensors. Our work may hold great promise in applications such as lab on a chip, micro/nano factories, and environmental detection. Electronic supplementary information (ESI) available. See DOI: 10.1039/c2nr32494f

The design of multi temperature and humidity monitoring system for incubator

NASA Astrophysics Data System (ADS)

Yu, Junyu; Xu, Peng; Peng, Zitao; Qiang, Haonan; Shen, Xiaoyan

2017-01-01

Currently, there is only one monitor of the temperature and humidity in an incubator, which may cause inaccurate or unreliable data, and even endanger the life safety of the baby. In order to solve this problem,we designed a multi-point temperature and humidity monitoring system for incubators. The system uses the STC12C5A60S2 microcontrollers as the sender core chip which is connected to four AM2321 temperature and humidity sensors. We select STM32F103ZET6 core development board as the receiving end,cooperating with Zigbee wireless transmitting and receiving module to realize data acquisition and transmission. This design can realize remote real-time observation data on the computer by communicating with PC via Ethernet. Prototype tests show that the system can effectively collect and display the information of temperature and humidity of multiple incubators at the same time and there are four monitors in each incubator.

[An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

PubMed

Balashov, A M; Selishchev, S V

2004-01-01

An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Science Enabling ASICs and FEEs for the JUICE and JEO Missions

NASA Technical Reports Server (NTRS)

Paschalidis, Nicholas; Sittler, Ed; Cooper, John; Christian, Eric; Moore, Tom

2011-01-01

A family of science enabling radiation hard Application Specific Integrated Circuits (ASICs), Front End Electronics (FEEs) and Event Processing Systems, with flight heritage on many NASA missions, is presented. These technologies play an important role in the miniaturization of instruments -and spacecraft systems- at the same time increasing performance and reducing power. The technologies target time of flight, position sensing, and energy measurements as well as standard housekeeping and telemetry functions for particle and fields instruments, but find applications in other instrument categories too. More specifically the technologies include: the TOF chip, 1D and 2D Delay Lines with MCP detectors, for high precision fast and low power time of flight and position sensing; the Energy chip for multichannel SSD readout with time over threshold and standard voltage read out for TDC and ADC digitization; Fast multi channel read out chip with commandable thresholds; the TRIO chip for multiplexed ADC and housekeeping etc. It should be mentioned that the ASICs include basic trigger capabilities to enable random event processing in a heavy background of penetrators and UV foreground. Typical instruments include time of flight versus energy and look angle particle analyzers such as: plasma composition, energetic particle, neutral atom imaging as well as fast plasma and deltaE/E ion/electron telescopes. Flight missions include: Cassini/LEMMS, IMAGE/HENA, MESSENGER/EPPS/MLA/X-ray/MLA, STEREO, PLUTO-NH/PEPSSI/LORI, IBEX-Lo, JUNO/JEDI, RBSP/RBSPICE, MMS/HPCA/EPD, SO/SIS. Given the proven capability on heavy radiation missions such as JUNO, MMS and RBSB, as well diverse long duration missions such as MESSENGER, PLUTO and Cassini, it is expected that these technologies will play an important role in the particle and fields (at least) instruments on the upcoming JUICE and JEO missions.

Multi-angle lensless digital holography for depth resolved imaging on a chip.

PubMed

Su, Ting-Wei; Isikman, Serhan O; Bishara, Waheb; Tseng, Derek; Erlinger, Anthony; Ozcan, Aydogan

2010-04-26

A multi-angle lensfree holographic imaging platform that can accurately characterize both the axial and lateral positions of cells located within multi-layered micro-channels is introduced. In this platform, lensfree digital holograms of the micro-objects on the chip are recorded at different illumination angles using partially coherent illumination. These digital holograms start to shift laterally on the sensor plane as the illumination angle of the source is tilted. Since the exact amount of this lateral shift of each object hologram can be calculated with an accuracy that beats the diffraction limit of light, the height of each cell from the substrate can be determined over a large field of view without the use of any lenses. We demonstrate the proof of concept of this multi-angle lensless imaging platform by using light emitting diodes to characterize various sized microparticles located on a chip with sub-micron axial and lateral localization over approximately 60 mm(2) field of view. Furthermore, we successfully apply this lensless imaging approach to simultaneously characterize blood samples located at multi-layered micro-channels in terms of the counts, individual thicknesses and the volumes of the cells at each layer. Because this platform does not require any lenses, lasers or other bulky optical/mechanical components, it provides a compact and high-throughput alternative to conventional approaches for cytometry and diagnostics applications involving lab on a chip systems.

Advanced packaging for Integrated Micro-Instruments

NASA Technical Reports Server (NTRS)

Lyke, James L.

1995-01-01

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Bio-inspired multi-mode optic flow sensors for micro air vehicles

NASA Astrophysics Data System (ADS)

Park, Seokjun; Choi, Jaehyuk; Cho, Jihyun; Yoon, Euisik

2013-06-01

Monitoring wide-field surrounding information is essential for vision-based autonomous navigation in micro-air-vehicles (MAV). Our image-cube (iCube) module, which consists of multiple sensors that are facing different angles in 3-D space, can be applied to the wide-field of view optic flows estimation (μ-Compound eyes) and to attitude control (μ- Ocelli) in the Micro Autonomous Systems and Technology (MAST) platforms. In this paper, we report an analog/digital (A/D) mixed-mode optic-flow sensor, which generates both optic flows and normal images in different modes for μ- Compound eyes and μ-Ocelli applications. The sensor employs a time-stamp based optic flow algorithm which is modified from the conventional EMD (Elementary Motion Detector) algorithm to give an optimum partitioning of hardware blocks in analog and digital domains as well as adequate allocation of pixel-level, column-parallel, and chip-level signal processing. Temporal filtering, which may require huge hardware resources if implemented in digital domain, is remained in a pixel-level analog processing unit. The rest of the blocks, including feature detection and timestamp latching, are implemented using digital circuits in a column-parallel processing unit. Finally, time-stamp information is decoded into velocity from look-up tables, multiplications, and simple subtraction circuits in a chip-level processing unit, thus significantly reducing core digital processing power consumption. In the normal image mode, the sensor generates 8-b digital images using single slope ADCs in the column unit. In the optic flow mode, the sensor estimates 8-b 1-D optic flows from the integrated mixed-mode algorithm core and 2-D optic flows with an external timestamp processing, respectively.

All-optical SR flip-flop based on SOA-MZI switches monolithically integrated on a generic InP platform

NASA Astrophysics Data System (ADS)

Pitris, St.; Vagionas, Ch.; Kanellos, G. T.; Kisacik, R.; Tekin, T.; Broeke, R.; Pleros, N.

2016-03-01

At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.

High brightness laser-diode device emitting 160 watts from a 100 μm/NA 0.22 fiber.

PubMed

Yu, Junhong; Guo, Linui; Wu, Hualing; Wang, Zhao; Tan, Hao; Gao, Songxin; Wu, Deyong; Zhang, Kai

2015-11-10

A practical method of achieving a high-brightness and high-power fiber-coupled laser-diode device is demonstrated both by experiment and ZEMAX software simulation, which is obtained by a beam transformation system, free-space beam combining, and polarization beam combining based on a mini-bar laser-diode chip. Using this method, fiber-coupled laser-diode module output power from the multimode fiber with 100 μm core diameter and 0.22 numerical aperture (NA) could reach 174 W, with equalizing brightness of 14.2  MW/(cm2·sr). By this method, much wider applications of fiber-coupled laser-diodes are anticipated.

Argus: a 16-pixel millimeter-wave spectrometer for the Green Bank Telescope

NASA Astrophysics Data System (ADS)

Sieth, Matthew; Devaraj, Kiruthika; Voll, Patricia; Church, Sarah; Gawande, Rohit; Cleary, Kieran; Readhead, Anthony C. S.; Kangaslahti, Pekka; Samoska, Lorene; Gaier, Todd; Goldsmith, Paul F.; Harris, Andrew I.; Gundersen, Joshua O.; Frayer, David; White, Steve; Egan, Dennis; Reeves, Rodrigo

2014-07-01

We report on the development of Argus, a 16-pixel spectrometer, which will enable fast astronomical imaging over the 85-116 GHz band. Each pixel includes a compact heterodyne receiver module, which integrates two InP MMIC low-noise amplifiers, a coupled-line bandpass filter and a sub-harmonic Schottky diode mixer. The receiver signals are routed to and from the multi-chip MMIC modules with multilayer high frequency printed circuit boards, which includes LO splitters and IF amplifiers. Microstrip lines on flexible circuitry are used to transport signals between temperature stages. The spectrometer frontend is designed to be scalable, so that the array design can be reconfigured for future instruments with hundreds of pixels. Argus is scheduled to be commissioned at the Robert C. Byrd Green Bank Telescope in late 2014. Preliminary data for the first Argus pixels are presented.

Architectures for Cognitive Systems

DTIC Science & Technology

2010-02-01

highly modular many- node chip was designed which addressed power efficiency to the maximum extent possible. Each node contains an Asynchronous Field...optimization to perform complex cognitive computing operations. This project focused on the design of the core and integration across a four node chip . A...follow on project will focus on creating a 3 dimensional stack of chips that is enabled by the low power usage. The chip incorporates structures to

Advanced modulation technology development for earth station demodulator applications. Coded modulation system development

NASA Technical Reports Server (NTRS)

Miller, Susan P.; Kappes, J. Mark; Layer, David H.; Johnson, Peter N.

1990-01-01

A jointly optimized coded modulation system is described which was designed, built, and tested by COMSAT Laboratories for NASA LeRC which provides a bandwidth efficiency of 2 bits/s/Hz at an information rate of 160 Mbit/s. A high speed rate 8/9 encoder with a Viterbi decoder and an Octal PSK modem are used to achieve this. The BER performance is approximately 1 dB from the theoretically calculated value for this system at a BER of 5 E-7 under nominal conditions. The system operates in burst mode for downlink applications and tests have demonstrated very little degradation in performance with frequency and level offset. Unique word miss rate measurements were conducted which demonstrate reliable acquisition at low values of Eb/No. Codec self tests have verified the performance of this subsystem in a stand alone mode. The codec is capable of operation at a 200 Mbit/s information rate as demonstrated using a codec test set which introduces noise digitally. The measured performance is within 0.2 dB of the computer simulated predictions. A gate array implementation of the most time critical element of the high speed Viterbi decoder was completed. This gate array add-compare-select chip significantly reduces the power consumption and improves the manufacturability of the decoder. This chip has general application in the implementation of high speed Viterbi decoders.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications.

PubMed

Kirk, Andrew G; Plant, David V; Szymanski, Ted H; Vranesic, Zvonko G; Tooley, Frank A P; Rolston, David R; Ayliffe, Michael H; Lacroix, Frederic K; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F

2003-05-10

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design and implementation of a modulator-based free-space optical backplane for multiprocessor applications

NASA Astrophysics Data System (ADS)

Kirk, Andrew G.; Plant, David V.; Szymanski, Ted H.; Vranesic, Zvonko G.; Tooley, Frank A. P.; Rolston, David R.; Ayliffe, Michael H.; Lacroix, Frederic K.; Robertson, Brian; Bernier, Eric; Brosseau, Daniel F.

2003-05-01

Design and implementation of a free-space optical backplane for multiprocessor applications is presented. The system is designed to interconnect four multiprocessor nodes that communicate by using multiplexed 32-bit packets. Each multiprocessor node is electrically connected to an optoelectronic VLSI chip which implements the hyperplane interconnection architecture. The chips each contain 256 optical transmitters (implemented as dual-rail multiple quantum-well modulators) and 256 optical receivers. A rigid free-space microoptical interconnection system that interconnects the transceiver chips in a 512-channel unidirectional ring is implemented. Full design, implementation, and operational details are provided.

Design and Experimental Verification of a 0.19 V 53 μW 65 nm CMOS Integrated Supply-Sensing Sensor With a Supply-Insensitive Temperature Sensor and an Inductive-Coupling Transmitter for a Self-Powered Bio-sensing System Using a Biofuel Cell.

PubMed

Kobayashi, Atsuki; Ikeda, Kei; Ogawa, Yudai; Kai, Hiroyuki; Nishizawa, Matsuhiko; Nakazato, Kazuo; Niitsu, Kiichi

2017-12-01

In this paper, we present a self-powered bio-sensing system with the capability of proximity inductive-coupling communication for supply sensing and temperature monitoring. The proposed bio-sensing system includes a biofuel cell as a power source and a sensing frontend that is associated with the CMOS integrated supply-sensing sensor. The sensor consists of a digital-based gate leakage timer, a supply-insensitive time-domain temperature sensor, and a current-driven inductive-coupling transmitter and achieves low-voltage operation. The timer converts the output voltage from a biofuel cell to frequency. The temperature sensor provides a pulse width modulation (PWM) output that is not dependent on the supply voltage, and the associated inductive-coupling transmitter enables proximity communication. A test chip was fabricated in 65 nm CMOS technology and consumed 53 μW with a supply voltage of 190 mV. The low-voltage-friendly design satisfied the performance targets of each integrated sensor without any trimming. The chips allowed us to successfully demonstrate proximity communication with an asynchronous receiver, and the measurement results show the potential for self-powered operation using biofuel cells. The analysis and experimental verification of the system confirmed their robustness.

Research on Automatic Positioning System of Ultrasonic Testing of Wind Turbine Blade Flaws

NASA Astrophysics Data System (ADS)

Liu, Q. X.; Wang, Z. H.; Long, S. G.; Cai, M.; Cai, M.; Wang, X.; Chen, X. Y.; Bu, J. L.

2017-11-01

Ultrasonic testing technology has been used essentially in non-destructive testing of wind turbine blades. However, it is fact that the ultrasonic flaw detection method has inefficiently employed in recent years. This is because the testing result will illustrate a small deviation due to the artificial, environmental and technical factors. Therefore, it is an urgent technical demand for engineers to test the various flaws efficiently and quickly. An automatic positioning system has been designed in this paper to record the moving coordinates and the target distance in real time. Simultaneously, it could launch and acquire the sonic wave automatically. The ADNS-3080 optoelectronic chip is manufactured by Agilent Technologies Inc, which is also utilized in the system. With the combination of the chip, the power conversion module and the USB transmission module, the collected data can be transmitted from the upper monitor to the hardware that could process and control the data through software programming. An experiment has been designed to prove the reliability of automotive positioning system. The result has been validated by comparing the result collected form LABVIEW and actual plots on Perspex plane, it concludes that the system possesses high accuracy and magnificent meanings in practical engineering.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

PubMed

Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

2018-04-01

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Frequency non-degenerate phase-sensitive optical parametric amplification based on four-wave-mixing in width-modulated silicon waveguides.

PubMed

Wang, Zhaolu; Liu, Hongjun; Sun, Qibing; Huang, Nan; Li, Xuefeng

2014-12-15

A width-modulated silicon waveguide is proposed to realize non-degenerate phase sensitive optical parametric amplification. It is found that the relative phase at the input of the phase sensitive amplifier (PSA) θIn-PSA can be tuned by tailoring the width and length of the second segment of the width-modulated silicon waveguide, which will influence the gain in the parametric amplification process. The maximum gain of PSA is larger by 9 dB compared with the phase insensitive amplifier (PIA) gain, and the gain bandwidth of PSA is larger by 35 nm compared with the gain bandwidth of PIA. Our on-chip PSA can find important potential applications in highly integrated optical circuits for optical chip-to-chip communication and computers.

On-chip WDM mode-division multiplexing interconnection with optional demodulation function.

PubMed

Ye, Mengyuan; Yu, Yu; Chen, Guanyu; Luo, Yuchan; Zhang, Xinliang

2015-12-14

We propose and fabricate a wavelength-division-multiplexing (WDM) compatible and multi-functional mode-division-multiplexing (MDM) integrated circuit, which can perform the mode conversion and multiplexing for the incoming multipath WDM signals, avoiding the wavelength conflict. An phase-to-intensity demodulation function can be optionally applied within the circuit while performing the mode multiplexing. For demonstration, 4 × 10 Gb/s non-return-to-zero differential phase shift keying (NRZ-DPSK) signals are successfully processed, with open and clear eye diagrams. Measured bit error ratio (BER) results show less than 1 dB receive sensitivity variation for three modes and four wavelengths with demodulation. In the case without demodulation, the average power penalties at 4 wavelengths are -1.5, -3 and -3.5 dB for TE₀-TE₀, TE₀-TE₁ and TE₀-TE₂ mode conversions, respectively. The proposed flexible scheme can be used at the interface of long-haul and on-chip communication systems.

A Very Low Cost BCH Decoder for High Immunity of On-Chip Memories

NASA Astrophysics Data System (ADS)

Seo, Haejun; Han, Sehwan; Heo, Yoonseok; Cho, Taewon

BCH(Bose-Chaudhuri-Hoquenbhem) code, a type of block codes-cyclic codes, has very strong error-correcting ability which is vital for performing the error protection on the memory system. BCH code has many kinds of dual algorithms, PGZ(Pererson-Gorenstein-Zierler) algorithm out of them is advantageous in view of correcting the errors through the simple calculation in t value. However, this is problematic when this becomes 0 (divided by zero) in case ν ≠ t. In this paper, the circuit would be simplified by suggesting the multi-mode hardware architecture in preparation that v were 0~3. First, production cost would be less thanks to the smaller number of gates. Second, lessening power consumption could lengthen the recharging period. The very low cost and simple datapath make our design a good choice in small-footprint SoC(System on Chip) as ECC(Error Correction Code/Circuit) in memory system.

Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

PubMed

Yu, Theodore; Cauwenberghs, Gert

2009-01-01

We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

Microscale Symmetrical Electroporator Array as a Versatile Molecular Delivery System

NASA Astrophysics Data System (ADS)

Ouyang, Mengxing; Hill, Winfield; Lee, Jung Hyun; Hur, Soojung Claire

2017-03-01

Successful developments of new therapeutic strategies often rely on the ability to deliver exogenous molecules into cytosol. We have developed a versatile on-chip vortex-assisted electroporation system, engineered to conduct sequential intracellular delivery of multiple molecules into various cell types at low voltage in a dosage-controlled manner. Micro-patterned planar electrodes permit substantial reduction in operational voltages and seamless integration with an existing microfluidic technology. Equipped with real-time process visualization functionality, the system enables on-chip optimization of electroporation parameters for cells with varying properties. Moreover, the system’s dosage control and multi-molecular delivery capabilities facilitate intracellular delivery of various molecules as a single agent or in combination and its utility in biological research has been demonstrated by conducting RNA interference assays. We envision the system to be a powerful tool, aiding a wide range of applications, requiring single-cell level co-administrations of multiple molecules with controlled dosages.

Mode selecting switch using multimode interference for on-chip optical interconnects.

PubMed

Priti, Rubana B; Pishvai Bazargani, Hamed; Xiong, Yule; Liboiron-Ladouceur, Odile

2017-10-15

A novel mode selecting switch (MSS) is experimentally demonstrated for on-chip mode-division multiplexing (MDM) optical interconnects. The MSS consists of a Mach-Zehnder interferometer with tapered multi-mode interference couplers and TiN thermo-optic phase shifters for conversion and switching between the optical data encoded on the fundamental and first-order quasi-transverse electric (TE) modes. The C-band MSS exhibits a >25  dB switching extinction ratio and < -12 dB crosstalk. We validate the dynamic switching with a 25.8 kHz gating signal measuring switching times for both TE0 and TE1 modes of <10.9  μs. All channels exhibit less than 1.7 dB power penalty at a 10 -12 bit error rate, while switching the non-return-to-zero PRBS-31 data signals at 10  Gb/s.

The use of multi criteria analysis to compare the operating scenarios of the hybrid generation system of wind turbines, photovoltaic modules and a fuel cell

NASA Astrophysics Data System (ADS)

Ceran, Bartosz

2017-11-01

The paper presents the results of the use of multi-criteria analysis to compare hybrid power generation system collaboration scenarios (HSW) consisting of wind turbines, solar panels and energy storage electrolyzer - PEM type fuel cell with electricity system. The following scenarios were examined: the base S-I-hybrid system powers the off-grid mode receiver, S-II, S-III, S-IV scenarios-electricity system covers 25%, 50%, 75% of energy demand by the recipient. The effect of weights of the above-mentioned criteria on the final result of the multi-criteria analysis was examined.

Visible high power fiber coupled diode lasers

NASA Astrophysics Data System (ADS)

Köhler, Bernd; Drovs, Simon; Stoiber, Michael; Dürsch, Sascha; Kissel, Heiko; Könning, Tobias; Biesenbach, Jens; König, Harald; Lell, Alfred; Stojetz, Bernhard; Löffler, Andreas; Strauß, Uwe

2018-02-01

In this paper we report on further development of fiber coupled high-power diode lasers in the visible spectral range. New visible laser modules presented in this paper include the use of multi single emitter arrays @ 450 nm leading to a 120 W fiber coupled unit with a beam quality of 44 mm x mrad, as well as very compact modules with multi-W output power from 405 nm to 640 nm. However, as these lasers are based on single emitters, power scaling quickly leads to bulky laser units with a lot of optical components to be aligned. We also report on a new approach based on 450 nm diode laser bars, which dramatically reduces size and alignment effort. These activities were performed within the German government-funded project "BlauLas": a maximum output power of 80 W per bar has been demonstrated @ 450 nm. We show results of a 200 μm NA0.22 fiber coupled 35 W source @ 450 nm, which has been reduced in size by a factor of 25 compared to standard single emitter approach. In addition, we will present a 200 μm NA0.22 fiber coupled laser unit with an output power of 135 W.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Menglu; Tu, K. N., E-mail: kntu@ucla.edu; Kim, Dong Wook

Thermal-crosstalk induced thermomigration failure in un-powered microbumps has been found in 2.5D integrated circuit (IC) circuit. In 2.5D IC, a Si interposer was used between a polymer substrate and a device chip which has transistors. The interposer has no transistors. If transistors are added to the interposer chip, it becomes 3D IC. In our test structure, there are two Si chips placed horizontally on a Si interposer. The vertical connections between the interposer and the Si chips are through microbumps. We powered one daisy chain of the microbumps under one Si chip; however, the un-powered microbumps in the neighboring chipmore » are failed with big holes in the solder layer. We find that Joule heating from the powered microbumps is transferred horizontally to the bottom of the neighboring un-powered microbumps, and creates a large temperature gradient, in the order of 1000 °C/cm, through the un-powered microbumps in the neighboring chip, so the latter failed by thermomigration. In addition, we used synchrotron radiation tomography to compare three sets of microbumps in the test structure: microbumps under electromigration, microbumps under thermomigration, and microbumps under a constant temperature thermal annealing. The results show that the microbumps under thermomigration have the largest damage. Furthermore, simulation of temperature distribution in the test structure supports the finding of thermomigration.« less

Self-powered integrated systems-on-chip (energy chip)

NASA Astrophysics Data System (ADS)

Hussain, M. M.; Fahad, H.; Rojas, J.; Hasan, M.; Talukdar, A.; Oommen, J.; Mink, J.

2010-04-01

In today's world, consumer driven technology wants more portable electronic gadgets to be developed, and the next big thing in line is self-powered handheld devices. Therefore to reduce the power consumption as well as to supply sufficient power to run those devices, several critical technical challenges need to be overcome: a. Nanofabrication of macro/micro systems which incorporates the direct benefit of light weight (thus portability), low power consumption, faster response, higher sensitivity and batch production (low cost). b. Integration of advanced nano-materials to meet the performance/cost benefit trend. Nano-materials may offer new functionalities that were previously underutilized in the macro/micro dimension. c. Energy efficiency to reduce power consumption and to supply enough power to meet that low power demand. We present a pragmatic perspective on a self-powered integrated System on Chip (SoC). We envision the integrated device will have two objectives: low power consumption/dissipation and on-chip power generation for implementation into handheld or remote technologies for defense, space, harsh environments and medical applications. This paper provides insight on materials choices, intelligent circuit design, and CMOS compatible integration.

An experimental investigation of using carbon foam-PCM-MWCNTs composite materials for thermal management of electronic devices under pulsed power modes

NASA Astrophysics Data System (ADS)

Alshaer, W. G.; Rady, M. A.; Nada, S. A.; Palomo Del Barrio, Elena; Sommier, Alain

2017-02-01

The present article reports on a detailed experimental investigation of using carbon foam-PCM-MWCNTs composite materials for thermal management (TM) of electronic devices subjected to pulsed power. The TM module was fabricated by infiltrating paraffin wax (RT65) as a phase change material (PCM) and multi walled carbon nanotubes (MWCNTs) as a thermal conductivity enhancer in a carbon foam as a base structure. Two carbon foam materials of low and high values of thermal conductivities, CF20 and KL1-250 (3.1 and 40 W/m K), were tested as a base structure for the TM modules. Tests were conducted at different power intensities and power cycling/loading modes. Results showed that for all power varying modes and all carbon foams, the infiltration of RT65 into carbon foam reduces the temperature of TM module and results in damping the temperature spikes height. Infiltration of MWCNTS into RT65 further improves the effectiveness of TM module. Temperature damping was more pronounced in stand-alone pulsed power cycles as compared to pulsed power spikes modes. The effectiveness of inclusion of RT65 and RT65/MWCNTs in damping the temperature spikes height is remarkable in TM modules based on KL1-250 as compared to CF-20.

Improvement of modulation bandwidth in electroabsorption-modulated laser by utilizing the resonance property in bonding wire.

PubMed

Kwon, Oh Kee; Han, Young Tak; Baek, Yong Soon; Chung, Yun C

2012-05-21

We present and demonstrate a simple and cost-effective technique for improving the modulation bandwidth of electroabsorption-modulated laser (EML). This technique utilizes the RF resonance caused by the EML chip (i.e., junction capacitance) and bonding wire (i.e, wire inductance). We analyze the effects of the lengths of the bonding wires on the frequency responses of EML by using an equivalent circuit model. To verify this analysis, we package a lumped EML chip on the sub-mount and measure its frequency responses. The results show that, by using the proposed technique, we can increase the modulation bandwidth of EML from ~16 GHz to ~28 GHz.

On-chip Magnetic Separation and Cell Encapsulation in Droplets†

PubMed Central

Chen, Aaron; Byvank, Tom; Chang, Woo-Jin; Bharde, Atul; Vieira, Greg; Miller, Brandon; Chalmers, Jeffrey J.; Bashir, Rashid; Sooryakumar, Ratnasingham

2014-01-01

The demand for high-throughput single cell assays is gaining importance because of the heterogeneity of many cell suspensions, even after significant initial sorting. These suspensions may display cell-to-cell variability at the gene expression level that could impact single cell functional genomics, cancer, stem-cell research and drug screening. The on-chip monitoring of individual cells in an isolated environment would prevent cross-contamination, provide high recovery yield, and enable study of biological traits at a single cell level. These advantages of on-chip biological experiments is a significant improvement for myriad of cell analyses over conventional methods, which require bulk samples providing only averaged information on cell metabolism. We report on a device that integrates mobile magnetic trap array with microfluidic technology to provide, combined functionality of separation of immunomagnetically labeled cells or magnetic beads and their encapsulation with reagents into pico-liter droplets. This scheme of simultaneous reagent delivery and compartmentalization of the cells immediately after sorting, all performed seamlessly within the same chip, offers unique advantages such as the ability to capture cell traits as originated from its native environment, reduced chance of contamination, minimal use and freshness of the reagent solution that reacts only with separated objects, and tunable encapsulation characteristics independent of the input flow. In addition to the demonstrated preliminary cell viability assay, the device can potentially be integrated with other up- or downstream on-chip modules to become a powerful single-cell analysis tool. PMID:23370785

Microfabricated rankine cycle steam turbine for power generation and methods of making the same

NASA Technical Reports Server (NTRS)

Muller, Norbert (Inventor); Lee, Changgu (Inventor); Frechette, Luc (Inventor)

2009-01-01

In accordance with the present invention, an integrated micro steam turbine power plant on-a-chip has been provided. The integrated micro steam turbine power plant on-a-chip of the present invention comprises a miniature electric power generation system fabricated using silicon microfabrication technology and lithographic patterning. The present invention converts heat to electricity by implementing a thermodynamic power cycle on a chip. The steam turbine power plant on-a-chip generally comprises a turbine, a pump, an electric generator, an evaporator, and a condenser. The turbine is formed by a rotatable, disk-shaped rotor having a plurality of rotor blades disposed thereon and a plurality of stator blades. The plurality of stator blades are interdigitated with the plurality of rotor blades to form the turbine. The generator is driven by the turbine and converts mechanical energy into electrical energy.

Towards a Multifunctional Electrochemical Sensing and Niosome Generation Lab-on-Chip Platform Based on a Plug-and-Play Concept.

PubMed

Kara, Adnane; Rouillard, Camille; Mathault, Jessy; Boisvert, Martin; Tessier, Frédéric; Landari, Hamza; Melki, Imene; Laprise-Pelletier, Myriam; Boisselier, Elodie; Fortin, Marc-André; Boilard, Eric; Greener, Jesse; Miled, Amine

2016-05-28

In this paper, we present a new modular lab on a chip design for multimodal neurotransmitter (NT) sensing and niosome generation based on a plug-and-play concept. This architecture is a first step toward an automated platform for an automated modulation of neurotransmitter concentration to understand and/or treat neurodegenerative diseases. A modular approach has been adopted in order to handle measurement or drug delivery or both measurement and drug delivery simultaneously. The system is composed of three fully independent modules: three-channel peristaltic micropumping system, a three-channel potentiostat and a multi-unit microfluidic system composed of pseudo-Y and cross-shape channels containing a miniature electrode array. The system was wirelessly controlled by a computer interface. The system is compact, with all the microfluidic and sensing components packaged in a 5 cm × 4 cm × 4 cm box. Applied to serotonin, a linear calibration curve down to 0.125 mM, with a limit of detection of 31 μ M was collected at unfunctionalized electrodes. Added sensitivity and selectivity was achieved by incorporating functionalized electrodes for dopamine sensing. Electrode functionalization was achieved with gold nanoparticles and using DNA and o-phenylene diamine polymer. The as-configured platform is demonstrated as a central component toward an "intelligent" drug delivery system based on a feedback loop to monitor drug delivery.

Towards a Multifunctional Electrochemical Sensing and Niosome Generation Lab-on-Chip Platform Based on a Plug-and-Play Concept

PubMed Central

Kara, Adnane; Rouillard, Camille; Mathault, Jessy; Boisvert, Martin; Tessier, Frédéric; Landari, Hamza; Melki, Imene; Laprise-Pelletier, Myriam; Boisselier, Elodie; Fortin, Marc-André; Boilard, Eric; Greener, Jesse; Miled, Amine

2016-01-01

In this paper, we present a new modular lab on a chip design for multimodal neurotransmitter (NT) sensing and niosome generation based on a plug-and-play concept. This architecture is a first step toward an automated platform for an automated modulation of neurotransmitter concentration to understand and/or treat neurodegenerative diseases. A modular approach has been adopted in order to handle measurement or drug delivery or both measurement and drug delivery simultaneously. The system is composed of three fully independent modules: three-channel peristaltic micropumping system, a three-channel potentiostat and a multi-unit microfluidic system composed of pseudo-Y and cross-shape channels containing a miniature electrode array. The system was wirelessly controlled by a computer interface. The system is compact, with all the microfluidic and sensing components packaged in a 5 cm × 4 cm × 4 cm box. Applied to serotonin, a linear calibration curve down to 0.125 mM, with a limit of detection of 31 μM was collected at unfunctionalized electrodes. Added sensitivity and selectivity was achieved by incorporating functionalized electrodes for dopamine sensing. Electrode functionalization was achieved with gold nanoparticles and using DNA and o-phenylene diamine polymer. The as-configured platform is demonstrated as a central component toward an “intelligent” drug delivery system based on a feedback loop to monitor drug delivery. PMID:27240377

A distributed control approach for power and energy management in a notional shipboard power system

NASA Astrophysics Data System (ADS)

Shen, Qunying

The main goal of this thesis is to present a power control module (PCON) based approach for power and energy management and to examine its control capability in shipboard power system (SPS). The proposed control scheme is implemented in a notional medium voltage direct current (MVDC) integrated power system (IPS) for electric ship. To realize the control functions such as ship mode selection, generator launch schedule, blackout monitoring, and fault ride-through, a PCON based distributed power and energy management system (PEMS) is developed. The control scheme is proposed as two-layer hierarchical architecture with system level on the top as the supervisory control and zonal level on the bottom as the decentralized control, which is based on the zonal distribution characteristic of the notional MVDC IPS that was proposed as one of the approaches for Next Generation Integrated Power System (NGIPS) by Norbert Doerry. Several types of modules with different functionalities are used to derive the control scheme in detail for the notional MVDC IPS. Those modules include the power generation module (PGM) that controls the function of generators, the power conversion module (PCM) that controls the functions of DC/DC or DC/AC converters, etc. Among them, the power control module (PCON) plays a critical role in the PEMS. It is the core of the control process. PCONs in the PEMS interact with all the other modules, such as power propulsion module (PPM), energy storage module (ESM), load shedding module (LSHED), and human machine interface (HMI) to realize the control algorithm in PEMS. The proposed control scheme is implemented in real time using the real time digital simulator (RTDS) to verify its validity. To achieve this, a system level energy storage module (SESM) and a zonal level energy storage module (ZESM) are developed in RTDS to cooperate with PCONs to realize the control functionalities. In addition, a load shedding module which takes into account the reliability of power supply (in terms of quality of service) is developed. This module can supply uninterruptible power to the mission critical loads. In addition, a multi-agent system (MAS) based framework is proposed to implement the PCON based PEMS through a hardware setup that is composed of MAMBA boards and FPGA interface. Agents are implemented using Java Agent DEvelopment Framework (JADE). Various test scenarios were tested to validate the approach.

Design and fabricate multi channel microfluidic mold on top of glass slide using SU-8

NASA Astrophysics Data System (ADS)

Azman, N. A. N.; Rajapaksha, R. D. A. A.; Uda, M. N. A.; Hashim, U.

2017-09-01

Microfluidic is the study of fluid in microscale. Microfluidics provides miniaturized fluidic networks for processing and analyzing liquids in the nanoliter to milliliter range. Microfluidic device comprises of some essential segments or structure that are micromixer, microchannel and microchamber. The SU-8 mold is known as the most used technique in microfluidic fabrication due to the characteristic of very gooey polymer that can be spread over a thickness. In this study, in order to reduce the fabrication cost, the development and fabrication of SU-8 mold is replace by using a glass plate instead of silicon wafer which is used in the previous research. We designed a microfluidic chip for use with an IDE sensors to conduct multiplex detection of multiple channels. The microfluidic chip was designed to include multiplex detection for pathogen that consists of multiple channels of simultaneous results. The multi-channel microfluidic chip was designed, including the fluid outlet and inlet. A multi-channel microfluidic chip was used for pathogen detection. This paper sum up the fabrication of lab SU-8 mold using glass slide.

Deterministic Integration of Quantum Dots into on-Chip Multimode Interference Beamsplitters Using in Situ Electron Beam Lithography

NASA Astrophysics Data System (ADS)

Schnauber, Peter; Schall, Johannes; Bounouar, Samir; Höhne, Theresa; Park, Suk-In; Ryu, Geun-Hwan; Heindel, Tobias; Burger, Sven; Song, Jin-Dong; Rodt, Sven; Reitzenstein, Stephan

2018-04-01

The development of multi-node quantum optical circuits has attracted great attention in recent years. In particular, interfacing quantum-light sources, gates and detectors on a single chip is highly desirable for the realization of large networks. In this context, fabrication techniques that enable the deterministic integration of pre-selected quantum-light emitters into nanophotonic elements play a key role when moving forward to circuits containing multiple emitters. Here, we present the deterministic integration of an InAs quantum dot into a 50/50 multi-mode interference beamsplitter via in-situ electron beam lithography. We demonstrate the combined emitter-gate interface functionality by measuring triggered single-photon emission on-chip with $g^{(2)}(0) = 0.13\\pm 0.02$. Due to its high patterning resolution as well as spectral and spatial control, in-situ electron beam lithography allows for integration of pre-selected quantum emitters into complex photonic systems. Being a scalable single-step approach, it paves the way towards multi-node, fully integrated quantum photonic chips.

Fabrication of five-level ultraplanar micromirror arrays by flip-chip assembly

NASA Astrophysics Data System (ADS)

Michalicek, M. Adrian; Bright, Victor M.

2001-10-01

This paper reports a detailed study of the fabrication of various piston, torsion, and cantilever style micromirror arrays using a novel, simple, and inexpensive flip-chip assembly technique. Several rectangular and polar arrays were commercially prefabricated in the MUMPs process and then flip-chip bonded to form advanced micromirror arrays where adverse effects typically associated with surface micromachining were removed. These arrays were bonded by directly fusing the MUMPs gold layers with no complex preprocessing. The modules were assembled using a computer-controlled, custom-built flip-chip bonding machine. Topographically opposed bond pads were designed to correct for slight misalignment errors during bonding and typically result in less than 2 micrometers of lateral alignment error. Although flip-chip micromirror performance is briefly discussed, the means used to create these arrays is the focus of the paper. A detailed study of flip-chip process yield is presented which describes the primary failure mechanisms for flip-chip bonding. Studies of alignment tolerance, bonding force, stress concentration, module planarity, bonding machine calibration techniques, prefabrication errors, and release procedures are presented in relation to specific observations in process yield. Ultimately, the standard thermo-compression flip-chip assembly process remains a viable technique to develop highly complex prototypes of advanced micromirror arrays.

Catastrophic Fault Recovery with Self-Reconfigurable Chips

NASA Technical Reports Server (NTRS)

Zheng, Will Hua; Marzwell, Neville I.; Chau, Savio N.

2006-01-01

Mission critical systems typically employ multi-string redundancy to cope with possible hardware failure. Such systems are only as fault tolerant as there are many redundant strings. Once a particular critical component exhausts its redundant spares, the multi-string architecture cannot tolerate any further hardware failure. This paper aims at addressing such catastrophic faults through the use of 'Self-Reconfigurable Chips' as a last resort effort to 'repair' a faulty critical component.

A dynamic multi-level optimal design method with embedded finite-element modeling for power transformers

NASA Astrophysics Data System (ADS)

Zhang, Yunpeng; Ho, Siu-lau; Fu, Weinong

2018-05-01

This paper proposes a dynamic multi-level optimal design method for power transformer design optimization (TDO) problems. A response surface generated by second-order polynomial regression analysis is updated dynamically by adding more design points, which are selected by Shifted Hammersley Method (SHM) and calculated by finite-element method (FEM). The updating stops when the accuracy requirement is satisfied, and optimized solutions of the preliminary design are derived simultaneously. The optimal design level is modulated through changing the level of error tolerance. Based on the response surface of the preliminary design, a refined optimal design is added using multi-objective genetic algorithm (MOGA). The effectiveness of the proposed optimal design method is validated through a classic three-phase power TDO problem.

White LED visible light communication technology research

NASA Astrophysics Data System (ADS)

Yang, Chao

2017-03-01

Visible light communication is a new type of wireless optical communication technology. White LED to the success of development, the LED lighting technology is facing a new revolution. Because the LED has high sensitivity, modulation, the advantages of good performance, large transmission power, can make it in light transmission light signal at the same time. Use white LED light-emitting characteristics, on the modulation signals to the visible light transmission, can constitute a LED visible light communication system. We built a small visible optical communication system. The system composition and structure has certain value in the field of practical application, and we also research the key technology of transmitters and receivers, the key problem has been resolved. By studying on the optical and LED the characteristics of a high speed modulation driving circuit and a high sensitive receiving circuit was designed. And information transmission through the single chip microcomputer test, a preliminary verification has realized the data transmission function.

Fabrication and demonstration of 1 × 8 silicon-silica multi-chip switch based on optical phased array

NASA Astrophysics Data System (ADS)

Katayose, Satomi; Hashizume, Yasuaki; Itoh, Mikitaka

2016-08-01

We experimentally demonstrated a 1 × 8 silicon-silica hybrid thermo-optic switch based on an optical phased array using a multi-chip integration technique. The switch consists of a silicon chip with optical phase shifters and two silica-based planar lightwave circuit (PLC) chips composed of optical couplers and fiber connections. We adopted a rib waveguide as the silicon waveguide to reduce the coupling loss and increase the alignment tolerance for coupling between silicon and silica waveguides. As a result, we achieved a fast switching response of 81 µs, a high extinction ratio of over 18 dB and a low insertion loss of 4.9-8.1 dB including a silicon-silica coupling loss of 0.5 ± 0.3 dB at a wavelength of 1.55 µm.

Open-access and multi-directional electroosmotic flow chip for positioning heterotypic cells.

PubMed

Terao, Kyohei; Kitazawa, Yuko; Yokokawa, Ryuji; Okonogi, Atsuhito; Kotera, Hidetoshi

2011-04-21

We propose a novel method of cell positioning using electroosmotic flow (EOF) to analyze cell-cell interactions. The EOF chip has an open-to-air configuration, is equipped with four electrodes to induce multi-directional EOF, and allows access of tools for liquid handling and of physical probes for cell measurements. Evaluation of the flow within this chip indicated that it controlled hydrodynamic transport of cells, in terms of both speed and direction. We also evaluated cell viability after EOF application and determined appropriate conditions for cell positioning. Two cells were successively positioned in pocket-like microstructures, one in each micropocket, by controlling the EOF direction. As an experimental demonstration, we observed contact interactions between two individual cells through gap junction channels. The EOF chip should provide ways to elucidate various cell-cell interactions between heterotypic cells.

The research of data acquisition system for Raman spectrometer

NASA Astrophysics Data System (ADS)

Cui, Xiao; Guo, Pan; Zhang, Yinchao; Chen, Siying; Chen, He; Chen, Wenbo

2011-11-01

Raman spectrometer has been widely used as an identification tool for analyzing material structure and composition in many fields. However, Raman scattering echo signal is very weak, about dozens of photons at most in one laser plus signal. Therefore, it is a great challenge to design a Raman spectrum data acquisition system which could accurately receive the weak echo signal. The system designed in this paper receives optical signals with the principle of photon counter and could detect single photon. The whole system consists of a photoelectric conversion module H7421-40 and a photo counting card including a field programmable gate array (FPGA) chip and a PCI9054 chip. The module H7421-40 including a PMT, an amplifier and a discriminator has high sensitivity on wavelength from 300nm to 720nm. The Center Wavelength is 580nm which is close to the excitation wavelength (532nm), QE 40% at peak wavelength, Count Sensitivity is 7.8*105(S-1PW-1) and Count Linearity is 1.5MHZ. In FPGA chip, the functions are divided into three parts: parameter setting module, controlling module, data collection and storage module. All the commands, parameters and data are transmitted between FPGA and computer by PCI9054 chip through the PCI interface. The result of experiment shows that the Raman spectrum data acquisition system is reasonable and efficient. There are three primary advantages of the data acquisition system: the first one is the high sensitivity with single photon detection capability; the second one is the high integrated level which means all the operation could be done by the photo counting card; and the last one is the high expansion ability because of the smart reconfigurability of FPGA chip.

System on chip module configured for event-driven architecture

DOEpatents

Robbins, Kevin; Brady, Charles E.; Ashlock, Tad A.

2017-10-17

A system on chip (SoC) module is described herein, wherein the SoC modules comprise a processor subsystem and a hardware logic subsystem. The processor subsystem and hardware logic subsystem are in communication with one another, and transmit event messages between one another. The processor subsystem executes software actors, while the hardware logic subsystem includes hardware actors, the software actors and hardware actors conform to an event-driven architecture, such that the software actors receive and generate event messages and the hardware actors receive and generate event messages.

Ring resonator-based on-chip modulation transformer for high-performance phase-modulated microwave photonic links.

PubMed

Zhuang, Leimeng; Taddei, Caterina; Hoekman, Marcel; Leinse, Arne; Heideman, René; van Dijk, Paulus; Roeloffzen, Chris

2013-11-04

In this paper, we propose and experimentally demonstrate a novel wideband on-chip photonic modulation transformer for phase-modulated microwave photonic links. The proposed device is able to transform phase-modulated optical signals into intensity-modulated versions (or vice versa) with nearly zero conversion of laser phase noise to intensity noise. It is constructed using waveguide-based ring resonators, which features simple architecture, stable operation, and easy reconfigurability. Beyond the stand-alone functionality, the proposed device can also be integrated with other functional building blocks of photonic integrated circuits (PICs) to create on-chip complex microwave photonic signal processors. As an application example, a PIC consisting of two such modulation transformers and a notch filter has been designed and realized in TriPleX(TM) waveguide technology. The realized device uses a 2 × 2 splitting circuit and 3 ring resonators with a free spectral range of 25 GHz, which are all equipped with continuous tuning elements. The device can perform phase-to-intensity modulation transform and carrier suppression simultaneously, which enables high-performance phase-modulated microwave photonics links (PM-MPLs). Associated with the bias-free and low-complexity advantages of the phase modulators, a single-fiber-span PM-MPL with a RF bandwidth of 12 GHz (3 dB-suppression band 6 to 18 GHz) has been demonstrated comprising the proposed PIC, where the achieved spurious-free dynamic range performance is comparable to that of Class-AB MPLs using low-biased Mach-Zehnder modulators.

Design of low noise imaging system

NASA Astrophysics Data System (ADS)

Hu, Bo; Chen, Xiaolai

2017-10-01

In order to meet the needs of engineering applications for low noise imaging system under the mode of global shutter, a complete imaging system is designed based on the SCMOS (Scientific CMOS) image sensor CIS2521F. The paper introduces hardware circuit and software system design. Based on the analysis of key indexes and technologies about the imaging system, the paper makes chips selection and decides SCMOS + FPGA+ DDRII+ Camera Link as processing architecture. Then it introduces the entire system workflow and power supply and distribution unit design. As for the software system, which consists of the SCMOS control module, image acquisition module, data cache control module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The imaging experimental results show that the imaging system exhibits a 2560*2160 pixel resolution, has a maximum frame frequency of 50 fps. The imaging quality of the system satisfies the requirement of the index.

Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

DTIC Science & Technology

2006-11-01

Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

A low-power high-speed ultra-wideband pulse radio transmission system.

PubMed

Wei Tang; Culurciello, E

2009-10-01

We present a low-power high-speed ultra-wideband (UWB) transmitter with a wireless transmission test platform. The system is specifically designed for low-power high-speed wireless implantable biosensors. The integrated transmitter consists of a compact pulse generator and a modulator. The circuit is fabricated in the 0.5-mum silicon-on-sapphire process and occupies 420 mum times 420 mum silicon area. The transmitter is capable of generating pulses with 1-ns width and the pulse rate can be controlled between 90 MHz and 270 MHz. We built a demonstration/testing system for the transmitter. The transmitter achieves a 14-Mb/s data rate. With 50% duty cycle data, the power consumption of the chip is between 10 mW and 21 mW when the transmission distance is from 3.2 to 4 m. The core circuit size is 70 mum times 130 mum.

VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

PubMed

Feng, Lichen; Li, Zunchao; Wang, Yuanfa

2018-02-01

Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

Numerical investigations of self- and cross-phase modulation effects in high-power fiber amplifiers (Conference Presentation)

NASA Astrophysics Data System (ADS)

Zunoubi, Mohammad R.; Anderson, Brian; Naderi, Shadi A.; Madden, Timothy J.; Dajani, Iyad

2017-03-01

The development of high-power fiber lasers is of great interest due to the advantages they offer relative to other laser technologies. Currently, the maximum power from a reportedly single-mode fiber amplifier stands at 10 kW. Though impressive, this power level was achieved at the cost of a large spectral linewidth, making the laser unsuitable for coherent or spectral beam combination techniques required to reach power levels necessary for airborne tactical applications. An effective approach in limiting the SBS effect is to insert an electro-optic phase modulator at the low-power end of a master oscillator power amplifier (MOPA) system. As a result, the optical power is spread among spectral sidebands; thus raising the overall SBS threshold of the amplifier. It is the purpose of this work to present a comprehensive numerical scheme that is based on the extended nonlinear Schrodinger equations that allows for accurate analysis of phase modulated fiber amplifier systems in relation to the group velocity dispersion and Kerr nonlinearities and their effect on the coherent beam combining efficiency. As such, we have simulated a high-power MOPA system modulated via filtered pseudo-random bit sequence format for different clock rates and power levels. We show that at clock rates of ≥30 GHz, the combination of GVD and self-phase modulation may lead to a drastic drop in beam combining efficiency at the multi-kW level. Furthermore, we extend our work to study the effect of cross-phase modulation where an amplifier is seeded with two laser sources.

A miniature electronic nose system based on an MWNT-polymer microsensor array and a low-power signal-processing chip.

PubMed

Chiu, Shih-Wen; Wu, Hsiang-Chiu; Chou, Ting-I; Chen, Hsin; Tang, Kea-Tiong

2014-06-01

This article introduces a power-efficient, miniature electronic nose (e-nose) system. The e-nose system primarily comprises two self-developed chips, a multiple-walled carbon nanotube (MWNT)-polymer based microsensor array, and a low-power signal-processing chip. The microsensor array was fabricated on a silicon wafer by using standard photolithography technology. The microsensor array comprised eight interdigitated electrodes surrounded by SU-8 "walls," which restrained the material-solvent liquid in a defined area of 650 × 760 μm(2). To achieve a reliable sensor-manufacturing process, we used a two-layer deposition method, coating the MWNTs and polymer film as the first and second layers, respectively. The low-power signal-processing chip included array data acquisition circuits and a signal-processing core. The MWNT-polymer microsensor array can directly connect with array data acquisition circuits, which comprise sensor interface circuitry and an analog-to-digital converter; the signal-processing core consists of memory and a microprocessor. The core executes the program, classifying the odor data received from the array data acquisition circuits. The low-power signal-processing chip was designed and fabricated using the Taiwan Semiconductor Manufacturing Company 0.18-μm 1P6M standard complementary metal oxide semiconductor process. The chip consumes only 1.05 mW of power at supply voltages of 1 and 1.8 V for the array data acquisition circuits and the signal-processing core, respectively. The miniature e-nose system, which used a microsensor array, a low-power signal-processing chip, and an embedded k-nearest-neighbor-based pattern recognition algorithm, was developed as a prototype that successfully recognized the complex odors of tincture, sorghum wine, sake, whisky, and vodka.

Functional differentiation of human pluripotent stem cells on a chip.

PubMed

Giobbe, Giovanni G; Michielin, Federica; Luni, Camilla; Giulitti, Stefano; Martewicz, Sebastian; Dupont, Sirio; Floreani, Annarosa; Elvassore, Nicola

2015-07-01

Microengineering human "organs-on-chips" remains an open challenge. Here, we describe a robust microfluidics-based approach for the differentiation of human pluripotent stem cells directly on a chip. Extrinsic signal modulation, achieved through optimal frequency of medium delivery, can be used as a parameter for improved germ layer specification and cell differentiation. Human cardiomyocytes and hepatocytes derived on chips showed functional phenotypes and responses to temporally defined drug treatments.

Towards a “Sample-In, Answer-Out” Point-of-Care Platform for Nucleic Acid Extraction and Amplification: Using an HPV E6/E7 mRNA Model System

PubMed Central

Gulliksen, Anja; Keegan, Helen; Martin, Cara; O'Leary, John; Solli, Lars A.; Falang, Inger Marie; Grønn, Petter; Karlgård, Aina; Mielnik, Michal M.; Johansen, Ib-Rune; Tofteberg, Terje R.; Baier, Tobias; Gransee, Rainer; Drese, Klaus; Hansen-Hagge, Thomas; Riegger, Lutz; Koltay, Peter; Zengerle, Roland; Karlsen, Frank; Ausen, Dag; Furuberg, Liv

2012-01-01

The paper presents the development of a “proof-of-principle” hands-free and self-contained diagnostic platform for detection of human papillomavirus (HPV) E6/E7 mRNA in clinical specimens. The automated platform performs chip-based sample preconcentration, nucleic acid extraction, amplification, and real-time fluorescent detection with minimal user interfacing. It consists of two modular prototypes, one for sample preparation and one for amplification and detection; however, a common interface is available to facilitate later integration into one single module. Nucleic acid extracts (n = 28) from cervical cytology specimens extracted on the sample preparation chip were tested using the PreTect HPV-Proofer and achieved an overall detection rate for HPV across all dilutions of 50%–85.7%. A subset of 6 clinical samples extracted on the sample preparation chip module was chosen for complete validation on the NASBA chip module. For 4 of the samples, a 100% amplification for HPV 16 or 33 was obtained at the 1 : 10 dilution for microfluidic channels that filled correctly. The modules of a “sample-in, answer-out” diagnostic platform have been demonstrated from clinical sample input through sample preparation, amplification and final detection. PMID:22235204

A site oriented supercomputer for theoretical physics: The Fermilab Advanced Computer Program Multi Array Processor System (ACMAPS)

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nash, T.; Atac, R.; Cook, A.

1989-03-06

The ACPMAPS multipocessor is a highly cost effective, local memory parallel computer with a hypercube or compound hypercube architecture. Communication requires the attention of only the two communicating nodes. The design is aimed at floating point intensive, grid like problems, particularly those with extreme computing requirements. The processing nodes of the system are single board array processors, each with a peak power of 20 Mflops, supported by 8 Mbytes of data and 2 Mbytes of instruction memory. The system currently being assembled has a peak power of 5 Gflops. The nodes are based on the Weitek XL Chip set. Themore » system delivers performance at approximately $300/Mflop. 8 refs., 4 figs.« less

Tissue Chips to aid drug development and modeling for rare diseases

PubMed Central

Low, Lucie A.; Tagle, Danilo A.

2016-01-01

Introduction The technologies used to design, create and use microphysiological systems (MPS, “tissue chips” or “organs-on-chips”) have progressed rapidly in the last 5 years, and validation studies of the functional relevance of these platforms to human physiology, and response to drugs for individual model organ systems, are well underway. These studies are paving the way for integrated multi-organ systems that can model diseases and predict drug efficacy and toxicology of multiple organs in real-time, improving the potential for diagnostics and development of novel treatments of rare diseases in the future. Areas covered This review will briefly summarize the current state of tissue chip research and highlight model systems where these microfabricated (or bioengineered) devices are already being used to screen therapeutics, model disease states, and provide potential treatments in addition to helping elucidate the basic molecular and cellular phenotypes of rare diseases. Expert opinion Microphysiological systems hold great promise and potential for modeling rare disorders, as well as for their potential use to enhance the predictive power of new drug therapeutics, plus potentially increase the statistical power of clinical trials while removing the inherent risks of these trials in rare disease populations. PMID:28626620

A smartphone controlled handheld microfluidic liquid handling system.

PubMed

Li, Baichen; Li, Lin; Guan, Allan; Dong, Quan; Ruan, Kangcheng; Hu, Ronggui; Li, Zhenyu

2014-10-21

Microfluidics and lab-on-a-chip technologies have made it possible to manipulate small volume liquids with unprecedented resolution, automation and integration. However, most current microfluidic systems still rely on bulky off-chip infrastructures such as compressed pressure sources, syringe pumps and computers to achieve complex liquid manipulation functions. Here, we present a handheld automated microfluidic liquid handling system controlled by a smartphone, which is enabled by combining elastomeric on-chip valves and a compact pneumatic system. As a demonstration, we show that the system can automatically perform all the liquid handling steps of a bead-based HIV1 p24 sandwich immunoassay on a multi-layer PDMS chip without any human intervention. The footprint of the system is 6 × 10.5 × 16.5 cm, and the total weight is 829 g including battery. Powered by a 12.8 V 1500 mAh Li battery, the system consumed 2.2 W on average during the immunoassay and lasted for 8.7 h. This handheld microfluidic liquid handling platform is generally applicable to many biochemical and cell-based assays requiring complex liquid manipulation and sample preparation steps such as FISH, PCR, flow cytometry and nucleic acid sequencing. In particular, the integration of this technology with read-out biosensors may help enable the realization of the long-sought Tricorder-like handheld in vitro diagnostic (IVD) systems.

Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

NASA Astrophysics Data System (ADS)

Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

2007-05-01

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

Radioistopes to Solar to High Energy Accelerators - Chip-Scale Energy Sources

NASA Astrophysics Data System (ADS)

Lal, Amit

2013-12-01

This talk will present MEMS based power sources that utilize radioisotopes, solar energy, and potentially nuclear energy through advancements in integration of new structures and materials within MEMS. Micro power harvesters can harness power from vibration, radioisotopes, light, sound, and biology may provide pathways to minimize or even eliminate batteries in sensor nodes. In this talk work on radioisotope thin films for MEMS will be include the self-reciprocating cantilever, betavoltaic cells, and high DC voltages. The self-reciprocating cantilever energy harvester allows small commercially viable amounts of radioisotopes to generate mW to Watts of power so that very reliable power sources that last 100s of years are possible. The tradeoffs between reliability and potential stigma with radioisotopes allow one to span a useful design space with reliability as a key parameter. These power sources provide pulsed power at three different time scales using mechanical, RF, and static extraction of energy from collected charge. Multi-use capability, both harvesting radioisotope power and local vibration energy extends the reliability of micro-power sources further.

Differences in chewing sounds of dry-crisp snacks by multivariate data analysis

NASA Astrophysics Data System (ADS)

De Belie, N.; Sivertsvik, M.; De Baerdemaeker, J.

2003-09-01

Chewing sounds of different types of dry-crisp snacks (two types of potato chips, prawn crackers, cornflakes and low calorie snacks from extruded starch) were analysed to assess differences in sound emission patterns. The emitted sounds were recorded by a microphone placed over the ear canal. The first bite and the first subsequent chew were selected from the time signal and a fast Fourier transformation provided the power spectra. Different multivariate analysis techniques were used for classification of the snack groups. This included principal component analysis (PCA) and unfold partial least-squares (PLS) algorithms, as well as multi-way techniques such as three-way PLS, three-way PCA (Tucker3), and parallel factor analysis (PARAFAC) on the first bite and subsequent chew. The models were evaluated by calculating the classification errors and the root mean square error of prediction (RMSEP) for independent validation sets. It appeared that the logarithm of the power spectra obtained from the chewing sounds could be used successfully to distinguish the different snack groups. When different chewers were used, recalibration of the models was necessary. Multi-way models distinguished better between chewing sounds of different snack groups than PCA on bite or chew separately and than unfold PLS. From all three-way models applied, N-PLS with three components showed the best classification capabilities, resulting in classification errors of 14-18%. The major amount of incorrect classifications was due to one type of potato chips that had a very irregular shape, resulting in a wide variation of the emitted sounds.

NASA Tech Briefs, July 2011

NASA Technical Reports Server (NTRS)

2011-01-01

Topics covered include: 1) Collaborative Clustering for Sensor Networks; 2) Teleoperated Marsupial Mobile Sensor Platform Pair for Telepresence Insertion Into Challenging Structures; 3) Automated Verification of Spatial Resolution in Remotely Sensed Imagery; 4) Electrical Connector Mechanical Seating Sensor; 5) In Situ Aerosol Detector; 6) Multi-Parameter Aerosol Scattering Sensor; 7) MOSFET Switching Circuit Protects Shape Memory Alloy Actuators; 8) Optimized FPGA Implementation of Multi-Rate FIR Filters Through Thread Decomposition; 9) Circuit for Communication Over Power Lines; 10) High-Efficiency Ka-Band Waveguide Two-Way Asymmetric Power Combiner; 11) 10-100 Gbps Offload NIC for WAN, NLR, and Grid Computing; 12) Pulsed Laser System to Simulate Effects of Cosmic Rays in Semiconductor Devices; 13) Flight Planning in the Cloud; 14) MPS Editor; 15) Object-Oriented Multi Disciplinary Design, Analysis, and Optimization Tool; 16) Cryogenic-Compatible Winchester Connector Mount and Retaining System for Composite Tubes; 17) Development of Position-Sensitive Magnetic Calorimeters for X-Ray Astronomy; 18) Planar Rotary Piezoelectric Motor Using Ultrasonic Horns; 19) Self-Rupturing Hermetic Valve; 20) Explosive Bolt Dual-Initiated from One Side; 21) Dampers for Stationary Labyrinth Seals; 22) Two-Arm Flexible Thermal Strap; 23) Carbon Dioxide Removal via Passive Thermal Approaches; 24) Polymer Electrolyte-Based Ambient Temperature Oxygen Microsensors for Environmental Monitoring; 25) Pressure Shell Approach to Integrated Environmental Protection; 26) Image Quality Indicator for Infrared Inspections; 27) Micro-Slit Collimators for X-Ray/Gamma-Ray Imaging; 28) Scatterometer-Calibrated Stability Verification Method; 29) Test Port for Fiber-Optic-Coupled Laser Altimeter; 30) Phase Retrieval System for Assessing Diamond Turning and Optical Surface Defects; 31) Laser Oscillator Incorporating a Wedged Polarization Rotator and a Porro Prism as Cavity Mirror; 32) Generic, Extensible, Configurable Push-Pull Framework for Large-Scale Science Missions; 33) Dynamic Loads Generation for Multi-Point Vibration Excitation Problems; 34) Optimal Control via Self-Generated Stochasticity; 35) Space-Time Localization of Plasma Turbulence Using Multiple Spacecraft Radio Links; 36) Surface Contact Model for Comets and Asteroids; 37) Dust Mitigation Vehicle; 38) Optical Coating Performance for Heat Reflectors of the JWST-ISIM Electronic Component; 39) SpaceCube Demonstration Platform; 40) Aperture Mask for Unambiguous Parity Determination in Long Wavelength Imagers; 41) Spaceflight Ka-Band High-Rate Radiation-Hard Modulator; 42) Enabling Disabled Persons to Gain Access to Digital Media; 43) Cytometer on a Chip; 44) Principles, Techniques, and Applications of Tissue Microfluidics; and 45) Two-Stage Winch for Kites and Tethered Balloons or Blimps.

Design and characterization of a novel power over fiber system integrating a high power diode laser

NASA Astrophysics Data System (ADS)

Perales, Mico; Yang, Mei-huan; Wu, Cheng-liang; Hsu, Chin-wei; Chao, Wei-sheng; Chen, Kun-hsein; Zahuranec, Terry

2017-02-01

High power 9xx nm diode lasers along with MH GoPower's (MHGP's) flexible line of Photovoltaic Power Converters (PPCs) are spurring high power applications for power over fiber (PoF), including applications for powering remote sensors and sensors monitoring high voltage equipment, powering high voltage IGBT gate drivers, converters used in RF over Fiber (RFoF) systems, and system power applications, including powering UAVs. In PoF, laser power is transmitted over fiber, and is converted to electricity by photovoltaic cells (packaged into Photovoltaic Power Converters, or PPCs) which efficiently convert the laser light. In this research, we design a high power multi-channel PoF system, incorporating a high power 976 nm diode laser, a cabling system with fiber break detection, and a multichannel PPC-module. We then characterizes system features such as its response time to system commands, the PPC module's electrical output stability, the PPC-module's thermal response, the fiber break detection system response, and the diode laser optical output stability. The high power PoF system and this research will serve as a scalable model for those interested in researching, developing, or deploying a high power, voltage isolated, and optically driven power source for high reliability utility, communications, defense, and scientific applications.

A CMOS ASIC Design for SiPM Arrays

PubMed Central

Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K.; Miyaoka, Robert S.; Rudell, Jacques C.

2012-01-01

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM). PMID:24825923

78 FR 77569 - Airworthiness Directives; Turbomeca S.A. Turboshaft Engines

Federal Register 2010, 2011, 2012, 2013, 2014

2013-12-24

... engines and, if a discrepancy is found, repair of the affected module. This AD was prompted by a ``chip... condition for the specified products. The MCAI states: A ``chip light illumination'' event in flight on an... prompted by a ``chip illumination event'' in flight on a Turbomeca S.A. Arriel 1 engine. We are issuing...

Advanced Grid Simulator for Multi-Megawatt Power Converter Testing and Certification

DOE Office of Scientific and Technical Information (OSTI.GOV)

Koralewicz, Przemyslaw; Gevorgian, Vahan; Wallen, Robb

2017-02-16

Grid integration testing of inverter-coupled renewable energy technologies is an essential step in the qualification of renewable energy and energy storage systems to ensure the stability of the power system. New types of devices must be thoroughly tested and validated for compliance with relevant grid codes and interconnection requirements. For this purpose, highly specialized custom-made testing equipment is needed to emulate various types of realistic grid conditions that are required by certification bodies or for research purposes. For testing multi-megawatt converters, a high power grid simulator capable of creating controlled grid conditions and meeting both power quality and dynamic characteristicsmore » is needed. This paper describes the new grid simulator concept based on ABB's medium voltage ACS6000 drive technology that utilizes advanced modulation and control techniques to create an unique testing platform for various multi-megawatt power converter systems. Its performance is demonstrated utilizing the test results obtained during commissioning activities at the National Renewable Energy Laboratory in Colorado, USA.« less

A triple-mode hexa-standard reconfigurable TI cross-coupled ΣΔ modulator

NASA Astrophysics Data System (ADS)

Prakash A. V, Jos; Jose, Babita R.; Mathew, Jimson; Jose, Bijoy A.

2017-07-01

Hardware reconfigurability is an attractive solution for modern multi-standard wireless systems. This paper analyses the performance and implementation of an efficient triple-mode hexa-standard reconfigurable sigma-delta (∑Δ) modulator designed for six different wireless communication standards. Enhanced noise-shaping characteristics and increased digitisation rate, obtained by time-interleaved cross-coupling of ∑Δ paths, have been utilised for the modulator design. Power/hardware efficiency and the capability to acclimate the requirements of wide hexa-standard specifications are achieved by introducing an advanced noise-shaping structure, the dual-extended architecture. Simulation results of the proposed architecture using Hspice shows that the proposed modulator obtains a peak signal-to-noise ratio of 83.4/80.2/67.8/61.5/60.8/51.03 dB for hexa-standards, i.e. GSM/Bluetooth/GPS/WCDMA/WLAN/WiMAX standards with significantly less hardware and low operating frequency. The proposed architecture is implemented in 45 nm CMOS process using a 1 V supply and 0.7 V input range with a power consumption of 1.93 mW. Both architectural- and transistor-level simulation results prove the effectiveness and feasibility of this architecture to accomplish multi-standard cellular communication characteristics.

Multi-DSP and FPGA based Multi-channel Direct IF/RF Digital receiver for atmospheric radar

NASA Astrophysics Data System (ADS)

Yasodha, Polisetti; Jayaraman, Achuthan; Kamaraj, Pandian; Durga rao, Meka; Thriveni, A.

2016-07-01

Modern phased array radars depend highly on digital signal processing (DSP) to extract the echo signal information and to accomplish reliability along with programmability and flexibility. The advent of ASIC technology has made various digital signal processing steps to be realized in one DSP chip, which can be programmed as per the application and can handle high data rates, to be used in the radar receiver to process the received signal. Further, recent days field programmable gate array (FPGA) chips, which can be re-programmed, also present an opportunity to utilize them to process the radar signal. A multi-channel direct IF/RF digital receiver (MCDRx) is developed at NARL, taking the advantage of high speed ADCs and high performance DSP chips/FPGAs, to be used for atmospheric radars working in HF/VHF bands. Multiple channels facilitate the radar t be operated in multi-receiver modes and also to obtain the wind vector with improved time resolution, without switching the antenna beam. MCDRx has six channels, implemented on a custom built digital board, which is realized using six numbers of ADCs for simultaneous processing of the six input signals, Xilinx vertex5 FPGA and Spartan6 FPGA, and two ADSPTS201 DSP chips, each of which performs one phase of processing. MCDRx unit interfaces with the data storage/display computer via two gigabit ethernet (GbE) links. One of the six channels is used for Doppler beam swinging (DBS) mode and the other five channels are used for multi-receiver mode operations, dedicatedly. Each channel has (i) ADC block, to digitize RF/IF signal, (ii) DDC block for digital down conversion of the digitized signal, (iii) decoding block to decode the phase coded signal, and (iv) coherent integration block for integrating the data preserving phase intact. ADC block consists of Analog devices make AD9467 16-bit ADCs, to digitize the input signal at 80 MSPS. The output of ADC is centered around (80 MHz - input frequency). The digitized data is fed to DDC block, which down converts the data to base-band. The DDC block has NCO, mixer and two chains of Bessel filters (fifth order cascaded integration comb filter, two FIR filters, two half band filters and programmable FIR filters) for in-phase (I) and Quadrature phase (Q) channels. The NCO has 32 bits and is set to match the output frequency of ADC. Further, DDC down samples (decimation) the data and reduces the data rate to 16 MSPS. This data is further decimated and the data rate is reduced down to 4/2/1/0.5/0.25/0.125/0.0625 MSPS for baud lengths 0.25/0.5/1/2/4/8/16 μs respectively. The down sampled data is then fed to decoding block, which performs cross correlation to achieve pulse compression of the binary-phase coded data to obtain better range resolution with maximum possible height coverage. This step improves the signal power by a factor equal to the length of the code. Coherent integration block integrates the decoded data coherently for successive pulses, which improves the signal to noise ratio and reduces the data volume. DDC, decoding and coherent integration blocks are implemented in Xilinx vertex5 FPGA. Till this point, function of all six channels is same for DBS mode and multi-receiver modes. Data from vertex5 FPGA is transferred to PC via GbE-1 interface for multi-modes or to two Analog devices make ADSP-TS201 DSP chips (A and B), via link port for DBS mode. ADSP-TS201 chips perform the normalization, DC removal, windowing, FFT computation and spectral averaging on the data, which is transferred to storage/display PC via GbE-2 interface for real-time data display and data storing. Physical layer of GbE interface is implemented in an external chip (Marvel 88E1111) and MAC layer is implemented internal to vertex5 FPGA. The MCDRx has total 4 GB of DDR2 memory for data storage. Spartan6 FPGA is used for generating timing signals, required for basic operation of the radar and testing of the MCDRx.

High efficiency integration of three-dimensional functional microdevices inside a microfluidic chip by using femtosecond laser multifoci parallel microfabrication

NASA Astrophysics Data System (ADS)

Xu, Bing; Du, Wen-Qiang; Li, Jia-Wen; Hu, Yan-Lei; Yang, Liang; Zhang, Chen-Chu; Li, Guo-Qiang; Lao, Zhao-Xin; Ni, Jin-Cheng; Chu, Jia-Ru; Wu, Dong; Liu, Su-Ling; Sugioka, Koji

2016-01-01

High efficiency fabrication and integration of three-dimension (3D) functional devices in Lab-on-a-chip systems are crucial for microfluidic applications. Here, a spatial light modulator (SLM)-based multifoci parallel femtosecond laser scanning technology was proposed to integrate microstructures inside a given ‘Y’ shape microchannel. The key novelty of our approach lies on rapidly integrating 3D microdevices inside a microchip for the first time, which significantly reduces the fabrication time. The high quality integration of various 2D-3D microstructures was ensured by quantitatively optimizing the experimental conditions including prebaking time, laser power and developing time. To verify the designable and versatile capability of this method for integrating functional 3D microdevices in microchannel, a series of microfilters with adjustable pore sizes from 12.2 μm to 6.7 μm were fabricated to demonstrate selective filtering of the polystyrene (PS) particles and cancer cells with different sizes. The filter can be cleaned by reversing the flow and reused for many times. This technology will advance the fabrication technique of 3D integrated microfluidic and optofluidic chips.

Fully Integrated On-Chip Coil in 0.13 μm CMOS for Wireless Power Transfer Through Biological Media.

PubMed

Zargham, Meysam; Gulak, P Glenn

2015-04-01

Delivering milliwatts of wireless power at centimeter distances is advantageous to many existing and emerging biomedical applications. It is highly desirable to fully integrate the receiver on a single chip in standard CMOS with no additional post-processing steps or external components. This paper presents a 2 × 2.18 mm(2) on-chip wireless power transfer (WPT) receiver (Rx) coil fabricated in 0.13 μm CMOS. The WPT system utilizes a 14.5 × 14.5 mm(2) transmitter (Tx) coil that is fabricated on a standard FR4 substrate. The on-chip power harvester demonstrates a peak WPT efficiency of -18.47 dB , -20.96 dB and -20.15 dB at 10 mm of separation through air, bovine muscle and 0.2 molar NaCl, respectively. The achieved efficiency enables the delivery of milliwatts of power to application circuits while staying below safe power density and electromagnetic (EM) exposure limits.

An isolated SNM model for high-stability multi-port register file in 65 nm CMOS

NASA Astrophysics Data System (ADS)

Zhang, Yuejun; Wang, Pengjun; Li, Gang

2017-09-01

In modern microprocessors, the multi-port register file is one of the key modules which provides fast and multiple data access for instructions. As the number of access ports in register files increases, stability becomes a key issue due to the voltage fluctuation on bit lines. We propose to apply an isolated inverter to address the voltage fluctuation. To assess the register stability, we derive a closed-form expression of static noise margin (SNM) for our register file. The proposed SNM model can be used as a guideline to predict the impact of several register parameters on the stability and optimize register file designs. To validate the proposed SNM model, we fabricated a test chip of two-write-four-read (2W4R) 1024 bits register file in a TSMC 65 nm low-power CMOS technology. The experimental result shows that the stability of our register file cells with an isolated inverter improve the conventional cells by approximately 2.4 times. Also, the supply voltage causes a fluctuation of SNM of about 65%, while temperature and transistor mismatch cause a fluctuation of SNM of about 20%. Project supported by the National Natural Science Foundation of China (Nos, 61404076, 61474068), the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), the S&T Plan of Zhejiang Provincial Science and Technology Department (No. 2015C31010), the China Spark Program (No. 2015GA701053), the Ningbo Natural Science Foundation (Nos. 2014A610148, 2015A610107), and the K. C. Wong Magna Fund in Ningbo University, China.

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on-chip control and timing function) enabling a high flexibility architecture, make this imager a good candidate for high performance tracking applications.

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network.

PubMed

Lee, Dasheng

2008-12-02

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient program.

Energy Harvesting Chip and the Chip Based Power Supply Development for a Wireless Sensor Network

PubMed Central

Lee, Dasheng

2008-01-01

In this study, an energy harvesting chip was developed to scavenge energy from artificial light to charge a wireless sensor node. The chip core is a miniature transformer with a nano-ferrofluid magnetic core. The chip embedded transformer can convert harvested energy from its solar cell to variable voltage output for driving multiple loads. This chip system yields a simple, small, and more importantly, a battery-less power supply solution. The sensor node is equipped with multiple sensors that can be enabled by the energy harvesting power supply to collect information about the human body comfort degree. Compared with lab instruments, the nodes with temperature, humidity and photosensors driven by harvested energy had variation coefficient measurement precision of less than 6% deviation under low environmental light of 240 lux. The thermal comfort was affected by the air speed. A flow sensor equipped on the sensor node was used to detect airflow speed. Due to its high power consumption, this sensor node provided 15% less accuracy than the instruments, but it still can meet the requirement of analysis for predicted mean votes (PMV) measurement. The energy harvesting wireless sensor network (WSN) was deployed in a 24-hour convenience store to detect thermal comfort degree from the air conditioning control. During one year operation, the sensor network powered by the energy harvesting chip retained normal functions to collect the PMV index of the store. According to the one month statistics of communication status, the packet loss rate (PLR) is 2.3%, which is as good as the presented results of those WSNs powered by battery. Referring to the electric power records, almost 54% energy can be saved by the feedback control of an energy harvesting sensor network. These results illustrate that, scavenging energy not only creates a reliable power source for electronic devices, such as wireless sensor nodes, but can also be an energy source by building an energy efficient program. PMID:27873953

Conceptual design of a 10 to the 8th power bit magnetic bubble domain mass storage unit and fabrication, test and delivery of a feasibility model

NASA Technical Reports Server (NTRS)

1972-01-01

The conceptual design of a highly reliable 10 to the 8th power-bit bubble domain memory for the space program is described. The memory has random access to blocks of closed-loop shift registers, and utilizes self-contained bubble domain chips with on-chip decoding. Trade-off studies show that the highest reliability and lowest power dissipation is obtained when the memory is organized on a bit-per-chip basis. The final design has 800 bits/register, 128 registers/chip, 16 chips/plane, and 112 planes, of which only seven are activated at a time. A word has 64 data bits +32 checkbits, used in a 16-adjacent code to provide correction of any combination of errors in one plane. 100 KHz maximum rotational frequency keeps power low (equal to or less than, 25 watts) and also allows asynchronous operation. Data rate is 6.4 megabits/sec, access time is 200 msec to an 800-word block and an additional 4 msec (average) to a word. The fabrication and operation are also described for a 64-bit bubble domain memory chip designed to test the concept of on-chip magnetic decoding. Access to one of the chip's four shift registers for the read, write, and clear functions is by means of bubble domain decoders utilizing the interaction between a conductor line and a bubble.

Color design model of high color rendering index white-light LED module.

PubMed

Ying, Shang-Ping; Fu, Han-Kuei; Hsieh, Hsin-Hsin; Hsieh, Kun-Yang

2017-05-10

The traditional white-light light-emitting diode (LED) is packaged with a single chip and a single phosphor but has a poor color rendering index (CRI). The next-generation package comprises two chips and a single phosphor, has a high CRI, and retains high luminous efficacy. This study employs two chips and two phosphors to improve the diode's color tunability with various proportions of two phosphors and various densities of phosphor in the silicone used. A color design model is established for color fine-tuning of the white-light LED module. The maximum difference between the measured and color-design-model simulated CIE 1931 color coordinates is approximately 0.0063 around a correlated color temperature (CCT) of 2500 K. This study provides a rapid method to obtain the color fine-tuning of a white-light LED module with a high CRI and luminous efficacy.

A 30 GHz monolithic receive module technology assessment

NASA Technical Reports Server (NTRS)

Geddes, J.; Sokolov, V.; Bauhahn, P.; Contolatis, T.

1988-01-01

This report is a technology assessment relevant to the 30 GHz Monolithic Receive Module development. It is based on results obtained on the present NASA Contract (NAS3-23356) as well as on information gathered from literature and other industry sources. To date the on-going Honeywell program has concentrated on demonstrating the so-called interconnected receive module which consists of four monolithic chips - the low noise front-end amplifier (LNA), the five bit phase shifter (PS), the gain control amplifier (GC), and the RF to IF downconverter (RF/IF). Results on all four individual chips have been obtained and interconnection of the first three functions has been accomplished. Future work on this contract is aimed at a higher level of integration, i.e., integration of the first three functions (LNA + PS + GC) on a single GaAs chip. The report presents the status of this technology and projections of its future directions.

Amplifier Module for 260-GHz Band Using Quartz Waveguide Transitions

NASA Technical Reports Server (NTRS)

Padmanabhan, Sharmila; Fung, King Man; Kangaslahti, Pekka P.; Peralta, Alejandro; Soria, Mary M.; Pukala, David M.; Sin, Seth; Samoska, Lorene A.; Sarkozy, Stephen; Lai, Richard

2012-01-01

Packaging of MMIC LNA (monolithic microwave integrated circuit low-noise amplifier) chips at frequencies over 200 GHz has always been problematic due to the high loss in the transition between the MMIC chip and the waveguide medium in which the chip will typically be used. In addition, above 200 GHz, wire-bond inductance between the LNA and the waveguide can severely limit the RF matching and bandwidth of the final waveguide amplifier module. This work resulted in the development of a low-loss quartz waveguide transition that includes a capacitive transmission line between the MMIC and the waveguide probe element. This capacitive transmission line tunes out the wirebond inductance (where the wire-bond is required to bond between the MMIC and the probe element). This inductance can severely limit the RF matching and bandwidth of the final waveguide amplifier module. The amplifier module consists of a quartz E-plane waveguide probe transition, a short capacitive tuning element, a short wire-bond to the MMIC, and the MMIC LNA. The output structure is similar, with a short wire-bond at the output of the MMIC, a quartz E-plane waveguide probe transition, and the output waveguide. The quartz probe element is made of 3-mil quartz, which is the thinnest commercially available material. The waveguide band used is WR4, from 170 to 260 GHz. This new transition and block design is an improvement over prior art because it provides for better RF matching, and will likely yield lower loss and better noise figure. The development of high-performance, low-noise amplifiers in the 180-to- 700-GHz range has applications for future earth science and planetary instruments with low power and volume, and astrophysics array instruments for molecular spectroscopy. This frequency band, while suitable for homeland security and commercial applications (such as millimeter-wave imaging, hidden weapons detection, crowd scanning, airport security, and communications), also has applications to future NASA missions. The Global Atmospheric Composition Mission (GACM) in the NRC Decadel Survey will need low-noise amplifiers with extremely low noise temperatures, either at room temperature or for cryogenic applications, for atmospheric remote sensing.

Low voltage electrophoresis chip with multi-segments synchronized scanning

NASA Astrophysics Data System (ADS)

Gu, Wenwen; Wen, Zhiyu; Xu, Yi

2017-03-01

For low voltage electrophoresis chip, there is always a problem that the samples are truncated and peaks are broadened, as well as longer time for separation. In this paper, a low voltage electrophoresis separation model was established, and the separation conditions were discussed. A new driving mode was proposed for applying low voltage, which was called multi-segments synchronized scanning. By using this driving mode, the reversed electric field that existed between the multi-segments can enrich samples and shorten the sample zone. The low voltage electrophoresis experiments using multi-segments synchronized scanning were carried out by home-made silicon-PDMS-based chip. The fluorescein isothiocyanate (FITC) labeled lysine and phenylalanine mixed samples with the concentration of 10-4 mol/L were successfully separated under the optimal conditions of 10 mmol/L borax buffer (pH = 10.0), 200 V/cm separation electric field and electrode switch time of 2.5 s. The separation was completed with a resolution of 2.0, and the peak time for lysine and phenylalanine was 4 min and 6 min, respectively.

Quad-Chip Double-Balanced Frequency Tripler

NASA Technical Reports Server (NTRS)

Lin, Robert H.; Ward, John S.; Bruneau, Peter J.; Mehdi, Imran; Thomas, Bertrand C.; Maestrini, Alain

2010-01-01

Solid-state frequency multipliers are used to produce tunable broadband sources at millimeter and submillimeter wavelengths. The maximum power produced by a single chip is limited by the electrical breakdown of the semiconductor and by the thermal management properties of the chip. The solution is to split the drive power to a frequency tripler using waveguides to divide the power among four chips, then recombine the output power from the four chips back into a single waveguide. To achieve this, a waveguide branchline quadrature hybrid coupler splits a 100-GHz input signal into two paths with a 90 relative phase shift. These two paths are split again by a pair of waveguide Y-junctions. The signals from the four outputs of the Y-junctions are tripled in frequency using balanced Schottky diode frequency triplers before being recombined with another pair of Y-junctions. A final waveguide branchline quadrature hybrid coupler completes the combination. Using four chips instead of one enables using four-times higher power input, and produces a nearly four-fold power output as compared to using a single chip. The phase shifts introduced by the quadrature hybrid couplers provide isolation for the input and output waveguides, effectively eliminating standing waves between it and surrounding components. This is accomplished without introducing the high losses and expense of ferrite isolators. A practical use of this technology is to drive local oscillators as was demonstrated around 300 GHz for a heterodyne spectrometer operating in the 2-3-THz band. Heterodyne spectroscopy in this frequency band is especially valuable for astrophysics due to the presence of a very large number of molecular spectral lines. Besides high-resolution radar and spectrographic screening applications, this technology could also be useful for laboratory spectroscopy.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

1997-01-01

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

Si photonics technology for future optical interconnection

NASA Astrophysics Data System (ADS)

Zheng, Xuezhe; Krishnamoorthy, Ashok V.

2011-12-01

Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

A fiber-coupled incoherent light source for ultra-precise optical trapping

NASA Astrophysics Data System (ADS)

Menke, Tim; Schittko, Robert; Mazurenko, Anton; Tai, M. Eric; Lukin, Alexander; Rispoli, Matthew; Kaufman, Adam M.; Greiner, Markus

2017-04-01

The ability to engineer arbitrary optical potentials using spatial light modulation has opened up exciting possibilities in ultracold quantum gas experiments. Yet, despite the high trap quality currently achievable, interference-induced distortions caused by scattering along the optical path continue to impede more sensitive measurements. We present a design of a high-power, spatially and temporally incoherent light source that bears the potential to reduce the impact of such distortions. The device is based on an array of non-lasing semiconductor emitters mounted on a single chip whose optical output is coupled into a multi-mode fiber. By populating a large number of fiber modes, the low spatial coherence of the input light is further reduced due to the differing optical path lengths amongst the modes and the short coherence length of the light. In addition to theoretical calculations showcasing the feasibility of this approach, we present experimental measurements verifying the low degree of spatial coherence achievable with such a source, including a detailed analysis of the speckle contrast at the fiber end. We acknowledge support from the National Science Foundation, the Gordon and Betty Moore Foundation's EPiQS Initiative, an Air Force Office of Scientific Research MURI program and an Army Research Office MURI program.

CMOS-compatible InP/InGaAs digital photoreceiver

DOEpatents

Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

1997-11-04

A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

Enhanced Contacts for Inverted Metamorphic Multi-Junction Solar Cells Using Carbon Nanotube Metal Matrix Composites

DTIC Science & Technology

2018-01-18

to a variety solar energy markets. For instance, micro-cracks have been shown to cause decreased power output in single- and multi-crystalline Si PV ...fingers in silicon wafer solar cells and PV modules," Solar Energy Materials and Solar Cells, vol. 108, pp. 78-81, 1// 2013. [4] T. H. Reijenga and H...AFRL-RV-PS- AFRL-RV-PS- TR-2017-0125 TR-2017-0125 ENHANCED CONTACTS FOR INVERTED METAMORPHIC MULTI-JUNCTION SOLAR CELLS USING CARBON NANOTUBE METAL

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

Navigating tissue chips from development to dissemination: A pharmaceutical industry perspective

PubMed Central

Fabre, Kristin; Chakilam, Ananthsrinivas; Dragan, Yvonne; Duignan, David B; Eswaraka, Jeetu; Gan, Jinping; Guzzie-Peck, Peggy; Otieno, Monicah; Jeong, Claire G; Keller, Douglas A; de Morais, Sonia M; Phillips, Jonathan A; Proctor, William; Sura, Radhakrishna; Van Vleet, Terry; Watson, David; Will, Yvonne; Tagle, Danilo; Berridge, Brian

2017-01-01

Tissue chips are poised to deliver a paradigm shift in drug discovery. By emulating human physiology, these chips have the potential to increase the predictive power of preclinical modeling, which in turn will move the pharmaceutical industry closer to its aspiration of clinically relevant and ultimately animal-free drug discovery. Despite the tremendous science and innovation invested in these tissue chips, significant challenges remain to be addressed to enable their routine adoption into the industrial laboratory. This article describes the main steps that need to be taken and highlights key considerations in order to transform tissue chip technology from the hands of the innovators into those of the industrial scientists. Written by scientists from 13 pharmaceutical companies and partners at the National Institutes of Health, this article uniquely captures a consensus view on the progression strategy to facilitate and accelerate the adoption of this valuable technology. It concludes that success will be delivered by a partnership approach as well as a deep understanding of the context within which these chips will actually be used. Impact statement The rapid pace of scientific innovation in the tissue chip (TC) field requires a cohesive partnership between innovators and end users. Near term uptake of these human-relevant platforms will fill gaps in current capabilities for assessing important properties of disposition, efficacy and safety liabilities. Similarly, these platforms could support mechanistic studies which aim to resolve challenges later in development (e.g. assessing the human relevance of a liability identified in animal studies). Building confidence that novel capabilities of TCs can address real world challenges while they themselves are being developed will accelerate their application in the discovery and development of innovative medicines. This article outlines a strategic roadmap to unite innovators and end users thus making implementation smooth and rapid. With the collective contributions from multiple international pharmaceutical companies and partners at National Institutes of Health, this article should serve as an invaluable resource to the multi-disciplinary field of TC development. PMID:28622731

Navigating tissue chips from development to dissemination: A pharmaceutical industry perspective.

PubMed

Ewart, Lorna; Fabre, Kristin; Chakilam, Ananthsrinivas; Dragan, Yvonne; Duignan, David B; Eswaraka, Jeetu; Gan, Jinping; Guzzie-Peck, Peggy; Otieno, Monicah; Jeong, Claire G; Keller, Douglas A; de Morais, Sonia M; Phillips, Jonathan A; Proctor, William; Sura, Radhakrishna; Van Vleet, Terry; Watson, David; Will, Yvonne; Tagle, Danilo; Berridge, Brian

2017-10-01

Tissue chips are poised to deliver a paradigm shift in drug discovery. By emulating human physiology, these chips have the potential to increase the predictive power of preclinical modeling, which in turn will move the pharmaceutical industry closer to its aspiration of clinically relevant and ultimately animal-free drug discovery. Despite the tremendous science and innovation invested in these tissue chips, significant challenges remain to be addressed to enable their routine adoption into the industrial laboratory. This article describes the main steps that need to be taken and highlights key considerations in order to transform tissue chip technology from the hands of the innovators into those of the industrial scientists. Written by scientists from 13 pharmaceutical companies and partners at the National Institutes of Health, this article uniquely captures a consensus view on the progression strategy to facilitate and accelerate the adoption of this valuable technology. It concludes that success will be delivered by a partnership approach as well as a deep understanding of the context within which these chips will actually be used. Impact statement The rapid pace of scientific innovation in the tissue chip (TC) field requires a cohesive partnership between innovators and end users. Near term uptake of these human-relevant platforms will fill gaps in current capabilities for assessing important properties of disposition, efficacy and safety liabilities. Similarly, these platforms could support mechanistic studies which aim to resolve challenges later in development (e.g. assessing the human relevance of a liability identified in animal studies). Building confidence that novel capabilities of TCs can address real world challenges while they themselves are being developed will accelerate their application in the discovery and development of innovative medicines. This article outlines a strategic roadmap to unite innovators and end users thus making implementation smooth and rapid. With the collective contributions from multiple international pharmaceutical companies and partners at National Institutes of Health, this article should serve as an invaluable resource to the multi-disciplinary field of TC development.

Miniaturization of environmental chemical assays in flowing systems: the lab-on-a-valve approach vis-à-vis lab-on-a-chip microfluidic devices.

PubMed

Miró, Manuel; Hansen, Elo Harald

2007-09-26

The analytical capabilities of the microminiaturized lab-on-a-valve (LOV) module integrated into a microsequential injection (muSI) fluidic system in terms of analytical chemical performance, microfluidic handling and on-line sample processing are compared to those of the micro total analysis systems (muTAS), also termed lab-on-a-chip (LOC). This paper illustrates, via selected representative examples, the potentials of the LOV scheme vis-à-vis LOC microdevices for environmental assays. By means of user-friendly programmable flow and the exploitation of the interplay between the thermodynamics and the kinetics of the chemical reactions at will, LOV allows accommodation of reactions which, at least at the present stage, are not feasible by application of microfluidic LOC systems. Thus, in LOV one may take full advantage of kinetic discriminations schemes, where even subtle differences in reactions are utilized for analytical purposes. Furthermore, it is also feasible to handle multi-step sequential reactions of divergent kinetics; to conduct multi-parametric determinations without manifold reconfiguration by utilization of the inherent open-architecture of the micromachined unit for implementation of peripheral modules and automated handling of a variety of reagents; and most importantly, it offers itself as a versatile front end to a plethora of detection schemes. Not the least, LOV is regarded as an emerging downscaled tool to overcome the dilemma of LOC microsystems to admit real-life samples. This is nurtured via its intrinsic flexibility for accommodation of sample pre-treatment schemes aimed at the on-line manipulation of complex samples. Thus, LOV is playing a prominent role in the environmental field, whenever the monitoring of trace level concentration of pollutants is pursued, because both matrix isolation and preconcentration of target analytes is most often imperative, or in fact necessary, prior to sample presentation to the detector.