Sample records for multi-level interconnect circuit

  1. Three dimensional, multi-chip module

    DOEpatents

    Bernhardt, A.F.; Petersen, R.W.

    1993-08-31

    A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow dummy chips'' are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned on the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

  2. Three dimensional, multi-chip module

    DOEpatents

    Bernhardt, Anthony F.; Petersen, Robert W.

    1993-01-01

    A plurality of multi-chip modules are stacked and bonded around the perimeter by sold-bump bonds to adjacent modules on, for instance, three sides of the perimeter. The fourth side can be used for coolant distribution, for more interconnect structures, or other features, depending on particular design considerations of the chip set. The multi-chip modules comprise a circuit board, having a planarized interconnect structure formed on a first major surface, and integrated circuit chips bonded to the planarized interconnect surface. Around the periphery of each circuit board, long, narrow "dummy chips" are bonded to the finished circuit board to form a perimeter wall. The wall is higher than any of the chips on the circuit board, so that the flat back surface of the board above will only touch the perimeter wall. Module-to-module interconnect is laser-patterned o the sides of the boards and over the perimeter wall in the same way and at the same time that chip to board interconnect may be laser-patterned.

  3. Single-mode glass waveguide technology for optical interchip communication on board level

    NASA Astrophysics Data System (ADS)

    Brusberg, Lars; Neitz, Marcel; Schröder, Henning

    2012-01-01

    The large bandwidth demand in long-distance telecom networks lead to single-mode fiber interconnects as result of low dispersion, low loss and dense wavelength multiplexing possibilities. In contrast, multi-mode interconnects are suitable for much shorter lengths up to 300 meters and are promising for optical links between racks and on board level. Active optical cables based on multi-mode fiber links are at the market and research in multi-mode waveguide integration on board level is still going on. Compared to multi-mode, a single-mode waveguide has much more integration potential because of core diameters of around 20% of a multi-mode waveguide by a much larger bandwidth. But light coupling in single-mode waveguides is much more challenging because of lower coupling tolerances. Together with the silicon photonics technology, a single-mode waveguide technology on board-level will be the straight forward development goal for chip-to-chip optical interconnects integration. Such a hybrid packaging platform providing 3D optical single-mode links bridges the gap between novel photonic integrated circuits and the glass fiber based long-distance telecom networks. Following we introduce our 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip interconnects. This novel packaging approach merges micro-system packaging and glass integrated optics. It consists of a thin glass substrate with planar integrated singlemode waveguide circuits, optical mirrors and lenses providing an integration platform for photonic IC assembly and optical fiber interconnect. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties. That makes it perfect for microsystem packaging. The paper presents recent results in single-mode waveguide technology on wafer level and waveguide characterization. Furthermore the integration in a hybrid packaging process and design issues are discussed.

  4. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    PubMed

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

  5. Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

    NASA Technical Reports Server (NTRS)

    Routh, D. E.; Sharma, G. C. (Inventor)

    1982-01-01

    The processing of wafer devices to form multilevel interconnects for microelectronic circuits is described. The method is directed to performing the sequential steps of etching the via, removing the photo resist pattern, back sputtering the entire wafer surface and depositing the next layer of interconnect material under common vacuum conditions without exposure to atmospheric conditions. Apparatus for performing the method includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a DC magnetron sputtering system. A gas inlet is provided in the chamber for the introduction of various gases to the vacuum chamber and the creation of various gas plasma during the sputtering steps.

  6. Designing an Electronics Data Package for Printed Circuit Boards (PCBs)

    DTIC Science & Technology

    2013-08-01

    finished PCB flatness deviation should be less than 0.010 inches per inch. 4  The minimum copper wall thickness of plated-thru holes should be...Memory Card International Association)  IPC-6015 MCM-L (Multi-Chip Module – Laminated )  IPC-6016 HDI (High Density Interconnect)  IPC-6018...Interconnect ICT In Circuit Tester IPC Association Connecting Electronics Industries MCM-L Multi-Chip Module – Laminated MIL Military NEMA National

  7. TCAD Analysis of Heating and Maximum Current Density in Carbon Nanofiber Interconnects

    DTIC Science & Technology

    2011-09-01

    a metallic MWCNT interconnect. From [20]. ....20  Figure 11.  Simple equivalent circuit model of a metallic MWCNT interconnect. From [20...Carbon Nanotube MWCNT Multi-Walled Carbon Nanotube SCU Santa Clara University Si Silicon SiO2 Silicon Dioxide SiC Silicon Carbide Au Gold...proven, multi-walled carbon nanotube ( MWCNT ) [2]. He later discovered single-walled carbon nanotubes (SWCNT) in 1993 [13]. Since Iijima’s discovery

  8. Fabrication of multijunction high voltage concentrator solar cells by integrated circuit technology

    NASA Technical Reports Server (NTRS)

    Valco, G. J.; Kapoor, V. J.; Evans, J. C., Jr.; Chai, A.-T.

    1981-01-01

    Standard integrated circuit technology has been developed for the design and fabrication of planar multijunction (PMJ) solar cell chips. Each 1 cm x 1 cm solar chip consisted of six n(+)/p, back contacted, internally series interconnected unit cells. These high open circuit voltage solar cells were fabricated on 2 ohm-cm, p-type 75 microns thick, silicon substrates. A five photomask level process employing contact photolithography was used to pattern for boron diffusions, phorphorus diffusions, and contact metallization. Fabricated devices demonstrated an open circuit voltage of 3.6 volts and a short circuit current of 90 mA at 80 AMl suns. An equivalent circuit model of the planar multi-junction solar cell was developed.

  9. Design and implementation of GaAs HBT circuits with ACME

    NASA Technical Reports Server (NTRS)

    Hutchings, Brad L.; Carter, Tony M.

    1993-01-01

    GaAs HBT circuits offer high performance (5-20 GHz) and radiation hardness (500 Mrad) that is attractive for space applications. ACME is a CAD tool specifically developed for HBT circuits. ACME implements a novel physical schematic-capture design technique where designers simultaneously view the structure and physical organization of a circuit. ACME's design interface is similar to schematic capture; however, unlike conventional schematic capture, designers can directly control the physical placement of both function and interconnect at the schematic level. In addition, ACME provides design-time parasitic extraction, complex wire models, and extensions to Multi-Chip Modules (MCM's). A GaAs HBT gate-array and semi-custom circuits have been developed with ACME; several circuits have been fabricated and found to be fully functional .

  10. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

  11. Temperature-Dependent Modeling and Crosstalk Analysis in Mixed Carbon Nanotube Bundle Interconnects

    NASA Astrophysics Data System (ADS)

    Rai, Mayank Kumar; Garg, Harsh; Kaushik, B. K.

    2017-08-01

    The temperature-dependent circuit modeling and performance analysis in terms of crosstalk in capacitively coupled mixed carbon nanotube bundle (MCB) interconnects, at the far end of the victim line, have been analyzed with four different structures of MCBs (MCB-1, MCB-2, MCB-3 and MCB-4) constituted under case 1 and case 2 at the 22-nm technology node. The impact of tunneling and intershell coupling between adjacent shells on temperature-dependent equivalent circuit parameters of a multi-walled carbon nanotube bundle are also critically analyzed and employed for different MCB structures under case 1. A similar analysis is performed for copper interconnects and comparisons are made between results obtained through these analyses over temperatures ranging from 300 K to 500 K. The simulation program with integrated circuit emphasis simulation results reveals that, compared with all MCB structures under case 1 and case 2, with rise in temperature from 300 K to 500 K, crosstalk-induced noise voltage levels at the far end of the victim line are found to be significantly large in copper. It is also observed that due to the dominance of larger temperature-dependent resistance and ground capacitance in case 1, the MCB-2 is of lower crosstalk-induced noise voltage levels than other structures of MCBs. On the other hand, the MCB-1 has smaller time duration of victim output. Results further reveal that, compared with case 2 of MCB, with rise in temperatures, the victim line gets less prone to crosstalk-induced noise in MCB interconnects constituted under case 1, due to tunneling effects and intershell coupling between adjacent shells. Based on these comparative results, a promising MCB structure (MCB-2) has been proposed among other structures under the consideration of tunneling effects and intershell coupling (case 1).

  12. Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2015-01-01

    Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

  13. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    PubMed

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  14. High density electronic circuit and process for making

    DOEpatents

    Morgan, William P.

    1999-01-01

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing.

  15. Modular cryogenic interconnects for multi-qubit devices.

    PubMed

    Colless, J I; Reilly, D J

    2014-11-01

    We have developed a modular interconnect platform for the control and readout of multiple solid-state qubits at cryogenic temperatures. The setup provides 74 filtered dc-bias connections, 32 control and readout connections with -3 dB frequency above 5 GHz, and 4 microwave feed lines that allow low loss (less than 3 dB) transmission 10 GHz. The incorporation of a radio-frequency interposer enables the platform to be separated into two printed circuit boards, decoupling the simple board that is bonded to the qubit chip from the multilayer board that incorporates expensive connectors and components. This modular approach lifts the burden of duplicating complex interconnect circuits for every prototype device. We report the performance of this platform at milli-Kelvin temperatures, including signal transmission and crosstalk measurements.

  16. Fully Solution-Processable Fabrication of Multi-Layered Circuits on a Flexible Substrate Using Laser Processing

    PubMed Central

    Ji, Seok Young; Choi, Wonsuk; Jeon, Jin-Woo; Chang, Won Seok

    2018-01-01

    The development of printing technologies has enabled the realization of electric circuit fabrication on a flexible substrate. However, the current technique remains restricted to single-layer patterning. In this paper, we demonstrate a fully solution-processable patterning approach for multi-layer circuits using a combined method of laser sintering and ablation. Selective laser sintering of silver (Ag) nanoparticle-based ink is applied to make conductive patterns on a heat-sensitive substrate and insulating layer. The laser beam path and irradiation fluence are controlled to create circuit patterns for flexible electronics. Microvia drilling using femtosecond laser through the polyvinylphenol-film insulating layer by laser ablation, as well as sequential coating of Ag ink and laser sintering, achieves an interlayer interconnection between multi-layer circuits. The dimension of microvia is determined by a sophisticated adjustment of the laser focal position and intensity. Based on these methods, a flexible electronic circuit with chip-size-package light-emitting diodes was successfully fabricated and demonstrated to have functional operations. PMID:29425144

  17. High density electronic circuit and process for making

    DOEpatents

    Morgan, W.P.

    1999-06-29

    High density circuits with posts that protrude beyond one surface of a substrate to provide easy mounting of devices such as integrated circuits are disclosed. The posts also provide stress relief to accommodate differential thermal expansion. The process allows high interconnect density with fewer alignment restrictions and less wasted circuit area than previous processes. The resulting substrates can be test platforms for die testing and for multi-chip module substrate testing. The test platform can contain active components and emulate realistic operational conditions, replacing shorts/opens net testing. 8 figs.

  18. Modeling and experimental characterization of electromigration in interconnect trees

    NASA Astrophysics Data System (ADS)

    Thompson, C. V.; Hau-Riege, S. P.; Andleigh, V. K.

    1999-11-01

    Most modeling and experimental characterization of interconnect reliability is focussed on simple straight lines terminating at pads or vias. However, laid-out integrated circuits often have interconnects with junctions and wide-to-narrow transitions. In carrying out circuit-level reliability assessments it is important to be able to assess the reliability of these more complex shapes, generally referred to as `trees.' An interconnect tree consists of continuously connected high-conductivity metal within one layer of metallization. Trees terminate at diffusion barriers at vias and contacts, and, in the general case, can have more than one terminating branch when they include junctions. We have extended the understanding of `immortality' demonstrated and analyzed for straight stud-to-stud lines, to trees of arbitrary complexity. This leads to a hierarchical approach for identifying immortal trees for specific circuit layouts and models for operation. To complete a circuit-level-reliability analysis, it is also necessary to estimate the lifetimes of the mortal trees. We have developed simulation tools that allow modeling of stress evolution and failure in arbitrarily complex trees. We are testing our models and simulations through comparisons with experiments on simple trees, such as lines broken into two segments with different currents in each segment. Models, simulations and early experimental results on the reliability of interconnect trees are shown to be consistent.

  19. Planned development of a 3D computer based on free-space optical interconnects

    NASA Astrophysics Data System (ADS)

    Neff, John A.; Guarino, David R.

    1994-05-01

    Free-space optical interconnection has the potential to provide upwards of a million data channels between planes of electronic circuits. This may result in the planar board and backplane structures of today giving away to 3-D stacks of wafers or multi-chip modules interconnected via channels running perpendicular to the processor planes, thereby eliminating much of the packaging overhead. Three-dimensional packaging is very appealing for tightly coupled fine-grained parallel computing where the need for massive numbers of interconnections is severely taxing the capabilities of the planar structures. This paper describes a coordinated effort by four research organizations to demonstrate an operational fine-grained parallel computer that achieves global connectivity through the use of free space optical interconnects.

  20. Method for sequentially processing a multi-level interconnect circuit in a vacuum chamber

    NASA Technical Reports Server (NTRS)

    Routh, D. E.; Sharma, G. C. (Inventor)

    1984-01-01

    An apparatus is disclosed which includes a vacuum system having a vacuum chamber in which wafers are processed on rotating turntables. The vacuum chamber is provided with an RF sputtering system and a dc magnetron sputtering system. A gas inlet introduces various gases to the vacuum chamber and creates various gas plasma during the sputtering steps. The rotating turntables insure that the respective wafers are present under the sputtering guns for an average amount of time such that consistency in sputtering and deposition is achieved. By continuous and sequential processing of the wafers in a common vacuum chamber without removal, the adverse affects of exposure to atmospheric conditions are eliminated providing higher quality circuit contacts and functional device.

  1. Multi-petascale highly efficient parallel supercomputer

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.

    A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time andmore » supports DMA functionality allowing for parallel processing message-passing.« less

  2. Behavioral modeling of VCSELs for high-speed optical interconnects

    NASA Astrophysics Data System (ADS)

    Szczerba, Krzysztof; Kocot, Chris

    2018-02-01

    Transition from on-off keying to 4-level pulse amplitude modulation (PAM) in VCSEL based optical interconnects allows for an increase of data rates, at the cost of 4.8 dB sensitivity penalty. The resulting strained link budget creates a need for accurate VCSEL models for driver integrated circuit (IC) design and system level simulations. Rate equation based equivalent circuit models are convenient for the IC design, but system level analysis requires computationally efficient closed form behavioral models based Volterra series and neural networks. In this paper we present and compare these models.

  3. Multi-gigabit optical interconnects for next-generation on-board digital equipment

    NASA Astrophysics Data System (ADS)

    Venet, Norbert; Favaro, Henri; Sotom, Michel; Maignan, Michel; Berthon, Jacques

    2017-11-01

    Parallel optical interconnects are experimentally assessed as a technology that may offer the high-throughput data communication capabilities required to the next-generation on-board digital processing units. An optical backplane interconnect was breadboarded, on the basis of a digital transparent processor that provides flexible connectivity and variable bandwidth in telecom missions with multi-beam antenna coverage. The unit selected for the demonstration required that more than tens of Gbit/s be supported by the backplane. The demonstration made use of commercial parallel optical link modules at 850 nm wavelength, with 12 channels running at up to 2.5 Gbit/s. A flexible optical fibre circuit was developed so as to route board-to-board connections. It was plugged to the optical transmitter and receiver modules through 12-fibre MPO connectors. BER below 10-14 and optical link budgets in excess of 12 dB were measured, which would enable to integrate broadcasting. Integration of the optical backplane interconnect was successfully demonstrated by validating the overall digital processor functionality.

  4. Multi-gigabit optical interconnects for next-generation on-board digital equipment

    NASA Astrophysics Data System (ADS)

    Venet, Norbert; Favaro, Henri; Sotom, Michel; Maignan, Michel; Berthon, Jacques

    2004-06-01

    Parallel optical interconnects are experimentally assessed as a technology that may offer the high-throughput data communication capabilities required to the next-generation on-board digital processing units. An optical backplane interconnect was breadboarded, on the basis of a digital transparent processor that provides flexible connectivity and variable bandwidth in telecom missions with multi-beam antenna coverage. The unit selected for the demonstration required that more than tens of Gbit/s be supported by the backplane. The demonstration made use of commercial parallel optical link modules at 850 nm wavelength, with 12 channels running at up to 2.5 Gbit/s. A flexible optical fibre circuit was developed so as to route board-to-board connections. It was plugged to the optical transmitter and receiver modules through 12-fibre MPO connectors. BER below 10-14 and optical link budgets in excess of 12 dB were measured, which would enable to integrate broadcasting. Integration of the optical backplane interconnect was successfully demonstrated by validating the overall digital processor functionality.

  5. 47 CFR 95.1313 - Interconnection prohibited.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... points in the wireline or radio network of a public telephone company and persons served by multi-use... licensees or other authorized persons for transmitter control (including dial-up transmitter control circuits) or as an integral part of an authorized, private, internal system of communication or as an...

  6. WDM mid-board optics for chip-to-chip wavelength routing interconnects in the H2020 ICT-STREAMS

    NASA Astrophysics Data System (ADS)

    Kanellos, G. T.; Pleros, N.

    2017-02-01

    Multi-socket server boards have emerged to increase the processing power density on the board level and further flatten the data center networks beyond leaf-spine architectures. Scaling however the number of processors per board puts current electronic technologies into challenge, as it requires high bandwidth interconnects and high throughput switches with increased number of ports that are currently unavailable. On-board optical interconnection has proved the potential to efficiently satisfy the bandwidth needs, but their use has been limited to parallel links without performing any smart routing functionality. With CWDM optical interconnects already a commodity, cyclical wavelength routing proposed to fit the datacom for rack-to-rack and board-to-board communication now becomes a promising on-board routing platform. ICT-STREAMS is a European research project that aims to combine WDM parallel on-board transceivers with a cyclical AWGR, in order to create a new board-level, chip-to-chip interconnection paradigm that will leverage WDM parallel transmission to a powerful wavelength routing platform capable to interconnect multiple processors with unprecedented bandwidth and throughput capacity. Direct, any-to-any, on-board interconnection of multiple processors will significantly contribute to further flatten the data centers and facilitate east-west communication. In the present communication, we present ICT-STREAMS on-board wavelength routing architecture for multiple chip-to-chip interconnections and evaluate the overall system performance in terms of throughput and latency for several schemes and traffic profiles. We also review recent advances of the ICT-STREAMS platform key-enabling technologies that span from Si in-plane lasers and polymer based electro-optical circuit boards to silicon photonics transceivers and photonic-crystal amplifiers.

  7. PAM4 silicon photonic microring resonator-based transceiver circuits

    NASA Astrophysics Data System (ADS)

    Palermo, Samuel; Yu, Kunzhi; Roshan-Zamir, Ashkan; Wang, Binhao; Li, Cheng; Seyedi, M. Ashkan; Fiorentino, Marco; Beausoleil, Raymond

    2017-02-01

    Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4Vppd output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.

  8. Optical interconnections and networks; Proceedings of the Meeting, The Hague, Netherlands, Mar. 14, 15, 1990

    NASA Technical Reports Server (NTRS)

    Bartelt, Hartmut (Editor)

    1990-01-01

    The conference presents papers on interconnections, clock distribution, neural networks, and components and materials. Particular attention is given to a comparison of optical and electrical data interconnections at the board and backplane levels, a wafer-level optical interconnection network layout, an analysis and simulation of photonic switch networks, and the integration of picosecond GaAs photoconductive devices with silicon circuits for optical clocking and interconnects. Consideration is also given to the optical implementation of neural networks, invariance in an optoelectronic implementation of neural networks, and the recording of reversible patterns in polymer lightguides.

  9. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated with Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Liangyu, Chen; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 1000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  10. Evidence of Processing Non-Idealities in 4H-SiC Integrated Circuits Fabricated With Two Levels of Metal Interconnect

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Evans, Laura J.; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.

    2015-01-01

    The fabrication and prolonged 500 C electrical testing of 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) with two levels of metal interconnect is reported in another submission to this conference proceedings. While some circuits functioned more than 3000 hours at 500 C, the majority of packaged ICs from this wafer electrically failed after less than 200 hours of operation in the same test conditions. This work examines the root physical degradation and failure mechanisms believed responsible for observed large discrepancies in 500 C operating time. Evidence is presented for four distinct issues that significantly impacted 500 C IC operational yield and lifetime for this wafer.

  11. Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

    2001-01-01

    In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

  12. Stretchable multilayer self-aligned interconnects fabricated using excimer laser photoablation and in situ masking

    NASA Astrophysics Data System (ADS)

    Lin, Kevin L.; Jain, Kanti

    2009-02-01

    Stretchable interconnects are essential to large-area flexible circuits and large-area sensor array systems, and they play an important role towards the realization of the realm of systems which include wearable electronics, sensor arrays for structural health monitoring, and sensor skins for tactile feedback. These interconnects must be reliable and robust for viability, and must be flexible, stretchable, and conformable to non-planar surfaces. This research describes the design, modeling, fabrication, and testing of stretchable interconnects on polymer substrates using metal patterns both as functional interconnect layers and as in-situ masks for excimer laser photoablation. Excimer laser photoablation is often used for patterning of polymers and thin-film metals. The fluences for photoablation of polymers are generally much lower than the threshold fluence for removal or damage of high-thermallyconductive metals; thus, metal thin films can be used as in-situ masks for polymers if the proper fluence is used. Selfaligned single-layer and multi-layer interconnects of various designs (rectilinear and 'meandering') have been fabricated, and certain 'meandering' interconnect designs can be stretched up to 50% uniaxially while maintaining good electrical conductivity and structural integrity. These results are compared with Finite Element Analysis (FEA) models and are observed to be in good accordance with them. This fabrication approach eliminates masks and microfabrication processing steps as compared to traditional fabrication approaches; furthermore, this technology is scalable for large-area sensor arrays and electronic circuits, adaptable for a variety of materials and interconnects designs, and compatible with MEMS-based capacitive sensor technology.

  13. Printed wiring board system programmer's manual

    NASA Technical Reports Server (NTRS)

    Brinkerhoff, C. D.

    1973-01-01

    The printed wiring board system provides automated techniques for the design of printed circuit boards and hybrid circuit boards. The system consists of four programs: (1) the preprocessor program combines user supplied data and pre-defined library data to produce the detailed circuit description data; (2) the placement program assigns circuit components to specific areas of the board in a manner that optimizes the total interconnection length of the circuit; (3) the organizer program assigns pin interconnections to specific board levels and determines the optimal order in which the router program should attempt to layout the paths connecting the pins; and (4) the router program determines the wire paths which are to be used to connect each input pin pair on the circuit board. This document is intended to serve as a programmer's reference manual for the printed wiring board system. A detailed description of the internal logic and flow of the printed wiring board programs is included.

  14. The Unification of Space Qualified Integrated Circuits by Example of International Space Project GAMMA-400

    NASA Astrophysics Data System (ADS)

    Bobkov, S. G.; Serdin, O. V.; Arkhangelskiy, A. I.; Arkhangelskaja, I. V.; Suchkov, S. I.; Topchiev, N. P.

    The problem of electronic component unification at the different levels (circuits, interfaces, hardware and software) used in space industry is considered. The task of computer systems for space purposes developing is discussed by example of scientific data acquisition system for space project GAMMA-400. The basic characteristics of high reliable and fault tolerant chips developed by SRISA RAS for space applicable computational systems are given. To reduce power consumption and enhance data reliability, embedded system interconnect made hierarchical: upper level is Serial RapidIO 1x or 4x with rate transfer 1.25 Gbaud; next level - SpaceWire with rate transfer up to 400 Mbaud and lower level - MIL-STD-1553B and RS232/RS485. The Ethernet 10/100 is technology interface and provided connection with the previously released modules too. Systems interconnection allows creating different redundancy systems. Designers can develop heterogeneous systems that employ the peer-to-peer networking performance of Serial RapidIO using multiprocessor clusters interconnected by SpaceWire.

  15. Multi-level Simulation of a Real Time Vibration Monitoring System Component

    NASA Technical Reports Server (NTRS)

    Robertson, Bryan A.; Wilkerson, Delisa

    2005-01-01

    This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by Marshall Space Flight Center (MSFC) Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data fiom two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMC-IRA design has completed all engineering and deliverable unit testing. P

  16. Multi-level Simulation of a Real Time Vibration Monitoring System Component

    NASA Technical Reports Server (NTRS)

    Roberston, Bryan; Wilkerson, DeLisa

    2004-01-01

    This paper describes the development of a custom built Digital Signal Processing (DSP) printed circuit board designed to implement the Advanced Real Time Vibration Monitoring Subsystem proposed by MSFC Transportation Directorate in 2000 for the Space Shuttle Main Engine Advanced Health Management System (AHMS). This Real Time Vibration Monitoring System (RTVMS) is being developed for ground use as part of the AHMS Health Management Computer-Integrated Rack Assembly (HMC-IRA). The HMC-IRA RTVMS design contains five DSPs which are highly interconnected through individual communication ports, shared memory, and a unique communication router that allows all the DSPs to receive digitized data from two multi-channel analog boards simultaneously. This paper will briefly cover the overall board design but will focus primarily on the state-of-the-art simulation environment within which this board was developed. This 16-layer board with over 1800 components and an additional mezzanine card has been an extremely challenging design. Utilization of a Mentor Graphics simulation environment provided the unique board and system level simulation capability to ascertain any timing or functional concerns before production. By combining VHDL, Synopsys Software and Hardware Models, and the Mentor Design Capture Environment, multiple simulations were developed to verify the RTVMS design. This multi-level simulation allowed the designers to achieve complete operability without error the first time the RTVMS printed circuit board was powered. The HMCIRA design has completed all engineering unit testing and the deliverable unit is currently under development.

  17. SEM evaluation of metallization on semiconductors. [Scanning Electron Microscope

    NASA Technical Reports Server (NTRS)

    Fresh, D. L.; Adolphsen, J. W.

    1974-01-01

    A test method for the evaluation of metallization on semiconductors is presented and discussed. The method has been prepared in MIL-STD format for submittal as a proposed addition to MIL-STD-883. It is applicable to discrete devices and to integrated circuits and specifically addresses batch-process oriented defects. Quantitative accept/reject criteria are given for contact windows, other oxide steps, and general interconnecting metallization. Figures are provided that illustrate typical types of defects. Apparatus specifications, sampling plans, and specimen preparation and examination requirements are described. Procedures for glassivated devices and for multi-metal interconnection systems are included.

  18. MULTI-ELECTRODE TUBE PULSE MEMORY CIRCUIT

    DOEpatents

    Gundlach, J.C.; Reeves, J.B.

    1958-05-20

    Control circuits are described for pulse memory devices for scalers and the like, and more particularly to a driving or energizing circuit for a polycathode gaseous discharge tube having an elongated anode and a successive series of cathodes spaced opposite the anode along its length. The circuit is so arranged as to utilize an arc discharge between the anode and a cathode to count a series of pulses. Upon application of an input pulse the discharge is made to occur between the anode and the next successive cathode, and an output pulse is produced when a particular subsequent cathode is reached. The circuit means for transfering the discharge by altering the anode potential and potential of the cathodes and interconnecting the cathodes constitutes the novel aspects of the invention. A low response time and reduced number of circuit components are the practical advantages of the described circuit.

  19. How thin barrier metal can be used to prevent Co diffusion in the modern integrated circuits?

    NASA Astrophysics Data System (ADS)

    Dixit, Hemant; Konar, Aniruddha; Pandey, Rajan; Ethirajan, Tamilmani

    2017-11-01

    In modern integrated circuits (ICs), billions of transistors are connected to each other via thin metal layers (e.g. copper, cobalt, etc) known as interconnects. At elevated process temperatures, inter-diffusion of atomic species can occur among these metal layers, causing sub-optimal performance of interconnects, which may lead to the failure of an IC. Thus, typically a thin barrier metal layer is used to prevent the inter-diffusion of atomic species within interconnects. For ICs with sub-10 nm transistors (10 nm technology node), the design rule (thickness scaling) demands the thinnest possible barrier layer. Therefore, here we investigate the critical thickness of a titanium-nitride (TiN) barrier that can prevent the cobalt diffusion using multi-scale modeling and simulations. First, we compute the Co diffusion barrier in crystalline and amorphous TiN with the nudged elastic band method within first-principles density functional theory simulations. Later, using the calculated activation energy barriers, we quantify the Co diffusion length in the TiN metal layer with the help of kinetic Monte Carlo simulations. Such a multi-scale modelling approach yields an exact critical thickness of the metal layer sufficient to prevent the Co diffusion in IC interconnects. We obtain a diffusion length of a maximum of 2 nm for a typical process of thermal annealing at 400 °C for 30 min. Our study thus provides useful physical insights for the Co diffusion in the TiN layer and further quantifies the critical thickness (~2 nm) to which the metal barrier layer can be thinned down for sub-10 nm ICs.

  20. Microchannel cooling of face down bonded chips

    DOEpatents

    Bernhardt, A.F.

    1993-06-08

    Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multi chip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

  1. Hard and flexible optical printed circuit board

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, Hyun Sik; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

    2007-02-01

    We report on the design and fabrication of hard and flexible optical printed circuit boards (O-PCBs). The objective is to realize generic and application-specific O-PCBs, either in hard form or flexible form, that are compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly, for low-cost and high-volume universal applications. The O-PCBs consist of 2-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate micro/nano-scale photonic devices. The micro/nano-optical functional devices include lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices. For flexible boards, the optical waveguide arrays are fabricated on flexible poly-ethylen terephthalate (PET) substrates by UV embossing. Electrical layer carrying VCSEL and PD array is laminated with the optical layer carrying waveguide arrays. Both hard and flexible electrical lines are replaced with high speed optical interconnection between chips over four waveguide channels up to 10Gbps on each. We discuss uses of hard or flexible O-PCBs for telecommunication systems, computer systems, transportation systems, space/avionic systems, and bio-sensor systems.

  2. Device-level and module-level three-dimensional integrated circuits created using oblique processing

    NASA Astrophysics Data System (ADS)

    Burckel, D. Bruce

    2016-07-01

    This paper demonstrates that another class of three-dimensional integrated circuits (3-D-ICs) exists, distinct from through-silicon-via-centric and monolithic 3-D-ICs. Furthermore, it is possible to create devices that are 3-D "at the device level" (i.e., with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of two-dimensional planar device architecture enables a wide range of interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

  3. Stress redistribution and damage in interconnects caused by electromigration

    NASA Astrophysics Data System (ADS)

    Chiras, Stefanie Ruth

    Electromigration has long been recognized as a phenomenon that induces mass redistribution in metals which, when constrained, can lead to the creation of stress. Since the development of the integrated circuit, electromigration. in interconnects, (the metal lines which carry current between devices in integrated circuits), has become a reliability concern. The primary failure mechanism in the interconnects is usually voiding, which causes electrical resistance increases in the circuit. In some cases, however, another failure mode occurs, fracture of the surrounding dielectric driven by electromigration induced compressive stresses within the interconnect. It is this failure mechanism that is the focus of this thesis. To study dielectric fracture, both residual processing stresses and the development of electromigration induced stress in isolated, constrained interconnects was measured. The high-resolution measurements were made using two types of piezospectroscopy, complemented by finite element analysis (FEA). Both procedures directly measured stress in the underlying or neighboring substrate and used FEA to determine interconnect stresses. These interconnect stresses were related to the effected circuit failure mode through post-test scanning electron microscopy and resistance measurements taken during electromigration testing. The results provide qualitative evidence of electromigration driven passivation fracture, and quantitative analysis of the theoretical model of the failure, the "immortal" interconnect concept.

  4. Optical waveguide circuit board with a surface-mounted optical receiver array

    NASA Astrophysics Data System (ADS)

    Thomson, J. E.; Levesque, Harold; Savov, Emil; Horwitz, Fred; Booth, Bruce L.; Marchegiano, Joseph E.

    1994-03-01

    A photonic circuit board is fabricated for potential application to interchip and interboard parallel optical links. The board comprises photolithographically patterned polymer optical waveguides on a conventional glass-epoxy electrical circuit board and a surface-mounted integrated circuit (IC) package that optically and electrically couples to an optoelectronic IC. The waveguide circuits include eight-channel arrays of straights, cross-throughs, curves, self- aligning interconnects to multi-fiber ribbon, and out-of-plane turning mirrors. A coherent, fused bundle of optical fibers couples light between 45-deg waveguide mirrors and a GaAs receiver array in the IC package. The fiber bundle is easily aligned to the mirrors and the receivers and is amenable to surface mounting and hermetic sealing. The waveguide-receiver- array board achieved error-free data rates up to 1.25 Gbits/s per channel, and modal noise was shown to be negligible.

  5. Electro-optical backplane demonstrator with integrated multimode gradient-index thin glass waveguide panel

    NASA Astrophysics Data System (ADS)

    Schröder, Henning; Brusberg, Lars; Pitwon, Richard; Whalley, Simon; Wang, Kai; Miller, Allen; Herbst, Christian; Weber, Daniel; Lang, Klaus-Dieter

    2015-03-01

    Optical interconnects for data transmission at board level offer increased energy efficiency, system density, and bandwidth scalability compared to purely copper driven systems. We present recent results on manufacturing of electrooptical printed circuit board (PCB) with integrated planar glass waveguides. The graded index multi-mode waveguides are patterned inside commercially available thin-glass panels by performing a specific ion-exchange process. The glass waveguide panel is embedded within the layer stack-up of a PCB using proven industrial processes. This paper describes the design, manufacture, assembly and characterization of the first electro-optical backplane demonstrator based on integrated planar glass waveguides. The electro-optical backplane in question is created by laminating the glass waveguide panel into a conventional multi-layer electronic printed circuit board stack-up. High precision ferrule mounts are automatically assembled, which will enable MT compliant connectors to be plugged accurately to the embedded waveguide interfaces on the glass panel edges. The demonstration platform comprises a standardized sub-rack chassis and five pluggable test cards each housing optical engines and pluggable optical connectors. The test cards support a variety of different data interfaces and can support data rates of up to 32 Gb/s per channel.

  6. Novel Three-Dimensional Vertical Interconnect Technology for Microwave and RF Applications

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.

    1999-01-01

    In this paper, novel 3D interconnects suitable for applications in microwave and RF integrated circuit technology have been presented. The interconnect fabrication process and design details are presented. In addition, measured and numerically modeled results of the performance of the interconnects have been shown. The results indicate that the proposed technology has tremendous potential applications in integrated circuit technology. C,

  7. Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2016-01-01

    This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

  8. Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Spry, David J.; Neudeck, Philip G.; Chen, Liang-Yu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2016-01-01

    This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over approximately 1-micrometer scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

  9. Two-dimensional optoelectronic interconnect-processor and its operational bit error rate

    NASA Astrophysics Data System (ADS)

    Liu, J. Jiang; Gollsneider, Brian; Chang, Wayne H.; Carhart, Gary W.; Vorontsov, Mikhail A.; Simonis, George J.; Shoop, Barry L.

    2004-10-01

    Two-dimensional (2-D) multi-channel 8x8 optical interconnect and processor system were designed and developed using complementary metal-oxide-semiconductor (CMOS) driven 850-nm vertical-cavity surface-emitting laser (VCSEL) arrays and the photodetector (PD) arrays with corresponding wavelengths. We performed operation and bit-error-rate (BER) analysis on this free-space integrated 8x8 VCSEL optical interconnects driven by silicon-on-sapphire (SOS) circuits. Pseudo-random bit stream (PRBS) data sequence was used in operation of the interconnects. Eye diagrams were measured from individual channels and analyzed using a digital oscilloscope at data rates from 155 Mb/s to 1.5 Gb/s. Using a statistical model of Gaussian distribution for the random noise in the transmission, we developed a method to compute the BER instantaneously with the digital eye-diagrams. Direct measurements on this interconnects were also taken on a standard BER tester for verification. We found that the results of two methods were in the same order and within 50% accuracy. The integrated interconnects were investigated in an optoelectronic processing architecture of digital halftoning image processor. Error diffusion networks implemented by the inherently parallel nature of photonics promise to provide high quality digital halftoned images.

  10. Subsurface microscopy of interconnect layers of an integrated circuit.

    PubMed

    Köklü, F Hakan; Unlü, M Selim

    2010-01-15

    We apply the NA-increasing lens technique to confocal and wide-field backside microscopy of integrated circuits. We demonstrate 325 nm (lambda(0)/4) lateral spatial resolution while imaging metal structures located inside the interconnect layer of an integrated circuit. Vectorial field calculations are presented justifying our findings.

  11. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Astrophysics Data System (ADS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  12. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    NASA Technical Reports Server (NTRS)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  13. Trinary flip-flops using Savart plate and spatial light modulator for optical computation in multivalued logic

    NASA Astrophysics Data System (ADS)

    Ghosh, Amal K.; Basuray, Amitabha

    2008-11-01

    The memory devices in multi-valued logic are of most significance in modern research. This paper deals with the implementation of basic memory devices in multi-valued logic using Savart plate and spatial light modulator (SLM) based optoelectronic circuits. Photons are used here as the carrier to speed up the operations. Optical tree architecture (OTA) has been also utilized in the optical interconnection network. We have exploited the advantages of Savart plates, SLMs and OTA and proposed the SLM based high speed JK, D-type and T-type flip-flops in a trinary system.

  14. Advances in integrated photonic circuits for packet-switched interconnection

    NASA Astrophysics Data System (ADS)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  15. Hexagonal boron nitride intercalated multi-layer graphene: a possible ultimate solution to ultra-scaled interconnect technology

    NASA Astrophysics Data System (ADS)

    Li, Yong-Jun; Sun, Qing-Qing; Chen, Lin; Zhou, Peng; Wang, Peng-Fei; Ding, Shi-Jin; Zhang, David Wei

    2012-03-01

    We proposed intercalation of hexagonal boron nitride (hBN) in multilayer graphene to improve its performance in ultra-scaled interconnects for integrated circuit. The effect of intercalated hBN layer in bilayer graphene is investigated using non-equilibrium Green's functions. We find the hBN intercalated bilayer graphene exhibit enhanced transport properties compared with pristine bilayer ones, and the improvement is attributed to suppression of interlayer scattering and good planar bonding condition of inbetween hBN layer. Based on these results, we proposed a via structure that not only benefits from suppressed interlayer scattering between multilayer graphene, but also sustains the unique electrical properties of graphene when many graphene layers are stacking together. The ideal current density across the structure can be as high as 4.6×109 A/cm2 at 1V, which is very promising for the future high-performance interconnect.

  16. Scaling induced performance challenges/limitations of on-chip metal interconnects and comparisons with optical interconnects

    NASA Astrophysics Data System (ADS)

    Kapur, Pawan

    The miniaturization paradigm for silicon integrated circuits has resulted in a tremendous cost and performance advantage. Aggressive shrinking of devices provides faster transistors and a greater functionality for circuit design. However, scaling induced smaller wire cross-sections coupled with longer lengths owing to larger chip areas, result in a steady deterioration of interconnects. This degradation in interconnect trends threatens to slow down the rapid growth along Moore's law. This work predicts that the situation is worse than anticipated. It shows that in the light of technology and reliability constraints, scaling induced increase in electron surface scattering, fractional cross section area occupied by the highly resistive barrier, and realistic interconnect operation temperature will lead to a significant rise in effective resistivity of modern copper based interconnects. We start by discussing various technology factors affecting copper resistivity. We, next, develop simulation tools to model these effects. Using these tools, we quantify the increase in realistic copper resistivity as a function of future technology nodes, under various technology assumptions. Subsequently, we evaluate the impact of these technology effects on delay and power dissipation of global signaling interconnects. Modern long on-chip wires use repeaters, which dramatically improves their delay and bandwidth. We quantify the repeated wire delays and power dissipation using realistic resistance trends at future nodes. With the motivation of reducing power, we formalize a methodology, which trades power with delay very efficiently for repeated wires. Using this method, we find that although the repeater power comes down, the total power dissipation due to wires is still found to be very large at future nodes. Finally, we explore optical interconnects as a possible substitute, for specific interconnect applications. We model an optical receiver and waveguides. Using this we assess future optical system performance. Finally, we compare the delay and power of future metal interconnects with that of optical interconnects for global signaling application. We also compare the power dissipation of the two approaches for an upper level clock distribution application. We find that for long on-chip communication links, optical interconnects have lower latencies than future metal interconnects at comparable levels of power dissipation.

  17. Electronics box having internal circuit cards interconnected to external connectors sans motherboard

    NASA Technical Reports Server (NTRS)

    Hockett, John E. (Inventor)

    2005-01-01

    An electronics chassis box includes a pair of opposing sidewalls, a pair of opposing end walls, a bottom surface, a top cover, and ring connectors assemblies mounted in selective ones of the walls of the electronic box. Boss members extend from the bottom surface at different heights upon which circuit cards are mounted in spatial relationship to each other. A flex interconnect substantially reduces and generally eliminates the need of a motherboard by interconnecting the circuit cards to one another and to external connectors mounted within the ring connector assemblies.

  18. Optical printed circuit board (O-PCB) and VLSI photonic integrated circuits: visions, challenges, and progresses

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, S. G.; O, B. H.; Park, S. G.; Noh, H. S.; Kim, K. H.; Song, S. H.

    2006-09-01

    A collective overview and review is presented on the original work conducted on the theory, design, fabrication, and in-tegration of micro/nano-scale optical wires and photonic devices for applications in a newly-conceived photonic systems called "optical printed circuit board" (O-PCBs) and "VLSI photonic integrated circuits" (VLSI-PIC). These are aimed for compact, high-speed, multi-functional, intelligent, light-weight, low-energy and environmentally friendly, low-cost, and high-volume applications to complement or surpass the capabilities of electrical PCBs (E-PCBs) and/or VLSI electronic integrated circuit (VLSI-IC) systems. These consist of 2-dimensional or 3-dimensional planar arrays of micro/nano-optical wires and circuits to perform the functions of all-optical sensing, storing, transporting, processing, switching, routing and distributing optical signals on flat modular boards or substrates. The integrated optical devices include micro/nano-scale waveguides, lasers, detectors, switches, sensors, directional couplers, multi-mode interference devices, ring-resonators, photonic crystal devices, plasmonic devices, and quantum devices, made of polymer, silicon and other semiconductor materials. For VLSI photonic integration, photonic crystals and plasmonic structures have been used. Scientific and technological issues concerning the processes of miniaturization, interconnection and integration of these systems as applicable to board-to-board, chip-to-chip, and intra-chip integration, are discussed along with applications for future computers, telecommunications, and sensor-systems. Visions and challenges toward these goals are also discussed.

  19. Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

    NASA Technical Reports Server (NTRS)

    Slaughter, D. W.

    1977-01-01

    A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

  20. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chiang, Patrick

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  1. Superconducting Multilayer High-Density Flexible Printed Circuit Board for Very High Thermal Resistance Interconnections

    NASA Astrophysics Data System (ADS)

    de la Broïse, Xavier; Le Coguie, Alain; Sauvageot, Jean-Luc; Pigot, Claude; Coppolani, Xavier; Moreau, Vincent; d'Hollosy, Samuel; Knarosovski, Timur; Engel, Andreas

    2018-05-01

    We have successively developed two superconducting flexible PCBs for cryogenic applications. The first one is monolayer, includes 552 tracks (10 µm wide, 20 µm spacing), and receives 24 wire-bonded integrated circuits. The second one is multilayer, with one track layer between two shielding layers interconnected by microvias, includes 37 tracks, and can be interconnected at both ends by wire bonding or by connectors. The first cold measurements have been performed and show good performances. The novelty of these products is, for the first one, the association of superconducting materials with very narrow pitch and bonded integrated circuits and, for the second one, the introduction of a superconducting multilayer structure interconnected by vias which is, to our knowledge, a world-first.

  2. Multi-petascale highly efficient parallel supercomputer

    DOEpatents

    Asaad, Sameh; Bellofatto, Ralph E.; Blocksome, Michael A.; Blumrich, Matthias A.; Boyle, Peter; Brunheroto, Jose R.; Chen, Dong; Cher, Chen -Yong; Chiu, George L.; Christ, Norman; Coteus, Paul W.; Davis, Kristan D.; Dozsa, Gabor J.; Eichenberger, Alexandre E.; Eisley, Noel A.; Ellavsky, Matthew R.; Evans, Kahn C.; Fleischer, Bruce M.; Fox, Thomas W.; Gara, Alan; Giampapa, Mark E.; Gooding, Thomas M.; Gschwind, Michael K.; Gunnels, John A.; Hall, Shawn A.; Haring, Rudolf A.; Heidelberger, Philip; Inglett, Todd A.; Knudson, Brant L.; Kopcsay, Gerard V.; Kumar, Sameer; Mamidala, Amith R.; Marcella, James A.; Megerian, Mark G.; Miller, Douglas R.; Miller, Samuel J.; Muff, Adam J.; Mundy, Michael B.; O'Brien, John K.; O'Brien, Kathryn M.; Ohmacht, Martin; Parker, Jeffrey J.; Poole, Ruth J.; Ratterman, Joseph D.; Salapura, Valentina; Satterfield, David L.; Senger, Robert M.; Smith, Brian; Steinmacher-Burow, Burkhard; Stockdell, William M.; Stunkel, Craig B.; Sugavanam, Krishnan; Sugawara, Yutaka; Takken, Todd E.; Trager, Barry M.; Van Oosten, James L.; Wait, Charles D.; Walkup, Robert E.; Watson, Alfred T.; Wisniewski, Robert W.; Wu, Peng

    2015-07-14

    A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

  3. Silicon compilation: From the circuit to the system

    NASA Astrophysics Data System (ADS)

    Obrien, Keven

    The methodology used for the compilation of silicon from a behavioral level to a system level is presented. The aim was to link the heretofore unrelated areas of high level synthesis and system level design. This link will play an important role in the development of future design automation tools as it will allow hardware/software co-designs to be synthesized. A design methodology that alllows, through the use of an intermediate representation, SOLAR, a System level Design Language (SDL), to be combined with a Hardware Description Language (VHDL) is presented. Two main steps are required in order to transform this specification into a synthesizable one. Firstly, a system level synthesis step including partitioning and communication synthesis is required in order to split the model into a set of interconnected subsystems, each of which will be processed by a high level synthesis tool. For this latter step AMICAL is used and this allows powerful scheduling techniques to be used, that accept very abstract descriptions of control flow dominated circuits as input, and interconnected RTL blocks that may feed existing logic-level synthesis tools to be generated.

  4. Compensation for Lithography Induced Process Variations during Physical Design

    NASA Astrophysics Data System (ADS)

    Chin, Eric Yiow-Bing

    This dissertation addresses the challenge of designing robust integrated circuits in the deep sub micron regime in the presence of lithography process variability. By extending and combining existing process and circuit analysis techniques, flexible software frameworks are developed to provide detailed studies of circuit performance in the presence of lithography variations such as focus and exposure. Applications of these software frameworks to select circuits demonstrate the electrical impact of these variations and provide insight into variability aware compact models that capture the process dependent circuit behavior. These variability aware timing models abstract lithography variability from the process level to the circuit level and are used to estimate path level circuit performance with high accuracy with very little overhead in runtime. The Interconnect Variability Characterization (IVC) framework maps lithography induced geometrical variations at the interconnect level to electrical delay variations. This framework is applied to one dimensional repeater circuits patterned with both 90nm single patterning and 32nm double patterning technologies, under the presence of focus, exposure, and overlay variability. Studies indicate that single and double patterning layouts generally exhibit small variations in delay (between 1--3%) due to self compensating RC effects associated with dense layouts and overlay errors for layouts without self-compensating RC effects. The delay response of each double patterned interconnect structure is fit with a second order polynomial model with focus, exposure, and misalignment parameters with 12 coefficients and residuals of less than 0.1ps. The IVC framework is also applied to a repeater circuit with cascaded interconnect structures to emulate more complex layout scenarios, and it is observed that the variations on each segment average out to reduce the overall delay variation. The Standard Cell Variability Characterization (SCVC) framework advances existing layout-level lithography aware circuit analysis by extending it to cell-level applications utilizing a physically accurate approach that integrates process simulation, compact transistor models, and circuit simulation to characterize electrical cell behavior. This framework is applied to combinational and sequential cells in the Nangate 45nm Open Cell Library, and the timing response of these cells to lithography focus and exposure variations demonstrate Bossung like behavior. This behavior permits the process parameter dependent response to be captured in a nine term variability aware compact model based on Bossung fitting equations. For a two input NAND gate, the variability aware compact model captures the simulated response to an accuracy of 0.3%. The SCVC framework is also applied to investigate advanced process effects including misalignment and layout proximity. The abstraction of process variability from the layout level to the cell level opens up an entire new realm of circuit analysis and optimization and provides a foundation for path level variability analysis without the computationally expensive costs associated with joint process and circuit simulation. The SCVC framework is used with slight modification to illustrate the speedup and accuracy tradeoffs of using compact models. With variability aware compact models, the process dependent performance of a three stage logic circuit can be estimated to an accuracy of 0.7% with a speedup of over 50,000. Path level variability analysis also provides an accurate estimate (within 1%) of ring oscillator period in well under a second. Another significant advantage of variability aware compact models is that they can be easily incorporated into existing design methodologies for design optimization. This is demonstrated by applying cell swapping on a logic circuit to reduce the overall delay variability along a circuit path. By including these variability aware compact models in cell characterization libraries, design metrics such as circuit timing, power, area, and delay variability can be quickly assessed to optimize for the correct balance of all design metrics, including delay variability. Deterministic lithography variations can be easily captured using the variability aware compact models described in this dissertation. However, another prominent source of variability is random dopant fluctuations, which affect transistor threshold voltage and in turn circuit performance. The SCVC framework is utilized to investigate the interactions between deterministic lithography variations and random dopant fluctuations. Monte Carlo studies show that the output delay distribution in the presence of random dopant fluctuations is dependent on lithography focus and exposure conditions, with a 3.6 ps change in standard deviation across the focus exposure process window. This indicates that the electrical impact of random variations is dependent on systematic lithography variations, and this dependency should be included for precise analysis.

  5. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-06-24

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping lase pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  6. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1987-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  7. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, David B.

    1989-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is anarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  8. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1985-08-23

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  9. Planarization of metal films for multilevel interconnects

    DOEpatents

    Tuckerman, D.B.

    1989-03-21

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration. 6 figs.

  10. Low-dielectric constant insulators for future integrated circuits and packages.

    PubMed

    Kohl, Paul A

    2011-01-01

    Future integrated circuits and packages will require extraordinary dielectric materials for interconnects to allow transistor advances to be translated into system-level advances. Exceedingly low-permittivity and low-loss materials are required at every level of the electronic system, from chip-level insulators to packages and printed wiring boards. In this review, the requirements and goals for future insulators are discussed followed by a summary of current state-of-the-art materials and technical approaches. Much work needs to be done for insulating materials and structures to meet future needs.

  11. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  12. Fault-Tolerant Control of ANPC Three-Level Inverter Based on Order-Reduction Optimal Control Strategy under Multi-Device Open-Circuit Fault.

    PubMed

    Xu, Shi-Zhou; Wang, Chun-Jie; Lin, Fang-Li; Li, Shi-Xiang

    2017-10-31

    The multi-device open-circuit fault is a common fault of ANPC (Active Neutral-Point Clamped) three-level inverter and effect the operation stability of the whole system. To improve the operation stability, this paper summarized the main solutions currently firstly and analyzed all the possible states of multi-device open-circuit fault. Secondly, an order-reduction optimal control strategy was proposed under multi-device open-circuit fault to realize fault-tolerant control based on the topology and control requirement of ANPC three-level inverter and operation stability. This control strategy can solve the faults with different operation states, and can works in order-reduction state under specific open-circuit faults with specific combined devices, which sacrifices the control quality to obtain the stability priority control. Finally, the simulation and experiment proved the effectiveness of the proposed strategy.

  13. Thin-film decoupling capacitors for multi-chip modules

    NASA Astrophysics Data System (ADS)

    Dimos, D.; Lockwood, S. J.; Schwartz, R. W.; Rogers, M. S.

    Thin-film decoupling capacitors based on ferroelectric lead lanthanum zirconate titanate (PLZT) films are being developed for use in advanced packages, such as multi-chip modules. These thin-film decoupling capacitors are intended to replace multi-layer ceramic capacitors for certain applications, since they can be more fully integrated into the packaging architecture. The increased integration that can be achieved should lead to decreased package volume and improved high-speed performance, due to a decrease in interconnect inductance. PLZT films are fabricated by spin coating using metal carboxylate/alkoxide solutions. These films exhibit very high dielectric constants ((var epsilon) greater than or equal to 900), low dielectric losses (tan(delta) = 0.01), excellent insulation resistances (rho greater than 10(exp 13) (Omega)-cm at 125 C), and good breakdown field strengths (E(sub B) = 900 kV/cm). For integrated circuit applications, the PLZT dielectric is less than 1 micron thick, which results in a large capacitance/area (8-9 nF/sq mm). The thin-film geometry and processing conditions also make these capacitors suitable for direct incorporation onto integrated circuits and for packages that require embedded components.

  14. Chip-To-Chip Optical Interconnection Using MEMS Mirrors

    DTIC Science & Technology

    2009-03-26

    the Figure 2.3: SEM of a 2D micromirror with embedded polysilicon circuit paths within the frame structures which drives individual thermal actuation...single-crystal silicon micromirror for large bi-directional 2d scanning applications,” Sens. and Actuators, A, vol. 130-131, pp. 454–460, 8/14 2006. 14...thesis (m.s.), AFIT, Mar 2008. AFIT/GEO/ENP/08-03. 17. B. McCarthy, V. M. Bright, and J. A. Neff, “A multi-component solder self- assembled micromirror

  15. Planarization of metal films for multilevel interconnects by pulsed laser heating

    DOEpatents

    Tuckerman, David B.

    1987-01-01

    In the fabrication of multilevel integrated circuits, each metal layer is planarized by heating to momentarily melt the layer. The layer is melted by sweeping laser pulses of suitable width, typically about 1 microsecond duration, over the layer in small increments. The planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers. The planarization method is particularly applicable to circuits having ground or power planes and allows for multilevel interconnects. Dielectric layers can also be planarized to produce a fully planar multilevel interconnect structure. The method is useful for the fabrication of VLSI circuits, particularly for wafer-scale integration.

  16. Ultra high speed image processing techniques. [electronic packaging techniques

    NASA Technical Reports Server (NTRS)

    Anthony, T.; Hoeschele, D. F.; Connery, R.; Ehland, J.; Billings, J.

    1981-01-01

    Packaging techniques for ultra high speed image processing were developed. These techniques involve the development of a signal feedthrough technique through LSI/VLSI sapphire substrates. This allows the stacking of LSI/VLSI circuit substrates in a 3 dimensional package with greatly reduced length of interconnecting lines between the LSI/VLSI circuits. The reduced parasitic capacitances results in higher LSI/VLSI computational speeds at significantly reduced power consumption levels.

  17. Healing Voids In Interconnections In Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Cuddihy, Edward F.; Lawton, Russell A.; Gavin, Thomas

    1989-01-01

    Unusual heat treatment heals voids in aluminum interconnections on integrated circuits (IC's). Treatment consists of heating IC to temperature between 200 degrees C and 400 degrees C, holding it at that temperature, and then plunging IC immediately into liquid nitrogen. Typical holding time at evaluated temperature is 30 minutes.

  18. Optomechanical Design and Characterization of a Printed-Circuit-Board-Based Free-Space Optical Interconnect Package

    NASA Astrophysics Data System (ADS)

    Zheng, Xuezhe; Marchand, Philippe J.; Huang, Dawei; Kibar, Osman; Ozkan, Nur S. E.; Esener, Sadik C.

    1999-09-01

    We present a proof of concept and a feasibility demonstration of a practical packaging approach in which free-space optical interconnects (FSOI s) can be integrated simply on electronic multichip modules (MCM s) for intra-MCM board interconnects. Our system-level packaging architecture is based on a modified folded 4 f imaging system that has been implemented with only off-the-shelf optics, conventional electronic packaging, and passive-assembly techniques to yield a potentially low-cost and manufacturable packaging solution. The prototypical system as built supports 48 independent FSOI channels with 8 separate laser and detector chips, for which each chip consists of a one-dimensional array of 12 devices. All the chips are assembled on a single substrate that consists of a printed circuit board or a ceramic MCM. Optical link channel efficiencies of greater than 90% and interchannel cross talk of less than 20 dB at low frequency have been measured. The system is compact at only 10 in. 3 (25.4 cm 3 ) and is scalable, as it can easily accommodate additional chips as well as two-dimensional optoelectronic device arrays for increased interconnection density.

  19. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.

    1998-06-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC.

  20. Monolithically mode division multiplexing photonic integrated circuit for large-capacity optical interconnection.

    PubMed

    Chen, Guanyu; Yu, Yu; Zhang, Xinliang

    2016-08-01

    We propose and fabricate an on-chip mode division multiplexed (MDM) photonic interconnection system. Such a monolithically photonic integrated circuit (PIC) is composed of a grating coupler, two micro-ring modulators, mode multiplexer/demultiplexer, and two germanium photodetectors. The signals' generation, multiplexing, transmission, demultiplexing, and detection are successfully demonstrated on the same chip. Twenty Gb/s MDM signals are successfully processed with clear and open eye diagrams, validating the feasibility of the proposed circuit. The measured power penalties show a good performance of the MDM link. The proposed on-chip MDM system can be potentially used for large-capacity optical interconnection in future high-performance computers and big data centers.

  1. Implementation of interconnect simulation tools in spice

    NASA Technical Reports Server (NTRS)

    Satsangi, H.; Schutt-Aine, J. E.

    1993-01-01

    Accurate computer simulation of high speed digital computer circuits and communication circuits requires a multimode approach to simulate both the devices and the interconnects between devices. Classical circuit analysis algorithms (lumped parameter) are needed for circuit devices and the network formed by the interconnected devices. The interconnects, however, have to be modeled as transmission lines which incorporate electromagnetic field analysis. An approach to writing a multimode simulator is to take an existing software package which performs either lumped parameter analysis or field analysis and add the missing type of analysis routines to the package. In this work a traditionally lumped parameter simulator, SPICE, is modified so that it will perform lossy transmission line analysis using a different model approach. Modifying SPICE3E2 or any other large software package is not a trivial task. An understanding of the programming conventions used, simulation software, and simulation algorithms is required. This thesis was written to clarify the procedure for installing a device into SPICE3E2. The installation of three devices is documented and the installations of the first two provide a foundation for installation of the lossy line which is the third device. The details of discussions are specific to SPICE, but the concepts will be helpful when performing installations into other circuit analysis packages.

  2. Separate Poles Mode for Large-Capacity HVDC System

    NASA Astrophysics Data System (ADS)

    Zhu, Lin; Gao, Qin

    2017-05-01

    This paper proposes a novel connection mode, separate poles mode (SPM), for large-capacity HVDC systems. The proposed mode focuses on the core issues of HVDC connection in interconnected power grids and principally aims at increasing effective electric distance between poles, which helps to mitigate the interaction problems between AC system and DC system. Receiving end of bipolar HVDC has been divided into different inverter stations under the mode, and thus significantly alleviates difficulties in power transmission and consumption of receiving-end AC grids. By investigating the changes of multi-feed short-circuit ratio (MISCR), finding that HVDC with SPM shows critical impacts upon itself and other HVDC systems with conventional connection mode, which demonstrates that SPM can make balance between MISCR increase and short-circuit current limit.

  3. Re-using biological devices: a model-aided analysis of interconnected transcriptional cascades designed from the bottom-up.

    PubMed

    Pasotti, Lorenzo; Bellato, Massimo; Casanova, Michela; Zucca, Susanna; Cusella De Angelis, Maria Gabriella; Magni, Paolo

    2017-01-01

    The study of simplified, ad-hoc constructed model systems can help to elucidate if quantitatively characterized biological parts can be effectively re-used in composite circuits to yield predictable functions. Synthetic systems designed from the bottom-up can enable the building of complex interconnected devices via rational approach, supported by mathematical modelling. However, such process is affected by different, usually non-modelled, unpredictability sources, like cell burden. Here, we analyzed a set of synthetic transcriptional cascades in Escherichia coli . We aimed to test the predictive power of a simple Hill function activation/repression model (no-burden model, NBM) and of a recently proposed model, including Hill functions and the modulation of proteins expression by cell load (burden model, BM). To test the bottom-up approach, the circuit collection was divided into training and test sets, used to learn individual component functions and test the predicted output of interconnected circuits, respectively. Among the constructed configurations, two test set circuits showed unexpected logic behaviour. Both NBM and BM were able to predict the quantitative output of interconnected devices with expected behaviour, but only the BM was also able to predict the output of one circuit with unexpected behaviour. Moreover, considering training and test set data together, the BM captures circuits output with higher accuracy than the NBM, which is unable to capture the experimental output exhibited by some of the circuits even qualitatively. Finally, resource usage parameters, estimated via BM, guided the successful construction of new corrected variants of the two circuits showing unexpected behaviour. Superior descriptive and predictive capabilities were achieved considering resource limitation modelling, but further efforts are needed to improve the accuracy of models for biological engineering.

  4. Electrically driven monolithic subwavelength plasmonic interconnect circuits

    PubMed Central

    Liu, Yang; Zhang, Jiasen; Liu, Huaping; Wang, Sheng; Peng, Lian-Mao

    2017-01-01

    In the post-Moore era, an electrically driven monolithic optoelectronic integrated circuit (OEIC) fabricated from a single material is pursued globally to enable the construction of wafer-scale compact computing systems with powerful processing capabilities and low-power consumption. We report a monolithic plasmonic interconnect circuit (PIC) consisting of a photovoltaic (PV) cascading detector, Au-strip waveguides, and electrically driven surface plasmon polariton (SPP) sources. These components are fabricated from carbon nanotubes (CNTs) via a CMOS (complementary metal-oxide semiconductor)–compatible doping-free technique in the same feature size, which can be reduced to deep-subwavelength scale (~λ/7 to λ/95, λ = 1340 nm) compared with the 14-nm technique node. An OEIC could potentially be configured as a repeater for data transport because of its “photovoltaic” operation mode to transform SPP energy directly into electricity to drive subsequent electronic circuits. Moreover, chip-scale throughput capability has also been demonstrated by fabricating a 20 × 20 PIC array on a 10 mm × 10 mm wafer. Tailoring photonics for monolithic integration with electronics beyond the diffraction limit opens a new era of chip-level nanoscale electronic-photonic systems, introducing a new path to innovate toward much faster, smaller, and cheaper computing frameworks. PMID:29062890

  5. Fiber bundle probes for interconnecting miniaturized medical imaging devices

    NASA Astrophysics Data System (ADS)

    Zamora, Vanessa; Hofmann, Jens; Marx, Sebastian; Herter, Jonas; Nguyen, Dennis; Arndt-Staufenbiel, Norbert; Schröder, Henning

    2017-02-01

    Miniaturization of medical imaging devices will significantly improve the workflow of physicians in hospitals. Photonic integrated circuit (PIC) technologies offer a high level of miniaturization. However, they need fiber optic interconnection solutions for their functional integration. As part of European funded project (InSPECT) we investigate fiber bundle probes (FBPs) to be used as multi-mode (MM) to single-mode (SM) interconnections for PIC modules. The FBP consists of a set of four or seven SM fibers hexagonally distributed and assembled into a holder that defines a multicore connection. Such a connection can be used to connect MM fibers, while each SM fiber is attached to the PIC module. The manufacturing of these probes is explored by using well-established fiber fusion, epoxy adhesive, innovative adhesive and polishing techniques in order to achieve reliable, low-cost and reproducible samples. An innovative hydrofluoric acid-free fiber etching technology has been recently investigated. The preliminary results show that the reduction of the fiber diameter shows a linear behavior as a function of etching time. Different etch rate values from 0.55 μm/min to 2.3 μm/min were found. Several FBPs with three different type of fibers have been optically interrogated at wavelengths of 630nm and 1550nm. Optical losses are found of approx. 35dB at 1550nm for FBPs composed by 80μm fibers. Although FBPs present moderate optical losses, they might be integrated using different optical fibers, covering a broad spectral range required for imaging applications. Finally, we show the use of FBPs as promising MM-to-SM interconnects for real-world interfacing to PIC's.

  6. Viewing Integrated-Circuit Interconnections By SEM

    NASA Technical Reports Server (NTRS)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  7. Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

    PubMed Central

    Huang, Yue; Mason, Andrew J.

    2013-01-01

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

  8. Lab-on-CMOS integration of microfluidics and electrochemical sensors.

    PubMed

    Huang, Yue; Mason, Andrew J

    2013-10-07

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

  9. Electronic interconnects and devices with topological surface states and methods for fabricating same

    DOEpatents

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2017-04-04

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  10. Electronic interconnects and devices with topological surface states and methods for fabricating same

    DOEpatents

    Yazdani, Ali; Ong, N. Phuan; Cava, Robert J.

    2016-05-03

    An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

  11. Beam forming network

    NASA Technical Reports Server (NTRS)

    Cramer, P. W., Jr. (Inventor)

    1985-01-01

    The network, which is connected to a layer of 134 feed elements that transmit and receive microwaves, consists of a pair of circuit boards parallel to the feed element layer. One of the two boards has 87 dividers that each divide a signal to be transmitted into seven portions, and the other board has 134 combiners that each collect seven transmit signal portions and deliver the sum to one of the feed elements. A similar arrangement is used to handle received signals. The large number of interconnections are made by printed circuit conductors radiating from each of the numerous dividers and combiners, and by providing interconnection pins that interconnect the ends of pairs of conductors lying on the two boards. The printed circuit conductors extend in undulating paths that provide maximum separation of conductors to minimize crosstalk.

  12. Computation for Electromigration in Interconnects of Microelectronic Devices

    NASA Astrophysics Data System (ADS)

    Averbuch, Amir; Israeli, Moshe; Ravve, Igor; Yavneh, Irad

    2001-03-01

    Reliability and performance of microelectronic devices depend to a large extent on the resistance of interconnect lines. Voids and cracks may occur in the interconnects, causing a severe increase in the total resistance and even open circuits. In this work we analyze void motion and evolution due to surface diffusion effects and applied external voltage. The interconnects under consideration are three-dimensional (sandwich) constructs made of a very thin metal film of possibly variable thickness attached to a substrate of nonvanishing conductance. A two-dimensional level set approach was applied to study the dynamics of the moving (assumed one-dimensional) boundary of a void in the metal film. The level set formulation of an electromigration and diffusion model results in a fourth-order nonlinear (two-dimensional) time-dependent PDE. This equation was discretized by finite differences on a regular grid in space and a Runge-Kutta integration scheme in time, and solved simultaneously with a second-order static elliptic PDE describing the electric potential distribution throughout the interconnect line. The well-posed three-dimensional problem for the potential was approximated via singular perturbations, in the limit of small aspect ratio, by a two-dimensional elliptic equation with variable coefficients describing the combined local conductivity of metal and substrate (which is allowed to vary in time and space). The difference scheme for the elliptic PDE was solved by a multigrid technique at each time step. Motion of voids in both weak and strong electric fields was examined, and different initial void configurations were considered, including circles, ellipses, polygons with rounded corners, a butterfly, and long grooves. Analysis of the void behavior and its influence on the resistance gives the circuit designer a tool for choosing the proper parameters of an interconnect (width-to-length ratio, properties of the line material, conductivity of the underlayer, etc.).

  13. Power inverter with optical isolation

    DOEpatents

    Duncan, Paul G.; Schroeder, John Alan

    2005-12-06

    An optically isolated power electronic power conversion circuit that includes an input electrical power source, a heat pipe, a power electronic switch or plurality of interconnected power electronic switches, a mechanism for connecting the switch to the input power source, a mechanism for connecting comprising an interconnecting cable and/or bus bar or plurality of interconnecting cables and/or input bus bars, an optically isolated drive circuit connected to the switch, a heat sink assembly upon which the power electronic switch or switches is mounted, an output load, a mechanism for connecting the switch to the output load, the mechanism for connecting including an interconnecting cable and/or bus bar or plurality of interconnecting cables and/or output bus bars, at least one a fiber optic temperature sensor mounted on the heat sink assembly, at least one fiber optic current sensor mounted on the load interconnection cable and/or output bus bar, at least one fiber optic voltage sensor mounted on the load interconnection cable and/or output bus bar, at least one fiber optic current sensor mounted on the input power interconnection cable and/or input bus bar, and at least one fiber optic voltage sensor mounted on the input power interconnection cable and/or input bus bar.

  14. A self-assembled synthesis of carbon nanotubes for interconnects.

    PubMed

    Chen, Zexiang; Cao, Guichuan; Lin, Zulun; Koehler, Irmgard; Bachmann, Peter K

    2006-02-28

    We report a novel approach to grow highly oriented, freestanding and structured carbon nanotubes (CNTs) between two substrates, using microwave plasma chemical vapour deposition. Sandwiched, multi-layered catalyst structures are employed to generate such structures. The as-grown CNTs adhere well to both the substrate and the top contact, and provide a low-resistance electric contact between the two. High-resolution scanning electron microscope (SEM) images show that the CNTs grow perpendicular to these surfaces. This presents a simple way to grow CNTs in different, predetermined directions in a single growth step. The overall resistance of a CNT bundle and two CNT-terminal contacts is measured to be about 14.7 k Ω. The corresponding conductance is close to the quantum limit conductance G(0). This illustrates that our new approach is promising for the direct assembly of CNT-based interconnects in integrated circuits (ICs) or other micro-electronic devices.

  15. Multilevel photonic modules for millimeter-wave phased-array antennas

    NASA Astrophysics Data System (ADS)

    Paolella, Arthur C.; Joshi, Abhay M.; Wright, James G.; Coryell, Louis A.

    1998-11-01

    Optical signal distribution for phased array antennas in communication system is advantageous to designers. By distributing the microwave and millimeter wave signal through optical fiber there is the potential for improved performance and lower weight. In addition when applied to communication satellites this weight saving translates into substantially reduced launch costs. The goal of the Phase I Small Business Innovation Research (SBIR) Program is the development of multi-level photonic modules for phased array antennas. The proposed module with ultimately comprise of a monolithic, InGaAs/InP p-i-n photodetector-p-HEMT power amplifier, opto-electronic integrated circuit, that has 44 GHz bandwidth and output power of 50 mW integrated with a planar antenna. The photodetector will have a high quantum efficiency and will be front-illuminated, thereby improved optical performance. Under Phase I a module was developed using standard MIC technology with a high frequency coaxial feed interconnect.

  16. Printed circuit board impedance matching step for microwave (millimeter wave) devices

    DOEpatents

    Pao, Hsueh-Yuan; Aguirre, Jerardo; Sargis, Paul

    2013-10-01

    An impedance matching ground plane step, in conjunction with a quarter wave transformer section, in a printed circuit board provides a broadband microwave matching transition from board connectors or other elements that require thin substrates to thick substrate (>quarter wavelength) broadband microwave (millimeter wave) devices. A method of constructing microwave and other high frequency electrical circuits on a substrate of uniform thickness, where the circuit is formed of a plurality of interconnected elements of different impedances that individually require substrates of different thicknesses, by providing a substrate of uniform thickness that is a composite or multilayered substrate; and forming a pattern of intermediate ground planes or impedance matching steps interconnected by vias located under various parts of the circuit where components of different impedances are located so that each part of the circuit has a ground plane substrate thickness that is optimum while the entire circuit is formed on a substrate of uniform thickness.

  17. High density circuit technology, part 2

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    A multilevel metal interconnection system for very large scale integration (VLSI) systems utilizing polyimides as the interlayer dielectric material is described. A complete characterization of polyimide materials is given as well as experimental methods accomplished using a double level metal test pattern. A low temperature, double exposure polyimide patterning procedure is also presented.

  18. Photolithography-Based Patterning of Liquid Metal Interconnects for Monolithically Integrated Stretchable Circuits.

    PubMed

    Park, Chan Woo; Moon, Yu Gyeong; Seong, Hyejeong; Jung, Soon Won; Oh, Ji-Young; Na, Bock Soon; Park, Nae-Man; Lee, Sang Seok; Im, Sung Gap; Koo, Jae Bon

    2016-06-22

    We demonstrate a new patterning technique for gallium-based liquid metals on flat substrates, which can provide both high pattern resolution (∼20 μm) and alignment precision as required for highly integrated circuits. In a very similar manner as in the patterning of solid metal films by photolithography and lift-off processes, the liquid metal layer painted over the whole substrate area can be selectively removed by dissolving the underlying photoresist layer, leaving behind robust liquid patterns as defined by the photolithography. This quick and simple method makes it possible to integrate fine-scale interconnects with preformed devices precisely, which is indispensable for realizing monolithically integrated stretchable circuits. As a way for constructing stretchable integrated circuits, we propose a hybrid configuration composed of rigid device regions and liquid interconnects, which is constructed on a rigid substrate first but highly stretchable after being transferred onto an elastomeric substrate. This new method can be useful in various applications requiring both high-resolution and precisely aligned patterning of gallium-based liquid metals.

  19. Thin glass based packaging and photonic single-mode waveguide integration by ion-exchange technology on board and module level

    NASA Astrophysics Data System (ADS)

    Brusberg, Lars; Lang, Günter; Schröder, Henning

    2011-01-01

    The proposed novel packaging approach merges micro-system packaging and glass integrated optics. It provides 3D optical single-mode intra system links to bridge the gap between novel photonic integrated circuits and the glass fibers for inter system interconnects. We introduce our hybrid 3D photonic packaging approach based on thin glass substrates with planar integrated optical single-mode waveguides for fiber-to-chip and chip-to-chip links. Optical mirrors and lenses provide optical mode matching for photonic IC assemblies and optical fiber interconnects. Thin glass is commercially available in panel and wafer formats and characterizes excellent optical and high-frequency properties as reviewed in the paper. That makes it perfect for micro-system packaging. The adopted planar waveguide process based on ion-exchange technology is capable for high-volume manufacturing. This ion-exchange process and the optical propagation are described in detail for thin glass substrates. An extensive characterization of all basic circuit elements like straight and curved waveguides, couplers and crosses proves the low attenuation of the optical circuit elements.

  20. Optimized Signaling Method for High-Speed Transmission Channels with Higher Order Transfer Function

    NASA Astrophysics Data System (ADS)

    Ševčík, Břetislav; Brančík, Lubomír; Kubíček, Michal

    2017-08-01

    In this paper, the selected results from testing of optimized CMOS friendly signaling method for high-speed communications over cables and printed circuit boards (PCBs) are presented and discussed. The proposed signaling scheme uses modified concept of pulse width modulated (PWM) signal which enables to better equalize significant channel losses during data high-speed transmission. Thus, the very effective signaling method to overcome losses in transmission channels with higher order transfer function, typical for long cables and multilayer PCBs, is clearly analyzed in the time and frequency domain. Experimental results of the measurements include the performance comparison of conventional PWM scheme and clearly show the great potential of the modified signaling method for use in low power CMOS friendly equalization circuits, commonly considered in modern communication standards as PCI-Express, SATA or in Multi-gigabit SerDes interconnects.

  1. Laser Direct Routing for High Density Interconnects

    NASA Astrophysics Data System (ADS)

    Moreno, Wilfrido Alejandro

    The laser restructuring of electronic circuits fabricated using standard Very Large Scale Integration (VLSI) process techniques, is an excellent alternative that allows low-cost quick turnaround production with full circuit similarity between the Laser Restructured prototype and the customized product for mass production. Laser Restructurable VLSI (LRVLSI) would allow design engineers the capability to interconnect cells that implement generic logic functions and signal processing schemes to achieve a higher level of design complexity. LRVLSI of a particular circuit at the wafer or packaged chip level is accomplished using an integrated computer controlled laser system to create low electrical resistance links between conductors and to cut conductor lines. An infrastructure for rapid prototyping and quick turnaround using Laser Restructuring of VLSI circuits was developed to meet three main parallel objectives: to pursue research on novel interconnect technologies using LRVLSI, to develop the capability of operating in a quick turnaround mode, and to maintain standardization and compatibility with commercially available equipment for feasible technology transfer. The system is to possess a high degree of flexibility, high data quality, total controllability, full documentation, short downtime, a user-friendly operator interface, automation, historical record keeping, and error indication and logging. A specially designed chip "SLINKY" was used as the test vehicle for the complete characterization of the Laser Restructuring system. With the use of Design of Experiment techniques the Lateral Diffused Link (LDL), developed originally at MIT Lincoln Laboratories, was completely characterized and for the first time a set of optimum process parameters was obtained. With the designed infrastructure fully operational, the priority objective was the search for a substitute for the high resistance, high current leakage to substrate, and relatively low density Lateral Diffused Link. A high density Laser Vertical Link with resistance values below 10 ohms was developed, studied and tested using design of experiment methodologies. The vertical link offers excellent advantages in the area of quick prototyping of electronic circuits, but even more important, due to having similar characteristics to a foundry produced via, it gives quick transfer from the prototype system verification stage to the mass production stage.

  2. A novel FPGA-programmable switch matrix interconnection element in quantum-dot cellular automata

    NASA Astrophysics Data System (ADS)

    Hashemi, Sara; Rahimi Azghadi, Mostafa; Zakerolhosseini, Ali; Navi, Keivan

    2015-04-01

    The Quantum-dot cellular automata (QCA) is a novel nanotechnology, promising extra low-power, extremely dense and very high-speed structure for the construction of logical circuits at a nanoscale. In this paper, initially previous works on QCA-based FPGA's routing elements are investigated, and then an efficient, symmetric and reliable QCA programmable switch matrix (PSM) interconnection element is introduced. This element has a simple structure and offers a complete routing capability. It is implemented using a bottom-up design approach that starts from a dense and high-speed 2:1 multiplexer and utilise it to build the target PSM interconnection element. In this study, simulations of the proposed circuits are carried out using QCAdesigner, a layout and simulation tool for QCA circuits. The results demonstrate high efficiency of the proposed designs in QCA-based FPGA routing.

  3. Optical interconnects for in-plane high-speed signal distribution at 10 Gb/s: Analysis and demonstration

    NASA Astrophysics Data System (ADS)

    Chang, Yin-Jung

    With decreasing transistor size, increasing chip speed, and larger numbers of processors in a system, the performance of a module/system is being limited by the off-chip and off-module bandwidth-distance products. Optical links have moved from fiber-based long distance communications to the cabinet level of 1m--100m, and recently to the backplane-level (10cm--1m). Board-level inter-chip parallel optical interconnects have been demonstrated recently by researchers from Intel, IBM, Fujitsu, NTT and a few research groups in universities. However, the board-level signal/clock distribution function using optical interconnects, the lightwave circuits, the system design, a practically convenient integration scheme committed to the implementation of a system prototype have not been explored or carefully investigated. In this dissertation, the development of a board-level 1 x 4 optical-to-electrical signal distribution at 10Gb/s is presented. In contrast to other prototypes demonstrating board-level parallel optical interconnects that have been drawing much attention for the past decade, the optical link design for the high-speed signal broadcasting is even more complicated and the pitch between receivers could be varying as opposed to fixed-pitch design that has been widely-used in the parallel optical interconnects. New challenges for the board-level high-speed signal broadcasting include, but are not limited to, a new optical link design, a lightwave circuit as a distribution network, and a novel integration scheme that can be a complete radical departure from the traditional assembly method. One of the key building blocks in the lightwave circuit is the distribution network in which a 1 x 4 multimode interference (MMI) splitter is employed. MMI devices operating at high data rates are important in board-level optical interconnects and need to be characterized in the application of board-level signal broadcasting. To determine the speed limitations of MMI devices, the ultra-short pulse response of these devices is modeled based on the guided-mode theory incorporated with Fourier transform technique. For example, for 50 fs Gaussian input pulses into a 1 x 16 splitter, the output pulses are severely degraded in coupling efficiency (48%) and completely broken up in time primarily due to inter-modal and intra-modal (waveguide) dispersion. Material dispersion is found to play only a minor role in the pulse response of MMI devices. However, for 1ps input pulses into the same 1 x 16 splitter, the output pulses are only moderately degraded in coupling efficiency (86%) and only slightly degraded in shape. With the understanding of the necessary condition of the distortionless high-speed signal transmission through MMI devices, high-speed data transmission at 40Gb/s per channel with a total bandwidth of 320Gb/s for 8 output ports is demonstrated for the first time on a 1 x 8 photo-definable polymer-based MMI power splitter. The device is designed with multimode input/output waveguides of 10mum in width and 7.6mum in height for a better input coupling efficiency for which the high-speed testing demands. The eye diagrams are all clear and fully open with an extinction ratio of 10.1dB and a jitter of 1.65 ps. The transmission validity is further confirmed by the bit-error-rate testing at the pseudoramdom binary sequence of 27--1. The fabrication process developed lays the cornerstone of the integration scheme and system design for the prototype of hybrid interconnects. An important problem regarding the guided-mode attenuation associated with optical-interconnect-polymer waveguides fabricated on FR-4 printed-circuit boards is also quantified for the first time. On-board optical waveguides are receiving more attention recently from Fujitsu American Laboratory, IBM Watson Research Center, and Packaging Research Center here at Georgia Tech. This branch of research work is part of the effort in investigating, scientifically, the attenuation mechanism and the effects of the buffer layer thickness on board-level in-plane optical interconnects. The rigorous transmission-line network approach is used and the FR-4 substrate is treated as a long-period substrate grating. A quantitative metric for an appropriate matrix truncation is presented. The peaks of attenuation are shown to occur near the Bragg conditions that characterize the leaky-wave stop bands. For a typical 400mum period FR-4 substrate with an 8mum corrugation depth, a buffer layer thickness of about 40mum is found to be needed to make the attenuation negligibly small. An experimental prototype for on-board optical-to-electrical signal broadcasting operating at 10Gb/s per channel over an interconnect distance of 10cm is demonstrated. An improved 1 x 4 multimode interference (MMI) splitter at 1550nm with linearly-tapered output facet is heterogeneously integrated with four p-i-n photodetectors (PDs) on a Silicon (Si) bench. The Si bench itself is hybrid integrated onto an FR-4 printed-circuit board with four receiver channels. A novel fabrication/integration approach demonstrates the simultaneous alignment between the four waveguides and the four PDs during the MMI fabrication process. The entire system is fully functional at 10Gb/s.

  4. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, D.B.

    1988-06-06

    Integrated circuit chips are electrically connected to a silicon wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability. 6 figs.

  5. Thin-film chip-to-substrate interconnect and methods for making same

    DOEpatents

    Tuckerman, David B.

    1991-01-01

    Integrated circuit chips are electrically connected to a silica wafer interconnection substrate. Thin film wiring is fabricated down bevelled edges of the chips. A subtractive wire fabrication method uses a series of masks and etching steps to form wires in a metal layer. An additive method direct laser writes or deposits very thin metal lines which can then be plated up to form wires. A quasi-additive or subtractive/additive method forms a pattern of trenches to expose a metal surface which can nucleate subsequent electrolytic deposition of wires. Low inductance interconnections on a 25 micron pitch (1600 wires on a 1 cm square chip) can be produced. The thin film hybrid interconnect eliminates solder joints or welds, and minimizes the levels of metallization. Advantages include good electrical properties, very high wiring density, excellent backside contact, compactness, and high thermal and mechanical reliability.

  6. Overload-protector/fault-indicator circuit

    NASA Technical Reports Server (NTRS)

    Paluka, J. R.; Moore, S. F.

    1977-01-01

    Circuit incorporates three-terminal current limiter (78M24) to increase overall reliability and to eliminate transistor burnouts resulting from shorted interconnection lines and other overloads. Fact-acting light emitting diodes across the limiters show status of transistor output circuits.

  7. Applications of SPICE for modeling miniaturized biomedical sensor systems

    NASA Technical Reports Server (NTRS)

    Mundt, C. W.; Nagle, H. T.

    2000-01-01

    This paper proposes a model for a miniaturized signal conditioning system for biopotential and ion-selective electrode arrays. The system consists of three main components: sensors, interconnections, and signal conditioning chip. The model for this system is based on SPICE. Transmission-line based equivalent circuits are used to represent the sensors, lumped resistance-capacitance circuits describe the interconnections, and a model for the signal conditioning chip is extracted from its layout. A system for measurements of biopotentials and ionic activities can be miniaturized and optimized for cardiovascular applications based on the development of an integrated SPICE system model of its electrochemical, interconnection, and electronic components.

  8. Fast Determination of Distribution-Connected PV Impacts Using a Variable Time-Step Quasi-Static Time-Series Approach: Preprint

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Mather, Barry

    The increasing deployment of distribution-connected photovoltaic (DPV) systems requires utilities to complete complex interconnection studies. Relatively simple interconnection study methods worked well for low penetrations of photovoltaic systems, but more complicated quasi-static time-series (QSTS) analysis is required to make better interconnection decisions as DPV penetration levels increase. Tools and methods must be developed to support this. This paper presents a variable-time-step solver for QSTS analysis that significantly shortens the computational time and effort to complete a detailed analysis of the operation of a distribution circuit with many DPV systems. Specifically, it demonstrates that the proposed variable-time-step solver can reduce themore » required computational time by as much as 84% without introducing any important errors to metrics, such as the highest and lowest voltage occurring on the feeder, number of voltage regulator tap operations, and total amount of losses realized in the distribution circuit during a 1-yr period. Further improvement in computational speed is possible with the introduction of only modest errors in these metrics, such as a 91 percent reduction with less than 5 percent error when predicting voltage regulator operations.« less

  9. Digital communication system

    NASA Technical Reports Server (NTRS)

    Monford, L. G., Jr. (Inventor)

    1974-01-01

    A digital communication system is reported for parallel operation of 16 or more transceiver units with the use of only four interconnecting wires. A remote synchronization circuit produces unit address control words sequentially in data frames of 16 words. Means are provided in each transceiver unit to decode calling signals and to transmit calling and data signals. The transceivers communicate with each other over one data line. The synchronization unit communicates the address control information to the transceiver units over an address line and further provides the timing information over a clock line. A reference voltage level or ground line completes the interconnecting four wire hookup.

  10. Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

    PubMed

    Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Kim, In Gyoo; Oh, Jin Hyuk; Kim, Sun Ae; Park, Jaegyu; Kim, Sanggi

    2015-06-10

    When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

  11. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Blansett, Ethan L.; Schroeppel, Richard Crabtree; Tang, Jason D.

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in themore » photonic domain to achieve the requisite encryption rates. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines two classes of all optical logic (SEED, gain competition) and how each discrete logic element can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of the SEED and gain competition devices in an optical circuit were modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model of the SEED or gain competition device takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an encrypting/scrambling algorithm based on a study of candidate encryption algorithms. We found that a low gate count, cascadable encryption algorithm is most feasible given device and processing constraints. The modeling and simulation of optical designs using these components is proceeding in parallel with efforts to perfect the physical devices and their interconnect. We have applied these techniques to the development of a 'toy' algorithm that may pave the way for more robust optical algorithms. These design/modeling/simulation techniques are now ready to be applied to larger optical designs in advance of our ability to implement such systems in hardware.« less

  12. Biologically based neural circuit modelling for the study of fear learning and extinction

    NASA Astrophysics Data System (ADS)

    Nair, Satish S.; Paré, Denis; Vicentic, Aleksandra

    2016-11-01

    The neuronal systems that promote protective defensive behaviours have been studied extensively using Pavlovian conditioning. In this paradigm, an initially neutral-conditioned stimulus is paired with an aversive unconditioned stimulus leading the subjects to display behavioural signs of fear. Decades of research into the neural bases of this simple behavioural paradigm uncovered that the amygdala, a complex structure comprised of several interconnected nuclei, is an essential part of the neural circuits required for the acquisition, consolidation and expression of fear memory. However, emerging evidence from the confluence of electrophysiological, tract tracing, imaging, molecular, optogenetic and chemogenetic methodologies, reveals that fear learning is mediated by multiple connections between several amygdala nuclei and their distributed targets, dynamical changes in plasticity in local circuit elements as well as neuromodulatory mechanisms that promote synaptic plasticity. To uncover these complex relations and analyse multi-modal data sets acquired from these studies, we argue that biologically realistic computational modelling, in conjunction with experiments, offers an opportunity to advance our understanding of the neural circuit mechanisms of fear learning and to address how their dysfunction may lead to maladaptive fear responses in mental disorders.

  13. On-chip WDM mode-division multiplexing interconnection with optional demodulation function.

    PubMed

    Ye, Mengyuan; Yu, Yu; Chen, Guanyu; Luo, Yuchan; Zhang, Xinliang

    2015-12-14

    We propose and fabricate a wavelength-division-multiplexing (WDM) compatible and multi-functional mode-division-multiplexing (MDM) integrated circuit, which can perform the mode conversion and multiplexing for the incoming multipath WDM signals, avoiding the wavelength conflict. An phase-to-intensity demodulation function can be optionally applied within the circuit while performing the mode multiplexing. For demonstration, 4 × 10 Gb/s non-return-to-zero differential phase shift keying (NRZ-DPSK) signals are successfully processed, with open and clear eye diagrams. Measured bit error ratio (BER) results show less than 1 dB receive sensitivity variation for three modes and four wavelengths with demodulation. In the case without demodulation, the average power penalties at 4 wavelengths are -1.5, -3 and -3.5 dB for TE₀-TE₀, TE₀-TE₁ and TE₀-TE₂ mode conversions, respectively. The proposed flexible scheme can be used at the interface of long-haul and on-chip communication systems.

  14. 14 CFR 25.1717 - Circuit protective devices: EWIS.

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... AIRCRAFT AIRWORTHINESS STANDARDS: TRANSPORT CATEGORY AIRPLANES Electrical Wiring Interconnection Systems (EWIS) § 25.1717 Circuit protective devices: EWIS. Electrical wires and cables must be designed and...

  15. Recent patents on Cu/low-k dielectrics interconnects in integrated circuits.

    PubMed

    Jiang, Qing; Zhu, Yong F; Zhao, Ming

    2007-01-01

    In past decades, the development of microelectronics has moved along with constant speed of scaling to maximize transistor density as driven by the need for electrical and functional performance. For further development, the propagation velocity of electromagnetic waves becomes increasingly important due to their unyielding constraints on interconnect delay. To minimize it, it was forced to the introduction of the Cu/low-k dielectric interconnects to very large scale integrated circuits (VLSI) where k denotes the dielectric constant. In addition, reliable barrier structures, which are the thinnest part among the device parts to maximize space availability for the actual Cu IWs, are required to prevent penetration of different materials. In light of the above statements, this review will focus recent patents and some studies on Cu interconnects including Cu interconnect wires, low-k dielectrics and related barrier materials as well manufacturing techniques in VLSI, which are one of the most essential concerns in microelectronic industry and decides the further development of VLSI. In addition, possible future development in this field is considered.

  16. Novel Vertical Interconnects With 180 Degree Phase Shift for Amplifiers, Filters, and Integrated Antennas

    NASA Technical Reports Server (NTRS)

    Goverdhanam, Kavita; Simons, Rainee N.; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

    2001-01-01

    In this paper, novel low loss, wide-band coplanar stripline technology for RF/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semiconductor devices and microelectromechanical systems (MEMS).

  17. Eddy current measurement of the thickness of top Cu film of the multilayer interconnects in the integrated circuit (IC) manufacturing process

    NASA Astrophysics Data System (ADS)

    Qu, Zilian; Meng, Yonggang; Zhao, Qian

    2015-03-01

    This paper proposes a new eddy current method, named equivalent unit method (EUM), for the thickness measurement of the top copper film of multilayer interconnects in the chemical mechanical polishing (CMP) process, which is an important step in the integrated circuit (IC) manufacturing. The influence of the underneath circuit layers on the eddy current is modeled and treated as an equivalent film thickness. By subtracting this equivalent film component, the accuracy of the thickness measurement of the top copper layer with an eddy current sensor is improved and the absolute error is 3 nm for sampler measurement.

  18. Superconductor Digital Electronics: -- Current Status, Future Prospects

    NASA Astrophysics Data System (ADS)

    Mukhanov, Oleg

    2011-03-01

    Two major applications of superconductor electronics: communications and supercomputing will be presented. These areas hold a significant promise of a large impact on electronics state-of-the-art for the defense and commercial markets stemming from the fundamental advantages of superconductivity: simultaneous high speed and low power, lossless interconnect, natural quantization, and high sensitivity. The availability of relatively small cryocoolers lowered the foremost market barrier for cryogenically-cooled superconductor electronic systems. These fundamental advantages enabled a novel Digital-RF architecture - a disruptive technological approach changing wireless communications, radar, and surveillance system architectures dramatically. Practical results were achieved for Digital-RF systems in which wide-band, multi-band radio frequency signals are directly digitized and digital domain is expanded throughout the entire system. Digital-RF systems combine digital and mixed signal integrated circuits based on Rapid Single Flux Quantum (RSFQ) technology, superconductor analog filter circuits, and semiconductor post-processing circuits. The demonstrated cryocooled Digital-RF systems are the world's first and fastest directly digitizing receivers operating with live satellite signals, enabling multi-net data links, and performing signal acquisition from HF to L-band with 30 GHz clock frequencies. In supercomputing, superconductivity leads to the highest energy efficiencies per operation. Superconductor technology based on manipulation and ballistic transfer of magnetic flux quanta provides a superior low-power alternative to CMOS and other charge-transfer based device technologies. The fundamental energy consumption in SFQ circuits defined by flux quanta energy 2 x 10-19 J. Recently, a novel energy-efficient zero-static-power SFQ technology, eSFQ/ERSFQ was invented, which retains all advantages of standard RSFQ circuits: high-speed, dc power, internal memory. The voltage bias regulation, determined by SFQ clock, enables the zero-power at zero-activity regimes, indispensable for sensor and quantum bit readout.

  19. Generating multi-double-scroll attractors via nonautonomous approach.

    PubMed

    Hong, Qinghui; Xie, Qingguo; Shen, Yi; Wang, Xiaoping

    2016-08-01

    It is a common phenomenon that multi-scroll attractors are realized by introducing the various nonlinear functions with multiple breakpoints in double scroll chaotic systems. Differently, we present a nonautonomous approach for generating multi-double-scroll attractors (MDSA) without changing the original nonlinear functions. By using the multi-level-logic pulse excitation technique in double scroll chaotic systems, MDSA can be generated. A Chua's circuit, a Jerk circuit, and a modified Lorenz system are given as designed example and the Matlab simulation results are presented. Furthermore, the corresponding realization circuits are designed. The Pspice results are in agreement with numerical simulation results, which verify the availability and feasibility of this method.

  20. Optical interconnect for large-scale systems

    NASA Astrophysics Data System (ADS)

    Dress, William

    2013-02-01

    This paper presents a switchless, optical interconnect module that serves as a node in a network of identical distribution modules for large-scale systems. Thousands to millions of hosts or endpoints may be interconnected by a network of such modules, avoiding the need for multi-level switches. Several common network topologies are reviewed and their scaling properties assessed. The concept of message-flow routing is discussed in conjunction with the unique properties enabled by the optical distribution module where it is shown how top-down software control (global routing tables, spanning-tree algorithms) may be avoided.

  1. System and Method for Multi-Wavelength Optical Signal Detection

    NASA Technical Reports Server (NTRS)

    McGlone, Thomas D. (Inventor)

    2017-01-01

    The system and method for multi-wavelength optical signal detection enables the detection of optical signal levels significantly below those processed at the discrete circuit level by the use of mixed-signal processing methods implemented with integrated circuit technologies. The present invention is configured to detect and process small signals, which enables the reduction of the optical power required to stimulate detection networks, and lowers the required laser power to make specific measurements. The present invention provides an adaptation of active pixel networks combined with mixed-signal processing methods to provide an integer representation of the received signal as an output. The present invention also provides multi-wavelength laser detection circuits for use in various systems, such as a differential absorption light detection and ranging system.

  2. Interconnecting Multidiscilinary Data Infrastructures: From Federation to Brokering Framework

    NASA Astrophysics Data System (ADS)

    Nativi, S.

    2014-12-01

    Standardization and federation activities have been played an essential role to push interoperability at the disciplinary and cross-disciplinary level. However, they demonstrated not to be sufficient to resolve important interoperability challenges, including: disciplinary heterogeneity, cross-organizations diversities, cultural differences. Significant international initiatives like GEOSS, IODE, and CEOS demonstrated that a federation system dealing with global and multi-disciplinary domain turns out to be rater complex, raising more the already high entry level barriers for both Providers and Users. In particular, GEOSS demonstrated that standardization and federation actions must be accompanied and complemented by a brokering approach. Brokering architecture and its implementing technologies are able to implement an effective interoperability level among multi-disciplinary systems, lowering the entry level barriers for both data providers and users. This presentation will discuss the brokering philosophy as a complementary approach for standardization and federation to interconnect existing and heterogeneous infrastructures and systems. The GEOSS experience will be analyzed, specially.

  3. Elastic all-optical multi-hop interconnection in data centers with adaptive spectrum allocation

    NASA Astrophysics Data System (ADS)

    Hong, Yuanyuan; Hong, Xuezhi; Chen, Jiajia; He, Sailing

    2017-01-01

    In this paper, a novel flex-grid all-optical interconnect scheme that supports transparent multi-hop connections in data centers is proposed. An inter-rack all-optical multi-hop connection is realized with an optical loop employed at flex-grid wavelength selective switches (WSSs) in an intermediate rack rather than by relaying through optical-electric-optical (O-E-O) conversions. Compared with the conventional O-E-O based approach, the proposed all-optical scheme is able to off-load the traffic at intermediate racks, leading to a reduction of the power consumption and cost. The transmission performance of the proposed flex-grid multi-hop all-optical interconnect scheme with various modulation formats, including both coherently detected and directly detected approaches, are investigated by Monte-Carlo simulations. To enhance the spectrum efficiency (SE), number-of-hop adaptive bandwidth allocation is introduced. Numerical results show that the SE can be improved by up to 33.3% at 40 Gbps, and by up to 25% at 100 Gbps. The impact of parameters, such as targeted bit error rate (BER) level and insertion loss of components, on the transmission performance of the proposed approach are also explored. The results show that the maximum SE improvement of the adaptive approach over the non-adaptive one is enhanced with the decrease of the targeted BER levels and the component insertion loss.

  4. High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

    NASA Technical Reports Server (NTRS)

    Shalkhauser, K. A.; Li, K.; Shih, Y. C.

    1992-01-01

    Packaging schemes were developed that provide low-loss, hermetic enclosure for advanced monolithic microwave and millimeter-wave integrated circuits (MMICs). The package designs are based on a fused quartz substrate material that offers improved radio frequency (RF) performance through 44 gigahertz (GHz). The small size and weight of the packages make them appropriate for a variety of applications, including phased array antenna systems. Packages were designed in two forms; one for housing a single MMIC chip, the second in the form of a multi-chip phased array module. The single chip array module was developed in three separate sizes, for chips of different geometry and frequency requirements. The phased array module was developed to address packaging directly for antenna applications, and includes transmission line and interconnect structures to support multi-element operation. All packages are fabricated using fused quartz substrate materials. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices. The package and test fixture designs were both developed in a generic sense, optimizing performance for a wide range of possible applications and devices.

  5. Packaging Technologies for High Temperature Electronics and Sensors

    NASA Technical Reports Server (NTRS)

    Chen, Liang-Yu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

    2013-01-01

    This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500 C silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chip-level packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550 C. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500 C for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500 C are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

  6. 47 CFR 36.124 - Tandem switching equipment-Category 2.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... circuits with each other or with local or tandem telephone central office trunks, intertoll dial selector equipment, or intertoll trunk equipment in No. 5 type electronic offices. Equipment, including switchboards... interconnection of: Toll center to toll center circuits; toll center to tributary circuits; tributary to tributary...

  7. 47 CFR 36.124 - Tandem switching equipment-Category 2.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... circuits with each other or with local or tandem telephone central office trunks, intertoll dial selector equipment, or intertoll trunk equipment in No. 5 type electronic offices. Equipment, including switchboards... interconnection of: Toll center to toll center circuits; toll center to tributary circuits; tributary to tributary...

  8. 47 CFR 36.124 - Tandem switching equipment-Category 2.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... circuits with each other or with local or tandem telephone central office trunks, intertoll dial selector equipment, or intertoll trunk equipment in No. 5 type electronic offices. Equipment, including switchboards... interconnection of: Toll center to toll center circuits; toll center to tributary circuits; tributary to tributary...

  9. 47 CFR 36.124 - Tandem switching equipment-Category 2.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... circuits with each other or with local or tandem telephone central office trunks, intertoll dial selector equipment, or intertoll trunk equipment in No. 5 type electronic offices. Equipment, including switchboards... interconnection of: Toll center to toll center circuits; toll center to tributary circuits; tributary to tributary...

  10. 47 CFR 36.124 - Tandem switching equipment-Category 2.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... circuits with each other or with local or tandem telephone central office trunks, intertoll dial selector equipment, or intertoll trunk equipment in No. 5 type electronic offices. Equipment, including switchboards... interconnection of: Toll center to toll center circuits; toll center to tributary circuits; tributary to tributary...

  11. Modular chassis simplifies packaging and interconnecting of circuit boards

    NASA Technical Reports Server (NTRS)

    Arens, W. E.; Boline, K. G.

    1964-01-01

    A system of modular chassis structures has simplified the design for mounting a number of printed circuit boards. This design is structurally adaptable to computer and industrial control system applications.

  12. Generating multi-double-scroll attractors via nonautonomous approach

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hong, Qinghui; Xie, Qingguo, E-mail: qgxie@mail.hust.edu.cn; Shen, Yi

    It is a common phenomenon that multi-scroll attractors are realized by introducing the various nonlinear functions with multiple breakpoints in double scroll chaotic systems. Differently, we present a nonautonomous approach for generating multi-double-scroll attractors (MDSA) without changing the original nonlinear functions. By using the multi-level-logic pulse excitation technique in double scroll chaotic systems, MDSA can be generated. A Chua's circuit, a Jerk circuit, and a modified Lorenz system are given as designed example and the Matlab simulation results are presented. Furthermore, the corresponding realization circuits are designed. The Pspice results are in agreement with numerical simulation results, which verify themore » availability and feasibility of this method.« less

  13. Method for reworkable packaging of high speed, low electrical parasitic power electronics modules through gate drive integration

    DOEpatents

    Passmore, Brandon; Cole, Zach; Whitaker, Bret; Barkley, Adam; McNutt, Ty; Lostetter, Alexander

    2016-08-02

    A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

  14. Maze solving automatons for self-healing of open interconnects: Modular add-on for circuit boards

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Nair, Aswathi; Raghunandan, Karthik; Yaswant, Vaddi

    We present the circuit board integration of a self-healing mechanism to repair open faults. The electric field driven mechanism physically restores fractured interconnects in electronic circuits and has the ability to solve mazes. The repair is performed by conductive particles dispersed in an insulating fluid. We demonstrate the integration of the healing module onto printed circuit boards and the ability of maze solving. We model and perform experiments on the influence of the geometry of conductive particles as well as the terminal impedances of the route on the healing efficiency. The typical heal rate is 10 μm/s with healed route havingmore » mean resistance of 8 kΩ across a 200 micron gap and depending on the materials and concentrations used.« less

  15. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tang, Jason D.; Schroeppel, Richard Crabtree; Robertson, Perry J.

    With the build-out of large transport networks utilizing optical technologies, more and more capacity is being made available. Innovations in Dense Wave Division Multiplexing (DWDM) and the elimination of optical-electrical-optical conversions have brought on advances in communication speeds as we move into 10 Gigabit Ethernet and above. Of course, there is a need to encrypt data on these optical links as the data traverses public and private network backbones. Unfortunately, as the communications infrastructure becomes increasingly optical, advances in encryption (done electronically) have failed to keep up. This project examines the use of optical logic for implementing encryption in themore » photonic domain to achieve the requisite encryption rates. This paper documents the innovations and advances of work first detailed in 'Photonic Encryption using All Optical Logic,' [1]. A discussion of underlying concepts can be found in SAND2003-4474. In order to realize photonic encryption designs, technology developed for electrical logic circuits must be translated to the photonic regime. This paper examines S-SEED devices and how discrete logic elements can be interconnected and cascaded to form an optical circuit. Because there is no known software that can model these devices at a circuit level, the functionality of S-SEED devices in an optical circuit was modeled in PSpice. PSpice allows modeling of the macro characteristics of the devices in context of a logic element as opposed to device level computational modeling. By representing light intensity as voltage, 'black box' models are generated that accurately represent the intensity response and logic levels in both technologies. By modeling the behavior at the systems level, one can incorporate systems design tools and a simulation environment to aid in the overall functional design. Each black box model takes certain parameters (reflectance, intensity, input response), and models the optical ripple and time delay characteristics. These 'black box' models are interconnected and cascaded in an encrypting/scrambling algorithm based on a study of candidate encryption algorithms. Demonstration circuits show how these logic elements can be used to form NAND, NOR, and XOR functions. This paper also presents functional analysis of a serial, low gate count demonstration algorithm suitable for scrambling/encryption using S-SEED devices.« less

  16. Shock absorbing mount for electrical components

    NASA Technical Reports Server (NTRS)

    Dillon, R. F., Jr.; Mayne, R. C. (Inventor)

    1975-01-01

    A shock mount for installing electrical components on circuit boards is described. The shock absorber is made of viscoelastic material which interconnects the electrical components. With this system, shocks imposed on one component of the circuit are not transmitted to other components. A diagram of a typical circuit is provided.

  17. Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects

    PubMed Central

    Kim, Gyungock; Park, Hyundai; Joo, Jiho; Jang, Ki-Seok; Kwack, Myung-Joon; Kim, Sanghoon; Gyoo Kim, In; Hyuk Oh, Jin; Ae Kim, Sun; Park, Jaegyu; Kim, Sanggi

    2015-01-01

    When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications. PMID:26061463

  18. Packaging Technologies for High Temperature Electronics and Sensors

    NASA Technical Reports Server (NTRS)

    Chen, Liangyu; Hunter, Gary W.; Neudeck, Philip G.; Beheim, Glenn M.; Spry, David J.; Meredith, Roger D.

    2013-01-01

    This paper reviews ceramic substrates and thick-film metallization based packaging technologies in development for 500degC silicon carbide (SiC) electronics and sensors. Prototype high temperature ceramic chip-level packages and printed circuit boards (PCBs) based on ceramic substrates of aluminum oxide (Al2O3) and aluminum nitride (AlN) have been designed and fabricated. These ceramic substrate-based chiplevel packages with gold (Au) thick-film metallization have been electrically characterized at temperatures up to 550degC. A 96% alumina based edge connector for a PCB level subsystem interconnection has also been demonstrated recently. The 96% alumina packaging system composed of chip-level packages and PCBs has been tested with high temperature SiC devices at 500degC for over 10,000 hours. In addition to tests in a laboratory environment, a SiC JFET with a packaging system composed of a 96% alumina chip-level package and an alumina printed circuit board mounted on a data acquisition circuit board was launched as a part of the MISSE-7 suite to the International Space Station via a Shuttle mission. This packaged SiC transistor was successfully tested in orbit for eighteen months. A spark-plug type sensor package designed for high temperature SiC capacitive pressure sensors was developed. This sensor package combines the high temperature interconnection system with a commercial high temperature high pressure stainless steel seal gland (electrical feed-through). Test results of a packaged high temperature capacitive pressure sensor at 500degC are also discussed. In addition to the pressure sensor package, efforts for packaging high temperature SiC diode-based gas chemical sensors are in process.

  19. A Comprehensive Surface Mount Technology Solution for Integrated Circuits onto Flexible Screen Printed Electrical Interconnects

    DTIC Science & Technology

    2014-05-19

    their acceptable thermal stability, Polyimides have established as a conventional substrate material for flexible interconnects, which can be...of the silver flake ink for the screen-printed interconnects, the assembled unit fulfills biocompatibility requirements in a limited manner ([29...30]). Even though biocompatibility of substrate [31] is fulfilled, toxicity of the insulating mask [32] and encapsulation need to be considered

  20. Multi-variants synthesis of Petri nets for FPGA devices

    NASA Astrophysics Data System (ADS)

    Bukowiec, Arkadiusz; Doligalski, Michał

    2015-09-01

    There is presented new method of synthesis of application specific logic controllers for FPGA devices. The specification of control algorithm is made with use of control interpreted Petri net (PT type). It allows specifying parallel processes in easy way. The Petri net is decomposed into state-machine type subnets. In this case, each subnet represents one parallel process. For this purpose there are applied algorithms of coloring of Petri nets. There are presented two approaches of such decomposition: with doublers of macroplaces or with one global wait place. Next, subnets are implemented into two-level logic circuit of the controller. The levels of logic circuit are obtained as a result of its architectural decomposition. The first level combinational circuit is responsible for generation of next places and second level decoder is responsible for generation output symbols. There are worked out two variants of such circuits: with one shared operational memory or with many flexible distributed memories as a decoder. Variants of Petri net decomposition and structures of logic circuits can be combined together without any restrictions. It leads to existence of four variants of multi-variants synthesis.

  1. Canonical multi-valued input Reed-Muller trees and forms

    NASA Technical Reports Server (NTRS)

    Perkowski, M. A.; Johnson, P. D.

    1991-01-01

    There is recently an increased interest in logic synthesis using EXOR gates. The paper introduces the fundamental concept of Orthogonal Expansion, which generalizes the ring form of the Shannon expansion to the logic with multiple-valued (mv) inputs. Based on this concept we are able to define a family of canonical tree circuits. Such circuits can be considered for binary and multiple-valued input cases. They can be multi-level (trees and DAG's) or flattened to two-level AND-EXOR circuits. Input decoders similar to those used in Sum of Products (SOP) PLA's are used in realizations of multiple-valued input functions. In the case of the binary logic the family of flattened AND-EXOR circuits includes several forms discussed by Davio and Green. For the case of the logic with multiple-valued inputs, the family of the flattened mv AND-EXOR circuits includes three expansions known from literature and two new expansions.

  2. Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

    PubMed

    Tan, Michael Loong Peng; Lentaris, Georgios; Amaratunga Aj, Gehan

    2012-08-19

    The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

  3. Advanced On-Board Processor (AOP). [for future spacecraft applications

    NASA Technical Reports Server (NTRS)

    1973-01-01

    Advanced On-board Processor the (AOP) uses large scale integration throughout and is the most advanced space qualified computer of its class in existence today. It was designed to satisfy most spacecraft requirements which are anticipated over the next several years. The AOP design utilizes custom metallized multigate arrays (CMMA) which have been designed specifically for this computer. This approach provides the most efficient use of circuits, reduces volume, weight, assembly costs and provides for a significant increase in reliability by the significant reduction in conventional circuit interconnections. The required 69 CMMA packages are assembled on a single multilayer printed circuit board which together with associated connectors constitutes the complete AOP. This approach also reduces conventional interconnections thus further reducing weight, volume and assembly costs.

  4. Si photonics technology for future optical interconnection

    NASA Astrophysics Data System (ADS)

    Zheng, Xuezhe; Krishnamoorthy, Ashok V.

    2011-12-01

    Scaling of computing systems require ultra-efficient interconnects with large bandwidth density. Silicon photonics offers a disruptive solution with advantages in reach, energy efficiency and bandwidth density. We review our progress in developing building blocks for ultra-efficient WDM silicon photonic links. Employing microsolder based hybrid integration with low parasitics and high density, we optimize photonic devices on SOI platforms and VLSI circuits on more advanced bulk CMOS technology nodes independently. Progressively, we successfully demonstrated single channel hybrid silicon photonic transceivers at 5 Gbps and 10 Gbps, and 80 Gbps arrayed WDM silicon photonic transceiver using reverse biased depletion ring modulators and Ge waveguide photo detectors. Record-high energy efficiency of less than 100fJ/bit and 385 fJ/bit were achieved for the hybrid integrated transmitter and receiver, respectively. Waveguide grating based optical proximity couplers were developed with low loss and large optical bandwidth to enable multi-layer intra/inter-chip optical interconnects. Thermal engineering of WDM devices by selective substrate removal, together with WDM link using synthetic wavelength comb, we significantly improved the device tuning efficiency and reduced the tuning range. Using these innovative techniques, two orders of magnitude tuning power reduction was achieved. And tuning cost of only a few 10s of fJ/bit is expected for high data rate WDM silicon photonic links.

  5. Silicon Carbide Integrated Circuit Chip

    NASA Image and Video Library

    2015-02-17

    A multilevel interconnect silicon carbide integrated circuit chip with co-fired ceramic package and circuit board recently developed at the NASA GRC Smart Sensors and Electronics Systems Branch for high temperature applications. High temperature silicon carbide electronics and compatible packaging technologies are elements of instrumentation for aerospace engine control and long term inner-solar planet explorations.

  6. Practical proof of CP element based design for 14nm node and beyond

    NASA Astrophysics Data System (ADS)

    Maruyama, Takashi; Takita, Hiroshi; Ikeno, Rimon; Osawa, Morimi; Kojima, Yoshinori; Sugatani, Shinji; Hoshino, Hiromi; Hino, Toshio; Ito, Masaru; Iizuka, Tetsuya; Komatsu, Satoshi; Ikeda, Makoto; Asada, Kunihiro

    2013-03-01

    To realize HVM (High Volume Manufacturing) with CP (Character Projection) based EBDW, the shot count reduction is the essential key. All device circuits should be composed with predefined character parts and we call this methodology "CP element based design". In our previous work, we presented following three concepts [2]. 1) Memory: We reported the prospects of affordability for the CP-stencil resource. 2) Logic cell: We adopted a multi-cell clustering approach in the physical synthesis. 3) Random interconnect: We proposed an ultra-regular layout scheme using fixed size wiring tiles containing repeated tracks and cutting points at the tile edges. In this paper, we will report the experimental proofs in these methodologies. In full chip layout, CP stencil resource management is critical key. From the MCC-POC (Proof of Concept) result [1], we assumed total available CP stencil resource as 9000um2. We should manage to layout all circuit macros within this restriction. Especially the issues in assignment of CP-stencil resource for the memory macros are the most important as they consume considerable degree of resource because of the various line-ups such as 1RW-, 2RW-SRAMs, Resister Files and ROM which require several varieties of large size peripheral circuits. Furthermore the memory macros typically take large area of more than 40% of die area in the forefront logic LSI products so that the shot count increase impact is serious. To realize CP-stencil resource saving we had constructed automatic CP analyzing system. We developed two types of extraction mode of simple division by block and layout repeatability recognition. By properly controlling these models based upon each peripheral circuit characteristics, we could minimize the consumption of CP stencil resources. The estimation for 14nm technology node had been performed based on the analysis of practical memory compiler. The required resource for memory macro is proved to be affordable value which is 60% of full CP stencil resource and wafer level converted shot count is proved to be the level which meets 100WPH throughput. In logic cell design, circuit performance verification result after the cell clustering has been estimated. The cell clustering by the acknowledgment of physical distance proved to owe large penalty mainly in the wiring length. To reduce this design penalty, we proposed CP cell clustering by the acknowledgment of logical distance. For shot-count reduction of random interconnect area design, we proposed a more structural routing architecture which consists of the track exchange and the via position arrangement. Putting these design approaches together, we can design CP stencils to hit the target throughput within the area constraint. From the analysis for other macros such as analog, I/O, and DUMMY, it has proved that we don't need special CP design approach than legacy pattern matching CP extraction. From all these experimental results we get good prospects to the reality of full CP element based layout.

  7. Lightweight concentrator module with 30 percent AM0 efficient GaAs/GaSb tandem cells

    NASA Technical Reports Server (NTRS)

    Avery, J. E.; Fraas, L. M.; Sundaram, V. S.; Mansoori, N.; Yerkes, J. W.; Brinker, D. J.; Curtis, H. B.; O'Neill, M. J.

    1990-01-01

    A concept is presented for an aerospace concentrator module with lightweight domed lenses and 30 percent AM0 efficient GaAs/GaSb tandem solar cell circuits. The performance of transparent GaAs cells is reviewed. NASA's high-altitude jet flight calibration data for recent GaSb cells assembled with bulk GaAs filters are reported, along with subsequent Boeing and NASA measurements of GaSb I-V performance at various light levels and temperatures. The expected performance of a basic two-terminal tandem concentrator circuit with three-to-one voltage matching is discussed. All of the necessary components being developed to assemble complete flight test coupons are shown. Straightforward interconnect and assembly techniques yield voltage matched circuits with near-optimum performance over a wide temperature range.

  8. The Development of an IMU Integrated Clothes for Postural Monitoring Using Conductive Yarn and Interconnecting Technology.

    PubMed

    Kang, Sung-Won; Choi, Hyeob; Park, Hyung-Il; Choi, Byoung-Gun; Im, Hyobin; Shin, Dongjun; Jung, Young-Giu; Lee, Jun-Young; Park, Hong-Won; Park, Sukyung; Roh, Jung-Sim

    2017-11-07

    Spinal disease is a common yet important condition that occurs because of inappropriate posture. Prevention could be achieved by continuous posture monitoring, but most measurement systems cannot be used in daily life due to factors such as burdensome wires and large sensing modules. To improve upon these weaknesses, we developed comfortable "smart wear" for posture measurement using conductive yarn for circuit patterning and a flexible printed circuit board (FPCB) for interconnections. The conductive yarn was made by twisting polyester yarn and metal filaments, and the resistance per unit length was about 0.05 Ω/cm. An embroidered circuit was made using the conductive yarn, which showed increased yield strength and uniform electrical resistance per unit length. Circuit networks of sensors and FPCBs for interconnection were integrated into clothes using a computer numerical control (CNC) embroidery process. The system was calibrated and verified by comparing the values measured by the smart wear with those measured by a motion capture camera system. Six subjects performed fixed movements and free computer work, and, with this system, we were able to measure the anterior/posterior direction tilt angle with an error of less than 4°. The smart wear does not have excessive wires, and its structure will be optimized for better posture estimation in a later study.

  9. Merging parallel optics packaging and surface mount technologies

    NASA Astrophysics Data System (ADS)

    Kopp, Christophe; Volpert, Marion; Routin, Julien; Bernabé, Stéphane; Rossat, Cyrille; Tournaire, Myriam; Hamelin, Régis

    2008-02-01

    Optical links are well known to present significant advantages over electrical links for very high-speed data rate at 10Gpbs and above per channel. However, the transition towards optical interconnects solutions for short and very short reach applications requires the development of innovative packaging solutions that would deal with very high volume production capability and very low cost per unit. Moreover, the optoelectronic transceiver components must be able to move from the edge to anywhere on the printed circuit board, for instance close to integrated circuits with high speed IO. In this paper, we present an original packaging design to manufacture parallel optic transceivers that are surface mount devices. The package combines highly integrated Multi-Chip-Module on glass and usual IC ceramics packaging. The use of ceramic and the development of sealing technologies achieve hermetic requirements. Moreover, thanks to a chip scale package approach the final device exhibits a much minimized footprint. One of the main advantages of the package is its flexibility to be soldered or plugged anywhere on the printed circuit board as any other electronic device. As a demonstrator we present a 2 by 4 10Gbps transceiver operating at 850nm.

  10. 24 CFR 3285.802 - Structural interconnection of multi-section homes.

    Code of Federal Regulations, 2011 CFR

    2011-04-01

    ...-section homes. 3285.802 Section 3285.802 Housing and Urban Development Regulations Relating to Housing and..., DEPARTMENT OF HOUSING AND URBAN DEVELOPMENT MODEL MANUFACTURED HOME INSTALLATION STANDARDS Exterior and Interior Close-Up § 3285.802 Structural interconnection of multi-section homes. (a) For multi-section homes...

  11. 24 CFR 3285.802 - Structural interconnection of multi-section homes.

    Code of Federal Regulations, 2010 CFR

    2010-04-01

    ...-section homes. 3285.802 Section 3285.802 Housing and Urban Development Regulations Relating to Housing and..., DEPARTMENT OF HOUSING AND URBAN DEVELOPMENT MODEL MANUFACTURED HOME INSTALLATION STANDARDS Exterior and Interior Close-Up § 3285.802 Structural interconnection of multi-section homes. (a) For multi-section homes...

  12. 24 CFR 3285.802 - Structural interconnection of multi-section homes.

    Code of Federal Regulations, 2013 CFR

    2013-04-01

    ...-section homes. 3285.802 Section 3285.802 Housing and Urban Development Regulations Relating to Housing and..., DEPARTMENT OF HOUSING AND URBAN DEVELOPMENT MODEL MANUFACTURED HOME INSTALLATION STANDARDS Exterior and Interior Close-Up § 3285.802 Structural interconnection of multi-section homes. (a) For multi-section homes...

  13. The use of hybrid integrated circuit techniques in biotelemetry applications

    NASA Technical Reports Server (NTRS)

    Fryer, T. B.

    1977-01-01

    A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.

  14. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    NASA Astrophysics Data System (ADS)

    Yin, Lan; Bozler, Carl; Harburg, Daniel V.; Omenetto, Fiorenzo; Rogers, John A.

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  15. Design guidelines for advanced LSI microcircuit packaging using thick film multilayer technology

    NASA Technical Reports Server (NTRS)

    Peckinpaugh, C. J.

    1974-01-01

    Ceramic multilayer circuitry results from the sequential build-up of two or more layers of pre-determined conductive interconnections separated by dielectric layers and fired at an elevated temperature to form a solidly fused structure. The resultant ceramic interconnect matrix is used as a base to mount active and passive devices and provide the necessary electrical interconnection to accomplish the desired electrical circuit. Many methods are known for developing multilevel conductor mechanisms such as multilayer printed circuits, welded wire matrices, flexible copper tape conductors, and thin and thick-film ceramic multilayers. Each method can be considered as a specialized field with each possessing its own particular set of benefits and problems. This design guide restricts itself to the art of design, fabrication and assembly of ceramic multilayer circuitry and the reliability of the end product.

  16. System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

    NASA Technical Reports Server (NTRS)

    Windyka, John A.; Zablocki, Ed G.

    1997-01-01

    This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

  17. 75 FR 60863 - Safety Advisory 2010-02

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-10-01

    ... equipped, railroads should ensure that the circuit plan shows the actual interconnection and the designed... detection device (or equivalent) is programmed or equipped to provide the appropriate designed pre-emption... circuit and as designed. By conducting comprehensive periodic joint inspections, the railroad and State...

  18. Optoelectronic Integrated Circuits For Neural Networks

    NASA Technical Reports Server (NTRS)

    Psaltis, D.; Katz, J.; Kim, Jae-Hoon; Lin, S. H.; Nouhi, A.

    1990-01-01

    Many threshold devices placed on single substrate. Integrated circuits containing optoelectronic threshold elements developed for use as planar arrays of artificial neurons in research on neural-network computers. Mounted with volume holograms recorded in photorefractive crystals serving as dense arrays of variable interconnections between neurons.

  19. First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu

    2016-01-01

    A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

  20. 3D-ICs created using oblique processing

    NASA Astrophysics Data System (ADS)

    Burckel, D. Bruce

    2016-03-01

    This paper demonstrates that another class of three-dimensional integrated circuits (3D-ICs) exists, distinct from through silicon via centric and monolithic 3D-ICs. Furthermore, it is possible to create devices that are 3D at the device level (i.e. with active channels oriented in each of the three coordinate axes), by performing standard CMOS fabrication operations at an angle with respect to the wafer surface into high aspect ratio silicon substrates using membrane projection lithography (MPL). MPL requires only minimal fixturing changes to standard CMOS equipment, and no change to current state-of-the-art lithography. Eliminating the constraint of 2D planar device architecture enables a wide range of new interconnect topologies which could help reduce interconnect resistance/capacitance, and potentially improve performance.

  1. The 30/20 GHz mixed user architecture development study: Executive summary

    NASA Technical Reports Server (NTRS)

    1979-01-01

    The baseline 30/30 GHz satellite communication system, designed for cost-effective communications in the years 1990 to 2000, incorporates on-board satellite demodulation and routing of individual 64 kbps digital voice-grade circuits. This level of routing flexibility is necessary to provide efficient communications to the large number of direct-to-user terminals (DTU) projected. The circuit interfacing hardware is distributed among all the DTU and master control stations. The switching circuitry which provides full interconnectivity between 30 to 45 thousand circuits is in the satellite. The DTU terminal cost, perhaps the largest element in the system cost, represents the largest economic value element of the system because it avoids using terrestrial signal distribution and routing and the charges associated with these functions. Satellite baseline design and power requirements for the system are examined.

  2. George E. Pake Prize: A Few Challenges in the Evolution of Semiconductor Device/Manufacturing Technology

    NASA Astrophysics Data System (ADS)

    Doering, Robert

    In the early 1980s, the semiconductor industry faced the related challenges of ``scaling through the one-micron barrier'' and converting single-level-metal NMOS integrated circuits to multi-level-metal CMOS. Multiple advances in lithography technology and device materials/process integration led the way toward the deep-sub-micron transistors and interconnects that characterize today's electronic chips. In the 1990s, CMOS scaling advanced at an accelerated pace enabled by rapid advances in many aspects of optical lithography. However, the industry also needed to continue the progress in manufacturing on ever-larger silicon wafers to maintain economy-of-scale trends. Simultaneously, the increasing complexity and absolute-precision requirements of manufacturing compounded the necessity for new processes, tools, and control methodologies. This talk presents a personal perspective on some of the approaches that addressed the aforementioned challenges. In particular, early work on integrating silicides, lightly-doped-drain FETs, shallow recessed isolation, and double-level metal will be discussed. In addition, some pioneering efforts in deep-UV lithography and single-wafer processing will be covered. The latter will be mainly based on results from the MMST Program - a 100 M +, 5-year R&D effort, funded by DARPA, the U.S. Air Force, and Texas Instruments, that developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits in 1993. This was principally enabled by the development of: (1) 100% single-wafer processing, including rapid-thermal processing (RTP), and (2) computer-integrated-manufacturing (CIM), including real-time, in-situ process control.

  3. Helium Ion Secondary Electron Mode Microscopy For Interconnect Material Imaging

    NASA Astrophysics Data System (ADS)

    Ogawa, Shinichi; Thompson, William; Stern, Lewis; Scipioni, Larry; Notte, John; Farkas, Lou; Barriss, Louise

    2010-04-01

    The recently developed helium ion microscope (HIM) is now capable of 0.35 nm secondary electron (SE) mode image resolution. When low-k dielectrics or copper interconnects in ultra large scale integrated circuits (ULSI) interconnect structures were imaged in this mode, it was found that unique pattern dimension and fidelity information at sub-nanometer resolution was available for the first time. This paper will discuss the helium ion microscope architecture and the SE imaging techniques that make the HIM observation method of particular value to the low-k dielectric and dual damascene copper interconnect technologies.

  4. Bi-level microelectronic device package with an integral window

    DOEpatents

    Peterson, Kenneth A.; Watson, Robert D.

    2004-01-06

    A package with an integral window for housing a microelectronic device. The integral window is bonded directly to the package without having a separate layer of adhesive material disposed in-between the window and the package. The device can be a semiconductor chip, CCD chip, CMOS chip, VCSEL chip, laser diode, MEMS device, or IMEMS device. The multilayered package can be formed of a LTCC or HTCC cofired ceramic material, with the integral window being simultaneously joined to the package during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded so that the light-sensitive side is optically accessible through the window. The package has at least two levels of circuits for making electrical interconnections to a pair of microelectronic devices. The result is a compact, low-profile package having an integral window that is hermetically sealed to the package prior to mounting and interconnecting the microelectronic device(s).

  5. Lightwave technology in microwave systems

    NASA Astrophysics Data System (ADS)

    Popa, A. E.; Gee, C. M.; Yen, H. W.

    1986-01-01

    Many advanced microwave system concepts such as active aperture phased array antennas use distributed topologies in which lightwave circuits are being proposed to interconnect both the analog and digital modules of the system. Lightwave components designed to implement these interconnects are reviewed and their performance analyzed. The impact of trends in component development are discussed.

  6. Inverter for Interchangeable Use as Current Source Inverter and Voltage Source Inverter for Interconnecting to Grid

    NASA Astrophysics Data System (ADS)

    Teruya, Daisuke; Masukawa, Shigeo; Iida, Shoji

    We propose a novel inverter that can be operated either as a Current Source Inverter (CSI) or as a Voltage Source Inverter (VSI) by changing only the control signals. It is proper to apply it to the interconnecting system with renewal energy, such as photovoltaic cells or wind generation systems, to a grid. This inverter is usually operated as the CSI connected to the grid. Even if the energy source has a lower voltage than the grid, the energy can be supplied to the grid through the proposed inverter. The power factor can be briefly maintained at almost unity. When power supply from the grid is interrupted, the proposed circuit should be operated as the VSI in the stand-alone operation mode. In this way, the circuit can maintain a constant output voltage to the loads. In this paper, the proposed circuit configuration and the control schemes for both the CSI and the VSI are described. Further, the circuit characteristics for both are discussed experimentally.

  7. The Development of an IMU Integrated Clothes for Postural Monitoring Using Conductive Yarn and Interconnecting Technology

    PubMed Central

    Kang, Sung-Won; Park, Hyung-Il; Choi, Byoung-Gun; Shin, Dongjun; Jung, Young-Giu; Lee, Jun-Young; Park, Hong-Won; Park, Sukyung

    2017-01-01

    Spinal disease is a common yet important condition that occurs because of inappropriate posture. Prevention could be achieved by continuous posture monitoring, but most measurement systems cannot be used in daily life due to factors such as burdensome wires and large sensing modules. To improve upon these weaknesses, we developed comfortable “smart wear” for posture measurement using conductive yarn for circuit patterning and a flexible printed circuit board (FPCB) for interconnections. The conductive yarn was made by twisting polyester yarn and metal filaments, and the resistance per unit length was about 0.05 Ω/cm. An embroidered circuit was made using the conductive yarn, which showed increased yield strength and uniform electrical resistance per unit length. Circuit networks of sensors and FPCBs for interconnection were integrated into clothes using a computer numerical control (CNC) embroidery process. The system was calibrated and verified by comparing the values measured by the smart wear with those measured by a motion capture camera system. Six subjects performed fixed movements and free computer work, and, with this system, we were able to measure the anterior/posterior direction tilt angle with an error of less than 4°. The smart wear does not have excessive wires, and its structure will be optimized for better posture estimation in a later study. PMID:29112125

  8. Optical interconnect technologies for high-bandwidth ICT systems

    NASA Astrophysics Data System (ADS)

    Chujo, Norio; Takai, Toshiaki; Mizushima, Akiko; Arimoto, Hideo; Matsuoka, Yasunobu; Yamashita, Hiroki; Matsushima, Naoki

    2016-03-01

    The bandwidth of information and communication technology (ICT) systems is increasing and is predicted to reach more than 10 Tb/s. However, an electrical interconnect cannot achieve such bandwidth because of its density limits. To solve this problem, we propose two types of high-density optical fiber wiring for backplanes and circuit boards such as interface boards and switch boards. One type uses routed ribbon fiber in a circuit board because it has the ability to be formed into complex shapes to avoid interfering with the LSI and electrical components on the board. The backplane is required to exhibit high density and flexibility, so the second type uses loose fiber. We developed a 9.6-Tb/s optical interconnect demonstration system using embedded optical modules, optical backplane, and optical connector in a network apparatus chassis. We achieved 25-Gb/s transmission between FPGAs via the optical backplane.

  9. 2 Gbit/s 0.5 μm complementary metal-oxide semiconductor optical transceiver with event-driven dynamic power-on capability

    NASA Astrophysics Data System (ADS)

    Wang, Xingle; Kiamilev, Fouad; Gui, Ping; Wang, Xiaoqing; Ekman, Jeremy; Zuo, Yongrong; Blankenberg, Jason; Haney, Michael

    2006-06-01

    A 2 Gb/s0.5 μm complementary metal-oxide semiconductor optical transceiver designed for board- or backplane level power-efficient interconnections is presented. The transceiver supports optical wake-on-link (OWL), an event-driven dynamic power-on technique. Depending on external events, the transceiver resides in either the active mode or the sleep mode and switches accordingly. The active-to-sleep transition shuts off the normal, gigabit link and turns on dedicated circuits to establish a low-power (~1.8 mW), low data rate (less than 100 Mbits/s) link. In contrast the normal, gigabit link consumes over 100 mW. Similarly the sleep-to-active transition shuts off the low-power link and turns on the normal, gigabit link. The low-power link, sharing the same optical channel with the normal, gigabit link, is used to achieve transmitter/receiver pair power-on synchronization and greatly reduces the power consumption of the transceiver. A free-space optical platform was built to evaluate the transceiver performance. The experiment successfully demonstrated the event-driven dynamic power-on operation. To our knowledge, this is the first time a dynamic power-on scheme has been implemented for optical interconnects. The areas of the circuits that implement the low-power link are approximately one-tenth of the areas of the gigabit link circuits.

  10. Note: cryogenic microstripline-on-Kapton microwave interconnects.

    PubMed

    Harris, A I; Sieth, M; Lau, J M; Church, S E; Samoska, L A; Cleary, K

    2012-08-01

    Simple broadband microwave interconnects are needed for increasing the size of focal plane heterodyne radiometer arrays. We have measured loss and crosstalk for arrays of microstrip transmission lines in flex circuit technology at 297 and 77 K, finding good performance to at least 20 GHz. The dielectric constant of Kapton substrates changes very little from 297 to 77 K, and the electrical loss drops. The small cross-sectional area of metal in a printed circuit structure yields overall thermal conductivities similar to stainless steel coaxial cable. Operationally, the main performance tradeoffs are between crosstalk and thermal conductivity. We tested a patterned ground plane to reduce heat flux.

  11. Performance optimization of dense-array concentrator photovoltaic system considering effects of circumsolar radiation and slope error.

    PubMed

    Wong, Chee-Woon; Chong, Kok-Keong; Tan, Ming-Hui

    2015-07-27

    This paper presents an approach to optimize the electrical performance of dense-array concentrator photovoltaic system comprised of non-imaging dish concentrator by considering the circumsolar radiation and slope error effects. Based on the simulated flux distribution, a systematic methodology to optimize the layout configuration of solar cells interconnection circuit in dense array concentrator photovoltaic module has been proposed by minimizing the current mismatch caused by non-uniformity of concentrated sunlight. An optimized layout of interconnection solar cells circuit with minimum electrical power loss of 6.5% can be achieved by minimizing the effects of both circumsolar radiation and slope error.

  12. Image dissector control and data system electronics, part 1, part 2, and part 3

    NASA Technical Reports Server (NTRS)

    1975-01-01

    The operating and calibration procedures, design details, and maintenance information for the control console and the associated electronics are presented. Detailed circuit connector information is included which describes the destination of each wire leaving each pin of each circuit board. The schematic diagrams of the circuit boards in the system and of the interconnection between boards and consoles are presented.

  13. Performance of Topological Insulator Interconnects

    NASA Astrophysics Data System (ADS)

    Philip, Timothy M.; Hirsbrunner, Mark R.; Park, Moon Jip; Gilbert, Matthew J.

    2017-01-01

    The poor performance of copper interconnects at the nanometer scale calls for new material solutions for continued scaling of integrated circuits. We propose the use of three dimensional time-reversal-invariant topological insulators (TIs), which host backscattering-protected surface states, for this purpose. Using semiclassical methods, we demonstrate that nanoscale TI interconnects have a resistance 1-3 orders of magnitude lower than copper interconnects and graphene nanoribbons at the nanometer scale. We use the nonequilibrium Green function (NEGF) formalism to measure the change in conductance of nanoscale TI and metal interconnects caused by the presence of impurity disorder. We show that metal interconnects suffer a resistance increase, relative to the clean limit, in excess of 500% due to disorder while the TI's surface states increase less than 35% in the same regime.

  14. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV).

    PubMed

    Shen, Wen-Wei; Chen, Kuan-Neng

    2017-12-01

    3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

  15. Intra- and interregional coregulation of opioid genes: broken symmetry in spinal circuits

    PubMed Central

    Kononenko, Olga; Galatenko, Vladimir; Andersson, Malin; Bazov, Igor; Watanabe, Hiroyuki; Zhou, Xing Wu; Iatsyshyna, Anna; Mityakina, Irina; Yakovleva, Tatiana; Sarkisyan, Daniil; Ponomarev, Igor; Krishtal, Oleg; Marklund, Niklas; Tonevitsky, Alex; Adkins, DeAnna L.; Bakalkin, Georgy

    2017-01-01

    Regulation of the formation and rewiring of neural circuits by neuropeptides may require coordinated production of these signaling molecules and their receptors that may be established at the transcriptional level. Here, we address this hypothesis by comparing absolute expression levels of opioid peptides with their receptors, the largest neuropeptide family, and by characterizing coexpression (transcriptionally coordinated) patterns of these genes. We demonstrated that expression patterns of opioid genes highly correlate within and across functionally and anatomically different areas. Opioid peptide genes, compared with their receptor genes, are transcribed at much greater absolute levels, which suggests formation of a neuropeptide cloud that covers the receptor-expressed circuits. Surprisingly, we found that both expression levels and the proportion of opioid receptors are strongly lateralized in the spinal cord, interregional coexpression patterns are side specific, and intraregional coexpression profiles are affected differently by left- and right-side unilateral body injury. We propose that opioid genes are regulated as interconnected components of the same molecular system distributed between distinct anatomic regions. The striking feature of this system is its asymmetric coexpression patterns, which suggest side-specific regulation of selective neural circuits by opioid neurohormones.—Kononenko, O., Galatenko, V., Andersson, M., Bazov, I., Watanabe, H., Zhou, X. W., Iatsyshyna, A., Mityakina, I., Yakovleva, T., Sarkisyan, D., Ponomarev, I., Krishtal, O., Marklund, N., Tonevitsky, A., Adkins, D. L., Bakalkin, G. Intra- and interregional coregulation of opioid genes: broken symmetry in spinal circuits. PMID:28122917

  16. Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET

    PubMed Central

    2012-01-01

    The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency. PMID:22901374

  17. Thick-SOI Echelle grating for any-to-any wavelength routing interconnection in multi-socket computing environments

    NASA Astrophysics Data System (ADS)

    Dabos, G.; Pitris, S.; Mitsolidou, C.; Alexoudi, T.; Fitsios, D.; Cherchi, M.; Harjanne, M.; Aalto, T.; Kanellos, G. T.; Pleros, N.

    2017-02-01

    As data centers constantly expand, electronic switches are facing the challenge of enhanced scalability and the request for increased pin-count and bandwidth. Photonic technology and wavelength division multiplexing have always been a strong alternative for efficient routing and their potential was already proven in the telecoms. CWDM transceivers have emerged in the board-to-board level interconnection, revealing the potential for wavelength-routing to be applied in the datacom and an AWGR-based approach has recently been proposed towards building an optical multi-socket interconnection to offer any-to-any connectivity with high aggregated throughput and reduced power consumption. Echelle gratings have long been recognized as the multiplexing block exhibiting smallest footprint and robustness in a wide number of applications compared to other alternatives such as the Arrayed Waveguide Grating. Such filtering devices can also perform in a similar way to cyclical AWGR and serve as mid-board routing platforms in multi-socket environments. In this communication, we present such a 3x3 Echelle grating integrated on thick SOI platform with aluminum-coated facets that is shown to perform successful wavelength-routing functionality at 10 Gb/s. The device exhibits a footprint of 60x270 μm2, while the static characterization showed a 3 dB on-chip loss for the best channel. The 3 dB-bandwidth of the channels was 4.5 nm and the free spectral range was 90 nm. The echelle was evaluated in a 2x2 wavelength routing topology, exhibiting a power penalty of below 0.4 dB at 10-9 BER for the C-band. Further experimental evaluations of the platform involve commercially available CWDM datacenter transceivers, towards emulating an optically-interconnected multi-socket environment traffic scenario.

  18. Hybrid stretchable circuits on silicone substrate

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Robinson, A., E-mail: adam.1.robinson@nokia.com; Aziz, A., E-mail: a.aziz1@lancaster.ac.uk; Liu, Q.

    When rigid and stretchable components are integrated onto a single elastic carrier substrate, large strain heterogeneities appear in the vicinity of the deformable-non-deformable interfaces. In this paper, we report on a generic approach to manufacture hybrid stretchable circuits where commercial electronic components can be mounted on a stretchable circuit board. Similar to printed circuit board development, the components are electrically bonded on the elastic substrate and interconnected with stretchable electrical traces. The substrate—a silicone matrix carrying concentric rigid disks—ensures both the circuit elasticity and the mechanical integrity of the most fragile materials.

  19. Electrochemical planarization

    DOEpatents

    Bernhardt, A.F.; Contolini, R.J.

    1993-10-26

    In a process for fabricating planarized thin film metal interconnects for integrated circuit structures, a planarized metal layer is etched back to the underlying dielectric layer by electropolishing, ion milling or other procedure. Electropolishing reduces processing time from hours to minutes and allows batch processing of multiple wafers. The etched back planarized thin film interconnect is flush with the dielectric layer. 12 figures.

  20. Multi-Layer E-Textile Circuits

    NASA Technical Reports Server (NTRS)

    Dunne, Lucy E.; Bibeau, Kaila; Mulligan, Lucie; Frith, Ashton; Simon, Cory

    2012-01-01

    Stitched e-textile circuits facilitate wearable, flexible, comfortable wearable technology. However, while stitched methods of e-textile circuits are common, multi-layer circuit creation remains a challenge. Here, we present methods of stitched multi-layer circuit creation using accessible tools and techniques.

  1. Multijunction high voltage concentrator solar cells

    NASA Technical Reports Server (NTRS)

    Valco, G. J.; Kapoor, V. J.; Evans, J. C.; Chai, A.-T.

    1981-01-01

    The standard integrated circuit technology has been developed to design and fabricate new innovative planar multi-junction solar cell chips for concentrated sunlight applications. This 1 cm x 1 cm cell consisted of several voltage generating regions called unit cells which were internally connected in series within a single chip resulting in high open circuit voltages. Typical open-circuit voltages of 3.6 V and short-circuit currents of 90 ma were obtained at 80 AM1 suns. A dramatic increase in both short circuit current and open circuit voltage with increased light levels was observed.

  2. Multi-scale reflection modulator-based optical interconnects

    NASA Astrophysics Data System (ADS)

    Nair, Rohit

    This dissertation describes the design, analysis, and experimental validation of micro- and macro-optical components for implementing optical interconnects at multiple scales for varied applications. Three distance scales are explored: millimeter, centimeter, and meter-scales. At the millimeter-scale, we propose the use of optical interconnects at the intra-chip level. With the rapid scaling down of CMOS critical dimensions in accordance to Moore's law, the bandwidth requirements of global interconnects in microprocessors has exceeded the capabilities of metal links. These are the wires that connect the most remote parts of the chip and are disproportionately problematic in terms of chip area and power consumption. Consequently, in the mid-2000s, we saw a shift in the chip architecture: a move towards multicore designs. However, this only delays the inevitable communication bottleneck between cores. To satisfy this bandwidth, we propose to replace the global metal interconnects with optical interconnects. We propose to use the hybrid integration of silicon with GaAs/AlAs-based multiple quantum well devices as optical modulators and photodetectors along with polymeric waveguides to transport the light. We use grayscale lithography to fabricate curved facets into the waveguides to couple light into the modulators and photodetectors. Next, at the chip-to-chip level in high-performance multiprocessor computing systems, communication distances vary from a few centimeters to tens of centimeters. An optical design for coupling light from off-chip lasers to on-chip surface-normal modulators is proposed in order to implement chip-to-chip free-space optical interconnects. The method uses a dual-prism module constructed from prisms made of two different glasses. The various alignment tolerances of the proposed system are investigated and found to be well within pick-and-place accuracies. For the off-chip lasers, vertical cavity surface emitting lasers (VCSELs) are proposed. The rationale behind using on-chip modulators rather than VCSELs is to avoid VCSEL thermal loads on chip, and because of higher reliability of modulators than VCSELs. Particularly above 10Gbps, an empirical model developed shows the rapid decrease of VCSEL median time to failure vs. data rate. Thus the proposed interconnect scheme which utilizes continuous wave VCSELs that are externally modulated by on-chip multiple quantum well modulators is applicable for chip-to-chip optical interconnects at 20Gbps and higher line data rates. Finally, for applications such as remote telemetry, where the interrogation distances can vary from a few meters to tens or even hundreds of meters we demonstrate a modulated retroreflector that utilizes InGaAs/InAlAs-based large-area multiple quantum well modulators on all three faces of a retroreflector. The large-area devices, fabricated by metalorganic chemical vapor deposition, are characterized in terms of the yield and leakage currents. A yield higher than that achieved previously using devices fabricated by molecular beam epitaxy is observed. The retroreflector module is constructed using standard FR4 printed circuit boards, thereby simplifying the wiring issue. A high optical contrast ratio of 8.23dB is observed for a drive of 20V. A free-standing PCB retroreflector is explored and found to have insufficient angular tolerances (+/-0.5 degrees). We show that the angular errors in the corner-cube construction can be corrected for using off-the-shelf optical components as opposed to mounting the PCBs on a precision corner cube, as has been done previously.

  3. Stretchable interconnections for flexible electronic systems.

    PubMed

    Jianhui, Lin; Bing, Yan; Xiaoming, Wu; Tianling, Ren; Litian, Liu

    2009-01-01

    Sensors, actuators and integrated circuits (IC) can be encapsulated together on an elastic substrate, which makes a flexible electronic system. In this system, electrical interconnections that can sustain large and reversible stretching are in great need. This paper is devoted to the fabrication of highly stretchable metal interconnections. Transfer printing technology is utilized, which mainly involves the transfer of 100-nm-thick gold ribbons from silicon wafers to pre-stretched elastic substrates. After the elastic substrates relax from the pre-strain, the gold ribbons buckle and form wavy geometries. These wavy geometries change in shapes to accommodate the applied strain and can be reversely stretched without cracks or fractures occurring, which will greatly raise the stretchability of the gold ribbons. As an application example, some of these wavy ribbons can accommodate high levels of stretching (up to 100%) and bending (with curvature radius down to 1.20 mm). Moreover, the efficiency and reliability of the transfer, especially for slender ribbons, have been increased due to the improvement of the technology. All the characteristics above will permit making stretchable gold conductors as interconnections for flexible electronic systems such as implantable medical systems and smart clothes.

  4. IC layout adjustment method and tool for improving dielectric reliability at interconnects

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kahng, Andrew B.; Chan, Tuck Boon

    Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges aremore » to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.« less

  5. Interconnect-free parallel logic circuits in a single mechanical resonator

    PubMed Central

    Mahboob, I.; Flurin, E.; Nishiguchi, K.; Fujiwara, A.; Yamaguchi, H.

    2011-01-01

    In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator. PMID:21326230

  6. Interconnect-free parallel logic circuits in a single mechanical resonator.

    PubMed

    Mahboob, I; Flurin, E; Nishiguchi, K; Fujiwara, A; Yamaguchi, H

    2011-02-15

    In conventional computers, wiring between transistors is required to enable the execution of Boolean logic functions. This has resulted in processors in which billions of transistors are physically interconnected, which limits integration densities, gives rise to huge power consumption and restricts processing speeds. A method to eliminate wiring amongst transistors by condensing Boolean logic into a single active element is thus highly desirable. Here, we demonstrate a novel logic architecture using only a single electromechanical parametric resonator into which multiple channels of binary information are encoded as mechanical oscillations at different frequencies. The parametric resonator can mix these channels, resulting in new mechanical oscillation states that enable the construction of AND, OR and XOR logic gates as well as multibit logic circuits. Moreover, the mechanical logic gates and circuits can be executed simultaneously, giving rise to the prospect of a parallel logic processor in just a single mechanical resonator.

  7. Coupling Between Microstrip Lines With Finite Width Ground Plane Embedded in Thin Film Circuits

    NASA Technical Reports Server (NTRS)

    Ponchak, George E.; Dalton, Edan; Tentzeris, Manos M.; Papapolymerou, John

    2003-01-01

    Three-dimensional (3D) interconnects built upon multiple layers of polyimide are required for constructing 3D circuits on CMOS (low resistivity) Si wafers, GaAs, and ceramic substrates. Thin film microstrip lines (TFMS) with finite width ground planes embedded in the polyimide are often used. However, the closely spaced TFMS lines a r e susceptible to high levels of coupling, which degrades circuit performance. In this paper, Finite Difference Time Domain (FDTD) analysis and experimental measurements a r e used to show that the ground planes must be connected by via holes to reduce coupling in both the forward and backward directions. Furthermore, it is shown that coupled microstrip lines establish a slotline type mode between the two ground planes and a dielectric waveguide type mode, and that the via holes recommended here eliminate these two modes.

  8. CMOS-compatible InP/InGaAs digital photoreceiver

    DOEpatents

    Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

    1997-01-01

    A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

  9. CMOS-compatible InP/InGaAs digital photoreceiver

    DOEpatents

    Lovejoy, M.L.; Rose, B.H.; Craft, D.C.; Enquist, P.M.; Slater, D.B. Jr.

    1997-11-04

    A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1,000 Mb/s or more. 4 figs.

  10. Three Dimensional Integration and On-Wafer Packaging for Heterogeneous Wafer-Scale Circuit Architectures

    DTIC Science & Technology

    2006-11-01

    Chip Level CMOS Chip High resistivity Si Metal Interconnect 25μm 24GHz fully integrated receiver CMOS transimpedance Amplifier (13GHz BW, 52dBΩ...power of a high-resistivity SiGe power amplifier chip with the wide operating frequency range and compactness of a CMOS mixed signal chip operating...With good RF channel selectivity, system specifications such as the linearity of the low noise amplifier (LNA), the phase noise of the voltage

  11. Chip-package nano-structured copper and nickel interconnections with metallic and polymeric bonding interfaces

    NASA Astrophysics Data System (ADS)

    Aggarwal, Ankur

    With the semiconductor industry racing toward a historic transition, nano chips with less than 45 nm features demand I/Os in excess of 20,000 that support computing speed in terabits per second, with multi-core processors aggregately providing highest bandwidth at lowest power. On the other hand, emerging mixed signal systems are driving the need for 3D packaging with embedded active components and ultra-short interconnections. Decreasing I/O pitch together with low cost, high electrical performance and high reliability are the key technological challenges identified by the 2005 International Technology Roadmap for Semiconductors (ITRS). Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nano-scale devices. Electrical interconnections are multi-functional materials that must also be able to withstand complex, sustained and cyclic thermo-mechanical loads. In addition, the materials must be environmentally-friendly, corrosion resistant, thermally stable over a long time, and resistant to electro-migration. A major challenge is also to develop economic processes that can be integrated into back end of the wafer foundry, i.e. with wafer level packaging. Device-to-system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect will not satisfy the thermo-mechanical reliability requirements at very fine pitches of the order of 30 microns and less. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. A novel chip-package interconnection technology is developed to address the IC packaging requirements beyond the ITRS projections and to introduce innovative design and fabrication concepts that will further advance the performance of the chip, the package, and the system board. The nano-structured interconnect technology simultaneously packages all the ICs intact in wafer form with quantum jump in the number of interconnections with the lowest electrical parasitics. The intrinsic properties of nano materials also enable several orders of magnitude higher interconnect densities with the best mechanical properties for the highest reliability and yet provide higher current and heat transfer densities. Nano-structured interconnects provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to enable advanced analog/digital testing, reliability testing, and burn-in at wafer level. This thesis investigates the electrical and mechanical performance of nanostructured interconnections through modeling and test vehicle fabrication. The analytical models evaluate the performance improvements over solder and compliant interconnections. Test vehicles with nano-interconnections were fabricated using low cost electro-deposition techniques and assembled with various bonding interfaces. Interconnections were fabricated at 200 micron pitch to compare with the existing solder joints and at 50 micron pitch to demonstrate fabrication processes at fine pitches. Experimental and modeling results show that the proposed nano-interconnections could enhance the reliability and potentially meet all the system performance requirements for the emerging micro/nano-systems.

  12. Computationally Efficient Modeling and Simulation of Large Scale Systems

    NASA Technical Reports Server (NTRS)

    Jain, Jitesh (Inventor); Koh, Cheng-Kok (Inventor); Balakrishnan, Vankataramanan (Inventor); Cauley, Stephen F (Inventor); Li, Hong (Inventor)

    2014-01-01

    A system for simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof, including a processor, and a memory, the processor configured to perform obtaining a matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure, the element values for each matrix including inductance L and inverse capacitance P, obtaining an adjacency matrix A associated with the interconnect structure, storing the matrices X, Y, and A in the memory, and performing numerical integration to solve first and second equations.

  13. RapidIO as a multi-purpose interconnect

    NASA Astrophysics Data System (ADS)

    Baymani, Simaolhoda; Alexopoulos, Konstantinos; Valat, Sébastien

    2017-10-01

    RapidIO (http://rapidio.org/) technology is a packet-switched high-performance fabric, which has been under active development since 1997. Originally meant to be a front side bus, it developed into a system level interconnect which is today used in all 4G/LTE base stations world wide. RapidIO is often used in embedded systems that require high reliability, low latency and scalability in a heterogeneous environment - features that are highly interesting for several use cases, such as data analytics and data acquisition (DAQ) networks. We will present the results of evaluating RapidIO in a data analytics environment, from setup to benchmark. Specifically, we will share the experience of running ROOT and Hadoop on top of RapidIO. To demonstrate the multi-purpose characteristics of RapidIO, we will also present the results of investigating RapidIO as a technology for high-speed DAQ networks using a generic multi-protocol event-building emulation tool. In addition we will present lessons learned from implementing native ports of CERN applications to RapidIO.

  14. TRANSISTOR HIGH VOLTAGE POWER SUPPLY

    DOEpatents

    Driver, G.E.

    1958-07-15

    High voltage, direct current power supplies are described for use with battery powered nuclear detection equipment. The particular advantages of the power supply described, are increased efficiency and reduced size and welght brought about by the use of transistors in the circuit. An important feature resides tn the employment of a pair of transistors in an alternatefiring oscillator circuit having a coupling transformer and other circuit components which are used for interconnecting the various electrodes of the transistors.

  15. Creating single-copy genetic circuits

    PubMed Central

    Lee, Jeong Wook; Gyorgy, Andras; Cameron, D. Ewen; Pyenson, Nora; Choi, Kyeong Rok; Way, Jeffrey C.; Silver, Pamela A.; Del Vecchio, Domitilla; Collins, James J.

    2017-01-01

    SUMMARY Synthetic biology is increasingly used to develop sophisticated living devices for basic and applied research. Many of these genetic devices are engineered using multi-copy plasmids, but as the field progresses from proof-of-principle demonstrations to practical applications, it is important to develop single-copy synthetic modules that minimize consumption of cellular resources and can be stably maintained as genomic integrants. Here we use empirical design, mathematical modeling and iterative construction and testing to build single-copy, bistable toggle switches with improved performance and reduced metabolic load that can be stably integrated into the host genome. Deterministic and stochastic models led us to focus on basal transcription to optimize circuit performance and helped to explain the resulting circuit robustness across a large range of component expression levels. The design parameters developed here provide important guidance for future efforts to convert functional multi-copy gene circuits into optimized single-copy circuits for practical, real-world use. PMID:27425413

  16. Laser printing of 3D metallic interconnects

    NASA Astrophysics Data System (ADS)

    Beniam, Iyoel; Mathews, Scott A.; Charipar, Nicholas A.; Auyeung, Raymond C. Y.; Piqué, Alberto

    2016-04-01

    The use of laser-induced forward transfer (LIFT) techniques for the printing of functional materials has been demonstrated for numerous applications. The printing gives rise to patterns, which can be used to fabricate planar interconnects. More recently, various groups have demonstrated electrical interconnects from laser-printed 3D structures. The laser printing of these interconnects takes place through aggregation of voxels of either molten metal or of pastes containing dispersed metallic particles. However, the generated 3D structures do not posses the same metallic conductivity as a bulk metal interconnect of the same cross-section and length as those formed by wire bonding or tab welding. An alternative is to laser transfer entire 3D structures using a technique known as lase-and-place. Lase-and-place is a LIFT process whereby whole components and parts can be transferred from a donor substrate onto a desired location with one single laser pulse. This paper will describe the use of LIFT to laser print freestanding, solid metal foils or beams precisely over the contact pads of discrete devices to interconnect them into fully functional circuits. Furthermore, this paper will also show how the same laser can be used to bend or fold the bulk metal foils prior to transfer, thus forming compliant 3D structures able to provide strain relief for the circuits under flexing or during motion from thermal mismatch. These interconnect "ridges" can span wide gaps (on the order of a millimeter) and accommodate height differences of tens of microns between adjacent devices. Examples of these laser printed 3D metallic bridges and their role in the development of next generation electronics by additive manufacturing will be presented.

  17. Fuzzy Edge Connectivity of Graphical Fuzzy State Space Model in Multi-connected System

    NASA Astrophysics Data System (ADS)

    Harish, Noor Ainy; Ismail, Razidah; Ahmad, Tahir

    2010-11-01

    Structured networks of interacting components illustrate complex structure in a direct or intuitive way. Graph theory provides a mathematical modeling for studying interconnection among elements in natural and man-made systems. On the other hand, directed graph is useful to define and interpret the interconnection structure underlying the dynamics of the interacting subsystem. Fuzzy theory provides important tools in dealing various aspects of complexity, imprecision and fuzziness of the network structure of a multi-connected system. Initial development for systems of Fuzzy State Space Model (FSSM) and a fuzzy algorithm approach were introduced with the purpose of solving the inverse problems in multivariable system. In this paper, fuzzy algorithm is adapted in order to determine the fuzzy edge connectivity between subsystems, in particular interconnected system of Graphical Representation of FSSM. This new approach will simplify the schematic diagram of interconnection of subsystems in a multi-connected system.

  18. The ultrasound brain helmet: new transducers and volume registration for in vivo simultaneous multi-transducer 3-D transcranial imaging.

    PubMed

    Lindsey, Brooks D; Light, Edward D; Nicoletto, Heather A; Bennett, Ellen R; Laskowitz, Daniel T; Smith, Stephen W

    2011-06-01

    Because stroke remains an important and time-sensitive health concern in developed nations, we present a system capable of fusing 3-D transcranial ultrasound volumes acquired from two sides of the head. This system uses custom sparse array transducers built on flexible multilayer circuits that can be positioned for simultaneous imaging through both temporal acoustic windows, allowing for potential registration of multiple real-time 3-D scans of cerebral vasculature. We examine hardware considerations for new matrix arrays-transducer design and interconnects-in this application. Specifically, it is proposed that SNR may be increased by reducing the length of probe cables. This claim is evaluated as part of the presented system through simulation, experimental data, and in vivo imaging. Ultimately, gains in SNR of 7 dB are realized by replacing a standard probe cable with a much shorter flex interconnect; higher gains may be possible using ribbon-based probe cables. In vivo images are presented, showing cerebral arteries with and without the use of microbubble contrast agent; they have been registered and fused using a simple algorithm which maximizes normalized cross-correlation.

  19. Optically interconnected phased arrays

    NASA Technical Reports Server (NTRS)

    Bhasin, Kul B.; Kunath, Richard R.

    1988-01-01

    Phased-array antennas are required for many future NASA missions. They will provide agile electronic beam forming for communications and tracking in the range of 1 to 100 GHz. Such phased arrays are expected to use several hundred GaAs monolithic integrated circuits (MMICs) as transmitting and receiving elements. However, the interconnections of these elements by conventional coaxial cables and waveguides add weight, reduce flexibility, and increase electrical interference. Alternative interconnections based on optical fibers, optical processing, and holography are under evaluation as possible solutions. In this paper, the current status of these techniques is described. Since high-frequency optical components such as photodetectors, lasers, and modulators are key elements in these interconnections, their performance and limitations are discussed.

  20. All-zigzag graphene nanoribbons for planar interconnect application

    NASA Astrophysics Data System (ADS)

    Chen, Po-An; Chiang, Meng-Hsueh; Hsu, Wei-Chou

    2017-07-01

    A feasible "lightning-shaped" zigzag graphene nanoribbon (ZGNR) structure for planar interconnects is proposed. Based on the density functional theory and non-equilibrium Green's function, the electron transport properties are evaluated. The lightning-shaped structure increases significantly the conductance of the graphene interconnect with an odd number of zigzag chains. This proposed technique can effectively utilize the linear I-V characteristic of asymmetric ZGNRs for interconnect application. Variability study accounting for width/length variation and the edge effect is also included. The transmission spectra, transmission eigenstates, and transmission pathways are analyzed to gain the physical insights. This lightning-shaped ZGNR enables all 2D material-based devices and circuits on flexible and transparent substrates.

  1. Dynamically re-configurable CMOS imagers for an active vision system

    NASA Technical Reports Server (NTRS)

    Yang, Guang (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

  2. College of DuPage Planning Process: College of DuPage Planning, the Foundation for Decision Making.

    ERIC Educational Resources Information Center

    College of DuPage, Glen Ellyn, IL. Office of Research and Planning.

    At College of DuPage (CD), in Glen Ellyn, Illinois, institutional planning is a multi-level, on-going process involving continuous college-wide input. The nine schematic levels in the CD planning process are interconnected and progress from global and broad-based issues, answering such questions as why the college exists, to concrete levels…

  3. Design of a multi-channel free space optical interconnection component

    NASA Astrophysics Data System (ADS)

    Jia, Da-Gong; Zhang, Pei-Song; Jing, Wen-Cai; Tan, Jun; Zhang, Hong-Xia; Zhang, Yi-Mo

    2008-11-01

    A multi-channel free space optical interconnection component, fiber optic rotary joint, was designed using a Dove prism. When the Dove prism is rotated an angle of α around the longitudinal axis, the image rotates an angle of 2 α. The optical interconnection component consists of the signal transmission system, Dove prim and driving mechanism. The planetary gears are used to achieve the speed ratio of 2:1 between the total optical interconnection component and the Dove prism. The C-lenses are employed to couple different optical signals in the signal transmission system. The coupling loss between the receiving fiber of stationary part and the transmitting fiber of rotary part is measured.

  4. A 10-GHz amplifier using an epitaxial lift-off pseudomorphic HEMT device

    NASA Technical Reports Server (NTRS)

    Young, Paul G.; Romanofsky, Robert R.; Alterovitz, Samuel A.; Mena, Rafael A.; Smith, Edwyn D.

    1993-01-01

    A process to integrate epitaxial lift-off devices and microstrip circuits has been demonstrated using a pseudomorphic HEMT on an alumina substrate. The circuit was a 10 GHz amplifier with the interconnection between the device and the microstrip circuit being made with photolithographically patterned metal. The measured and modeled response correlated extremely well with a maximum gain of 6.8 dB and a return loss of -14 dB at 10.4 GHz.

  5. Multilevel metallization method for fabricating a metal oxide semiconductor device

    NASA Technical Reports Server (NTRS)

    Hollis, B. R., Jr.; Feltner, W. R.; Bouldin, D. L.; Routh, D. E. (Inventor)

    1978-01-01

    An improved method is described of constructing a metal oxide semiconductor device having multiple layers of metal deposited by dc magnetron sputtering at low dc voltages and low substrate temperatures. The method provides multilevel interconnections and cross over between individual circuit elements in integrated circuits without significantly reducing the reliability or seriously affecting the yield.

  6. Chip-on-Board Technology 1996 Year-end Report (Design, Manufacturing, and Reliability Study)

    NASA Technical Reports Server (NTRS)

    Le, Binh Q.; Nhan, Elbert; Maurer, Richard H.; Lew, Ark L.; Lander, Juan R.

    1996-01-01

    The major impetus for flight qualifying Chip-On-Board (COB) packaging technology is the shift in emphasis for space missions to smaller, better, and cheaper spacecraft and satellites resulting from the NASA New Millenium initiative and similar requirements in DoD-sponsored programs. The most important benefit that can potentially be derived from miniaturizing spacecraft and satellites is the significant cost saving realizable if a smaller launch vehicle may be employed. Besides the program cost saving, there are several other advantages to building COB-based space hardware. First, once a well-controlled process is established, COB can be low cost compared to standard Multi-Chip Module (MCM) technology. This cost competitiveness is regarded as a result of the generally greater availability and lower cost of Known Good Die (KGD). Coupled with the elimination of the first level of packaging (chip package), compact, high-density circuit boards can be realized with Printed Wiring Boards (PWB) that can now be made with ever-decreasing feature size in line width and via hole. Since the COB packaging technique in this study is based mainly on populating bare dice on a suitable multi-layer laminate substrate which is not hermetically sealed, die coating for protection from the environment is required. In recent years, significant improvements have been made in die coating materials which further enhance the appeal of COB. Hysol epoxies, silicone, parylene and silicon nitride are desirable because of their compatible Thermal Coefficient of Expansion (TCE) and good moisture resistant capability. These die coating materials have all been used in the space and other industries with varying degrees of success. COB technology, specifically siliconnitride coated hardware, has been flown by Lockheed on the Polar satellite. In addition, DARPA has invested a substantial amount of resources on MCM and COB-related activities recently. With COB on the verge of becoming a dominant player in DoD programs, DARPA is increasing its support of the availability of KGDs which will help decrease their cost. Aside from the various major developments and trends in the space and defense industries that are favorable to the acceptance and widespread use of'COB packaging technology, implementing COB can be appealing in other aspects. Since the interconnection interface is usually the weak link in a system, the overall circuit or system reliability may actually be improved because of the elimination of a level of interconnect/packaging at the chip. With COB, mixing packaging technologies is possible. Because some devices are only available in commercial plastic packages, populating a multi-layer laminate substrate with both bare dice and plastic-package parts is inevitable. Another attractive feature of COB is that re-workability is possible if die coating is applied only on the die top. This method allows local replacement of individual dice that were found to be defective instead of replacing an entire board. In terms of thermal management, unpackaged devices offer a shorter thermal resistance path than their packaged counterparts thereby improving thermal sinking and heat removal from the parts.

  7. Results on 3D interconnection from AIDA WP3

    NASA Astrophysics Data System (ADS)

    Moser, Hans-Günther; AIDA-WP3

    2016-09-01

    From 2010 to 2014 the EU funded AIDA project established in one of its work packages (WP3) a network of groups working collaboratively on advanced 3D integration of electronic circuits and semiconductor sensors for applications in particle physics. The main motivation came from the severe requirements on pixel detectors for tracking and vertexing at future Particle Physics experiments at LHC, super-B factories and linear colliders. To go beyond the state-of-the-art, the main issues were studying low mass, high bandwidth applications, with radiation hardness capabilities, with low power consumption, offering complex functionality, with small pixel size and without dead regions. The interfaces and interconnects of sensors to electronic readout integrated circuits are a key challenge for new detector applications.

  8. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formedmore » with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.« less

  9. Evaluation of hybrid polymers for high-precision manufacturing of 3D optical interconnects by two-photon absorption lithography

    NASA Astrophysics Data System (ADS)

    Schleunitz, A.; Klein, J. J.; Krupp, A.; Stender, B.; Houbertz, R.; Gruetzner, G.

    2017-02-01

    The fabrication of optical interconnects has been widely investigated for the generation of optical circuit boards. Twophoton absorption (TPA) lithography (or high-precision 3D printing) as an innovative production method for direct manufacture of individual 3D photonic structures gains more and more attention when optical polymers are employed. In this regard, we have evaluated novel ORMOCER-based hybrid polymers tailored for the manufacture of optical waveguides by means of high-precision 3D printing. In order to facilitate future industrial implementation, the processability was evaluated and the optical performance of embedded waveguides was assessed. The results illustrate that hybrid polymers are not only viable consumables for industrial manufacture of polymeric micro-optics using generic processes such as UV molding. They also are potential candidates to fabricate optical waveguide systems down to the chip level where TPA-based emerging manufacturing techniques are engaged. Hence, it is shown that hybrid polymers continue to meet the increasing expectations of dynamically growing markets of micro-optics and optical interconnects due to the flexibility of the employed polymer material concept.

  10. Battery tester

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Poljak, M.D.

    1985-08-12

    This abstract discloses an improved battery tester for determining the acceptability of a Lithium Sulfur Dioxide (LiSO/sub 2/) storage battery at a given temperature and with one or more cells therein. The tester is generally made up of a first-comparison circuit having a series of series-interconnected components, namely a comparator, first and second flip-flops, and an AND gate. A first resistor is parallel connected to the first-comparison circuit. A second comparison circuit is also parallel connected to the first-comparison circuit and is generally made up of series-interconnected components, namely a second resistor, a capacitor, a buffer, and a second-comparator. Amore » first switch is connected to the first resistor and a second switch is parallel connected to the second-comparison circuit between the capacitor and the buffer. A logic control arrangement controls the operation of both switches, both comparators, and both flip-flops for testing a battery as to its start-up voltage and performance voltage characteristics all in a relatively short time period. In another embodiment of the tester, it is provided with an analog-to-digital converter, a memory, and a sensor arrangement for enhancing the versatility and reliability of the tester in determining the acceptability of a LiSO/sub 2/ battery.« less

  11. TAB interconnects for space concentrator solar cell arrays

    NASA Technical Reports Server (NTRS)

    Avery, J.; Bauman, J. S.; Gallagher, P.; Yerkes, J. W.

    1993-01-01

    The Boeing Company has evaluated the use of Tape Automated Bonding (TAB) and Surface Mount Technology (SMT) for a highly reliable, low cost interconnect for concentrator solar cell arrays. TAB and SMT are currently used in the electronics industry for chip interconnects and printed circuit board assembly. TAB tape consists of sixty-four 3-mil/1-oz tin-plated copper leads on 8-mil centers. The leads are thermocompression gang bonded to GaAs concentrator solar cell with silver contacts. This bond, known as an Inner Lead Bond (ILB), allows for pretesting and sorting capability via nondestruct wire bond pull and flash testing. Destructive wire pull tests resulted in preferred mid-span failures. Improvements in fill factor were attributed to decreased contact resistance on TAB bonded cells. Preliminary thermal cycling and aging tests were shown excellent bond strength and metallurgical results. Auger scans of bond sites reveals an Ag-Cu-Tin composition. Improper bonds are identified through flash testing as a performance degradation. On going testing of cells are underway at Lewis Research Center. SMT techniques are utilized to excise and form TAB leads post ILB. The formed leads' shape isolates thermal mismatches between the cells and the flex circuit they are mounted on. TABed cells are picked and placed with a gantry x-y-z positioning system with pattern recognition. Adhesives are selected to avoid thermal expansion mismatch and promote thermal transfer to the flex circuit. TAB outer lead bonds are parallel gap welded (PGW) to the flex circuit to finish the concentrator solar cell subassembly.

  12. Development of a Thin-Film Solar Cell Interconnect for the Powersphere Concept

    NASA Technical Reports Server (NTRS)

    Simburger, Edward J.; Matsumoto, James H.; Giants, Thomas W.; Garcia, Alexander, III; Liu, Simon; Rawal, Suraj P.; Perry, Alan R.; Marshall, Craig; Lin, John K.; Scarborough, Stephen E.

    2005-01-01

    Dual junction amorphous silicon (a-Si) solar cells produced on polyimide substrate have been selected as the best candidate to produce a lightweight solar array for the PowerSphere program. The PowerSphere concept features a space-inflatable, geodetic solar array approximately 0.6 meters in diameter and capable of generating about 20W of electrical power. Trade studies of various wiring concepts and connection methods led to an interconnect design with a copper contact that wraps around the edge, to the back of the solar cell. Applying Plasma Vapor Deposited (PVD) copper film to both sides and the edge of the solar cell produces the wrap around contact. This procedure results in a contact pad on the back of the solar cell, which is then laser welded to a flex circuit material. The flex circuit is constructed of copper in a custom designed routing pattern, and then sandwiched in a Kapton insulation layer. The flex circuit then serves as the primary power distribution system between the solar cells and the spacecraft. Flex circuit material is the best candidate for the wiring harness because it allows for low force deployment of the solar cells by the inflatable hinges on the PowerSphere. An additional frame structure, fabricated and assembled by ILC Dover, will reinforce the wrap around contact-flex blanket connection, thus providing a mechanically robust solar cell interconnect for the PowerSphere multifunctional program. The PowerSphere team will use the wraparound contact design approach as the primary solution for solar cell integration and the flex blanket for power distribution.

  13. Design and development of cell queuing, processing, and scheduling modules for the iPOINT input-buffered ATM testbed

    NASA Astrophysics Data System (ADS)

    Duan, Haoran

    1997-12-01

    This dissertation presents the concepts, principles, performance, and implementation of input queuing and cell-scheduling modules for the Illinois Pulsar-based Optical INTerconnect (iPOINT) input-buffered Asynchronous Transfer Mode (ATM) testbed. Input queuing (IQ) ATM switches are well suited to meet the requirements of current and future ultra-broadband ATM networks. The IQ structure imposes minimum memory bandwidth requirements for cell buffering, tolerates bursty traffic, and utilizes memory efficiently for multicast traffic. The lack of efficient cell queuing and scheduling solutions has been a major barrier to build high-performance, scalable IQ-based ATM switches. This dissertation proposes a new Three-Dimensional Queue (3DQ) and a novel Matrix Unit Cell Scheduler (MUCS) to remove this barrier. 3DQ uses a linked-list architecture based on Synchronous Random Access Memory (SRAM) to combine the individual advantages of per-virtual-circuit (per-VC) queuing, priority queuing, and N-destination queuing. It avoids Head of Line (HOL) blocking and provides per-VC Quality of Service (QoS) enforcement mechanisms. Computer simulation results verify the QoS capabilities of 3DQ. For multicast traffic, 3DQ provides efficient usage of cell buffering memory by storing multicast cells only once. Further, the multicast mechanism of 3DQ prevents a congested destination port from blocking other less- loaded ports. The 3DQ principle has been prototyped in the Illinois Input Queue (iiQueue) module. Using Field Programmable Gate Array (FPGA) devices, SRAM modules, and integrated on a Printed Circuit Board (PCB), iiQueue can process incoming traffic at 800 Mb/s. Using faster circuit technology, the same design is expected to operate at the OC-48 rate (2.5 Gb/s). MUCS resolves the output contention by evaluating the weight index of each candidate and selecting the heaviest. It achieves near-optimal scheduling and has a very short response time. The algorithm originates from a heuristic strategy that leads to 'socially optimal' solutions, yielding a maximum number of contention-free cells being scheduled. A novel mixed digital-analog circuit has been designed to implement the MUCS core functionality. The MUCS circuit maps the cell scheduling computation to the capacitor charging and discharging procedures that are conducted fully in parallel. The design has a uniform circuit structure, low interconnect counts, and low chip I/O counts. Using 2 μm CMOS technology, the design operates on a 100 MHz clock and finds a near-optimal solution within a linear processing time. The circuit has been verified at the transistor level by HSPICE simulation. During this research, a five-port IQ-based optoelectronic iPOINT ATM switch has been developed and demonstrated. It has been fully functional with an aggregate throughput of 800 Mb/s. The second-generation IQ-based switch is currently under development. Equipped with iiQueue modules and MUCS module, the new switch system will deliver a multi-gigabit aggregate throughput, eliminate HOL blocking, provide per-VC QoS, and achieve near-100% link bandwidth utilization. Complete documentation of input modules and trunk module for the existing testbed, and complete documentation of 3DQ, iiQueue, and MUCS for the second-generation testbed are given in this dissertation.

  14. Extended Range Passive Wireless Tag System and Method

    NASA Technical Reports Server (NTRS)

    Fink, Patrick W. (Inventor); Lin, Gregory Y. (Inventor); Kennedy, Timothy F. (Inventor)

    2013-01-01

    A passive wireless tag assembly comprises a plurality of antennas and transmission lines interconnected with circuitry and constructed and arranged in a Van Atta array or configuration to reflect an interrogator signal in the direction from where it came. The circuitry may comprise at least one surface acoustic wave (SAW)-based circuit that functions as a signal reflector and is operatively connected with an information circuit. In another embodiment, at least one delay circuit and/or at least one passive modulation circuit(s) are utilized. In yet another embodiment, antennas connected to SAW-based devices are mounted to at least one of the orthogonal surfaces of a corner reflector.

  15. Experimental demonstration of the optical multi-mesh hypercube: scaleable interconnection network for multiprocessors and multicomputers.

    PubMed

    Louri, A; Furlonge, S; Neocleous, C

    1996-12-10

    A prototype of a novel topology for scaleable optical interconnection networks called the optical multi-mesh hypercube (OMMH) is experimentally demonstrated to as high as a 150-Mbit/s data rate (2(7) - 1 nonreturn-to-zero pseudo-random data pattern) at a bit error rate of 10(-13)/link by the use of commercially available devices. OMMH is a scaleable network [Appl. Opt. 33, 7558 (1994); J. Lightwave Technol. 12, 704 (1994)] architecture that combines the positive features of the hypercube (small diameter, connectivity, symmetry, simple routing, and fault tolerance) and the mesh (constant node degree and size scaleability). The optical implementation method is divided into two levels: high-density local connections for the hypercube modules, and high-bit-rate, low-density, long connections for the mesh links connecting the hypercube modules. Free-space imaging systems utilizing vertical-cavity surface-emitting laser (VCSEL) arrays, lenslet arrays, space-invariant holographic techniques, and photodiode arrays are demonstrated for the local connections. Optobus fiber interconnects from Motorola are used for the long-distance connections. The OMMH was optimized to operate at the data rate of Motorola's Optobus (10-bit-wide, VCSEL-based bidirectional data interconnects at 150 Mbits/s). Difficulties encountered included the varying fan-out efficiencies of the different orders of the hologram, misalignment sensitivity of the free-space links, low power (1 mW) of the individual VCSEL's, and noise.

  16. High-Performance Computing for the Electromagnetic Modeling and Simulation of Interconnects

    NASA Technical Reports Server (NTRS)

    Schutt-Aine, Jose E.

    1996-01-01

    The electromagnetic modeling of packages and interconnects plays a very important role in the design of high-speed digital circuits, and is most efficiently performed by using computer-aided design algorithms. In recent years, packaging has become a critical area in the design of high-speed communication systems and fast computers, and the importance of the software support for their development has increased accordingly. Throughout this project, our efforts have focused on the development of modeling and simulation techniques and algorithms that permit the fast computation of the electrical parameters of interconnects and the efficient simulation of their electrical performance.

  17. Electro-Optic Computing Architectures. Volume I

    DTIC Science & Technology

    1998-02-01

    The objective of the Electro - Optic Computing Architecture (EOCA) program was to develop multi-function electro - optic interfaces and optical...interconnect units to enhance the performance of parallel processor systems and form the building blocks for future electro - optic computing architectures...Specifically, three multi-function interface modules were targeted for development - an Electro - Optic Interface (EOI), an Optical Interconnection Unit (OW

  18. Passive Resonant Bidirectional Converter with Galvanic Barrier

    NASA Technical Reports Server (NTRS)

    Rosenblad, Nathan S. (Inventor)

    2014-01-01

    A passive resonant bidirectional converter system that transports energy across a galvanic barrier includes a converter using at least first and second converter sections, each section including a pair of transfer terminals, a center tapped winding; a chopper circuit interconnected between the center tapped winding and one of the transfer terminals; an inductance feed winding interconnected between the other of the transfer terminals and the center tap and a resonant tank circuit including at least the inductance of the center tap winding and the parasitic capacitance of the chopper circuit for operating the converter section at resonance; the center tapped windings of the first and second converter sections being disposed on a first common winding core and the inductance feed windings of the first and second converter sections being disposed on a second common winding core for automatically synchronizing the resonant oscillation of the first and second converter sections and transferring energy between the converter sections until the voltage across the pairs of transfer terminals achieves the turns ratio of the center tapped windings.

  19. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    PubMed

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

  20. Computer model of a reverberant and parallel circuit coupling

    NASA Astrophysics Data System (ADS)

    Kalil, Camila de Andrade; de Castro, Maria Clícia Stelling; Cortez, Célia Martins

    2017-11-01

    The objective of the present study was to deepen the knowledge about the functioning of the neural circuits by implementing a signal transmission model using the Graph Theory in a small network of neurons composed of an interconnected reverberant and parallel circuit, in order to investigate the processing of the signals in each of them and the effects on the output of the network. For this, a program was developed in C language and simulations were done using neurophysiological data obtained in the literature.

  1. Compact fluid cooled power converter supporting multiple circuit boards

    DOEpatents

    Radosevich, Lawrence D.; Meyer, Andreas A.; Beihoff, Bruce C.; Kannenberg, Daniel G.

    2005-03-08

    A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  2. An optimized routing algorithm for the automated assembly of standard multimode ribbon fibers in a full-mesh optical backplane

    NASA Astrophysics Data System (ADS)

    Basile, Vito; Guadagno, Gianluca; Ferrario, Maddalena; Fassi, Irene

    2018-03-01

    In this paper a parametric, modular and scalable algorithm allowing a fully automated assembly of a backplane fiber-optic interconnection circuit is presented. This approach guarantees the optimization of the optical fiber routing inside the backplane with respect to specific criteria (i.e. bending power losses), addressing both transmission performance and overall costs issues. Graph theory has been exploited to simplify the complexity of the NxN full-mesh backplane interconnection topology, firstly, into N independent sub-circuits and then, recursively, into a limited number of loops easier to be generated. Afterwards, the proposed algorithm selects a set of geometrical and architectural parameters whose optimization allows to identify the optimal fiber optic routing for each sub-circuit of the backplane. The topological and numerical information provided by the algorithm are then exploited to control a robot which performs the automated assembly of the backplane sub-circuits. The proposed routing algorithm can be extended to any array architecture and number of connections thanks to its modularity and scalability. Finally, the algorithm has been exploited for the automated assembly of an 8x8 optical backplane realized with standard multimode (MM) 12-fiber ribbons.

  3. Novel Highly Parallel and Systolic Architectures Using Quantum Dot-Based Hardware

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Benny N.; Spotnitz, Matthew

    1997-01-01

    VLSI technology has made possible the integration of massive number of components (processors, memory, etc.) into a single chip. In VLSI design, memory and processing power are relatively cheap and the main emphasis of the design is on reducing the overall interconnection complexity since data routing costs dominate the power, time, and area required to implement a computation. Communication is costly because wires occupy the most space on a circuit and it can also degrade clock time. In fact, much of the complexity (and hence the cost) of VLSI design results from minimization of data routing. The main difficulty in VLSI routing is due to the fact that crossing of the lines carrying data, instruction, control, etc. is not possible in a plane. Thus, in order to meet this constraint, the VLSI design aims at keeping the architecture highly regular with local and short interconnection. As a result, while the high level of integration has opened the way for massively parallel computation, practical and full exploitation of such a capability in many applications of interest has been hindered by the constraints on interconnection pattern. More precisely. the use of only localized communication significantly simplifies the design of interconnection architecture but at the expense of somewhat restricted class of applications. For example, there are currently commercially available products integrating; hundreds of simple processor elements within a single chip. However, the lack of adequate interconnection pattern among these processing elements make them inefficient for exploiting a large degree of parallelism in many applications.

  4. Design and verification of wide-band, simultaneous, multi-frequency, tuning circuits for large moment transmitter loops

    NASA Astrophysics Data System (ADS)

    Dvorak, Steven L.; Sternberg, Ben K.; Feng, Wanjie

    2017-03-01

    In this paper we discuss the design and verification of wide-band, multi-frequency, tuning circuits for large-moment Transmitter (TX) loops. Since these multi-frequency, tuned-TX loops allow for the simultaneous transmission of multiple frequencies at high-current levels, they are ideally suited for frequency-domain geophysical systems that collect data while moving, such as helicopter mounted systems. Furthermore, since multi-frequency tuners use the same TX loop for all frequencies, instead of using separate tuned-TX loops for each frequency, they allow for the use of larger moment TX loops. In this paper we discuss the design and simulation of one- and three-frequency tuned TX loops and then present measurement results for a three-frequency, tuned-TX loop.

  5. Multi-piecewise quadratic nonlinearity memristor and its 2N-scroll and 2N + 1-scroll chaotic attractors system.

    PubMed

    Wang, Chunhua; Liu, Xiaoming; Xia, Hu

    2017-03-01

    In this paper, two kinds of novel ideal active flux-controlled smooth multi-piecewise quadratic nonlinearity memristors with multi-piecewise continuous memductance function are presented. The pinched hysteresis loop characteristics of the two memristor models are verified by building a memristor emulator circuit. Using the two memristor models establish a new memristive multi-scroll Chua's circuit, which can generate 2N-scroll and 2N+1-scroll chaotic attractors without any other ordinary nonlinear function. Furthermore, coexisting multi-scroll chaotic attractors are found in the proposed memristive multi-scroll Chua's circuit. Phase portraits, Lyapunov exponents, bifurcation diagrams, and equilibrium point analysis have been used to research the basic dynamics of the memristive multi-scroll Chua's circuit. The consistency of circuit implementation and numerical simulation verifies the effectiveness of the system design.

  6. Synchronization of Lienard-Type Oscillators in Uniform Electrical Networks

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sinha, Mohit; Dorfler, Florian; Johnson, Brian B.

    2016-08-01

    This paper presents a condition for global asymptotic synchronization of Lienard-type nonlinear oscillators in uniform LTI electrical networks with series R-L circuits modeling interconnections. By uniform electrical networks, we mean that the per-unit-length impedances are identical for the interconnecting lines. We derive conditions for global asymptotic synchronization for a particular feedback architecture where the derivative of the oscillator output current supplements the innate current feedback induced by simply interconnecting the oscillator to the network. Our proof leverages a coordinate transformation to a set of differential coordinates that emphasizes signal differences and the particular form of feedback permits the formulation ofmore » a quadratic Lyapunov function for this class of networks. This approach is particularly interesting since synchronization conditions are difficult to obtain by means of quadratic Lyapunov functions when only current feedback is used and for networks composed of series R-L circuits. Our synchronization condition depends on the algebraic connectivity of the underlying network, and reiterates the conventional wisdom from Lyapunov- and passivity-based arguments that strong coupling is required to ensure synchronization.« less

  7. Stretchable biocompatible electronics by embedding electrical circuitry in biocompatible elastomers.

    PubMed

    Jahanshahi, Amir; Salvo, Pietro; Vanfleteren, Jan

    2012-01-01

    Stretchable and curvilinear electronics has been used recently for the fabrication of micro systems interacting with the human body. The applications range from different kinds of implantable sensors inside the body to conformable electrodes and artificial skins. One of the key parameters in biocompatible stretchable electronics is the fabrication of reliable electrical interconnects. Although very recent literature has reported on the reliability of stretchable interconnects by cyclic loading, work still needs to be done on the integration of electrical circuitry composed of rigid components and stretchable interconnects in a biological environment. In this work, the feasibility of a developed technology to fabricate simple electrical circuits with meander shaped stretchable interconnects is presented. Stretchable interconnects are 200 nm thin Au layer supported with polyimide (PI). A stretchable array of light emitting diodes (LEDs) is embedded in biocompatible elastomer using this technology platform and it features a 50% total elongation.

  8. Advanced BCD technology with vertical DMOS based on a semi-insulation structure

    NASA Astrophysics Data System (ADS)

    Kui, Ma; Xinghua, Fu; Jiexin, Lin; Fashun, Yang

    2016-07-01

    A new semi-insulation structure in which one isolated island is connected to the substrate was proposed. Based on this semi-insulation structure, an advanced BCD technology which can integrate a vertical device without extra internal interconnection structure was presented. The manufacturing of the new semi-insulation structure employed multi-epitaxy and selectively multi-doping. Isolated islands are insulated with the substrate by reverse-biased PN junctions. Adjacent isolated islands are insulated by isolation wall or deep dielectric trenches. The proposed semi-insulation structure and devices fixed in it were simulated through two-dimensional numerical computer simulators. Based on the new BCD technology, a smart power integrated circuit was designed and fabricated. The simulated and tested results of Vertical DMOS, MOSFETs, BJTs, resistors and diodes indicated that the proposed semi-insulation structure is reasonable and the advanced BCD technology is validated. Project supported by the National Natural Science Foundation of China (No. 61464002), the Science and Technology Fund of Guizhou Province (No. Qian Ke He J Zi [2014]2066), and the Dr. Fund of Guizhou University (No. Gui Da Ren Ji He Zi (2013)20Hao).

  9. A new method for multi-bit and qudit transfer based on commensurate waveguide arrays

    NASA Astrophysics Data System (ADS)

    Petrovic, J.; Veerman, J. J. P.

    2018-05-01

    The faithful state transfer is an important requirement in the construction of classical and quantum computers. While the high-speed transfer is realized by optical-fibre interconnects, its implementation in integrated optical circuits is affected by cross-talk. The cross-talk between densely packed optical waveguides limits the transfer fidelity and distorts the signal in each channel, thus severely impeding the parallel transfer of states such as classical registers, multiple qubits and qudits. Here, we leverage on the suitably engineered cross-talk between waveguides to achieve the parallel transfer on optical chip. Waveguide coupling coefficients are designed to yield commensurate eigenvalues of the array and hence, periodic revivals of the input state. While, in general, polynomially complex, the inverse eigenvalue problem permits analytic solutions for small number of waveguides. We present exact solutions for arrays of up to nine waveguides and use them to design realistic buses for multi-(qu)bit and qudit transfer. Advantages and limitations of the proposed solution are discussed in the context of available fabrication techniques.

  10. Vehicle drive module having improved cooling configuration

    DOEpatents

    Radosevich, Lawrence D.; Meyer, Andreas A.; Kannenberg, Daniel G.; Kaishian, Steven C.; Beihoff, Bruce C.

    2007-02-13

    An electric vehicle drive includes a thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. Power electronic circuits are thermally matched, such as between component layers and between the circuits and the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  11. Power converter having improved fluid cooling

    DOEpatents

    Meyer, Andreas A.; Radosevich, Lawrence D.; Beihoff, Bruce C.; Kehl, Dennis L.; Kannenberg, Daniel G.

    2007-03-06

    A thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support, which may be controlled in a closed-loop manner. Interfacing between circuits, circuit mounting structure, and the support provide for greatly enhanced cooling. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  12. Thermally matched fluid cooled power converter

    DOEpatents

    Radosevich, Lawrence D.; Kannenberg, Daniel G.; Kaishian, Steven C.; Beihoff, Bruce C.

    2005-06-21

    A thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. Power electronic circuits are thermally matched, such as between component layers and between the circuits and the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  13. Millimeter-wave interconnects for microwave-frequency quantum machines

    NASA Astrophysics Data System (ADS)

    Pechal, Marek; Safavi-Naeini, Amir H.

    2017-10-01

    Superconducting microwave circuits form a versatile platform for storing and manipulating quantum information. A major challenge to further scalability is to find approaches for connecting these systems over long distances and at high rates. One approach is to convert the quantum state of a microwave circuit to optical photons that can be transmitted over kilometers at room temperature with little loss. Many proposals for electro-optic conversion between microwave and optics use optical driving of a weak three-wave mixing nonlinearity to convert the frequency of an excitation. Residual absorption of this optical pump leads to heating, which is problematic at cryogenic temperatures. Here we propose an alternative approach where a nonlinear superconducting circuit is driven to interconvert between microwave-frequency (7 ×109 Hz) and millimeter-wave-frequency photons (3 ×1011 Hz). To understand the potential for quantum state conversion between microwave and millimeter-wave photons, we consider the driven four-wave mixing quantum dynamics of nonlinear circuits. In contrast to the linear dynamics of the driven three-wave mixing converters, the proposed four-wave mixing converter has nonlinear decoherence channels that lead to a more complex parameter space of couplings and pump powers that we map out. We consider physical realizations of such converter circuits by deriving theoretically the upper bound on the maximum obtainable nonlinear coupling between any two modes in a lossless circuit, and synthesizing an optimal circuit based on realistic materials that saturates this bound. Our proposed circuit dissipates less than 10-9 times the energy of current electro-optic converters per qubit. Finally, we outline the quantum link budget for optical, microwave, and millimeter-wave connections, showing that our approach is viable for realizing interconnected quantum processors for intracity or quantum data center environments.

  14. Porous silicon based micro-opto-electro-mechanical-systems (MOEMS) components for free space optical interconnects

    NASA Astrophysics Data System (ADS)

    Song, Da

    2008-02-01

    One of the major challenges confronting the current integrated circuits (IC) industry is the metal "interconnect bottleneck". To overcome this obstacle, free space optical interconnects (FSOIs) can be used to address the demand for high speed data transmission, multi-functionality and multi-dimensional integration for the next generation IC. One of the crucial elements in FSOIs system is to develop a high performance and flexible optical network to transform the incoming optical signal into a distributed set of optical signals whose direction, alignment and power can be independently controlled. Among all the optical materials for the realization of FSOI components, porous silicon (PSi) is one of the most promising candidates because of its unique optical properties, flexible fabrication methods and integration with conventional IC material sets. PSi-based Distributed Bragg Reflector (DBR) and Fabry-Perot (F-P) structures with unique optical properties are realized by electrochemical etching of silicon. By incorporating PSi optical structures with Micro-Opto-Electro-Mechanical-Systems (MOEMS), several components required for FSOI have been developed. The first type of component is the out-of-plane freestanding optical switch. Implementing a PSi DBR structure as an optically active region, the device can realize channel selection by changing the tilting angle of the micromirror supported by the thermal bimorph actuator. All the fabricated optical switches have reached kHz working frequency and life time of millions of cycles. The second type of component is the in-plane tunable optical filter. By introducing PSi F-P structure into the in-plane PSi film, a thermally tunable optical filter with a sensitivity of 7.9nm/V has been realized for add/drop optical signal selection. Also, for the first time, a new type of PSi based reconfigurable diffractive optical element (DOE) has been developed. By using patterned photoresist as a protective mask for electrochemical etching, the freestanding PSi-based MOEMS DOE has been created as a beam splitter to redistribute the incoming optical signal with onto desired detector arrays. All the developed devices are realized in array fashion and can be addressed and controlled individually. The combination of PSi and MOEMS opens the door for a new generation of silicon compatible optical interconnects.

  15. Finite element analysis on deformation of stretchable electronic interconnect substrate using polydimethylsiloxanes (PDMS)

    NASA Astrophysics Data System (ADS)

    Roslan, M. F.; Shaffiar, N. M.; Khairusshima, M. K. N.; Sharifah, I. S. S.

    2018-01-01

    Over the years, the technology of electronic industry has growth tremendously. Open ended research on how to make a better concept of electronic circuit is ongoing especially on the stretchable electronic devices. There are many designs to achieve stretchability in electronic circuits. The problem occurs when deformation applied to the stretchable electronic circuit, it cannot maintain its functionality. Fracture may happen on the conductor. In this research, the study on deformation of stretchable electronic interconnects substrate using Polydimethlysiloxanes is carried out. The purpose of this research are to study the axial deformation occur, to determine the optimum shape of the conductor designs (horseshoe, rectangular and u-shape design) for the stretchable electronic interconnect and to compare the mechanical properties of Polydimethlysiloxanes (PDMS) with Polyurethane (PU) using Finite Element Analysis (FEA). The simulation was done on the FE model of the stretchable circuit with dimension of 2.4 X 2.4 X 0.5 mm. The stretching of the FE model was simulated with the range of elongation at 10, 20 and 30 percent from its original length in order to find the strain value for all three of the conductor designs. The best conductor design is used to simulate with different types of substrate (PDMS and PU). From the simulation result, Horseshoe design record the lowest strain value for each elongation, followed by rectangular and U-shape design. Thus, Horseshoe is considered as the optimum design for the conductor compared to the other two designs. From the result also, it shows that PDMS substrate will offer more maximum allowable stretchability compared to PU substrates. Thus PDMS is considered as a better substrate compare to PU. PDMS is a good material to replace PU since it can perform under tension much better mechanically.

  16. Towards co-packaging of photonics and microelectronics in existing manufacturing facilities

    NASA Astrophysics Data System (ADS)

    Janta-Polczynski, Alexander; Cyr, Elaine; Bougie, Jerome; Drouin, Alain; Langlois, Richard; Childers, Darrell; Takenobu, Shotaro; Taira, Yoichi; Lichoulas, Ted W.; Kamlapurkar, Swetha; Engelmann, Sebastian; Fortier, Paul; Boyer, Nicolas; Barwicz, Tymon

    2018-02-01

    The impact of integrated photonics on optical interconnects is currently muted by challenges in photonic packaging and in the dense integration of photonic modules with microelectronic components on printed circuit boards. Single mode optics requires tight alignment tolerance for optical coupling and maintaining this alignment in a cost-efficient package can be challenging during thermal excursions arising from downstream microelectronic assembly processes. In addition, the form factor of typical fiber connectors is incompatible with the dense module integration expected on printed circuit boards. We have implemented novel approaches to interfacing photonic chips to standard optical fibers. These leverage standard high throughput microelectronic assembly tooling and self-alignment techniques resulting in photonic packaging that is scalable in manufacturing volume and in the number of optical IOs per chip. In addition, using dense optical fiber connectors with space-efficient latching of fiber patch cables results in compact module size and efficient board integration, bringing the optics closer to the logic chip to alleviate bandwidth bottlenecks. This packaging direction is also well suited for embedding optics in multi-chip modules, including both photonic and microelectronic chips. We discuss the challenges and rewards in this type of configuration such as thermal management and signal integrity.

  17. Inmarsat aeronautical mobile satellite system: Internetworking issues

    NASA Technical Reports Server (NTRS)

    Sengupta, Jay R.

    1990-01-01

    The Inmarsat Aeronautical Mobile Satellite System (AMSS) provides air-ground and air-air communications services to aero-mobile users on a global basis. Communicating parties may be connected either directly, or more commonly, via interconnecting networks to the Inmarsat AMSS, in order to construct end-to-end communications circuits. The aircraft earth station (AES) and the aeronautical ground earth station (GES) are the points of interconnection of the Inmarsat AMSS to users, as well as to interconnecting networks. This paper reviews the internetworking aspects of the Inmarsat AMSS, by introducing the Inmarsat AMSS network architecture and services concepts and then discussing the internetwork address/numbering and routing techniques.

  18. RLE progress report no. 133, 1 January - 31 December 1990

    NASA Technical Reports Server (NTRS)

    Allen, Jonathan; Kleppner, Daniel; Ziegler, Mary J. (Editor); Passero, Barbara (Editor)

    1990-01-01

    Activities of the Research Laboratory of Electronics at MIT are summarized. NASA-sponsored research in the area of synthetic aperture radar image interpretation and simulation is described. Other government-sponsored and industry-sponsored studies are also described which address the following topics: microwave and millimeter wave integrated circuits, high-speed integrated circuit interconnects, Instrument Landing System/Microwave Landing System frequency management assessment, and superconducting electronics.

  19. Study of complete interconnect reliability for a GaAs MMIC power amplifier

    NASA Astrophysics Data System (ADS)

    Lin, Qian; Wu, Haifeng; Chen, Shan-ji; Jia, Guoqing; Jiang, Wei; Chen, Chao

    2018-05-01

    By combining the finite element analysis (FEA) and artificial neural network (ANN) technique, the complete prediction of interconnect reliability for a monolithic microwave integrated circuit (MMIC) power amplifier (PA) at the both of direct current (DC) and alternating current (AC) operation conditions is achieved effectively in this article. As a example, a MMIC PA is modelled to study the electromigration failure of interconnect. This is the first time to study the interconnect reliability for an MMIC PA at the conditions of DC and AC operation simultaneously. By training the data from FEA, a high accuracy ANN model for PA reliability is constructed. Then, basing on the reliability database which is obtained from the ANN model, it can give important guidance for improving the reliability design for IC.

  20. Electro-Optic Computing Architectures: Volume II. Components and System Design and Analysis

    DTIC Science & Technology

    1998-02-01

    The objective of the Electro - Optic Computing Architecture (EOCA) program was to develop multi-function electro - optic interfaces and optical...interconnect units to enhance the performance of parallel processor systems and form the building blocks for future electro - optic computing architectures...Specifically, three multi-function interface modules were targeted for development - an Electro - Optic Interface (EOI), an Optical Interconnection Unit

  1. Statistical metrology—measurement and modeling of variation for advanced process development and design rule generation

    NASA Astrophysics Data System (ADS)

    Boning, Duane S.; Chung, James E.

    1998-11-01

    Advanced process technology will require more detailed understanding and tighter control of variation in devices and interconnects. The purpose of statistical metrology is to provide methods to measure and characterize variation, to model systematic and random components of that variation, and to understand the impact of variation on both yield and performance of advanced circuits. Of particular concern are spatial or pattern-dependencies within individual chips; such systematic variation within the chip can have a much larger impact on performance than wafer-level random variation. Statistical metrology methods will play an important role in the creation of design rules for advanced technologies. For example, a key issue in multilayer interconnect is the uniformity of interlevel dielectric (ILD) thickness within the chip. For the case of ILD thickness, we describe phases of statistical metrology development and application to understanding and modeling thickness variation arising from chemical-mechanical polishing (CMP). These phases include screening experiments including design of test structures and test masks to gather electrical or optical data, techniques for statistical decomposition and analysis of the data, and approaches to calibrating empirical and physical variation models. These models can be integrated with circuit CAD tools to evaluate different process integration or design rule strategies. One focus for the generation of interconnect design rules are guidelines for the use of "dummy fill" or "metal fill" to improve the uniformity of underlying metal density and thus improve the uniformity of oxide thickness within the die. Trade-offs that can be evaluated via statistical metrology include the improvements to uniformity possible versus the effect of increased capacitance due to additional metal.

  2. Universal test system for system embedded optical interconnect

    NASA Astrophysics Data System (ADS)

    Pitwon, R.; Wang, K.; Immonen, M.; Schröder, H.; Neitz, M.

    2018-02-01

    We introduce a universal test and measurement system allowing comparative characterisation of optical transceivers, board-to-board optical connectors and both embedded and passive optical circuit boards. The system comprises a test enclosure with interlocking and interchangeable test cards, allowing different technologies spanning different Technology Readiness Levels to be both characterised alone and in combination with other technologies. They form part of the open test design standards portfolio developed on the FP7 PhoxTroT and H2020 COSMICC projects and allow testing on a common test platform.

  3. Compact Interconnection Networks Based on Quantum Dots

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarress, Katayoon; Spotnitz, Matthew

    2003-01-01

    Architectures that would exploit the distinct characteristics of quantum-dot cellular automata (QCA) have been proposed for digital communication networks that connect advanced digital computing circuits. In comparison with networks of wires in conventional very-large-scale integrated (VLSI) circuitry, the networks according to the proposed architectures would be more compact. The proposed architectures would make it possible to implement complex interconnection schemes that are required for some advanced parallel-computing algorithms and that are difficult (and in many cases impractical) to implement in VLSI circuitry. The difficulty of implementation in VLSI and the major potential advantage afforded by QCA were described previously in Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), NASA Tech Briefs, Vol. 25, No. 10 (October 2001), page 42. To recapitulate: Wherever two wires in a conventional VLSI circuit cross each other and are required not to be in electrical contact with each other, there must be a layer of electrical insulation between them. This, in turn, makes it necessary to resort to a noncoplanar and possibly a multilayer design, which can be complex, expensive, and even impractical. As a result, much of the cost of designing VLSI circuits is associated with minimization of data routing and assignment of layers to minimize crossing of wires. Heretofore, these considerations have impeded the development of VLSI circuitry to implement complex, advanced interconnection schemes. On the other hand, with suitable design and under suitable operating conditions, QCA-based signal paths can be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes. The proposed architectures require two advances in QCA-based circuitry beyond basic QCA-based binary-signal wires described in the cited prior article. One of these advances would be the development of QCA-based wires capable of bidirectional transmission of signals. The other advance would be the development of QCA circuits capable of high-impedance state outputs. The high-impedance states would be utilized along with the 0- and 1-state outputs of QCA.

  4. Resilience of the quantum Rabi model in circuit QED

    NASA Astrophysics Data System (ADS)

    E Manucharyan, Vladimir; Baksic, Alexandre; Ciuti, Cristiano

    2017-07-01

    In circuit quantum electrodynamics (circuit QED), an artificial ‘circuit atom’ can couple to a quantized microwave radiation much stronger than its real atomic counterpart. The celebrated quantum Rabi model describes the simplest interaction of a two-level system with a single-mode boson field. When the coupling is large enough, the bare multilevel structure of a realistic circuit atom cannot be ignored even if the circuit is strongly anharmonic. We explored this situation theoretically for flux (fluxonium) and charge (Cooper pair box) type multi-level circuits tuned to their respective flux/charge degeneracy points. We identified which spectral features of the quantum Rabi model survive and which are renormalized for large coupling. Despite significant renormalization of the low-energy spectrum in the fluxonium case, the key quantum Rabi feature—nearly-degenerate vacuum consisting of an atomic state entangled with a multi-photon field—appears in both types of circuits when the coupling is sufficiently large. Like in the quantum Rabi model, for very large couplings the entanglement spectrum is dominated by only two, nearly equal eigenvalues, in spite of the fact that a large number of bare atomic states are actually involved in the atom-resonator ground state. We interpret the emergence of the two-fold degeneracy of the vacuum of both circuits as an environmental suppression of flux/charge tunneling due to their dressing by virtual low-/high-impedance photons in the resonator. For flux tunneling, the dressing is nothing else than the shunting of a Josephson atom with a large capacitance of the resonator. Suppression of charge tunneling is a manifestation of the dynamical Coulomb blockade of transport in tunnel junctions connected to resistive leads.

  5. Distributed and Lumped Parameter Models for the Characterization of High Throughput Bioreactors

    PubMed Central

    Conoscenti, Gioacchino; Cutrì, Elena; Tuan, Rocky S.; Raimondi, Manuela T.; Gottardi, Riccardo

    2016-01-01

    Next generation bioreactors are being developed to generate multiple human cell-based tissue analogs within the same fluidic system, to better recapitulate the complexity and interconnection of human physiology [1, 2]. The effective development of these devices requires a solid understanding of their interconnected fluidics, to predict the transport of nutrients and waste through the constructs and improve the design accordingly. In this work, we focus on a specific model of bioreactor, with multiple input/outputs, aimed at generating osteochondral constructs, i.e., a biphasic construct in which one side is cartilaginous in nature, while the other is osseous. We next develop a general computational approach to model the microfluidics of a multi-chamber, interconnected system that may be applied to human-on-chip devices. This objective requires overcoming several challenges at the level of computational modeling. The main one consists of addressing the multi-physics nature of the problem that combines free flow in channels with hindered flow in porous media. Fluid dynamics is also coupled with advection-diffusion-reaction equations that model the transport of biomolecules throughout the system and their interaction with living tissues and C constructs. Ultimately, we aim at providing a predictive approach useful for the general organ-on-chip community. To this end, we have developed a lumped parameter approach that allows us to analyze the behavior of multi-unit bioreactor systems with modest computational effort, provided that the behavior of a single unit can be fully characterized. PMID:27669413

  6. Distributed and Lumped Parameter Models for the Characterization of High Throughput Bioreactors.

    PubMed

    Iannetti, Laura; D'Urso, Giovanna; Conoscenti, Gioacchino; Cutrì, Elena; Tuan, Rocky S; Raimondi, Manuela T; Gottardi, Riccardo; Zunino, Paolo

    Next generation bioreactors are being developed to generate multiple human cell-based tissue analogs within the same fluidic system, to better recapitulate the complexity and interconnection of human physiology [1, 2]. The effective development of these devices requires a solid understanding of their interconnected fluidics, to predict the transport of nutrients and waste through the constructs and improve the design accordingly. In this work, we focus on a specific model of bioreactor, with multiple input/outputs, aimed at generating osteochondral constructs, i.e., a biphasic construct in which one side is cartilaginous in nature, while the other is osseous. We next develop a general computational approach to model the microfluidics of a multi-chamber, interconnected system that may be applied to human-on-chip devices. This objective requires overcoming several challenges at the level of computational modeling. The main one consists of addressing the multi-physics nature of the problem that combines free flow in channels with hindered flow in porous media. Fluid dynamics is also coupled with advection-diffusion-reaction equations that model the transport of biomolecules throughout the system and their interaction with living tissues and C constructs. Ultimately, we aim at providing a predictive approach useful for the general organ-on-chip community. To this end, we have developed a lumped parameter approach that allows us to analyze the behavior of multi-unit bioreactor systems with modest computational effort, provided that the behavior of a single unit can be fully characterized.

  7. Ultra-precision fabrication of high density micro-optical backbone interconnections for data center and mobile application

    NASA Astrophysics Data System (ADS)

    Lohmann, U.; Jahns, J.; Wagner, T.; Werner, C.

    2012-10-01

    A microoptical 3D interconnection scheme and fabricated samples of this fiberoptical multi-channel interconnec- tion with an actual capacity of 144 channels were shown. Additionally the aspects of micrometer-fabrication of such microoptical interconnection modules in the view of alignment-tolerances were considered. For the realiza- tion of the interconnection schemes, the approach of planar-integrated free space optics (PIFSO) is used with its well known advantages. This approach offers the potential for complex interconnectivity, and yet compact size.

  8. Evaluation of advanced microelectronic fluxless solder-bump contacts for hybrid microcircuits

    NASA Technical Reports Server (NTRS)

    Mandal, R. P.

    1976-01-01

    Technology for interconnecting monolithic integrated circuit chips with other components is investigated. The advantages and disadvantages of the current flip-chip approach as compared to other interconnection methods are outlined. A fluxless solder-bump contact technology is evaluated. Multiple solder-bump contacts were formed on silicon integrated circuit chips. The solder-bumps, comprised of a rigid nickel under layer and a compliant solder overlayer, were electroformed onto gold device pads with the aid of thick dry film photomasks. Different solder alloys and the use of conductive epoxy for bonding were explored. Fluxless solder-bump bond quality and reliability were evaluated by measuring the effects of centrifuge, thermal cycling, and high temperature storage on bond visual characteristics, bond electrical continuity, and bond shear tests. The applicability and suitability of this technology for hybrid microelectronic packaging is discussed.

  9. Voltage imaging to understand connections and functions of neuronal circuits.

    PubMed

    Antic, Srdjan D; Empson, Ruth M; Knöpfel, Thomas

    2016-07-01

    Understanding of the cellular mechanisms underlying brain functions such as cognition and emotions requires monitoring of membrane voltage at the cellular, circuit, and system levels. Seminal voltage-sensitive dye and calcium-sensitive dye imaging studies have demonstrated parallel detection of electrical activity across populations of interconnected neurons in a variety of preparations. A game-changing advance made in recent years has been the conceptualization and development of optogenetic tools, including genetically encoded indicators of voltage (GEVIs) or calcium (GECIs) and genetically encoded light-gated ion channels (actuators, e.g., channelrhodopsin2). Compared with low-molecular-weight calcium and voltage indicators (dyes), the optogenetic imaging approaches are 1) cell type specific, 2) less invasive, 3) able to relate activity and anatomy, and 4) facilitate long-term recordings of individual cells' activities over weeks, thereby allowing direct monitoring of the emergence of learned behaviors and underlying circuit mechanisms. We highlight the potential of novel approaches based on GEVIs and compare those to calcium imaging approaches. We also discuss how novel approaches based on GEVIs (and GECIs) coupled with genetically encoded actuators will promote progress in our knowledge of brain circuits and systems. Copyright © 2016 the American Physiological Society.

  10. Voltage imaging to understand connections and functions of neuronal circuits

    PubMed Central

    Antic, Srdjan D.; Empson, Ruth M.

    2016-01-01

    Understanding of the cellular mechanisms underlying brain functions such as cognition and emotions requires monitoring of membrane voltage at the cellular, circuit, and system levels. Seminal voltage-sensitive dye and calcium-sensitive dye imaging studies have demonstrated parallel detection of electrical activity across populations of interconnected neurons in a variety of preparations. A game-changing advance made in recent years has been the conceptualization and development of optogenetic tools, including genetically encoded indicators of voltage (GEVIs) or calcium (GECIs) and genetically encoded light-gated ion channels (actuators, e.g., channelrhodopsin2). Compared with low-molecular-weight calcium and voltage indicators (dyes), the optogenetic imaging approaches are 1) cell type specific, 2) less invasive, 3) able to relate activity and anatomy, and 4) facilitate long-term recordings of individual cells' activities over weeks, thereby allowing direct monitoring of the emergence of learned behaviors and underlying circuit mechanisms. We highlight the potential of novel approaches based on GEVIs and compare those to calcium imaging approaches. We also discuss how novel approaches based on GEVIs (and GECIs) coupled with genetically encoded actuators will promote progress in our knowledge of brain circuits and systems. PMID:27075539

  11. Modeling the Transitions between Collective and Solitary Migration Phenotypes in Cancer Metastasis

    PubMed Central

    Huang, Bin; Jolly, Mohit Kumar; Lu, Mingyang; Tsarfaty, Ilan; Ben-Jacob, Eshel; Onuchic, Jose’ N

    2015-01-01

    Cellular plasticity during cancer metastasis is a major clinical challenge. Two key cellular plasticity mechanisms —Epithelial-to-Mesenchymal Transition (EMT) and Mesenchymal-to-Amoeboid Transition (MAT) – have been carefully investigated individually, yet a comprehensive understanding of their interconnections remains elusive. Previously, we have modeled the dynamics of the core regulatory circuits for both EMT (miR-200/ZEB/miR-34/SNAIL) and MAT (Rac1/RhoA). We now extend our previous work to study the coupling between these two core circuits by considering the two microRNAs (miR-200 and miR-34) as external signals to the core MAT circuit. We show that this coupled circuit enables four different stable steady states (phenotypes) that correspond to hybrid epithelial/mesenchymal (E/M), mesenchymal (M), amoeboid (A) and hybrid amoeboid/mesenchymal (A/M) phenotypes. Our model recapitulates the metastasis-suppressing role of the microRNAs even in the presence of EMT-inducing signals like Hepatocyte Growth Factor (HGF). It also enables mapping the microRNA levels to the transitions among various cell migration phenotypes. Finally, it offers a mechanistic understanding for the observed phenotypic transitions among different cell migration phenotypes, specifically the Collective-to-Amoeboid Transition (CAT). PMID:26627083

  12. Proteus: a reconfigurable computational network for computer vision

    NASA Astrophysics Data System (ADS)

    Haralick, Robert M.; Somani, Arun K.; Wittenbrink, Craig M.; Johnson, Robert; Cooper, Kenneth; Shapiro, Linda G.; Phillips, Ihsin T.; Hwang, Jenq N.; Cheung, William; Yao, Yung H.; Chen, Chung-Ho; Yang, Larry; Daugherty, Brian; Lorbeski, Bob; Loving, Kent; Miller, Tom; Parkins, Larye; Soos, Steven L.

    1992-04-01

    The Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing The system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs a hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1,024 RISC processors. The processors use one megabyte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates, and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. The parallelism is directly controllable through an advanced software system for partitioning, scheduling, and development. System software includes a translator for the INSIGHT language, a parallel debugger, low and high level simulators, and a message passing system for all control needs. Image processing application software includes a variety of point operators neighborhood, operators, convolution, and the mathematical morphology operations of binary and gray scale dilation, erosion, opening, and closing.

  13. Elastic properties of porous low-k dielectric nano-films

    NASA Astrophysics Data System (ADS)

    Zhou, W.; Bailey, S.; Sooryakumar, R.; King, S.; Xu, G.; Mays, E.; Ege, C.; Bielefeld, J.

    2011-08-01

    Low-k dielectrics have predominantly replaced silicon dioxide as the interlayer dielectric for interconnects in state of the art integrated circuits. In order to further reduce interconnect RC delays, additional reductions in k for these low-k materials are being pursued via the introduction of controlled levels of porosity. The main challenge for such dielectrics is the substantial reduction in elastic properties that accompanies the increased pore volume. We report on Brillouin light scattering measurements used to determine the elastic properties of these films at thicknesses well below 200 nm, which are pertinent to their introduction into present ultralarge scale integrated technology. The observation of longitudinal and transverse standing wave acoustic resonances and their transformation into traveling waves with finite in-plane wave vectors provides for a direct non-destructive measure of the principal elastic constants that characterize the elastic properties of these porous nano-scale films. The mode dispersion further confirms that for porosity levels of up to 25%, the reduction in the dielectric constant does not result in severe degradation in the Young's modulus and Poisson's ratio of the films.

  14. Compact vehicle drive module having improved thermal control

    DOEpatents

    Meyer, Andreas A.; Radosevich, Lawrence D.; Beihoff, Bruce C.; Kehl, Dennis L.; Kannenberg, Daniel G.

    2006-01-03

    An electric vehicle drive includes a thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support, which may be controlled in a closed-loop manner. Interfacing between circuits, circuit mounting structure, and the support provide for greatly enhanced cooling. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  15. Integrated optical circuit engineering V; Proceedings of the Meeting, San Diego, CA, Aug. 17-20, 1987

    NASA Astrophysics Data System (ADS)

    Mentzer, Mark A.

    Recent advances in the theoretical and practical design and applications of optoelectronic devices and optical circuits are examined in reviews and reports. Topics discussed include system and market considerations, guided-wave phenomena, waveguide devices, processing technology, lithium niobate devices, and coupling problems. Consideration is given to testing and measurement, integrated optics for fiber-optic systems, optical interconnect technology, and optical computing.

  16. Measurement and Analysis of Multiple Output Transient Propagation in BJT Analog Circuits

    NASA Astrophysics Data System (ADS)

    Roche, Nicolas J.-H.; Khachatrian, A.; Warner, J. H.; Buchner, S. P.; McMorrow, D.; Clymer, D. A.

    2016-08-01

    The propagation of Analog Single Event Transients (ASETs) to multiple outputs of Bipolar Junction Transistor (BJTs) Integrated Circuits (ICs) is reported for the first time. The results demonstrate that ASETs can appear at several outputs of a BJT amplifier or comparator as a result of a single ion or single laser pulse strike at a single physical location on the chip of a large-scale integrated BJT analog circuit. This is independent of interconnect cross-talk or charge-sharing effects. Laser experiments, together with SPICE simulations and analysis of the ASET's propagation in the s-domain are used to explain how multiple-output transients (MOTs) are generated and propagate in the device. This study demonstrates that both the charge collection associated with an ASET and the ASET's shape, commonly used to characterize the propagation of SETs in devices and systems, are unable to explain quantitatively how MOTs propagate through an integrated analog circuit. The analysis methodology adopted here involves combining the Fourier transform of the propagating signal and the current-source transfer function in the s-domain. This approach reveals the mechanisms involved in the transient signal propagation from its point of generation to one or more outputs without the signal following a continuous interconnect path.

  17. MOCVD Growth of III-V Photodetectors and Light Emitters for Integration of Optoelectronic Devices on Si substrates

    NASA Astrophysics Data System (ADS)

    Geng, Yu

    With the increase of clock speed and wiring density in integrated circuits, inter-chip and intra-chip interconnects through conventional electrical wires encounter increasing difficulties because of the large power loss and bandwidth limitation. Optical interconnects have been proposed as an alternative to copper-based interconnects and are under intense study due to their large data capacity, high data quality and low power consumption. III-V compound semiconductors offer high intrinsic electron mobility, small effective electron mass and direct bandgap, which make this material system advantageous for high-speed optoelectronic devices. The integration of III-V optoelectronic devices on Si substrates will provide the combined advantage of a high level of integration and large volume production of Si-based electronic circuitry with the superior electrical and optical performance of III-V components, paving the way to a new generation of hybrid integrated circuits. In this thesis, the direct heteroepitaxy of photodetectors (PDs) and light emitters using metal-organic chemical vapor deposition for the integration of photonic devices on Si substrates were studied. First we studied the selective-area growth of InP/GaAs on patterned Si substrates for PDs. To overcome the loading effect, a multi-temperature composite growth technique for GaAs was developed. By decreasing various defects such as dislocations and anti-phase domains, the GaAs and InP buffer layers are with good crystalline quality and the PDs show high speed and low dark current performance both at the edge and center of the large growth well. Then the growth and fabrication of GaAs/AlGaAs QW lasers were studied. Ellipsometry was used to calibrate the Al composition of AlGaAs. Thick p and n type AlGaAs with a mirrorlike surface were grown by high V/III ratio and high temperature. The GaAs/AlGaAs broad area QW laser was successfully grown and fabricated on GaAs substrate and showed a pulsed lasing result with a threshold current density of about 800 A/cm2. For the integration of lasers on Si substrate, quantum dot (QD) lasers were studied. A flow-and-stop process of TBA was used to grow InAs QDs with the in-situ monitor EpiRas. QDs with a PL wavelength of ˜1.3 mum were grown on GaAs and Si substrates. To decrease the PL degradation problem caused by the contaminations from AlGaAs, an InGaAs insertion layer was inserted in between the AlGaAs and QDs region. Microdisk and a-Si waveguide lasers are designed and fabricated.

  18. Parallel interconnect for a novel system approach to short distance high information transfer data links

    NASA Astrophysics Data System (ADS)

    Raskin, Glenn; Lebby, Michael S.; Carney, F.; Kazakia, M.; Schwartz, Daniel B.; Gaw, Craig A.

    1997-04-01

    The OPTOBUSTM family of products provides for high performance parallel interconnection utilizing optical links in a 10-bit wide bi-directional configuration. The link is architected to be 'transparent' in that it is totally asynchronous and dc coupled so that it can be treated as a perfect cable with extremely low skew and no losses. An optical link consists of two identical transceiver modules and a pair of connectorized 62.5 micrometer multi mode fiber ribbon cables. The OPTOBUSTM I link provides bi- directional functionality at 4 Gbps (400 Mbps per channel), while the OPTOBUSTM II link will offer the same capability at 8 Gbps (800 Mbps per channel). The transparent structure of the OPTOBUSTM links allow for an arbitrary data stream regardless of its structure. Both the OPTOBUSTM I and OPTOBUSTM II transceiver modules are packaged as partially populated 14 by 14 pin grid arrays (PGA) with optical receptacles on one side of the module. The modules themselves are composed of several elements; including passives, integrated circuits optoelectronic devices and optical interface units (OIUs) (which consist of polymer waveguides and a specially designed lead frame). The initial offering of the modules electrical interface utilizes differential CML. The CML line driver sinks 5 mA of current into one of two pins. When terminated with 50 ohm pull-up resistors tied to a voltage between VCC and VCC-2, the result is a differential swing of plus or minus 250 mV, capable of driving standard PECL I/Os. Future offerings of the OPTOBUSTM links will incorporate LVDS and PECL interfaces as well as CML. The integrated circuits are silicon based. For OPTOBUSTM I links, a 1.5 micrometer drawn emitter NPN bipolar process is used for the receiver and an enhanced 0.8 micrometer CMOS process for the laser driver. For OPTOBUSTM II links, a 0.8 micrometer drawn emitter NPN bipolar process is used for the receiver and the driver IC utilizes 0.8 micrometer BiCMOS technology. The OPTOBUSTM architecture uses AlGaAs vertical cavity surface emitting lasers (VCSELs) at 850 nm in conjunction with unique opto-electronic packaging concepts. Most laser based transmitter subsystems are incapable of carrying an arbitrary NRZ data stream at high data rates. The receiver subsystem utilizes a conventional GaAs PIN photo-detector. In parallel interconnect systems. The design must take into account the simultaneous switching noise from the neighboring systems. If not well controlled, the high density of the multiple interconnects can limit the sensitivity and therefore the performance of the system. The packaging approach of the VCSEL and PIN arrays allow for high bandwidths and provide the coupling mechanisms necessary to interface to the 62.5 micrometer multi mode fiber. To allow for extremely high electrical signals the OPTOBUSTM package utilizes a multilayer tape automated bonded (TAB) lead frame. The lead frame contains separate signal and ground layers. The ground layer successfully provides for a pseudo-coaxial environment (low inductance and effective signal coupling to the ground plane).

  19. Fair comparison of complexity between a multi-band CAP and DMT for data center interconnects.

    PubMed

    Wei, J L; Sanchez, C; Giacoumidis, E

    2017-10-01

    We present, to the best of our knowledge, the first known detailed analysis and fair comparison of complexity of a 56 Gb/s multi-band carrierless amplitude and phase (CAP) and discrete multi-tone (DMT) over 80 km dispersion compensation fiber-free single-mode fiber links based on intensity modulation and direct detection for data center interconnects. We show that the matched finite impulse response filters and inverse fast Fourier transform (IFFT)/FFT take the majority of the complexity of the multi-band CAP and DMT, respectively. The choice of the multi-band CAP sub-band count and the DMT IFFT/FFT size makes significant impact on the system complexity or performance, and trade-off must be considered.

  20. Joining and interconnect formation of nanowires and carbon nanotubes for nanoelectronics and nanosystems.

    PubMed

    Cui, Qingzhou; Gao, Fan; Mukherjee, Subhadeep; Gu, Zhiyong

    2009-06-01

    Interconnect formation is critical for the assembly and integration of nanocomponents to enable nanoelectronics- and nanosystems-related applications. Recent progress on joining and interconnect formation of key nanomaterials, especially nanowires and carbon nanotubes, into functional circuits and/or prototype devices is reviewed. The nanosoldering technique through nanoscale lead-free solders is discussed in more detail in this Review. Various strategies of fabricating lead-free nanosolders and the utilization of the nanosoldering technique to form functional solder joints are reviewed, and related challenges facing the nanosoldering technique are discussed. A perspective is given for using lead-free nanosolders and the nanosoldering technique for the construction of complex and/or hybrid nanoelectronics and nanosystems.

  1. Sparsely-Bonded CMOS Hybrid Imager

    NASA Technical Reports Server (NTRS)

    Sun, Chao (Inventor); Jones, Todd J. (Inventor); Nikzad, Shouleh (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor); Hancock, Bruce R. (Inventor); Dickie, Matthew R. (Inventor); Hoenk, Michael E. (Inventor); Wrigley, Christopher J. (Inventor); Pain, Bedabrata (Inventor)

    2015-01-01

    A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

  2. Silicon photonic IC embedded optical-PCB for high-speed interconnect application

    NASA Astrophysics Data System (ADS)

    Kallega, Rakshitha; Nambiar, Siddharth; Kumar, Abhai; Ranganath, Praveen; Selvaraja, Shankar Kumar

    2018-02-01

    Optical-Printed Circuit Board (PCB) is an emerging optical interconnect technology to bridge the gap between the board edge and the processing module. The technology so far has been used as a broadband transmitter using polymer waveguides in the PCB. In this paper, we report a Silicon Nitride based photonic IC embedded in the PCB along with the polymers as waveguides in the PCB. The motivation for such integration is to bring routing capability and to reduce the power loss due to broadcasting mode.

  3. Rupture testing for the quality control of electrodeposited copper interconnections in high-speed, high-density circuits

    NASA Technical Reports Server (NTRS)

    Zakraysek, Louis

    1987-01-01

    Printed Wiring Multilayer Board (PWMLB) structures for high speed, high density circuits are prone to failure due to the microcracking of electrolytic copper interconnections. The failure can occur in the foil that makes up the inner layer traces or in the plated through holes (PTH) deposit that forms the layer to layer interconnections. It is shown that there are some distinctive differences in the quality of Type E copper and that these differences can be detected before its use in a PWMLB. It is suggested that the strength of some Type E copper can be very low when the material is hot and that it is the use of this poor quality material in a PWMLB that results in PTH and inner layer microcracking. Since the PWMLB failure in question are induced by a thermal stress, and since the poorer grades of Type E materials used in these structures are susceptible to premature failure under thermal stress, the use of elevated temperature rupture and creep rupture testing is proposed as a means for screening copper foil, or its PTH equivalent, in order to eliminate the problem of Type E copper microcracking in advanced PWMLBs.

  4. Power converter having improved EMI shielding

    DOEpatents

    Beihoff, Bruce C.; Kehl, Dennis L.; Gettelfinger, Lee A.; Kaishian, Steven C.; Phillips, Mark G.; Radosevich, Lawrence D.

    2006-06-13

    EMI shielding is provided for power electronics circuits and the like via a direct-mount reference plane support and shielding structure. The thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support forms a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  5. Power converter connection configuration

    DOEpatents

    Beihoff, Bruce C.; Kehl, Dennis L.; Gettelfinger, Lee A.; Kaishian, Steven C.; Phillips, Mark G.; Radosevich, Lawrence D.

    2008-11-11

    EMI shielding is provided for power electronics circuits and the like via a direct-mount reference plane support and shielding structure. The thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support forms a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  6. Microchannel cooling of face down bonded chips

    DOEpatents

    Bernhardt, Anthony F.

    1993-01-01

    Microchannel cooling is applied to flip-chip bonded integrated circuits, in a manner which maintains the advantages of flip-chip bonds, while overcoming the difficulties encountered in cooling the chips. The technique is suited to either multichip integrated circuit boards in a plane, or to stacks of circuit boards in a three dimensional interconnect structure. Integrated circuit chips are mounted on a circuit board using flip-chip or control collapse bonds. A microchannel structure is essentially permanently coupled with the back of the chip. A coolant delivery manifold delivers coolant to the microchannel structure, and a seal consisting of a compressible elastomer is provided between the coolant delivery manifold and the microchannel structure. The integrated circuit chip and microchannel structure are connected together to form a replaceable integrated circuit module which can be easily decoupled from the coolant delivery manifold and the circuit board. The coolant supply manifolds may be disposed between the circuit boards in a stack and coupled to supplies of coolant through a side of the stack.

  7. The MSFC complementary metal oxide semiconductor (including multilevel interconnect metallization) process handbook

    NASA Technical Reports Server (NTRS)

    Bouldin, D. L.; Eastes, R. W.; Feltner, W. R.; Hollis, B. R.; Routh, D. E.

    1979-01-01

    The fabrication techniques for creation of complementary metal oxide semiconductor integrated circuits at George C. Marshall Space Flight Center are described. Examples of C-MOS integrated circuits manufactured at MSFC are presented with functional descriptions of each. Typical electrical characteristics of both p-channel metal oxide semiconductor and n-channel metal oxide semiconductor discrete devices under given conditions are provided. Procedures design, mask making, packaging, and testing are included.

  8. Semiconductor/High-Tc-Superconductor Hybrid ICs

    NASA Technical Reports Server (NTRS)

    Burns, Michael J.

    1995-01-01

    Hybrid integrated circuits (ICs) containing both Si-based semiconducting and YBa(2)Cu(3)O(7-x) superconducting circuit elements on sapphire substrates developed. Help to prevent diffusion of Cu from superconductors into semiconductors. These hybrid ICs combine superconducting and semiconducting features unavailable in superconducting or semiconducting circuitry alone. For example, complementary metal oxide/semiconductor (CMOS) readout and memory devices integrated with fast-switching Josephson-junction super-conducting logic devices and zero-resistance interconnections.

  9. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    DOEpatents

    Rogers, John A; Meitl, Matthew; Sun, Yugang; Ko, Heung Cho; Carlson, Andrew; Choi, Won Mook; Stoykovich, Mark; Jiang, Hanqing; Huang, Yonggang; Nuzzo, Ralph G; Zhu, Zhengtao; Menard, Etienne; Khang, Dahl-Young

    2014-05-20

    In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

  10. Controlled buckling structures in semiconductor interconnects and nanomembranes for stretchable electronics

    DOEpatents

    Rogers, John A [Champaign, IL; Meitl, Matthew [Raleigh, NC; Sun, Yugang [Naperville, IL; Ko, Heung Cho [Urbana, IL; Carlson, Andrew [Urbana, IL; Choi, Won Mook [Champaign, IL; Stoykovich, Mark [Dover, NH; Jiang, Hanqing [Urbana, IL; Huang, Yonggang [Glencoe, IL; Nuzzo, Ralph G [Champaign, IL; Lee, Keon Jae [Tokyo, JP; Zhu, Zhengtao [Rapid City, SD; Menard, Etienne [Durham, NC; Khang, Dahl-Young [Seoul, KR; Kan, Seong Jun [Daejeon, KR; Ahn, Jong Hyun [Suwon, KR; Kim, Hoon-sik [Champaign, IL

    2012-07-10

    In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

  11. Modular power converter having fluid cooled support

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

    2005-09-06

    A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  12. Modular power converter having fluid cooled support

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

    2005-12-06

    A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  13. GaAs VLSI for aerospace electronics

    NASA Technical Reports Server (NTRS)

    Larue, G.; Chan, P.

    1990-01-01

    Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

  14. Phase Two of the Array Automated Assembly Task for the Low Cost Solar Array Project

    NASA Technical Reports Server (NTRS)

    Campbell, R. B.; Page, D. J.; Rai-Choudhury, P.; Seman, E. J.; Hanes, M. H.; Rohatgi, A.; Davis, J. R.

    1979-01-01

    Various top contact metal systems were studied. Only Ti Pd Cu approaches baseline (Ti Pd Ag) quality, but this system shows a lack of long term stability. Aluminum back surface field structures were fabricated and thicknesses of p superscript + material of up to 7.0 microns were achieved with open circuit voltages of 0.59V. A general purpose ultrasonic welder was purchased and tests using various metal foils are under way. During fabrication of the demonstration module, several cells became cracked. Due to redundancy of interconnections, the module was not open circuited but the efficiency was reduced to 8.8%. The broken cell was interconnected with a strap across the back and the efficiency was increased to 11.5%. A cost analysis was made and the results indicate a selling price of $0.56/watt peak (in 1986 with 1975 dollars).

  15. Machine Vision Within The Framework Of Collective Neural Assemblies

    NASA Astrophysics Data System (ADS)

    Gupta, Madan M.; Knopf, George K.

    1990-03-01

    The proposed mechanism for designing a robust machine vision system is based on the dynamic activity generated by the various neural populations embedded in nervous tissue. It is postulated that a hierarchy of anatomically distinct tissue regions are involved in visual sensory information processing. Each region may be represented as a planar sheet of densely interconnected neural circuits. Spatially localized aggregates of these circuits represent collective neural assemblies. Four dynamically coupled neural populations are assumed to exist within each assembly. In this paper we present a state-variable model for a tissue sheet derived from empirical studies of population dynamics. Each population is modelled as a nonlinear second-order system. It is possible to emulate certain observed physiological and psychophysiological phenomena of biological vision by properly programming the interconnective gains . Important early visual phenomena such as temporal and spatial noise insensitivity, contrast sensitivity and edge enhancement will be discussed for a one-dimensional tissue model.

  16. 3-D Packaging: A Technology Review

    NASA Technical Reports Server (NTRS)

    Strickland, Mark; Johnson, R. Wayne; Gerke, David

    2005-01-01

    Traditional electronics are assembled as a planar arrangement of components on a printed circuit board (PCB) or other type of substrate. These planar assemblies may then be plugged into a motherboard or card cage creating a volume of electronics. This architecture is common in many military and space electronic systems as well as large computer and telecommunications systems and industrial electronics. The individual PCB assemblies can be replaced if defective or for system upgrade. Some applications are constrained by the volume or the shape of the system and are not compatible with the motherboard or card cage architecture. Examples include missiles, camcorders, and digital cameras. In these systems, planar rigid-flex substrates are folded to create complex 3-D shapes. The flex circuit serves the role of motherboard, providing interconnection between the rigid boards. An example of a planar rigid - flex assembly prior to folding is shown. In both architectures, the interconnection is effectively 2-D.

  17. Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

    NASA Astrophysics Data System (ADS)

    Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

    2017-07-01

    Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

  18. System architecture of a gallium arsenide one-gigahertz digital IC tester

    NASA Technical Reports Server (NTRS)

    Fouts, Douglas J.; Johnson, John M.; Butner, Steven E.; Long, Stephen I.

    1987-01-01

    The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.

  19. A fast low-power optical memory based on coupled micro-ring lasers

    NASA Astrophysics Data System (ADS)

    Hill, Martin T.; Dorren, Harmen J. S.; de Vries, Tjibbe; Leijtens, Xaveer J. M.; den Besten, Jan Hendrik; Smalbrugge, Barry; Oei, Yok-Siang; Binsma, Hans; Khoe, Giok-Djan; Smit, Meint K.

    2004-11-01

    The increasing speed of fibre-optic-based telecommunications has focused attention on high-speed optical processing of digital information. Complex optical processing requires a high-density, high-speed, low-power optical memory that can be integrated with planar semiconductor technology for buffering of decisions and telecommunication data. Recently, ring lasers with extremely small size and low operating power have been made, and we demonstrate here a memory element constructed by interconnecting these microscopic lasers. Our device occupies an area of 18 × 40µm2 on an InP/InGaAsP photonic integrated circuit, and switches within 20ps with 5.5fJ optical switching energy. Simulations show that the element has the potential for much smaller dimensions and switching times. Large numbers of such memory elements can be densely integrated and interconnected on a photonic integrated circuit: fast digital optical information processing systems employing large-scale integration should now be viable.

  20. Vehicle drive module having improved terminal design

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Phillips, Mark G.; Kehl, Dennis L.; Kaishian, Steven C.; Kannenberg, Daniel G.

    2006-04-25

    A terminal structure for vehicle drive power electronics circuits reduces the need for a DC bus and thereby the incidence of parasitic inductance. The structure is secured to a support that may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as by direct contact between the terminal assembly and AC and DC circuit components. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  1. Power converter having improved terminal structure

    DOEpatents

    Radosevich, Lawrence D.; Kannenberg, Daniel G.; Phillips, Mark G.; Kaishian, Steven C.

    2007-03-06

    A terminal structure for power electronics circuits reduces the need for a DC bus and thereby the incidence of parasitic inductance. The structure is secured to a support that may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as by direct contact between the terminal assembly and AC and DC circuit components. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  2. Self-similar and fractal design for stretchable electronics

    DOEpatents

    Rogers, John A.; Fan, Jonathan; Yeo, Woon-Hong; Su, Yewang; Huang, Yonggang; Zhang, Yihui

    2017-04-04

    The present invention provides electronic circuits, devices and device components including one or more stretchable components, such as stretchable electrical interconnects, electrodes and/or semiconductor components. Stretchability of some of the present systems is achieved via a materials level integration of stretchable metallic or semiconducting structures with soft, elastomeric materials in a configuration allowing for elastic deformations to occur in a repeatable and well-defined way. The stretchable device geometries and hard-soft materials integration approaches of the invention provide a combination of advance electronic function and compliant mechanics supporting a broad range of device applications including sensing, actuation, power storage and communications.

  3. Process for 3D chip stacking

    DOEpatents

    Malba, V.

    1998-11-10

    A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

  4. Process for 3D chip stacking

    DOEpatents

    Malba, Vincent

    1998-01-01

    A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

  5. Chemical sensors fabricated by a photonic integrated circuit foundry

    NASA Astrophysics Data System (ADS)

    Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

    2018-02-01

    We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

  6. Advanced packaging for Integrated Micro-Instruments

    NASA Technical Reports Server (NTRS)

    Lyke, James L.

    1995-01-01

    The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

  7. Rapid Selective Annealing of Cu Thin Films on Si Using Microwaves

    NASA Technical Reports Server (NTRS)

    Brain, R. A.; Atwater, H. A.; Watson, T. J.; Barmatz, M.

    1994-01-01

    A major goal of the semiconductor indurstry is to lower the processing temperatures needed for interconnects in silicon integrated circuits. Typical rapid thermal annealing processes heat the film as well as the substrate, creating device problems.

  8. Laser microprocessing technologies for automotive, flexible electronics, and solar energy sectors

    NASA Astrophysics Data System (ADS)

    Nikumb, Suwas; Bathe, Ravi; Knopf, George K.

    2014-10-01

    Laser microprocessing technologies offer an important tool to fulfill the needs of many industrial sectors. In particular, there is growing interest in applications of these processes in the manufacturing areas such as automotive parts fabrication, printable electronics and solar energy panels. The technology is primarily driven by our understanding of the fundamental laser-material interaction, process control strategies and the advancement of significant fabrication experience over the past few years. The wide-ranging operating parameters available with respect to power, pulse width variation, beam quality, higher repetition rates as well as precise control of the energy deposition through programmable pulse shaping technologies, enables pre-defined material removal, selective scribing of individual layer within a stacked multi-layer thin film structure, texturing of material surfaces as well as precise introduction of heat into the material to monitor its characteristic properties are a few examples. In this research, results in the area of laser surface texturing of metals for added hydrodynamic lubricity to reduce friction, processing of ink-jet printed graphene oxide for flexible printed electronic circuit fabrication and scribing of multi-layer thin films for the development of photovoltaic CuInGaSe2 (CIGS) interconnects for solar panel devices will be discussed.

  9. Self-assembled three dimensional network designs for soft electronics

    PubMed Central

    Jang, Kyung-In; Li, Kan; Chung, Ha Uk; Xu, Sheng; Jung, Han Na; Yang, Yiyuan; Kwak, Jean Won; Jung, Han Hee; Song, Juwon; Yang, Ce; Wang, Ao; Liu, Zhuangjian; Lee, Jong Yoon; Kim, Bong Hoon; Kim, Jae-Hwan; Lee, Jungyup; Yu, Yongjoon; Kim, Bum Jun; Jang, Hokyung; Yu, Ki Jun; Kim, Jeonghyun; Lee, Jung Woo; Jeong, Jae-Woong; Song, Young Min; Huang, Yonggang; Zhang, Yihui; Rogers, John A.

    2017-01-01

    Low modulus, compliant systems of sensors, circuits and radios designed to intimately interface with the soft tissues of the human body are of growing interest, due to their emerging applications in continuous, clinical-quality health monitors and advanced, bioelectronic therapeutics. Although recent research establishes various materials and mechanics concepts for such technologies, all existing approaches involve simple, two-dimensional (2D) layouts in the constituent micro-components and interconnects. Here we introduce concepts in three-dimensional (3D) architectures that bypass important engineering constraints and performance limitations set by traditional, 2D designs. Specifically, open-mesh, 3D interconnect networks of helical microcoils formed by deterministic compressive buckling establish the basis for systems that can offer exceptional low modulus, elastic mechanics, in compact geometries, with active components and sophisticated levels of functionality. Coupled mechanical and electrical design approaches enable layout optimization, assembly processes and encapsulation schemes to yield 3D configurations that satisfy requirements in demanding, complex systems, such as wireless, skin-compatible electronic sensors. PMID:28635956

  10. Technology achievements and projections for communication satellites of the future

    NASA Technical Reports Server (NTRS)

    Bagwell, J. W.

    1986-01-01

    Multibeam systems of the future using monolithic microwave integrated circuits to provide phase control and power gain are contrasted with discrete microwave power amplifiers from 10 to 75 W and their associated waveguide feeds, phase shifters and power splitters. Challenging new enabling technology areas include advanced electrooptical control and signal feeds. Large scale MMIC's will be used incorporating on chip control interfaces, latching, and phase and amplitude control with power levels of a few watts each. Beam forming algorithms for 80 to 90 deg. wide angle scanning and precise beam forming under wide ranging environments will be required. Satelllite systems using these dynamically reconfigured multibeam antenna systems will demand greater degrees of beam interconnectivity. Multiband and multiservice users will be interconnected through the same space platform. Monolithic switching arrays operating over a wide range of RF and IF frequencies are contrasted with current IF switch technology implemented discretely. Size, weight, and performance improvements by an order of magnitude are projected.

  11. Self-assembled three dimensional network designs for soft electronics

    NASA Astrophysics Data System (ADS)

    Jang, Kyung-In; Li, Kan; Chung, Ha Uk; Xu, Sheng; Jung, Han Na; Yang, Yiyuan; Kwak, Jean Won; Jung, Han Hee; Song, Juwon; Yang, Ce; Wang, Ao; Liu, Zhuangjian; Lee, Jong Yoon; Kim, Bong Hoon; Kim, Jae-Hwan; Lee, Jungyup; Yu, Yongjoon; Kim, Bum Jun; Jang, Hokyung; Yu, Ki Jun; Kim, Jeonghyun; Lee, Jung Woo; Jeong, Jae-Woong; Song, Young Min; Huang, Yonggang; Zhang, Yihui; Rogers, John A.

    2017-06-01

    Low modulus, compliant systems of sensors, circuits and radios designed to intimately interface with the soft tissues of the human body are of growing interest, due to their emerging applications in continuous, clinical-quality health monitors and advanced, bioelectronic therapeutics. Although recent research establishes various materials and mechanics concepts for such technologies, all existing approaches involve simple, two-dimensional (2D) layouts in the constituent micro-components and interconnects. Here we introduce concepts in three-dimensional (3D) architectures that bypass important engineering constraints and performance limitations set by traditional, 2D designs. Specifically, open-mesh, 3D interconnect networks of helical microcoils formed by deterministic compressive buckling establish the basis for systems that can offer exceptional low modulus, elastic mechanics, in compact geometries, with active components and sophisticated levels of functionality. Coupled mechanical and electrical design approaches enable layout optimization, assembly processes and encapsulation schemes to yield 3D configurations that satisfy requirements in demanding, complex systems, such as wireless, skin-compatible electronic sensors.

  12. Board-to-Board Free-Space Optical Interconnections Passing through Boards for a Bookshelf-Assembled Terabit-Per-Second-Class ATM Switch.

    PubMed

    Hirabayashi, K; Yamamoto, T; Matsuo, S; Hino, S

    1998-05-10

    We propose free-space optical interconnections for a bookshelf-assembled terabit-per-second-class ATM switch. Thousands of arrayed optical beams, each having a rate of a few gigabits per second, propagate vertically to printed circuit boards, passing through some boards, and are connected to arbitrary transmitters and receivers on boards by polarization controllers and prism arrays. We describe a preliminary experiment using a 1-mm-pitch 2 x 2 beam-collimator array that uses vertical-cavity surface-emitting laser diodes. These optical interconnections can be made quite stable in terms of mechanical shock and temperature fluctuation by the attachment of reinforcing frames to the boards and use of an autoalignment system.

  13. Computationally efficient modeling and simulation of large scale systems

    NASA Technical Reports Server (NTRS)

    Jain, Jitesh (Inventor); Cauley, Stephen F. (Inventor); Li, Hong (Inventor); Koh, Cheng-Kok (Inventor); Balakrishnan, Venkataramanan (Inventor)

    2010-01-01

    A method of simulating operation of a VLSI interconnect structure having capacitive and inductive coupling between nodes thereof. A matrix X and a matrix Y containing different combinations of passive circuit element values for the interconnect structure are obtained where the element values for each matrix include inductance L and inverse capacitance P. An adjacency matrix A associated with the interconnect structure is obtained. Numerical integration is used to solve first and second equations, each including as a factor the product of the inverse matrix X.sup.1 and at least one other matrix, with first equation including X.sup.1Y, X.sup.1A, and X.sup.1P, and the second equation including X.sup.1A and X.sup.1P.

  14. Ultralow-k nanoporous organosilicate dielectric films imprinted with dendritic spheres.

    PubMed

    Lee, Byeongdu; Park, Young-Hee; Hwang, Yong-Taek; Oh, Weontae; Yoon, Jinhwan; Ree, Moonhor

    2005-02-01

    Integrated circuits that have improved functionality and speed in a smaller package and that consume less power are desired by the microelectronics industry as well as by end users, to increase device performance and reduce costs. The fabrication of high-performance integrated circuits requires the availability of materials with low or ultralow dielectric constant (low-k: k

  15. Solar cell circuit and method for manufacturing solar cells

    NASA Technical Reports Server (NTRS)

    Mardesich, Nick (Inventor)

    2010-01-01

    The invention is a novel manufacturing method for making multi-junction solar cell circuits that addresses current problems associated with such circuits by allowing the formation of integral diodes in the cells and allows for a large number of circuits to readily be placed on a single silicon wafer substrate. The standard Ge wafer used as the base for multi-junction solar cells is replaced with a thinner layer of Ge or a II-V semiconductor material on a silicon/silicon dioxide substrate. This allows high-voltage cells with multiple multi-junction circuits to be manufactured on a single wafer, resulting in less array assembly mass and simplified power management.

  16. Optical link by using optical wiring method for reducing EMI

    NASA Astrophysics Data System (ADS)

    Cho, In-Kui; Kwon, Jong-Hwa; Choi, Sung-Woong; Bondarik, Alexander; Yun, Je-Hoon; Kim, Chang-Joo; Ahn, Seung-Beom; Jeong, Myung-Yung; Park, Hyo Hoon

    2008-12-01

    A practical optical link system was prepared with a transmitter (Tx) and receiver (Rx) for reducing EMI (electromagnetic interference). The optical TRx module consisted of a metal optical bench, a module printed circuit board (PCB), a driver/receiver IC, a VCSEL/PD array, and an optical link block composed of plastic optical fiber (POF). For the optical interconnection between the light-sources and detectors, an optical wiring method has been proposed to enable easy assembly. The key benefit of fiber optic link is the absence of electromagnetic interference (EMI) noise creation and susceptibility. This paper provides a method for optical interconnection between an optical Tx and an optical Rx, comprising the following steps: (i) forming a light source device, an optical detection device, and an optical transmission unit on a substrate (metal optical bench (MOB)); (ii) preparing a flexible optical transmission-connection medium (optical wiring link) to optically connect the light source device formed on the substrate with the optical detection device; and (iii) directly connecting one end of the surface-finished optical transmission connection medium with the light source device and the other end with the optical detection device. Electronic interconnections have uniquely electronic problems such as EMI, shorting, and ground loops. Since these problems only arise during transduction (electronics-to-optics or opticsto- electronics), the purely optical part and optical link(interconnection) is free of these problems. 1 An optical link system constructed with TRx modules was fabricated and the optical characteristics about data links and EMI levels were measured. The results clearly demonstrate that the use of an optical wiring method can provide robust and cost-effective assembly for reducing EMI of inter-chip interconnect. We successfully achieved a 4.5 Gb/s data transmission rate without EMI problems.

  17. High-resolution inkjet printing of all-polymer transistor circuits.

    PubMed

    Sirringhaus, H; Kawase, T; Friend, R H; Shimoda, T; Inbasekaran, M; Wu, W; Woo, E P

    2000-12-15

    Direct printing of functional electronic materials may provide a new route to low-cost fabrication of integrated circuits. However, to be useful it must allow continuous manufacturing of all circuit components by successive solution deposition and printing steps in the same environment. We demonstrate direct inkjet printing of complete transistor circuits, including via-hole interconnections based on solution-processed polymer conductors, insulators, and self-organizing semiconductors. We show that the use of substrate surface energy patterning to direct the flow of water-based conducting polymer inkjet droplets enables high-resolution definition of practical channel lengths of 5 micrometers. High mobilities of 0.02 square centimeters per volt second and on-off current switching ratios of 10(5) were achieved.

  18. Vehicle drive module having improved EMI shielding

    DOEpatents

    Beihoff, Bruce C.; Kehl, Dennis L.; Gettelfinger, Lee A.; Kaishian, Steven C.; Phillips, Mark G.; Radosevich, Lawrence D.

    2006-11-28

    EMI shielding in an electric vehicle drive is provided for power electronics circuits and the like via a direct-mount reference plane support and shielding structure. The thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support forms a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  19. Interconnection Assessment Methodology and Cost Benefit Analysis for High-Penetration PV Deployment in the Arizona Public Service System

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Baggu, Murali; Giraldez, Julieta; Harris, Tom

    In an effort to better understand the impacts of high penetrations of photovoltaic (PV) generators on distribution systems, Arizona Public Service and its partners completed a multi-year project to develop the tools and knowledge base needed to safely and reliably integrate high penetrations of utility- and residential-scale PV. Building upon the APS Community Power Project-Flagstaff Pilot, this project investigates the impact of PV on a representative feeder in northeast Flagstaff. To quantify and catalog the effects of the estimated 1.3 MW of PV that will be installed on the feeder (both smaller units at homes and large, centrally located systems),more » high-speed weather and electrical data acquisition systems and digital 'smart' meters were designed and installed to facilitate monitoring and to build and validate comprehensive, high-resolution models of the distribution system. These models are being developed to analyze the impacts of PV on distribution circuit protection systems (including coordination and anti-islanding), predict voltage regulation and phase balance issues, and develop volt/VAr control schemes. This paper continues from a paper presented at the 2014 IEEE PVSC conference that described feeder model evaluation and high penetration advanced scenario analysis, specifically feeder reconfiguration. This paper presents results from Phase 5 of the project. Specifically, the paper discusses tool automation; interconnection assessment methodology and cost benefit analysis.« less

  20. High density circuit technology, part 1

    NASA Technical Reports Server (NTRS)

    Wade, T. E.

    1982-01-01

    The metal (or dielectric) lift-off processes used in the semiconductor industry to fabricate high density very large scale integration (VLSI) systems were reviewed. The lift-off process consists of depositing the light-sensitive material onto the wafer and patterning first in such a manner as to form a stencil for the interconnection material. Then the interconnection layer is deposited and unwanted areas are lifted off by removing the underlying stencil. Several of these lift-off techniques were examined experimentally. The use of an auxiliary layer of polyimide to form a lift-off stencil offers considerable promise.

  1. Metallic Nanowire Interconnections for Integrated Circuit Fabrication

    NASA Technical Reports Server (NTRS)

    Ng, Hou Tee (Inventor); Li, Jun (Inventor); Meyyappan, Meyya (Inventor)

    2007-01-01

    A method for fabricating an electrical interconnect between two or more electrical components. A conductive layer is provided on a substarte and a thin, patterned catalyst array is deposited on an exposed surface of the conductive layer. A gas or vapor of a metallic precursor of a metal nanowire (MeNW) is provided around the catalyst array, and MeNWs grow between the conductive layer and the catalyst array. The catalyst array and a portion of each of the MeNWs are removed to provide exposed ends of the MeNWs.

  2. SOFC seal and cell thermal management

    DOEpatents

    Potnis, Shailesh Vijay [Neenah, WI; Rehg, Timothy Joseph [Huntington Beach, CA

    2011-05-17

    The solid oxide fuel cell module includes a manifold, a plate, a cathode electrode, a fuel cell and an anode electrode. The manifold includes an air or oxygen inlet in communication with divergent passages above the periphery of the cell which combine to flow the air or oxygen radially or inwardly for reception in the center of the cathode flow field. The latter has interconnects providing circuitous cooling passages in a generally radial outward direction cooling the fuel cell and which interconnects are formed of different thermal conductivity materials for a preferential cooling.

  3. Implementation of Basic and Universal Gates In a single Circuit Based On Quantum-dot Cellular Automata Using Multi-Layer Crossbar Wire

    NASA Astrophysics Data System (ADS)

    Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha; Nandi, Supratim

    2017-08-01

    Quantum-dot Cellular Automata (QCA) is one of the most substitutes developing nanotechnologies for electronic circuits, as a result of lower force utilization, higher speed and smaller size in correlation with CMOS innovation. The essential devices, a Quantum-dot cell can be utilized to logic gates and wires. As it is the key building block on nanotechnology circuits. By applying simple gates, the hardware requirements for a QCA circuit can be decreased and circuits can be less complex as far as level, delay and cell check. This article exhibits an unobtrusive methodology for actualizing novel upgraded simple and universal gates, which can be connected to outline numerous variations of complex QCA circuits. Proposed gates are straightforward in structure and capable as far as implementing any digital circuits. The main aim is to build all basic and universal gates in a simple circuit with and without crossbar-wire. Simulation results and physical relations affirm its handiness in actualizing each advanced circuit.

  4. Reliability analysis of magnetic logic interconnect wire subjected to magnet edge imperfections

    NASA Astrophysics Data System (ADS)

    Zhang, Bin; Yang, Xiaokuo; Liu, Jiahao; Li, Weiwei; Xu, Jie

    2018-02-01

    Nanomagnet logic (NML) devices have been proposed as one of the best candidates for the next generation of integrated circuits thanks to its substantial advantages of nonvolatility, radiation hardening and potentially low power. In this article, errors of nanomagnetic interconnect wire subjected to magnet edge imperfections have been evaluated for the purpose of reliable logic propagation. The missing corner defects of nanomagnet in the wire are modeled with a triangle, and the interconnect fabricated with various magnetic materials is thoroughly investigated by micromagnetic simulations under different corner defect amplitudes and device spacings. The results show that as the defect amplitude increases, the success rate of logic propagation in the interconnect decreases. More results show that from the interconnect wire fabricated with materials, iron demonstrates the best defect tolerance ability among three representative and frequently used NML materials, also logic transmission errors can be mitigated by adjusting spacing between nanomagnets. These findings can provide key technical guides for designing reliable interconnects. Project supported by the National Natural Science Foundation of China (No. 61302022) and the Scientific Research Foundation for Postdoctor of Air Force Engineering University (Nos. 2015BSKYQD03, 2016KYMZ06).

  5. Issues of nanoelectronics: a possible roadmap.

    PubMed

    Wang, Kang L

    2002-01-01

    In this review, we will discuss a possible roadmap in scaling a nanoelectronic device from today's CMOS technology to the ultimate limit when the device fails. In other words, at the limit, CMOS will have a severe short channel effect, significant power dissipation in its quiescent (standby) state, and problems related to other essential characteristics. Efforts to use structures such as the double gate, vertical surround gate, and SOI to improve the gate control have continually been made. Other types of structures using SiGe source/drain, asymmetric Schottky source/drain, and the like will be investigated as viable structures to achieve ultimate CMOS. In reaching its scaling limit, tunneling will be an issue for CMOS. The tunneling current through the gate oxide and between the source and drain will limit the device operation. When tunneling becomes significant, circuits may incorporate tunneling devices with CMOS to further increase the functionality per device count. We will discuss both the top-down and bottom-up approaches in attaining the nanometer scale and eventually the atomic scale. Self-assembly is used as a bottom-up approach. The state of the art is reviewed, and the challenges of the multiple-step processing in using the self-assembly approach are outlined. Another facet of the scaling trend is to decrease the number of electrons in devices, ultimately leading to single electrons. If the size of a single-electron device is scaled in such a way that the Coulomb self-energy is higher than the thermal energy (at room temperature), a single-electron device will be able to operate at room temperature. In principle, the speed of the device will be fast as long as the capacitance of the load is also scaled accordingly. The single-electron device will have a small drive current, and thus the load capacitance, including those of interconnects and fanouts, must be small to achieve a reasonable speed. However, because the increase in the density (and/or functionality) of integrated circuits is the principal driver, the wiring or interconnects will increase and become the bottleneck for the design of future high-density and high-functionality circuits, particularly for single-electron devices. Furthermore, the massive interconnects needed in the architecture used today will result in an increase in load capacitance. Thus for single-electron device circuits, it is critical to have minimal interconnect loads. And new types of architectures with minimal numbers of global interconnects will be needed. Cellular automata, which need only nearest-neighbor interconnects, are discussed as a plausible example. Other architectures such as neural networks are also possible. Examples of signal processing using cellular automata are discussed. Quantum computing and information processing are based on quantum mechanical descriptions of individual particles correlated among each other. A quantum bit or qubit is described as a linear superposition of the wave functions of a two-state system, for example, the spin of a particle. With the interaction of two qubits, they are connected in a "wireless fashion" using wave functions via quantum mechanical interaction, referred to as entanglement. The interconnection by the nonlocality of wave functions affords a massive parallel nature for computing or so-called quantum parallelism. We will describe the potential and solid-state implementations of quantum computing and information, using electron spin and/or nuclear spin in Si and Ge. Group IV elements have a long coherent time and other advantages. The example of using SiGe for g factor engineering will be described.

  6. Ultra-thin silicon (UTSi) on insulator CMOS transceiver and time-division multiplexed switch chips for smart pixel integration

    NASA Astrophysics Data System (ADS)

    Zhang, Liping; Sawchuk, Alexander A.

    2001-12-01

    We describe the design, fabrication and functionality of two different 0.5 micron CMOS optoelectronic integrated circuit (OEIC) chips based on the Peregrine Semiconductor Ultra-Thin Silicon on insulator technology. The Peregrine UTSi silicon- on-sapphire (SOS) technology is a member of the silicon-on- insulator (SOI) family. The low-loss synthetic sapphire substrate is optically transparent and has good thermal conductivity and coefficient of thermal expansion properties, which meet the requirements for flip-chip bonding of VCSELs and other optoelectronic input-output components. One chip contains transceiver and network components, including four channel high-speed CMOS transceiver modules, pseudo-random bit stream (PRBS) generators, a voltage controlled oscillator (VCO) and other test circuits. The transceiver chips can operate in both self-testing mode and networking mode. An on- chip clock and true-single-phase-clock (TSPC) D-flip-flop have been designed to generate a PRBS at over 2.5 Gb/s for the high-speed transceiver arrays to operate in self-testing mode. In the networking mode, an even number of transceiver chips forms a ring network through free-space or fiber ribbon interconnections. The second chip contains four channel optical time-division multiplex (TDM) switches, optical transceiver arrays, an active pixel detector and additional test devices. The eventual applications of these chips will require monolithic OEICs with integrated optical input and output. After fabrication and testing, the CMOS transceiver array dies will be packaged with 850 nm vertical cavity surface emitting lasers (VCSELs), and metal-semiconductor- metal (MSM) or GaAs p-i-n detector die arrays to achieve high- speed optical interconnections. The hybrid technique could be either wire bonding or flip-chip bonding of the CMOS SOS smart-pixel arrays with arrays of VCSELs and photodetectors onto an optoelectronic chip carrier as a multi-chip module (MCM).

  7. 49 CFR 236.750 - Interlocking, automatic.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... 49 Transportation 4 2010-10-01 2010-10-01 false Interlocking, automatic. 236.750 Section 236.750 Transportation Other Regulations Relating to Transportation (Continued) FEDERAL RAILROAD ADMINISTRATION... manually, and which are so interconnected by means of electric circuits that their movements must succeed...

  8. Development of a Converter-Based Transmission Line Emulator with Three-Phase Short-Circuit Fault Emulation Capability

    DOE PAGES

    Zhang, Shuoting; Liu, Bo; Zheng, Sheng; ...

    2018-01-01

    A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage source converter (VSC)-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. Here, this paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault statemore » and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.« less

  9. Development of a Converter-Based Transmission Line Emulator with Three-Phase Short-Circuit Fault Emulation Capability

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Zhang, Shuoting; Liu, Bo; Zheng, Sheng

    A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage source converter (VSC)-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. Here, this paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault statemore » and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.« less

  10. Multi-resonant electromagnetic shunt in base isolation for vibration damping and energy harvesting

    NASA Astrophysics Data System (ADS)

    Pei, Yalu; Liu, Yilun; Zuo, Lei

    2018-06-01

    This paper investigates multi-resonant electromagnetic shunts applied to base isolation for dual-function vibration damping and energy harvesting. Two multi-mode shunt circuit configurations, namely parallel and series, are proposed and optimized based on the H2 criteria. The root-mean-square (RMS) value of the relative displacement between the base and the primary structure is minimized. Practically, this will improve the safety of base-isolated buildings subjected the broad bandwidth ground acceleration. Case studies of a base-isolated building are conducted in both the frequency and time domains to investigate the effectiveness of multi-resonant electromagnetic shunts under recorded earthquake signals. It shows that both multi-mode shunt circuits outperform traditional single mode shunt circuits by suppressing the first and the second vibration modes simultaneously. Moreover, for the same stiffness ratio, the parallel shunt circuit is more effective at harvesting energy and suppressing vibration, and can more robustly handle parameter mistuning than the series shunt circuit. Furthermore, this paper discusses experimental validation of the effectiveness of multi-resonant electromagnetic shunts for vibration damping and energy harvesting on a scaled-down base isolation system.

  11. Test Structures For Bumpy Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  12. Electrical power converter method and system employing multiple output converters

    DOEpatents

    Beihoff, Bruce C [Wauwatosa, WI; Radosevich, Lawrence D [Muskego, WI; Meyer, Andreas A [Richmond Heights, OH; Gollhardt, Neil [Fox Point, WI; Kannenberg, Daniel G [Waukesha, WI

    2007-05-01

    A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  13. Fluid cooled vehicle drive module

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

    2005-11-15

    An electric vehicle drive includes a support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EM/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  14. Electrical power converter method and system employing multiple-output converters

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Meyer, Andreas A.; Gollhardt, Neil; Kannenberg, Daniel G.

    2006-03-21

    A support may receive one or more power electronic circuits. The support may aid in removing heat from the circuits through fluid circulating through the support. The support, in conjunction with other packaging features may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  15. Seismic Hazard Analysis on a Complex, Interconnected Fault Network

    NASA Astrophysics Data System (ADS)

    Page, M. T.; Field, E. H.; Milner, K. R.

    2017-12-01

    In California, seismic hazard models have evolved from simple, segmented prescriptive models to much more complex representations of multi-fault and multi-segment earthquakes on an interconnected fault network. During the development of the 3rd Uniform California Earthquake Rupture Forecast (UCERF3), the prevalence of multi-fault ruptures in the modeling was controversial. Yet recent earthquakes, for example, the Kaikora earthquake - as well as new research on the potential of multi-fault ruptures (e.g., Nissen et al., 2016; Sahakian et al. 2017) - have validated this approach. For large crustal earthquakes, multi-fault ruptures may be the norm rather than the exception. As datasets improve and we can view the rupture process at a finer scale, the interconnected, fractal nature of faults is revealed even by individual earthquakes. What is the proper way to model earthquakes on a fractal fault network? We show multiple lines of evidence that connectivity even in modern models such as UCERF3 may be underestimated, although clustering in UCERF3 mitigates some modeling simplifications. We need a methodology that can be applied equally well where the fault network is well-mapped and where it is not - an extendable methodology that allows us to "fill in" gaps in the fault network and in our knowledge.

  16. Fabrication of Circuits on Flexible Substrates Using Conductive SU-8 for Sensing Applications

    PubMed Central

    Gerardo, Carlos D.; Cretu, Edmond; Rohling, Robert

    2017-01-01

    This article describes a new low-cost rapid microfabrication technology for high-density interconnects and passive devices on flexible substrates for sensing applications. Silver nanoparticles with an average size of 80 nm were used to create a conductive SU-8 mixture with a concentration of wt 25%. The patterned structures after hard baking have a sheet resistance of 11.17 Ω/☐. This conductive SU-8 was used to pattern planar inductors, capacitors and interconnection lines on flexible Kapton film. The conductive SU-8 structures were used as a seed layer for a subsequent electroplating process to increase the conductivity of the devices. Examples of inductors, resistor-capacitor (RC) and inductor-capacitor (LC) circuits, interconnection lines and a near-field communication (NFC) antenna are presented as a demonstration. As an example of high-resolution miniaturization, we fabricated microinductors having line widths of 5 μm. Mechanical bending tests were successful down to a 5 mm radius. To the best of the authors’ knowledge, this is the first report of conductive SU-8 used to fabricate such planar devices and the first on flexible substrates. This is a proof of concept that this fabrication approach can be used as an alternative for microfabrication of planar passive devices on flexible substrates. PMID:28629134

  17. Integration of micro-/nano-/quantum-scale photonic devices: scientific and technological considerations

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, Seung-Gol; O, Beom Hoan; Park, Se Geun

    2004-08-01

    Scientific and technological issues and considerations regarding the integration of miniaturized microphotonic devices, circuits and systems in micron, submicron, and quantum scale, are presented. First, we examine the issues regarding the miniaturization of photonic devices including the size effect, proximity effect, energy confinement effect, microcavity effect, optical and quantum interference effect, high field effect, nonlinear effect, noise effect, quantum optical effect, and chaotic effect. Secondly, we examine the issues regarding the interconnection including the optical alignment, minimizing the interconnection losses, and maintaining optical modes. Thirdly, we address the issues regarding the two-dimensional or three-dimensional integration either in a hybrid format or in a monolithic format between active devices and passive devices of varying functions. We find that the concept of optical printed circuit board (O-PCB) that we propose is highly attractive as a platform for micro/nano/quantum-scale photonic integration. We examine the technological issues to be addressed in the process of fabrication, characterization, and packaging for actual implementation of the miniaturization, interconnection and integration. Devices that we have used for our study include: mode conversion schemes, micro-ring and micro-racetrack resonator devices, multimode interference devices, lasers, vertical cavity surface emitting microlasers, and their arrays. Future prospects are also discussed.

  18. Board-to-board optical interconnection using novel optical plug and slot

    NASA Astrophysics Data System (ADS)

    Cho, In K.; Yoon, Keun Byoung; Ahn, Seong H.; Kim, Jin Tae; Lee, Woo Jin; Shin, Kyoung Up; Heo, Young Un; Park, Hyo Hoon

    2004-10-01

    A novel optical PCB with transmitter/receiver system boards and optical bakcplane was prepared, which is board-to-board interconnection by optical plug and slot. We report an 8Gb/s PRBS NRZ data transmission between transmitter system board and optical backplane embedded multimode polymeric waveguide arrays. The basic concept of ETRI's optical PCB is as follows; 1) Metal optical bench is integrated with optoelectronic devices, driver and receiver circuits, polymeric waveguide and access line PCB module. 2) Multimode polymeric waveguide inside an optical backplane, which is embedded into PCB. 3) Optical slot and plug for high-density(channel pitch : 500um) board-to-board interconnection. The polymeric waveguide technology can be used for transmission of data on transmitter/ receiver system boards and for backplane interconnections. The main components are low-loss tapered polymeric waveguides and a novel optical plug and slot for board-to-board interconnections, respectively. The optical PCB is characteristic of low coupling loss, easy insertion/extraction of the boards and, especially, reliable optical coupling unaffected from external environment after board insertion.

  19. Electro-optic techniques for VLSI interconnect

    NASA Astrophysics Data System (ADS)

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  20. Digital logic circuits in yeast with CRISPR-dCas9 NOR gates

    PubMed Central

    Gander, Miles W.; Vrana, Justin D.; Voje, William E.; Carothers, James M.; Klavins, Eric

    2017-01-01

    Natural genetic circuits enable cells to make sophisticated digital decisions. Building equally complex synthetic circuits in eukaryotes remains difficult, however, because commonly used components leak transcriptionally, do not arbitrarily interconnect or do not have digital responses. Here, we designed dCas9-Mxi1-based NOR gates in Saccharomyces cerevisiae that allow arbitrary connectivity and large genetic circuits. Because we used the chromatin remodeller Mxi1, our gates showed minimal leak and digital responses. We built a combinatorial library of NOR gates that directly convert guide RNA (gRNA) inputs into gRNA outputs, enabling the gates to be ‘wired' together. We constructed logic circuits with up to seven gRNAs, including repression cascades with up to seven layers. Modelling predicted the NOR gates have effectively zero transcriptional leak explaining the limited signal degradation in the circuits. Our approach enabled the largest, eukaryotic gene circuits to date and will form the basis for large, synthetic, cellular decision-making systems. PMID:28541304

  1. Development of an optical parallel logic device and a half-adder circuit for digital optical processing

    NASA Technical Reports Server (NTRS)

    Athale, R. A.; Lee, S. H.

    1978-01-01

    The paper describes the fabrication and operation of an optical parallel logic (OPAL) device which performs Boolean algebraic operations on binary images. Several logic operations on two input binary images were demonstrated using an 8 x 8 device with a CdS photoconductor and a twisted nematic liquid crystal. Two such OPAL devices can be interconnected to form a half-adder circuit which is one of the essential components of a CPU in a digital signal processor.

  2. Photonic Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  3. ISITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI (Very Large Scale Integrated) Circuits

    DTIC Science & Technology

    1989-12-01

    rows and columns should be minimized. There are two methodologies for achieving this objective, namely, logic minimization to I I I 15 I A B C D E T...type and N-type polysilicon (Figure 2.5( b )) and interconnecting the gates with metal at a later I processing step. The two layers of aluminum available...polysiliconI ...... .. ... .. .. . .. ... .. ... .. I N polysilicon Iii~~iiiiiiii~~iiiiii (a) ( b ) 3 Figure 2.5. Controlling the Threshold Voltage in

  4. Flexible programmable logic module

    DOEpatents

    Robertson, Perry J.; Hutchinson, Robert L.; Pierson, Lyndon G.

    2001-01-01

    The circuit module of this invention is a VME board containing a plurality of programmable logic devices (PLDs), a controlled impedance clock tree, and interconnecting buses. The PLDs are arranged to permit systolic processing of a problem by offering wide data buses and a plurality of processing nodes. The board contains a clock reference and clock distribution tree that can drive each of the PLDs with two critically timed clock references. External clock references can be used to drive additional circuit modules all operating from the same synchronous clock reference.

  5. Measurement, modeling, and simulation of cryogenic SiGe HBT amplifier circuits for fast single spin readout

    NASA Astrophysics Data System (ADS)

    England, Troy; Curry, Matthew; Carr, Steve; Swartzentruber, Brian; Lilly, Michael; Bishop, Nathan; Carrol, Malcolm

    2015-03-01

    Fast, low-power quantum state readout is one of many challenges facing quantum information processing. Single electron transistors (SETs) are potentially fast, sensitive detectors for performing spin readout of electrons bound to Si:P donors. From a circuit perspective, however, their output impedance and nonlinear conductance are ill suited to drive the parasitic capacitance typical of coaxial conductors used in cryogenic environments, necessitating a cryogenic amplification stage. We will discuss calibration data, as well as modeling and simulation of cryogenic silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) circuits connected to a silicon SET and operating at 4 K. We find a continuum of solutions from simple, single-HBT amplifiers to more complex, multi-HBT circuits suitable for integration, with varying noise levels and power vs. bandwidth tradeoffs. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  6. Temporal integration and 1/f power scaling in a circuit model of cerebellar interneurons.

    PubMed

    Maex, Reinoud; Gutkin, Boris

    2017-07-01

    Inhibitory interneurons interconnected via electrical and chemical (GABA A receptor) synapses form extensive circuits in several brain regions. They are thought to be involved in timing and synchronization through fast feedforward control of principal neurons. Theoretical studies have shown, however, that whereas self-inhibition does indeed reduce response duration, lateral inhibition, in contrast, may generate slow response components through a process of gradual disinhibition. Here we simulated a circuit of interneurons (stellate and basket cells) of the molecular layer of the cerebellar cortex and observed circuit time constants that could rise, depending on parameter values, to >1 s. The integration time scaled both with the strength of inhibition, vanishing completely when inhibition was blocked, and with the average connection distance, which determined the balance between lateral and self-inhibition. Electrical synapses could further enhance the integration time by limiting heterogeneity among the interneurons and by introducing a slow capacitive current. The model can explain several observations, such as the slow time course of OFF-beam inhibition, the phase lag of interneurons during vestibular rotation, or the phase lead of Purkinje cells. Interestingly, the interneuron spike trains displayed power that scaled approximately as 1/ f at low frequencies. In conclusion, stellate and basket cells in cerebellar cortex, and interneuron circuits in general, may not only provide fast inhibition to principal cells but also act as temporal integrators that build a very short-term memory. NEW & NOTEWORTHY The most common function attributed to inhibitory interneurons is feedforward control of principal neurons. In many brain regions, however, the interneurons are densely interconnected via both chemical and electrical synapses but the function of this coupling is largely unknown. Based on large-scale simulations of an interneuron circuit of cerebellar cortex, we propose that this coupling enhances the integration time constant, and hence the memory trace, of the circuit. Copyright © 2017 the American Physiological Society.

  7. Two different ways for waveguides and optoelectronics components on top of C-MOS

    NASA Astrophysics Data System (ADS)

    Fedeli, J. M.; Jeannot, S.; Kostrzewa, M.; Di Cioccio, L.; Jousseaume, V.; Orobtchouk, R.; Maury, P.; Zussy, M.

    2006-02-01

    While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first "total bonding" approach, waveguides have been elaborated using classical "Silicon On Insulators" technology and then reported using molecular bonding on top off Si wafers. The S0I substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.

  8. Design of a Multi-Level/Analog Ferroelectric Memory Device

    NASA Technical Reports Server (NTRS)

    MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

    2006-01-01

    Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

  9. Fluid Power Multi-actuator Circuit Board with Microcomputer Control Option.

    ERIC Educational Resources Information Center

    McKechnie, R. E.; Vickers, G. W.

    1981-01-01

    Describes a portable fluid power engineering laboratory and class demonstration apparatus designed to enable students to design, build, and test multi-actuator circuits. Features a variety of standard pneumatic values and actuators fitted with quick disconnect couplings. Discusses sequencing circuit boards, microcomputer control, cost, and…

  10. Chip-to-chip interconnects based on 3D stacking of optoelectrical dies on Si

    NASA Astrophysics Data System (ADS)

    Duan, P.; Raz, O.; Smalbrugge, B. E.; Duis, J.; Dorren, H. J. S.

    2012-01-01

    We demonstrate a new approach to increase the optical interconnection bandwidth density by stacking the opto-electrical dies directly on the CMOS driver. The suggested implementation is aiming to provide a wafer scale process which will make the use of wire bonding redundant and will allow for impedance matched metallic wiring between the electronic driving circuit and its opto-electronic counter part. We suggest the use of a thick photoresist ramp between CMOS driver and opto-electrical dies surface as the bridge for supporting co-plannar waveguides (CPW) electrically plated with lithographic accuracy. In this way all three dimensions of the interconnecting metal layer, width, length and thickness can be completely controlled. In this 1st demonstration all processing is done on commercially available devices and products, and is compatible with CMOS processing technology. To test the applicability of CPW instead of wire bonds for interconnecting the CMOS circuit and opto-electronic chips, we have made test samples and tested their performance at speeds up to 10 Gbps. In this demonstration, a silicon substrate was used on which we evaporated gold co-planar waveguides (CPW) to mimic a wire on the driver. An optical link consisting of a VCSEL chip and a photodiode chip has been assembled and fully characterized using optical coupling into and out of a multimode fiber (MMF). A 10 Gb/s 27-1 NRZ PRBS signal transmitted from one chip to another chip was detected error free. A 4 dB receiver sensitivity penalty is measured for the integrated device compared to a commercial link.

  11. A multi-channel isolated power supply in non-equipotential circuit

    NASA Astrophysics Data System (ADS)

    Li, Xiang; Zhao, Bo-Wen; Zhang, Yan-Chi; Xie, Da

    2018-04-01

    A multi-channel isolation power supply is designed for the problems of different MOSFET or IGBT in the non-equipotential circuit in this paper. It mainly includes the square wave generation circuit, the high-frequency transformer and the three-terminal stabilized circuit. The first part is used to generate the 24V square wave, and as the input of the magnetic ring transformer. In the second part, the magnetic ring transformer consists of one input and three outputs to realize multi-channel isolation output. The third part can output different potential and realize non-equal potential function through the three-terminal stabilized chip. In addition, the multi-channel isolation power source proposed in this paper is Small size, high reliability and low price, and it is convenient for power electronic switches that operate on multiple different potentials. Therefore, the research on power supply of power electronic circuit has practical significance.

  12. Controllability of multi-agent systems with time-delay in state and switching topology

    NASA Astrophysics Data System (ADS)

    Ji, Zhijian; Wang, Zidong; Lin, Hai; Wang, Zhen

    2010-02-01

    In this article, the controllability issue is addressed for an interconnected system of multiple agents. The network associated with the system is of the leader-follower structure with some agents taking leader role and others being followers interconnected via the neighbour-based rule. Sufficient conditions are derived for the controllability of multi-agent systems with time-delay in state, as well as a graph-based uncontrollability topology structure is revealed. Both single and double integrator dynamics are considered. For switching topology, two algebraic necessary and sufficient conditions are derived for the controllability of multi-agent systems. Several examples are also presented to illustrate how to control the system to shape into the desired configurations.

  13. A compact multi-bit flip-flop with smaller height implementation and metal-less intra-cell routing

    NASA Astrophysics Data System (ADS)

    Seo, Jaewoo; Jung, Jinwook; Shin, Youngsoo

    2018-03-01

    Multi-bit flip-ops (MBFFs) are widely used in modern circuit designs because of their lower power consumption and smaller footprint. However, conventional MBFFs have routability issues due to the dense intra-cell connections. Since many horizontal connections are populated in the typical MBFF layouts, metal-2 (M2) tracks are highly occupied inside the cell. Accordingly, routers cannot leverage the M2 tracks for inter-cell connections. The conventional MBFFs also show a limited impact on the cell area reduction. Since the cell area saving of an MBFF mainly comes from the clock driver sharing, the layouts of other ip-op modules remain almost the same. In this paper, we propose a compact MBFF with metal-less clock routing and smaller height implementation. To achieve a sparse population of M2 routing tracks, we vertically place MBFF modules and interconnect them using the poly layer. As a result, the wire length of M2 layer inside a cell is significantly reduced. We also propose the smaller cell height implementation for compact MBFF layouts. Assuming the default standard cell height of 9 tracks, we present a 6-track MBFF implementation and the glue logic which makes legal cell placement with the 9-track logic cells. Experiments with a few test circuits show that the number of routing grids having congestion overflow is reduced by 16% and 73%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively. Total cell area is also reduced by 8% and 2%, on average, compared to the single-bit flip-op and conventional MBFF based designs, respectively.

  14. Planar Submillimeter-Wave Mixer Technology with Integrated Antenna

    NASA Technical Reports Server (NTRS)

    Chattopadhyay, Gautam; Mehdi, Imran; Gill, John J.; Lee, Choonsup; lombart, Muria L.; Thomas, Betrand

    2010-01-01

    High-performance mixers at terahertz frequencies require good matching between the coupling circuits such as antennas and local oscillators and the diode embedding impedance. With the availability of amplifiers at submillimeter wavelengths and the need to have multi-pixel imagers and cameras, planar mixer architecture is required to have an integrated system. An integrated mixer with planar antenna provides a compact and optimized design at terahertz frequencies. Moreover, it leads to a planar architecture that enables efficient interconnect with submillimeter-wave amplifiers. In this architecture, a planar slot antenna is designed on a thin gallium arsenide (GaAs) membrane in such a way that the beam on either side of the membrane is symmetric and has good beam profile with high coupling efficiency. A coplanar waveguide (CPW) coupled Schottky diode mixer is designed and integrated with the antenna. In this architecture, the local oscillator (LO) is coupled through one side of the antenna and the RF from the other side, without requiring any beam sp litters or diplexers. The intermediate frequency (IF) comes out on a 50-ohm CPW line at the edge of the mixer chip, which can be wire-bonded to external circuits. This unique terahertz mixer has an integrated single planar antenna for coupling both the radio frequency (RF) input and LO injection without any diplexer or beamsplitters. The design utilizes novel planar slot antenna architecture on a 3- mthick GaAs membrane. This work is required to enable future multi-pixel terahertz receivers for astrophysics missions, and lightweight and compact receivers for planetary missions to the outer planets in our solar system. Also, this technology can be used in tera hertz radar imaging applications as well as for testing of quantum cascade lasers (QCLs).

  15. LLMapReduce: Multi-Level Map-Reduce for High Performance Data Analysis

    DTIC Science & Technology

    2016-05-23

    LLMapReduce works with several schedulers such as SLURM, Grid Engine and LSF. Keywords—LLMapReduce; map-reduce; performance; scheduler; Grid Engine ...SLURM; LSF I. INTRODUCTION Large scale computing is currently dominated by four ecosystems: supercomputing, database, enterprise , and big data [1...interconnects [6]), High performance math libraries (e.g., BLAS [7, 8], LAPACK [9], ScaLAPACK [10]) designed to exploit special processing hardware, High

  16. Thermo-mechanical properties and integrity of metallic interconnects in microelectronics

    NASA Astrophysics Data System (ADS)

    Ege, Efe Sinan

    In this dissertation, combined numerical (Finite Element Method) and experimental efforts were undertaken to study thermo-mechanical behavior in microelectronic devices. Interconnects, including chip-level metallization and package-level solder joints, are used to join many of the circuit parts in modern equipment. The dissertation is structured into six independent studies after the introductory chapter. The first two studies focus on thermo-mechanical fatigue of solder joints. Thermo-mechanical fatigue, in the form of damage along a microstructurally coarsened region in tin-lead solder, is analyzed along with the effects of intermetallic morphology. Also, lap-shear testing is modeled to characterize the joint and to investigate the validity of experimental data from different solder and substrate geometries. In the third study, the effects of pre-machined holes on strain localization and overall ductility in bulk eutectic tin-lead alloy is examined. Finite element analyses, taking into account the viscoplastic response, were carried out to provide a mechanistic rationale to corroborate the experimental findings. The fourth study concerns chip-level copper interconnects. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without the thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. This study is followed by a chapter on atomistics of interface-mediated plasticity in thin metallic films. The objective is to gain fundamental insight into the underlying mechanisms affecting the mechanical response of nanoscale thin films. The final study investigates the effect of microstructural heterogeneity on indentation response, for the purpose of raising awareness of the uncertainties involved in applying indentation techniques in probing mechanical properties of miniaturized devices.

  17. Anxiety and nicotine dependence: Emerging role of the habenulo-interpeduncular axis

    PubMed Central

    Molas, Susanna; DeGroot, Steven; Zhao-Shea, Rubing; Tapper, Andrew R.

    2016-01-01

    While innovative modern neuroscience approaches have aided in discerning brain circuitry underlying negative emotional behaviors including fear and anxiety responses, how these circuits are recruited in normal and pathological conditions remains poorly understood. Recently, genetic tools that selectively manipulate single neuronal populations have uncovered an understudied circuit, the medial habenula (mHb)-interpeduncular (IPN) axis, that modulates basal negative emotional responses. Interestingly, the mHb-IPN pathway also represents an essential circuit that signals heightened anxiety induced by nicotine withdrawal. Insights into how this circuit inter-connects with regions more classically associated with anxiety and how chronic nicotine exposure induces neuroadaptations resulting in an anxiogenic state, may thereby provide novel strategies and molecular targets for therapies that facilitate smoking cessation, as well as, anxiety relief. PMID:27890353

  18. Implementing Bayesian networks with embedded stochastic MRAM

    NASA Astrophysics Data System (ADS)

    Faria, Rafatul; Camsari, Kerem Y.; Datta, Supriyo

    2018-04-01

    Magnetic tunnel junctions (MTJ's) with low barrier magnets have been used to implement random number generators (RNG's) and it has recently been shown that such an MTJ connected to the drain of a conventional transistor provides a three-terminal tunable RNG or a p-bit. In this letter we show how this p-bit can be used to build a p-circuit that emulates a Bayesian network (BN), such that the correlations in real world variables can be obtained from electrical measurements on the corresponding circuit nodes. The p-circuit design proceeds in two steps: the BN is first translated into a behavioral model, called Probabilistic Spin Logic (PSL), defined by dimensionless biasing (h) and interconnection (J) coefficients, which are then translated into electronic circuit elements. As a benchmark example, we mimic a family tree of three generations and show that the genetic relatedness calculated from a SPICE-compatible circuit simulator matches well-known results.

  19. Method for producing a hybridization of detector array and integrated circuit for readout

    NASA Technical Reports Server (NTRS)

    Fossum, Eric R. (Inventor); Grunthaner, Frank J. (Inventor)

    1993-01-01

    A process is explained for fabricating a detector array in a layer of semiconductor material on one substrate and an integrated readout circuit in a layer of semiconductor material on a separate substrate in order to select semiconductor material for optimum performance of each structure, such as GaAs for the detector array and Si for the integrated readout circuit. The detector array layer is lifted off its substrate, laminated on the metallized surface on the integrated surface, etched with reticulating channels to the surface of the integrated circuit, and provided with interconnections between the detector array pixels and the integrated readout circuit through the channels. The adhesive material for the lamination is selected to be chemically stable to provide electrical and thermal insulation and to provide stress release between the two structures fabricated in semiconductor materials that may have different coefficients of thermal expansion.

  20. Four-to-one power combiner for 20 GHz phased array antenna using RADC MMIC phase shifters

    NASA Technical Reports Server (NTRS)

    1991-01-01

    The design and microwave simulation of two-to-one microstrip power combiners is described. The power combiners were designed for use in a four element phase array receive antenna subarray at 20 GHz. Four test circuits are described which were designed to enable testing of the power combiner and the four element phased array antenna. Test Circuit 1 enables measurement of the two-to-one power combiner. Test Circuit 2 enables measurement of the four-to-one power combiner. Test Circuit 3 enables measurement of a four element antenna array without phase shifting MMIC's in order to characterize the power combiner with the antenna patch-to-microstrip coaxial feedthroughs. Test circuit 4 is the four element phased array antenna including the RADC MMIC phase shifters and appropriate interconnects to provide bias voltages and control phase bits.

  1. Design of rapid prototype of UAV line-of-sight stabilized control system

    NASA Astrophysics Data System (ADS)

    Huang, Gang; Zhao, Liting; Li, Yinlong; Yu, Fei; Lin, Zhe

    2018-01-01

    The line-of-sight (LOS) stable platform is the most important technology of UAV (unmanned aerial vehicle), which can reduce the effect to imaging quality from vibration and maneuvering of the aircraft. According to the requirement of LOS stability system (inertial and optical-mechanical combined method) and UAV's structure, a rapid prototype is designed using based on industrial computer using Peripheral Component Interconnect (PCI) and Windows RTX to exchange information. The paper shows the control structure, and circuit system including the inertial stability control circuit with gyro and voice coil motor driven circuit, the optical-mechanical stability control circuit with fast-steering-mirror (FSM) driven circuit and image-deviation-obtained system, outer frame rotary follower, and information-exchange system on PC. Test results show the stability accuracy reaches 5μrad, and prove the effectiveness of the combined line-of-sight stabilization control system, and the real-time rapid prototype runs stable.

  2. Cables and crosstalk

    NASA Astrophysics Data System (ADS)

    Paul, Clayton R.

    1991-06-01

    Crosstalk is the unintentional electromagnetic coupling between circuits which are connected by parallel conductors that lie in close proximity to each other. Some examples are wires in cable harnesses or metallic lands on printed-circuit boards (PCB's). This unintended interaction between two or more circuits via their electromagnetic fields can cause interference problems. Signals from one circuit that couple to another circuit appear at the terminals of the devices that are interconnected by the wires. If these signals are of sufficient magnitude or spectral content, they may cause unintended operation of the device or a degradation in its performance. A summary of the standard models used for predicting crosstalk in various types of configurations is presented. The discussion focusses on the relative accuracies, regions of applicability, and computational complexity of the models. A simple explanation of the ability (or inability) of shielded wires and twisted pairs of wires to reduce the crosstalk is also given.

  3. Hardware Trust Implications of 3-D Integration

    DTIC Science & Technology

    2010-12-01

    between two points of the combined circuit, allowing more transistors to be placed closer to each other. The reduced global interconnect length, and the...Scandiuzzo, S. Cani, L. Perugini, E. Franchi , R. Canegallo, and R. Guerrieri. Chip-to-chip communication based on capacitive coupling. In Proceedings

  4. 40-Gb/s directly-modulated photonic crystal lasers under optical injection-locking

    NASA Astrophysics Data System (ADS)

    Chen, Chin-Hui; Takeda, Koji; Shinya, Akihiko; Nozaki, Kengo; Sato, Tomonari; Kawaguchi, Yoshihiro; Notomi, Masaya; Matsuo, Shinji

    2011-08-01

    CMOS integrated circuits (IC) usually requires high data bandwidth for off-chip input/output (I/O) data transport with sufficiently low power consumption in order to overcome pin-count limitation. In order to meet future requirements of photonic network interconnect, we propose an optical output device based on an optical injection-locked photonic crystal (PhC) laser to realize low-power and high-speed off-chip interconnects. This device enables ultralow-power operation and is suitable for highly integrated photonic circuits because of its strong light-matter interaction in the PhC nanocavity and ultra-compact size. High-speed operation is achieved by using the optical injection-locking (OIL) technique, which has been shown as an effective means to enhance modulation bandwidth beyond the relaxation resonance frequency limit. In this paper, we report experimental results of the OIL-PhC laser under various injection conditions and also demonstrate 40-Gb/s large-signal direct modulation with an ultralow energy consumption of 6.6 fJ/bit.

  5. Coaxial metal-silicide Ni2Si/C54-TiSi2 nanowires.

    PubMed

    Chen, Chih-Yen; Lin, Yu-Kai; Hsu, Chia-Wei; Wang, Chiu-Yen; Chueh, Yu-Lun; Chen, Lih-Juann; Lo, Shen-Chuan; Chou, Li-Jen

    2012-05-09

    One-dimensional metal silicide nanowires are excellent candidates for interconnect and contact materials in future integrated circuits devices. Novel core-shell Ni(2)Si/C54-TiSi(2) nanowires, 2 μm in length, were grown controllably via a solid-liquid-solid growth mechanism. Their interesting ferromagnetic behaviors and excellent electrical properties have been studied in detail. The coercivities (Hcs) of the core-shell Ni(2)Si/C54-TiSi(2) nanowires was determined to be 200 and 50 Oe at 4 and 300 K, respectively, and the resistivity was measured to be as low as 31 μΩ-cm. The shift of the hysteresis loop with the temperature in zero field cooled (ZFC) and field cooled (FC) studies was found. ZFC and FC curves converge near room temperature at 314 K. The favorable ferromagnetic and electrical properties indicate that the unique core-shell nanowires can be used in penetrative ferromagnetic devices at room temperature simultaneously as a future interconnection in integrated circuits.

  6. Investigation of welded interconnection of large area wraparound contacted silicon solar cells

    NASA Technical Reports Server (NTRS)

    Lott, D. R.

    1984-01-01

    An investigation was conducted to evaluate the welding and temperature cycle testing of large area 5.9 x 5.9 wraparound silicon solar cells utilizing printed circuit substrates with SSC-155 interconnect copper metals and the LMSC Infrared Controlled weld station. An initial group of 5 welded modules containing Phase 2 developmental 5.9 x 5.9 cm cells were subjected to cyclical temperatures of + or 80 C at a rate of 120 cycles per day. Anomalies were noted in the adhesion of the cell contact metallization; therefore, 5 additional modules were fabricated and tested using available Phase I cells with demonstrated contact integrity. Cycling of the later module type through 12,000 cycles indicated the viability of this type of lightweight flexible array concept. This project demonstrated acceptable use of an alternate interconnect copper in combination with large area wraparound cells and emphasized the necessity to implement weld pull as opposed to solder pull procedures at the cell vendors for cells that will be interconnected by welding.

  7. Design of micro-ring optical sensors and circuits for integration on optical printed circuit boards (O-PCBs)

    NASA Astrophysics Data System (ADS)

    Lee, El-Hang; Lee, Hyun S.; Lee, S. G.; O, B. H.; Park, S. G.; Kim, K. H.

    2007-05-01

    We report on the design of micro-ring resonator optical sensors for integration on what we call optical printed circuit boards (O-PCBs). The objective is to realize application-specific O-PCBs, either on hard board or on flexible board, by integrating micro/nano-scale optical sensors for compact, light-weight, low-energy, high-speed, intelligent, and environmentally friendly processing of information. The O-PCBs consist of two-dimensional planar arrays of micro/nano-scale optical wires, circuits and devices that are interconnected and integrated to perform the functions of sensing and then storing, transporting, processing, switching, routing and distributing optical signals that have been collected by means of sensors. For fabrication, the polymer and organic optical wires and waveguides are first fabricated on a board and are used to interconnect and integrate sensors and other micro/ nano-scale photonic devices. Here, in our study, we focus on the sensors based on the micro-ring structures. We designed bio-sensors using silicon based micro-ring resonator. We investigate the characteristics such as sensitivity and selectivity (or quality factor) of micro-ring resonator for their use in bio-sensing application. We performed simulation studies on the quality factor of micro-ring resonators by varying the radius of the ring resonators and the separation between adjacent waveguides. We introduce the effective coupling coefficient as a realistic value to describe the strength of the coupling in micro-ring resonators.

  8. A hardware experimental platform for neural circuits in the auditory cortex

    NASA Astrophysics Data System (ADS)

    Rodellar-Biarge, Victoria; García-Dominguez, Pablo; Ruiz-Rizaldos, Yago; Gómez-Vilda, Pedro

    2011-05-01

    Speech processing in the human brain is a very complex process far from being fully understood although much progress has been done recently. Neuromorphic Speech Processing is a new research orientation in bio-inspired systems approach to find solutions to automatic treatment of specific problems (recognition, synthesis, segmentation, diarization, etc) which can not be adequately solved using classical algorithms. In this paper a neuromorphic speech processing architecture is presented. The systematic bottom-up synthesis of layered structures reproduce the dynamic feature detection of speech related to plausible neural circuits which work as interpretation centres located in the Auditory Cortex. The elementary model is based on Hebbian neuron-like units. For the computation of the architecture a flexible framework is proposed in the environment of Matlab®/Simulink®/HDL, which allows building models in different description styles, complexity and implementation levels. It provides a flexible platform for experimenting on the influence of the number of neurons and interconnections, in the precision of the results and in performance evaluation. The experimentation with different architecture configurations may help both in better understanding how neural circuits may work in the brain as well as in how speech processing can benefit from this understanding.

  9. Structure, production and signaling of leptin

    PubMed Central

    Münzberg, Heike; Morrison, Christopher D.

    2014-01-01

    The cloning of leptin in 1994 was an important milestone in obesity research. In those days obesity was stigmatized as a condition caused by lack of character and self-control. Mutations in either leptin or its receptor were the first single gene mutations found to cause morbid obesity, and it is now appreciated that obesity is caused by a dysregulation of central neuronal circuits. From the first discovery of the leptin deficient obese mouse (ob/ob), to the cloning of leptin (ob aka lep) and leptin receptor (db aka lepr) genes, much has been learned about leptin and its action in the central nervous system. The initial high hopes that leptin would cure obesity were quickly dampened by the discovery that most obese humans have increased leptin levels and develop leptin resistance. Nevertheless, leptin target sites in the brain represent an excellent blueprint for distinct neuronal circuits that control energy homeostasis. A better understanding of the regulation and interconnection of these circuits will further guide and improve the development of safe and effective interventions to treat obesity. This review will highlight our current knowledge about the hormone leptin, its signaling pathways and its central actions to mediate distinct physiological functions. PMID:25305050

  10. Optics vs copper: from the perspective of "Thunderbolt" interconnect technology

    NASA Astrophysics Data System (ADS)

    Cheng, Hengju; Krause, Christine; Ko, Jamyuen; Gao, Miaobin; Liu, Guobin; Wu, Huichin; Qi, Mike; Lam, Chun-Chit

    2013-02-01

    Interconnect technology has been progressed at a very fast pace for the past decade. The signaling rates have steadily increased from 100:Mb/s to 25Gb/s. In every generation of interconnect technology evolution, optics always seems to take over at first, however, at the end, the cost advantage of copper wins over. Because of this, optical interconnects are limited to longer distance links where the attenuation in copper cable is too large for the integrated circuits to compensate. Optical interconnect has long been viewed as the premier solution in compared with copper interconnect. With the release of Thunderbolt technology, we are entering a new era in consumer electronics that runs at 10Gb/s line rate (20Gb/s throughput per connector interface). Thunderbolt interconnect technology includes both active copper cables and active optical cables as the transmission media which have very different physical characteristics. In order for optics to succeed in consumer electronics, several technology hurdles need to be cleared. For example, the optical cable needs to handle the consumer abuses such as pinch and bend. Also, the optical engine used in the active optical cable needs to be physically very small so that we don't change the looks and feels of the cable/connector. Most importantly, the cost of optics needs to come down significantly to effectively compete with the copper solution. Two interconnect technologies are compared and discussed on the relative cost, power consumption, form factor, density, and future scalability.

  11. Circuit for high resolution decoding of multi-anode microchannel array detectors

    NASA Technical Reports Server (NTRS)

    Kasle, David B. (Inventor)

    1995-01-01

    A circuit for high resolution decoding of multi-anode microchannel array detectors consisting of input registers accepting transient inputs from the anode array; anode encoding logic circuits connected to the input registers; midpoint pipeline registers connected to the anode encoding logic circuits; and pixel decoding logic circuits connected to the midpoint pipeline registers is described. A high resolution algorithm circuit operates in parallel with the pixel decoding logic circuit and computes a high resolution least significant bit to enhance the multianode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of the anode array. A multiplexer is connected to the pixel decoding logic circuit and allows a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size. An output register concatenates the high resolution least significant bit onto the standard ten bit pixel address location to provide an eleven bit pixel address, and also stores the full eleven bit pixel address. A timing and control state machine is connected to the input registers, the anode encoding logic circuits, and the output register for managing the overall operation of the circuit.

  12. Unraveling Cajal's view of the olfactory system

    PubMed Central

    Figueres-Oñate, María; Gutiérrez, Yolanda; López-Mascaraque, Laura

    2014-01-01

    The olfactory system has a highly regular organization of interconnected synaptic circuits from the periphery. It is therefore an excellent model for understanding general principles about how the brain processes information. Cajal revealed the basic cell types and their interconnections at the end of the XIX century. Since his original descriptions, the observation and analysis of the olfactory system and its components represents a major topic in neuroscience studies, providing important insights into the neural mechanisms. In this review, we will highlight the importance of Cajal contributions and his legacy to the actual knowledge of the olfactory system. PMID:25071462

  13. Applications considerations in the system design of highly concurrent multiprocessors

    NASA Technical Reports Server (NTRS)

    Lundstrom, Stephen F.

    1987-01-01

    A flow model processor approach to parallel processing is described, using very-high-performance individual processors, high-speed circuit switched interconnection networks, and a high-speed synchronization capability to minimize the effect of the inherently serial portions of applications on performance. Design studies related to the determination of the number of processors, the memory organization, and the structure of the networks used to interconnect the processor and memory resources are discussed. Simulations indicate that applications centered on the large shared data memory should be able to sustain over 500 million floating point operations per second.

  14. Generic three-dimensional wavelength routers based on cross connects of multilayer diffractive elements

    NASA Astrophysics Data System (ADS)

    Deng, Xuegong; Chen, Ray T.

    2001-05-01

    We report a generic method to construct 3D wavelength routers by adapting a novel design for multi-optical wavelength interconnects (MOWI's). Optical wavelength- selective (WS) interconnections are realized by resorting to layered diffractive phase elements. Besides, we simultaneously carry out several other integrated operations on the incident beams according to their wavelengths. We demonstrate an 4 X 4 inline 3D WS optical crossconnect and a 1D 1 X 8 WS perfect shuffler. The devices are well feasible for mass production by using current standard microelectronics technologies. It is plausible that the proposed WS MOWI scenario will find critical applications in module-to-module and board-to-board optical interconnect systems, as well as in other devices for short-link multi- wavelength networks that would benefit from function integration.

  15. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    NASA Technical Reports Server (NTRS)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  16. Cooled electrical terminal assembly and device incorporating same

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Phillips, Mark G.; Kehl, Dennis L.; Kaishian, Steven C.; Kannenberg, Daniel G.

    2006-08-22

    A terminal structure provides interfacing with power electronics circuitry and external circuitry. The thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the terminal structure and the circuits through fluid circulating through the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  17. Cooled electrical terminal assembly and device incorporating same

    DOEpatents

    Beihoff, Bruce C.; Radosevich, Lawrence D.; Phillips, Mark G.; Kehl, Dennis L.; Kaishian, Steven C.; Kannenberg, Daniel G.

    2005-05-24

    A terminal structure provides interfacing with power electronics circuitry and external circuitry. The thermal support may receive one or more power electronic circuits. The support may aid in removing heat from the terminal structure and the circuits through fluid circulating through the support. The support may form a shield from both external EMI/RFI and from interference generated by operation of the power electronic circuits. Features may be provided to permit and enhance connection of the circuitry to external circuitry, such as improved terminal configurations. Modular units may be assembled that may be coupled to electronic circuitry via plug-in arrangements or through interface with a backplane or similar mounting and interconnecting structures.

  18. Three-dimensional reconstruction of brain-wide wiring networks in Drosophila at single-cell resolution.

    PubMed

    Chiang, Ann-Shyn; Lin, Chih-Yung; Chuang, Chao-Chun; Chang, Hsiu-Ming; Hsieh, Chang-Huain; Yeh, Chang-Wei; Shih, Chi-Tin; Wu, Jian-Jheng; Wang, Guo-Tzau; Chen, Yung-Chang; Wu, Cheng-Chi; Chen, Guan-Yu; Ching, Yu-Tai; Lee, Ping-Chang; Lin, Chih-Yang; Lin, Hui-Hao; Wu, Chia-Chou; Hsu, Hao-Wei; Huang, Yun-Ann; Chen, Jing-Yi; Chiang, Hsin-Jung; Lu, Chun-Fang; Ni, Ru-Fen; Yeh, Chao-Yuan; Hwang, Jenn-Kang

    2011-01-11

    Animal behavior is governed by the activity of interconnected brain circuits. Comprehensive brain wiring maps are thus needed in order to formulate hypotheses about information flow and also to guide genetic manipulations aimed at understanding how genes and circuits orchestrate complex behaviors. To assemble this map, we deconstructed the adult Drosophila brain into approximately 16,000 single neurons and reconstructed them into a common standardized framework to produce a virtual fly brain. We have constructed a mesoscopic map and found that it consists of 41 local processing units (LPUs), six hubs, and 58 tracts covering the whole Drosophila brain. Despite individual local variation, the architecture of the Drosophila brain shows invariance for both the aggregation of local neurons (LNs) within specific LPUs and for the connectivity of projection neurons (PNs) between the same set of LPUs. An open-access image database, named FlyCircuit, has been constructed for online data archiving, mining, analysis, and three-dimensional visualization of all single neurons, brain-wide LPUs, their wiring diagrams, and neural tracts. We found that the Drosophila brain is assembled from families of multiple LPUs and their interconnections. This provides an essential first step in the analysis of information processing within and between neurons in a complete brain. Copyright © 2011 Elsevier Ltd. All rights reserved.

  19. Cascade photonic integrated circuit architecture for electro-optic in-phase quadrature/single sideband modulation or frequency conversion.

    PubMed

    Hasan, Mehedi; Hall, Trevor

    2015-11-01

    A photonic integrated circuit architecture for implementing frequency upconversion is proposed. The circuit consists of a 1×2 splitter and 2×1 combiner interconnected by two stages of differentially driven phase modulators having 2×2 multimode interference coupler between the stages. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. The intrinsic conversion efficiency of the proposed design is improved by 6 dB over the alternative functionally equivalent circuit based on dual parallel Mach-Zehnder modulators known in the prior art. A two-tone analysis is presented to study the linearity of the proposed circuit, and a comparison is provided over the alternative. The proposed circuit is suitable for integration in any platform that offers linear electro-optic phase modulation such as LiNbO(3), silicon, III-V, or hybrid technology.

  20. Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch

    PubMed Central

    Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

    2010-01-01

    Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and ‘memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch. PMID:20212522

  1. Synthesizing a novel genetic sequential logic circuit: a push-on push-off switch.

    PubMed

    Lou, Chunbo; Liu, Xili; Ni, Ming; Huang, Yiqi; Huang, Qiushi; Huang, Longwen; Jiang, Lingli; Lu, Dan; Wang, Mingcong; Liu, Chang; Chen, Daizhuo; Chen, Chongyi; Chen, Xiaoyue; Yang, Le; Ma, Haisu; Chen, Jianguo; Ouyang, Qi

    2010-01-01

    Design and synthesis of basic functional circuits are the fundamental tasks of synthetic biologists. Before it is possible to engineer higher-order genetic networks that can perform complex functions, a toolkit of basic devices must be developed. Among those devices, sequential logic circuits are expected to be the foundation of the genetic information-processing systems. In this study, we report the design and construction of a genetic sequential logic circuit in Escherichia coli. It can generate different outputs in response to the same input signal on the basis of its internal state, and 'memorize' the output. The circuit is composed of two parts: (1) a bistable switch memory module and (2) a double-repressed promoter NOR gate module. The two modules were individually rationally designed, and they were coupled together by fine-tuning the interconnecting parts through directed evolution. After fine-tuning, the circuit could be repeatedly, alternatively triggered by the same input signal; it functions as a push-on push-off switch.

  2. Computer-Aided Design of Low-Noise Microwave Circuits

    NASA Astrophysics Data System (ADS)

    Wedge, Scott William

    1991-02-01

    Devoid of most natural and manmade noise, microwave frequencies have detection sensitivities limited by internally generated receiver noise. Low-noise amplifiers are therefore critical components in radio astronomical antennas, communications links, radar systems, and even home satellite dishes. A general technique to accurately predict the noise performance of microwave circuits has been lacking. Current noise analysis methods have been limited to specific circuit topologies or neglect correlation, a strong effect in microwave devices. Presented here are generalized methods, developed for computer-aided design implementation, for the analysis of linear noisy microwave circuits comprised of arbitrarily interconnected components. Included are descriptions of efficient algorithms for the simultaneous analysis of noisy and deterministic circuit parameters based on a wave variable approach. The methods are therefore particularly suited to microwave and millimeter-wave circuits. Noise contributions from lossy passive components and active components with electronic noise are considered. Also presented is a new technique for the measurement of device noise characteristics that offers several advantages over current measurement methods.

  3. Circuit filling factor (CFF) for multiply tuned probes, revisited

    NASA Astrophysics Data System (ADS)

    Conradi, Mark S.; Zens, Albert P.

    2018-07-01

    The concept of circuit filling factor (CFF) is re-examined for multi-tuned, multi-inductor probe circuits. The CFF is the fraction of magnetic stored energy residing in the NMR coil. The CFF theorem states that the CFF sums to unity across all the resonant normal modes. It dictates that improved performance from a large CFF in one mode comes at the expense of CFF (and performance) at the other mode(s). Simple analytical calculations of two-mode circuits are used to demonstrate and confirm the CFF theorem. A triple-resonance circuit is calculated to show the large trade-offs involved there. The theorem can provide guidance for choosing the best circuit and relative inductances in multi-nuclear probes. The CFF is directly accessible from ball frequency-shift measurements. We give experimental measures of the CFF from ball shifts and compare to calculated values of the CFF, with good agreement.

  4. Advanced metal lift-off process using electron-beam flood exposure of single-layer photoresist

    NASA Astrophysics Data System (ADS)

    Minter, Jason P.; Ross, Matthew F.; Livesay, William R.; Wong, Selmer S.; Narcy, Mark E.; Marlowe, Trey

    1999-06-01

    In the manufacture of many types of integrated circuit and thin film devices, it is desirable to use a lift-of process for the metallization step to avoid manufacturing problems encountered when creating metal interconnect structures using plasma etch. These problems include both metal adhesion and plasma etch difficulties. Key to the success of the lift-off process is the creation of a retrograde or undercut profile in the photoresists before the metal deposition step. Until now, lift-off processing has relied on costly multi-layer photoresists schemes, image reversal, and non-repeatable photoresist processes to obtain the desired lift-off profiles in patterned photoresist. This paper present a simple, repeatable process for creating robust, user-defined lift-off profiles in single layer photoresist using a non-thermal electron beam flood exposure. For this investigation, lift-off profiles created using electron beam flood exposure of many popular photoresists were evaluated. Results of lift-off profiles created in positive tone AZ7209 and ip3250 are presented here.

  5. A universal computer control system for motors

    NASA Technical Reports Server (NTRS)

    Szakaly, Zoltan F. (Inventor)

    1991-01-01

    A control system for a multi-motor system such as a space telerobot, having a remote computational node and a local computational node interconnected with one another by a high speed data link is described. A Universal Computer Control System (UCCS) for the telerobot is located at each node. Each node is provided with a multibus computer system which is characterized by a plurality of processors with all processors being connected to a common bus, and including at least one command processor. The command processor communicates over the bus with a plurality of joint controller cards. A plurality of direct current torque motors, of the type used in telerobot joints and telerobot hand-held controllers, are connected to the controller cards and responds to digital control signals from the command processor. Essential motor operating parameters are sensed by analog sensing circuits and the sensed analog signals are converted to digital signals for storage at the controller cards where such signals can be read during an address read/write cycle of the command processing processor.

  6. 47 CFR 54.500 - Terms and definitions.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... and state agencies that provides free or reduced price lunches to economically disadvantaged children... Management and Budget is eligible for a free lunch. (j) Pre-discount price. The “pre-discount price” means... service such as cellular, interconnected voice over Internet protocol (VoIP), and the circuit capacity...

  7. Control electronics for a multi-laser/multi-detector scanning system

    NASA Technical Reports Server (NTRS)

    Kennedy, W.

    1980-01-01

    The Mars Rover Laser Scanning system uses a precision laser pointing mechanism, a photodetector array, and the concept of triangulation to perform three dimensional scene analysis. The system is used for real time terrain sensing and vision. The Multi-Laser/Multi-Detector laser scanning system is controlled by a digital device called the ML/MD controller. A next generation laser scanning system, based on the Level 2 controller, is microprocessor based. The new controller capabilities far exceed those of the ML/MD device. The first draft circuit details and general software structure are presented.

  8. Numerical simulation of CTE mismatch and thermal-structural stresses in the design of interconnects

    NASA Astrophysics Data System (ADS)

    Peter, Geoffrey John M.

    With the ever-increasing chip complexity, interconnects have to be designed to meet the new challenges. Advances in optical lithography have made chip feature sizes available today at 70 nm dimensions. With advances in Extreme Ultraviolet Lithography, X-ray Lithography, and Ion Projection Lithography it is expected that the line width will further decrease to 20 nm or less. With the decrease in feature size, the number of active devices on the chip increases. With higher levels of circuit integration, the challenge is to dissipate the increased heat flux from the chip surface area. Thermal management considerations include coefficient of thermal expansion (CTE) matching to prevent failure between the chip and the board. This in turn calls for improved system performance and reliability of the electronic structural systems. Experience has shown that in most electronic systems, failures are mostly due to CTE mismatch between the chip, board, and the solder joint (solder interconnect). The resulting high thermal-structural stress and strain due to CTE mismatch produces cracks in the solder joints with eventual failure of the electronic component. In order to reduce the thermal stress between the chip, board, and the solder joint, this dissertation examines the effect of inserting wire bundle (wire interconnect) between the chip and the board. The flexibility of the wires or fibers would reduce the stress at the rigid joints. Numerical simulations of two, and three-dimensional models of the solder and wire interconnects are examined. The numerical simulation is linear in nature and is based on linear isotropic material properties. The effect of different wire material properties is examined. The effect of varying the wire diameter is studied by changing the wire diameter. A major cause of electronic equipment failure is due to fatigue failure caused by thermal cycling, and vibrations. A two-dimensional modal and harmonic analysis was simulated for the wire interconnect and the solder interconnect. The numerical model simulated using ANSYS program was validated with the numerical/experimental results of other published researchers. In addition the results were cross-checked by IDEAS program. A prototype non-working wire interconnect is proposed to emphasize practical application. The numerical analysis, in this dissertation is based on a U.S. Patent granted to G. Peter(42).

  9. A Phase-Locked Loop Epilepsy Network Emulator.

    PubMed

    Watson, P D; Horecka, K M; Cohen, N J; Ratnam, R

    2016-10-15

    Most seizure forecasting employs statistical learning techniques that lack a representation of the network interactions that give rise to seizures. We present an epilepsy network emulator (ENE) that uses a network of interconnected phase-locked loops (PLLs) to model synchronous, circuit-level oscillations between electrocorticography (ECoG) electrodes. Using ECoG data from a canine-epilepsy model (Davis et al. 2011) and a physiological entropy measure (approximate entropy or ApEn, Pincus 1995), we demonstrate the entropy of the emulator phases increases dramatically during ictal periods across all ECoG recording sites and across all animals in the sample. Further, this increase precedes the observable voltage spikes that characterize seizure activity in the ECoG data. These results suggest that the ENE is sensitive to phase-domain information in the neural circuits measured by ECoG and that an increase in the entropy of this measure coincides with increasing likelihood of seizure activity. Understanding this unpredictable phase-domain electrical activity present in ECoG recordings may provide a target for seizure detection and feedback control.

  10. Trade-offs between lens complexity and real estate utilization in a free-space multichip global interconnection module.

    PubMed

    Milojkovic, Predrag; Christensen, Marc P; Haney, Michael W

    2006-07-01

    The FAST-Net (Free-space Accelerator for Switching Terabit Networks) concept uses an array of wide-field-of-view imaging lenses to realize a high-density shuffle interconnect pattern across an array of smart-pixel integrated circuits. To simplify the optics we evaluated the efficiency gained in replacing spherical surfaces with aspherical surfaces by exploiting the large disparity between narrow vertical cavity surface emitting laser (VCSEL) beams and the wide field of view of the imaging optics. We then analyzed trade-offs between lens complexity and chip real estate utilization and determined that there exists an optimal numerical aperture for VCSELs that maximizes their area density. The results provide a general framework for the design of wide-field-of-view free-space interconnection systems that incorporate high-density VCSEL arrays.

  11. Performance of a 300 Mbps 1:16 serial/parallel optoelectronic receiver module

    NASA Technical Reports Server (NTRS)

    Richard, M. A.; Claspy, P. C.; Bhasin, K. B.; Bendett, M. B.

    1990-01-01

    Optical interconnects are being considered for the high speed distribution of multiplexed control signals in GaAs monolithic microwave integrated circuit (MMIC) based phased array antennas. The performance of a hybrid GaAs optoelectronic integrated circuit (OEIC) is described, as well as its design and fabrication. The OEIC converts a 16-bit serial optical input to a 16 parallel line electrical output using an on-board 1:16 demultiplexer and operates at data rates as high as 30b Mbps. The performance characteristics and potential applications of the device are presented.

  12. Interchip link system using an optical wiring method.

    PubMed

    Cho, In-Kui; Ryu, Jin-Hwa; Jeong, Myung-Yung

    2008-08-15

    A chip-scale optical link system is presented with a transmitter/receiver and optical wire link. The interchip link system consists of a metal optical bench, a printed circuit board module, a driver/receiver integrated circuit, a vertical cavity surface-emitting laser/photodiode array, and an optical wire link composed of plastic optical fibers (POFs). We have developed a downsized POF and an optical wiring method that allows on-site installation with a simple annealing as optical wiring technologies for achieving high-density optical interchip interconnection within such devices. Successful data transfer measurements are presented.

  13. Large-Constraint-Length, Fast Viterbi Decoder

    NASA Technical Reports Server (NTRS)

    Collins, O.; Dolinar, S.; Hsu, In-Shek; Pollara, F.; Olson, E.; Statman, J.; Zimmerman, G.

    1990-01-01

    Scheme for efficient interconnection makes VLSI design feasible. Concept for fast Viterbi decoder provides for processing of convolutional codes of constraint length K up to 15 and rates of 1/2 to 1/6. Fully parallel (but bit-serial) architecture developed for decoder of K = 7 implemented in single dedicated VLSI circuit chip. Contains six major functional blocks. VLSI circuits perform branch metric computations, add-compare-select operations, and then store decisions in traceback memory. Traceback processor reads appropriate memory locations and puts out decoded bits. Used as building block for decoders of larger K.

  14. Solid oxide fuel cell having monolithic core

    DOEpatents

    Ackerman, John P.; Young, John E.

    1984-01-01

    A solid oxide fuel cell for electrochemically combining fuel and oxidant for generating galvanic output, wherein the cell core has an array of electrolyte and interconnect walls that are substantially devoid of any composite inert materials for support. Instead, the core is monolithic, where each electrolyte wall consists of thin layers of cathode and anode materials sandwiching a thin layer of electrolyte material therebetween, and each interconnect wall consists of thin layers of the cathode and anode materials sandwiching a thin layer of interconnect material therebetween. The electrolyte walls are arranged and backfolded between adjacent interconnect walls operable to define a plurality of core passageways alternately arranged where the inside faces thereof have only the anode material or only the cathode material exposed. Means direct the fuel to the anode-exposed core passageways and means direct the oxidant to the cathode-exposed core passageway; and means also direct the galvanic output to an exterior circuit. Each layer of the electrolyte and interconnect materials is of the order of 0.002-0.01 cm thick; and each layer of the cathode and anode materials is of the order of 0.002-0.05 cm thick.

  15. Low power, scalable multichannel high voltage controller

    DOEpatents

    Stamps, James Frederick [Livermore, CA; Crocker, Robert Ward [Fremont, CA; Yee, Daniel Dadwa [Dublin, CA; Dils, David Wright [Fort Worth, TX

    2006-03-14

    A low voltage control circuit is provided for individually controlling high voltage power provided over bus lines to a multitude of interconnected loads. An example of a load is a drive for capillary channels in a microfluidic system. Control is distributed from a central high voltage circuit, rather than using a number of large expensive central high voltage circuits to enable reducing circuit size and cost. Voltage is distributed to each individual load and controlled using a number of high voltage controller channel switches connected to high voltage bus lines. The channel switches each include complementary pull up and pull down photo isolator relays with photo isolator switching controlled from the central high voltage circuit to provide a desired bus line voltage. Switching of the photo isolator relays is further controlled in each channel switch using feedback from a resistor divider circuit to maintain the bus voltage swing within desired limits. Current sensing is provided using a switched resistive load in each channel switch, with switching of the resistive loads controlled from the central high voltage circuit.

  16. Low power, scalable multichannel high voltage controller

    DOEpatents

    Stamps, James Frederick [Livermore, CA; Crocker, Robert Ward [Fremont, CA; Yee, Daniel Dadwa [Dublin, CA; Dils, David Wright [Fort Worth, TX

    2008-03-25

    A low voltage control circuit is provided for individually controlling high voltage power provided over bus lines to a multitude of interconnected loads. An example of a load is a drive for capillary channels in a microfluidic system. Control is distributed from a central high voltage circuit, rather than using a number of large expensive central high voltage circuits to enable reducing circuit size and cost. Voltage is distributed to each individual load and controlled using a number of high voltage controller channel switches connected to high voltage bus lines. The channel switches each include complementary pull up and pull down photo isolator relays with photo isolator switching controlled from the central high voltage circuit to provide a desired bus line voltage. Switching of the photo isolator relays is further controlled in each channel switch using feedback from a resistor divider circuit to maintain the bus voltage swing within desired limits. Current sensing is provided using a switched resistive load in each channel switch, with switching of the resistive loads controlled from the central high voltage circuit.

  17. Anxiety and Nicotine Dependence: Emerging Role of the Habenulo-Interpeduncular Axis.

    PubMed

    Molas, Susanna; DeGroot, Steven R; Zhao-Shea, Rubing; Tapper, Andrew R

    2017-02-01

    While innovative modern neuroscience approaches have aided in discerning brain circuitry underlying negative emotional behaviors including fear and anxiety responses, how these circuits are recruited in normal and pathological conditions remains poorly understood. Recently, genetic tools that selectively manipulate single neuronal populations have uncovered an understudied circuit, the medial habenula (mHb)-interpeduncular (IPN) axis, that modulates basal negative emotional responses. Interestingly, the mHb-IPN pathway also represents an essential circuit that signals heightened anxiety induced by nicotine withdrawal. Insights into how this circuit interconnects with regions more classically associated with anxiety, and how chronic nicotine exposure induces neuroadaptations resulting in an anxiogenic state, may thereby provide novel strategies and molecular targets for therapies that facilitate smoking cessation, as well as for anxiety relief. Copyright © 2016 Elsevier Ltd. All rights reserved.

  18. Electronic plants

    PubMed Central

    Stavrinidou, Eleni; Gabrielsson, Roger; Gomez, Eliot; Crispin, Xavier; Nilsson, Ove; Simon, Daniel T.; Berggren, Magnus

    2015-01-01

    The roots, stems, leaves, and vascular circuitry of higher plants are responsible for conveying the chemical signals that regulate growth and functions. From a certain perspective, these features are analogous to the contacts, interconnections, devices, and wires of discrete and integrated electronic circuits. Although many attempts have been made to augment plant function with electroactive materials, plants’ “circuitry” has never been directly merged with electronics. We report analog and digital organic electronic circuits and devices manufactured in living plants. The four key components of a circuit have been achieved using the xylem, leaves, veins, and signals of the plant as the template and integral part of the circuit elements and functions. With integrated and distributed electronics in plants, one can envisage a range of applications including precision recording and regulation of physiology, energy harvesting from photosynthesis, and alternatives to genetic modification for plant optimization. PMID:26702448

  19. Mechanical integrity of a carbon nanotube/copper-based through-silicon via for 3D integrated circuits: a multi-scale modeling approach.

    PubMed

    Awad, Ibrahim; Ladani, Leila

    2015-12-04

    Carbon nanotube (CNT)/copper (Cu) composite material is proposed to replace Cu-based through-silicon vias (TSVs) in micro-electronic packages. The proposed material is believed to offer extraordinary mechanical and electrical properties and the presence of CNTs in Cu is believed to overcome issues associated with miniaturization of Cu interconnects, such as electromigration. This study introduces a multi-scale modeling of the proposed TSV in order to evaluate its mechanical integrity under mechanical and thermo-mechanical loading conditions. Molecular dynamics (MD) simulation was used to determine CNT/Cu interface adhesion properties. A cohesive zone model (CZM) was found to be most appropriate to model the interface adhesion, and CZM parameters at the nanoscale were determined using MD simulation. CZM parameters were then used in the finite element analysis in order to understand the mechanical and thermo-mechanical behavior of composite TSV at micro-scale. From the results, CNT/Cu separation does not take place prior to plastic deformation of Cu in bending, and separation does not take place when standard thermal cycling is applied. Further investigation is recommended in order to alleviate the increased plastic deformation in Cu at the CNT/Cu interface in both loading conditions.

  20. Mitigating Interconnection Challenges of the High Penetration Utility-Interconnected Photovoltaic (PV) in the Electrical Distribution Systems: Cooperative Research and Development Final Report, CRADA Number CRD-14-563

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chakraborty, Sudipta

    Various interconnection challenges exist when connecting distributed PV into the electrical distribution grid in terms of safety, reliability, and stability of the electric power systems. Some of the urgent areas for research, as identified by inverter manufacturers, installers and utilities, are potential for transient overvoltage from PV inverters, multi-inverter anti-islanding, impact of smart inverters on volt-VAR support, impact of bidirectional power flow, and potential for distributed generation curtailment solutions to mitigate grid stability challenges. Under this project, NREL worked with SolarCity to address these challenges through research, testing and analysis at the Energy System Integration Facility (ESIF). Inverters from differentmore » manufacturers were tested at ESIF and NREL's unique power hardware-in-the-loop (PHIL) capability was utilized to evaluate various system-level impacts. Through the modeling, simulation, and testing, this project eliminated critical barriers on high PV penetration and directly supported the Department of Energy's SunShot goal of increasing the solar PV on the electrical grid.« less

  1. Optical interconnection network for parallel access to multi-rank memory in future computing systems.

    PubMed

    Wang, Kang; Gu, Huaxi; Yang, Yintang; Wang, Kun

    2015-08-10

    With the number of cores increasing, there is an emerging need for a high-bandwidth low-latency interconnection network, serving core-to-memory communication. In this paper, aiming at the goal of simultaneous access to multi-rank memory, we propose an optical interconnection network for core-to-memory communication. In the proposed network, the wavelength usage is delicately arranged so that cores can communicate with different ranks at the same time and broadcast for flow control can be achieved. A distributed memory controller architecture that works in a pipeline mode is also designed for efficient optical communication and transaction address processes. The scaling method and wavelength assignment for the proposed network are investigated. Compared with traditional electronic bus-based core-to-memory communication, the simulation results based on the PARSEC benchmark show that the bandwidth enhancement and latency reduction are apparent.

  2. Multi-mode ultra-strong coupling (I): spectroscopic experiments using a vacuum-gap transmon circuit architecture

    NASA Astrophysics Data System (ADS)

    Bosman, Sal J.; Gely, Mario F.; Singh, Vibhor; Bruno, Alessandro; Bothner, Daniel; Steele, Gary A.

    In circuit QED, multi-mode extensions of the quantum Rabi model suffer from divergence problems. Here, we spectroscopically study multi-mode ultra-strong coupling using a transmon circuit architecture, which provides no clear guidelines on how many modes play a role in the dynamics of the system. As our transmon qubit, we employ a suspended island above the voltage anti-node of a λ / 4 coplanar microwave resonator, thereby realising a circuit where 88% of the qubit capacitance is formed by a vacuum-gap capacitor with the center conductor of the resonator. We measure vacuum Rabi splitting over multiple modes up to 2 GHz, reaching coupling ratios of g / ω = 0 . 18 , well within the ultra-strong coupling regime. We observe a qubit-mediated mode coupling, measurable up to the fifth mode at 38 GHz. Using a novel analytical quantum circuit model of this architecture, which includes all modes without introducing divergencies, we are able to fit the full spectrum and extract a vacuum fluctuations induced Bloch-Siegert shift of up to 62 MHz. This circuit architecture expands the versatility of the transmon technology platform and opens many possibilities in multi-mode physics in the ultra-strong coupling regime.

  3. WDM package enabling high-bandwidth optical intrasystem interconnects for high-performance computer systems

    NASA Astrophysics Data System (ADS)

    Schrage, J.; Soenmez, Y.; Happel, T.; Gubler, U.; Lukowicz, P.; Mrozynski, G.

    2006-02-01

    From long haul, metro access and intersystem links the trend goes to applying optical interconnection technology at increasingly shorter distances. Intrasystem interconnects such as data busses between microprocessors and memory blocks are still based on copper interconnects today. This causes a bottleneck in computer systems since the achievable bandwidth of electrical interconnects is limited through the underlying physical properties. Approaches to solve this problem by embedding optical multimode polymer waveguides into the board (electro-optical circuit board technology, EOCB) have been reported earlier. The principle feasibility of optical interconnection technology in chip-to-chip applications has been validated in a number of projects. For reasons of cost considerations waveguides with large cross sections are used in order to relax alignment requirements and to allow automatic placement and assembly without any active alignment of components necessary. On the other hand the bandwidth of these highly multimodal waveguides is restricted due to mode dispersion. The advance of WDM technology towards intrasystem applications will provide sufficiently high bandwidth which is required for future high-performance computer systems: Assuming that, for example, 8 wavelength-channels with 12Gbps (SDR1) each are given, then optical on-board interconnects with data rates a magnitude higher than the data rates of electrical interconnects for distances typically found at today's computer boards and backplanes can be realized. The data rate will be twice as much, if DDR2 technology is considered towards the optical signals as well. In this paper we discuss an approach for a hybrid integrated optoelectronic WDM package which might enable the application of WDM technology to EOCB.

  4. Rapid prototyping of interfacing microcomponents for printed circuit board-level optical interconnects

    NASA Astrophysics Data System (ADS)

    Van Erps, Jürgen; Vervaeke, Michael; Thienpont, Hugo

    2012-01-01

    One of the important challenges for the deployment of the emerging breed of nanotechnology components is interfacing them with the external world, preferably accomplished with low-cost micro-optical devices. For the fabrication of this kind of micro-optical components, we make use of deep proton writing (DPW) as a generic rapid prototyping technology. DPW consists of bombarding polymer samples with swift protons, which results after chemical processing steps in high quality micro-optical components. The strength of the DPW micro-machining technology is the ability to fabricate monolithic building blocks that include micro-optical and mechanical functionalities which can be precisely integrated into more complex photonic systems. In this paper we give an overview of the process steps of the technology and we present several examples of micro-optical and micro-mechanical components, fabricated through DPW, targeting applications in printed circuit baordlevel optical interconnections. These include: high-precision 2-D fiber connectors, discrete out-of-plane coupling structures featuring high-quality 45° and curved micro-mirrors, arrays of high aspect ratio micro-pillars and backplane connectors. While DPW is clearly not a mass fabrication technique as such, one of its assets is that once the master component has been prototyped, a metal mould can be generated from the DPW master by applying electroplating. After removal of the plastic master, this metal mould can be used as a shim in a final microinjection moulding or hot embossing step. This way, the master component can be mass-produced at low cost in a wide variety of high-tech plastics.

  5. MO detector (MOD): a dual-function optical modulator-detector for on-chip communication

    NASA Astrophysics Data System (ADS)

    Sun, Shuai; Zhang, Ruoyu; Peng, Jiaxin; Narayana, Vikram K.; Dalir, Hamed; El-Ghazawi, Tarek; Sorger, Volker J.

    2018-04-01

    Physical challenges at the device and interconnect level limit both network and computing energy efficiency. While photonics is being considered to address interconnect bottlenecks, optical routing is still limited by electronic circuitry, requiring substantial overhead for optical-electrical-optical conversion. Here we show a novel design of an integrated broadband photonic-plasmonic hybrid device termed MODetector featuring dual light modulation and detection function to act as an optical transceiver in the photonic network-on-chip. With over 10 dB extinction ratio and 0.8 dB insertion loss at the modulation state, this MODetector provides 0.7 W/A responsivity in the detection state with 36 ps response time. This multi-functional device: (i) eliminates OEO conversion, (ii) reduces optical losses from photodetectors when not needed, and (iii) enables cognitive routing strategies for network-on-chips.

  6. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2006-12-12

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  7. Multi-channel detector readout method and integrated circuit

    DOEpatents

    Moses, William W.; Beuville, Eric; Pedrali-Noy, Marzio

    2004-05-18

    An integrated circuit which provides multi-channel detector readout from a detector array. The circuit receives multiple signals from the elements of a detector array and compares the sampled amplitudes of these signals against a noise-floor threshold and against one another. A digital signal is generated which corresponds to the location of the highest of these signal amplitudes which exceeds the noise floor threshold. The digital signal is received by a multiplexing circuit which outputs an analog signal corresponding the highest of the input signal amplitudes. In addition a digital control section provides for programmatic control of the multiplexer circuit, amplifier gain, amplifier reset, masking selection, and test circuit functionality on each input thereof.

  8. Parallel LC circuit model for multi-band absorption and preliminary design of radiative cooling.

    PubMed

    Feng, Rui; Qiu, Jun; Liu, Linhua; Ding, Weiqiang; Chen, Lixue

    2014-12-15

    We perform a comprehensive analysis of multi-band absorption by exciting magnetic polaritons in the infrared region. According to the independent properties of the magnetic polaritons, we propose a parallel inductance and capacitance(PLC) circuit model to explain and predict the multi-band resonant absorption peaks, which is fully validated by using the multi-sized structure with identical dielectric spacing layer and the multilayer structure with the same strip width. More importantly, we present the application of the PLC circuit model to preliminarily design a radiative cooling structure realized by merging several close peaks together. This omnidirectional and polarization insensitive structure is a good candidate for radiative cooling application.

  9. Advantages and Challenges of 10-Gbps Transmission on High-Density Interconnect Boards

    NASA Astrophysics Data System (ADS)

    Yee, Chang Fei; Jambek, Asral Bahari; Al-Hadi, Azremi Abdullah

    2016-06-01

    This paper provides a brief introduction to high-density interconnect (HDI) technology and its implementation on printed circuit boards (PCBs). The advantages and challenges of implementing 10-Gbps signal transmission on high-density interconnect boards are discussed in detail. The advantages (e.g., smaller via dimension and via stub removal) and challenges (e.g., crosstalk due to smaller interpair separation) of HDI are studied by analyzing the S-parameter, time-domain reflectometry (TDR), and transmission-line eye diagrams obtained by three-dimensional electromagnetic modeling (3DEM) and two-dimensional electromagnetic modeling (2DEM) using Mentor Graphics HyperLynx and Keysight Advanced Design System (ADS) electronic computer-aided design (ECAD) software. HDI outperforms conventional PCB technology in terms of signal integrity, but proper routing topology should be applied to overcome the challenge posed by crosstalk due to the tight spacing between traces.

  10. SEMICONDUCTOR TECHNOLOGY Development of spin-on-glass process for triple metal interconnects

    NASA Astrophysics Data System (ADS)

    Li, Peng; Wenbin, Zhao; Guozhang, Wang; Zongguang, Yu

    2010-12-01

    Spin-on-glass (SOG), an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization, is an alternative to silicon dioxide (SiO2) deposited using PECVD processes. However, its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits, particularly in university processing labs. This paper will show that a thin layer of CVD SiO2 and a curing temperature below the sintering temperature of the metal interconnect layer will promote adhesion, reduce gaps, and prevent cracking. Electron scanning microscope analysis has been used to demonstrate the success of the improved technique. This optimized process has been used in batches of double-poly, triple-metal CMOS wafer fabrication to date.

  11. Solid state remote circuit selector switch

    NASA Technical Reports Server (NTRS)

    Peterson, V. S.

    1970-01-01

    Remote switching circuit utilizes voltage logic to switch on desired circuit. Circuit controls rotating multi-range pressure transducers in jet engine testing and can be used in coded remote circuit activator where sequence of switching has to occur in defined length of time to prevent false or undesired circuit activation.

  12. Continuous epitaxial growth of extremely strong Cu6Sn5 textures at liquid-Sn/(111)Cu interface under temperature gradient

    NASA Astrophysics Data System (ADS)

    Zhong, Y.; Zhao, N.; Liu, C. Y.; Dong, W.; Qiao, Y. Y.; Wang, Y. P.; Ma, H. T.

    2017-11-01

    As the diameter of solder interconnects in three-dimensional integrated circuits (3D ICs) downsizes to several microns, how to achieve a uniform microstructure with thousands of interconnects on stacking chips becomes a critical issue in 3D IC manufacturing. We report a promising way for fabricating fully intermetallic interconnects with a regular grain morphology and a strong texture feature by soldering single crystal (111) Cu/Sn/polycrystalline Cu interconnects under the temperature gradient. Continuous epitaxial growth of η-Cu6Sn5 at cold end liquid-Sn/(111)Cu interfaces has been demonstrated. The resultant η-Cu6Sn5 grains show faceted prism textures with an intersecting angle of 60° and highly preferred orientation with their ⟨ 11 2 ¯ 0 ⟩ directions nearly paralleling to the direction of the temperature gradient. These desirable textures are maintained even after soldering for 120 min. The results pave the way for controlling the morphology and orientation of interfacial intermetallics in 3D packaging technologies.

  13. Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

    NASA Astrophysics Data System (ADS)

    Stinner, F. Scott

    As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with <10 micros stage delays, and NAND and NOR logic gates. In order to produce higher performance and more consistent transistors, we develop a new hybrid procedure for processing the CdSe nanocrystals. This procedure produces transistors with repeatable performance exceeding 40 cm2/Vs when fabricated on silicon wafers and 16 cm 2/vs when fabricated as part of photopatterned integrated circuits on Kapton substrates. In order to demonstrate the full potential of these transistors, methods to create high-frequency oscillators were developed. These methods allow for transistors to operate at higher voltages as well as provide a means for wirebonding to the Kapton substrate, both of which are required for operating and probing high-frequency oscillators. Simulations of this system show the potential for operation at MHz frequencies. Demonstration of these transistors in this frequency range would open the door for development of CdSe integrated circuits for high-performance sensor, display, and audio applications. To develop further applications of electronics on flexible substrates, procedures are developed for the integration of polychromatic displays on polyethylene terephthalate (PET) substrates and a commercial near field communication (NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

  14. Electronic filters, hearing aids and methods

    NASA Technical Reports Server (NTRS)

    Engebretson, A. Maynard (Inventor)

    1995-01-01

    An electronic filter for an electroacoustic system. The system has a microphone for generating an electrical output from external sounds and an electrically driven transducer for emitting sound. Some of the sound emitted by the transducer returns to the microphone means to add a feedback contribution to its electrical output. The electronic filter includes a first circuit for electronic processing of the electrical output of the microphone to produce a first signal. An adaptive filter, interconnected with the first circuit, performs electronic processing of the first signal to produce an adaptive output to the first circuit to substantially offset the feedback contribution in the electrical output of the microphone, and the adaptive filter includes means for adapting only in response to polarities of signals supplied to and from the first circuit. Other electronic filters for hearing aids, public address systems and other electroacoustic systems, as well as such systems and methods of operating them are also disclosed.

  15. Electronic filters, hearing aids and methods

    NASA Technical Reports Server (NTRS)

    Engebretson, A. Maynard (Inventor); O'Connell, Michael P. (Inventor); Zheng, Baohua (Inventor)

    1991-01-01

    An electronic filter for an electroacoustic system. The system has a microphone for generating an electrical output from external sounds and an electrically driven transducer for emitting sound. Some of the sound emitted by the transducer returns to the microphone means to add a feedback contribution to its electical output. The electronic filter includes a first circuit for electronic processing of the electrical output of the microphone to produce a filtered signal. An adaptive filter, interconnected with the first circuit, performs electronic processing of the filtered signal to produce an adaptive output to the first circuit to substantially offset the feedback contribution in the electrical output of the microphone, and the adaptive filter includes means for adapting only in response to polarities of signals supplied to and from the first circuit. Other electronic filters for hearing aids, public address systems and other electroacoustic systems, as well as such systems, and methods of operating them are also disclosed.

  16. Large-scale, high-density (up to 512 channels) recording of local circuits in behaving animals

    PubMed Central

    Berényi, Antal; Somogyvári, Zoltán; Nagy, Anett J.; Roux, Lisa; Long, John D.; Fujisawa, Shigeyoshi; Stark, Eran; Leonardo, Anthony; Harris, Timothy D.

    2013-01-01

    Monitoring representative fractions of neurons from multiple brain circuits in behaving animals is necessary for understanding neuronal computation. Here, we describe a system that allows high-channel-count recordings from a small volume of neuronal tissue using a lightweight signal multiplexing headstage that permits free behavior of small rodents. The system integrates multishank, high-density recording silicon probes, ultraflexible interconnects, and a miniaturized microdrive. These improvements allowed for simultaneous recordings of local field potentials and unit activity from hundreds of sites without confining free movements of the animal. The advantages of large-scale recordings are illustrated by determining the electroanatomic boundaries of layers and regions in the hippocampus and neocortex and constructing a circuit diagram of functional connections among neurons in real anatomic space. These methods will allow the investigation of circuit operations and behavior-dependent interregional interactions for testing hypotheses of neural networks and brain function. PMID:24353300

  17. Spiers Memorial Lecture. Molecular mechanics and molecular electronics.

    PubMed

    Beckman, Robert; Beverly, Kris; Boukai, Akram; Bunimovich, Yuri; Choi, Jang Wook; DeIonno, Erica; Green, Johnny; Johnston-Halperin, Ezekiel; Luo, Yi; Sheriff, Bonnie; Stoddart, Fraser; Heath, James R

    2006-01-01

    We describe our research into building integrated molecular electronics circuitry for a diverse set of functions, and with a focus on the fundamental scientific issues that surround this project. In particular, we discuss experiments aimed at understanding the function of bistable rotaxane molecular electronic switches by correlating the switching kinetics and ground state thermodynamic properties of those switches in various environments, ranging from the solution phase to a Langmuir monolayer of the switching molecules sandwiched between two electrodes. We discuss various devices, low bit-density memory circuits, and ultra-high density memory circuits that utilize the electrochemical switching characteristics of these molecules in conjunction with novel patterning methods. We also discuss interconnect schemes that are capable of bridging the micrometre to submicrometre length scales of conventional patterning approaches to the near-molecular length scales of the ultra-dense memory circuits. Finally, we discuss some of the challenges associated with fabricated ultra-dense molecular electronic integrated circuits.

  18. Pulsed depressed collector

    DOEpatents

    Kemp, Mark A

    2015-11-03

    A high power RF device has an electron beam cavity, a modulator, and a circuit for feed-forward energy recovery from a multi-stage depressed collector to the modulator. The electron beam cavity include a cathode, an anode, and the multi-stage depressed collector, and the modulator is configured to provide pulses to the cathode. Voltages of the electrode stages of the multi-stage depressed collector are allowed to float as determined by fixed impedances seen by the electrode stages. The energy recovery circuit includes a storage capacitor that dynamically biases potentials of the electrode stages of the multi-stage depressed collector and provides recovered energy from the electrode stages of the multi-stage depressed collector to the modulator. The circuit may also include a step-down transformer, where the electrode stages of the multi-stage depressed collector are electrically connected to separate taps on the step-down transformer.

  19. The 20 kilovolt rocket borne electron accelerator. [equipment specifications

    NASA Technical Reports Server (NTRS)

    Harrison, R.

    1973-01-01

    The accelerator system is a preprogrammed multi-voltage system capable of operating at a current level of 1/2 ampere at the 20 kilovolt level. The five major functional areas which comprise this system are: (1) Silver zinc battery packs; (2) the electron gun assembly; (3) gun control and opening circuits; (4) the telemetry conditioning section; and (5) the power conversion section.

  20. Hybrid VLSI/QCA Architecture for Computing FFTs

    NASA Technical Reports Server (NTRS)

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  1. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bradt, M.; Behnke, M. R.; Bloethe, W.G.

    This paper presents a summary of the most important protection and coordination considerations for wind power plants. Short-circuit characteristics of both aggregate wind plant and individual wind turbine genera- tors, as well as general interconnection protection requirements are discussed. Many factors such as security, reliability, and safety are considered for proper conservative protection of the wind power plant and individual turbines.

  2. Status of the Consolidation of the LHC Superconducting Magnets and Circuits

    NASA Astrophysics Data System (ADS)

    Tock, J. Ph; Atieh, S.; Bodart, D.; Bordry, F.; Bourcey, N.; Cruikshank, P.; Dahlerup-Petersen, K.; Dalin, J. M.; Garion, C.; Musso, A.; Ostojic, R.; Perin, A.; Pojer, M.; Savary, F.; Scheuerlein, C.

    2014-05-01

    The first LHC long shutdown (LS1) started in February 2013. It was triggered by the need to consolidate the 13 kA splices between the superconducting magnets to allow the LHC to reach safely its design energy of 14 TeV center of mass. The final design of the consolidated splices is recalled. 1695 interconnections containing 10 170 splices have to be opened. In addition to the work on the 13 kA splices, the other interventions performed during the first long shut-down on all the superconducting circuits are described. All this work has been structured in a project, gathering about 280 persons. The opening of the interconnections started in April 2013 and consolidation works are planned to be completed by August 2014. This paper describes first the preparation phase with the building of the teams and the detailed planning of the operation. Then, it gives feedback from the worksite, namely lessons learnt and adaptations that were implemented, both from the technical and organizational points of view. Finally, perspectives for the completion of this consolidation campaign are given.

  3. Microwave evaluation of electromigration susceptibility in advanced interconnects

    NASA Astrophysics Data System (ADS)

    Sunday, Christopher E.; Veksler, Dmitry; Cheung, Kin C.; Obeng, Yaw S.

    2017-11-01

    Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs.

  4. An optogenetics- and imaging-assisted simultaneous multiple patch-clamp recording system for decoding complex neural circuits

    PubMed Central

    Wang, Guangfu; Wyskiel, Daniel R; Yang, Weiguo; Wang, Yiqing; Milbern, Lana C; Lalanne, Txomin; Jiang, Xiaolong; Shen, Ying; Sun, Qian-Quan; Zhu, J Julius

    2015-01-01

    Deciphering neuronal circuitry is central to understanding brain function and dysfunction, yet it remains a daunting task. To facilitate the dissection of neuronal circuits, a process requiring functional analysis of synaptic connections and morphological identification of interconnected neurons, we present here a method for stable simultaneous octuple patch-clamp recordings. This method allows physiological analysis of synaptic interconnections among 4–8 simultaneously recorded neurons and/or 10–30 sequentially recorded neurons, and it allows anatomical identification of >85% of recorded interneurons and >99% of recorded principal neurons. We describe how to apply the method to rodent tissue slices; however, it can be used on other model organisms. We also describe the latest refinements and optimizations of mechanics, electronics, optics and software programs that are central to the realization of a combined single- and two-photon microscopy–based, optogenetics- and imaging-assisted, stable, simultaneous quadruple–viguple patch-clamp recording system. Setting up the system, from the beginning of instrument assembly and software installation to full operation, can be completed in 3–4 d. PMID:25654757

  5. Roughness measurements on coupling structures for optical interconnections integrated on a printed circuit board

    NASA Astrophysics Data System (ADS)

    Hendrickx, Nina; Van Erps, Jürgen; Suyal, Himanshu; Taghizadeh, Mohammad; Thienpont, Hugo; Van Daele, Peter

    2006-04-01

    In this paper, laser ablation (at UGent), deep proton writing (at VUB) and laser direct writing (at HWU) are presented as versatile technologies that can be used for the fabrication of coupling structures for optical interconnections integrated on a printed circuit board (PCB). The optical layer, a highly cross-linked acrylate based polymer, is applied on an FR4 substrate. Both laser ablation and laser direct writing are used for the definition of arrays of multimode optical waveguides, which guide the light in the plane of the optical layer. In order to couple light vertically in/out of the plane of the optical waveguides, coupling structures have to be integrated into the optical layer. Out-of-plane turning mirrors, that deflect the light beam over 90°, are used for this purpose. The surface roughness and angle of three mirror configurations are evaluated: a laser ablated one that is integrated into the optical waveguide, a laser direct written one that is also directly written onto the waveguide and a DPW insert that is plugged into a cavity into the waveguiding layer.

  6. Smart repeater system for communications interoperability during multiagency law enforcement operations

    NASA Astrophysics Data System (ADS)

    Crutcher, Richard I.; Jones, R. W.; Moore, Michael R.; Smith, S. F.; Tolley, Alan L.; Rochelle, Robert W.

    1997-02-01

    A prototype 'smart' repeater that provides interoperability capabilities for radio communication systems in multi-agency and multi-user scenarios is being developed by the Oak Ridge National Laboratory. The smart repeater functions as a deployable communications platform that can be dynamically reconfigured to cross-link the radios of participating federal, state, and local government agencies. This interconnection capability improves the coordination and execution of multi-agency operations, including coordinated law enforcement activities and general emergency or disaster response scenarios. The repeater provides multiple channels of operation in the 30-50, 118-136, 138-174, and 403-512 MHz land mobile communications and aircraft bands while providing the ability to cross-connect among multiple frequencies, bands, modulation types, and encryption formats. Additionally, two telephone interconnects provide links to the fixed and cellular telephone networks. The 800- and 900-MHz bands are not supported by the prototype, but the modular design of the system accommodates future retrofits to extend frequency capabilities with minimal impact to the system. Configuration of the repeater is through a portable personal computer with a Windows-based graphical interface control screen that provides dynamic reconfiguration of network interconnections and formats.

  7. Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

    NASA Technical Reports Server (NTRS)

    Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

    2011-01-01

    Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

  8. Laser printed interconnects for flexible electronics

    NASA Astrophysics Data System (ADS)

    Pique, Alberto; Beniam, Iyoel; Mathews, Scott; Charipar, Nicholas

    Laser-induced forward transfer (LIFT) can be used to generate microscale 3D structures for interconnect applications non-lithographically. The laser printing of these interconnects takes place through aggregation of voxels of either molten metal or dispersed metallic nanoparticles. However, the resulting 3D structures do not achieve the bulk conductivity of metal interconnects of the same cross-section and length as those formed by wire bonding or tab welding. It is possible, however, to laser transfer entire structures using a LIFT technique known as lase-and-place. Lase-and-place allows whole components and parts to be transferred from a donor substrate onto a desired location with one single laser pulse. This talk will present the use of LIFT to laser print freestanding solid metal interconnects to connect individual devices into functional circuits. Furthermore, the same laser can bend or fold the thin metal foils prior to transfer, thus forming compliant 3D structures able to provide strain relief due to flexing or thermal mismatch. Examples of these laser printed 3D metallic bridges and their role in the development of next generation flexible electronics by additive manufacturing will be presented. This work was funded by the Office of Naval Research (ONR) through the Naval Research Laboratory Basic Research Program.

  9. Synaptic behaviors of a single metal-oxide-metal resistive device

    NASA Astrophysics Data System (ADS)

    Choi, Sang-Jun; Kim, Guk-Bae; Lee, Kyoobin; Kim, Ki-Hong; Yang, Woo-Young; Cho, Soohaeng; Bae, Hyung-Jin; Seo, Dong-Seok; Kim, Sang-Il; Lee, Kyung-Jin

    2011-03-01

    The mammalian brain is far superior to today's electronic circuits in intelligence and efficiency. Its functions are realized by the network of neurons connected via synapses. Much effort has been extended in finding satisfactory electronic neural networks that act like brains, i.e., especially the electronic version of synapse that is capable of the weight control and is independent of the external data storage. We demonstrate experimentally that a single metal-oxide-metal structure successfully stores the biological synaptic weight variations (synaptic plasticity) without any external storage node or circuit. Our device also demonstrates the reliability of plasticity experimentally with the model considering the time dependence of spikes. All these properties are embodied by the change of resistance level corresponding to the history of injected voltage-pulse signals. Moreover, we prove the capability of second-order learning of the multi-resistive device by applying it to the circuit composed of transistors. We anticipate our demonstration will invigorate the study of electronic neural networks using non-volatile multi-resistive device, which is simpler and superior compared to other storage devices.

  10. UWB multi-burst transmit driver for averaging receivers

    DOEpatents

    Dallum, Gregory E

    2012-11-20

    A multi-burst transmitter for ultra-wideband (UWB) communication systems generates a sequence of precisely spaced RF bursts from a single trigger event. There are two oscillators in the transmitter circuit, a gated burst rate oscillator and a gated RF burst or RF power output oscillator. The burst rate oscillator produces a relatively low frequency, i.e., MHz, square wave output for a selected transmit cycle, and drives the RF burst oscillator, which produces RF bursts of much higher frequency, i.e., GHz, during the transmit cycle. The frequency of the burst rate oscillator sets the spacing of the RF burst packets. The first oscillator output passes through a bias driver to the second oscillator. The bias driver conditions, e.g., level shifts, the signal from the first oscillator for input into the second oscillator, and also controls the length of each RF burst. A trigger pulse actuates a timing circuit, formed of a flip-flop and associated reset time delay circuit, that controls the operation of the first oscillator, i.e., how long it oscillates (which defines the transmit cycle).

  11. A proposed holistic approach to on-chip, off-chip, test, and package interconnections

    NASA Astrophysics Data System (ADS)

    Bartelink, Dirk J.

    1998-11-01

    The term interconnection has traditionally implied a `robust' connection from a transistor or a group of transistors in an IC to the outside world, usually a PC board. Optimum system utilization is done from outside the IC. As an alternative, this paper addresses `unimpeded' transistor-to-transistor interconnection aimed at reaching the high circuit densities and computational capabilities of neighboring IC's. In this view, interconnections are not made to some human-centric place outside the IC world requiring robustness—except for system input and output connections. This unimpeded interconnect style is currently available only through intra-chip signal traces in `system-on-a-chip' implementations, as exemplified by embedded DRAMs. Because the traditional off-chip penalty in performance and wiring density is so large, a merging of complex process technologies is the only option today. It is suggested that, for system integration to move forward, the traditional robustness requirement inherited from conventional packaging interconnect and IC manufacturing test must be discarded. Traditional system assembly from vendor parts requires robustness under shipping, inspection and assembly. The trend toward systems on a chip signifies willingness by semiconductor companies to design and fabricate whole systems in house, so that `in-house' chip-to-chip assembly is not beyond reach. In this scenario, bare chips never leave the controlled environment of the IC fabricator while the two major contributors to off-chip signal penalty, ESD protection and the need to source a 50-ohm test head, are avoided. With in-house assembly, ESD protection can be eliminated with the precautions already familiar in plasma etching. Test interconnection impacts the fundamentals of IC manufacturing, particularly with clock speeds approaching 1GHz, and cannot be an afterthought. It should be an integral part of the chip-to-chip interconnection bandwidth optimization, because—as we must recognize—test is also performed using IC's. A system interconnection is proposed using multiple chips fabricated with conventional silicon processes, including MEMS technology. The system resembles an MCM that can be joined without committing to final assembly to perform at-speed testing. 50-Ohm test probes never load the circuit; only intended neighboring chips are ever connected. A `back-plane' chip provides the connection layers for both inter- and intra-chip signals and also serves as the probe card, in analogy with membrane probes now used for single-chip testing. Intra-chip connections, which require complicated connections during test that exactly match the product, are then properly made and all waveforms and loading conditions under test will be identical to those of the product. The major benefit is that all front-end chip technologies can be merged—logic, memory, RF, even passives. ESD protection is required only on external system connections. Manufacturing test information will accurately characterize process faults and thus avoid the Known-Good-Die problem that has slowed the arrival of conventional MCM's.

  12. Effect of Sensors on the Reliability and Control Performance of Power Circuits in the Web of Things (WoT)

    PubMed Central

    Bae, Sungwoo; Kim, Myungchin

    2016-01-01

    In order to realize a true WoT environment, a reliable power circuit is required to ensure interconnections among a range of WoT devices. This paper presents research on sensors and their effects on the reliability and response characteristics of power circuits in WoT devices. The presented research can be used in various power circuit applications, such as energy harvesting interfaces, photovoltaic systems, and battery management systems for the WoT devices. As power circuits rely on the feedback from voltage/current sensors, the system performance is likely to be affected by the sensor failure rates, sensor dynamic characteristics, and their interface circuits. This study investigated how the operational availability of the power circuits is affected by the sensor failure rates by performing a quantitative reliability analysis. In the analysis process, this paper also includes the effects of various reconstruction and estimation techniques used in power processing circuits (e.g., energy harvesting circuits and photovoltaic systems). This paper also reports how the transient control performance of power circuits is affected by sensor interface circuits. With the frequency domain stability analysis and circuit simulation, it was verified that the interface circuit dynamics may affect the transient response characteristics of power circuits. The verification results in this paper showed that the reliability and control performance of the power circuits can be affected by the sensor types, fault tolerant approaches against sensor failures, and the response characteristics of the sensor interfaces. The analysis results were also verified by experiments using a power circuit prototype. PMID:27608020

  13. A Sharp methodology for VLSI layout

    NASA Astrophysics Data System (ADS)

    Bapat, Shekhar

    1993-01-01

    The layout problem for VLSI circuits is recognized as a very difficult problem and has been traditionally decomposed into the several seemingly independent sub-problems of placement, global routing, and detailed routing. Although this structure achieves a reduction in programming complexity, it is also typically accompanied by a reduction in solution quality. Most current placement research recognizes that the separation is artificial, and that the placement and routing problems should be solved ideally in tandem. We propose a new interconnection model, Sharp and an associated partitioning algorithm. The Sharp interconnection model uses a partitioning shape that roughly resembles the musical sharp 'number sign' and makes extensive use of pre-computed rectilinear Steiner trees. The model is designed to generate strategic routing information along with the partitioning results. Additionally, the Sharp model also generates estimates of the routing congestion. We also propose the Sharp layout heuristic that solves the layout problem in its entirety. The Sharp layout heuristic makes extensive use of the Sharp partitioning model. The use of precomputed Steiner tree forms enables the method to model accurately net characteristics. For example, the Steiner tree forms can model both the length of the net and more importantly its route. In fact, the tree forms are also appropriate for modeling the timing delays of nets. The Sharp heuristic works to minimize both the total layout area by minimizing total net length (thus reducing the total wiring area), and the congestion imbalances in the various channels (thus reducing the unused or wasted channel area). Our heuristic uses circuit element movements amongst the different partitioning blocks and selection of alternate minimal Steiner tree forms to achieve this goal. The objective function for the algorithm can be modified readily to include other important circuit constraints like propagation delays. The layout technique first computes a very high-level approximation of the layout solution (i.e., the positions of the circuit elements and the associated net routes). The approximate solution is alternately refined, objective function. The technique creates well defined sub-problems and offers intermediary steps that can be solved in parallel, as well as a parallel mechanism to merge the sub-problem solutions.

  14. Fabric-based active electrode design and fabrication for health monitoring clothing.

    PubMed

    Merritt, Carey R; Nagle, H Troy; Grant, Edward

    2009-03-01

    In this paper, two versions of fabric-based active electrodes are presented to provide a wearable solution for ECG monitoring clothing. The first version of active electrode involved direct attachment of surface-mountable components to a textile screen-printed circuit using polymer thick film techniques. The second version involved attaching a much smaller, thinner, and less obtrusive interposer containing the active electrode circuitry to a simplified textile circuit. These designs explored techniques for electronic textile interconnection, chip attachment to textiles, and packaging of circuits on textiles for durability. The results from ECG tests indicate that the performance of each active electrode is comparable to commercial Ag/AgCl electrodes. The interposer-based active electrodes survived a five-cycle washing test while maintaining good signal integrity.

  15. Coaxial connector for use with printed circuit board edge connector

    DOEpatents

    Howard, Donald R.; MacGill, Robert A.

    1989-01-01

    A coaxial cable connector for interfacing with an edge connector for a printed circuit board whereby a coaxial cable can be interconnected with a printed circuit board through the edge connector. The coaxial connector includes a body having two leg portions extending from one side for receiving the edge connector therebetween, and a tubular portion extending from an opposing side for receiving a coaxial cable. A cavity within the body receives a lug of the edge connector and the center conductor of the coaxial cable. Adjacent lugs of the edge connector can be bend around the edge connector housing to function as spring-loaded contacts for receiving the coaxial connector. The lugs also function to facilitate shielding of the center conductor where fastened to the edge connector lug.

  16. Multiplex Superconducting Transmission Line for green power consolidation on a Smart Grid

    NASA Astrophysics Data System (ADS)

    McIntyre, P.; Gerity, J.; Kellams, J.; Sattarov, A.

    2017-12-01

    A multiplex superconducting transmission line (MSTL) is being developed for applications requiring interconnection of multi-MW electric power generation among a number of locations. MSTL consists of a cluster of many 2- or 3-conductor transmission lines within a coaxial cryostat envelope. Each line operates autonomously, so that the interconnection of multiple power loads can be done in a failure-tolerant network. Specifics of the electrical, mechanical, and cryogenic design are presented. The consolidation of transformation and conditioning and the failure-tolerant interconnects have the potential to offer important benefit for the green energy components of a Smart Grid.

  17. Adaptive Code Division Multiple Access Protocol for Wireless Network-on-Chip Architectures

    NASA Astrophysics Data System (ADS)

    Vijayakumaran, Vineeth

    Massive levels of integration following Moore's Law ushered in a paradigm shift in the way on-chip interconnections were designed. With higher and higher number of cores on the same die traditional bus based interconnections are no longer a scalable communication infrastructure. On-chip networks were proposed enabled a scalable plug-and-play mechanism for interconnecting hundreds of cores on the same chip. Wired interconnects between the cores in a traditional Network-on-Chip (NoC) system, becomes a bottleneck with increase in the number of cores thereby increasing the latency and energy to transmit signals over them. Hence, there has been many alternative emerging interconnect technologies proposed, namely, 3D, photonic and multi-band RF interconnects. Although they provide better connectivity, higher speed and higher bandwidth compared to wired interconnects; they also face challenges with heat dissipation and manufacturing difficulties. On-chip wireless interconnects is one other alternative proposed which doesn't need physical interconnection layout as data travels over the wireless medium. They are integrated into a hybrid NOC architecture consisting of both wired and wireless links, which provides higher bandwidth, lower latency, lesser area overhead and reduced energy dissipation in communication. However, as the bandwidth of the wireless channels is limited, an efficient media access control (MAC) scheme is required to enhance the utilization of the available bandwidth. This thesis proposes using a multiple access mechanism such as Code Division Multiple Access (CDMA) to enable multiple transmitter-receiver pairs to send data over the wireless channel simultaneously. It will be shown that such a hybrid wireless NoC with an efficient CDMA based MAC protocol can significantly increase the performance of the system while lowering the energy dissipation in data transfer. In this work it is shown that the wireless NoC with the proposed CDMA based MAC protocol outperformed the wired counterparts and several other wireless architectures proposed in literature in terms of bandwidth and packet energy dissipation. Significant gains were observed in packet energy dissipation and bandwidth even with scaling the system to higher number of cores. Non-uniform traffic simulations showed that the proposed CDMA-WiNoC was consistent in bandwidth across all traffic patterns. It is also shown that the CDMA based MAC scheme does not introduce additional reliability concerns in data transfer over the on-chip wireless interconnects.

  18. Multi-regulatory network of ROS: the interconnection of ROS, PGC-1 alpha, and AMPK-SIRT1 during exercise.

    PubMed

    Thirupathi, Anand; de Souza, Claudio Teodoro

    2017-11-01

    Transcriptional factors are easily susceptible to any stimuli, including exercise. Exercise can significantly influence PGC-1 α and AMPK-SIRT1 pathway, as it is involved in the regulation of energy metabolism and mitochondrial biogenesis. Exercise is a major energy deprivation process by which many of transcription factors get tuned positively. However, how transcription factors help to boost the antioxidant defense system at cellular level is elusive. It is well known that physical exercise can induce reactive oxygen species, but how these reactive oxygen species can help to regulate multiple transcription factors during exercise is an important area to be discussed yet. This review mainly focuses on interconnecting role of PGC-1 α and AMPK-SIRT1 pathway during exercise and how these proteins are getting tuned by reactive oxygen species in exercise condition.

  19. Multi-crystalline II-VI based multijunction solar cells and modules

    DOEpatents

    Hardin, Brian E.; Connor, Stephen T.; Groves, James R.; Peters, Craig H.

    2015-06-30

    Multi-crystalline group II-VI solar cells and methods for fabrication of same are disclosed herein. A multi-crystalline group II-VI solar cell includes a first photovoltaic sub-cell comprising silicon, a tunnel junction, and a multi-crystalline second photovoltaic sub-cell. A plurality of the multi-crystalline group II-VI solar cells can be interconnected to form low cost, high throughput flat panel, low light concentration, and/or medium light concentration photovoltaic modules or devices.

  20. Enhancing Image Processing Performance for PCID in a Heterogeneous Network of Multi-core Processors

    DTIC Science & Technology

    2009-09-01

    TFLOPS of Playstation 3 (PS3) nodes with IBM Cell Broadband Engine multi-cores and 15 dual-quad Xeon head nodes. The interconnect fabric includes... 4   3. INFORMATION MANAGEMENT FOR PARALLELIZATION AND...STREAMING............................................................. 7  4 . RESULTS

  1. Experimental observation of sub-terahertz backward-wave amplification in a multi-level microfabricated slow-wave circuit

    NASA Astrophysics Data System (ADS)

    Baik, Chan-Wook; Ahn, Ho Young; Kim, Yongsung; Lee, Jooho; Hong, Seogwoo; Lee, Sang Hun; Choi, Jun Hee; Kim, Sunil; Jeon, So-Yeon; Yu, SeGi; Collins, George; Read, Michael E.; Lawrence Ives, R.; Kim, Jong Min; Hwang, Sungwoo

    2015-11-01

    In our earlier paper dealing with dispersion retrieval from ultra-deep, reactive-ion-etched, slow-wave circuits on silicon substrates, it was proposed that splitting high-aspect-ratio circuits into multilevels enabled precise characterization in sub-terahertz frequency regime. This achievement prompted us to investigate beam-wave interaction through a vacuum-sealed integration with a 15-kV, 85-mA, thermionic, electron gun. Our experimental study demonstrates sub-terahertz, backward-wave amplification driven by an external oscillator. The measured output shows a frequency downshift, as well as power amplification, from beam loading even with low beam perveance. This offers a promising opportunity for the development of terahertz radiation sources, based on silicon technologies.

  2. Experimental observation of sub-terahertz backward-wave amplification in a multi-level microfabricated slow-wave circuit

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Baik, Chan-Wook, E-mail: cw.baik@samsung.com; Ahn, Ho Young; Kim, Yongsung

    2015-11-09

    In our earlier paper dealing with dispersion retrieval from ultra-deep, reactive-ion-etched, slow-wave circuits on silicon substrates, it was proposed that splitting high-aspect-ratio circuits into multilevels enabled precise characterization in sub-terahertz frequency regime. This achievement prompted us to investigate beam-wave interaction through a vacuum-sealed integration with a 15-kV, 85-mA, thermionic, electron gun. Our experimental study demonstrates sub-terahertz, backward-wave amplification driven by an external oscillator. The measured output shows a frequency downshift, as well as power amplification, from beam loading even with low beam perveance. This offers a promising opportunity for the development of terahertz radiation sources, based on silicon technologies.

  3. Energy Dissipation and Transport in Carbon Nanotube Devices

    NASA Astrophysics Data System (ADS)

    Pop, Eric

    2011-03-01

    Power consumption is a significant challenge in electronics, often limiting the performance of integrated circuits from mobile devices to massive data centers. Carbon nanotubes have emerged as potentially energy-efficient future devices and interconnects, with both large mobility and thermal conductivity. This talk will focus on understanding and controlling energy dissipation [1-3] and transport [4-6] in carbon nanotubes, with applications to low-energy devices, interconnects, heat sinks, and memory elements. Experiments have been used to gain new insight into the fundamental behavior of such devices, and to better inform practical device models. The results suggest much room for energy optimization in nanoelectronics through the design of geometry, interfaces, and materials..

  4. Low cost solar array project production process and equipment task: A Module Experimental Process System Development Unit (MEPSDU)

    NASA Technical Reports Server (NTRS)

    1981-01-01

    Several major modifications were made to the design presented at the PDR. The frame was deleted in favor of a "frameless" design which will provide a substantially improved cell packing factor. Potential shaded cell damage resulting from operation into a short circuit can be eliminated by a change in the cell series/parallel electrical interconnect configuration. The baseline process sequence defined for the MEPSON was refined and equipment design and specification work was completed. SAMICS cost analysis work accelerated, format A's were prepared and computer simulations completed. Design work on the automated cell interconnect station was focused on bond technique selection experiments.

  5. A flexible CPW package for a 30 GHz MMIC amplifier. [coplanar waveguide

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.; Taub, Susan R.

    1992-01-01

    A novel package, which consists of a carrier housing, has been developed for monolithic-millimeter wave Integrated Circuit amplifiers which operate at 30 giga-Hz. The carrier has coplanar waveguide (CPW) interconnects and provides heat-sinking, tuning, and cascading capabilities. The housing provides electrical isolation, mechanical protection and a feed-thru for biasing.

  6. Nanoprobe studies: Electrical transport in carbon nanotubes and crystal structure of aluminum nitride surfaces

    NASA Astrophysics Data System (ADS)

    Biswas, Sujit Kumar

    Nanoprobes are an extraordinary set of experimental tools that allow fabrication, manipulation, and measurement in nano-scale systems. The primary use of a nanoprobe for imaging tiny objects is supplemented by powerful electrical techniques, namely scanning surface potential microscopy and current sensing atomic force microscopy. They allow us to measure potential, and current in carbon nanotube circuits. Nanoprobes are superior to conventional two- or four-probe measurements because they can provide spatial information of local electronic properties. This makes them highly attractive in studying junctions and contacts with carbon nanotubes. We have studied single-walled carbon nanotube circuits, forming junctions to other nanotubes. The experimental results indicate that these junctions act like potential barriers of about 50 meV that can confine electrons with an effective mass of 0.003 me , within nanotube channels of length 0.5 mum lying in-between two such potential barriers. This leads to quantization of the channel, forming a resonant tunneling structure. We have also found that single-walled nanotubes have phase coherence lengths of the order of 1 mum. This leads to situations where the electron interference effects at scattering centers need to be considered. We have seen direct evidence of this, in the non-linear resistance increase within nanotubes with few defects. Ambipolar transistor behavior was measured in a p-type single-walled nanotube circuit that showed electron injection across the Schottky junction at high positive bias. We have also studied multi-walled carbon nanotube circuits using scanning potential microscopy, and found that a back gate potential can vary the resistance of the channel. Vertical nanotube arrays, suitable for interconnects, were also measured. These hollow multi-walled nanotube channels were about 45 nm in diameter, and 50 mum in length, fabricated in an anodized alumina template. We found that these structures could sustain current densities greater than 105 A/cm2. Conventional use of nanoprobes in imaging aluminum nitride surfaces displayed curious step bunching structures. We have used an innovative analysis technique with which the bulk lattice constant of the crystal was measured to an accuracy of about 4% of X-ray crystallography value of 0.497 nm. In addition, this technique showed that there were regions on the surface that had a larger lattice parameter of 0.64 nm, which we interpreted to be due to a variation in the chemical composition of the surface such as oxide formation. We believe that this technique may prove useful as a study of chemical-composition variations on a surface as well as relaxation of the surface layer.

  7. Increasing component functionality via multi-process additive manufacturing

    NASA Astrophysics Data System (ADS)

    Coronel, Jose L.; Fehr, Katherine H.; Kelly, Dominic D.; Espalin, David; Wicker, Ryan B.

    2017-05-01

    Additively manufactured components, although extensively customizable, are often limited in functionality. Multi-process additive manufacturing (AM) grants the ability to increase the functionality of components via subtractive manufacturing, wire embedding, foil embedding and pick and place. These processes are scalable to include several platforms ranging from desktop to large area printers. The Multi3D System is highlighted, possessing the capability to perform the above mentioned processes, all while transferring a fabricated component with a robotic arm. Work was conducted to fabricate a patent inspired, printed missile seeker. The seeker demonstrated the advantage of multi-process AM via introduction of the pick and place process. Wire embedding was also explored, with the successful interconnect of two layers of embedded wires in different planes. A final demonstration of a printed contour bracket, served to show the reduction of surface roughness on a printed part is 87.5% when subtractive manufacturing is implemented in tandem with AM. Functionality of the components on all the cases was improved. Results included optical components embedded within the printed housing, wires embedded with interconnection, and reduced surface roughness. These results highlight the improved functionality of components through multi-process AM, specifically through work conducted with the Multi3D System.

  8. Comparing SiGe HBT Amplifier Circuits for Fast Single-shot Spin Readout

    NASA Astrophysics Data System (ADS)

    England, Troy; Curry, Matthew; Carr, Stephen; Mounce, Andrew; Jock, Ryan; Sharma, Peter; Bureau-Oxton, Chloe; Rudolph, Martin; Hardin, Terry; Carroll, Malcolm

    Fast, low-power quantum state readout is one of many challenges facing quantum information processing. Single electron transistors (SETs) are potentially fast, sensitive detectors for performing spin readout. From a circuit perspective, however, their output impedance and nonlinear conductance are ill suited to drive the parasitic capacitance of coaxial conductors used in cryogenic environments, necessitating a cryogenic amplification stage. We will compare two amplifiers based on single-transistor circuits implemented with silicon germanium heterojunction bipolar transistors. Both amplifiers provide gain at low power levels, but the dynamics of each circuit vary significantly. We will explore the gain mechanisms, linearity, and noise of each circuit and explain the situations in which each amplifier is best used. This work was performed, in part, at the Center for Integrated Nanotechnologies, a U.S. DOE Office of Basic Energy Sciences user facility. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  9. A Phase-Locked Loop Epilepsy Network Emulator

    PubMed Central

    Watson, P.D.; Horecka, K. M.; Cohen, N.J.; Ratnam, R.

    2015-01-01

    Most seizure forecasting employs statistical learning techniques that lack a representation of the network interactions that give rise to seizures. We present an epilepsy network emulator (ENE) that uses a network of interconnected phase-locked loops (PLLs) to model synchronous, circuit-level oscillations between electrocorticography (ECoG) electrodes. Using ECoG data from a canine-epilepsy model (Davis et al. 2011) and a physiological entropy measure (approximate entropy or ApEn, Pincus 1995), we demonstrate the entropy of the emulator phases increases dramatically during ictal periods across all ECoG recording sites and across all animals in the sample. Further, this increase precedes the observable voltage spikes that characterize seizure activity in the ECoG data. These results suggest that the ENE is sensitive to phase-domain information in the neural circuits measured by ECoG and that an increase in the entropy of this measure coincides with increasing likelihood of seizure activity. Understanding this unpredictable phase-domain electrical activity present in ECoG recordings may provide a target for seizure detection and feedback control. PMID:26664133

  10. A single-layer platform for Boolean logic and arithmetic through DNA excision in mammalian cells

    PubMed Central

    Weinberg, Benjamin H.; Hang Pham, N. T.; Caraballo, Leidy D.; Lozanoski, Thomas; Engel, Adrien; Bhatia, Swapnil; Wong, Wilson W.

    2017-01-01

    Genetic circuits engineered for mammalian cells often require extensive fine-tuning to perform their intended functions. To overcome this problem, we present a generalizable biocomputing platform that can engineer genetic circuits which function in human cells with minimal optimization. We used our Boolean Logic and Arithmetic through DNA Excision (BLADE) platform to build more than 100 multi-input-multi-output circuits. We devised a quantitative metric to evaluate the performance of the circuits in human embryonic kidney and Jurkat T cells. Of 113 circuits analysed, 109 functioned (96.5%) with the correct specified behavior without any optimization. We used our platform to build a three-input, two-output Full Adder and six-input, one-output Boolean Logic Look Up Table. We also used BLADE to design circuits with temporal small molecule-mediated inducible control and circuits that incorporate CRISPR/Cas9 to regulate endogenous mammalian genes. PMID:28346402

  11. Seeking a unified framework for cerebellar function and dysfunction: from circuit operations to cognition

    PubMed Central

    D'Angelo, Egidio; Casali, Stefano

    2013-01-01

    Following the fundamental recognition of its involvement in sensory-motor coordination and learning, the cerebellum is now also believed to take part in the processing of cognition and emotion. This hypothesis is recurrent in numerous papers reporting anatomical and functional observations, and it requires an explanation. We argue that a similar circuit structure in all cerebellar areas may carry out various operations using a common computational scheme. On the basis of a broad review of anatomical data, it is conceivable that the different roles of the cerebellum lie in the specific connectivity of the cerebellar modules, with motor, cognitive, and emotional functions (at least partially) segregated into different cerebro-cerebellar loops. We here develop a conceptual and operational framework based on multiple interconnected levels (a meta-levels hypothesis): from cellular/molecular to network mechanisms leading to generation of computational primitives, thence to high-level cognitive/emotional processing, and finally to the sphere of mental function and dysfunction. The main concept explored is that of intimate interplay between timing and learning (reminiscent of the “timing and learning machine” capabilities long attributed to the cerebellum), which reverberates from cellular to circuit mechanisms. Subsequently, integration within large-scale brain loops could generate the disparate cognitive/emotional and mental functions in which the cerebellum has been implicated. We propose, therefore, that the cerebellum operates as a general-purpose co-processor, whose effects depend on the specific brain centers to which individual modules are connected. Abnormal functioning in these loops could eventually contribute to the pathogenesis of major brain pathologies including not just ataxia but also dyslexia, autism, schizophrenia, and depression. PMID:23335884

  12. A novel anti-theft security system for photovoltaic modules

    NASA Astrophysics Data System (ADS)

    Khan, Wasif Ali; Lim, Boon-Han; Lai, An-Chow; Chong, Kok-Keong

    2017-04-01

    Solar farms are considered as easy target for thieves because of insufficient protection measures. Existing anti-theft approaches are based on system level and are not very preventive and efficient because these can be bypassed with some technical knowledge. Additionally, it is difficult for security guards to tackle them as robbers come in a form of a gang equipped with heavy weapons. In this paper, a low power auto shut-off and non-destructive system is proposed for photovoltaic (PV) modules to achieve better level of security at module level. In proposed method, the power generation function of the PV module will be shut-off internally and cannot be re-activated by unauthorized personnel, in the case of theft. Hence, the PV module will not be functional even sold to new customers. The system comprises of a microcontroller, a low power position sensor, a controllable semiconductor switch and a wireless reactive-able system. The anti-theft system is developed to be laminated inside PV module and will be interconnected with solar cells so it becomes difficult for thieves to temper. The position of PV module is retrieved by position sensor and stored in a microcontroller as an initial reference value. Microcontroller uses this stored reference value to control power supply of PV module via power switch. The stored reference value can be altered using wireless circuitry by following authentication protocol. It makes the system non-destructive as anti-theft function can be reset again by authorized personnel, if it is recovered after theft or moved for maintenance purposes. The research component includes the design of a position sensing circuit, an auto shut-off circuit, a reactive-able wireless security protection algorithm and finally the integration of the multiple circuits.

  13. Brillouin light scattering studies on the mechanical properties of ultrathin, porous low-K dielectric films

    NASA Astrophysics Data System (ADS)

    Zhou, Wei; Sooryakumar, R.; King, Sean

    2010-03-01

    Low K dielectrics have predominantly replaced silicon dioxide as the interlayer dielectric material for interconnects in state of the art integrated circuits. To further reduce interconnect resistance-capacitance (RC) delays, additional reductions in the K for these low-K materials is being pursued by the introduction of controlled levels of porosity. The main challenge for porous low-K dielectrics is the substantial reduction in mechanical properties that is accompanied by the increased pore volume content needed to reduce K. We report on the application of the nondestructive Brillouin light scattering technique to monitor and characterize the mechanical properties of these porous films at thicknesses well below 200 nm that are pertinent to present applications. Observation of longitudinal and transverse standing wave acoustic resonances and the dispersion that accompany their transformation into traveling waves with finite in-plane wave vectors provides for the principal elastic constants that completely characterize the mechanical properties of these porous films. The mode amplitudes of the standing waves, their variation within the film, and the calculated Brillouin intensities account for most aspects of the spectra. The resulting elastic constants are compared with corresponding values obtained from other experimental techniques.

  14. A direct modulated optical link for MRI RF receive coil interconnection.

    PubMed

    Yuan, Jing; Wei, Juan; Shen, G X

    2007-11-01

    Optical glass fiber is a promising alternative to traditional coaxial cables for MRI RF receive coil interconnection to avoid any crosstalk and electromagnetic interference between multiple channels. A direct modulated optical link is proposed for MRI coil interconnection in this paper. The link performances of power gain, frequency response and dynamic range are measured. Phantom and in vivo human head images have been demonstrated by the connection of this direct modulated optical link to a head coil on a 0.3T MRI scanner for the first time. Comparable image qualities to coaxial cable link verify the feasibility of using the optical link for imaging with minor modification on the existing scanners. This optical link could also be easily extended for multi-channel array interconnections at high field of 1.5 T.

  15. Feedforward and feedback inhibition in neostriatal GABAergic spiny neurons.

    PubMed

    Tepper, James M; Wilson, Charles J; Koós, Tibor

    2008-08-01

    There are two distinct inhibitory GABAergic circuits in the neostriatum. The feedforward circuit consists of a relatively small population of GABAergic interneurons that receives excitatory input from the neocortex and exerts monosynaptic inhibition onto striatal spiny projection neurons. The feedback circuit comprises the numerous spiny projection neurons and their interconnections via local axon collaterals. This network has long been assumed to provide the majority of striatal GABAergic inhibition and to sharpen and shape striatal output through lateral inhibition, producing increased activity in the most strongly excited spiny cells at the expense of their less strongly excited neighbors. Recent results, mostly from recording experiments of synaptically connected pairs of neurons, have revealed that the two GABAergic circuits differ markedly in terms of the total number of synapses made by each, the strength of the postsynaptic response detected at the soma, the extent of presynaptic convergence and divergence and the net effect of the activation of each circuit on the postsynaptic activity of the spiny neuron. These data have revealed that the feedforward inhibition is powerful and widespread, with spiking in a single interneuron being capable of significantly delaying or even blocking the generation of spikes in a large number of postsynaptic spiny neurons. In contrast, the postsynaptic effects of spiking in a single presynaptic spiny neuron on postsynaptic spiny neurons are weak when measured at the soma, and unable to significantly affect spike timing or generation. Further, reciprocity of synaptic connections between spiny neurons is only rarely observed. These results suggest that the bulk of the fast inhibition that has the strongest effects on spiny neuron spike timing comes from the feedforward interneuronal system whereas the axon collateral feedback system acts principally at the dendrites to control local excitability as well as the overall level of activity of the spiny neuron.

  16. Formation stability analysis of unmanned multi-vehicles under interconnection topologies

    NASA Astrophysics Data System (ADS)

    Yang, Aolei; Naeem, Wasif; Fei, Minrui

    2015-04-01

    In this paper, the overall formation stability of an unmanned multi-vehicle is mathematically presented under interconnection topologies. A novel definition of formation error is first given and followed by the proposed formation stability hypothesis. Based on this hypothesis, a unique extension-decomposition-aggregation scheme is then employed to support the stability analysis for the overall multi-vehicle formation under a mesh topology. It is proved that the overall formation control system consisting of N number of nonlinear vehicles is not only asymptotically stable, but also exponentially stable in the sense of Lyapunov within a neighbourhood of the desired formation. This technique is shown to be applicable for a mesh topology but is equally applicable for other topologies. A simulation study of the formation manoeuvre of multiple Aerosonde UAVs (unmanned aerial vehicles), in 3-D space, is finally carried out verifying the achieved formation stability result.

  17. MPNACK: an optical switching scheme enabling the buffer-less reliable transmission

    NASA Astrophysics Data System (ADS)

    Yu, Xiaoshan; Gu, Huaxi; Wang, Kun; Xu, Meng; Guo, Yantao

    2016-01-01

    Optical data center networks are becoming an increasingly promising solution to solve the bottlenecks faced by electrical networks, such as low transmission bandwidth, high wiring complexity, and unaffordable power consumption. However, the optical circuit switching (OCS) network is not flexible enough to carry the traffic burst while the optical packet switching (OPS) network cannot solve the packet contention in an efficient way. To this end, an improved switching strategy named OPS with multi-hop Negative Acknowledgement (MPNACK) is proposed. This scheme uses a feedback mechanism, rather than the buffering structure, to handle the optical packet contention. The collided packet is treated as a NACK packet and sent back to the source server. When the sender receives this NACK packet, it knows a collision happens in the transmission path and a retransmission procedure is triggered. Overall, the OPS-NACK scheme enables a reliable transmission in the buffer-less optical network. Furthermore, with this scheme, the expensive and energy-hungry elements, optical or electrical buffers, can be removed from the optical interconnects, thus a more scalable and cost-efficient network can be constructed for cloud computing data centers.

  18. Wearable Wireless Telemetry System for Implantable BioMEMS Sensors

    NASA Technical Reports Server (NTRS)

    Simons, Rainee N.; Miranda, Felix A.; Wilson, Jeffrey D.; Simons, Renita E.

    2008-01-01

    Telemetry systems of a type that have been proposed for the monitoring of physiological functions in humans would include the following subsystems: Surgically implanted or ingested units that would comprise combinations of microelectromechanical systems (MEMS)- based sensors [bioMEMS sensors] and passive radio-frequency (RF) readout circuits that would include miniature loop antennas. Compact radio transceiver units integrated into external garments for wirelessly powering and interrogating the implanted or ingested units. The basic principles of operation of these systems are the same as those of the bioMEMS-sensor-unit/external-RFpowering- and-interrogating-unit systems described in "Printed Multi-Turn Loop Antennas for Biotelemetry" (LEW-17879-1) NASA Tech Briefs, Vol. 31, No. 6 (June 2007), page 48, and in the immediately preceding article, "Hand-Held Units for Short-Range Wireless Biotelemetry" (LEW-17483-1). The differences between what is reported here and what was reported in the cited prior articles lie in proposed design features and a proposed mode of operation. In a specific system of the type now proposed, the sensor unit would comprise mainly a capacitive MEMS pressure sensor located in the annular region of a loop antenna (more specifically, a square spiral inductor/ antenna), all fabricated as an integral unit on a high-resistivity silicon chip. The capacitor electrodes, the spiral inductor/antenna, and the conductor lines interconnecting them would all be made of gold. The dimensions of the sensor unit have been estimated to be about 110.4 mm. The external garment-mounted powering/ interrogating unit would include a multi-turn loop antenna and signal-processing circuits. During operation, this external unit would be positioned in proximity to the implanted or ingested unit to provide for near-field, inductive coupling between the loop antennas, which we have as the primary and secondary windings of an electrical transformer.

  19. Hot-Fire Test Results of an Oxygen/RP-2 Multi-Element Oxidizer-Rich Staged-Combustion Integrated Test Article

    NASA Technical Reports Server (NTRS)

    Hulka, J. R.; Protz, C. S.; Garcia, C. P.; Casiano, M. J.; Parton, J. A.

    2016-01-01

    As part of the Combustion Stability Tool Development project funded by the Air Force Space and Missile Systems Center, the NASA Marshall Space Flight Center was contracted to assemble and hot-fire test a multi-element integrated test article demonstrating combustion characteristics of an oxygen/hydrocarbon propellant oxidizer-rich staged-combustion engine thrust chamber. Such a test article simulates flow through the main injectors of oxygen/kerosene oxidizer-rich staged combustion engines such as the Russian RD-180 or NK-33 engines, or future U.S.-built engine systems such as the Aerojet-Rocketdyne AR-1 engine or the Hydrocarbon Boost program demonstration engine. For the thrust chamber assembly of the test article, several configurations of new main injectors, using relatively conventional gas-centered swirl coaxial injector elements, were designed and fabricated. The design and fabrication of these main injectors are described in a companion paper at this JANNAF meeting. New ablative combustion chambers were fabricated based on hardware previously used at NASA for testing at similar size and pressure. An existing oxygen/RP-1 oxidizer-rich subscale preburner injector from a previous NASA-funded program, along with existing and new inter-connecting hot gas duct hardware, were used to supply the oxidizer-rich combustion products to the oxidizer circuit of the main injector of the thrust chamber. Results from independent hot-fire tests of the preburner injector in a combustion chamber with a sonic throat are described in companion papers at this JANNAF conference. The resulting integrated test article - which includes the preburner, inter-connecting hot gas duct, main injector, and ablative combustion chamber - was assembled at Test Stand 116 at the East Test Area of the NASA Marshall Space Flight Center. The test article was well instrumented with static and dynamic pressure, temperature, and acceleration sensors to allow the collected data to be used for combustion analysis model development. Hot-fire testing was conducted with main combustion chamber pressures ranging from 1400 to 2100 psia, and main combustion chamber mixture ratios ranging from 2.4 to 2.9. Different levels of fuel film cooling injected from the injector face were examined ranging from none to about 12% of the total fuel flow. This paper presents the hot-fire test results of the integrated test article. Combustion performance, stability, thermal, and compatibility characteristics of both the preburner and the thrust chamber are described. Another companion paper at this JANNAF meeting includes additional and more detailed test data regarding the combustion dynamics and stability characteristics.

  20. Performance evaluation of multi-stratum resources integrated resilience for software defined inter-data center interconnect.

    PubMed

    Yang, Hui; Zhang, Jie; Zhao, Yongli; Ji, Yuefeng; Wu, Jialin; Lin, Yi; Han, Jianrui; Lee, Young

    2015-05-18

    Inter-data center interconnect with IP over elastic optical network (EON) is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resources integration among IP networks, optical networks and application stratums resources that allows to accommodate data center services. In view of this, this study extends to consider the service resilience in case of edge optical node failure. We propose a novel multi-stratum resources integrated resilience (MSRIR) architecture for the services in software defined inter-data center interconnect based on IP over EON. A global resources integrated resilience (GRIR) algorithm is introduced based on the proposed architecture. The MSRIR can enable cross stratum optimization and provide resilience using the multiple stratums resources, and enhance the data center service resilience responsiveness to the dynamic end-to-end service demands. The overall feasibility and efficiency of the proposed architecture is experimentally verified on the control plane of our OpenFlow-based enhanced SDN (eSDN) testbed. The performance of GRIR algorithm under heavy traffic load scenario is also quantitatively evaluated based on MSRIR architecture in terms of path blocking probability, resilience latency and resource utilization, compared with other resilience algorithms.

  1. Performance evaluation of multi-stratum resources integration based on network function virtualization in software defined elastic data center optical interconnect.

    PubMed

    Yang, Hui; Zhang, Jie; Ji, Yuefeng; Tian, Rui; Han, Jianrui; Lee, Young

    2015-11-30

    Data center interconnect with elastic optical network is a promising scenario to meet the high burstiness and high-bandwidth requirements of data center services. In our previous work, we implemented multi-stratum resilience between IP and elastic optical networks that allows to accommodate data center services. In view of this, this study extends to consider the resource integration by breaking the limit of network device, which can enhance the resource utilization. We propose a novel multi-stratum resources integration (MSRI) architecture based on network function virtualization in software defined elastic data center optical interconnect. A resource integrated mapping (RIM) scheme for MSRI is introduced in the proposed architecture. The MSRI can accommodate the data center services with resources integration when the single function or resource is relatively scarce to provision the services, and enhance globally integrated optimization of optical network and application resources. The overall feasibility and efficiency of the proposed architecture are experimentally verified on the control plane of OpenFlow-based enhanced software defined networking (eSDN) testbed. The performance of RIM scheme under heavy traffic load scenario is also quantitatively evaluated based on MSRI architecture in terms of path blocking probability, provisioning latency and resource utilization, compared with other provisioning schemes.

  2. "Generality of mis-fit"? The real-life difficulty of matching scales in an interconnected world.

    PubMed

    Keskitalo, E Carina H; Horstkotte, Tim; Kivinen, Sonja; Forbes, Bruce; Käyhkö, Jukka

    2016-10-01

    A clear understanding of processes at multiple scales and levels is of special significance when conceiving strategies for human-environment interactions. However, understanding and application of the scale concept often differ between administrative-political and ecological disciplines. These mirror major differences in potential solutions whether and how scales can, at all, be made congruent. As a result, opportunities of seeking "goodness-of-fit" between different concepts of governance should perhaps be reconsidered in the light of a potential "generality of mis-fit." This article reviews the interdisciplinary considerations inherent in the concept of scale in its ecological, as well as administrative-political, significance and argues that issues of how to manage "mis-fit" should be awarded more emphasis in social-ecological research and management practices. These considerations are exemplified by the case of reindeer husbandry in Fennoscandia. Whilst an indigenous small-scale practice, reindeer husbandry involves multi-level ecological and administrative-political complexities-complexities that we argue may arise in any multi-level system.

  3. Hybrid microcircuit metallization system for the SLL micro actuator

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hampy, R. E.; Knauss, G. L.; Komarek, E. E.

    1976-03-01

    A thin film technique developed for the SLL Micro Actuator in which both gold and aluminum can be incorporated on sapphire or fine grained alumina substrates in a two-level metallization system is described. Tungsten is used as a lateral transition metal permitting electrical contact between the gold and aluminum without the two metals coming in physical contact. Silicon dioxide serves as an insulator between the tungsten and aluminum for crossover purposes, and vias through the silicon dioxide permit interconnections where desired. Tungsten-gold is the first level conductor except at crossovers where tungsten only is used and aluminum is the secondmore » level conductor. Sheet resistances of the two levels can be as low as 0.01 ohm/square. Line widths and spaces as small as 0.025 mm can be attained. A second layer of silicon dioxide is deposited over the metallization and opened for all gold and aluminum bonding areas. The metallization system permits effective interconnection of a mixture of devices having both gold and aluminum terminations without creating undesirable gold-aluminum interfaces. Processing temperatures up to 400/sup 0/C can be tolerated for short times without effect on bondability, conductor, and insulator characteristics, thus permitting silicon-gold eutectic die attachment, component soldering, and higher temperatures during gold lead bonding. Tests conducted on special test pattern circuits indicate good stability over the temperature range -55 to +150/sup 0/C. Aging studies indicate no degradation in characteristics in tests of 500 h duration at 150/sup 0/C.« less

  4. Embedded optical interconnect technology in data storage systems

    NASA Astrophysics Data System (ADS)

    Pitwon, Richard C. A.; Hopkins, Ken; Milward, Dave; Muggeridge, Malcolm

    2010-05-01

    As both data storage interconnect speeds increase and form factors in hard disk drive technologies continue to shrink, the density of printed channels on the storage array midplane goes up. The dominant interconnect protocol on storage array midplanes is expected to increase to 12 Gb/s by 2012 thereby exacerbating the performance bottleneck in future digital data storage systems. The design challenges inherent to modern data storage systems are discussed and an embedded optical infrastructure proposed to mitigate this bottleneck. The proposed solution is based on the deployment of an electro-optical printed circuit board and active interconnect technology. The connection architecture adopted would allow for electronic line cards with active optical edge connectors to be plugged into and unplugged from a passive electro-optical midplane with embedded polymeric waveguides. A demonstration platform has been developed to assess the viability of embedded electro-optical midplane technology in dense data storage systems and successfully demonstrated at 10.3 Gb/s. Active connectors incorporate optical transceiver interfaces operating at 850 nm and are connected in an in-plane coupling configuration to the embedded waveguides in the midplane. In addition a novel method of passively aligning and assembling passive optical devices to embedded polymer waveguide arrays has also been demonstrated.

  5. Monolithic integrated high-T.sub.c superconductor-semiconductor structure

    NASA Technical Reports Server (NTRS)

    Barfknecht, Andrew T. (Inventor); Garcia, Graham A. (Inventor); Russell, Stephen D. (Inventor); Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Clayton, Stanley R. (Inventor)

    2000-01-01

    A method for the fabrication of active semiconductor and high-temperature superconducting device of the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

  6. Simulation by bondgraphs

    NASA Astrophysics Data System (ADS)

    Thoma, Jean Ulrich

    The fundamental principles and applications of the bond graph method, in which a system is represented on paper by letter elements and their interconnections (bonds), are presented in an introduction for engineering students. Chapters are devoted to simulation and graphical system models; bond graphs as networks for power and signal exchange; the simulation and design of mechanical engineering systems; the simulation of fluid power systems and hydrostatic devices; electrical circuits, drives, and components; practical procedures and problems of bond-graph-based numerical simulation; and applications to thermodynamics, chemistry, and biology. Also included are worked examples of applications to robotics, shocks and collisions, ac circuits, hydraulics, and a hydropneumatic fatigue-testing machine.

  7. Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent

    NASA Astrophysics Data System (ADS)

    Vandersypen, L. M. K.; Bluhm, H.; Clarke, J. S.; Dzurak, A. S.; Ishihara, R.; Morello, A.; Reilly, D. J.; Schreiber, L. R.; Veldhorst, M.

    2017-09-01

    Semiconductor spins are one of the few qubit realizations that remain a serious candidate for the implementation of large-scale quantum circuits. Excellent scalability is often argued for spin qubits defined by lithography and controlled via electrical signals, based on the success of conventional semiconductor integrated circuits. However, the wiring and interconnect requirements for quantum circuits are completely different from those for classical circuits, as individual direct current, pulsed and in some cases microwave control signals need to be routed from external sources to every qubit. This is further complicated by the requirement that these spin qubits currently operate at temperatures below 100 mK. Here, we review several strategies that are considered to address this crucial challenge in scaling quantum circuits based on electron spin qubits. Key assets of spin qubits include the potential to operate at 1 to 4 K, the high density of quantum dots or donors combined with possibilities to space them apart as needed, the extremely long-spin coherence times, and the rich options for integration with classical electronics based on the same technology.

  8. Ballistic One-Dimensional InAs Nanowire Cross-Junction Interconnects.

    PubMed

    Gooth, Johannes; Borg, Mattias; Schmid, Heinz; Schaller, Vanessa; Wirths, Stephan; Moselund, Kirsten; Luisier, Mathieu; Karg, Siegfried; Riel, Heike

    2017-04-12

    Coherent interconnection of quantum bits remains an ongoing challenge in quantum information technology. Envisioned hardware to achieve this goal is based on semiconductor nanowire (NW) circuits, comprising individual NW devices that are linked through ballistic interconnects. However, maintaining the sensitive ballistic conduction and confinement conditions across NW intersections is a nontrivial problem. Here, we go beyond the characterization of a single NW device and demonstrate ballistic one-dimensional (1D) quantum transport in InAs NW cross-junctions, monolithically integrated on Si. Characteristic 1D conductance plateaus are resolved in field-effect measurements across up to four NW-junctions in series. The 1D ballistic transport and sub-band splitting is preserved for both crossing-directions. We show that the 1D modes of a single injection terminal can be distributed into multiple NW branches. We believe that NW cross-junctions are well-suited as cross-directional communication links for the reliable transfer of quantum information as required for quantum computational systems.

  9. Optical Computers and Space Technology

    NASA Technical Reports Server (NTRS)

    Abdeldayem, Hossin A.; Frazier, Donald O.; Penn, Benjamin; Paley, Mark S.; Witherow, William K.; Banks, Curtis; Hicks, Rosilen; Shields, Angela

    1995-01-01

    The rapidly increasing demand for greater speed and efficiency on the information superhighway requires significant improvements over conventional electronic logic circuits. Optical interconnections and optical integrated circuits are strong candidates to provide the way out of the extreme limitations imposed on the growth of speed and complexity of nowadays computations by the conventional electronic logic circuits. The new optical technology has increased the demand for high quality optical materials. NASA's recent involvement in processing optical materials in space has demonstrated that a new and unique class of high quality optical materials are processible in a microgravity environment. Microgravity processing can induce improved orders in these materials and could have a significant impact on the development of optical computers. We will discuss NASA's role in processing these materials and report on some of the associated nonlinear optical properties which are quite useful for optical computers technology.

  10. Robot Serviced Space Facility

    NASA Technical Reports Server (NTRS)

    Purves, Lloyd R. (Inventor)

    1992-01-01

    A robot serviced space facility includes multiple modules which are identical in physical structure, but selectively differing in function. and purpose. Each module includes multiple like attachment points which are identically placed on each module so as to permit interconnection with immediately adjacent modules. Connection is made through like outwardly extending flange assemblies having identical male and female configurations for interconnecting to and locking to a complementary side of another flange. Multiple rows of interconnected modules permit force, fluid, data and power transfer to be accomplished by redundant circuit paths. Redundant modules of critical subsystems are included. Redundancy of modules and of interconnections results in a space complex with any module being removable upon demand, either for module replacement or facility reconfiguration. without eliminating any vital functions of the complex. Module replacement and facility assembly or reconfiguration are accomplished by a computer controlled articulated walker type robotic manipulator arm assembly having two identical end-effectors in the form of male configurations which are identical to those on module flanges and which interconnect to female configurations on other flanges. The robotic arm assembly moves along a connected set or modules by successively disconnecting, moving and reconnecting alternate ends of itself to a succession of flanges in a walking type maneuver. To transport a module, the robot keeps the transported module attached to one of its end-effectors and uses another flange male configuration of the attached module as a substitute end-effector during walking.

  11. Packaging Of Control Circuits In A Robot Arm

    NASA Technical Reports Server (NTRS)

    Kast, William

    1994-01-01

    Packaging system houses and connects control circuitry mounted on circuit boards within shoulder, upper section, and lower section of seven-degree-of-freedom robot arm. Has modular design that incorporates surface-mount technology, multilayer circuit boards, large-scale integrated circuits, and multi-layer flat cables between sections for compactness. Three sections of robot arm contain circuit modules in form of stardardized circuit boards. Each module contains two printed-circuit cards, one of each face.

  12. A family of neuromuscular stimulators with optical transcutaneous control.

    PubMed

    Jarvis, J C; Salmons, S

    1991-01-01

    A family of miniature implantable neuromuscular stimulators has been developed using surface-mounted Philips 4000-series integrated circuits. The electronic components are mounted by hand on printed circuits (platinum/gold on alumina) and the electrical connections are made by reflow soldering. The plastic integrated-circuit packages, ceramic resistors and metal interconnections are protected from the body fluids by a coating of biocompatible silicone rubber. This simple technology provides reliable function for at least 4 months under implanted conditions. The circuits have in common a single lithium cell power-supply (3.2 V) and an optical sensor which can be used to detect light flashes through the skin after the device has been implanted. This information channel may be used to switch the output of a device on or off, or to cycle through a series of pre-set programs. The devices are currently finding application in studies which provide an experimental basis for the clinical exploitation of electrically stimulated skeletal muscle in cardiac assistance, sphincter reconstruction or functional electrical stimulation of paralysed limbs.

  13. Aerosol-jet-printed, 1 volt H-bridge drive circuit on plastic with integrated electrochromic pixel.

    PubMed

    Ha, Mingjing; Zhang, Wei; Braga, Daniele; Renn, Michael J; Kim, Chris H; Frisbie, C Daniel

    2013-12-26

    In this report, we demonstrate a printed, flexible, and low-voltage circuit that successfully drives a polymer electrochromic (EC) pixel as large as 4 mm(2) that is printed on the same substrate. All of the key components of the drive circuitry, namely, resistors, capacitors, and transistors, were aerosol-jet-printed onto a plastic foil; metallic electrodes and interconnects were the only components prepatterned on the plastic by conventional photolithography. The large milliampere drive currents necessary to switch a 4 mm(2) EC pixel were controlled by printed electrolyte-gated transistors (EGTs) that incorporate printable ion gels for the gate insulator layers and poly(3-hexylthiophene) for the semiconductor channels. Upon application of a 1 V input pulse, the circuit switches the printed EC pixel ON (red) and OFF (blue) two times in approximately 4 s. The performance of the circuit and the behavior of the individual resistors, capacitors, EGTs, and the EC pixel are analyzed as functions of the printing parameters and operating conditions.

  14. Additive manufacturing of hybrid circuits

    DOE PAGES

    Bell, Nelson S.; Sarobol, Pylin; Cook, Adam; ...

    2016-03-26

    There is a rising interest in developing functional electronics using additively manufactured components. Considerations in materials selection and pathways to forming hybrid circuits and devices must demonstrate useful electronic function; must enable integration; and must complement the complex shape, low cost, high volume, and high functionality of structural but generally electronically passive additively manufactured components. This article reviews several emerging technologies being used in industry and research/development to provide integration advantages of fabricating multilayer hybrid circuits or devices. First, we review a maskless, noncontact, direct write (DW) technology that excels in the deposition of metallic colloid inks for electrical interconnects.more » Second, we review a complementary technology, aerosol deposition (AD), which excels in the deposition of metallic and ceramic powder as consolidated, thick conformal coatings and is additionally patternable through masking. As a result, we show examples of hybrid circuits/devices integrated beyond 2-D planes, using combinations of DW or AD processes and conventional, established processes.« less

  15. Development of the automatic test pattern generation for NPP digital electronic circuits using the degree of freedom concept

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Kim, D.S.; Seong, P.H.

    1995-08-01

    In this paper, an improved algorithm for automatic test pattern generation (ATG) for nuclear power plant digital electronic circuits--the combinational type of logic circuits is presented. For accelerating and improving the ATG process for combinational circuits the presented ATG algorithm has the new concept--the degree of freedom (DF). The DF, directly computed from the system descriptions such as types of gates and their interconnections, is the criterion to decide which among several alternate lines` logic values required along each path promises to be the most effective in order to accelerate and improve the ATG process. Based on the DF themore » proposed ATG algorithm is implemented in the automatic fault diagnosis system (AFDS) which incorporates the advanced fault diagnosis method of artificial intelligence technique, it is shown that the AFDS using the ATG algorithm makes Universal Card (UV Card) testing much faster than the present testing practice or by using exhaustive testing sets.« less

  16. Infrared-enhanced TV for fire detection

    NASA Technical Reports Server (NTRS)

    Hall, J. R.

    1978-01-01

    Closed-circuit television is superior to conventional smoke or heat sensors for detecting fires in large open spaces. Single TV camera scans entire area, whereas many conventional sensors and maze of interconnecting wiring might be required to get same coverage. Camera is monitored by person who would trip alarm if fire were detected, or electronic circuitry could process camera signal for fully-automatic alarm system.

  17. Flame Retardancy of Chemically Modified Lignin as Functional Additive to Epoxy Nanocomposites

    Treesearch

    John A. Howarter; Gamini P. Mendis; Alex N. Bruce; Jeffrey P. Youngblood; Mark A. Dietenberger; Laura Hasburgh

    2015-01-01

    Epoxy printed circuit boards are used in a variety of electronics applications as rigid, thermally stable substrates. Due to the propensity of components on the boards, such as batteries and interconnects, to fail and ignite the epoxy, flame retardant additives are required to minimize fire risk. Currently, industry uses brominated flame retardants, such as TBBPA, to...

  18. High bit rate mass data storage device

    NASA Technical Reports Server (NTRS)

    1973-01-01

    The HDDR-II mass data storage system consists of a Leach MTR 7114 recorder reproducer, a wire wrapped, integrated circuit flat plane and necessary power supplies for the flat plane. These units, with interconnecting cables and control panel are enclosed in a common housing mounted on casters. The electronics used in the HDDR-II double density decoding and encoding techniques are described.

  19. Initial results for the silicon monolithically interconnected solar cell product

    NASA Technical Reports Server (NTRS)

    Dinetta, L. C.; Shreve, K. P.; Cotter, J. E.; Barnett, A. M.

    1995-01-01

    This proprietary technology is based on AstroPower's electrostatic bonding and innovative silicon solar cell processing techniques. Electrostatic bonding allows silicon wafers to be permanently attached to a thermally matched glass superstrate and then thinned to final thicknesses less than 25 micron. These devices are based on the features of a thin, light-trapping silicon solar cell: high voltage, high current, light weight (high specific power) and high radiation resistance. Monolithic interconnection allows the fabrication costs on a per watt basis to be roughly independent of the array size, power or voltage, therefore, the cost effectiveness to manufacture solar cell arrays with output powers ranging from milliwatts up to four watts and output voltages ranging from 5 to 500 volts will be similar. This compares favorably to conventionally manufactured, commercial solar cell arrays, where handling of small parts is very labor intensive and costly. In this way, a wide variety of product specifications can be met using the same fabrication techniques. Prototype solar cells have demonstrated efficiencies greater than 11%. An open-circuit voltage of 5.4 volts, fill factor of 65%, and short-circuit current density of 28 mA/sq cm at AM1.5 illumination are typical. Future efforts are being directed to optimization of the solar cell operating characteristics as well as production processing. The monolithic approach has a number of inherent advantages, including reduced cost per interconnect and increased reliability of array connections. These features make this proprietary technology an excellent candidate for a large number of consumer products.

  20. High-performance, lattice-mismatched InGaAs/InP monolithic interconnected modules (MIMs)

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Fatemi, Navid S.; Wilt, David M.; Hoffman, Richard W., Jr.

    1998-10-01

    High performance, lattice-mismatched p/n InGaAs/lnP monolithic interconnected module (MIM) structures were developed for thermophotovoltaic (TPV) applications. A MIM device consists of several individual InGaAs photovoltaic (PV) cells series-connected on a single semi-insulating (S.I.) InP substrate. Both interdigitated and conventional (i.e., non-interdigitated) MIMs were fabricated. The energy bandgap (Eg) for these devices was 0.60 eV. A compositionally step-graded InPAs buffer was used to accommodate a lattice mismatch of 1.1% between the active InGaAs cell structure and the InP substrate. 1x1-cm, 15-cell, 0.60-eV MIMs demonstrated an open-circuit voltage (Voc) of 5.2 V (347 mV per cell) and a fill factor of 68.6%more » at a short-circuit current density (Jsc) of 2.0 A/cm{sup 2}, under flashlamp testing. The reverse saturation current density (Jo) was 1.6x10{sup {minus}6} A/cm{sup 2}. Jo values as low as 4.1x10{sup {minus}7} A/cm{sup 2} were also observed with a conventional planar cell geometry.« less

  1. Programmable single-cell mammalian biocomputers.

    PubMed

    Ausländer, Simon; Ausländer, David; Müller, Marius; Wieland, Markus; Fussenegger, Martin

    2012-07-05

    Synthetic biology has advanced the design of standardized control devices that program cellular functions and metabolic activities in living organisms. Rational interconnection of these synthetic switches resulted in increasingly complex designer networks that execute input-triggered genetic instructions with precision, robustness and computational logic reminiscent of electronic circuits. Using trigger-controlled transcription factors, which independently control gene expression, and RNA-binding proteins that inhibit the translation of transcripts harbouring specific RNA target motifs, we have designed a set of synthetic transcription–translation control devices that could be rewired in a plug-and-play manner. Here we show that these combinatorial circuits integrated a two-molecule input and performed digital computations with NOT, AND, NAND and N-IMPLY expression logic in single mammalian cells. Functional interconnection of two N-IMPLY variants resulted in bitwise intracellular XOR operations, and a combinatorial arrangement of three logic gates enabled independent cells to perform programmable half-subtractor and half-adder calculations. Individual mammalian cells capable of executing basic molecular arithmetic functions isolated or coordinated to metabolic activities in a predictable, precise and robust manner may provide new treatment strategies and bio-electronic interfaces in future gene-based and cell-based therapies.

  2. Arbitrary-Shaped Graphene-Based Planar Sandwich Supercapacitors on One Substrate with Enhanced Flexibility and Integration.

    PubMed

    Zheng, Shuanghao; Tang, Xingyan; Wu, Zhong-Shuai; Tan, Yuan-Zhi; Wang, Sen; Sun, Chenglin; Cheng, Hui-Ming; Bao, Xinhe

    2017-02-28

    The emerging smart power source-unitized electronics represent an utmost innovative paradigm requiring dramatic alteration from materials to device assembly and integration. However, traditional power sources with huge bottlenecks on the design and performance cannot keep pace with the revolutionized progress of shape-confirmable integrated circuits. Here, we demonstrate a versatile printable technology to fabricate arbitrary-shaped, printable graphene-based planar sandwich supercapacitors based on the layer-structured film of electrochemically exfoliated graphene as two electrodes and nanosized graphene oxide (lateral size of 100 nm) as a separator on one substrate. These monolithic planar supercapacitors not only possess arbitrary shapes, e.g., rectangle, hollow-square, "A" letter, "1" and "2" numbers, circle, and junction-wire shape, but also exhibit outstanding performance (∼280 F cm -3 ), excellent flexibility (no capacitance degradation under different bending states), and applicable scalability, which are far beyond those achieved by conventional technologies. More notably, such planar supercapacitors with superior integration can be readily interconnected in parallel and series, without use of metal interconnects and contacts, to modulate the output current and voltage of modular power sources for designable integrated circuits in various shapes and sizes.

  3. Microwave evaluation of electromigration susceptibility in advanced interconnects.

    PubMed

    Sunday, Christopher E; Veksler, Dmitry; Cheung, Kin C; Obeng, Yaw S

    2017-11-07

    Traditional metrology has been unable to adequately address the needs of the emerging integrated circuits (ICs) at the nano scale; thus, new metrology and techniques are needed. For example, the reliability challenges in fabrication need to be well understood and controlled to facilitate mass production of through-substrate-via (TSV) enabled three-dimensional integrated circuits (3D-ICs). This requires new approaches to the metrology. In this paper, we use the microwave propagation characteristics to study the reliability issues that precede the physical damage caused by electromigration in the Cu-filled TSVs. The pre-failure microwave insertion losses and group delay are dependent on both the device temperature and the amount of current forced through the devices-under-test. The microwave insertion losses increase with the increase in the test temperature, while the group delay increases with the increase in the forced direct current magnitude. The microwave insertion losses are attributed to the defect mobility at the Cu-TiN interface, and the group delay changes are due to resistive heating in the interconnects, which perturbs the dielectric properties of the cladding dielectrics of the copper fill in the TSVs. https://doi.org/10.1063/1.4992135.

  4. On Polymorphic Circuits and Their Design Using Evolutionary Algorithms

    NASA Technical Reports Server (NTRS)

    Stoica, Adrian; Zebulum, Ricardo; Keymeulen, Didier; Lohn, Jason; Clancy, Daniel (Technical Monitor)

    2002-01-01

    This paper introduces the concept of polymorphic electronics (polytronics) - referring to electronics with superimposed built-in functionality. A function change does not require switches/reconfiguration as in traditional approaches. Instead the change comes from modifications in the characteristics of devices involved in the circuit, in response to controls such as temperature, power supply voltage (VDD), control signals, light, etc. The paper illustrates polytronic circuits in which the control is done by temperature, morphing signals, and VDD respectively. Polytronic circuits are obtained by evolutionary design/evolvable hardware techniques. These techniques are ideal for the polytronics design, a new area that lacks design guidelines, know-how,- yet the requirements/objectives are easy to specify and test. The circuits are evolved/synthesized in two different modes. The first mode explores an unstructured space, in which transistors can be interconnected freely in any arrangement (in simulations only). The second mode uses a Field Programmable Transistor Array (FPTA) model, and the circuit topology is sought as a mapping onto a programmable architecture (these experiments are performed both in simulations and on FPTA chips). The experiments demonstrated the synthesis. of polytronic circuits by evolution. The capacity of storing/hiding "extra" functions provides for watermark/invisible functionality, thus polytronics may find uses in intelligence/security applications.

  5. Design of a 0.13-μm CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems

    NASA Astrophysics Data System (ADS)

    Morgado, Alonso; del Río, Rocío; de la Rosa, José M.

    2007-05-01

    This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multi-standard wireless terminals, capable of operating on three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuit- level in order to adapt its performance to the different standards specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.

  6. Microfabricated structures with electrical isolation and interconnections

    NASA Technical Reports Server (NTRS)

    Clark, William A. (Inventor); Juneau, Thor N. (Inventor); Roessig, Allen W. (Inventor); Lemkin, Mark A. (Inventor)

    2001-01-01

    The invention is directed to a microfabricated device. The device includes a substrate that is etched to define mechanical structures at least some of which are anchored laterally to the remainder of the substrate. Electrical isolation at points where mechanical structures are attached to the substrate is provided by filled isolation trenches. Filled trenches may also be used to electrically isolate structure elements from each other at points where mechanical attachment of structure elements is desired. The performance of microelectromechanical devices is improved by 1) having a high-aspect-ratio between vertical and lateral dimensions of the mechanical elements, 2) integrating electronics on the same substrate as the mechanical elements, 3) good electrical isolation among mechanical elements and circuits except where electrical interconnection is desired.

  7. Early stage of plastic deformation in thin films undergoing electromigration

    NASA Astrophysics Data System (ADS)

    Valek, B. C.; Tamura, N.; Spolenak, R.; Caldwell, W. A.; MacDowell, A. A.; Celestre, R. S.; Padmore, H. A.; Bravman, J. C.; Batterman, B. W.; Nix, W. D.; Patel, J. R.

    2003-09-01

    Electromigration occurs when a high current density drives atomic motion from the cathode to the anode end of a conductor, such as a metal interconnect line in an integrated circuit. While electromigration eventually causes macroscopic damage, in the form of voids and hillocks, the earliest stage of the process when the stress in individual micron-sized grains is still building up is largely unexplored. Using synchrotron-based x-ray microdiffraction during an in-situ electromigration experiment, we have discovered an early prefailure mode of plastic deformation involving preferential dislocation generation and motion and the formation of a subgrain structure within individual grains of a passivated Al (Cu) interconnect. This behavior occurs long before macroscopic damage (hillocks and voids) is observed.

  8. An Agent-Based Model for Studying Child Maltreatment and Child Maltreatment Prevention

    NASA Astrophysics Data System (ADS)

    Hu, Xiaolin; Puddy, Richard W.

    This paper presents an agent-based model that simulates the dynamics of child maltreatment and child maltreatment prevention. The developed model follows the principles of complex systems science and explicitly models a community and its families with multi-level factors and interconnections across the social ecology. This makes it possible to experiment how different factors and prevention strategies can affect the rate of child maltreatment. We present the background of this work and give an overview of the agent-based model and show some simulation results.

  9. Publics and biobanks: Pan-European diversity and the challenge of responsible innovation.

    PubMed

    Gaskell, George; Gottweis, Herbert; Starkbaum, Johannes; Gerber, Monica M; Broerse, Jacqueline; Gottweis, Ursula; Hobbs, Abbi; Helén, Ilpo; Paschou, Maria; Snell, Karoliina; Soulier, Alexandra

    2013-01-01

    This article examines public perceptions of biobanks in Europe using a multi-method approach combining quantitative and qualitative data. It is shown that public support for biobanks in Europe is variable and dependent on a range of interconnected factors: people's engagement with biobanks; concerns about privacy and data security, and trust in the socio-political system, key actors and institutions involved in biobanks. We argue that the biobank community needs to acknowledge the impact of these factors if they are to successfully develop and integrate biobanks at a pan-European level.

  10. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Waye, Scot

    Power electronics that use high-temperature devices pose a challenge for thermal management. With the devices running at higher temperatures and having a smaller footprint, the heat fluxes increase from previous power electronic designs. This project overview presents an approach to examine and design thermal management strategies through cooling technologies to keep devices within temperature limits, dissipate the heat generated by the devices and protect electrical interconnects and other components for inverter, converter, and charger applications. This analysis, validation, and demonstration intends to take a multi-scale approach over the device, module, and system levels to reduce size, weight, and cost.

  11. Fully chip-embedded automation of a multi-step lab-on-a-chip process using a modularized timer circuit.

    PubMed

    Kang, Junsu; Lee, Donghyeon; Heo, Young Jin; Chung, Wan Kyun

    2017-11-07

    For highly-integrated microfluidic systems, an actuation system is necessary to control the flow; however, the bulk of actuation devices including pumps or valves has impeded the broad application of integrated microfluidic systems. Here, we suggest a microfluidic process control method based on built-in microfluidic circuits. The circuit is composed of a fluidic timer circuit and a pneumatic logic circuit. The fluidic timer circuit is a serial connection of modularized timer units, which sequentially pass high pressure to the pneumatic logic circuit. The pneumatic logic circuit is a NOR gate array designed to control the liquid-controlling process. By using the timer circuit as a built-in signal generator, multi-step processes could be done totally inside the microchip without any external controller. The timer circuit uses only two valves per unit, and the number of process steps can be extended without limitation by adding timer units. As a demonstration, an automation chip has been designed for a six-step droplet treatment, which entails 1) loading, 2) separation, 3) reagent injection, 4) incubation, 5) clearing and 6) unloading. Each process was successfully performed for a pre-defined step-time without any external control device.

  12. Packaging Technology Designed, Fabricated, and Assembled for High-Temperature SiC Microsystems

    NASA Technical Reports Server (NTRS)

    Chen, Liang-Yu

    2003-01-01

    A series of ceramic substrates and thick-film metalization-based prototype microsystem packages designed for silicon carbide (SiC) high-temperature microsystems have been developed for operation in 500 C harsh environments. These prototype packages were designed, fabricated, and assembled at the NASA Glenn Research Center. Both the electrical interconnection system and the die-attach scheme for this packaging system have been tested extensively at high temperatures. Printed circuit boards used to interconnect these chip-level packages and passive components also are being fabricated and tested. NASA space and aeronautical missions need harsh-environment, especially high-temperature, operable microsystems for probing the inner solar planets and for in situ monitoring and control of next-generation aeronautical engines. Various SiC high-temperature-operable microelectromechanical system (MEMS) sensors, actuators, and electronics have been demonstrated at temperatures as high as 600 C, but most of these devices were demonstrated only in the laboratory environment partially because systematic packaging technology for supporting these devices at temperatures of 500 C and beyond was not available. Thus, the development of a systematic high-temperature packaging technology is essential for both in situ testing and the commercialization of high-temperature SiC MEMS. Researchers at Glenn developed new prototype packages for high-temperature microsystems using ceramic substrates (aluminum nitride and 96- and 90-wt% aluminum oxides) and gold (Au) thick-film metalization. Packaging components, which include a thick-film metalization-based wirebond interconnection system and a low-electrical-resistance SiC die-attachment scheme, have been tested at temperatures up to 500 C. The interconnection system composed of Au thick-film printed wire and 1-mil Au wire bond was tested in 500 C oxidizing air with and without 50-mA direct current for over 5000 hr. The Au thick-film metalization-based wirebond electrical interconnection system was also tested in an extremely dynamic thermal environment to assess thermal reliability. The I-V curve1 of a SiC high-temperature diode was measured in oxidizing air at 500 C for 1000 hr to electrically test the Au thick-film material-based die-attach assembly.

  13. AIN-Based Packaging for SiC High-Temperature Electronics

    NASA Technical Reports Server (NTRS)

    Savrun, Ender

    2004-01-01

    Packaging made primarily of aluminum nitride has been developed to enclose silicon carbide-based integrated circuits (ICs), including circuits containing SiC-based power diodes, that are capable of operation under conditions more severe than can be withstood by silicon-based integrated circuits. A major objective of this development was to enable packaged SiC electronic circuits to operate continuously at temperatures up to 500 C. AlN-packaged SiC electronic circuits have commercial potential for incorporation into high-power electronic equipment and into sensors that must withstand high temperatures and/or high pressures in diverse applications that include exploration in outer space, well logging, and monitoring of nuclear power systems. This packaging embodies concepts drawn from flip-chip packaging of silicon-based integrated circuits. One or more SiC-based circuit chips are mounted on an aluminum nitride package substrate or sandwiched between two such substrates. Intimate electrical connections between metal conductors on the chip(s) and the metal conductors on external circuits are made by direct bonding to interconnections on the package substrate(s) and/or by use of holes through the package substrate(s). This approach eliminates the need for wire bonds, which have been the most vulnerable links in conventional electronic circuitry in hostile environments. Moreover, the elimination of wire bonds makes it possible to pack chips more densely than was previously possible.

  14. Solar power generation system for reducing leakage current

    NASA Astrophysics Data System (ADS)

    Wu, Jinn-Chang; Jou, Hurng-Liahng; Hung, Chih-Yi

    2018-04-01

    This paper proposes a transformer-less multi-level solar power generation system. This solar power generation system is composed of a solar cell array, a boost power converter, an isolation switch set and a full-bridge inverter. A unipolar pulse-width modulation (PWM) strategy is used in the full-bridge inverter to attenuate the output ripple current. Circuit isolation is accomplished by integrating the isolation switch set between the solar cell array and the utility, to suppress the leakage current. The isolation switch set also determines the DC bus voltage for the full-bridge inverter connecting to the solar cell array or the output of the boost power converter. Accordingly, the proposed transformer-less multi-level solar power generation system generates a five-level voltage, and the partial power of the solar cell array is also converted to AC power using only the full-bridge inverter, so the power efficiency is increased. A prototype is developed to validate the performance of the proposed transformer-less multi-level solar power generation system.

  15. Design, Fabrication, and Characterization of a Microelectromechanical Directional Microphone

    DTIC Science & Technology

    2011-06-01

    7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES...Figure 5.2 SOIC packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 5.3 Laboratory setup...Mean Squared SOC System-On-Chip SOIC Small Outline Integrated Circuit SOIMUMPS Silicon-On-Insulator Multi-User MEMS Process SPL Sound Pressure Level

  16. System and method for monitoring and controlling stator winding temperature in a de-energized AC motor

    DOEpatents

    Lu, Bin [Kenosha, WI; Luebke, Charles John [Sussex, WI; Habetler, Thomas G [Snellville, GA; Zhang, Pinjia [Atlanta, GA; Becker, Scott K [Oak Creek, WI

    2011-12-27

    A system and method for measuring and controlling stator winding temperature in an AC motor while idling is disclosed. The system includes a circuit having an input connectable to an AC source and an output connectable to an input terminal of a multi-phase AC motor. The circuit further includes a plurality of switching devices to control current flow and terminal voltages in the multi-phase AC motor and a controller connected to the circuit. The controller is configured to activate the plurality of switching devices to create a DC signal in an output of the motor control device corresponding to an input to the multi-phase AC motor, determine or estimate a stator winding resistance of the multi-phase AC motor based on the DC signal, and estimate a stator temperature from the stator winding resistance. Temperature can then be controlled and regulated by DC injection into the stator windings.

  17. A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

    PubMed Central

    Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

    2017-01-01

    This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors. PMID:28368355

  18. A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems.

    PubMed

    Park, Kyeonghwan; Kim, Seung Mok; Eom, Won-Jin; Kim, Jae Joon

    2017-04-03

    This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC) for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR) of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS) process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

  19. On-Die Sensors for Transient Events

    NASA Astrophysics Data System (ADS)

    Suchak, Mihir Vimal

    Failures caused by transient electromagnetic events like Electrostatic Discharge (ESD) are a major concern for embedded systems. The component often failing is an integrated circuit (IC). Determining which IC is affected in a multi-device system is a challenging task. Debugging errors often requires sophisticated lab setups which require intentionally disturbing and probing various parts of the system which might not be easily accessible. Opening the system and adding probes may change its response to the transient event, which further compounds the problem. On-die transient event sensors were developed that require relatively little area on die, making them inexpensive, they consume negligible static current, and do not interfere with normal operation of the IC. These circuits can be used to determine the pin involved and the level of the event in the event of a transient event affecting the IC, thus allowing the user to debug system-level transient events without modifying the system. The circuit and detection scheme design has been completed and verified in simulations with Cadence Virtuoso environment. Simulations accounted for the impact of the ESD protection circuits, parasitics from the I/O pin, package and I/O ring, and included a model of an ESD gun to test the circuit's response to an ESD pulse as specified in IEC 61000-4-2. Multiple detection schemes are proposed. The final detection scheme consists of an event detector and a level sensor. The event detector latches on the presence of an event at a pad, to determine on which pin an event occurred. The level sensor generates current proportional to the level of the event. This current is converted to a voltage and digitized at the A/D converter to be read by the microprocessor. Detection scheme shows good performance in simulations when checked against process variations and different kind of events.

  20. Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

    NASA Astrophysics Data System (ADS)

    Ogiwara, Akifumi; Maekawa, Hikaru; Watanabe, Minoru; Moriwaki, Retsu

    2014-02-01

    A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

  1. Silicon Photonics: Challenges and Future

    DTIC Science & Technology

    2007-01-01

    process or phonon assisted. It directly impacts the internal quantum efficiency through the relationship : ηi = (1+ (τrad/τ non-rad ))-1 There are...linear cavity approach, the reported differential quantum efficiency is currently low. The measured characteristic temperature (To), is lower than...rule changes • package design 4.1.2 Inter-chip interconnects There is a requirement on the circuit card to transfer data more efficiently between

  2. Surface inspection: Research and development

    NASA Technical Reports Server (NTRS)

    Batchelder, J. S.

    1987-01-01

    Surface inspection techniques are used for process learning, quality verification, and postmortem analysis in manufacturing for a spectrum of disciplines. First, trends in surface analysis are summarized for integrated circuits, high density interconnection boards, and magnetic disks, emphasizing on-line applications as opposed to off-line or development techniques. Then, a closer look is taken at microcontamination detection from both a patterned defect and a particulate inspection point of view.

  3. Multijunction high-voltage solar cell

    NASA Technical Reports Server (NTRS)

    Evans, J. C., Jr.; Goradia, C.; Chai, A. T.

    1981-01-01

    Multijunction cell allows for fabrication of high-voltage solar cell on single semiconductor wafer. Photovoltaic energy source using cell is combined on wafer with circuit it is to power. Cell consists of many voltage-generating regions internally or externally interconnected to give desired voltage and current combination. For computer applications, module is built on silicon wafer with energy for internal information processing and readouts derived from external light source.

  4. Fractal dendrite-based electrically conductive composites for laser-scribed flexible circuits

    PubMed Central

    Yang, Cheng; Cui, Xiaoya; Zhang, Zhexu; Chiang, Sum Wai; Lin, Wei; Duan, Huan; Li, Jia; Kang, Feiyu; Wong, Ching-Ping

    2015-01-01

    Fractal metallic dendrites have been drawing more attentions recently, yet they have rarely been explored in electronic printing or packaging applications because of the great challenges in large-scale synthesis and limited understanding in such applications. Here we demonstrate a controllable synthesis of fractal Ag micro-dendrites at the hundred-gram scale. When used as the fillers for isotropically electrically conductive composites (ECCs), the unique three-dimensional fractal geometrical configuration and low-temperature sintering characteristic render the Ag micro dendrites with an ultra-low electrical percolation threshold of 0.97 vol% (8 wt%). The ultra-low percolation threshold and self-limited fusing ability may address some critical challenges in current interconnect technology for microelectronics. For example, only half of the laser-scribe energy is needed to pattern fine circuit lines printed using the present ECCs, showing great potential for wiring ultrathin circuits for high performance flexible electronics. PMID:26333352

  5. Modulating light propagation in ZnO-Cu₂O-inverse opal solar cells for enhanced photocurrents.

    PubMed

    Yantara, Natalia; Pham, Thi Thu Trang; Boix, Pablo P; Mathews, Nripan

    2015-09-07

    The advantages of employing an interconnected periodic ZnO morphology, i.e. an inverse opal structure, in electrodeposited ZnO/Cu2O devices are presented. The solar cells are fabricated using low cost solution based methods such as spin coating and electrodeposition. The impact of inverse opal geometry, mainly the diameter and thickness, is scrutinized. By employing 3 layers of an inverse opal structure with a 300 nm pore diameter, higher short circuit photocurrents (∼84% improvement) are observed; however the open circuit voltages decrease with increasing interfacial area. Optical simulation using a finite difference time domain method shows that the inverse opal structure modulates light propagation within the devices such that more photons are absorbed close to the ZnO/Cu2O junction. This increases the collection probability resulting in improved short circuit currents.

  6. The Corticohippocampal Circuit, Synaptic Plasticity, and Memory

    PubMed Central

    Basu, Jayeeta; Siegelbaum, Steven A.

    2015-01-01

    Synaptic plasticity serves as a cellular substrate for information storage in the central nervous system. The entorhinal cortex (EC) and hippocampus are interconnected brain areas supporting basic cognitive functions important for the formation and retrieval of declarative memories. Here, we discuss how information flow in the EC–hippocampal loop is organized through circuit design. We highlight recently identified corticohippocampal and intrahippocampal connections and how these long-range and local microcircuits contribute to learning. This review also describes various forms of activity-dependent mechanisms that change the strength of corticohippocampal synaptic transmission. A key point to emerge from these studies is that patterned activity and interaction of coincident inputs gives rise to associational plasticity and long-term regulation of information flow. Finally, we offer insights about how learning-related synaptic plasticity within the corticohippocampal circuit during sensory experiences may enable adaptive behaviors for encoding spatial, episodic, social, and contextual memories. PMID:26525152

  7. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Bell, Nelson S.; Sarobol, Pylin; Cook, Adam

    There is a rising interest in developing functional electronics using additively manufactured components. Considerations in materials selection and pathways to forming hybrid circuits and devices must demonstrate useful electronic function; must enable integration; and must complement the complex shape, low cost, high volume, and high functionality of structural but generally electronically passive additively manufactured components. This article reviews several emerging technologies being used in industry and research/development to provide integration advantages of fabricating multilayer hybrid circuits or devices. First, we review a maskless, noncontact, direct write (DW) technology that excels in the deposition of metallic colloid inks for electrical interconnects.more » Second, we review a complementary technology, aerosol deposition (AD), which excels in the deposition of metallic and ceramic powder as consolidated, thick conformal coatings and is additionally patternable through masking. As a result, we show examples of hybrid circuits/devices integrated beyond 2-D planes, using combinations of DW or AD processes and conventional, established processes.« less

  8. Method for making a monolithic integrated high-T.sub.c superconductor-semiconductor structure

    NASA Technical Reports Server (NTRS)

    Burns, Michael J. (Inventor); de la Houssaye, Paul R. (Inventor); Russell, Stephen D. (Inventor); Garcia, Graham A. (Inventor); Barfknecht, Andrew T. (Inventor); Clayton, Stanley R. (Inventor)

    2000-01-01

    A method for the fabrication of active semiconductor and high-temperature perconducting devices on the same substrate to form a monolithically integrated semiconductor-superconductor (MISS) structure is disclosed. A common insulating substrate, preferably sapphire or yttria-stabilized zirconia, is used for deposition of semiconductor and high-temperature superconductor substructures. Both substructures are capable of operation at a common temperature of at least 77 K. The separate semiconductor and superconductive regions may be electrically interconnected by normal metals, refractory metal silicides, or superconductors. Circuits and devices formed in the resulting MISS structures display operating characteristics which are equivalent to those of circuits and devices prepared on separate substrates.

  9. An enhanced high-speed multi-digit BCD adder using quantum-dot cellular automata

    NASA Astrophysics Data System (ADS)

    Ajitha, D.; Ramanaiah, K. V.; Sumalatha, V.

    2017-02-01

    The advent of development of high-performance, low-power digital circuits is achieved by a suitable emerging nanodevice called quantum-dot cellular automata (QCA). Even though many efficient arithmetic circuits were designed using QCA, there is still a challenge to implement high-speed circuits in an optimized manner. Among these circuits, one of the essential structures is a parallel multi-digit decimal adder unit with significant speed which is very attractive for future environments. To achieve high speed, a new correction logic formulation method is proposed for single and multi-digit BCD adder. The proposed enhanced single-digit BCD adder (ESDBA) is 26% faster than the carry flow adder (CFA)-based BCD adder. The multi-digit operations are also performed using the proposed ESDBA, which is cascaded innovatively. The enhanced multi-digit BCD adder (EMDBA) performs two 4-digit and two 8-digit BCD addition 50% faster than the CFA-based BCD adder with the nominal overhead of the area. The EMDBA performs two 4-digit BCD addition 24% faster with 23% decrease in the area, similarly for 8-digit operation the EMDBA achieves 36% increase in speed with 21% less area compared to the existing carry look ahead (CLA)-based BCD adder design. The proposed multi-digit adder produces significantly less delay of (N –1) + 3.5 clock cycles compared to the N* One digit BCD adder delay required by the conventional BCD adder method. It is observed that as per our knowledge this is the first innovative proposal for multi-digit BCD addition using QCA.

  10. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    PubMed

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  11. CMOS Amperometric ADC With High Sensitivity, Dynamic Range and Power Efficiency for Air Quality Monitoring.

    PubMed

    Li, Haitao; Boling, C Sam; Mason, Andrew J

    2016-08-01

    Airborne pollutants are a leading cause of illness and mortality globally. Electrochemical gas sensors show great promise for personal air quality monitoring to address this worldwide health crisis. However, implementing miniaturized arrays of such sensors demands high performance instrumentation circuits that simultaneously meet challenging power, area, sensitivity, noise and dynamic range goals. This paper presents a new multi-channel CMOS amperometric ADC featuring pixel-level architecture for gas sensor arrays. The circuit combines digital modulation of input currents and an incremental Σ∆ ADC to achieve wide dynamic range and high sensitivity with very high power efficiency and compact size. Fabricated in 0.5 [Formula: see text] CMOS, the circuit was measured to have 164 dB cross-scale dynamic range, 100 fA sensitivity while consuming only 241 [Formula: see text] and 0.157 [Formula: see text] active area per channel. Electrochemical experiments with liquid and gas targets demonstrate the circuit's real-time response to a wide range of analyte concentrations.

  12. Multilevel-Dc-Bus Inverter For Providing Sinusoidal And Pwm Electrical Machine Voltages

    DOEpatents

    Su, Gui-Jia [Knoxville, TN

    2005-11-29

    A circuit for controlling an ac machine comprises a full bridge network of commutation switches which are connected to supply current for a corresponding voltage phase to the stator windings, a plurality of diodes, each in parallel connection to a respective one of the commutation switches, a plurality of dc source connections providing a multi-level dc bus for the full bridge network of commutation switches to produce sinusoidal voltages or PWM signals, and a controller connected for control of said dc source connections and said full bridge network of commutation switches to output substantially sinusoidal voltages to the stator windings. With the invention, the number of semiconductor switches is reduced to m+3 for a multi-level dc bus having m levels. A method of machine control is also disclosed.

  13. Multi-dimensional construction of a novel active yolk@conductive shell nanofiber web as a self-standing anode for high-performance lithium-ion batteries

    NASA Astrophysics Data System (ADS)

    Liu, Hao; Chen, Luyi; Liang, Yeru; Fu, Ruowen; Wu, Dingcai

    2015-11-01

    A novel active yolk@conductive shell nanofiber web with a unique synergistic advantage of various hierarchical nanodimensional objects including the 0D monodisperse SiO2 yolks, the 1D continuous carbon shell and the 3D interconnected non-woven fabric web has been developed by an innovative multi-dimensional construction method, and thus demonstrates excellent electrochemical properties as a self-standing LIB anode.A novel active yolk@conductive shell nanofiber web with a unique synergistic advantage of various hierarchical nanodimensional objects including the 0D monodisperse SiO2 yolks, the 1D continuous carbon shell and the 3D interconnected non-woven fabric web has been developed by an innovative multi-dimensional construction method, and thus demonstrates excellent electrochemical properties as a self-standing LIB anode. Electronic supplementary information (ESI) available: Experimental details and additional information about material characterization. See DOI: 10.1039/c5nr06531c

  14. Models and methods for assessing the value of HVDC and MVDC technologies in modern power grids

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Makarov, Yuri V.; Elizondo, Marcelo A.; O'Brien, James G.

    This report reflects the results of U.S. Department of Energy’s (DOE) Grid Modernization project 0074 “Models and methods for assessing the value of HVDC [high-voltage direct current] and MTDC [multi-terminal direct current] technologies in modern power grids.” The work was done by the Pacific Northwest National Laboratory (PNNL) and Oak Ridge National Laboratory (ORNL) in cooperation with Mid-Continent Independent System Operator (MISO) and Siemens. The main motivation of this study was to show the benefit of using direct current (DC) systems larger than those in existence today as they overlap with the alternating current (AC) systems. Proper use of theirmore » flexibility in terms of active/reactive power control and fast response can provide much-needed services to the grid at the same time as moving large blocks of energy to take advantage of cost diversity. Ultimately, the project’s success will enable decision-makers and investors to make well-informed decisions regarding this use of DC systems. This project showed the technical feasibility of HVDC macrogrid for frequency control and congestion relief in addition to bulk power transfers. Industry-established models for commonly used technologies were employed, along with high-fidelity models for recently developed HVDC converter technologies; like the modular multilevel converters (MMCs), a voltage source converters (VSC). Models for General Electric Positive Sequence Load Flow (GE PSLF) and Siemens Power System Simulator (PSS/E), widely used analysis programs, were for the first time adapted to include at the same time both Western Electricity Coordinating Council (WECC) and Eastern Interconnection (EI), the two largest North American interconnections. The high-fidelity models and their control were developed in detail for MMC system and extended to HVDC systems in point-to-point and in three-node multi-terminal configurations. Using a continental-level mixed AC-DC grid model, and using a HVDC macrogrid power flow and transient stability model, the results showed that the HVDC macrogrid relieved congestion and mitigated loop flows in AC networks, and provided up to 24% improvement in frequency responses. These are realistic studies, based on the 2025 heavy summer and EI multi-regional modeling working group (MMWG) 2026 summer peak cases. This work developed high-fidelity models and simulation algorithms to understand the dynamics of MMC. The developed models and simulation algorithms are up to 25 times faster than the existing algorithms. Models and control algorithms for high-fidelity models were designed and tested for point-to-point and multi-terminal configurations. The multi-terminal configuration was tested connecting simplified models of EI, WI, and Electric Reliability Council of Texas (ERCOT). The developed models showed up to 45% improvement in frequency response with the connection of all the three asynchronous interconnections in the United States using fast and advanced DC technologies like the multi-terminal MMC-DC system. Future work will look into developing high-fidelity models of other advanced DC technologies, combining high-fidelity models with the continental-level model, incorporating additional services. More scenarios involving large-scale HVDC and MTDC will be evaluated.« less

  15. From Molecular Circuit Dysfunction to Disease: Case Studies in Epilepsy, Traumatic Brain Injury, and Alzheimer’s Disease

    PubMed Central

    Dulla, Chris G.; Coulter, Douglas A.; Ziburkus, Jokubas

    2015-01-01

    Complex circuitry with feed-forward and feed-back systems regulate neuronal activity throughout the brain. Cell biological, electrical, and neurotransmitter systems enable neural networks to process and drive the entire spectrum of cognitive, behavioral, and motor functions. Simultaneous orchestration of distinct cells and interconnected neural circuits relies on hundreds, if not thousands, of unique molecular interactions. Even single molecule dysfunctions can be disrupting to neural circuit activity, leading to neurological pathology. Here, we sample our current understanding of how molecular aberrations lead to disruptions in networks using three neurological pathologies as exemplars: epilepsy, traumatic brain injury (TBI), and Alzheimer’s disease (AD). Epilepsy provides a window into how total destabilization of network balance can occur. TBI is an abrupt physical disruption that manifests in both acute and chronic neurological deficits. Last, in AD progressive cell loss leads to devastating cognitive consequences. Interestingly, all three of these neurological diseases are interrelated. The goal of this review, therefore, is to identify molecular changes that may lead to network dysfunction, elaborate on how altered network activity and circuit structure can contribute to neurological disease, and suggest common threads that may lie at the heart of molecular circuit dysfunction. PMID:25948650

  16. From Molecular Circuit Dysfunction to Disease: Case Studies in Epilepsy, Traumatic Brain Injury, and Alzheimer's Disease.

    PubMed

    Dulla, Chris G; Coulter, Douglas A; Ziburkus, Jokubas

    2016-06-01

    Complex circuitry with feed-forward and feed-back systems regulate neuronal activity throughout the brain. Cell biological, electrical, and neurotransmitter systems enable neural networks to process and drive the entire spectrum of cognitive, behavioral, and motor functions. Simultaneous orchestration of distinct cells and interconnected neural circuits relies on hundreds, if not thousands, of unique molecular interactions. Even single molecule dysfunctions can be disrupting to neural circuit activity, leading to neurological pathology. Here, we sample our current understanding of how molecular aberrations lead to disruptions in networks using three neurological pathologies as exemplars: epilepsy, traumatic brain injury (TBI), and Alzheimer's disease (AD). Epilepsy provides a window into how total destabilization of network balance can occur. TBI is an abrupt physical disruption that manifests in both acute and chronic neurological deficits. Last, in AD progressive cell loss leads to devastating cognitive consequences. Interestingly, all three of these neurological diseases are interrelated. The goal of this review, therefore, is to identify molecular changes that may lead to network dysfunction, elaborate on how altered network activity and circuit structure can contribute to neurological disease, and suggest common threads that may lie at the heart of molecular circuit dysfunction. © The Author(s) 2015.

  17. An externally head-mounted wireless neural recording device for laboratory animal research and possible human clinical use.

    PubMed

    Yin, Ming; Li, Hao; Bull, Christopher; Borton, David A; Aceros, Juan; Larson, Lawrence; Nurmikko, Arto V

    2013-01-01

    In this paper we present a new type of head-mounted wireless neural recording device in a highly compact package, dedicated for untethered laboratory animal research and designed for future mobile human clinical use. The device, which takes its input from an array of intracortical microelectrode arrays (MEA) has ninety-seven broadband parallel neural recording channels and was integrated on to two custom designed printed circuit boards. These house several low power, custom integrated circuits, including a preamplifier ASIC, a controller ASIC, plus two SAR ADCs, a 3-axis accelerometer, a 48MHz clock source, and a Manchester encoder. Another ultralow power RF chip supports an OOK transmitter with the center frequency tunable from 3GHz to 4GHz, mounted on a separate low loss dielectric board together with a 3V LDO, with output fed to a UWB chip antenna. The IC boards were interconnected and packaged in a polyether ether ketone (PEEK) enclosure which is compatible with both animal and human use (e.g. sterilizable). The entire system consumes 17mA from a 1.2Ahr 3.6V Li-SOCl2 1/2AA battery, which operates the device for more than 2 days. The overall system includes a custom RF receiver electronics which are designed to directly interface with any number of commercial (or custom) neural signal processors for multi-channel broadband neural recording. Bench-top measurements and in vivo testing of the device in rhesus macaques are presented to demonstrate the performance of the wireless neural interface.

  18. Low-voltage high-performance silicon photonic devices and photonic integrated circuits operating up to 30 Gb/s.

    PubMed

    Kim, Gyungock; Park, Jeong Woo; Kim, In Gyoo; Kim, Sanghoon; Kim, Sanggi; Lee, Jong Moo; Park, Gun Sik; Joo, Jiho; Jang, Ki-Seok; Oh, Jin Hyuk; Kim, Sun Ae; Kim, Jong Hoon; Lee, Jun Young; Park, Jong Moon; Kim, Do-Won; Jeong, Deog-Kyoon; Hwang, Moon-Sang; Kim, Jeong-Kyoum; Park, Kyu-Sang; Chi, Han-Kyu; Kim, Hyun-Chang; Kim, Dong-Wook; Cho, Mu Hee

    2011-12-19

    We present high performance silicon photonic circuits (PICs) defined for off-chip or on-chip photonic interconnects, where PN depletion Mach-Zehnder modulators and evanescent-coupled waveguide Ge-on-Si photodetectors were monolithically integrated on an SOI wafer with CMOS-compatible process. The fabricated silicon PIC(off-chip) for off-chip optical interconnects showed operation up to 30 Gb/s. Under differential drive of low-voltage 1.2 V(pp), the integrated 1 mm-phase-shifter modulator in the PIC(off-chip) demonstrated an extinction ratio (ER) of 10.5dB for 12.5 Gb/s, an ER of 9.1dB for 20 Gb/s, and an ER of 7.2 dB for 30 Gb/s operation, without adoption of travelling-wave electrodes. The device showed the modulation efficiency of V(π)L(π) ~1.59 Vcm, and the phase-shifter loss of 3.2 dB/mm for maximum optical transmission. The Ge photodetector, which allows simpler integration process based on reduced pressure chemical vapor deposition exhibited operation over 30 Gb/s with a low dark current of 700 nA at -1V. The fabricated silicon PIC(intra-chip) for on-chip (intra-chip) photonic interconnects, where the monolithically integrated modulator and Ge photodetector were connected by a silicon waveguide on the same chip, showed on-chip data transmissions up to 20 Gb/s, indicating potential application in future silicon on-chip optical network. We also report the performance of the hybrid silicon electronic-photonic IC (EPIC), where a PIC(intra-chip) chip and 0.13μm CMOS interface IC chips were hybrid-integrated.

  19. Polymer waveguides for electro-optical integration in data centers and high-performance computers.

    PubMed

    Dangel, Roger; Hofrichter, Jens; Horst, Folkert; Jubin, Daniel; La Porta, Antonio; Meier, Norbert; Soganci, Ibrahim Murat; Weiss, Jonas; Offrein, Bert Jan

    2015-02-23

    To satisfy the intra- and inter-system bandwidth requirements of future data centers and high-performance computers, low-cost low-power high-throughput optical interconnects will become a key enabling technology. To tightly integrate optics with the computing hardware, particularly in the context of CMOS-compatible silicon photonics, optical printed circuit boards using polymer waveguides are considered as a formidable platform. IBM Research has already demonstrated the essential silicon photonics and interconnection building blocks. A remaining challenge is electro-optical packaging, i.e., the connection of the silicon photonics chips with the system. In this paper, we present a new single-mode polymer waveguide technology and a scalable method for building the optical interface between silicon photonics chips and single-mode polymer waveguides.

  20. L-connect routing of die surface pads to the die edge for stacking in a 3D array

    DOEpatents

    Petersen, Robert W.

    2000-01-01

    Integrated circuit chips and method of routing the interface pads from the face of the chip or die to one or more sidewall surfaces of the die. The interconnection is routed from the face of the die to one or more edges of the die, then routed over the edge of the die and onto the side surface. A new pad is then formed on the sidewall surface, which allows multiple die or chips to be stacked in a three-dimensional array, while enabling follow-on signal routing from the sidewall pads. The routing of the interconnects and formation of the sidewall pads can be carried out in an L-connect or L-shaped routing configuration, using a metalization process such as laser pantography.

Some links on this page may take you to non-federal websites. Their policies may differ from this site.
Top