Sample records for multiple microprocessor system

  1. Microprocessor Based Real-Time Monitoring of Multiple ECG Signals

    PubMed Central

    Nasipuri, M.; Basu, D.K.; Dattagupta, R.; Kundu, M.; Banerjee, S.

    1987-01-01

    A microprocessor based system capable of realtime monitoring of multiple ECG signals has been described. The system consists of a number of microprocessors connected in a hierarchical fashion and capable of working concurrently on ECG data collected from different channels. The system can monitor different arrhythmic abnormalities for at least 36 patients even for a heart rate of 500 beats/min.

  2. A survey of the state of the art and focused research in range systems, task 2

    NASA Technical Reports Server (NTRS)

    Yao, K.

    1986-01-01

    Many communication, control, and information processing subsystems are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since, in general, the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, the optimum powers of two coefficient solution was considered. Detailed explanations on the use of branch-and-bound algorithms for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is dully applicable to many other microprocessor controlled information processing systems.

  3. DSS 13 microprocessor antenna controller

    NASA Technical Reports Server (NTRS)

    Gosline, R. M.

    1988-01-01

    A microprocessor-based antenna monitor and control system with multiple CPUs are described. The system was developed as part of the unattended station project for DSS 13 and was enhanced for use by the SETI project. The operational features, hardware, and software designs are described, and a discussion is provided of the major problems encountered.

  4. A methodology based on reduced complexity algorithm for system applications using microprocessors

    NASA Technical Reports Server (NTRS)

    Yan, T. Y.; Yao, K.

    1988-01-01

    The paper considers a methodology on the analysis and design of a minimum mean-square error criterion linear system incorporating a tapped delay line (TDL) where all the full-precision multiplications in the TDL are constrained to be powers of two. A linear equalizer based on the dispersive and additive noise channel is presented. This microprocessor implementation with optimized power of two TDL coefficients achieves a system performance comparable to the optimum linear equalization with full-precision multiplications for an input data rate of 300 baud.

  5. An Interdisciplinary Microprocessor Project.

    ERIC Educational Resources Information Center

    Wilcox, Alan D.; And Others

    1985-01-01

    Describes an unusual project in which third-year computer science students designed and built a four-bit multiplier circuit and then combines it with software to complete a full 16-bit multiplication. The multiplier was built using TTL components, interfaced with a Z-80 microprocessor system, and programed in assembly language. (JN)

  6. Design of a Distributed Microprocessor Sensor System

    DTIC Science & Technology

    1990-04-01

    implemented through these methods, multiversion software and recovery the use of multiple identical software tasks running on blocks, are intended to... Multiversion software for real-time systems tolerant microprocessor that uses three processing is discussed by Shepherd32, Hitt33, Avizienis’, and...tasks and the there are no data available to determine the cost third is used for noncritical tasks. If a discrepancy effectiveness of multiversion

  7. A microprocessor based high speed packet switch for satellite communications

    NASA Technical Reports Server (NTRS)

    Arozullah, M.; Crist, S. C.

    1980-01-01

    The architectures of a single processor, a three processor, and a multiple processor system are described. The hardware circuits, and software routines required for implementing the three and multiple processor designs are presented. A bit-slice microprocessor was designed and microprogrammed. Maximum throughput was calculated for all three designs. Queue theoretic models for these three designs were developed and utilized to obtain analytical expressions for the average waiting times, overall average response times and average queue sizes. From these expressions, graphs were obtained showing the effect on the system performance of a number of design parameters.

  8. Optical detector calibrator system

    NASA Technical Reports Server (NTRS)

    Strobel, James P. (Inventor); Moerk, John S. (Inventor); Youngquist, Robert C. (Inventor)

    1996-01-01

    An optical detector calibrator system simulates a source of optical radiation to which a detector to be calibrated is responsive. A light source selected to emit radiation in a range of wavelengths corresponding to the spectral signature of the source is disposed within a housing containing a microprocessor for controlling the light source and other system elements. An adjustable iris and a multiple aperture filter wheel are provided for controlling the intensity of radiation emitted from the housing by the light source to adjust the simulated distance between the light source and the detector to be calibrated. The geared iris has an aperture whose size is adjustable by means of a first stepper motor controlled by the microprocessor. The multiple aperture filter wheel contains neutral density filters of different attenuation levels which are selectively positioned in the path of the emitted radiation by a second stepper motor that is also controlled by the microprocessor. An operator can select a number of detector tests including range, maximum and minimum sensitivity, and basic functionality. During the range test, the geared iris and filter wheel are repeatedly adjusted by the microprocessor as necessary to simulate an incrementally increasing simulated source distance. A light source calibration subsystem is incorporated in the system which insures that the intensity of the light source is maintained at a constant level over time.

  9. Development of the transtibial prosthesis controlled pneumatically and electrically by microcomputer system.

    PubMed

    Shimada, Youichi; Terayama, Yukio

    2006-01-01

    This report represents the development of the prototype transtibial prosthesis to assist a smooth and comfortable walking for an unilateral amputee. This prosthesis is composed of two air cylinders, solenoid valves, portable and small air tank for compressed air storage, a multiple sensor system and a microprocessor. Two air cylinders are located around the rods to act as antagonistic and agonistic muscles. The system causes flexion and extension of the foot plate jointed at the ankle with compressed air, injected -or discharged via a solenoid or electromagnetic valves. The valves or solenoids are controlled with a microprocessor (Microchip Technology Inc., PIC16F876), the microprocessor generates control signals to the interface circuits for valve opening and closing consistent with the foot position during the walking phase. The control patterns generated in the microprocessor are modified with feedback from the touch sensor, ankle joint angle sensor and the two dimensional acceleration sensor. The primary walking pattern for an individual amputee should be developed through the gait analysis with video.

  10. Design Method of Digital Optimal Control Scheme and Multiple Paralleled Bridge Type Current Amplifier for Generating Gradient Magnetic Fields in MRI Systems

    NASA Astrophysics Data System (ADS)

    Watanabe, Shuji; Takano, Hiroshi; Fukuda, Hiroya; Hiraki, Eiji; Nakaoka, Mutsuo

    This paper deals with a digital control scheme of multiple paralleled high frequency switching current amplifier with four-quadrant chopper for generating gradient magnetic fields in MRI (Magnetic Resonance Imaging) systems. In order to track high precise current pattern in Gradient Coils (GC), the proposal current amplifier cancels the switching current ripples in GC with each other and designed optimum switching gate pulse patterns without influences of the large filter current ripple amplitude. The optimal control implementation and the linear control theory in GC current amplifiers have affinity to each other with excellent characteristics. The digital control system can be realized easily through the digital control implementation, DSPs or microprocessors. Multiple-parallel operational microprocessors realize two or higher paralleled GC current pattern tracking amplifier with optimal control design and excellent results are given for improving the image quality of MRI systems.

  11. Multiprocessor switch with selective pairing

    DOEpatents

    Gara, Alan; Gschwind, Michael K; Salapura, Valentina

    2014-03-11

    System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus

  12. Smartcards in Libraries: A Brave New World.

    ERIC Educational Resources Information Center

    Myhill, Martin

    1998-01-01

    Describes the University of Exeter (UK), Mondex, and NatWest UK smartcard-based campus card system project. Smartcards, wallet-sized plastic cards with microprocessors, interface with network terminal devices and are programmable as data, identity, and finance cards. International standard multiple operating system (MULTOS) increases current…

  13. Using a Cray Y-MP as an array processor for a RISC Workstation

    NASA Technical Reports Server (NTRS)

    Lamaster, Hugh; Rogallo, Sarah J.

    1992-01-01

    As microprocessors increase in power, the economics of centralized computing has changed dramatically. At the beginning of the 1980's, mainframes and super computers were often considered to be cost-effective machines for scalar computing. Today, microprocessor-based RISC (reduced-instruction-set computer) systems have displaced many uses of mainframes and supercomputers. Supercomputers are still cost competitive when processing jobs that require both large memory size and high memory bandwidth. One such application is array processing. Certain numerical operations are appropriate to use in a Remote Procedure Call (RPC)-based environment. Matrix multiplication is an example of an operation that can have a sufficient number of arithmetic operations to amortize the cost of an RPC call. An experiment which demonstrates that matrix multiplication can be executed remotely on a large system to speed the execution over that experienced on a workstation is described.

  14. Variable frequency microprocessor clock generator

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Branson, C.N.

    A microprocessor-based system is described comprising: a digital central microprocessor provided with a clock input and having a rate of operation determined by the frequency of a clock signal input thereto; memory means operably coupled to the central microprocessor for storing programs respectively including a plurality of instructions and addressable by the central microprocessor; peripheral device operably connected to the central microprocessor, the first peripheral device being addressable by the central microprocessor for control thereby; a system clock generator for generating a digital reference clock signal having a reference frequency rate; and frequency rate reduction circuit means connected between themore » clock generator and the clock input of the central microprocessor for selectively dividing the reference clock signal to generate a microprocessor clock signal as an input to the central microprocessor for clocking the central microprocessor.« less

  15. JOVIAL/Ada Microprocessor Study.

    DTIC Science & Technology

    1982-04-01

    Study Final Technical Report interesting feature of the nodes is that they provide multiple virtual terminals, so it is possible to monitor several...Terminal Interface Tasking Except ion Handling A more elaborate system could allow such features as spooling, background jobs or multiple users. To a large...Another editor feature is the buffer. Buffers may hold small amounts of text or entire text objects. They allow multiple files to be edited simultaneously

  16. An FPGA computing demo core for space charge simulation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computedmore » using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.« less

  17. Self-Checking Pairs Of Microprocessors

    NASA Technical Reports Server (NTRS)

    Smith, Brian S.

    1995-01-01

    Method of imparting fault tolerance to computer system provides for immediate detection of faults at microprocessor level. Shadow microprocessor provides nominal duplicate outputs to verify functioning of main microprocessor. When output signal on any pin of one microprocessor differs from that on corresponding pin of other microprocessor, comparator puts out alarm signal.

  18. Single-event upset in advanced commercial power PC microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, F.; Farmanesh, F.; Swift, G. M.; Johnston, A. H.

    2003-01-01

    Single-event upset from heavy ions in measured for advanced commercial microprocessors, comparing upset sensitivity in registers and d-cache for several generations of devices. Multiple-bit upsets and asymmetry in registers upset cross sections are also discussed.

  19. 75 FR 54219 - Notice of Application for Approval of Discontinuance or Modification of a Railroad Signal System...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-09-03

    ... microprocessor-based systems. NJT proposes to verify and test signal locking systems controlled by microprocessor... interlocking, controlled points and other locations are controlled by solid-state vital microprocessor-based... components for control of both vital and non-vital functions. The logic does not change once a microprocessor...

  20. Personal Cabin Pressure Monitor and Warning System

    NASA Technical Reports Server (NTRS)

    Zysko, Jan A. (Inventor)

    2002-01-01

    A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.

  1. Personal Cabin Pressure Monitor and Warning System

    NASA Astrophysics Data System (ADS)

    Zysko, Jan A.

    2002-09-01

    A cabin pressure altitude monitor and warning system provides a warning when a detected cabin pressure altitude has reached a predetermined level. The system is preferably embodied in a portable, pager-sized device that can be carried or worn by an individual. A microprocessor calculates the pressure altitude from signals generated by a calibrated pressure transducer and a temperature sensor that compensates for temperature variations in the signals generated by the pressure transducer. The microprocessor is programmed to generate a warning or alarm if a cabin pressure altitude exceeding a predetermined threshold is detected. Preferably, the microprocessor generates two different types of warning or alarm outputs, a first early warning or alert when a first pressure altitude is exceeded. and a second more serious alarm condition when either a second. higher pressure altitude is exceeded, or when the first pressure altitude has been exceeded for a predetermined period of time. Multiple types of alarm condition indicators are preferably provided, including visual, audible and tactile. The system is also preferably designed to detect gas concentrations and other ambient conditions, and thus incorporates other sensors, such as oxygen, relative humidity, carbon dioxide, carbon monoxide and ammonia sensors, to provide a more complete characterization and monitoring of the local environment.

  2. A programmable power processor for a 25-kW power module

    NASA Technical Reports Server (NTRS)

    Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

    1979-01-01

    A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

  3. Operating system for a real-time multiprocessor propulsion system simulator. User's manual

    NASA Technical Reports Server (NTRS)

    Cole, G. L.

    1985-01-01

    The NASA Lewis Research Center is developing and evaluating experimental hardware and software systems to help meet future needs for real-time, high-fidelity simulations of air-breathing propulsion systems. Specifically, the real-time multiprocessor simulator project focuses on the use of multiple microprocessors to achieve the required computing speed and accuracy at relatively low cost. Operating systems for such hardware configurations are generally not available. A real time multiprocessor operating system (RTMPOS) that supports a variety of multiprocessor configurations was developed at Lewis. With some modification, RTMPOS can also support various microprocessors. RTMPOS, by means of menus and prompts, provides the user with a versatile, user-friendly environment for interactively loading, running, and obtaining results from a multiprocessor-based simulator. The menu functions are described and an example simulation session is included to demonstrate the steps required to go from the simulation loading phase to the execution phase.

  4. Microprocessor-based control systems application in nuclear power plant critical systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Shah, M.R.; Nowak, J.B.

    Microprocessor-based control systems have been used in fossil power plants and are receiving greater acceptance for application in nuclear plants. This technology is not new but it does require unique considerations when applied to nuclear power plants. Sargent and Lundy (S and L) has used a microprocessor-based component logic control system (interposing Logic System) for safety- and non-safety-related components in nuclear power plants under construction overseas. Currently, S and L is in the design stage to replace an existing analog control system with a microprocessor-based control system in the U.S. The trend in the industry is to replace systems inmore » existing plants or design new power plants with microprocessor-based control systems.« less

  5. 75 FR 2591 - Petition for Waiver of Compliance

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-01-15

    ... on vital microprocessor-based systems. CSXT proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative procedures every 4 years after initial... vital microprocessor-based systems. These systems utilize programmed logic equations in lieu of relays...

  6. Software and languages for microprocessors

    NASA Astrophysics Data System (ADS)

    Williams, David O.

    1986-08-01

    This paper forms the basis for lectures given at the 6th Summer School on Computing Techniques in Physics, organised by the Computational Physics group of the European Physics Society, and held at the Hotel Ski, Nové Město na Moravě, Czechoslovakia, on 17-26 September 1985. Various types of microprocessor applications are discussed and the main emphasis of the paper is devoted to 'embedded' systems, where the software development is not carried out on the target microprocessor. Some information is provided on the general characteristics of microprocessor hardware. Various types of microprocessor operating system are compared and contrasted. The selection of appropriate languages and software environments for use with microprocessors is discussed. Mechanisms for interworking between different languages, including reasonable error handling, are treated. The CERN developed cross-software suite for the Motorola 68000 family is described. Some remarks are made concerning program tools applicable to microprocessors. PILS, a Portable Interactive Language System, which can be interpreted or compiled for a range of microprocessors, is described in some detail, and the implementation techniques are discussed.

  7. A Microprocessor Project for Non-Electrical Engineering Students.

    ERIC Educational Resources Information Center

    Swingler, D. N.

    1981-01-01

    Offers rationale for and a description of a microprocessor-based control system project for mechanical engineering students. Includes reasons for selecting a Texas Instruments TM990/189 microprocessor system. (SK)

  8. Microprocessors in Systems Engineering at the U.S. Naval Academy.

    ERIC Educational Resources Information Center

    Mitchell, Eugene E., Ed.; Lowe, W. M., Ed.

    1982-01-01

    Describes the introduction of microprocessors into the Weapons and Systems Engineering Department at the U.S. Naval Academy, including planning decisions, implementation, procedures, uses of microprocessors in the department, and impact on the Systems Engineering major and curriculum. (SK)

  9. Redundant Asynchronous Microprocessor System

    NASA Technical Reports Server (NTRS)

    Meyer, G.; Johnston, J. O.; Dunn, W. R.

    1985-01-01

    Fault-tolerant computer structure called RAMPS (for redundant asynchronous microprocessor system) has simplicity of static redundancy but offers intermittent-fault handling ability of complex, dynamically redundant systems. New structure useful wherever several microprocessors are employed for control - in aircraft, industrial processes, robotics, and automatic machining, for example.

  10. Microprocessor-based interface for oceanography

    NASA Technical Reports Server (NTRS)

    Hansen, G. R.

    1979-01-01

    Ocean floor imaging system incorporates five identical microprocessor-based interface units each assigned to specific sonar instrument to simplify system. Central control module based on same microprocessor eliminates need for custom tailoring hardware interfaces for each instrument.

  11. Microprocessor control of a wind turbine generator

    NASA Technical Reports Server (NTRS)

    Gnecco, A. J.; Whitehead, G. T.

    1978-01-01

    A microprocessor based system was used to control the unattended operation of a wind turbine generator. The turbine and its microcomputer system are fully described with special emphasis on the wide variety of tasks performed by the microprocessor for the safe and efficient operation of the turbine. The flexibility, cost and reliability of the microprocessor were major factors in its selection.

  12. JPRS Report, Science & Technology, China, High-Performance Computer Systems

    DTIC Science & Technology

    1992-10-28

    microprocessor array The microprocessor array in the AP85 system is com- posed of 16 completely identical array element micro - processors . Each array element...microprocessors and capable of host machine reading and writing. The memory capacity of the array element micro - processors as a whole can be expanded...transmission functions to carry out data transmission from array element micro - processor to array element microprocessor, from array element

  13. State recovery and lockstep execution restart in a system with multiprocessor pairing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Gara, Alan; Gschwind, Michael K; Salapura, Valentina

    System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switchmore » or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.« less

  14. The Effects of Microprocessors on Industry, Society and Employment: A Meeting of the Frontier Group on Strategies for Change in a Technological Society (Bath, England, March 13, 1979).

    ERIC Educational Resources Information Center

    Harris, N. D. C.

    Discussed are the multiple impacts of microelectronics on society. Included are discussions of the problem of predicting effects, difficulty of exploiting new technology, manpower consequences, and needs within the United Kingdom relating to microprocessors. (RE)

  15. TMS communications hardware. Volume 2: Bus interface unit

    NASA Technical Reports Server (NTRS)

    Brown, J. S.; Hopkins, G. T.

    1979-01-01

    A prototype coaxial cable bus communication system used in the Trend Monitoring System to interconnect intelligent graphics terminals to a host minicomputer is described. The terminals and host are connected to the bus through a microprocessor-based RF modem termed a Bus Interface Unit (BIU). The BIU hardware and the Carrier Sense Multiple Access Listen-While-Talk protocol used on the network are described.

  16. Microprocessor-Controlled Laser Balancing System

    NASA Technical Reports Server (NTRS)

    Demuth, R. S.

    1985-01-01

    Material removed by laser action as part tested for balance. Directed by microprocessor, laser fires appropriate amount of pulses in correct locations to remove necessary amount of material. Operator and microprocessor software interact through video screen and keypad; no programing skills or unprompted system-control decisions required. System provides complete and accurate balancing in single load-and-spinup cycle.

  17. SEU induced errors observed in microprocessor systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Asenek, V.; Underwood, C.; Oldfield, M.

    In this paper, the authors present software tools for predicting the rate and nature of observable SEU induced errors in microprocessor systems. These tools are built around a commercial microprocessor simulator and are used to analyze real satellite application systems. Results obtained from simulating the nature of SEU induced errors are shown to correlate with ground-based radiation test data.

  18. Scheduler for multiprocessor system switch with selective pairing

    DOEpatents

    Gara, Alan; Gschwind, Michael Karl; Salapura, Valentina

    2015-01-06

    System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

  19. Multitasking operating systems for microprocessors

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Cramer, T.

    1981-01-01

    Microprocessors, because of their low cost, low power consumption, and small size, have caused an explosion in the number of innovative computer applications. Although there is a great deal of variation in microprocessor applications software, there is relatively little variation in the operating-system-level software from one application to the next. Nonetheless, operating system software, especially when multitasking is involved, can be very time consuming and expensive to develop. The major microprocessor manufacturers have acknowledged the need for operating systems in microprocessor applications and are now supplying real-time multitasking operating system software that is adaptable to a wide variety of usermore » systems. Use of this existing operating system software will decrease the number of redundant operating system development efforts, thus freeing programmers to work on more creative and productive problems. This paper discusses the basic terminology and concepts involved with multitasking operating systems. It is intended to provide a general understanding of the subject, so that the reader will be prepared to evaluate specific operating system software according to his or her needs. 2 references.« less

  20. Mold heating and cooling microprocessor conversion. Final report

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hoffman, D.P.

    Conversion of the microprocessors and software for the Mold Heating and Cooling (MHAC) pump package control systems was initiated to allow required system enhancements and provide data communications capabilities with the Plastics Information and Control System (PICS). The existing microprocessor-based control systems for the pump packages use an Intel 8088-based microprocessor board with a maximum of 64 Kbytes of program memory. The requirements for the system conversion were developed, and hardware has been selected to allow maximum reuse of existing hardware and software while providing the required additional capabilities and capacity. The new hardware will incorporate an Intel 80286-based microprocessormore » board with an 80287 math coprocessor, the system includes additional memory, I/O, and RS232 communication ports.« less

  1. Bus-Programmable Slave Card

    NASA Technical Reports Server (NTRS)

    Hall, William A.

    1990-01-01

    Slave microprocessors in multimicroprocessor computing system contains modified circuit cards programmed via bus connecting master processor with slave microprocessors. Enables interactive, microprocessor-based, single-loop control. Confers ability to load and run program from master/slave bus, without need for microprocessor development station. Tristate buffers latch all data and information on status. Slave central processing unit never connected directly to bus.

  2. The development of a microprocessor-controlled linearly-actuated valve assembly

    NASA Technical Reports Server (NTRS)

    Wall, R. H.

    1984-01-01

    The development of a proportional fluid control valve assembly is presented. This electromechanical system is needed for space applications to replace the current proportional flow controllers. The flow is controlled by a microprocessor system that monitors the control parameters of upstream pressure and requested volumetric flow rate. The microprocessor achieves the proper valve stem displacement by means of a digital linear actuator. A linear displacement sensor is used to measure the valve stem position. This displacement is monitored by the microprocessor system as a feedback signal to close the control loop. With an upstream pressure between 15 and 47 psig, the developed system operates between 779 standard CU cm/sec (SCCS) and 1543 SCCS.

  3. A Micro-Processor Based System as a Teaching Tool.

    ERIC Educational Resources Information Center

    Spero, Samuel W.

    1979-01-01

    Two instructional strategies incorporating a microprocessor-based computer system are described. These are the use of the system to drive a television monitor, and the system's use in generating problem sets. (MP)

  4. Advanced microprocessor based power protection system using artificial neural network techniques

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Chen, Z.; Kalam, A.; Zayegh, A.

    This paper describes an intelligent embedded microprocessor based system for fault classification in power system protection system using advanced 32-bit microprocessor technology. The paper demonstrates the development of protective relay to provide overcurrent protection schemes for fault detection. It also describes a method for power fault classification in three-phase system based on the use of neural network technology. The proposed design is implemented and tested on a single line three phase power system in power laboratory. Both the hardware and software development are described in detail.

  5. External Verification of SCADA System Embedded Controller Firmware

    DTIC Science & Technology

    2012-03-01

    microprocessor and read-only memory (ROM) or flash memory for storing firmware and control logic [5],[8]. A PLC typically has three software levels as shown in...implementing different firmware. Because PLCs are in effect a microprocessor device, an analysis of the current research on embedded devices is important...Electronics Engineers (IEEE) published a 15 best practices guide for firmware control on microprocessors [44]. IEEE suggests that microprocessors

  6. OS friendly microprocessor architecture: Hardware level computer security

    NASA Astrophysics Data System (ADS)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  7. 76 FR 61476 - Petition for Waiver of Compliance

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-10-04

    ... locking; and 236.109, Time releases, timing relays and timing devices; on vital microprocessor-based... microprocessor-based locking systems. These tests, at this interval, would replace the tests currently required... listed in Exhibit B. 2. All future purchases of microprocessor-controlled interlocking locations. 3...

  8. Distributed asynchronous microprocessor architectures in fault tolerant integrated flight systems

    NASA Technical Reports Server (NTRS)

    Dunn, W. R.

    1983-01-01

    The paper discusses the implementation of fault tolerant digital flight control and navigation systems for rotorcraft application. It is shown that in implementing fault tolerance at the systems level using advanced LSI/VLSI technology, aircraft physical layout and flight systems requirements tend to define a system architecture of distributed, asynchronous microprocessors in which fault tolerance can be achieved locally through hardware redundancy and/or globally through application of analytical redundancy. The effects of asynchronism on the execution of dynamic flight software is discussed. It is shown that if the asynchronous microprocessors have knowledge of time, these errors can be significantly reduced through appropiate modifications of the flight software. Finally, the papear extends previous work to show that through the combined use of time referencing and stable flight algorithms, individual microprocessors can be configured to autonomously tolerate intermittent faults.

  9. Scaling theory for information networks.

    PubMed

    Moses, Melanie E; Forrest, Stephanie; Davis, Alan L; Lodder, Mike A; Brown, James H

    2008-12-06

    Networks distribute energy, materials and information to the components of a variety of natural and human-engineered systems, including organisms, brains, the Internet and microprocessors. Distribution networks enable the integrated and coordinated functioning of these systems, and they also constrain their design. The similar hierarchical branching networks observed in organisms and microprocessors are striking, given that the structure of organisms has evolved via natural selection, while microprocessors are designed by engineers. Metabolic scaling theory (MST) shows that the rate at which networks deliver energy to an organism is proportional to its mass raised to the 3/4 power. We show that computational systems are also characterized by nonlinear network scaling and use MST principles to characterize how information networks scale, focusing on how MST predicts properties of clock distribution networks in microprocessors. The MST equations are modified to account for variation in the size and density of transistors and terminal wires in microprocessors. Based on the scaling of the clock distribution network, we predict a set of trade-offs and performance properties that scale with chip size and the number of transistors. However, there are systematic deviations between power requirements on microprocessors and predictions derived directly from MST. These deviations are addressed by augmenting the model to account for decentralized flow in some microprocessor networks (e.g. in logic networks). More generally, we hypothesize a set of constraints between the size, power and performance of networked information systems including transistors on chips, hosts on the Internet and neurons in the brain.

  10. Multi-bit operations in vertical spintronic shift registers

    NASA Astrophysics Data System (ADS)

    Lavrijsen, Reinoud; Petit, Dorothée C. M. C.; Fernández-Pacheco, Amalio; Lee, JiHyun; Mansell, Mansell; Cowburn, Russell P.

    2014-03-01

    Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

  11. Multi-bit operations in vertical spintronic shift registers.

    PubMed

    Lavrijsen, Reinoud; Petit, Dorothée C M C; Fernández-Pacheco, Amalio; Lee, Jihyun; Mansell, Mansell; Cowburn, Russell P

    2014-03-14

    Spintronic devices have in general demonstrated the feasibility of non-volatile memory storage and simple Boolean logic operations. Modern microprocessors have one further frequently used digital operation: bit-wise operations on multiple bits simultaneously. Such operations are important for binary multiplication and division and in efficient microprocessor architectures such as reduced instruction set computing (RISC). In this paper we show a four-stage vertical serial shift register made from RKKY coupled ultrathin (0.9 nm) perpendicularly magnetised layers into which a 3-bit data word is injected. The entire four stage shift register occupies a total length (thickness) of only 16 nm. We show how under the action of an externally applied magnetic field bits can be shifted together as a word and then manipulated individually, including being brought together to perform logic operations. This is one of the highest level demonstrations of logic operation ever performed on data in the magnetic state and brings closer the possibility of ultrahigh density all-magnetic microprocessors.

  12. Small Microprocessor for ASIC or FPGA Implementation

    NASA Technical Reports Server (NTRS)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  13. 77 FR 30048 - Petition for Waiver of Compliance

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-05-21

    ... locking; and 236.381, Traffic locking on vital microprocessor-based systems. MNCW proposes to verify and test signal locking systems controlled by microprocessor-based equipment by use of alternative...

  14. Microprocessor Airborne Data Acquisition & Replay (MADAR) System,

    DTIC Science & Technology

    1984-03-01

    Time Record 7. TAPE USAGE 28 7.1 Geseral2 7.2 Tape Time Remanfng lbdocator 28 7.3 Tape Record Capacity 30 . 8. MODULE CONSTRUCTION 30 8.1 Gemeral...general purpose quick-fit type, calibrated for use with a range of different aircraft. The concept was modified such that the microprocessor module was not...dedicated to boom usage but a versatile instrument for other applications. The microprocessor module (Fig. 1) became known as the Microprocessor

  15. Concept report: Microprocessor control of electrical power system

    NASA Technical Reports Server (NTRS)

    Perry, E.

    1977-01-01

    An electrical power system which uses a microprocessor for systems control and monitoring is described. The microprocessor controlled system permits real time modification of system parameters for optimizing a system configuration, especially in the event of an anomaly. By reducing the components count, the assembling and testing of the unit is simplified, and reliability is increased. A resuable modular power conversion system capable of satisfying a large percentage of space applications requirements is examined along with the programmable power processor. The PC global controller which handles systems control and external communication is analyzed, and a software description is given. A systems application summary is also included.

  16. Orbit determination software development for microprocessor based systems: Evaluation and recommendations

    NASA Technical Reports Server (NTRS)

    Shenitz, C. M.; Mcgarry, F. E.; Tasaki, K. K.

    1980-01-01

    A guide is presented for National Aeronautics and Space Administration management personnel who stand to benefit from the lessons learned in developing microprocessor-based flight dynamics software systems. The essential functional characteristics of microprocessors are presented. The relevant areas of system support software are examined, as are the distinguishing characteristics of flight dynamics software. Design examples are provided to illustrate the major points presented, and actual development experience obtained in this area is provided as evidence to support the conclusions reached.

  17. The Stand-Alone Microprocessor System: A Valuable Tool in College Admissions and Recruitment.

    ERIC Educational Resources Information Center

    Garrett, Larry Neal

    1983-01-01

    The stand-alone microprocessor is seen as one innovative tool that can be used both in the organizational management of decline and in meeting specific organizational needs such as those of the admissions director and staff. The term "microprocessor" is defined. (MLW)

  18. Microprocessors in the Curriculum and the Classroom.

    ERIC Educational Resources Information Center

    Summers, M. K.

    1978-01-01

    This article, directed at teachers concerned with computer science courses at sixth-form level with no prior knowledge of microprocessors, provides a basic introduction, and describes possible applications of a microprocessor development system as a teaching aid in computer sciences courses in UK secondary school. (Author/RAO)

  19. Automated mixed traffic transit vehicle microprocessor controller

    NASA Technical Reports Server (NTRS)

    Marks, R. A.; Cassell, P.; Johnston, A. R.

    1981-01-01

    An improved Automated Mixed Traffic Vehicle (AMTV) speed control system employing a microprocessor and transistor chopper motor current controller is described and its performance is presented in terms of velocity versus time curves. The on board computer hardware and software systems are described as is the software development system. All of the programming used in this controller was implemented using FORTRAN. This microprocessor controller made possible a number of safety features and improved the comfort associated with starting and shopping. In addition, most of the vehicle's performance characteristics can be altered by simple program parameter changes. A failure analysis of the microprocessor controller was generated and the results are included. Flow diagrams for the speed control algorithms and complete FORTRAN code listings are also included.

  20. Simulated fault injection - A methodology to evaluate fault tolerant microprocessor architectures

    NASA Technical Reports Server (NTRS)

    Choi, Gwan S.; Iyer, Ravishankar K.; Carreno, Victor A.

    1990-01-01

    A simulation-based fault-injection method for validating fault-tolerant microprocessor architectures is described. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time to assess the resulting fault impact. As an example, a fault-tolerant architecture which models the digital aspects of a dual-channel real-time jet-engine controller is used. The level of effectiveness of the dual configuration with respect to single and multiple transients is measured. The results indicate 100 percent coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist.

  1. Multitasking OS manages a team of processors

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Ripps, D.L.

    1983-07-21

    MTOS-68k is a real-time multitasking operating system designed for the popular MC68000 microprocessors. It aproaches task coordination and synchronization in a fashion that matches uniquely the structural simplicity and regularity of the 68000 instruction set. Since in many 68000 applications the speed and power of one CPU are not enough, MTOS-68k has been designed to support multiple processors, as well as multiple tasks. Typically, the devices are tightly coupled single-board computers, that is they share a backplane and parts of global memory.

  2. General-Purpose Electronic System Tests Aircraft

    NASA Technical Reports Server (NTRS)

    Glover, Richard D.

    1989-01-01

    Versatile digital equipment supports research, development, and maintenance. Extended aircraft interrogation and display system is general-purpose assembly of digital electronic equipment on ground for testing of digital electronic systems on advanced aircraft. Many advanced features, including multiple 16-bit microprocessors, pipeline data-flow architecture, advanced operating system, and resident software-development tools. Basic collection of software includes program for handling many types of data and for displays in various formats. User easily extends basic software library. Hardware and software interfaces to subsystems provided by user designed for flexibility in configuration to meet user's requirements.

  3. 75 FR 22174 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

    Federal Register 2010, 2011, 2012, 2013, 2014

    2010-04-27

    ... passive antitheft device installed on the Porsche Panamera includes a microprocessor-based immobilizer... modified antitheft system will now consist of a microprocessor based immobilizer system which prevents...

  4. High-speed microprocessor characterization. Final report/project accomplishments summary, CRADA Number KCP-94-1004

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Brown, L.W.

    The objective of the project was to characterize and document the critical operating parameters of an 0.8-micron, 350-MHz, 32-bit microprocessor prototype. The roles of FM and T and the participant company were: FM and T -- evaluation performance of the prototype 32-bit microprocessor using the IDS5000 and Tektronix S3260 Integrated Circuit Test System; Corda -- design and build the prototype microprocessor. This project was terminated with nearly all of the planned activities unaddressed.

  5. Study and Design of Flight Data Recording Systems for Military Aircraft

    DTIC Science & Technology

    1976-06-01

    minicomputer (PDP-11/ 40 ) with 24K of core memory and a disk operating system. Peripherals include a CRT terminal, two 9-track magnetic tape drives, a 19 high...in question-answer mode. The NTSB plans to adapt an existing routine to the PDP 11/ 40 which will prepare a ground track of the aircraft from the...20 microseconds). Like PMOS memory, multiple power supplies were required. The next generation of microprocessors were implemented on a 40 pin package

  6. Microprocessor based implementation of attitude and shape control of large space structures

    NASA Technical Reports Server (NTRS)

    Reddy, A. S. S. R.

    1984-01-01

    The feasibility of off the shelf eight bit and 16 bit microprocessors to implement linear state variable feedback control laws and assessing the real time response to spacecraft dynamics is studied. The complexity of the dynamic model is described along with the appropriate software. An experimental setup of a beam, microprocessor system for implementing the control laws and the needed generalized software to implement any state variable feedback control system is included.

  7. The SMile Card: a computerised data card for multiple sclerosis patients. SMile Card Scientific Board.

    PubMed

    Mancardi, G L; Uccelli, M M; Sonnati, M; Comi, G; Milanese, C; De Vincentiis, A; Battaglia, M A

    2000-04-01

    The SMile Card was developed as a means for computerising clinical information for the purpose of transferability, accessibility, standardisation and compilation of a national database of demographic and clinical information about multiple sclerosis (MS) patients. In many European countries, centres for MS are organised independently from one another making collaboration, consultation and patient referral complicated. Only the more highly advanced clinical centres, generally located in large urban areas, have had the possibility to utilise technical possibilities for improving the organisation of patient clinical and research information, although independently from other centres. The information system, developed utilising the Visual Basic language for Microsoft Windows 95, stores information via a 'smart card' in a database which is initiated and updated utilising a microprocessor, located at each neurological clinic. The SMile Card, currently being tested in Italy, permits patients to carry with them all relevant medical information without limitations. Neurologists are able to access and update, via the microprocessor, the patient's entire medical history and MS-related information, including the complete neurological examination and laboratory test results. The SMile Card provides MS patients and neurologists with a complete computerised archive of clinical information which is accessible throughout the country. In addition, data from the SMile Card system can be exported to other database programs.

  8. A MICROPROCESSOR ASCII CHARACTER BUFFERING SYSTEM

    EPA Science Inventory

    A microprocessor buffering system (MBS) was developed at the Environmental Monitoring and Support Laboratory -Cincinnati (EMSL-CI) to provide an efficient transfer for serial ASCII information between intelligent instrument systema and a Data General NOVA laboratory automation co...

  9. Safety of Vital Control and Communication Systems in Guided Ground Transportation : Analysis of Railroad Signaling System Microprocessor Interlocking

    DOT National Transportation Integrated Search

    1993-05-01

    This study has been conducted with the goal of gaining an insight into the issues of maintaining vital signal systems implemented with microprocessor chips and of making field changes to the application of such systems. To relate these abstract topic...

  10. Special purpose parallel computer architecture for real-time control and simulation in robotic applications

    NASA Technical Reports Server (NTRS)

    Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

    1993-01-01

    This is a real-time robotic controller and simulator which is a MIMD-SIMD parallel architecture for interfacing with an external host computer and providing a high degree of parallelism in computations for robotic control and simulation. It includes a host processor for receiving instructions from the external host computer and for transmitting answers to the external host computer. There are a plurality of SIMD microprocessors, each SIMD processor being a SIMD parallel processor capable of exploiting fine grain parallelism and further being able to operate asynchronously to form a MIMD architecture. Each SIMD processor comprises a SIMD architecture capable of performing two matrix-vector operations in parallel while fully exploiting parallelism in each operation. There is a system bus connecting the host processor to the plurality of SIMD microprocessors and a common clock providing a continuous sequence of clock pulses. There is also a ring structure interconnecting the plurality of SIMD microprocessors and connected to the clock for providing the clock pulses to the SIMD microprocessors and for providing a path for the flow of data and instructions between the SIMD microprocessors. The host processor includes logic for controlling the RRCS by interpreting instructions sent by the external host computer, decomposing the instructions into a series of computations to be performed by the SIMD microprocessors, using the system bus to distribute associated data among the SIMD microprocessors, and initiating activity of the SIMD microprocessors to perform the computations on the data by procedure call.

  11. PDSparc: A Drop-in Replacement for LEON3 Written Using Synopsys Processor Designer

    DTIC Science & Technology

    2015-08-18

    Written Using  Synopsys Processor Designer1  David Whelihan, Ph.D. and Kate Thurmer  MIT Lincoln Laboratory, Lexington, MA, USA    ABSTRACT  Microprocessors ...internet-enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors... microprocessor is a small part of a working system and requires peripherals such as DRAM controllers and communication sub-systems to properly carry out its

  12. Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing

    PubMed Central

    Bravo, Ignacio; Baliñas, Javier; Gardel, Alfredo; Lázaro, José L.; Espinosa, Felipe; García, Jorge

    2011-01-01

    This article describes an image processing system based on an intelligent ad-hoc camera, whose two principle elements are a high speed 1.2 megapixel Complementary Metal Oxide Semiconductor (CMOS) sensor and a Field Programmable Gate Array (FPGA). The latter is used to control the various sensor parameter configurations and, where desired, to receive and process the images captured by the CMOS sensor. The flexibility and versatility offered by the new FPGA families makes it possible to incorporate microprocessors into these reconfigurable devices, and these are normally used for highly sequential tasks unsuitable for parallelization in hardware. For the present study, we used a Xilinx XC4VFX12 FPGA, which contains an internal Power PC (PPC) microprocessor. In turn, this contains a standalone system which manages the FPGA image processing hardware and endows the system with multiple software options for processing the images captured by the CMOS sensor. The system also incorporates an Ethernet channel for sending processed and unprocessed images from the FPGA to a remote node. Consequently, it is possible to visualize and configure system operation and captured and/or processed images remotely. PMID:22163739

  13. 46 CFR 62.25-25 - Programable systems and devices.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

  14. 46 CFR 62.25-25 - Programable systems and devices.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

  15. 46 CFR 62.25-25 - Programable systems and devices.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

  16. 46 CFR 62.25-25 - Programable systems and devices.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ...-25 Shipping COAST GUARD, DEPARTMENT OF HOMELAND SECURITY (CONTINUED) MARINE ENGINEERING VITAL SYSTEM... range of the equipment. (b) Operating programs for microprocessor-based or computer-based vital control... power resumption. (c) If a microprocessor-based or computer-based system serves both vital and non-vital...

  17. A microprocessor-based one dimensional optical data processor for spatial frequency analysis

    NASA Technical Reports Server (NTRS)

    Collier, R. L.; Ballard, G. S.

    1982-01-01

    A high degree of accuracy was obtained in measuring the spatial frequency spectrum of known samples using an optical data processor based on a microprocessor, which reliably collected intensity versus angle data. Stray light control, system alignment, and angle measurement problems were addressed and solved. The capabilities of the instrument were extended by the addition of appropriate optics to allow the use of different wavelengths of laser radiation and by increasing the travel limits of the rotating arm to + or - 160 degrees. The acquisition, storage, and plotting of data by the computer permits the researcher a free hand in data manipulation such as subtracting background scattering from a diffraction pattern. Tests conducted to verify the operation of the processor using a 25 mm diameter pinhole, a 39.37 line pairs per mm series of multiple slits, and a microscope slide coated with 1.091 mm diameter polystyrene latex spheres are described.

  18. An assembler for the MOS Technology 6502 microprocessor as implemented in jolt (TM) and KIM-1 (TM)

    NASA Technical Reports Server (NTRS)

    Lilley, R. W.

    1976-01-01

    Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.

  19. Maxi CAI with a Micro.

    ERIC Educational Resources Information Center

    Gerhold, George; And Others

    This paper describes an effective microprocessor-based CAI system which has been repeatedly tested by a large number of students and edited accordingly. Tasks not suitable for microprocessor based systems (authoring, testing, and debugging) were handled on larger multi-terminal systems. This approach requires that the CAI language used on the…

  20. Multiplex electric discharge gas laser system

    NASA Technical Reports Server (NTRS)

    Laudenslager, James B. (Inventor); Pacala, Thomas J. (Inventor)

    1987-01-01

    A multiple pulse electric discharge gas laser system is described in which a plurality of pulsed electric discharge gas lasers are supported in a common housing. Each laser is supplied with excitation pulses from a separate power supply. A controller, which may be a microprocessor, is connected to each power supply for controlling the application of excitation pulses to each laser so that the lasers can be fired simultaneously or in any desired sequence. The output light beams from the individual lasers may be combined or utilized independently, depending on the desired application. The individual lasers may include multiple pairs of discharge electrodes with a separate power supply connected across each electrode pair so that multiple light output beams can be generated from a single laser tube and combined or utilized separately.

  1. Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device.

    PubMed

    Picone, Rico A R; Davis, Solomon; Devine, Cameron; Garbini, Joseph L; Sidles, John A

    2017-04-01

    We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

  2. Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

    NASA Astrophysics Data System (ADS)

    Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

    2017-04-01

    We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

  3. Establishment of cells to monitor Microprocessor through fusion genes of microRNA and GFP

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Tsutsui, Motomu; Hasegawa, Hitoki; Adachi, Koichi

    Microprocessor, the complex of Drosha and DGCR8, promotes the processing of primary microRNA to precursor microRNA, which is a crucial step for microRNA maturation. So far, no convenient assay systems have been developed for observing this step in vivo. Here we report the establishment of highly sensitive cellular systems where we can visually monitor the function of Microprocessor. During a series of screening of transfectants with fusion genes of the EGFP cDNA and primary microRNA genes, we have obtained certain cell lines where introduction of siRNA against DGCR8 or Drosha strikingly augments GFP signals. In contrast, these cells have notmore » responded to Dicer siRNA; thus they have a unique character that GFP signals should be negatively and specifically correlated to the action of Microprocessor among biogenesis of microRNA. These cell lines can be useful tools for real-time analysis of Microprocessor action in vivo and identifying its novel modulators.« less

  4. Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

    NASA Technical Reports Server (NTRS)

    Belcastro, C. M.

    1984-01-01

    A methodology was developed a assess the upset susceptibility/reliability of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general purpose microprocessor were studied. The upset tests involved the random input of analog transients which model lightning induced signals onto interface lines of an 8080 based microcomputer from which upset error data was recorded. The program code on the microprocessor during tests is designed to exercise all of the machine cycles and memory addressing techniques implemented in the 8080 central processing unit. A statistical analysis is presented in which possible correlations are established between the probability of upset occurrence and transient signal inputs during specific processing states and operations. A stochastic upset susceptibility model for the 8080 microprocessor is presented. The susceptibility of this microprocessor to upset, once analog transients have entered the system, is determined analytically by calculating the state probabilities of the stochastic model.

  5. A microprocessor application to a strapdown laser gyro navigator

    NASA Technical Reports Server (NTRS)

    Giardina, C.; Luxford, E.

    1980-01-01

    The replacement of analog circuit control loops for laser gyros (path length control, cross axis temperature compensation loops, dither servo and current regulators) with digital filters residing in microcomputers is addressed. In addition to the control loops, a discussion is given on applying the microprocessor hardware to compensation for coning and skulling motion where simple algorithms are processed at high speeds to compensate component output data (digital pulses) for linear and angular vibration motions. Highlights are given on the methodology and system approaches used in replacing differential equations describing the analog system in terms of the mechanized difference equations of the microprocessor. Standard one for one frequency domain techniques are employed in replacing analog transfer functions by their transform counterparts. Direct digital design techniques are also discussed along with their associated benefits. Time and memory loading analyses are also summarized, as well as signal and microprocessor architecture. Trade offs in algorithm, mechanization, time/memory loading, accuracy, and microprocessor architecture are also given.

  6. The formal verification of generic interpreters

    NASA Technical Reports Server (NTRS)

    Windley, P.; Levitt, K.; Cohen, G. C.

    1991-01-01

    The task assignment 3 of the design and validation of digital flight control systems suitable for fly-by-wire applications is studied. Task 3 is associated with formal verification of embedded systems. In particular, results are presented that provide a methodological approach to microprocessor verification. A hierarchical decomposition strategy for specifying microprocessors is also presented. A theory of generic interpreters is presented that can be used to model microprocessor behavior. The generic interpreter theory abstracts away the details of instruction functionality, leaving a general model of what an interpreter does.

  7. Coed Transactions, Vol. XI, No. 1, January 1979. Microprocessor Course Development Equipment Selection.

    ERIC Educational Resources Information Center

    Mitchell, Eugene E., Ed.; Leventhal, Lance A.

    Many devices and systems related to microprocessors are available on the marketplace. The author suggests that criteria for selecting and designing workstations and development systems are necessary. Seventeen important factors of designing workstations and six desirable features of a development system are presented. The kinds of places in which…

  8. Smart motor technology

    NASA Technical Reports Server (NTRS)

    Packard, D.; Schmitt, D.

    1984-01-01

    Current spacecraft design relies upon microprocessor control; however, motors usually require extensive additional electronic circuitry to interface with these microprocessor controls. An improved control technique that allows a smart brushless motor to connect directly to a microprocessor control system is described. An actuator with smart motors receives a spacecraft command directly and responds in a closed loop control mode. In fact, two or more smart motors can be controlled for synchronous operation.

  9. Microprocessor design for GaAs technology

    NASA Astrophysics Data System (ADS)

    Milutinovic, Veljko M.

    Recent advances in the design of GaAs microprocessor chips are examined in chapters contributed by leading experts; the work is intended as reading material for a graduate engineering course or as a practical R&D reference. Topics addressed include the methodology used for the architecture, organization, and design of GaAs processors; GaAs device physics and circuit design; design concepts for microprocessor-based GaAs systems; a 32-bit GaAs microprocessor; a 32-bit processor implemented in GaAs JFET; and a direct coupled-FET-logic E/D-MESFET experimental RISC machine. Drawings, micrographs, and extensive circuit diagrams are provided.

  10. Loran-C digital word generator for use with a KIM-1 microprocessor system

    NASA Technical Reports Server (NTRS)

    Nickum, J. D.

    1977-01-01

    The problem of translating the time of occurrence of received Loran-C pulses into a time, referenced to a particular period of occurrence is addressed and applied to the design of a digital word generator for a Loran-C sensor processor package. The digital information from this word generator is processed in a KIM-1 microprocessor system which is based on the MOS 6502 CPU. This final system will consist of a complete time difference sensor processor for determining position information using Loran-C charts. The system consists of the KIM-1 microprocessor module, a 4K RAM memory board, a user interface, and the Loran-C word generator.

  11. A microprocessor-based system for continuous monitoring of radiation levels around the CERN PS and PSB accelerators

    NASA Astrophysics Data System (ADS)

    Agoritsas, V.; Beck, F.; Benincasa, G. P.; Bovigny, J. P.

    1986-06-01

    This paper describes a new beam loss monitor system which has been installed in the PS and PSB machines, replacing an earlier system. The new system is controlled by a microprocessor which can operate independently of the accelerator control system, though setting up and central display are usually done remotely, using the standard control system facilities.

  12. Microprocessor control of photovoltaic systems

    NASA Technical Reports Server (NTRS)

    Millner, A. R.; Kaufman, D. L.

    1984-01-01

    The present low power CMOS microprocessor controller for photovoltaic power systems possesses three programs, which are respectively intended for (1) conventional battery-charging systems with state-of-charge estimation and sequential shedding of subarrays and loads, (2) maximum power-controlled battery-charging systems, and (3) variable speed dc motor drives. Attention is presently given to the development of this terrestrial equipment for spacecraft use.

  13. Pain and efficacy rating of a microprocessor-controlled metered injection system for local anaesthesia in minor hand surgery.

    PubMed

    Nimigan, André S; Gan, Bing Siang

    2011-01-01

    Purpose. Little attention has been given to syringe design and local anaesthetic administration methods. A microprocessor-controlled anaesthetic delivery device has become available that may minimize discomfort during injection. The purpose of this study was to document the pain experience associated with the use of this system and to compare it with use of a conventional syringe. Methods. A prospective, randomized clinical trial was designed. 40 patients undergoing carpal tunnel release were block randomized according to sex into a two groups: a traditional syringe group and a microprocessor-controlled device group. The primary outcome measure was surgical pain and local anaesthetic administration pain. Secondary outcomes included volume of anaesthetic used and injection time. Results. Analysis showed that equivalent anaesthesia was achieved in the microprocessor-controlled group despite using a significantly lower volume of local anaesthetic (P = .0002). This same group, however, has significantly longer injection times (P < .0001). Pain during the injection process or during surgery was not different between the two groups. Conclusions. This RCT comparing traditional and microprocessor controlled methods of administering local anaesthetic showed similar levels of discomfort in both groups. While the microprocessor-controlled group used less volume, the total time for the administration was significantly greater.

  14. Manufacturing Methods and Technology for Digital Fault Isolation of Hybrid Microelectronic Assemblies.

    DTIC Science & Technology

    1982-03-01

    Aircraft Company ARECAaSOENT CSR Ground Systems Group Task 007 Fullerton, California 92634 Project No. R1023 I$. =OTRS4.IWmOr SP NAnE lAD ABDASE it. REPORT...HMA feed mechanism, multiple type test sockets or adapters, and a localized UUT vessel for functional tests at temperature. The engineering model AP...test excluding (deactivated) microprocessor. * Models UUT and test adapter as a ROM. Independent latches or registers from interconnecting ports to

  15. Development and testing of the Rho Sigma Incorporated microprocessor control subsystem

    NASA Technical Reports Server (NTRS)

    Hankins, J. D.

    1979-01-01

    Product development and performance tests of three programmable microprocessor controllers for use with solar heating and cooling systems are presented. The products were developed to be marketable for public use.

  16. 77 FR 22384 - Petition To Modify an Exemption of a Previously Approved Antitheft Device; Porsche

    Federal Register 2010, 2011, 2012, 2013, 2014

    2012-04-13

    ... passive, microprocessor-based device which includes a starter interrupt function, transponder key and a.... Porsche stated that the antitheft system consists of two major subsystems: a microprocessor-based...

  17. 47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

  18. 47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

  19. 47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

  20. 47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

  1. 47 CFR 15.32 - Test procedures for CPU boards and computer power supplies.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... result in a complete personal computer system. If the oscillator and the microprocessor circuits are... microprocessor circuits are contained on separate circuit boards, both boards, typical of the combination that...

  2. The design of a microprocessor-based data logger

    USGS Publications Warehouse

    Leap, K.J.; Dedini, L.A.

    1982-01-01

    The design of a microprocessor-based data logger, which collects and digitizes analog voltage signals from a continuous-measuring instrumentation system and transmits serial data to a magnetic tape recorder, is discussed. The data logger was assembled from commercially-available components and can be user-programmed for greater flexibility. A description of the data logger hardware and software designs, general operating instructions, the microprocessor program listing, and electrical schematic diagrams are presented.

  3. Real-time fetal ECG system design using embedded microprocessors

    NASA Astrophysics Data System (ADS)

    Meyer-Baese, Uwe; Muddu, Harikrishna; Schinhaerl, Sebastian; Kumm, Martin; Zipf, Peter

    2016-05-01

    The emphasis of this project lies in the development and evaluation of new robust and high fidelity fetal electrocardiogram (FECG) systems to determine the fetal heart rate (FHR). Recently several powerful algorithms have been suggested to improve the FECG fidelity. Until now it is unknown if these algorithms allow a real-time processing, can be used in mobile systems (low power), and which algorithm produces the best error rate for a given system configuration. In this work we have developed high performance, low power microprocessor-based biomedical systems that allow a fair comparison of proposed, state-of-the-art FECG algorithms. We will evaluate different soft-core microprocessors and compare these solutions to other commercial off-the-shelf (COTS) hardcore solutions in terms of price, size, power, and speed.

  4. A floating-point/multiple-precision processor for airborne applications

    NASA Technical Reports Server (NTRS)

    Yee, R.

    1982-01-01

    A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

  5. An assessment of the connection machine

    NASA Technical Reports Server (NTRS)

    Schreiber, Robert

    1990-01-01

    The CM-2 is an example of a connection machine. The strengths and problems of this implementation are considered as well as important issues in the architecture and programming environment of connection machines in general. These are contrasted to the same issues in Multiple Instruction/Multiple Data (MIMD) microprocessors and multicomputers.

  6. The Use of Opto-Electronics in Viscometry.

    ERIC Educational Resources Information Center

    Mazza, R. J.; Washbourn, D. H.

    1982-01-01

    Describes a semi-automatic viscometer which incorporates a microprocessor system and uses optoelectronics to detect flow of liquid through the capillary, flow time being displayed on a timer with accuracy of 0.01 second. The system could be made fully automatic with an additional microprocessor circuit and inclusion of a pump. (Author/JN)

  7. Could a neuroscientist understand a microprocessor?

    DOE PAGES

    Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

    2017-01-12

    There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

  8. Could a Neuroscientist Understand a Microprocessor?

    PubMed Central

    Kording, Konrad Paul

    2017-01-01

    There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods. PMID:28081141

  9. Could a Neuroscientist Understand a Microprocessor?

    PubMed

    Jonas, Eric; Kording, Konrad Paul

    2017-01-01

    There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods from neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Additionally, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.

  10. Could a neuroscientist understand a microprocessor?

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Jonas, Eric; Kording, Konrad Paul; Diedrichsen, Jorn

    There is a popular belief in neuroscience that we are primarily data limited, and that producing large, multimodal, and complex datasets will, with the help of advanced data analysis algorithms, lead to fundamental insights into the way the brain processes information. These datasets do not yet exist, and if they did we would have no way of evaluating whether or not the algorithmically-generated insights were sufficient or even correct. To address this, here we take a classical microprocessor as a model organism, and use our ability to perform arbitrary experiments on it to see if popular data analysis methods frommore » neuroscience can elucidate the way it processes information. Microprocessors are among those artificial information processing systems that are both complex and that we understand at all levels, from the overall logical flow, via logical gates, to the dynamics of transistors. We show that the approaches reveal interesting structure in the data but do not meaningfully describe the hierarchy of information processing in the microprocessor. This suggests current analytic approaches in neuroscience may fall short of producing meaningful understanding of neural systems, regardless of the amount of data. Furthermore, we argue for scientists using complex non-linear dynamical systems with known ground truth, such as the microprocessor as a validation platform for time-series and structure discovery methods.« less

  11. Virtual Instrument Simulator for CERES

    NASA Technical Reports Server (NTRS)

    Chapman, John J.

    1997-01-01

    A benchtop virtual instrument simulator for CERES (Clouds and the Earth's Radiant Energy System) has been built at NASA, Langley Research Center in Hampton, VA. The CERES instruments will fly on several earth orbiting platforms notably NASDA's Tropical Rainfall Measurement Mission (TRMM) and NASA's Earth Observing System (EOS) satellites. CERES measures top of the atmosphere radiative fluxes using microprocessor controlled scanning radiometers. The CERES Virtual Instrument Simulator consists of electronic circuitry identical to the flight unit's twin microprocessors and telemetry interface to the supporting spacecraft electronics and two personal computers (PC) connected to the I/O ports that control azimuth and elevation gimbals. Software consists of the unmodified TRW developed Flight Code and Ground Support Software which serves as the instrument monitor and NASA/TRW developed engineering models of the scanners. The CERES Instrument Simulator will serve as a testbed for testing of custom instrument commands intended to solve in-flight anomalies of the instruments which could arise during the CERES mission. One of the supporting computers supports the telemetry display which monitors the simulator microprocessors during the development and testing of custom instrument commands. The CERES engineering development software models have been modified to provide a virtual instrument running on a second supporting computer linked in real time to the instrument flight microprocessor control ports. The CERES Instrument Simulator will be used to verify memory uploads by the CERES Flight Operations TEAM at NASA. Plots of the virtual scanner models match the actual instrument scan plots. A high speed logic analyzer has been used to track the performance of the flight microprocessor. The concept of using an identical but non-flight qualified microprocessor and electronics ensemble linked to a virtual instrument with identical system software affords a relatively inexpensive simulation system capable of high fidelity.

  12. Control methodologies for large space structures

    NASA Technical Reports Server (NTRS)

    Mcree, G. J.; Altonji, E.

    1984-01-01

    The objectives of this research were to develop techniques of controlling a dc-motor driven flywheel which would apply torque to the structure to which it was mounted. The motor control system was to be implemented using a microprocessor based controller. The purpose of the torque applied by this system was to dampen oscillations of the structure to which it was mounted. Before the work was terminated due to the unavailability of equipment, a system was developed and partially tested which would provide tight control of the flywheel velocity when it received a velocity command in the form of a voltage. The procedure followed in this development was to first model the motor and flywheel system on an analog computer. Prior to the time the microprocessor development system was available, an analog control loop was replaced by the microprocessor and the system was partially tested.

  13. MICROPROCESSOR CONTROL OF ROTOGRAVURE AIRFLOWS

    EPA Science Inventory

    The report discusses the technical and economic viability of using micro-processor-based control technology to collect volatile organic compound (VOC) emissions from a paper coating operation. The microprocessor-based control system monitors and controls both the airflow rate and...

  14. Pupillometry, a bioengineering overview

    NASA Technical Reports Server (NTRS)

    Myers, G.; Anchetta, J.; Hannaford, B.; Peng, P.; Sherman, K.; Stark, L.; Sun, F.; Usui, S.

    1981-01-01

    The pupillary control system is examined using a microprocessor based integrative pupillometer. The real time software functions of the microprocessor include: data collection, stimulus generation and area to diameter conversion. Results of an analysis of linear and nonlinear phenomena are presented.

  15. Bristol Ridge: A 28-nm $$\\times$$ 86 Performance-Enhanced Microprocessor Through System Power Management

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Sundaram, Sriram; Grenat, Aaron; Naffziger, Samuel

    Power management techniques can be effective at extracting more performance and energy efficiency out of mature systems on chip (SoCs). For instance, the peak performance of microprocessors is often limited by worst case technology (Vmax), infrastructure (thermal/electrical), and microprocessor usage assumptions. Performance/watt of microprocessors also typically suffers from guard bands associated with the test and binning processes as well as worst case aging/lifetime degradation. Similarly, on multicore processors, shared voltage rails tend to limit the peak performance achievable in low thread count workloads. In this paper, we describe five power management techniques that maximize the per-part performance under the before-mentionedmore » constraints. Using these techniques, we demonstrate a net performance increase of up to 15% depending on the application and TDP of the SoC, implemented on 'Bristol Ridge,' a 28-nm CMOS, dual-core x 86 accelerated processing unit.« less

  16. Photonic Integrated Circuits

    NASA Technical Reports Server (NTRS)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  17. Preliminary design and development of a reflectance spectrometer instrument

    NASA Technical Reports Server (NTRS)

    Mccord, T. B.

    1979-01-01

    An improved design for the reflectance spectrometer is described to be used on various terrestrial body missions. These improvements were made on the original Lunar Polar Orbiter design. These include a larger entrance mirror, rectangular aperture, multiple optical beams, spatial resolution, and a bandwidth extension to 5 microns. In addition, detailed electronic designs were produced for a charge amplifier and an amplifier/demodulator/integrator. Design of a microprocessor driven test system was begun. Laboratory tests were performed on a tuning fork chopper.

  18. Applications of Microcomputers in the Teaching of Physics 6502 Software.

    ERIC Educational Resources Information Center

    Marsh, David P.

    1980-01-01

    Described is a variety of uses of the microcomputer when coupled with software available for systems using 6502 microprocessors. Included are several computer programs which exhibit some of the possibilities for programing the 6502 microprocessors. (DS)

  19. Automated quantitative muscle biopsy analysis system

    NASA Technical Reports Server (NTRS)

    Castleman, Kenneth R. (Inventor)

    1980-01-01

    An automated system to aid the diagnosis of neuromuscular diseases by producing fiber size histograms utilizing histochemically stained muscle biopsy tissue. Televised images of the microscopic fibers are processed electronically by a multi-microprocessor computer, which isolates, measures, and classifies the fibers and displays the fiber size distribution. The architecture of the multi-microprocessor computer, which is iterated to any required degree of complexity, features a series of individual microprocessors P.sub.n each receiving data from a shared memory M.sub.n-1 and outputing processed data to a separate shared memory M.sub.n+1 under control of a program stored in dedicated memory M.sub.n.

  20. Design of a microprocessor-based Control, Interface and Monitoring (CIM unit for turbine engine controls research

    NASA Technical Reports Server (NTRS)

    Delaat, J. C.; Soeder, J. F.

    1983-01-01

    High speed minicomputers were used in the past to implement advanced digital control algorithms for turbine engines. These minicomputers are typically large and expensive. It is desirable for a number of reasons to use microprocessor-based systems for future controls research. They are relatively compact, inexpensive, and are representative of the hardware that would be used for actual engine-mounted controls. The Control, Interface, and Monitoring Unit (CIM) contains a microprocessor-based controls computer, necessary interface hardware and a system to monitor while it is running an engine. It is presently being used to evaluate an advanced turbofan engine control algorithm.

  1. Design description of a microprocessor based Engine Monitoring and Control unit (EMAC) for small turboshaft

    NASA Technical Reports Server (NTRS)

    Baez, A. N.

    1985-01-01

    Research programs have demonstrated that digital electronic controls are more suitable for advanced aircraft/rotorcraft turbine engine systems than hydromechanical controls. Commercially available microprocessors are believed to have the speed and computational capability required for implementing advanced digital control algorithms. Thus, it is desirable to demonstrate that off-the-shelf microprocessors are indeed capable of performing real time control of advanced gas turbine engines. The engine monitoring and control (EMAC) unit was designed and fabricated specifically to meet the requirements of an advanced gas turbine engine control system. The EMAC unit is fully operational in the Army/NASA small turboshaft engine digital research program.

  2. Microprocessor controlled advanced battery management systems

    NASA Technical Reports Server (NTRS)

    Payne, W. T.

    1978-01-01

    The advanced battery management system described uses the capabilities of an on-board microprocessor to: (1) monitor the state of the battery on a cell by cell basis; (2) compute the state of charge of each cell; (3) protect each cell from reversal; (4) prevent overcharge on each individual cell; and (5) control dual rate reconditioning to zero volts per cell.

  3. The Minerva Multi-Microprocessor.

    DTIC Science & Technology

    A multiprocessor system is described which is an experiment in low cost, extensible, multiprocessor architectures. Global issues such as inclusion of a central bus, design of the bus arbiter, and methods of interrupt handling are considered. The system initially includes two processor types, based on microprocessors, and these are discussed. Methods for reducing processor demand for the central bus are described.

  4. Hyperswitch communication network

    NASA Technical Reports Server (NTRS)

    Peterson, J.; Pniel, M.; Upchurch, E.

    1991-01-01

    The Hyperswitch Communication Network (HCN) is a large scale parallel computer prototype being developed at JPL. Commercial versions of the HCN computer are planned. The HCN computer being designed is a message passing multiple instruction multiple data (MIMD) computer, and offers many advantages in price-performance ratio, reliability and availability, and manufacturing over traditional uniprocessors and bus based multiprocessors. The design of the HCN operating system is a uniquely flexible environment that combines both parallel processing and distributed processing. This programming paradigm can achieve a balance among the following competing factors: performance in processing and communications, user friendliness, and fault tolerance. The prototype is being designed to accommodate a maximum of 64 state of the art microprocessors. The HCN is classified as a distributed supercomputer. The HCN system is described, and the performance/cost analysis and other competing factors within the system design are reviewed.

  5. Evolution of a standard microprocessor-based space computer

    NASA Technical Reports Server (NTRS)

    Fernandez, M.

    1980-01-01

    An existing in inventory computer hardware/software package (B-1 RFS/ECM) was repackaged and applied to multiple missile/space programs. Concurrent with the application efforts, low risk modifications were made to the computer from program to program to take advantage of newer, advanced technology and to meet increasingly more demanding requirements (computational and memory capabilities, longer life, and fault tolerant autonomy). It is concluded that microprocessors hold promise in a number of critical areas for future space computer applications. However, the benefits of the DoD VHSIC Program are required and the old proliferation problem must be revised.

  6. Generalized fast feedback system in the SLC

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Hendrickson, L.; Allison, S.; Gromme, T.

    A generalized fast feedback system has been developed to stabilize beams at various locations in the SLC. The system is designed to perform measurements and change actuator settings to control beam states such as position, angle and energy on a pulse to pulse basis. The software design is based on the state space formalism of digital control theory. The system is database-driven, facilitating the addition of new loops without requiring additional software. A communications system, KISNet, provides fast communications links between microprocessors for feedback loops which involve multiple micros. Feedback loops have been installed in seventeen locations throughout the SLCmore » and have proven to be invaluable in stabilizing the machine.« less

  7. Applying Ada to Beech Starship avionics

    NASA Technical Reports Server (NTRS)

    Funk, David W.

    1986-01-01

    As Ada solidified in its development, it became evident that it offered advantages for avionics systems because of it support for modern software engineering principles and real time applications. An Ada programming support environment was developed for two major avionics subsystems in the Beech Starship. The two subsystems include electronic flight instrument displays and the flight management computer system. Both of these systems use multiple Intel 80186 microprocessors. The flight management computer provides flight planning, navigation displays, primary flight display of checklists and other pilot advisory information. Together these systems represent nearly 80,000 lines of Ada source code and to date approximately 30 man years of effort. The Beech Starship avionics systems are in flight testing.

  8. Network command processing system overview

    NASA Technical Reports Server (NTRS)

    Nam, Yon-Woo; Murphy, Lisa D.

    1993-01-01

    The Network Command Processing System (NCPS) developed for the National Aeronautics and Space Administration (NASA) Ground Network (GN) stations is a spacecraft command system utilizing a MULTIBUS I/68030 microprocessor. This system was developed and implemented at ground stations worldwide to provide a Project Operations Control Center (POCC) with command capability for support of spacecraft operations such as the LANDSAT, Shuttle, Tracking and Data Relay Satellite, and Nimbus-7. The NCPS consolidates multiple modulation schemes for supporting various manned/unmanned orbital platforms. The NCPS interacts with the POCC and a local operator to process configuration requests, generate modulated uplink sequences, and inform users of the ground command link status. This paper presents the system functional description, hardware description, and the software design.

  9. Implementation of kernels on the Maestro processor

    NASA Astrophysics Data System (ADS)

    Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

    Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

  10. Low-power circuits design for the wireless force measurement system of the total knee arthroplasty.

    PubMed

    Chen, Hong; Liu, Ming; Wan, Weiyi; Jia, Chen; Zhang, Chun; Wang, Zihua

    2010-01-01

    This paper proposes a novel wireless force measurement system for the Total Knee Arthroplasty (TKA) to improve the ligament balancing procedure during TKA. The force measurement system is comprised of a Wireless Force Measurement Spacer (WFMS) and the display part. They communicate with each other by the Radio Frequency (RF) signal. The WFMS is designed to measure the force between the WFMS and the femoral component of the artificial implants and to transmit the force data wirelessly by a low power transceiver. The display part demonstrates the force data in 3D images in real time. The WFMS composes of a sensors array, a Universal Transducer Interfaces (UTIs) array, a low-power sub-threshold microprocessor and a transceiver. The sub-threshold 8-bit microprocessor is taped out with 0.18 microm CMOS technology. The testing results of the microprocessor show that the leakage power of 46nW and the dynamic power of 385nW@165kHz are achieved with the operating voltage of 350 mV. The test results of the system are given and the errors of the system are analyzed. The results verified the reliability of the system. The future work is to design the microprocessor and a lower power transceiver within a single chip.

  11. Small Private Key PKS on an Embedded Microprocessor

    PubMed Central

    Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

    2014-01-01

    Multivariate quadratic ( ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012. PMID:24651722

  12. Small private key MQPKS on an embedded microprocessor.

    PubMed

    Seo, Hwajeong; Kim, Jihyun; Choi, Jongseok; Park, Taehwan; Liu, Zhe; Kim, Howon

    2014-03-19

    Multivariate quadratic (MQ) cryptography requires the use of long public and private keys to ensure a sufficient security level, but this is not favorable to embedded systems, which have limited system resources. Recently, various approaches to MQ cryptography using reduced public keys have been studied. As a result of this, at CHES2011 (Cryptographic Hardware and Embedded Systems, 2011), a small public key MQ scheme, was proposed, and its feasible implementation on an embedded microprocessor was reported at CHES2012. However, the implementation of a small private key MQ scheme was not reported. For efficient implementation, random number generators can contribute to reduce the key size, but the cost of using a random number generator is much more complex than computing MQ on modern microprocessors. Therefore, no feasible results have been reported on embedded microprocessors. In this paper, we propose a feasible implementation on embedded microprocessors for a small private key MQ scheme using a pseudo-random number generator and hash function based on a block-cipher exploiting a hardware Advanced Encryption Standard (AES) accelerator. To speed up the performance, we apply various implementation methods, including parallel computation, on-the-fly computation, optimized logarithm representation, vinegar monomials and assembly programming. The proposed method reduces the private key size by about 99.9% and boosts signature generation and verification by 5.78% and 12.19% than previous results in CHES2012.

  13. [An integral chip for the multiphase pulse-duration modulation used for voltage changer in biomedical microprocessor systems].

    PubMed

    Balashov, A M; Selishchev, S V

    2004-01-01

    An integral chip (IC) was designed for controlling the step-down pulse voltage converter, which is based on the multiphase pulse-duration modulation, for use in biomedical microprocessor systems. The CMOS technology was an optimal basis for the IC designing. An additional feedback circuit diminishes the output voltage dispersion at dynamically changing loads.

  14. Mark IVA microprocessor support

    NASA Technical Reports Server (NTRS)

    Burford, A. L.

    1982-01-01

    The requirements and plans for the maintenance support of microprocessor-based controllers in the Deep Space Network Mark IVA System are discussed. Additional new interfaces and 16-bit processors have introduced problems not present in the Mark III System. The need for continuous training of maintenance personnel to maintain a level of expertise consistent with the sophistication of the required tools is also emphasized.

  15. Gait termination on a declined surface in trans-femoral amputees: Impact of using microprocessor-controlled limb system.

    PubMed

    Abdulhasan, Zahraa M; Scally, Andy J; Buckley, John G

    2018-05-30

    Walking down ramps is a demanding task for transfemoral-amputees and terminating gait on ramps is even more challenging because of the requirement to maintain a stable limb so that it can do the necessary negative mechanical work on the centre-of-mass in order to arrest (dissipate) forward/downward velocity. We determined how the use of a microprocessor-controlled limb system (simultaneous control over hydraulic resistances at ankle and knee) affected the negative mechanical work done by each limb when transfemoral-amputees terminated gait during ramp descent. Eight transfemoral-amputees completed planned gait terminations (stopping on prosthesis) on a 5-degree ramp from slow and customary walking speeds, with the limb's microprocessor active or inactive. When active the limb operated in its 'ramp-descent' mode and when inactive the knee and ankle devices functioned at constant default levels. Negative limb work, determined as the integral of the negative mechanical (external) limb power during the braking phase, was compared across speeds and microprocessor conditions. Negative work done by each limb increased with speed (p < 0.001), and on the prosthetic limb it was greater when the microprocessor was active compared to inactive (p = 0.004). There was no change in work done across microprocessor conditions on the intact limb (p = 0.35). Greater involvement of the prosthetic limb when the limb system was active indicates its ramp-descent mode effectively altered the hydraulic resistances at the ankle and knee. Findings highlight participants became more assured using their prosthetic limb to arrest centre-of-mass velocity. Copyright © 2018 Elsevier Ltd. All rights reserved.

  16. A microprocessor-based position control system for a telescope secondary mirror

    NASA Technical Reports Server (NTRS)

    Lorell, K. R.; Barrows, W. F.; Clappier, R. R.; Lee, G. K.

    1983-01-01

    The pointing requirements for the Shuttle IR Telescope Facility (SIRTF), which consists of an 0.85-m cryogenically cooled IR telescope, call for an image stability of 0.25 arcsec. Attention is presently given to a microprocessor-based position control system developed for the control of the SIRTF secondary mirror, employing a special control law (to minimize energy dissipation), a precision capacitive position sensor, and a specially designed power amplifier/actuator combination. The microprocessor generates the command angular position and rate waveforms in order to maintain a 90 percent dwell time/10 percent transition time ratio independently of chop frequency or amplitude. Performance and test results of a prototype system designed for use with a demonstration model of the SIRTF focal plane fine guidance sensor are presented.

  17. Control law synthesis and optimization software for large order aeroservoelastic systems

    NASA Technical Reports Server (NTRS)

    Mukhopadhyay, V.; Pototzky, A.; Noll, Thomas

    1989-01-01

    A flexible aircraft or space structure with active control is typically modeled by a large-order state space system of equations in order to accurately represent the rigid and flexible body modes, unsteady aerodynamic forces, actuator dynamics and gust spectra. The control law of this multi-input/multi-output (MIMO) system is expected to satisfy multiple design requirements on the dynamic loads, responses, actuator deflection and rate limitations, as well as maintain certain stability margins, yet should be simple enough to be implemented on an onboard digital microprocessor. A software package for performing an analog or digital control law synthesis for such a system, using optimal control theory and constrained optimization techniques is described.

  18. Multilevel Summation of Electrostatic Potentials Using Graphics Processing Units*

    PubMed Central

    Hardy, David J.; Stone, John E.; Schulten, Klaus

    2009-01-01

    Physical and engineering practicalities involved in microprocessor design have resulted in flat performance growth for traditional single-core microprocessors. The urgent need for continuing increases in the performance of scientific applications requires the use of many-core processors and accelerators such as graphics processing units (GPUs). This paper discusses GPU acceleration of the multilevel summation method for computing electrostatic potentials and forces for a system of charged atoms, which is a problem of paramount importance in biomolecular modeling applications. We present and test a new GPU algorithm for the long-range part of the potentials that computes a cutoff pair potential between lattice points, essentially convolving a fixed 3-D lattice of “weights” over all sub-cubes of a much larger lattice. The implementation exploits the different memory subsystems provided on the GPU to stream optimally sized data sets through the multiprocessors. We demonstrate for the full multilevel summation calculation speedups of up to 26 using a single GPU and 46 using multiple GPUs, enabling the computation of a high-resolution map of the electrostatic potential for a system of 1.5 million atoms in under 12 seconds. PMID:20161132

  19. RS-600 programmable controller: Solar heating and cooling

    NASA Technical Reports Server (NTRS)

    1978-01-01

    Three identical microprocessor control subsystems were developed which can be used in heating, heating and cooling, and/or hot water systems for single family, multifamily, or commercial applications. The controller incorporates a low cost, highly reliable (all solid state) microprocessor which can be easily reprogrammed.

  20. Formal verification of an avionics microprocessor

    NASA Technical Reports Server (NTRS)

    Srivas, Mandayam, K.; Miller, Steven P.

    1995-01-01

    Formal specification combined with mechanical verification is a promising approach for achieving the extremely high levels of assurance required of safety-critical digital systems. However, many questions remain regarding their use in practice: Can these techniques scale up to industrial systems, where are they likely to be useful, and how should industry go about incorporating them into practice? This report discusses a project undertaken to answer some of these questions, the formal verification of the AAMPS microprocessor. This project consisted of formally specifying in the PVS language a rockwell proprietary microprocessor at both the instruction-set and register-transfer levels and using the PVS theorem prover to show that the microcode correctly implemented the instruction-level specification for a representative subset of instructions. Notable aspects of this project include the use of a formal specification language by practicing hardware and software engineers, the integration of traditional inspections with formal specifications, and the use of a mechanical theorem prover to verify a portion of a commercial, pipelined microprocessor that was not explicitly designed for formal verification.

  1. Design and Development of a Multiprogramming Operating System for Sixteen Bit Microprocessors.

    DTIC Science & Technology

    1981-12-01

    with the technical details of how services are programmed or produced, except perhaps when they fail to meet user requirements. Users are interested in...locations and loading decks. As the expense *and speed of computers increased, executive programs were created to allow several users to sequence...single user operating system as a companion to the 8080 microprocessor. CP/M (Control Program for Microcomputers) was a single user operating system that

  2. Portable control device for networked mobile robots

    DOEpatents

    Feddema, John T.; Byrne, Raymond H.; Bryan, Jon R.; Harrington, John J.; Gladwell, T. Scott

    2002-01-01

    A handheld control device provides a way for controlling one or multiple mobile robotic vehicles by incorporating a handheld computer with a radio board. The device and software use a personal data organizer as the handheld computer with an additional microprocessor and communication device on a radio board for use in controlling one robot or multiple networked robots.

  3. A central microprocessor controlled electrical storage heating system

    NASA Astrophysics Data System (ADS)

    Horstmann, H.

    1980-12-01

    The use of a microprocessor to control the reloading of electrical storage heaters not only during the night, but whenever the electrical grid is cycled down, was tested. The test setup, used to control a total of about 10 MW installed storage heating in 96 dwellings, is described. It is demonstrated that additional consumers can be connected to the system without demand for more power stations.

  4. Concept for a power system controller for large space electrical power systems

    NASA Technical Reports Server (NTRS)

    Lollar, L. F.; Lanier, J. R., Jr.; Graves, J. R.

    1981-01-01

    The development of technology for a fail-operatonal power system controller (PSC) utilizing microprocessor technology for managing the distribution and power processor subsystems of a large multi-kW space electrical power system is discussed. The specific functions which must be performed by the PSC, the best microprocessor available to do the job, and the feasibility, cost savings, and applications of a PSC were determined. A limited function breadboard version of a PSC was developed to demonstrate the concept and potential cost savings.

  5. Application of Microprocessor-Based Equipment in Nuclear Power Plants - Technical Basis for a Qualification Methodology

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Korsah, K.

    This document (1) summarizes the most significant findings of the ''Qualification of Advanced Instrumentation and Control (I&C) Systems'' program initiated by the Nuclear Regulatory Commission (NRC); (2) documents a comparative analysis of U.S. and European qualification standards; and (3) provides recommendations for enhancing regulatory guidance for environmental qualification of microprocessor-based safety-related systems. Safety-related I&C system upgrades of present-day nuclear power plants, as well as I&C systems of Advanced Light-Water Reactors (ALWRs), are expected to make increasing use of microprocessor-based technology. The Nuclear Regulatory Commission (NRC) recognized that the use of such technology may pose environmental qualification challenges different from current,more » analog-based I&C systems. Hence, it initiated the ''Qualification of Advanced Instrumentation and Control Systems'' program. The objectives of this confirmatory research project are to (1) identify any unique environmental-stress-related failure modes posed by digital technologies and their potential impact on the safety systems and (2) develop the technical basis for regulatory guidance using these findings. Previous findings from this study have been documented in several technical reports. This final report in the series documents a comparative analysis of two environmental qualification standards--Institute of Electrical and Electronics Engineers (IEEE) Std 323-1983 and International Electrotechnical Commission (IEC) 60780 (1998)--and provides recommendations for environmental qualification of microprocessor-based systems based on this analysis as well as on the findings documented in the previous reports. The two standards were chosen for this analysis because IEEE 323 is the standard used in the U.S. for the qualification of safety-related equipment in nuclear power plants, and IEC 60780 is its European counterpart. In addition, the IEC document was published in 1998, and should reflect any new qualification concerns, from the European perspective, with regard to the use of microprocessor-based safety systems in power plants.« less

  6. An Intelligent Terminal for Access to a Medical Database

    PubMed Central

    Womble, M. E.; Wilson, S. D.; Keiser, H. N.; Tworek, M. L.

    1978-01-01

    Very powerful data base management systems (DBMS) now exist which allow medical personnel access to patient record data bases. DBMS's make it easy to retrieve either complete or abbreviated records of patients with similar characteristics. In addition, statistics on data base records are immediately accessible. However, the price of this power is a large computer with the inherent problems of access, response time, and reliability. If a general purpose, time-shared computer is used to get this power, the response time to a request can be either rapid or slow, depending upon loading by other users. Furthermore, if the computer is accessed via dial-up telephone lines, there is competition with other users for telephone ports. If either the DBMS or the host machine is replaced, the medical users, who are typically not sophisticated in computer usage, are forced to learn the new system. Microcomputers, because of their low cost and adaptability, lend themselves to a solution of these problems. A microprocessor-based intelligent terminal has been designed and implemented at the USAF School of Aerospace Medicine to provide a transparent interface between the user and his data base. The intelligent terminal system includes multiple microprocessors, floppy disks, a CRT terminal, and a printer. Users interact with the system at the CRT terminal using menu selection (framing). The system translates the menu selection into the query language of the DBMS and handles all actual communication with the DBMS and its host computer, including telephone dialing and sign on procedures, as well as the actual data base query and response. Retrieved information is stored locally for CRT display, hard copy production, and/or permanent retention. Microprocessor-based communication units provide security for sensitive medical data through encryption/decryption algorithms and high reliability error detection transmission schemes. Highly modular software design permits adapation to a different DBMS and/or host computer with only minor localized software changes. Importantly, this portability is completely transparent to system users. Although the terminal system is independent of the host computer and its DBMS, it has been linked to a UNIVAC 1108 computer supporting MRI's SYSTEM 2000 DBMS.

  7. Advances in Strapdown Inertial Systems. Lecture Series Held in Athens, Greece on 14-15 May 1984, in Rome, Italy on 17-18 May 1984 and in Copenhagen, Denmark on 21-22 May 1984

    DTIC Science & Technology

    1984-04-01

    software are required. Ported air cooling is provided in accordan-4 oith WKIM 600 Level 2 and Adequately supports the pow. dissipation (approxiimately 100... software multiplication with simple shifting operations in order to optimize operating speed. Finally, program development software for microprocessors...requiremuents and that the software was exhaustively verified and validated prior to initiation of flight testing will be describ- ed. A special flight

  8. A rocket-borne microprocessor-based experiment for investigation of energetic particles in the D and E regions

    NASA Technical Reports Server (NTRS)

    Braswell, F. M.

    1981-01-01

    An energetic experiment using the Z80 family of microcomputer components is described. Data collected from the experiment allowed fast and efficient postprocessing, yielding both energy-spectrum and pitch-angle distribution of energetic particles in the D and E regions. Advanced microprocessor system architecture and software concepts were used in the design to cope with the large amount of data being processed. This required the Z80 system to operate at over 80% of its total capacity. The microprocessor system was included in the payloads of three rockets launched during the Energy Budget Campaign at ESRANGE, Kiruna, Sweden in November 1980. Based on preliminary examination of the data, the performance of the experiment was satisfactory and good data were obtained on the energy spectrum and pitch-angle distribution of the particles.

  9. A rocket-borne pulse-height analyzer for energetic particle measurements

    NASA Technical Reports Server (NTRS)

    Leung, W.; Smith, L. G.; Voss, H. D.

    1979-01-01

    The pulse-height analyzer basically resembles a time-sharing multiplexing data-acquisition system which acquires analog data (from energetic particle spectrometers) and converts them into digital code. The PHA simultaneously acquires pulse-height information from the analog signals of the four input channels and sequentially multiplexes the digitized data to a microprocessor. The PHA together with the microprocessor form an on-board real-time data-manipulation system. The system processes data obtained during the rocket flight and reduces the amount of data to be sent back to the ground station. Consequently the data-reduction process for the rocket experiments is speeded up. By using a time-sharing technique, the throughput rate of the microprocessor is increased. Moreover, data from several particle spectrometers are manipulated to share one information channel; consequently, the TM capacity is increased.

  10. [Development of an automatic pneumatic tourniquet system that determines pressures in synchrony with systolic blood pressure].

    PubMed

    Liu, Hongyun; Li, Kaiyuan; Zhang, Zhengbo; Guo, Junyan; Wang, Weidong

    2012-11-01

    The correlation coefficients between arterial occlusion pressure and systolic blood pressure, diastolic blood pressure, limb circumference, body mass etc were obtained through healthy volunteer experiments, in which tourniquet were applied on upper/lower extremities. The prediction equations were derived from the data of experiments by multiple regression analysis. Based on the microprocessor C8051F340, a new pneumatic tourniquet system that can determine tourniquet pressure in synchrony with systolic blood pressure was developed and verified the function and stability of designed system. Results showed that the pneumatic tourniquet which automatically adjusts occlusion pressure in accordance with systolic blood pressure could stop the flow of blood to get a bloodless field.

  11. Development of a patch type embedded cardiac function monitoring system using dual microprocessor for arrhythmia detection in heart disease patient.

    PubMed

    Jang, Yongwon; Noh, Hyung Wook; Lee, I B; Jung, Ji-Wook; Song, Yoonseon; Lee, Sooyeul; Kim, Seunghwan

    2012-01-01

    A patch type embedded cardiac function monitoring system was developed to detect arrhythmias such as PVC (Premature Ventricular Contraction), pause, ventricular fibrillation, and tachy/bradycardia. The overall system is composed of a main module including a dual processor and a Bluetooth telecommunication module. The dual microprocessor strategy minimizes power consumption and size, and guarantees the resources of embedded software programs. The developed software was verified with standard DB, and showed good performance.

  12. Microprocessor control system for 200-kilowatt Mod-OA wind turbines

    NASA Technical Reports Server (NTRS)

    Nyland, T. W.; Birchenough, A. G.

    1982-01-01

    The microprocessor system and program used to control the operation of the 200-kW Mod-OA wind turbines is described. The system is programmed to begin startup and shutdown sequences automatically and to control yaw motion. Rotor speed and power output are controlled with integral and proportional control of the blade pitch angle. Included in the report are a description of the hardware and a discussion of the software programming technique. A listing of the PL/M software program is given.

  13. Dynamic characterization and microprocessor control of the NASA/UVA proof mass actuator

    NASA Technical Reports Server (NTRS)

    Zimmerman, D. C.; Inman, D. J.; Horner, G. C.

    1984-01-01

    The self-contained electromagnetic-reaction-type force-actuator system developed by NASA/UVA for the verification of spacecraft-structure vibration-control laws is characterized and demonstrated. The device is controlled by a dedicated microprocessor and has dynamic characteristics determined by Fourier analysis. Test data on a cantilevered beam are shown.

  14. Microprocessor-Based Neural-Pulse-Wave Analyzer

    NASA Technical Reports Server (NTRS)

    Kojima, G. K.; Bracchi, F.

    1983-01-01

    Microprocessor-based system analyzes amplitudes and rise times of neural waveforms. Displaying histograms of measured parameters helps researchers determine how many nerves contribute to signal and specify waveform characteristics of each. Results are improved noise rejection, full or partial separation of overlapping peaks, and isolation and identification of related peaks in different histograms. 2

  15. Microprocessor Design Using Hardware Description Language

    ERIC Educational Resources Information Center

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  16. Robust Duplication with Comparison Methods in Microcontrollers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.

    Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

  17. Robust Duplication with Comparison Methods in Microcontrollers

    DOE PAGES

    Quinn, Heather Marie; Baker, Zachary Kent; Fairbanks, Thomas D.; ...

    2016-01-01

    Commercial microprocessors could be useful computational platforms in space systems, as long as the risk is bound. Many spacecraft are computationally constrained because all of the computation is done on a single radiation-hardened microprocessor. It is possible that a commercial microprocessor could be used for configuration, monitoring and background tasks that are not mission critical. Most commercial microprocessors are affected by radiation, including single-event effects (SEEs) that could be destructive to the component or corrupt the data. Part screening can help designers avoid components with destructive failure modes, and mitigation can suppress data corruption. We have been experimenting with amore » method for masking radiation-induced faults through the software executing on the microprocessor. While triple-modular redundancy (TMR) techniques are very effective at masking faults in software, the increased amount of execution time to complete the computation is not desirable. Here in this article we present a technique for combining duplication with compare (DWC) with TMR that decreases observable errors by as much as 145 times with only a 2.35 time decrease in performance.« less

  18. Human supervision and microprocessor control of an optical tracking system

    NASA Technical Reports Server (NTRS)

    Bigley, W. J.; Vandenberg, J. D.

    1981-01-01

    Gunners using small calibre anti-aircraft systems have not been able to track high-speed air targets effectively. Substantial improvement in the accuracy of surface fire against attacking aircraft has been realized through the design of a director-type weapon control system. This system concept frees the gunner to exercise a supervisory/monitoring role while the computer takes over continuous target tracking. This change capitalizes on a key consideration of human factors engineering while increasing system accuracy. The advanced system design, which uses distributed microprocessor control, is discussed at the block diagram level and is contrasted with the previous implementation.

  19. Low-level processing for real-time image analysis

    NASA Technical Reports Server (NTRS)

    Eskenazi, R.; Wilf, J. M.

    1979-01-01

    A system that detects object outlines in television images in real time is described. A high-speed pipeline processor transforms the raw image into an edge map and a microprocessor, which is integrated into the system, clusters the edges, and represents them as chain codes. Image statistics, useful for higher level tasks such as pattern recognition, are computed by the microprocessor. Peak intensity and peak gradient values are extracted within a programmable window and are used for iris and focus control. The algorithms implemented in hardware and the pipeline processor architecture are described. The strategy for partitioning functions in the pipeline was chosen to make the implementation modular. The microprocessor interface allows flexible and adaptive control of the feature extraction process. The software algorithms for clustering edge segments, creating chain codes, and computing image statistics are also discussed. A strategy for real time image analysis that uses this system is given.

  20. Technology-Based Programs to Promote Walking Fluency or Improve Foot-Ground Contact during Walking: Two Case Studies of Adults with Multiple Disabilities

    ERIC Educational Resources Information Center

    Lancioni, Giulio E.; Singh, Nirbhay N.; O'Reilly, Mark F.; Sigafoos, Jeff; La Martire, Maria L.; Oliva, Doretta; Groeneweg, Jop

    2012-01-01

    These two case studies assessed technology-based programs for promoting walking fluency and improving foot-ground contact during walking with a man and a woman with multiple disabilities, respectively. The man showed breaks during walking and the woman presented with toe walking. The technology used in the studies included a microprocessor with…

  1. Promoting Mouth-Drying Responses to Reduce Drooling Effects by Persons with Intellectual and Multiple Disabilities: A Study of Two Cases

    ERIC Educational Resources Information Center

    Lancioni, Giulio E.; Singh, Nirbhay N.; O'Reilly, Mark F.; Sigafoos, Jeff; Oliva, Doretta; Smaldone, Angela; La Martire, Maria L.; Pichierri, Sabrina; Groeneweg, Jop

    2011-01-01

    This study assessed the use of microswitch technology to promote mouth-drying responses and thereby reduce the effects of drooling by two adults with severe intellectual and multiple disabilities. Mouth-drying responses were performed via a special napkin that contained pressure sensors, a microprocessor and an MP3 to monitor the responses and…

  2. Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

    NASA Technical Reports Server (NTRS)

    1977-01-01

    A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

  3. Programmable calculator as a data system controller

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Barth, A.W.; Strasburg, A.C.

    Digital data techniques are in common use for analysis of analog information obtained in various tests, and systems have been developed which use a minicomputer as the central controller and data processor. Now, microprocessors allow new design approaches at considerably less cost. This report outlines an approach to system design based on the use of a programmable calculator as the data system controller. A block diagram of the calculator-controlled data system is shown. It was found that the programmable calculator provides a viable alternative to minicomputers or microprocessors for the development laboratory requiring digital data processing. 3 figures. (RWR)

  4. Microprocessor-based cardiopulmonary monitoring system

    NASA Technical Reports Server (NTRS)

    1978-01-01

    The system uses a dedicated microprocessor for transducer control and data acquisition and analysis. No data will be stored in this system, but the data will be transmitted to the onboard data system. The data system will require approximately 12 inches of rack space and will consume only 100 watts of power. An experiment specific control panel, through a series of lighted buttons, will guide the operator through the test series providing a smaller margin of error. The experimental validity of the system was verified, and the reproducibility of data and reliability of the system checked. In addition, ease of training, ease of operator interaction, and crew acceptance were evaluated in actual flight conditions.

  5. [The design of a cardiac monitoring and analysing system with low power consumption].

    PubMed

    Chen, Zhen-cheng; Ni, Li-li; Zhu, Yan-gao; Wang, Hong-yan; Ma, Yan

    2002-07-01

    The paper deals with a portable analyzing monitor system with liquid crystal display (LCD), which is low in power consumption and suitable for China's specific conditions. Apart from the development of the overall scheme of the system, the paper introduces the design of the hardware and the software. The 80196 single chip microcomputer is used as the central microprocessor to process and real-time electrocardiac signal data. The system have the following functions: five types of arrhythmia analysis, alarm, freeze, and record of automatic paperfeeding. The portable system can be operated by alternate-current (AC) or direct-current (DC). Its hardware circuit is simplified and its software structure is optimized. Multiple low power consumption and LCD unit are adopted in its modular designs.

  6. Application of Fault-Tolerant Computing For Spacecraft Using Commercial-Off-The-Shelf Microprocessors

    DTIC Science & Technology

    2000-06-01

    real - time operating system and design of a human-computer interface (HCI) for a triple modular redundant (TMR) fault-tolerant microprocessor for use in space-based applications. Once disadvantage of using COTS hardware components is their susceptibility to the radiation effects present in the space environment. and specifically, radiation-induced single-event upsets (SEUs). In the event of an SEU, a fault-tolerant system can mitigate the effects of the upset and continue to process from the last known correct system state. The TMR basic hardware

  7. Feasibility study of a microprocessor based oculometer system

    NASA Technical Reports Server (NTRS)

    Varanasi, M. R.

    1981-01-01

    The elimination of redundancy in data to maximize processing speed and minimize storage requirements were objectives in a feasibility study of a microprocessor based oculometer system that would be portable in size and flexible in use. The appropriate architectural design of the signal processor, improved optics, and the reduction of size, weight, and power to the system were investigated. A flow chart is presented showing the strategy of the design. The simulation for developing microroutines for the high speed algorithmic processor subsystem is discussed as well as the Karhunen-Loeve transform technique for data compression.

  8. Microprocessor implementation of an FFT for ionospheric VLF observations

    NASA Technical Reports Server (NTRS)

    Elvidge, J.; Kintner, P.; Holzworth, R.

    1984-01-01

    A fast Fourier transform algorithm is implemented on a CMOS microprocessor for application to very low-frequency electric fields (less than 10 kHz) sensed on high-altitude scientific balloons. Two FFT's are calculated simultaneously by associating them with conjugate symmetric and conjugate antisymmetric results. One goal of the system was to detect spectral signatures associated with fast time variations present in natural signals such as whistlers and chorus. Although a full evaluation of the system was not possible for operational reasons, a measure of the system's success has been defined and evaluated.

  9. Flexible Architecture for FPGAs in Embedded Systems

    NASA Technical Reports Server (NTRS)

    Clark, Duane I.; Lim, Chester N.

    2012-01-01

    Commonly, field-programmable gate arrays (FPGAs) being developed in cPCI embedded systems include the bus interface in the FPGA. This complicates the development because the interface is complicated and requires a lot of development time and FPGA resources. In addition, flight qualification requires a substantial amount of time be devoted to just this interface. Another complication of putting the cPCI interface into the FPGA being developed is that configuration information loaded into the device by the cPCI microprocessor is lost when a new bit file is loaded, requiring cumbersome operations to return the system to an operational state. Finally, SRAM-based FPGAs are typically programmed via specialized cables and software, with programming files being loaded either directly into the FPGA, or into PROM devices. This can be cumbersome when doing FPGA development in an embedded environment, and does not have an easy path to flight. Currently, FPGAs used in space applications are usually programmed via multiple space-qualified PROM devices that are physically large and require extra circuitry (typically including a separate one-time programmable FPGA) to enable them to be used for this application. This technology adds a cPCI interface device with a simple, flexible, high-performance backend interface supporting multiple backend FPGAs. It includes a mechanism for programming the FPGAs directly via the microprocessor in the embedded system, eliminating specialized hardware, software, and PROM devices and their associated circuitry. It has a direct path to flight, and no extra hardware and minimal software are required to support reprogramming in flight. The device added is currently a small FPGA, but an advantage of this technology is that the design of the device does not change, regardless of the application in which it is being used. This means that it needs to be qualified for flight only once, and is suitable for one-time programmable devices or an application specific integrated circuit (ASIC). An application programming interface (API) further reduces the development time needed to use the interface device in a system.

  10. A Signal Processing Algorithm Based on Multiple Microprocessors for an Underwater Acoustic Imaging System.

    DTIC Science & Technology

    1980-12-01

    identified by the 49 4 UJ 4 4JJ 4A ww U- *i 0 tao Cv4- 50-0 trace) indicated that the bus usage was 7.9% of the loop’s execution time. The number of...1S Wc 0 4 wW 1 C, .- L 3 WQ - is = IViu4 W" L - &’aoI c O: W " Cn -- I C I0 " L =l- *. at C mW C 4 isq - is Ca W WCC .. .- C.- a .of C-( i I X0"e , Lw

  11. A microprocessor controlled pressure scanning system

    NASA Technical Reports Server (NTRS)

    Anderson, R. C.

    1976-01-01

    A microprocessor-based controller and data logger for pressure scanning systems is described. The microcomputer positions and manages data from as many as four 48-port electro-mechanical pressure scanners. The maximum scanning rate is 80 pressure measurements per second (20 ports per second on each of four scanners). The system features on-line calibration, position-directed data storage, and once-per-scan display in engineering units of data from a selected port. The system is designed to be interfaced to a facility computer through a shared memory. System hardware and software are described. Factors affecting measurement error in this type of system are also discussed.

  12. Stand-alone development system using a KIM-1 microcomputer module

    NASA Technical Reports Server (NTRS)

    Nickum, J. D.

    1978-01-01

    A small microprocessor-based system designed to: contain all or most of the interface hardware, designed to be easy to access and modify the hardware, to be capable of being strapped to the seat of a small general aviation aircraft, and to be independent of the aircraft power system is described. The system is used to develop a low cost Loran C sensor processor, but is designed such that the Loran interface boards may be removed and other hardware interfaces inserted into the same connectors. This flexibility is achieved through memory-mapping techniques into the microprocessor.

  13. NEAT1 Scaffolds RNA Binding Proteins and the Microprocessor to Globally Enhance Pri-miRNA Processing

    PubMed Central

    Jiang, Li; Shao, Changwei; Wu, Qi-Jia; Chen, Geng; Zhou, Jie; Yang, Bo; Li, Hairi; Gou, Lan-Tao; Zhang, Yi; Wang, Yangming; Yeo, Gene W.; Zhou, Yu; Fu, Xiang-Dong

    2018-01-01

    Summary MicroRNA biogenesis is known to be modulated by a variety of RNA binding proteins (RBPs), but in most cases, individual RBPs appear to influence the processing of a small subset of target miRNAs. We herein report that the RNA binding NONO/PSF heterodimer binds a large number of expressed pri-miRNAs in HeLa cells to globally enhance pri-miRNA processing by the Drosha/DGCR8 Microprocessor. Because NONO/PSF are key components of paraspeckles organized by the lncRNA NEAT1, we further demonstrate that NEAT1 also has a profound effect on global pri-miRNA processing. Mechanistic dissection reveals that NEAT1 broadly interacts with NONO/PSF as well as many other RBPs, and that multiple RNA segments in NEAT1, including a “pseudo pri-miRNA” near its 3′ end, help attract the Microprocessor. These findings suggest a bird nest model for a large non-coding RNA to orchestrate efficient processing of almost an entire class of small non-coding RNAs in the nucleus. PMID:28846091

  14. NEAT1 scaffolds RNA-binding proteins and the Microprocessor to globally enhance pri-miRNA processing.

    PubMed

    Jiang, Li; Shao, Changwei; Wu, Qi-Jia; Chen, Geng; Zhou, Jie; Yang, Bo; Li, Hairi; Gou, Lan-Tao; Zhang, Yi; Wang, Yangming; Yeo, Gene W; Zhou, Yu; Fu, Xiang-Dong

    2017-10-01

    MicroRNA (miRNA) biogenesis is known to be modulated by a variety of RNA-binding proteins (RBPs), but in most cases, individual RBPs appear to influence the processing of a small subset of target miRNAs. Here, we report that the RNA-binding NONO-PSF heterodimer binds a large number of expressed pri-miRNAs in HeLa cells to globally enhance pri-miRNA processing by the Drosha-DGCR8 Microprocessor. NONO and PSF are key components of paraspeckles organized by the long noncoding RNA (lncRNA) NEAT1. We further demonstrate that NEAT1 also has a profound effect on global pri-miRNA processing. Mechanistic dissection reveals that NEAT1 broadly interacts with the NONO-PSF heterodimer as well as many other RBPs and that multiple RNA segments in NEAT1, including a 'pseudo pri-miRNA' near its 3' end, help attract the Microprocessor. These findings suggest a 'bird nest' model in which an lncRNA orchestrates efficient processing of potentially an entire class of small noncoding RNAs in the nucleus.

  15. Analysis of inadvertent microprocessor lag time on eddy covariance results

    Treesearch

    Karl Zeller; Gary Zimmerman; Ted Hehn; Evgeny Donev; Diane Denny; Jeff Welker

    2001-01-01

    Researchers using the eddy covariance approach to measuring trace gas fluxes are often hoping to measure carbon dioxide and energy fluxes for ecosystem intercomparisons. This paper demonstrates a systematic microprocessor- caused lag of 20.1 to 20.2 s in a commercial sonic anemometer-analog-to-digital datapacker system operated at 10 Hz. The result of the inadvertent...

  16. European Science Notes Information Bulletin Reports on Current European and Middle Eastern Science

    DTIC Science & Technology

    1992-01-01

    evclopment in the Abbey-Polymer Processing and Properties ................... 524 J, Magill Corrosion and Protection Centre at the University of...34* Software Engineering and microprocessors and communication chips. The Information Processing Systems recently announced T9000 microprocessor will...computational fluid dynamics, struc- In addition to general and special-purpose tural mechanics, partial differential equations, processing , Europe has a

  17. Microfluidic Pneumatic Logic Circuits and Digital Pneumatic Microprocessors for Integrated Microfluidic Systems

    PubMed Central

    Rhee, Minsoung

    2010-01-01

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprecessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner. PMID:19823730

  18. Regulation of Plant Microprocessor Function in Shaping microRNA Landscape.

    PubMed

    Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

    2018-01-01

    MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem-loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed.

  19. Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis

    PubMed Central

    Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

    2016-01-01

    Background: There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. Objectives: The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Study design: Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Methods: Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. Results: The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation (p = .001), paretic limb health (p = .04), sounds (p = .02), and well-being (p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. Conclusion: The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety. PMID:27151648

  20. Regulation of Plant Microprocessor Function in Shaping microRNA Landscape

    PubMed Central

    Dolata, Jakub; Taube, Michał; Bajczyk, Mateusz; Jarmolowski, Artur; Szweykowska-Kulinska, Zofia; Bielewicz, Dawid

    2018-01-01

    MicroRNAs are small molecules (∼21 nucleotides long) that are key regulators of gene expression. They originate from long stem–loop RNAs as a product of cleavage by a protein complex called Microprocessor. The core components of the plant Microprocessor are the RNase type III enzyme Dicer-Like 1 (DCL1), the zinc finger protein Serrate (SE), and the double-stranded RNA binding protein Hyponastic Leaves 1 (HYL1). Microprocessor assembly and its processing of microRNA precursors have been reported to occur in discrete nuclear bodies called Dicing bodies. The accessibility of and modifications to Microprocessor components affect microRNA levels and may have dramatic consequences in plant development. Currently, numerous lines of evidence indicate that plant Microprocessor activity is tightly regulated. The cellular localization of HYL1 is dependent on a specific KETCH1 importin, and the E3 ubiquitin ligase COP1 indirectly protects HYL1 from degradation in a light-dependent manner. Furthermore, proper localization of HYL1 in Dicing bodies is regulated by MOS2. On the other hand, the Dicing body localization of DCL1 is regulated by NOT2b, which also interacts with SE in the nucleus. Post-translational modifications are substantial factors that contribute to protein functional diversity and provide a fine-tuning system for the regulation of protein activity. The phosphorylation status of HYL1 is crucial for its activity/stability and is a result of the interplay between kinases (MPK3 and SnRK2) and phosphatases (CPL1 and PP4). Additionally, MPK3 and SnRK2 are known to phosphorylate SE. Several other proteins (e.g., TGH, CDF2, SIC, and RCF3) that interact with Microprocessor have been found to influence its RNA-binding and processing activities. In this minireview, recent findings on the various modes of Microprocessor activity regulation are discussed. PMID:29922322

  1. Safety and walking ability of KAFO users with the C-Brace® Orthotronic Mobility System, a new microprocessor stance and swing control orthosis.

    PubMed

    Pröbsting, Eva; Kannenberg, Andreas; Zacharias, Britta

    2017-02-01

    There are clear indications for benefits of stance control orthoses compared to locked knee ankle foot orthoses. However, stance control orthoses still have limited function compared with a sound human leg. The aim of this study was to evaluate the potential benefits of a microprocessor stance and swing control orthosis compared to stance control orthoses and locked knee ankle foot orthoses in activities of daily living. Survey of lower limb orthosis users before and after fitting of a microprocessor stance and swing control orthosis. Thirteen patients with various lower limb pareses completed a baseline survey for their current orthotic device (locked knee ankle foot orthosis or stance control orthosis) and a follow-up for the microprocessor stance and swing control orthosis with the Orthosis Evaluation Questionnaire, a new self-reported outcome measure devised by modifying the Prosthesis Evaluation Questionnaire for use in lower limb orthotics and the Activities of Daily Living Questionnaire. The Orthosis Evaluation Questionnaire results demonstrated significant improvements by microprocessor stance and swing control orthosis use in the total score and the domains of ambulation ( p = .001), paretic limb health ( p = .04), sounds ( p = .02), and well-being ( p = .01). Activities of Daily Living Questionnaire results showed significant improvements with the microprocessor stance and swing control orthosis with regard to perceived safety and difficulty of activities of daily living. The microprocessor stance and swing control orthosis may facilitate an easier, more physiological, and safer execution of many activities of daily living compared to traditional leg orthosis technologies. Clinical relevance This study compared patient-reported outcomes of a microprocessor stance and swing control orthosis (C-Brace) to those with traditional knee ankle foot orthosis and stance control orthosis devices. The C-Brace offers new functions including controlled knee flexion during weight bearing and dynamic swing control, resulting in significant improvements in perceived orthotic mobility and safety.

  2. Single-chip microprocessor that communicates directly using light.

    PubMed

    Sun, Chen; Wade, Mark T; Lee, Yunsup; Orcutt, Jason S; Alloatti, Luca; Georgas, Michael S; Waterman, Andrew S; Shainline, Jeffrey M; Avizienis, Rimas R; Lin, Sen; Moss, Benjamin R; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H; Cook, Henry M; Ou, Albert J; Leu, Jonathan C; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J; Popović, Miloš A; Stojanović, Vladimir M

    2015-12-24

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  3. The biological microprocessor, or how to build a computer with biological parts

    PubMed Central

    Moe-Behrens, Gerd HG

    2013-01-01

    Systemics, a revolutionary paradigm shift in scientific thinking, with applications in systems biology, and synthetic biology, have led to the idea of using silicon computers and their engineering principles as a blueprint for the engineering of a similar machine made from biological parts. Here we describe these building blocks and how they can be assembled to a general purpose computer system, a biological microprocessor. Such a system consists of biological parts building an input / output device, an arithmetic logic unit, a control unit, memory, and wires (busses) to interconnect these components. A biocomputer can be used to monitor and control a biological system. PMID:24688733

  4. Microprocessor-controlled, wide-range streak camera

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Amy E. Lewis, Craig Hollabaugh

    Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storagemore » using flash-based storage media. The camera’s user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.« less

  5. Microprocessor-controlled wide-range streak camera

    NASA Astrophysics Data System (ADS)

    Lewis, Amy E.; Hollabaugh, Craig

    2006-08-01

    Bechtel Nevada/NSTec recently announced deployment of their fifth generation streak camera. This camera incorporates many advanced features beyond those currently available for streak cameras. The arc-resistant driver includes a trigger lockout mechanism, actively monitors input trigger levels, and incorporates a high-voltage fault interrupter for user safety and tube protection. The camera is completely modular and may deflect over a variable full-sweep time of 15 nanoseconds to 500 microseconds. The camera design is compatible with both large- and small-format commercial tubes from several vendors. The embedded microprocessor offers Ethernet connectivity, and XML [extensible markup language]-based configuration management with non-volatile parameter storage using flash-based storage media. The camera's user interface is platform-independent (Microsoft Windows, Unix, Linux, Macintosh OSX) and is accessible using an AJAX [asynchronous Javascript and XML]-equipped modem browser, such as Internet Explorer 6, Firefox, or Safari. User interface operation requires no installation of client software or browser plug-in technology. Automation software can also access the camera configuration and control using HTTP [hypertext transfer protocol]. The software architecture supports multiple-simultaneous clients, multiple cameras, and multiple module access with a standard browser. The entire user interface can be customized.

  6. Proceedings: DISE Workshop on Microprocessors and Education (Fort Collins, Colorado, August 16-18, 1976).

    ERIC Educational Resources Information Center

    Pittsburgh Univ., PA. Dept. of Electrical Engineering.

    Papers presented during four sessions of a workshop, which addressed the role of microprocessors in education, are included in this publication. The issues covered involved seven areas: (1) views of the microelectronics industry; (2) microprocessor architecture; (3) microprocessor chip design; (4) microprocessor software; (5) the impact of…

  7. A microprocessor-based cardiotachometer

    NASA Technical Reports Server (NTRS)

    Donaldson, J. A.; Crosier, W. G.

    1979-01-01

    The development of a highly accurate and reliable cardiotachometer for measuring the heart rate of test subjects is discussed. It measures heart rate over the range of 30 to 250 beats/minute and gives instantaneous (beat to beat) updates on the system output so that occasional noise artifacts or ectopic beats could be more easily identified except that occasional missed beats caused by switching ECG leads should not cause a change in the output. The cardiotachometer uses an improved analog filter and R-wave detector and an Intel 8080A microprocessor to handle all of the logic and arithmetic necessary. By using the microprocessor, future hardware modifications could easily be made if functional changes were needed.

  8. A programmable controller based on CAN field bus embedded microprocessor and FPGA

    NASA Astrophysics Data System (ADS)

    Cai, Qizhong; Guo, Yifeng; Chen, Wenhei; Wang, Mingtao

    2008-10-01

    One kind of new programmable controller(PLC) is introduced in this paper. The advanced embedded microprocessor and Field-Programmable Gate Array (FPGA) device are applied in the PLC system. The PLC system structure was presented in this paper. It includes 32 bits Advanced RISC Machines (ARM) embedded microprocessor as control core, FPGA as control arithmetic coprocessor and CAN bus as data communication criteria protocol connected the host controller and its various extension modules. It is detailed given that the circuits and working principle, IiO interface circuit between ARM and FPGA and interface circuit between ARM and FPGA coprocessor. Furthermore the interface circuit diagrams between various modules are written. In addition, it is introduced that ladder chart program how to control the transfer info of control arithmetic part in FPGA coprocessor. The PLC, through nearly two months of operation to meet the design of the basic requirements.

  9. Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

    NASA Technical Reports Server (NTRS)

    Liu, Yuan-Kwei

    1991-01-01

    The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/386 DX memory hierachy appears to be the most beneficial change to the current DMS design at this time.

  10. Analysis of the Intel 386 and i486 microprocessors for the Space Station Freedom Data Management System

    NASA Technical Reports Server (NTRS)

    Liu, Yuan-Kwei

    1991-01-01

    The feasibility is analyzed of upgrading the Intel 386 microprocessor, which has been proposed as the baseline processor for the Space Station Freedom (SSF) Data Management System (DMS), to the more advanced i486 microprocessors. The items compared between the two processors include the instruction set architecture, power consumption, the MIL-STD-883C Class S (Space) qualification schedule, and performance. The advantages of the i486 over the 386 are (1) lower power consumption; and (2) higher floating point performance. The i486 on-chip cache does not have parity check or error detection and correction circuitry. The i486 with on-chip cache disabled, however, has lower integer performance than the 386 without cache, which is the current DMS design choice. Adding cache to the 386/387 DX memory hierarchy appears to be the most beneficial change to the current DMS design at this time.

  11. Horizontal Directional Drilling-Length Detection Technology While Drilling Based on Bi-Electro-Magnetic Sensing.

    PubMed

    Wang, Yudan; Wen, Guojun; Chen, Han

    2017-04-27

    The drilling length is an important parameter in the process of horizontal directional drilling (HDD) exploration and recovery, but there has been a lack of accurate, automatically obtained statistics regarding this parameter. Herein, a technique for real-time HDD length detection and a management system based on the electromagnetic detection method with a microprocessor and two magnetoresistive sensors employing the software LabVIEW are proposed. The basic principle is to detect the change in the magnetic-field strength near a current coil while the drill stem and drill-stem joint successively pass through the current coil forward or backward. The detection system consists of a hardware subsystem and a software subsystem. The hardware subsystem employs a single-chip microprocessor as the main controller. A current coil is installed in front of the clamping unit, and two magneto resistive sensors are installed on the sides of the coil symmetrically and perpendicular to the direction of movement of the drill pipe. Their responses are used to judge whether the drill-stem joint is passing through the clamping unit; then, the order of their responses is used to judge the movement direction. The software subsystem is composed of a visual software running on the host computer and a software running in the slave microprocessor. The host-computer software processes, displays, and saves the drilling-length data, whereas the slave microprocessor software operates the hardware system. A combined test demonstrated the feasibility of the entire drilling-length detection system.

  12. Horizontal Directional Drilling-Length Detection Technology While Drilling Based on Bi-Electro-Magnetic Sensing

    PubMed Central

    Wang, Yudan; Wen, Guojun; Chen, Han

    2017-01-01

    The drilling length is an important parameter in the process of horizontal directional drilling (HDD) exploration and recovery, but there has been a lack of accurate, automatically obtained statistics regarding this parameter. Herein, a technique for real-time HDD length detection and a management system based on the electromagnetic detection method with a microprocessor and two magnetoresistive sensors employing the software LabVIEW are proposed. The basic principle is to detect the change in the magnetic-field strength near a current coil while the drill stem and drill-stem joint successively pass through the current coil forward or backward. The detection system consists of a hardware subsystem and a software subsystem. The hardware subsystem employs a single-chip microprocessor as the main controller. A current coil is installed in front of the clamping unit, and two magneto resistive sensors are installed on the sides of the coil symmetrically and perpendicular to the direction of movement of the drill pipe. Their responses are used to judge whether the drill-stem joint is passing through the clamping unit; then, the order of their responses is used to judge the movement direction. The software subsystem is composed of a visual software running on the host computer and a software running in the slave microprocessor. The host-computer software processes, displays, and saves the drilling-length data, whereas the slave microprocessor software operates the hardware system. A combined test demonstrated the feasibility of the entire drilling-length detection system. PMID:28448445

  13. A Microprocessor-Controlled Data Acquisition System for the Federal Scientific Model UA-500-1 Ubiquitous Spectrum Analyzer

    DTIC Science & Technology

    1976-09-01

    Model AN/ UGC -59A teletype and paper-tape punch console. This unit is connected with the Intellec 8 computer and punching operations are controlled by...order to use this program, the microprocessor would have to be one of the many types on the market that make use of the INTEL 8008-1 CPD chip. The use

  14. Eight microprocessor-based instrument data systems in the Galileo Orbiter spacecraft

    NASA Technical Reports Server (NTRS)

    Barry, R. C.

    1980-01-01

    Instrument data systems consist of a microprocessor, 3K bytes of Read Only Memory and 3K bytes of Random Access Memory. It interfaces with the spacecraft data bus through an isolated user interface with a direct memory access bus adaptor, and/or parallel data from instrument devices such as registers, buffers, analog to digital converters, multiplexers, and solid state sensors. These data systems support the spacecraft hardware and software communication protocol, decode and process instrument commands, generate continuous instrument operating modes, control the instrument mechanisms, acquire, process, format, and output instrument science data.

  15. Automated Liquid-Level Control of a Nutrient Reservoir for a Hydroponic System

    NASA Technical Reports Server (NTRS)

    Smith, Boris; Asumadu, Johnson A.; Dogan, Numan S.

    1997-01-01

    A microprocessor-based system for control of the liquid level of a nutrient reservoir for a plant hydroponic growing system has been developed. The system uses an ultrasonic transducer to sense the liquid level or height. A National Instruments' Multifunction Analog and Digital Input/Output PC Kit includes NI-DAQ DOS/Windows driver software for an IBM 486 personal computer. A Labview Full Development system for Windows is the graphical programming system being used. The system allows liquid level control to within 0.1 cm for all levels tried between 8 and 36 cm in the hydroponic system application. The detailed algorithms have been developed and a fully automated microprocessor based nutrient replenishment system has been described for this hydroponic system.

  16. Rapidly quantifying the relative distention of a human bladder

    NASA Technical Reports Server (NTRS)

    Companion, John A. (Inventor); Heyman, Joseph S. (Inventor); Mineo, Beth A. (Inventor); Cavalier, Albert R. (Inventor); Blalock, Travis N. (Inventor)

    1991-01-01

    A device and method was developed to rapidly quantify the relative distention of the bladder of a human subject. An ultrasonic transducer is positioned on the human subject near the bladder. A microprocessor controlled pulser excites the transducer by sending an acoustic wave into the human subject. This wave interacts with the bladder walls and is reflected back to the ultrasonic transducer where it is received, amplified, and processed by the receiver. The resulting signal is digitized by an analog to digital converter, controlled by the microprocessor again, and is stored in data memory. The software in the microprocessor determines the relative distention of the bladder as a function of the propagated ultrasonic energy. Based on programmed scientific measurements and the human subject's past history as contained in program memory, the microprocessor sends out a signal to turn on any or all of the available alarms. The alarm system includes and audible alarm, the visible alarm, the tactile alarm, and the remote wireless alarm.

  17. Single-chip microprocessor that communicates directly using light

    NASA Astrophysics Data System (ADS)

    Sun, Chen; Wade, Mark T.; Lee, Yunsup; Orcutt, Jason S.; Alloatti, Luca; Georgas, Michael S.; Waterman, Andrew S.; Shainline, Jeffrey M.; Avizienis, Rimas R.; Lin, Sen; Moss, Benjamin R.; Kumar, Rajesh; Pavanello, Fabio; Atabaki, Amir H.; Cook, Henry M.; Ou, Albert J.; Leu, Jonathan C.; Chen, Yu-Hsin; Asanović, Krste; Ram, Rajeev J.; Popović, Miloš A.; Stojanović, Vladimir M.

    2015-12-01

    Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems—from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices8. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a ‘zero-change’ approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

  18. Flight Experiment Demonstration System (FEDS) functional description and interface document

    NASA Technical Reports Server (NTRS)

    Belcher, R. C.; Shank, D. E.

    1984-01-01

    This document presents a functional description of the Flight Experiment Demonstration System (FEDS) and of interfaces between FEDS and external hardware and software. FEDS is a modification of the Automated Orbit Determination System (AODS). FEDS has been developed to support a ground demonstration of microprocessor-based onboard orbit determination. This document provides an overview of the structure and logic of FEDS and details the various operational procedures to build and execute FEDS. It also documents a microprocessor interface between FEDS and a TDRSS user transponder and describes a software simulator of the interface used in the development and system testing of FEDS.

  19. Advanced Transport Operating System (ATOPS) color displays software description microprocessor system

    NASA Technical Reports Server (NTRS)

    Slominski, Christopher J.; Plyler, Valerie E.; Dickson, Richard W.

    1992-01-01

    This document describes the software created for the Sperry Microprocessor Color Display System used for the Advanced Transport Operating Systems (ATOPS) project on the Transport Systems Research Vehicle (TSRV). The software delivery known as the 'baseline display system', is the one described in this document. Throughout this publication, module descriptions are presented in a standardized format which contains module purpose, calling sequence, detailed description, and global references. The global reference section includes procedures and common variables referenced by a particular module. The system described supports the Research Flight Deck (RFD) of the TSRV. The RFD contains eight cathode ray tubes (CRTs) which depict a Primary Flight Display, Navigation Display, System Warning Display, Takeoff Performance Monitoring System Display, and Engine Display.

  20. Design of Plant Eco-physiology Monitoring System Based on Embedded Technology

    NASA Astrophysics Data System (ADS)

    Li, Yunbing; Wang, Cheng; Qiao, Xiaojun; Liu, Yanfei; Zhang, Xinlu

    A real time system has been developed to collect plant's growth information comprehensively. Plant eco-physiological signals can be collected and analyzed effectively. The system adopted embedded technology: wireless sensors network collect the eco-physiological information. Touch screen and ARM microprocessor make the system work independently without PC. The system is versatile and all parameters can be set by the touch screen. Sensors' intelligent compensation can be realized in this system. Information can be displayed by either graphically or in table mode. The ARM microprocessor provides the interface to connect with the internet, so the system support remote monitoring and controlling. The system has advantages of friendly interface, flexible construction and extension. It's a good tool for plant's management.

  1. Development of a fault-tolerant microprocessor based computer system for space flight

    NASA Technical Reports Server (NTRS)

    Montgomery, V. T.

    1981-01-01

    A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.

  2. Multiprocessor shared-memory information exchange

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Santoline, L.L.; Bowers, M.D.; Crew, A.W.

    1989-02-01

    In distributed microprocessor-based instrumentation and control systems, the inter-and intra-subsystem communication requirements ultimately form the basis for the overall system architecture. This paper describes a software protocol which addresses the intra-subsystem communications problem. Specifically the protocol allows for multiple processors to exchange information via a shared-memory interface. The authors primary goal is to provide a reliable means for information to be exchanged between central application processor boards (masters) and dedicated function processor boards (slaves) in a single computer chassis. The resultant Multiprocessor Shared-Memory Information Exchange (MSMIE) protocol, a standard master-slave shared-memory interface suitable for use in nuclear safety systems, ismore » designed to pass unidirectional buffers of information between the processors while providing a minimum, deterministic cycle time for this data exchange.« less

  3. The application of digital signal processing techniques to a teleoperator radar system

    NASA Technical Reports Server (NTRS)

    Pujol, A.

    1982-01-01

    A digital signal processing system was studied for the determination of the spectral frequency distribution of echo signals from a teleoperator radar system. The system consisted of a sample and hold circuit, an analog to digital converter, a digital filter, and a Fast Fourier Transform. The system is interfaced to a 16 bit microprocessor. The microprocessor is programmed to control the complete digital signal processing. The digital filtering and Fast Fourier Transform functions are implemented by a S2815 digital filter/utility peripheral chip and a S2814A Fast Fourier Transform chip. The S2815 initially simulates a low-pass Butterworth filter with later expansion to complete filter circuit (bandpass and highpass) synthesizing.

  4. Synchronous clock stopper for microprocessor

    NASA Technical Reports Server (NTRS)

    Kitchin, David A. (Inventor)

    1985-01-01

    A synchronous clock stopper circuit for inhibiting clock pulses to a microprocessor in response to a stop request signal, and for reinstating the clock pulses in response to a start request signal thereby to conserve power consumption of the microprocessor when used in an environment of limited power. The stopping and starting of the microprocessor is synchronized, by a phase tracker, with the occurrences of a predetermined phase in the instruction cycle of the microprocessor in which the I/O data and address lines of the microprocessor are of high impedance so that a shared memory connected to the I/O lines may be accessed by other peripheral devices. The starting and stopping occur when the microprocessor initiates and completes, respectively, an instruction, as well as before and after transferring data with a memory. Also, the phase tracker transmits phase information signals over a bus to other peripheral devices which signals identify the current operational phase of the microprocessor.

  5. Radiation Test Results for Common CubeSat Microcontrollers and Microprocessors

    NASA Technical Reports Server (NTRS)

    Guertin, Steven M.; Amrbar, Mehran; Vartanian, Sergeh

    2015-01-01

    SEL, SEU, and TID results are presented for microcontrollers and microprocessors of interest for small satellite systems such as the TI MSP430F1611, MSP430F1612 and MSP430FR5739, Microchip PIC24F256GA110 and dsPIC33FJ256GP710, Atmel AT91SAM9G20, and Intel Atom E620T, and the Qualcomm Snapdragon APQ8064.

  6. FEDS - An experiment with a microprocessor-based orbit determination system using TDRS data

    NASA Technical Reports Server (NTRS)

    Shank, D.; Pajerski, R.

    1986-01-01

    An experiment in microprocessor-based onboard orbit determination has been conducted at NASA's Goddard Space Flight Center. The experiment collected forward-link observation data in real time from a prototype transponder and performed orbit estimation on a typical low-earth scientific satellite. This paper discusses the hardware and organizational configurations of the experiment, the structure of the onboard software, the mathematical models, and the experiment results.

  7. Interface Provides Standard-Bus Communication

    NASA Technical Reports Server (NTRS)

    Culliton, William G.

    1995-01-01

    Microprocessor-controlled interface (IEEE-488/LVABI) incorporates service-request and direct-memory-access features. Is circuit card enabling digital communication between system called "laser auto-covariance buffer interface" (LVABI) and compatible personal computer via general-purpose interface bus (GPIB) conforming to Institute for Electrical and Electronics Engineers (IEEE) Standard 488. Interface serves as second interface enabling first interface to exploit advantages of GPIB, via utility software written specifically for GPIB. Advantages include compatibility with multitasking and support of communication among multiple computers. Basic concept also applied in designing interfaces for circuits other than LVABI for unidirectional or bidirectional handling of parallel data up to 16 bits wide.

  8. Cumulative Timers for Microprocessors

    NASA Technical Reports Server (NTRS)

    Battle, John O.

    2007-01-01

    It has been proposed to equip future microprocessors with electronic cumulative timers, for essentially the same reasons for which land vehicles are equipped with odometers (total-distance-traveled meters) and aircraft are equipped with Hobbs meters (total-engine-operating time meters). Heretofore, there has been no way to determine the amount of use to which a microprocessor (or a product containing a microprocessor) has been subjected. The proposed timers would count all microprocessor clock cycles and could only be read by means of microprocessor instructions but, like odometers and Hobbs meters, could never be reset to zero without physically damaging the chip.

  9. Advanced development of a programmable power processor

    NASA Technical Reports Server (NTRS)

    Lukens, F. E.; Lanier, J. R., Jr.; Kapustka, R. E.; Graves, J.

    1980-01-01

    The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

  10. Design principles of a cooperative robot controller

    NASA Technical Reports Server (NTRS)

    Hayward, Vincent; Hayati, Samad

    1987-01-01

    The paper describes the design of a controller for cooperative robots being designed at McGill University in a collaborative effort with the Jet Propulsion Laboratory. The first part of the paper discusses the background and motivation for multiple arm control. Then, a set of programming primitives, which are based on the RCCL system and which permit a programmer to specify cooperative tasks are described. The first group of primitives are motion primitives which specify asynchronous motions, master/slave motions, and cooperative motions. In the context of cooperative robots, trajectory generation issues will be discussed and the implementation described. A second set of primitives provides for the specification of spatial relationships. The relations between programming and control in the case of multiple robot are examined. Finally, the paper describes the allocation of various tasks among a set of microprocessors sharing a common bus.

  11. A microprocessor-based automation test system for the experiment of the multi-stage compressor

    NASA Astrophysics Data System (ADS)

    Zhang, Huisheng; Lin, Chongping

    1991-08-01

    An automation test system that is controlled by the microprocessor and used in the multistage compressor experiment is described. Based on the analysis of the compressor experiment performances, a complete hardware system structure is set up. It is composed of a IBM PC/XT computer, a large scale sampled data system, the moving machine with three directions, the scanners, the digital instrumentation and some output devices. A program structure of real-time software system is described. The testing results show that this test system can take the measure of many parameter magnitudes in the blade row places and on a boundary layer in different states. The automatic extent and the accuracy of experiment is increased and the experimental cost is reduced.

  12. System and method for leveraging human physiological traits to control microprocessor frequency

    DOEpatents

    Shye, Alex; Pan, Yan; Scholbrock, Benjamin; Miller, J. Scott; Memik, Gokhan; Dinda, Peter A; Dick, Robert P

    2014-03-25

    A system and method for leveraging physiological traits to control microprocessor frequency are disclosed. In some embodiments, the system and method may optimize, for example, a particular processor-based architecture based on, for example, end user satisfaction. In some embodiments, the system and method may determine, for example, whether their users are satisfied to provide higher efficiency, improved reliability, reduced power consumption, increased security, and a better user experience. The system and method may use, for example, biometric input devices to provide information about a user's physiological traits to a computer system. Biometric input devices may include, for example, one or more of the following: an eye tracker, a galvanic skin response sensor, and/or a force sensor.

  13. Development of a microprocessor controller for stand-alone photovoltaic power systems

    NASA Technical Reports Server (NTRS)

    Millner, A. R.; Kaufman, D. L.

    1984-01-01

    A controller for stand-alone photovoltaic systems has been developed using a low power CMOS microprocessor. It performs battery state of charge estimation, array control, load management, instrumentation, automatic testing, and communications functions. Array control options are sequential subarray switching and maximum power control. A calculator keypad and LCD display provides manual control, fault diagnosis and digital multimeter functions. An RS-232 port provides data logging or remote control capability. A prototype 5 kW unit has been built and tested successfully. The controller is expected to be useful in village photovoltaic power systems, large solar water pumping installations, and other battery management applications.

  14. Device and method for measuring multi-phase fluid flow in a conduit using an elbow flow meter

    DOEpatents

    Ortiz, Marcos G.; Boucher, Timothy J.

    1997-01-01

    A system for measuring fluid flow in a conduit. The system utilizes pressure transducers disposed generally in line upstream and downstream of the flow of fluid in a bend in the conduit. Data from the pressure transducers is transmitted to a microprocessor or computer. The pressure differential measured by the pressure transducers is then used to calculate the fluid flow rate in the conduit. Control signals may then be generated by the microprocessor or computer to control flow, total fluid dispersed, (in, for example, an irrigation system), area of dispersal or other desired effect based on the fluid flow in the conduit.

  15. System and method for bidirectional flow and controlling fluid flow in a conduit

    DOEpatents

    Ortiz, Marcos German

    1999-01-01

    A system for measuring bidirectional flow, including backflow, of fluid in a conduit. The system utilizes a structural mechanism to create a pressure differential in the conduit. Pressure sensors are positioned upstream from the mechanism, at the mechanism, and downstream from the mechanism. Data from the pressure sensors are transmitted to a microprocessor or computer, and pressure differential detected between the pressure sensors is then used to calculate the backflow. Control signals may then be generated by the microprocessor or computer to shut off valves located in the conduit, upon the occurrence of backflow, or to control flow, total material dispersed, etc. in the conduit.

  16. Predictive sensor method and apparatus

    NASA Technical Reports Server (NTRS)

    Cambridge, Vivien J.; Koger, Thomas L.

    1993-01-01

    A microprocessor and electronics package employing predictive methodology was developed to accelerate the response time of slowly responding hydrogen sensors. The system developed improved sensor response time from approximately 90 seconds to 8.5 seconds. The microprocessor works in real-time providing accurate hydrogen concentration corrected for fluctuations in sensor output resulting from changes in atmospheric pressure and temperature. Following the successful development of the hydrogen sensor system, the system and predictive methodology was adapted to a commercial medical thermometer probe. Results of the experiment indicate that, with some customization of hardware and software, response time improvements are possible for medical thermometers as well as other slowly responding sensors.

  17. Deepthi Vaidhynathan | NREL

    Science.gov Websites

    Complex Systems Simulation and Optimization Group on performance analysis and benchmarking latest . Research Interests High Performance Computing|Embedded System |Microprocessors & Microcontrollers

  18. Using benchmarks for radiation testing of microprocessors and FPGAs

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Quinn, Heather; Robinson, William H.; Rech, Paolo

    Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

  19. Using benchmarks for radiation testing of microprocessors and FPGAs

    DOE PAGES

    Quinn, Heather; Robinson, William H.; Rech, Paolo; ...

    2015-12-17

    Performance benchmarks have been used over the years to compare different systems. These benchmarks can be useful for researchers trying to determine how changes to the technology, architecture, or compiler affect the system's performance. No such standard exists for systems deployed into high radiation environments, making it difficult to assess whether changes in the fabrication process, circuitry, architecture, or software affect reliability or radiation sensitivity. In this paper, we propose a benchmark suite for high-reliability systems that is designed for field-programmable gate arrays and microprocessors. As a result, we describe the development process and report neutron test data for themore » hardware and software benchmarks.« less

  20. An Economic Analysis of Two Groundwater Allocation Programs for the Salinas Valley

    DTIC Science & Technology

    1994-06-01

    monitoring system would establish a definable and 17Each individual well would have a frequency generator, analog/ digital converter, microprocessor with...RTU). The cost for purchasing and installing the frequency generator is estimated to be $1,100. The RTU consists of an analog/ digital converter and a...programmable microprocessor that can accept up to eight inputs and one output. The unit can transmit and receive digital data via LAN network or

  1. Programmable data collection platform study

    NASA Technical Reports Server (NTRS)

    1976-01-01

    The results of a feasibility study incorporating microprocessors in data collection platforms in described. An introduction to microcomputer hardware and software concepts is provided. The influence of microprocessor technology on the design of programmable data collection platform hardware is discussed. A standard modular PDCP design capable of meeting the design goals is proposed, and the process of developing PDCP programs is examined. A description of design and construction of the UT PDCP development system is given.

  2. Microprocessor Technology for Managers.

    DTIC Science & Technology

    1976-05-01

    HOURS IS THE APPLICATION OF MICROPROCESSORS TO VIDEO GAMES SUCH AS PING PONG, HANDBALL 1 SPACE WAR GAMES , AND COWBOYS AND INDIANS. MANY MANUFACTURERS OF...MICR OPROCESSOR COMPANIES AEG—T ELEFUNKEN~ 6 FRANKFURT 70, AEG-HOCHHAUS 1 GERMANY . ADAPTIVE SYSTEMS1 P.O . BOX 1481, POMPANO BEACH , FL 33061. -(305...KAWASAKI — CHI , JAPAN . WESTERN DIGITAL , 19242 RED HILL AVE. 1 NEWPORT BEACH I CA 92663. {714) 557-3550. ZILOG, 170 STATE ST., LOS ALTOS 1 CA 94022. {415

  3. Power Converters Maximize Outputs Of Solar Cell Strings

    NASA Technical Reports Server (NTRS)

    Frederick, Martin E.; Jermakian, Joel B.

    1993-01-01

    Microprocessor-controlled dc-to-dc power converters devised to maximize power transferred from solar photovoltaic strings to storage batteries and other electrical loads. Converters help in utilizing large solar photovoltaic arrays most effectively with respect to cost, size, and weight. Main points of invention are: single controller used to control and optimize any number of "dumb" tracker units and strings independently; power maximized out of converters; and controller in system is microprocessor.

  4. Microprocessor utilization in search and rescue missions

    NASA Technical Reports Server (NTRS)

    Schwartz, M.

    1977-01-01

    The feasibility of performing the same task in real time using microprocessor technology was determined. The least square algorithm was implemented on an Intel 8080 microprocessor. Results indicated that a microprocessor could easily match the IBM implementation in accuracy and be performed inside the time limitations set.

  5. A case study for the real-time experimental evaluation of the VIPER microprocessor

    NASA Astrophysics Data System (ADS)

    Carreno, Victor A.; Angellatta, Rob K.

    1991-09-01

    An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

  6. A case study for the real-time experimental evaluation of the VIPER microprocessor

    NASA Technical Reports Server (NTRS)

    Carreno, Victor A.; Angellatta, Rob K.

    1991-01-01

    An experiment to evaluate the applicability of the Verifiable Integrated Processor for Enhanced Reliability (VIPER) microprocessor to real time control is described. The VIPER microprocessor was invented by the Royal Signals and Radar Establishment (RSRE), U.K., and is an example of the use of formal mathematical methods for developing electronic digital systems with a high degree of assurance on the system design and implementation correctness. The experiment consisted of selecting a control law, writing the control law algorithm for the VIPER processor, and providing real time, dynamic inputs into the processor and monitoring the outputs. The control law selected and coded for the VIPER processor was the yaw damper function of an automatic landing program for a 737 aircraft. The mechanisms for interfacing the VIPER Single Board Computer to the VAX host are described. Results include run time experiences, performance evaluation, and comparison of VIPER and FORTRAN yaw damper algorithm output for accuracy estimation.

  7. Microprocessors in U.S. Electrical Engineering Departments, 1974-1975.

    ERIC Educational Resources Information Center

    Sloan, M. E.

    Drawn from a survey of engineering departments known to be teaching microprocessor courses, this paper shows that the adoption of microprocessors by Electrical Engineering Departments has been rapid compared with their adoption of minicomputers. The types of courses that are being taught can be categorized as: surveys of microprocessors, intensive…

  8. 76 FR 39895 - In the Matter of Certain Microprocessors, Components Thereof, and Products Containing Same...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2011-07-07

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-781] In the Matter of Certain Microprocessors... importation of certain microprocessors, components thereof, and products containing same by reason of... microprocessors, components thereof, and products containing same that infringe one or more of claims 11-16, 41...

  9. Use of electronic microprocessor-based instrumentation by the U.S. geological survey for hydrologic data collection

    USGS Publications Warehouse

    Shope, William G.; ,

    1991-01-01

    The U.S. Geological Survey is acquiring a new generation of field computers and communications software to support hydrologic data-collection at field locations. The new computer hardware and software mark the beginning of the Survey's transition from the use of electromechanical devices and paper tapes to electronic microprocessor-based instrumentation. Software is being developed for these microprocessors to facilitate the collection, conversion, and entry of data into the Survey's National Water Information System. The new automated data-collection process features several microprocessor-controlled sensors connected to a serial digital multidrop line operated by an electronic data recorder. Data are acquired from the sensors in response to instructions programmed into the data recorder by the user through small portable lap-top or hand-held computers. The portable computers, called personal field computers, also are used to extract data from the electronic recorders for transport by courier to the office computers. The Survey's alternative to manual or courier retrieval is the use of microprocessor-based remote telemetry stations. Plans have been developed to enhance the Survey's use of the Geostationary Operational Environmental Satellite telemetry by replacing the present network of direct-readout ground stations with less expensive units. Plans also provide for computer software that will support other forms of telemetry such as telephone or land-based radio.

  10. The special radiation-hardened processors for new highly informative experiments in space

    NASA Astrophysics Data System (ADS)

    Serdin, O. V.; Antonov, A. A.; Dubrovsky, A. G.; Novogilov, E. A.; Zuev, A. L.

    2017-01-01

    The article provides a detailed description of the series of special radiation-hardened microprocessor developed by SRISA for use in space technology. The microprocessors have 32-bit and 64-bit KOMDIV architecture with embedded SpaceWire, RapidIO, Ethernet and MIL-STD-1553B interfaces. These devices are used in space telescope GAMMA-400 data acquisition system, and may also be applied to other experiments in space (such as observatory “Millimetron” etc.).

  11. DSS 13 Microprocessor Antenna Controller

    NASA Technical Reports Server (NTRS)

    Gosline, R. M.

    1984-01-01

    A microprocessor based antenna controller system developed as part of the unattended station project for DSS 13 is described. Both the hardware and software top level designs are presented and the major problems encounted are discussed. Developments useful to related projects include a JPL standard 15 line interface using a single board computer, a general purpose parser, a fast floating point to ASCII conversion technique, and experience gained in using off board floating point processors with the 8080 CPU.

  12. Test report for single event effects of the 80386DX microprocessor

    NASA Technical Reports Server (NTRS)

    Watson, R. Kevin; Schwartz, Harvey R.; Nichols, Donald K.

    1993-01-01

    The Jet Propulsion Laboratory Section 514 Single Event Effects (SEE) Testing and Analysis Group has performed a series of SEE tests of certain strategic registers of Intel's 80386DX CHMOS 4 microprocessor. Following a summary of the test techniques and hardware used to gather the data, we present the SEE heavy ion and proton test results. We also describe the registers tested, along with a system impact analysis should these registers experience a single event upset.

  13. TDP-43 regulates the microprocessor complex activity during in vitro neuronal differentiation.

    PubMed

    Di Carlo, Valerio; Grossi, Elena; Laneve, Pietro; Morlando, Mariangela; Dini Modigliani, Stefano; Ballarino, Monica; Bozzoni, Irene; Caffarelli, Elisa

    2013-12-01

    TDP-43 (TAR DNA-binding protein 43) is an RNA-binding protein implicated in RNA metabolism at several levels. Even if ubiquitously expressed, it is considered as a neuronal activity-responsive factor and a major signature for neurological pathologies, making the comprehension of its activity in the nervous system a very challenging issue. TDP-43 has also been described as an accessory component of the Drosha-DGCR8 (DiGeorge syndrome critical region gene 8) microprocessor complex, which is crucially involved in basal and tissue-specific RNA processing events. In the present study, we exploited in vitro neuronal differentiation systems to investigate the TDP-43 demand for the microprocessor function, focusing on both its canonical microRNA biosynthetic activity and its alternative role as a post-transcriptional regulator of gene expression. Our findings reveal a novel role for TDP-43 as an essential factor that controls the stability of Drosha protein during neuronal differentiation, thus globally affecting the production of microRNAs. We also demonstrate that TDP-43 is required for the Drosha-mediated regulation of Neurogenin 2, a master gene orchestrating neurogenesis, whereas post-transcriptional control of Dgcr8, another Drosha target, resulted to be TDP-43-independent. These results implicate a previously uncovered contribution of TDP-43 in regulating the abundance and the substrate specificity of the microprocessor complex and provide new insights into TDP-43 as a key player in neuronal differentiation.

  14. Autoregulatory mechanisms controlling the Microprocessor.

    PubMed

    Triboulet, Robinson; Gregory, Richard I

    2010-01-01

    The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature 22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part ofa newly identified regulatory mechanism controlling Microprocessor activity.

  15. Experience in the installation of a microprocessor system for controlling converter units of the Vyborg substation

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Gusakovskii, K. B.; Zmaznov, E. Yu.; Katantsev, S. V.

    The experience in the installation of modern digital systems for controlling converter units at the Vyborg converter substation on the basis of advanced microprocessor devices is considered. It is shown that debugging of a control and protection system on mathematical and physical models does not guarantee optimum control of actual converter devices. Examples of advancing the control and protection system are described, the necessity for which has become obvious in tests of actual equipment. Comparison of oscillograms of processes before optimization of the control system and after its optimization and adjustment shows that the digital control system makes it possiblemore » to improve substantially the algorithms of control and protection in the short term and without changing the hardware component.« less

  16. Enhancement of a prosthetic knee with a microprocessor-controlled gait phase switch reduces falls and improves balance confidence and gait speed in community ambulators with unilateral transfemoral amputation.

    PubMed

    Fuenzalida Squella, Sara Agueda; Kannenberg, Andreas; Brandão Benetti, Ângelo

    2018-04-01

    Despite the evidence for improved safety and function of microprocessor stance and swing-controlled prosthetic knees, non-microprocessor-controlled prosthetic knees are still standard of care for persons with transfemoral amputations in most countries. Limited feature microprocessor-control enhancement of such knees could stand to significantly improve patient outcomes. To evaluate gait speed, balance, and fall reduction benefits of the new 3E80 default stance hydraulic knee compared to standard non-microprocessor-controlled prosthetic knees. Comparative within-subject clinical study. A total of 13 young, high-functioning community ambulators with a transfemoral amputation underwent assessment of performance-based (e.g. 2-min walk test, timed ramp/stair tests) and self-reported (e.g. falls, Activities-Specific Balance Confidence scale, Prosthesis Evaluation Questionnaire question #1, Satisfaction with the Prosthesis) outcome measures for their non-microprocessor-controlled prosthetic knees and again after 8 weeks of accommodation to the 3E80 microprocessor-enhanced knee. Self-reported falls significantly declined 77% ( p = .04), Activities-Specific Balance Confidence scores improved 12 points ( p = .005), 2-min walk test walking distance increased 20 m on level ( p = .01) and uneven ( p = .045) terrain, and patient satisfaction significantly improved ( p < .01) when using the 3E80 knee. Slope and stair ambulation performance did not differ between knee conditions. The 3E80 knee reduced self-reported fall incidents and improved balance confidence. Walking performance on both level and uneven terrains also improved compared to non-microprocessor-controlled prosthetic knees. Subjects' satisfaction was significantly higher than with their previous non-microprocessor-controlled prosthetic knees. The 3E80 may be considered a prosthetic option for improving gait performance, balance confidence, and safety in highly active amputees. Clinical relevance This study compared performance-based and self-reported outcome measures when using non-microprocessor and a new microprocessor-enhanced, default stance rotary hydraulic knee. The results inform rehabilitation professionals about the functional benefits of a limited-feature, microprocessor-enhanced hydraulic prosthetic knee over standard non-microprocessor-controlled prosthetic knees.

  17. The Single Event Effect Characteristics of the 486-DX4 Microprocessor

    NASA Technical Reports Server (NTRS)

    Kouba, Coy; Choi, Gwan

    1996-01-01

    This research describes the development of an experimental radiation testing environment to investigate the single event effect (SEE) susceptibility of the 486-DX4 microprocessor. SEE effects are caused by radiation particles that disrupt the logic state of an operating semiconductor, and include single event upsets (SEU) and single event latchup (SEL). The relevance of this work can be applied directly to digital devices that are used in spaceflight computer systems. The 486-DX4 is a powerful commercial microprocessor that is currently under consideration for use in several spaceflight systems. As part of its selection process, it must be rigorously tested to determine its overall reliability in the space environment, including its radiation susceptibility. The goal of this research is to experimentally test and characterize the single event effects of the 486-DX4 microprocessor using a cyclotron facility as the fault-injection source. The test philosophy is to focus on the "operational susceptibility," by executing real software and monitoring for errors while the device is under irradiation. This research encompasses both experimental and analytical techniques, and yields a characterization of the 486-DX4's behavior for different operating modes. Additionally, the test methodology can accommodate a wide range of digital devices, such as microprocessors, microcontrollers, ASICS, and memory modules, for future testing. The goals were achieved by testing with three heavy-ion species to provide different linear energy transfer rates, and a total of six microprocessor parts were tested from two different vendors. A consistent set of error modes were identified that indicate the manner in which the errors were detected in the processor. The upset cross-section curves were calculated for each error mode, and the SEU threshold and saturation levels were identified for each processor. Results show a distinct difference in the upset rate for different configurations of the on-chip cache, as well as proving that one vendor is superior to the other in terms of latchup susceptibility. Results from this testing were also used to provide a mean-time-between-failure estimate of the 486-DX4 operating in the radiation environment for the International Space Station.

  18. Rad-hard computer elements for space applications

    NASA Technical Reports Server (NTRS)

    Krishnan, G. S.; Longerot, Carl D.; Treece, R. Keith

    1993-01-01

    Space Hardened CMOS computer elements emulating a commercial microcontroller and microprocessor family have been designed, fabricated, qualified, and delivered for a variety of space programs including NASA's multiple launch International Solar-Terrestrial Physics (ISTP) program, Mars Observer, and government and commercial communication satellites. Design techniques and radiation performance of the 1.25 micron feature size products are described.

  19. General, database-driven fast-feedback system for the Stanford Linear Collider

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Rouse, F.; Allison, S.; Castillo, S.

    A new feedback system has been developed for stabilizing the SLC beams at many locations. The feedback loops are designed to sample and correct at the 60 Hz repetition rate of the accelerator. Each loop can be distributed across several of the standard 80386 microprocessors which control the SLC hardware. A new communications system, KISNet, has been implemented to pass signals between the microprocessors at this rate. The software is written in a general fashion using the state space formalism of digital control theory. This allows a new loop to be implemented by just setting up the online database andmore » perhaps installing a communications link. 3 refs., 4 figs.« less

  20. System and method for bidirectional flow and controlling fluid flow in a conduit

    DOEpatents

    Ortiz, M.G.

    1999-03-23

    A system for measuring bidirectional flow, including backflow, of fluid in a conduit is disclosed. The system utilizes a structural mechanism to create a pressure differential in the conduit. Pressure sensors are positioned upstream from the mechanism, at the mechanism, and downstream from the mechanism. Data from the pressure sensors are transmitted to a microprocessor or computer, and pressure differential detected between the pressure sensors is then used to calculate the backflow. Control signals may then be generated by the microprocessor or computer to shut off valves located in the conduit, upon the occurrence of backflow, or to control flow, total material dispersed, etc. in the conduit. 3 figs.

  1. Device and method for measuring multi-phase fluid flow in a conduit using an elbow flow meter

    DOEpatents

    Ortiz, M.G.; Boucher, T.J.

    1997-06-24

    A system is described for measuring fluid flow in a conduit. The system utilizes pressure transducers disposed generally in line upstream and downstream of the flow of fluid in a bend in the conduit. Data from the pressure transducers is transmitted to a microprocessor or computer. The pressure differential measured by the pressure transducers is then used to calculate the fluid flow rate in the conduit. Control signals may then be generated by the microprocessor or computer to control flow, total fluid dispersed, (in, for example, an irrigation system), area of dispersal or other desired effect based on the fluid flow in the conduit. 2 figs.

  2. A microprocessor-based control system for the Vienna PDS microdensitometer

    NASA Technical Reports Server (NTRS)

    Jenkner, H.; Stoll, M.; Hron, J.

    1984-01-01

    The Motorola Exorset 30 system, based on a Motorola 6809 microprocessor which serves as control processor for the microdensitometer is presented. User communication and instrument control are implemented in this syatem; data transmission to a host computer is provided via standard interfaces. The Vienna PDS system (VIPS) software was developed in BASIC and M6809 assembler. It provides efficient user interaction via function keys and argument input in a menu oriented environment. All parameters can be stored on, and retrieved from, minifloppy disks, making it possible to set up large scanning tasks. Extensive user information includes continuously updated status and coordinate displays, as well as a real time graphic display during scanning.

  3. Debris measure subsystem of the nanosatellite IRECIN

    NASA Astrophysics Data System (ADS)

    Ferrante, M.; di Ciolo, L.; Ortenzi, A.; Petrozzi, M.; del Re, V.

    2003-09-01

    The on board resources, needed to perform the mission tasks, are very limited in nano-satellites. This paper proposes an Electronic real-time system that acquires space debris measures. It uses a piezo-electric sensor. The described device is a subsystem on board of the IRECIN nanosatellite composed mainly by a r.i.s.c. microprocessor, an electronic part that interfaces to the debris sensor in order to provide a low noise electrical and suitable range to ADC 12 bit converter, and finally a memory in order to store the data. The microprocessor handles the Debris Measure System measuring the impacts number, their intensity and storing their waves form. This subsystem is able to communicate with the other IRECIN subsystems through I2C Bus and principally with the "Main Microprocessor" subsystem allowing the data download directly to the Ground Station. Moreover this subsystem lets free the "Main Microprocessor Board" from the management and charge of debris data. All electronic components are SMD technology in order to reduce weight and size. The realized Electronic board are completely developed, realized and tested at the Vitrociset S.P.A. under control of Research and Development Group. The proposed system is implemented on the IRECIN, a modular nanosatellite weighting less than 1.5 kg, constituted by sixteen external sides with surface-mounted solar cells and three internal Al plates, kept together by four steel bars. Lithium-ions batteries are added for eclipse operations. Attitude is determined by two three-axis magnetometers and the solar panels data. Control is provided by an active magnetic control system. The spacecraft will be spin-stabilized with the spin-axis normal to the orbit. debris and micrometeoroids mass and velocity.

  4. Design, development, and field demonstration of a remotely deployable water quality monitoring system

    NASA Technical Reports Server (NTRS)

    Wallace, J. W.; Lovelady, R. W.; Ferguson, R. L.

    1981-01-01

    A prototype water quality monitoring system is described which offers almost continuous in situ monitoring. The two-man portable system features: (1) a microprocessor controlled central processing unit which allows preprogrammed sampling schedules and reprogramming in situ; (2) a subsurface unit for multiple depth capability and security from vandalism; (3) an acoustic data link for communications between the subsurface unit and the surface control unit; (4) eight water quality parameter sensors; (5) a nonvolatile magnetic bubble memory which prevents data loss in the event of power interruption; (6) a rechargeable power supply sufficient for 2 weeks of unattended operation; (7) a water sampler which can collect samples for laboratory analysis; (8) data output in direct engineering units on printed tape or through a computer compatible link; (9) internal electronic calibration eliminating external sensor adjustment; and (10) acoustic location and recovery systems. Data obtained in Saginaw Bay, Lake Huron are tabulated.

  5. Validation of a wireless modular monitoring system for structures

    NASA Astrophysics Data System (ADS)

    Lynch, Jerome P.; Law, Kincho H.; Kiremidjian, Anne S.; Carryer, John E.; Kenny, Thomas W.; Partridge, Aaron; Sundararajan, Arvind

    2002-06-01

    A wireless sensing unit for use in a Wireless Modular Monitoring System (WiMMS) has been designed and constructed. Drawing upon advanced technological developments in the areas of wireless communications, low-power microprocessors and micro-electro mechanical system (MEMS) sensing transducers, the wireless sensing unit represents a high-performance yet low-cost solution to monitoring the short-term and long-term performance of structures. A sophisticated reduced instruction set computer (RISC) microcontroller is placed at the core of the unit to accommodate on-board computations, measurement filtering and data interrogation algorithms. The functionality of the wireless sensing unit is validated through various experiments involving multiple sensing transducers interfaced to the sensing unit. In particular, MEMS-based accelerometers are used as the primary sensing transducer in this study's validation experiments. A five degree of freedom scaled test structure mounted upon a shaking table is employed for system validation.

  6. IOTA: the array controller for a gigapixel OTCCD camera for Pan-STARRS

    NASA Astrophysics Data System (ADS)

    Onaka, Peter; Tonry, John; Luppino, Gerard; Lockhart, Charles; Lee, Aaron; Ching, Gregory; Isani, Sidik; Uyeshiro, Robin

    2004-09-01

    The PanSTARRS project has undertaken an ambitious effort to develop a completely new array controller architecture that is fundamentally driven by the large 1gigapixel, low noise, high speed OTCCD mosaic requirements as well as the size, power and weight restrictions of the PanSTARRS telescope. The result is a very small form factor next generation controller scalar building block with 1 Gigabit Ethernet interfaces that will be assembled into a system that will readout 512 outputs at ~1 Megapixel sample rates on each output. The paper will also discuss critical technology and fabrication techniques such as greater than 1MHz analog to digital converters (ADCs), multiple fast sampling and digital calculation of multiple correlated samples (DMCS), ball grid array (BGA) packaged circuits, LINUX running on embedded field programmable gate arrays (FPGAs) with hard core microprocessors for the prototype currently being developed.

  7. Implementation of the DAST ARW II control laws using an 8086 microprocessor and an 8087 floating-point coprocessor. [drones for aeroelasticity research

    NASA Technical Reports Server (NTRS)

    Kelly, G. L.; Berthold, G.; Abbott, L.

    1982-01-01

    A 5 MHZ single-board microprocessor system which incorporates an 8086 CPU and an 8087 Numeric Data Processor is used to implement the control laws for the NASA Drones for Aerodynamic and Structural Testing, Aeroelastic Research Wing II. The control laws program was executed in 7.02 msec, with initialization consuming 2.65 msec and the control law loop 4.38 msec. The software emulator execution times for these two tasks were 36.67 and 61.18, respectively, for a total of 97.68 msec. The space, weight and cost reductions achieved in the present, aircraft control application of this combination of a 16-bit microprocessor with an 80-bit floating point coprocessor may be obtainable in other real time control applications.

  8. "Smart" Sensor Module

    NASA Technical Reports Server (NTRS)

    Mahajan, Ajay

    2007-01-01

    An assembly that contains a sensor, sensor-signal-conditioning circuitry, a sensor-readout analog-to-digital converter (ADC), data-storage circuitry, and a microprocessor that runs special-purpose software and communicates with one or more external computer(s) has been developed as a prototype of "smart" sensor modules for monitoring the integrity and functionality (the "health") of engineering systems. Although these modules are now being designed specifically for use on rocket-engine test stands, it is anticipated that they could also readily be designed to be incorporated into health-monitoring subsystems of such diverse engineering systems as spacecraft, aircraft, land vehicles, bridges, buildings, power plants, oilrigs, and defense installations. The figure is a simplified block diagram of the "smart" sensor module. The analog sensor readout signal is processed by the ADC, the digital output of which is fed to the microprocessor. By means of a standard RS-232 cable, the microprocessor is connected to a local personal computer (PC), from which software is downloaded into a randomaccess memory in the microprocessor. The local PC is also used to debug the software. Once the software is running, the local PC is disconnected and the module is controlled by, and all output data from the module are collected by, a remote PC via an Ethernet bus. Several smart sensor modules like this one could be connected to the same Ethernet bus and controlled by the single remote PC. The software running in the microprocessor includes driver programs for operation of the sensor, programs that implement self-assessment algorithms, programs that implement protocols for communication with the external computer( s), and programs that implement evolutionary methodologies to enable the module to improve its performance over time. The design of the module and of the health-monitoring system of which it is a part reflects the understanding that the main purpose of a health-monitoring system is to detect damage and, therefore, the health-monitoring system must be able to function effectively in the presence of damage and should be capable of distinguishing between damage to itself and damage to the system being monitored. A major benefit afforded by the self-assessment algorithms is that in the output of the module, the sensor data indicative of the health of the engineering system being monitored are coupled with a confidence factor that quantifies the degree of reliability of the data. Hence, the output includes information on the health of the sensor module itself in addition to information on the health of the engineering system being monitored.

  9. Microprocessor Control Design for a Low-Head Crossflow Turbine.

    DTIC Science & Technology

    1985-03-01

    Controllers For a Typical 10 KW Hydroturbine ............ 1-5 I-1 Ely’s Crossflow Turbine . ........ 11-2 11-2 Basic Turbine * * 0 * 0 11-5 11-3 Turbine...the systems. For example, a 25 kilowatt hydroturbine built and installed by Bell Hydroelectric would cost approximately $20,000 in 1978 (6:49). The...O Manual Controller S2 E- Microprocessor Controller 1 2 3 4 5 6 7 8 YEARS Fig. 1-2 Comparative Costs of Controllers For a Typical 10 KW Hydroturbine

  10. Microprocessor realizations of range rate filters

    NASA Technical Reports Server (NTRS)

    1979-01-01

    The performance of five digital range rate filters is evaluated. A range rate filter receives an input of range data from a radar unit and produces an output of smoothed range data and its estimated derivative range rate. The filters are compared through simulation on an IBM 370. Two of the filter designs are implemented on a 6800 microprocessor-based system. Comparisons are made on the bases of noise variance reduction ratios and convergence times of the filters in response to simulated range signals.

  11. Autoregulatory mechanisms controlling the microprocessor.

    PubMed

    Triboulet, Robinson; Gregory, Richard I

    2011-01-01

    The Microprocessor, comprising the ribonuclease Drosha and its essential cofactor, the double-stranded RNA-binding protein, DGCR8, is essential for the first step of the miRNA biogenesis pathway. It specifically cleaves double-stranded RNA within stem-loop structures of primary miRNA transcripts (pri-miRNAs) to generate precursor (pre-miRNA) intermediates. Pre-miRNAs are subsequently processed by Dicer to their mature ∼22 nt form. Thus, Microprocessor is essential for miRNA maturation, and pri-miRNA cleavage by this complex defines one end of the mature miRNA. Moreover, it is emerging that dysregulation of the Microprocessor is associated with various human diseases. It is therefore important to understand the mechanisms by which the expression of the subunits of the Microprocessor is regulated. Recent findings have uncovered a post-transcriptional mechanism that maintains the integrity of the Microprocessor. These studies revealed that the Microprocessor is involved in the processing of the messenger RNA (mRNA) that encodes DGCR8. This regulatory feedback loop, along with the reported role played by DGCR8 in the stabilization of Drosha protein, is part of a newly identified regulatory mechanism controlling Microprocessor activity.

  12. Post-transcriptional control of DGCR8 expression by the Microprocessor.

    PubMed

    Triboulet, Robinson; Chang, Hao-Ming; Lapierre, Robert J; Gregory, Richard I

    2009-06-01

    The Microprocessor, comprising the RNase III Drosha and the double-stranded RNA binding protein DGCR8, is essential for microRNA (miRNA) biogenesis. In the miRNA processing pathway certain hairpin structures within primary miRNA (pri-miRNA) transcripts are specifically cleaved by the Microprocessor to release approximately 60-70-nucleotide precursor miRNA (pre-miRNA) intermediates. Although both Drosha and DGCR8 are required for Microprocessor activity, the mechanisms regulating the expression of these proteins are unknown. Here we report that the Microprocessor negatively regulates DGCR8 expression. Using in vitro reconstitution and in vivo studies, we demonstrate that a hairpin, localized in the 5' untranslated region (5'UTR) of DGCR8 mRNA, is cleaved by the Microprocessor. Accordingly, knockdown of Drosha leads to an increase in DGCR8 mRNA and protein levels in cells. Furthermore, we found that the DGCR8 5'UTR confers Microprocessor-dependent repression of a luciferase reporter gene in vivo. Our results uncover a novel feedback loop that regulates DGCR8 levels.

  13. Microprocessors in Schools?

    ERIC Educational Resources Information Center

    Cuthbert, L. G.

    1981-01-01

    Examines reasons for including microprocessors in school curricula. Indicates that practical work with microprocessors is not easy and discusses problems associated with using and constructing these control and processing devices of microcomputers. (SK)

  14. APPLEPIPS /Apple Personal Image Processing System/ - An interactive digital image processing system for the Apple II microcomputer

    NASA Technical Reports Server (NTRS)

    Masuoka, E.; Rose, J.; Quattromani, M.

    1981-01-01

    Recent developments related to microprocessor-based personal computers have made low-cost digital image processing systems a reality. Image analysis systems built around these microcomputers provide color image displays for images as large as 256 by 240 pixels in sixteen colors. Descriptive statistics can be computed for portions of an image, and supervised image classification can be obtained. The systems support Basic, Fortran, Pascal, and assembler language. A description is provided of a system which is representative of the new microprocessor-based image processing systems currently on the market. While small systems may never be truly independent of larger mainframes, because they lack 9-track tape drives, the independent processing power of the microcomputers will help alleviate some of the turn-around time problems associated with image analysis and display on the larger multiuser systems.

  15. Computer Technology: State of the Art.

    ERIC Educational Resources Information Center

    Withington, Frederic G.

    1981-01-01

    Describes the nature of modern general-purpose computer systems, including hardware, semiconductor electronics, microprocessors, computer architecture, input output technology, and system control programs. Seven suggested readings are cited. (FM)

  16. ASRC Aerospace Corporation Selects Dynamically Reconfigurable Anadigm(Registered Trademark) FPAA For Advanced Data Acquisition System

    NASA Technical Reports Server (NTRS)

    Mata, Carlos T.

    2003-01-01

    Anadigm(registered trademark) today announced that ASRC Aerospace Corporation has designed Anadigm's dynamically reconfigurable Field Programmable Analog Array (FPAA) technology into an advanced data acquisition system developed under contract for NASA. ASRC Aerospace designed in the Anadigm(registered trademark) FPAA to provide complex analog signal conditioning in its intelligent, self-calibrating, and self-healing advanced data acquisition system (ADAS). The ADAS has potential applications in industrial, manufacturing, and aerospace markets. This system offers highly reliable operation while reducing the need for user interaction. Anadigm(registered trademark)'s dynamically reconfigurable FPAAs can be reconfigured in-system by the designer or on the fly by a microprocessor. A single device can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. In the case of the ASRC advanced data acquisition system, the FPAA helps ensure that the system will continue to operating at 100% functionality despite changes in the environment, component degradation, and/or component failures.

  17. Microprocessor prosthetic knees.

    PubMed

    Berry, Dale

    2006-02-01

    This article traces the development of microprocessor prosthetic knees from early research in the 1970s to the present. Read about how microprocessor knees work, functional options, patient selection, and the future of this prosthetic.

  18. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

    Code of Federal Regulations, 2013 CFR

    2013-01-01

    ... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

  19. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

  20. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for ‘military...

    Code of Federal Regulations, 2014 CFR

    2014-01-01

    ... reexports of general purpose microprocessors for âmilitary end usesâ and to âmilitary end usersâ. 744.17... microprocessors for ‘military end uses’ and to ‘military end users’. (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

  1. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

  2. 15 CFR 744.17 - Restrictions on certain exports and reexports of general purpose microprocessors for “military...

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... reexports of general purpose microprocessors for âmilitary end-usesâ and to âmilitary end-users.â 744.17... microprocessors for “military end-uses” and to “military end-users.” (a) General prohibition. In addition to the... reexport commodities described in ECCN 3A991.a.1 on the CCL (“microprocessor microcircuits”, “microcomputer...

  3. Post-Coma Persons Emerged from a Minimally Conscious State and Showing Multiple Disabilities Learn to Manage a Radio-Listening Activity

    ERIC Educational Resources Information Center

    Lancioni, Giulio E.; Singh, Nirbhay N.; O'Reilly, Mark F.; Sigafoos, Jeff; Colonna, Fabio; Buonocunto, Francesca; Sacco, Valentina; Megna, Marisa; Oliva, Doretta

    2012-01-01

    This study assessed microswitch-based technology to enable three post-coma adults, who had emerged from a minimally conscious state but presented motor and communication disabilities, to operate a radio device. The material involved a modified radio device, a microprocessor-based electronic control unit, a personal microswitch, and an amplified…

  4. Can low-cost VOR and Omega receivers suffice for RNAV - A new computer-based navigation technique

    NASA Technical Reports Server (NTRS)

    Hollaar, L. A.

    1978-01-01

    It is shown that although RNAV is particularly valuable for the personal transportation segment of general aviation, it has not gained complete acceptance. This is due, in part, to its high cost and the necessary special-handling air traffic control. VOR/DME RNAV calculations are ideally suited for analog computers, and the use of microprocessor technology has been suggested for reducing RNAV costs. Three navigation systems, VOR, Omega, and DR, are compared for common navigational difficulties, such as station geometry, siting errors, ground disturbances, and terminal area coverage. The Kalman filtering technique is described with reference to the disadvantages when using a system including standard microprocessors. An integrated navigation system, using input data from various low-cost sensor systems, is presented and current simulation studies are noted.

  5. Microprocessor tester for the treat upgrade reactor trip system

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Lenkszus, F.R.; Bucher, R.G.

    1984-01-01

    The upgrading of the Transient Reactor Test (TREAT) Facility at ANL-Idaho has been designed to provide additional experimental capabilities for the study of core disruptive accident (CDA) phenomena. In addition, a programmable Automated Reactor Control System (ARCS) will permit high-power transients up to 11,000 MW having a controlled reactor period of from 15 to 0.1 sec. These modifications to the core neutronics will improve simulation of LMFBR accident conditions. Finally, a sophisticated, multiply-redundant safety system, the Reactor Trip System (RTS), will provide safe operation for both steady state and transient production operating modes. To insure that this complex safety systemmore » is functioning properly, a Dedicated Microprocessor Tester (DMT) has been implemented to perform a thorough checkout of the RTS prior to all TREAT operations.« less

  6. Generic interpreters and microprocessor verification

    NASA Technical Reports Server (NTRS)

    Windley, Phillip J.

    1990-01-01

    The following topics are covered in viewgraph form: (1) generic interpreters; (2) Viper microprocessors; (3) microprocessor verification; (4) determining correctness; (5) hierarchical decomposition; (6) interpreter theory; (7) AVM-1; (8) phase-level specification; and future work.

  7. Microprocessor-based multichannel flutter monitor using dynamic strain gage signals

    NASA Technical Reports Server (NTRS)

    Smalley, R. R.

    1976-01-01

    Two microprocessor-based multichannel monitors for monitoring strain gage signals during aerodynamic instability (flutter) testing in production type turbojet engines were described. One system monitors strain gage signals in the time domain and gives an output indication whenever the signal amplitude of any gage exceeds a pre-set alarm or abort level for that particular gage. The second system monitors the strain gage signals in the frequency domain and therefore is able to use both the amplitude and frequency information. Thus, an alarm signal is given whenever the spectral content of the strain gage signal exceeds, at any point, its corresponding amplitude vs. frequency limit profiles. Each system design is described with details on design trade-offs, hardware, software, and operating experience.

  8. Application experience with the NASA aircraft interrogation and display system - A ground-support equipment for digital flight systems

    NASA Technical Reports Server (NTRS)

    Glover, R. D.

    1983-01-01

    The NASA Dryden Flight Research Facility has developed a microprocessor-based, user-programmable, general-purpose aircraft interrogation and display system (AIDS). The hardware and software of this ground-support equipment have been designed to permit diverse applications in support of aircraft digital flight-control systems and simulation facilities. AIDS is often employed to provide engineering-units display of internal digital system parameters during development and qualification testing. Such visibility into the system under test has proved to be a key element in the final qualification testing of aircraft digital flight-control systems. Three first-generation 8-bit units are now in service in support of several research aircraft projects, and user acceptance has been high. A second-generation design, extended AIDS (XAIDS), incorporating multiple 16-bit processors, is now being developed to support the forward swept wing aircraft project (X-29A). This paper outlines the AIDS concept, summarizes AIDS operational experience, and describes the planned XAIDS design and mechanization.

  9. 2nd Generation QUATARA Flight Computer Project

    NASA Technical Reports Server (NTRS)

    Falker, Jay; Keys, Andrew; Fraticelli, Jose Molina; Capo-Iugo, Pedro; Peeples, Steven

    2015-01-01

    Single core flight computer boards have been designed, developed, and tested (DD&T) to be flown in small satellites for the last few years. In this project, a prototype flight computer will be designed as a distributed multi-core system containing four microprocessors running code in parallel. This flight computer will be capable of performing multiple computationally intensive tasks such as processing digital and/or analog data, controlling actuator systems, managing cameras, operating robotic manipulators and transmitting/receiving from/to a ground station. In addition, this flight computer will be designed to be fault tolerant by creating both a robust physical hardware connection and by using a software voting scheme to determine the processor's performance. This voting scheme will leverage on the work done for the Space Launch System (SLS) flight software. The prototype flight computer will be constructed with Commercial Off-The-Shelf (COTS) components which are estimated to survive for two years in a low-Earth orbit.

  10. Microprocessor-controlled iontophoretic drug delivery of 5-fluorouracil: pharmacodynamic and pharmacokinetic study.

    PubMed

    Chandrashekar, N S; Shobha Rani, R H

    2007-01-01

    The purpose of this study was to fabricate monolithic 5-fluorouracil (5-FU) transdermal patch with microprocessor- controlled iontophoretic delivery, to evaluate the pharmacodynamic effects on Dalton's lymphoma ascites (DLA) induced in Balb/c mice, and to study pharmacokinetics in rabbits. The transdermal patches were prepared by solvent casting method; a reprogrammable microprocessor was developed and connected to the patches. DLA cells were injected to the hind limb of Balb/c mice (10 animals/group). In the first group of mice 5-FU was administered i.v. (12 mg/kg). In the second group of mice, transdermal patches (20 mg/patch/animal) were installed and kept for 10 consecutive days, while the third (control) group was kept without any treatment. The tumor diameter was measured every 5th day for 30 days, and the animal survival time and death pattern were studied. The electric current density protocol of 0.5 mA/cm(2) for 30 min was used in the pharmacokinetic study in rabbits. There was a significant reduction in tumor volume in the animals treated with monolithic matrix 5-FU transdermal patch compared to untreated controls and i.v. therapy. Tumor volume of the control animals was 5.8 cm(3) on the 30th day, while in 5-FU with transdermal patch delivery animals it was only 0.23 cm(3) (p <0.05). DLA cells tumor-bearing mice treated with 5-FU with transdermal patch had significantly increased lifespan (ILS). Control animals survived only 21+/-1 days after the tumor inoculation, while i.v. 5-FU and 5-FU patches animals survived 24+/-2.7 days and 39.5+/-1.87 days with ILS of 25.58% and 88.09%, respectively (p <0.01). There was significant sustained release of 5-FU through microprocessor-controlled patches and half-life was significantly higher (p <0.05) compared to the i.v. route. Cytotoxic concentration of 5-FU can be achieved through the transdermal drug delivery and effective therapeutic drug concentration can be maintained up to 24 h, with less toxicity. A new generation of transdermal drug delivery systems based on microprocessor-controlled iontophoresis is in the late stages of development and promises to enhance the treatment of local and systemic medical conditions. The incorporation of microprocessor into these systems has been an important advancement to ensure safe and efficient administration of a wide variety of drugs.

  11. Nuclear Science Symposium, 23rd, Scintillation and Semiconductor Counter Symposium, 15th, and Nuclear Power Systems Symposium, 8th, New Orleans, La., October 20-22, 1976, Proceedings

    NASA Technical Reports Server (NTRS)

    Wagner, L. J.

    1977-01-01

    The volume includes papers on semiconductor radiation detectors of various types, components of radiation detection and dosimetric systems, digital and microprocessor equipment in nuclear industry and science, and a wide variety of applications of nuclear radiation detectors. Semiconductor detectors of X-rays, gamma radiation, heavy ions, neutrons, and other nuclear particles, plastic scintillator arrays, drift chambers, spark wire chambers, and radiation dosimeter systems are reported on. Digital and analog conversion systems, digital data and control systems, microprocessors, and their uses in scientific research and nuclear power plants are discussed. Large-area imaging and biomedical nucleonic instrumentation, nuclear power plant safeguards, reactor instrumentation, nuclear power plant instrumentation, space instrumentation, and environmental instrumentation are dealt with. Individual items are announced in this issue.

  12. Microprocessor controlled portable TLD system

    NASA Technical Reports Server (NTRS)

    Apathy, I.; Deme, S.; Feher, I.

    1996-01-01

    An up-to-date microprocessor controlled thermoluminescence dosemeter (TLD) system for environmental and space dose measurements has been developed. The earlier version of the portable TLD system, Pille, was successfully used on Soviet orbital stations as well as on the US Space Shuttle, and for environmental monitoring. The new portable TLD system, Pille'95, consists of a reader and TL bulb dosemeters, and each dosemeter is provided with an EEPROM chip for automatic identification. The glow curve data are digitised and analysed by the program of the reader. The measured data and the identification number appear on the LED display of the reader. Up to several thousand measured data together with the glow curves can be stored on a removable flash memory card. The whole system is supplied either from built-in rechargeable batteries or from the mains of the space station.

  13. Progress on advanced dc and ac induction drives for electric vehicles

    NASA Technical Reports Server (NTRS)

    Schwartz, H. J.

    1982-01-01

    Progress is reported in the development of complete electric vehicle propulsion systems, and the results of tests on the Road Load Simulator of two such systems representative of advanced dc and ac drive technology are presented. One is the system used in the DOE's ETV-1 integrated test vehicle which consists of a shunt wound dc traction motor under microprocessor control using a transistorized controller. The motor drives the vehicle through a fixed ratio transmission. The second system uses an ac induction motor controlled by transistorized pulse width modulated inverter which drives through a two speed automatically shifted transmission. The inverter and transmission both operate under the control of a microprocessor. The characteristics of these systems are also compared with the propulsion system technology available in vehicles being manufactured at the inception of the DOE program and with an advanced, highly integrated propulsion system upon which technology development was recently initiated.

  14. Holo-Chidi video concentrator card

    NASA Astrophysics Data System (ADS)

    Nwodoh, Thomas A.; Prabhakar, Aditya; Benton, Stephen A.

    2001-12-01

    The Holo-Chidi Video Concentrator Card is a frame buffer for the Holo-Chidi holographic video processing system. Holo- Chidi is designed at the MIT Media Laboratory for real-time computation of computer generated holograms and the subsequent display of the holograms at video frame rates. The Holo-Chidi system is made of two sets of cards - the set of Processor cards and the set of Video Concentrator Cards (VCCs). The Processor cards are used for hologram computation, data archival/retrieval from a host system, and for higher-level control of the VCCs. The VCC formats computed holographic data from multiple hologram computing Processor cards, converting the digital data to analog form to feed the acousto-optic-modulators of the Media lab's Mark-II holographic display system. The Video Concentrator card is made of: a High-Speed I/O (HSIO) interface whence data is transferred from the hologram computing Processor cards, a set of FIFOs and video RAM used as buffer for data for the hololines being displayed, a one-chip integrated microprocessor and peripheral combination that handles communication with other VCCs and furnishes the card with a USB port, a co-processor which controls display data formatting, and D-to-A converters that convert digital fringes to analog form. The co-processor is implemented with an SRAM-based FPGA with over 500,000 gates and controls all the signals needed to format the data from the multiple Processor cards into the format required by Mark-II. A VCC has three HSIO ports through which up to 500 Megabytes of computed holographic data can flow from the Processor Cards to the VCC per second. A Holo-Chidi system with three VCCs has enough frame buffering capacity to hold up to thirty two 36Megabyte hologram frames at a time. Pre-computed holograms may also be loaded into the VCC from a host computer through the low- speed USB port. Both the microprocessor and the co- processor in the VCC can access the main system memory used to store control programs and data for the VCC. The Card also generates the control signals used by the scanning mirrors of Mark-II. In this paper we discuss the design of the VCC and its implementation in the Holo-Chidi system.

  15. Soft control of scanning probe microscope with high flexibility.

    PubMed

    Liu, Zhenghui; Guo, Yuzheng; Zhang, Zhaohui; Zhu, Xing

    2007-01-01

    Most commercial scanning probe microscopes have multiple embedded digital microprocessors and utilize complex software for system control, which is not easily obtained or modified by researchers wishing to perform novel and special applications. In this paper, we present a simple and flexible control solution that just depends on software running on a single-processor personal computer with real-time Linux operating system to carry out all the control tasks including negative feedback, tip moving, data processing and user interface. In this way, we fully exploit the potential of a personal computer in calculating and programming, enabling us to manipulate the scanning probe as required without any special digital control circuits and related technical know-how. This solution has been successfully applied to a homemade ultrahigh vacuum scanning tunneling microscope and a multiprobe scanning tunneling microscope.

  16. The revolution in data gathering systems. [mini and microcomputers in NASA wind tunnels

    NASA Technical Reports Server (NTRS)

    Cambra, J. M.; Trover, W. F.

    1975-01-01

    This paper gives a review of the data-acquisition systems used in NASA's wind tunnels from the 1950's to the present as a basis for assessing the impact of minicomputers and microcomputers on data acquisition and processing. The operation and disadvantages of wind-tunnel data systems are summarized for the period before 1950, the early 1950's, the early and late 1960's, and the early 1970's. Some significant advances discussed include the use or development of solid-state components, minicomputer systems, large central computers, on-line data processing, autoranging DC amplifiers, MOS-FET multiplexers, MSI and LSI logic, computer-controlled programmable amplifiers, solid-state remote multiplexing, integrated circuits, and microprocessors. The distributed system currently in use with the 40-ft by 80-ft wind tunnel at Ames Research Center is described in detail. The expected employment of distributed systems and microprocessors in the next decade is noted.

  17. Fiber optic, Fabry-Perot high temperature sensor

    NASA Technical Reports Server (NTRS)

    James, K.; Quick, B.

    1984-01-01

    A digital, fiber optic temperature sensor using a variable Fabry-Perot cavity as the sensor element was analyzed, designed, fabricated, and tested. The fiber transmitted cavity reflection spectra is dispersed then converted from an optical signal to electrical information by a charged coupled device (CCD). A microprocessor-based color demodulation system converts the wavelength information to temperature. This general sensor concept not only utilizes an all-optical means of parameter sensing and transmitting, but also exploits microprocessor technology for automated control, calibration, and enhanced performance. The complete temperature sensor system was evaluated in the laboratory. Results show that the Fabry-Perot temperature sensor has good resolution (0.5% of full seale), high accuracy, and potential high temperature ( 1000 C) applications.

  18. Arranging computer architectures to create higher-performance controllers

    NASA Technical Reports Server (NTRS)

    Jacklin, Stephen A.

    1988-01-01

    Techniques for integrating microprocessors, array processors, and other intelligent devices in control systems are reviewed, with an emphasis on the (re)arrangement of components to form distributed or parallel processing systems. Consideration is given to the selection of the host microprocessor, increasing the power and/or memory capacity of the host, multitasking software for the host, array processors to reduce computation time, the allocation of real-time and non-real-time events to different computer subsystems, intelligent devices to share the computational burden for real-time events, and intelligent interfaces to increase communication speeds. The case of a helicopter vibration-suppression and stabilization controller is analyzed as an example, and significant improvements in computation and throughput rates are demonstrated.

  19. A microprocessor based anti-aliasing filter for a PCM system

    NASA Technical Reports Server (NTRS)

    Morrow, D. C.; Sandlin, D. R.

    1984-01-01

    Described is the design and evaluation of a microprocessor based digital filter. The filter was made to investigate the feasibility of a digital replacement for the analog pre-sampling filters used in telemetry systems at the NASA Ames-Dryden Flight Research Facility (DFRF). The digital filter will utilize an Intel 2920 Analog Signal Processor (ASP) chip. Testing includes measurements of: (1) the filter frequency response and, (2) the filter signal resolution. The evaluation of the digital filter was made on the basis of circuit size, projected environmental stability and filter resolution. The 2920 based digital filter was found to meet or exceed the pre-sampling filter specifications for limited signal resolution applications.

  20. Application of digital control to a magnetic model suspension and balance model

    NASA Technical Reports Server (NTRS)

    Luh, P. B.; Covert, E. E.; Whitaker, H. P.; Haldeman, C. W.

    1978-01-01

    The feasibility of using a digital computer for performing the automatic control functions for a magnetic suspension and balance system (MSBS) for use with wind tunnel models was investigated. Modeling was done using both a prototype MSBS and a one dimensional magnetic balance. A microcomputer using the Intel 8080 microprocessor is described and results are given using this microprocessor to control the one dimensional balance. Hybrid simulations for one degree of freedom of the MSBS were also performed and are reported. It is concluded that use of a digital computer to control the MSBS is eminently feasible and should extend both the accuracy and utility of the system.

  1. A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor

    PubMed Central

    González, Diego; Botella, Guillermo; Meyer-Baese, Uwe; García, Carlos; Sanz, Concepción; Prieto-Matías, Manuel; Tirado, Francisco

    2012-01-01

    This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system. PMID:23201989

  2. Single event effect testing of the Intel 80386 family and the 80486 microprocessor

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Moran, A.; LaBel, K.; Gates, M.

    The authors present single event effect test results for the Intel 80386 microprocessor, the 80387 coprocessor, the 82380 peripheral device, and on the 80486 microprocessor. Both single event upset and latchup conditions were monitored.

  3. Microprocessors and the Curriculum.

    ERIC Educational Resources Information Center

    Pasahow, Edward J.

    1981-01-01

    Presents three approaches to teaching the use of a microprocessor: (1) a "generic" device on paper; (2) a "conglomeration" device, surveying a number of real products; and (3) the "how" course which covers a small number of actual but related microprocessors. (CT)

  4. Software resilience and the effectiveness of software mitigation in microcontrollers

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Quinn, Heather; Baker, Zachary; Fairbanks, Tom

    Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

  5. Software resilience and the effectiveness of software mitigation in microcontrollers

    DOE PAGES

    Quinn, Heather; Baker, Zachary; Fairbanks, Tom; ...

    2015-12-01

    Commercially available microprocessors could be useful to the space community for noncritical computations. There are many possible components that are smaller, lower-power, and less expensive than traditional radiation-hardened microprocessors. Many commercial microprocessors have issues with single-event effects (SEEs), such as single-event upsets (SEUs) and single-event transients (SETs), that can cause the microprocessor to calculate an incorrect result or crash. In this paper we present the Trikaya technique for masking SEUs and SETs through software mitigation techniques. Furthermore, test results show that this technique can be very effective at masking errors, making it possible to fly these microprocessors for a varietymore » of missions.« less

  6. Full Duplex, Spread Spectrum Radio System

    NASA Technical Reports Server (NTRS)

    Harvey, Bruce A.

    2000-01-01

    The goal of this project was to support the development of a full duplex, spread spectrum voice communications system. The assembly and testing of a prototype system consisting of a Harris PRISM spread spectrum radio, a TMS320C54x signal processing development board and a Zilog Z80180 microprocessor was underway at the start of this project. The efforts under this project were the development of multiple access schemes, analysis of full duplex voice feedback delays, and the development and analysis of forward error correction (FEC) algorithms. The multiple access analysis involved the selection between code division multiple access (CDMA), frequency division multiple access (FDMA) and time division multiple access (TDMA). Full duplex voice feedback analysis involved the analysis of packet size and delays associated with full loop voice feedback for confirmation of radio system performance. FEC analysis included studies of the performance under the expected burst error scenario with the relatively short packet lengths, and analysis of implementation in the TMS320C54x digital signal processor. When the capabilities and the limitations of the components used were considered, the multiple access scheme chosen was a combination TDMA/FDMA scheme that will provide up to eight users on each of three separate frequencies. Packets to and from each user will consist of 16 samples at a rate of 8,000 samples per second for a total of 2 ms of voice information. The resulting voice feedback delay will therefore be 4 - 6 ms. The most practical FEC algorithm for implementation was a convolutional code with a Viterbi decoder. Interleaving of the bits of each packet will be required to offset the effects of burst errors.

  7. Verification of the FtCayuga fault-tolerant microprocessor system. Volume 1: A case study in theorem prover-based verification

    NASA Technical Reports Server (NTRS)

    Srivas, Mandayam; Bickford, Mark

    1991-01-01

    The design and formal verification of a hardware system for a task that is an important component of a fault tolerant computer architecture for flight control systems is presented. The hardware system implements an algorithm for obtaining interactive consistancy (byzantine agreement) among four microprocessors as a special instruction on the processors. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, provided certain preconditions hold. An assumption is made that the processors execute synchronously. For verification, the authors used a computer aided design hardware design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

  8. Verification of the FtCayuga fault-tolerant microprocessor system. Volume 2: Formal specification and correctness theorems

    NASA Technical Reports Server (NTRS)

    Bickford, Mark; Srivas, Mandayam

    1991-01-01

    Presented here is a formal specification and verification of a property of a quadruplicately redundant fault tolerant microprocessor system design. A complete listing of the formal specification of the system and the correctness theorems that are proved are given. The system performs the task of obtaining interactive consistency among the processors using a special instruction on the processors. The design is based on an algorithm proposed by Pease, Shostak, and Lamport. The property verified insures that an execution of the special instruction by the processors correctly accomplishes interactive consistency, providing certain preconditions hold, using a computer aided design verification tool, Spectool, and the theorem prover, Clio. A major contribution of the work is the demonstration of a significant fault tolerant hardware design that is mechanically verified by a theorem prover.

  9. An active drop counting device using condenser microphone for superheated emulsion detector

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Das, Mala; Marick, C.; Kanjilal, D.

    2008-11-15

    An active device for superheated emulsion detector is described. A capacitive diaphragm sensor or condenser microphone is used to convert the acoustic pulse of drop nucleation to electrical signal. An active peak detector is included in the circuit to avoid multiple triggering of the counter. The counts are finally recorded by a microprocessor based data acquisition system. Genuine triggers, missed by the sensor, were studied using a simulated clock pulse. The neutron energy spectrum of {sup 252}Cf fission neutron source was measured using the device with R114 as the sensitive liquid and compared with the calculated fission neutron energy spectrummore » of {sup 252}Cf. Frequency analysis of the detected signals was also carried out.« less

  10. An active drop counting device using condenser microphone for superheated emulsion detector

    NASA Astrophysics Data System (ADS)

    Das, Mala; Arya, A. S.; Marick, C.; Kanjilal, D.; Saha, S.

    2008-11-01

    An active device for superheated emulsion detector is described. A capacitive diaphragm sensor or condenser microphone is used to convert the acoustic pulse of drop nucleation to electrical signal. An active peak detector is included in the circuit to avoid multiple triggering of the counter. The counts are finally recorded by a microprocessor based data acquisition system. Genuine triggers, missed by the sensor, were studied using a simulated clock pulse. The neutron energy spectrum of C252f fission neutron source was measured using the device with R114 as the sensitive liquid and compared with the calculated fission neutron energy spectrum of C252f. Frequency analysis of the detected signals was also carried out.

  11. [Extension of cardiac monitoring function by used of ordinary ECG machine].

    PubMed

    Chen, Zhencheng; Jiang, Yong; Ni, Lili; Wang, Hongyan

    2002-06-01

    This paper deals with a portable monitor system on liquid crystal display (LCD) based on this available ordinary ECG machine, which is low power and suitable for China's specific condition. Apart from developing the overall scheme of the system, this paper also has completed the design of the hardware and the software. The 80c196 single chip microcomputer is taken as the central microprocessor and real time electrocardiac single is data treated and analyzed in the system. With the performance of ordinary monitor, this machine also possesses the following functions: five types of arrhythmia analysis, alarm, freeze, and record of automatic pappering, convenient in carrying, with alternate-current (AC) or direct-current (DC) powered. The hardware circuit is simplified and the software structure is optimized in this paper. Multiple low power designs and LCD unit design are adopted and completed in it. Popular in usage, low in cost price, the portable monitor system will have a valuable influence on China's monitor system field.

  12. Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

    NASA Technical Reports Server (NTRS)

    Carson, John C. (Inventor); Indin, Ronald J. (Inventor); Shanken, Stuart N. (Inventor)

    1994-01-01

    A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

  13. Benchmark tests on the digital equipment corporation Alpha AXP 21164-based AlphaServer 8400, including a comparison of optimized vector and superscalar processing

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Wasserman, H.J.

    1996-02-01

    The second generation of the Digital Equipment Corp. (DEC) DECchip Alpha AXP microprocessor is referred to as the 21164. From the viewpoint of numerically-intensive computing, the primary difference between it and its predecessor, the 21064, is that the 21164 has twice the multiply/add throughput per clock period (CP), a maximum of two floating point operations (FLOPS) per CP vs. one for 21064. The AlphaServer 8400 is a shared-memory multiprocessor server system that can accommodate up to 12 CPUs and up to 14 GB of memory. In this report we will compare single processor performance of the 8400 system with thatmore » of the International Business Machines Corp. (IBM) RISC System/6000 POWER-2 microprocessor running at 66 MHz, the Silicon Graphics, Inc. (SGI) MIPS R8000 microprocessor running at 75 MHz, and the Cray Research, Inc. CRAY J90. The performance comparison is based on a set of Fortran benchmark codes that represent a portion of the Los Alamos National Laboratory supercomputer workload. The advantage of using these codes, is that the codes also span a wide range of computational characteristics, such as vectorizability, problem size, and memory access pattern. The primary disadvantage of using them is that detailed, quantitative analysis of performance behavior of all codes on all machines is difficult. One important addition to the benchmark set appears for the first time in this report. Whereas the older version was written for a vector processor, the newer version is more optimized for microprocessor architectures. Therefore, we have for the first time, an opportunity to measure performance on a single application using implementations that expose the respective strengths of vector and superscalar architecture. All results in this report are from single processors. A subsequent article will explore shared-memory multiprocessing performance of the 8400 system.« less

  14. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Gebis, Joseph; Oliker, Leonid; Shalf, John

    The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software controlled scratchpad memories, such as the Cell local store, attempt to ameliorate this discrepancy by enabling precise control over memory movement; however, scratchpad technology confronts the programmer and compiler with an unfamiliar and difficult programming model. In this work, we present the Virtual Vector Architecture (ViVA), which combines the memory semantics of vector computers with a software-controlled scratchpad memory in order to provide a more effective and practical approach to latency hiding. ViVA requires minimal changesmore » to the core design and could thus be easily integrated with conventional processor cores. To validate our approach, we implemented ViVA on the Mambo cycle-accurate full system simulator, which was carefully calibrated to match the performance on our underlying PowerPC Apple G5 architecture. Results show that ViVA is able to deliver significant performance benefits over scalar techniques for a variety of memory access patterns as well as two important memory-bound compact kernels, corner turn and sparse matrix-vector multiplication -- achieving 2x-13x improvement compared the scalar version. Overall, our preliminary ViVA exploration points to a promising approach for improving application performance on leading microprocessors with minimal design and complexity costs, in a power efficient manner.« less

  15. Microprocessor Seminar, phase 2

    NASA Technical Reports Server (NTRS)

    Scott, W. R.

    1977-01-01

    Workshop sessions and papers were devoted to various aspects of microprocessor and large scale integrated circuit technology. Presentations were made on advanced LSI developments for high reliability military and NASA applications. Microprocessor testing techniques were discussed, and test data were presented. High reliability procurement specifications were also discussed.

  16. Operational experience on the MP-200 series commercial wind turbine generators

    NASA Technical Reports Server (NTRS)

    Rose, M. B.

    1982-01-01

    The MP-200 wind turbine generator is described. The mechanical system, microprocessor controller, and display devices, are described. Also discussed are modifications to the prototype, operational experience, and MP-600 systems development.

  17. 78 FR 3449 - Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements...

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-01-16

    ... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-781] Certain Microprocessors, Components Thereof, and Products Containing Same; Request for Statements on the Public Interest AGENCY: U.S... a limited exclusion order as to subject Intel microprocessors, but that implementation be delayed...

  18. Information Technologies for the 1980's: Lasers and Microprocessors.

    ERIC Educational Resources Information Center

    Mathews, William D.

    This discussion of the development and application of lasers and microprocessors to information processing stresses laser communication in relation to capacity, reliability, and cost and the advantages of this technology to real-time information access and information storage. The increased capabilities of microprocessors are reviewed, and a…

  19. Gallium-arsenide process evaluation based on a RISC microprocessor example

    NASA Astrophysics Data System (ADS)

    Brown, Richard B.; Upton, Michael; Chandna, Ajay; Huff, Thomas R.; Mudge, Trevor N.; Oettel, Richard E.

    1993-10-01

    This work evaluates the features of a gallium-arsenide E/D MESFET process in which a 32-b RISC microprocessor was implemented. The design methodology and architecture of this prototype CPU are described. The performance sensitivity of the microprocessor and other large circuit blocks to different process parameters is analyzed, and recommendations for future process features, circuit approaches, and layout styles are made. These recommendations are reflected in the design of a second microprocessor using a more advanced process that achieves much higher density and performance.

  20. Integrally regulated solar array demonstration using an Intel 8080 microprocessor

    NASA Technical Reports Server (NTRS)

    Petrik, E. J.

    1977-01-01

    A concept for regulating the voltage of a solar array by using a microprocessor to effect discrete voltage changes was demonstrated. Eight shorting switches were employed to regulate a simulated array at set-point voltages between 10,000 and 15,000 volts. The demonstration showed that the microprocessor easily regulated the solar array output voltage independently of whether or not the switched cell groups were binary sized in voltage. In addition, the microprocessor provided logic memory capability to perform additional tasks such as locating and insolating a faulty switch.

  1. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  2. Genomic analysis suggests that mRNA destabilization by the microprocessor is specialized for the auto-regulation of Dgcr8.

    PubMed

    Shenoy, Archana; Blelloch, Robert

    2009-09-11

    The Microprocessor, containing the RNA binding protein Dgcr8 and RNase III enzyme Drosha, is responsible for processing primary microRNAs to precursor microRNAs. The Microprocessor regulates its own levels by cleaving hairpins in the 5'UTR and coding region of the Dgcr8 mRNA, thereby destabilizing the mature transcript. To determine whether the Microprocessor has a broader role in directly regulating other coding mRNA levels, we integrated results from expression profiling and ultra high-throughput deep sequencing of small RNAs. Expression analysis of mRNAs in wild-type, Dgcr8 knockout, and Dicer knockout mouse embryonic stem (ES) cells uncovered mRNAs that were specifically upregulated in the Dgcr8 null background. A number of these transcripts had evolutionarily conserved predicted hairpin targets for the Microprocessor. However, analysis of deep sequencing data of 18 to 200nt small RNAs in mouse ES, HeLa, and HepG2 indicates that exonic sequence reads that map in a pattern consistent with Microprocessor activity are unique to Dgcr8. We conclude that the Microprocessor's role in directly destabilizing coding mRNAs is likely specifically targeted to Dgcr8 itself, suggesting a specialized cellular mechanism for gene auto-regulation.

  3. Performance, operational limits, of an Electronic Switching Spherical Array (ESSA) antenna

    NASA Technical Reports Server (NTRS)

    Stockton, R.

    1979-01-01

    The development of a microprocessor controller which provides multimode operational capability for the Electronic Switching Spherical Array (ESSA) Antenna is described. The best set of operating conditions were determined and the performance of an ESSA antenna was demonstrated in the following modes: (1) omni; (2) acquisition/track; (3) directive; and (4) multibeam. The control algorithms, software flow diagrams, and electronic circuitry were developed. The microprocessor and control electronics were built and interfaced with the antenna to carry out performance testing. The acquisition/track mode for users in the Tracking and Data Relay Satellite System is emphasized.

  4. Microprocessor-controlled laser tracker for atmospheric sensing

    NASA Technical Reports Server (NTRS)

    Johnson, R. A.; Webster, C. R.; Menzies, R. T.

    1985-01-01

    An optical tracking system comprising a visible HeNe laser, an imaging detector, and a microprocessor-controlled mirror, has been designed to track a moving retroreflector located up to 500 m away from an atmospheric instrument and simultaneously direct spectrally tunable infrared laser radiation to the retroreflector for double-ended, long-path absorption measurements of atmospheric species. The tracker has been tested during the recent flight of a balloon-borne tunable diode laser absorption spectrometer which monitors the concentrations of stratospheric species within a volume defined by a 0.14-m-diameter retroreflector lowered 500 m below the instrument gondola.

  5. Deployment of Shaped Charges by a Semi-Autonomous Ground Vehicle

    DTIC Science & Technology

    2007-06-01

    lives on a daily basis. BigFoot seeks to replace the local human component by deploying and remotely detonating shaped charges to destroy IEDs...robotic arm to deploy and remotely detonate shaped charges. BigFoot incorporates improved communication range over previous Autonomous Ground Vehicles...and an updated user interface that includes controls for the arm and camera by interfacing multiple microprocessors. BigFoot is capable of avoiding

  6. Utilization of Educationally Oriented Microcomputer Based Laboratories

    ERIC Educational Resources Information Center

    Fitzpatrick, Michael J.; Howard, James A.

    1977-01-01

    Describes one approach to supplying engineering and computer science educators with an economical portable digital systems laboratory centered around microprocessors. Expansion of the microcomputer based laboratory concept to include Learning Resource Aided Instruction (LRAI) systems is explored. (Author)

  7. On-board landmark navigation and attitude reference parallel processor system

    NASA Technical Reports Server (NTRS)

    Gilbert, L. E.; Mahajan, D. T.

    1978-01-01

    An approach to autonomous navigation and attitude reference for earth observing spacecraft is described along with the landmark identification technique based on a sequential similarity detection algorithm (SSDA). Laboratory experiments undertaken to determine if better than one pixel accuracy in registration can be achieved consistent with onboard processor timing and capacity constraints are included. The SSDA is implemented using a multi-microprocessor system including synchronization logic and chip library. The data is processed in parallel stages, effectively reducing the time to match the small known image within a larger image as seen by the onboard image system. Shared memory is incorporated in the system to help communicate intermediate results among microprocessors. The functions include finding mean values and summation of absolute differences over the image search area. The hardware is a low power, compact unit suitable to onboard application with the flexibility to provide for different parameters depending upon the environment.

  8. Data and results of a laboratory investigation of microprocessor upset caused by simulated lightning-induced analog transients

    NASA Technical Reports Server (NTRS)

    Belcastro, C. M.

    1984-01-01

    Advanced composite aircraft designs include fault-tolerant computer-based digital control systems with thigh reliability requirements for adverse as well as optimum operating environments. Since aircraft penetrate intense electromagnetic fields during thunderstorms, onboard computer systems maya be subjected to field-induced transient voltages and currents resulting in functional error modes which are collectively referred to as digital system upset. A methodology was developed for assessing the upset susceptibility of a computer system onboard an aircraft flying through a lightning environment. Upset error modes in a general-purpose microprocessor were studied via tests which involved the random input of analog transients which model lightning-induced signals onto interface lines of an 8080-based microcomputer from which upset error data were recorded. The application of Markov modeling to upset susceptibility estimation is discussed and a stochastic model development.

  9. FAME, a microprocessor based front-end analysis and modeling environment

    NASA Technical Reports Server (NTRS)

    Rosenbaum, J. D.; Kutin, E. B.

    1980-01-01

    Higher order software (HOS) is a methodology for the specification and verification of large scale, complex, real time systems. The HOS methodology was implemented as FAME (front end analysis and modeling environment), a microprocessor based system for interactively developing, analyzing, and displaying system models in a low cost user-friendly environment. The nature of the model is such that when completed it can be the basis for projection to a variety of forms such as structured design diagrams, Petri-nets, data flow diagrams, and PSL/PSA source code. The user's interface with the analyzer is easily recognized by any current user of a structured modeling approach; therefore extensive training is unnecessary. Furthermore, when all the system capabilities are used one can check on proper usage of data types, functions, and control structures thereby adding a new dimension to the design process that will lead to better and more easily verified software designs.

  10. Investigation of new techniques for aircraft navigation using the omega navigation

    NASA Technical Reports Server (NTRS)

    Baxa, E. G., Jr.

    1978-01-01

    An OMEGA navigation receiver with a microprocessor as the computational component was investigated. A version of the INTEL 4004 microprocessor macroassembler suitable for use on the CDC-6600 system and development of a FORTRAN IV simulator program for the microprocessor was developed. Supporting studies included development and evaluation of navigation algorithms to generate relative position information from OMEGA VLF phase measurements. Simulation studies were used to evaluate assumptions made in developing a navigation equation in OMEGA Line of Position (LOP) coordinates. Included in the navigation algorithms was a procedure for calculating a position in latitude/longitude given an OMEGA LOP fix. Implementation of a digital phase locked loop (DPLL) was evaluated on the basic of phase response characteristics over a range of input phase variations. Included also is an analytical evaluation on the basis of error probability of an algorithm for automatic time synchronization of the receiver to the OMEGA broadcast format. The use of actual OMEGA phase data and published propagation prediction corrections to determine phase velocity estimates was discussed.

  11. MICROPROCESSOR-BASED DATA-ACQUISITION SYSTEM FOR A BOREHOLE RADAR.

    USGS Publications Warehouse

    Bradley, Jerry A.; Wright, David L.

    1987-01-01

    An efficient microprocessor-based system is described that permits real-time acquisition, stacking, and digital recording of data generated by a borehole radar system. Although the system digitizes, stacks, and records independently of a computer, it is interfaced to a desktop computer for program control over system parameters such as sampling interval, number of samples, number of times the data are stacked prior to recording on nine-track tape, and for graphics display of the digitized data. The data can be transferred to the desktop computer during recording, or it can be played back from a tape at a latter time. Using the desktop computer, the operator observes results while recording data and generates hard-copy graphics in the field. Thus, the radar operator can immediately evaluate the quality of data being obtained, modify system parameters, study the radar logs before leaving the field, and rerun borehole logs if necessary. The system has proven to be reliable in the field and has increased productivity both in the field and in the laboratory.

  12. A monitoring system for vegetable greenhouses based on a wireless sensor network.

    PubMed

    Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

    2010-01-01

    A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring.

  13. A long-range and long-life telemetry data-acquisition system for heart rate and multiple body temperatures from free-ranging animals

    NASA Technical Reports Server (NTRS)

    Lund, G. F.; Westbrook, R. M.; Fryer, T. B.; Miranda, R. F.

    1979-01-01

    The system includes an implantable transmitter, external receiver-retransmitter collar, and a microprocessor-controlled demodulator. The size of the implant is suitable for animals with body weights of a few kilograms or more; further size reduction of the implant is possible. The ECG is sensed by electrodes designed for internal telemetry and to reduce movement artifacts. The R-wave characteristics are then specifically selected to trigger a short radio frequency pulse. Temperatures are sensed at desired locations by thermistors and then, based on a heartbeat counter, transmitted intermittently via pulse interval modulation. This modulation scheme includes first and last calibration intervals for a reference by ratios with the temperature intervals to achieve good accuracy even over long periods. Pulse duration and pulse sequencing are used to discriminate between heart rate and temperature pulses as well as RF interference.

  14. Development of an Automated Emergency Response System (AERS) for Rail Transit Systems

    DOT National Transportation Integrated Search

    1984-10-01

    As a result of a fire in 1979 at the Bay Area Rapid Transit District (BART), a microprocessor-based information retrieval system was developed to aid in the emergency decision-making process. This system was proposed, designed and programmed by a sup...

  15. Commercial Parts Radiation Testing

    DTIC Science & Technology

    2015-01-13

    New Mexico’s COSMIAC Center performed radiation testing on a series of operational amplifiers, microcontrollers and microprocessor. The...commercial microcontroller and microprocessor equipment. The team would develop a list of the most promising commercial parts that might be utilized to...parts will include microprocessors, microcontrollers and memory modules. In addition, Field Programmable Gate Arrays (FPGAs) will also be chosen

  16. Microprocessors: An Understandable Guide for the Classroom Teacher.

    ERIC Educational Resources Information Center

    Okinaka, Russell T.

    A microprocessor constitutes the heart and soul of a personal computer. Indeed, the quality of a personal computer is determined largely by the type of microprocessor that is included within its circuitry. Since the microcomputer revolution began in the late 1970s, these special chips have gone through a series of improvements and modifications.…

  17. Cellular functions of the microprocessor.

    PubMed

    Macias, Sara; Cordiner, Ross A; Cáceres, Javier F

    2013-08-01

    The microprocessor is a complex comprising the RNase III enzyme Drosha and the double-stranded RNA-binding protein DGCR8 (DiGeorge syndrome critical region 8 gene) that catalyses the nuclear step of miRNA (microRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as an endonuclease. Recent global analyses of microprocessor and Dicer proteins have suggested novel functions for these components independent of their role in miRNA biogenesis. A HITS-CLIP (high-throughput sequencing of RNA isolated by cross-linking immunoprecipitation) experiment designed to identify novel substrates of the microprocessor revealed that this complex binds and regulates a large variety of cellular RNAs. The microprocessor-mediated cleavage of several classes of RNAs not only regulates transcript levels, but also modulates alternative splicing events, independently of miRNA function. Importantly, DGCR8 can also associate with other nucleases, suggesting the existence of alternative DGCR8 complexes that may regulate the fate of a subset of cellular RNAs. The aim of the present review is to provide an overview of the diverse functional roles of the microprocessor.

  18. Transcription of the Workshop on General Aviation Advanced Avionics Systems

    NASA Technical Reports Server (NTRS)

    Tashker, M. (Editor)

    1975-01-01

    Papers are presented dealing with the design of reliable, low cost, advanced avionics systems applicable to general aviation in the 1980's and beyond. Sensors, displays, integrated circuits, microprocessors, and minicomputers are among the topics discussed.

  19. The Blind, From Braille to the Present.

    ERIC Educational Resources Information Center

    Truquet, Monique

    1980-01-01

    Traces the historical development of processing information for the blind from the system devised by Barbier to present systems of producing Braille documents using computers. Cites the impact of microprocessors and outlines possibilities for Braille reproductions in the future. (GS)

  20. Talking Fire Alarms Calm Kids.

    ERIC Educational Resources Information Center

    Executive Educator, 1984

    1984-01-01

    The new microprocessor-based fire alarm systems can help to control smoke movement throughout school buildings by opening vents and doors, identify the burning section, activate voice alarms, provide firefighters with telephone systems during the fire, and release fire-preventing gas. (KS)

  1. DESIGN, DEVELOPMENT, AND FIELD DEMONSTRATION OF A REMOTELY DEPLOYABLE WATER QUALITY MONITORING SYSTEM

    EPA Science Inventory

    A prototype water quality monitoring system is described which offers almost continuous in situ monitoring. The two-man portable system features: (1) a microprocessor controlled central processing unit which allows preprogrammed sampling schedules and reprogramming in situ; (2) a...

  2. Microprocessor control and networking for the amps breadboard

    NASA Technical Reports Server (NTRS)

    Floyd, Stephen A.

    1987-01-01

    Future space missions will require more sophisticated power systems, implying higher costs and more extensive crew and ground support involvement. To decrease this human involvement, as well as to protect and most efficiently utilize this important resource, NASA has undertaken major efforts to promote progress in the design and development of autonomously managed power systems. Two areas being actively pursued are autonomous power system (APS) breadboards and knowledge-based expert system (KBES) applications. The former are viewed as a requirement for the timely development of the latter. Not only will they serve as final testbeds for the various KBES applications, but will play a major role in the knowledge engineering phase of their development. The current power system breadboard designs are of a distributed microprocessor nature. The distributed nature, plus the need to connect various external computer capabilities (i.e., conventional host computers and symbolic processors), places major emphasis on effective networking. The communications and networking technologies for the first power system breadboard/test facility are described.

  3. Report on the formal specification and partial verification of the VIPER microprocessor

    NASA Technical Reports Server (NTRS)

    Brock, Bishop; Hunt, Warren A., Jr.

    1991-01-01

    The formal specification and partial verification of the VIPER microprocessor is reviewed. The VIPER microprocessor was designed by RSRE, Malvern, England, for safety critical computing applications (e.g., aircraft, reactor control, medical instruments, armaments). The VIPER was carefully specified and partially verified in an attempt to provide a microprocessor with completely predictable operating characteristics. The specification of VIPER is divided into several levels of abstraction, from a gate-level description up to an instruction execution model. Although the consistency between certain levels was demonstrated with mechanically-assisted mathematical proof, the formal verification of VIPER was never completed.

  4. A lightweight security scheme for wireless body area networks: design, energy evaluation and proposed microprocessor design.

    PubMed

    Selimis, Georgios; Huang, Li; Massé, Fabien; Tsekoura, Ioanna; Ashouei, Maryam; Catthoor, Francky; Huisken, Jos; Stuyt, Jan; Dolmans, Guido; Penders, Julien; De Groot, Harmke

    2011-10-01

    In order for wireless body area networks to meet widespread adoption, a number of security implications must be explored to promote and maintain fundamental medical ethical principles and social expectations. As a result, integration of security functionality to sensor nodes is required. Integrating security functionality to a wireless sensor node increases the size of the stored software program in program memory, the required time that the sensor's microprocessor needs to process the data and the wireless network traffic which is exchanged among sensors. This security overhead has dominant impact on the energy dissipation which is strongly related to the lifetime of the sensor, a critical aspect in wireless sensor network (WSN) technology. Strict definition of the security functionality, complete hardware model (microprocessor and radio), WBAN topology and the structure of the medium access control (MAC) frame are required for an accurate estimation of the energy that security introduces into the WBAN. In this work, we define a lightweight security scheme for WBAN, we estimate the additional energy consumption that the security scheme introduces to WBAN based on commercial available off-the-shelf hardware components (microprocessor and radio), the network topology and the MAC frame. Furthermore, we propose a new microcontroller design in order to reduce the energy consumption of the system. Experimental results and comparisons with other works are given.

  5. [Multimag-M magnetotherapy system of the new generation].

    PubMed

    Borisov, A G; Grigor'ev, E M; Gurzhin, S G; Zhulev, V I; Kriakov, V G; Proshin, E M

    2007-01-01

    The Multimag-M microprocessor chronomagne-totherapy system of the new generation is described. The system provides on-line diagnosis of the pulse parameters and the breathing rate during a biotechnical feedback session. The requirements to the system software, as well as its specific features and design principles, are considered.

  6. A microarchitecture for resource-limited superscalar microprocessors

    NASA Astrophysics Data System (ADS)

    Basso, Todd David

    1999-11-01

    Microelectronic components in space and satellite systems must be resistant to total dose radiation, single-even upset, and latchup in order to accomplish their missions. The demand for inexpensive, high-volume, radiation hardened (rad-hard) integrated circuits (ICs) is expected to increase dramatically as the communication market continues to expand. Motorola's Complementary Gallium Arsenide (CGaAsTM) technology offers superior radiation tolerance compared to traditional CMOS processes, while being more economical than dedicated rad-hard CMOS processes. The goals of this dissertation are to optimize a superscalar microarchitecture suitable for CGaAsTM microprocessors, develop circuit techniques for such applications, and evaluate the potential of CGaAsTM for the development of digital VLSI circuits. Motorola's 0.5 mum CGaAsTM process is summarized and circuit techniques applicable to digital CGaAsTM are developed. Direct coupled FET, complementary, and domino logic circuits are compared based on speed, power, area, and noise margins. These circuit techniques are employed in the design of a 600 MHz PowerPCTM arithmetic logic unit. The dissertation emphasizes CGaASTM-specific design considerations, specifically, low integration level. A baseline superscalar microarchitecture is defined and SPEC95 integer benchmark simulations are used to evaluate the applicability of advanced architectural features to microprocessors having low integration levels. The performance simulations center around the optimization of a simple superscalar core, small-scale branch prediction, instruction prefetching, and an off-chip primary data cache. The simulation results are used to develop a superscalar microarchitecture capable of outperforming a comparable sequential pipeline, while using only 500,000 transistors. The architecture, running at 200 MHz, is capable of achieving an estimated 153 MIPS, translating to a 27% performance increase over a comparable traditional pipelined microprocessor. The proposed microarchitecture is process independent and can be applied to low-cost, or transistor-limited applications. The proposed microarchitecture is implemented in the design of a 0.35 mum CMOS microprocessor, and the design of a 0.5 mum CGaAsTM micro-processor. The two technologies and designs are compared to ascertain the state of CGaAsTM for digital VLSI applications.

  7. Formal Verification of the AAMP-FV Microcode

    NASA Technical Reports Server (NTRS)

    Miller, Steven P.; Greve, David A.; Wilding, Matthew M.; Srivas, Mandayam

    1999-01-01

    This report describes the experiences of Collins Avionics & Communications and SRI International in formally specifying and verifying the microcode in a Rockwell proprietary microprocessor, the AAMP-FV, using the PVS verification system. This project built extensively on earlier experiences using PVS to verify the microcode in the AAMP5, a complex, pipelined microprocessor designed for use in avionics displays and global positioning systems. While the AAMP5 experiment demonstrated the technical feasibility of formal verification of microcode, the steep learning curve encountered left unanswered the question of whether it could be performed at reasonable cost. The AAMP-FV project was conducted to determine whether the experience gained on the AAMP5 project could be used to make formal verification of microcode cost effective for safety-critical and high volume devices.

  8. Ambulatory REACT: real-time seizure detection with a DSP microprocessor.

    PubMed

    McEvoy, Robert P; Faul, Stephen; Marnane, William P

    2010-01-01

    REACT (Real-Time EEG Analysis for event deteCTion) is a Support Vector Machine based technology which, in recent years, has been successfully applied to the problem of automated seizure detection in both adults and neonates. This paper describes the implementation of REACT on a commercial DSP microprocessor; the Analog Devices Blackfin®. The primary aim of this work is to develop a prototype system for use in ambulatory or in-ward automated EEG analysis. Furthermore, the complexity of the various stages of the REACT algorithm on the Blackfin processor is analysed; in particular the EEG feature extraction stages. This hardware profile is used to select a reduced, platform-aware feature set, in order to evaluate the seizure classification accuracy of a lower-complexity, lower-power REACT system.

  9. The Microprocessor controls the activity of mammalian retrotransposons

    PubMed Central

    Heras, Sara R.; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L.; Cáceres, Javier F.

    2013-01-01

    More than half of the human genome is made of Transposable Elements. Their ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human LINE-1 (Long INterspersed Element 1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons acting as a defender of human genome integrity. PMID:23995758

  10. The Microprocessor controls the activity of mammalian retrotransposons.

    PubMed

    Heras, Sara R; Macias, Sara; Plass, Mireya; Fernandez, Noemí; Cano, David; Eyras, Eduardo; Garcia-Perez, José L; Cáceres, Javier F

    2013-10-01

    More than half of the human genome is made of transposable elements whose ongoing mobilization is a driving force in genetic diversity; however, little is known about how the host regulates their activity. Here, we show that the Microprocessor (Drosha-DGCR8), which is required for microRNA biogenesis, also recognizes and binds RNAs derived from human long interspersed element 1 (LINE-1), Alu and SVA retrotransposons. Expression analyses demonstrate that cells lacking a functional Microprocessor accumulate LINE-1 mRNA and encoded proteins. Furthermore, we show that structured regions of the LINE-1 mRNA can be cleaved in vitro by Drosha. Additionally, we used a cell culture-based assay to show that the Microprocessor negatively regulates LINE-1 and Alu retrotransposition in vivo. Altogether, these data reveal a new role for the Microprocessor as a post-transcriptional repressor of mammalian retrotransposons and a defender of human genome integrity.

  11. Design studies for a technology assessment receiver for global positioning system

    NASA Technical Reports Server (NTRS)

    Painter, J. H.

    1981-01-01

    The operational conditions of a radio receiver - microprocessor for the global positioning system are studied. Navigation fundamentals and orbit characterization are reviewed. The global positioning system is described with emphasis upon signal structure and satellite positioning. Ranging and receiver processing techniques are discussed.

  12. A real time, FEM based optimal control algorithm and its implementation using parallel processing hardware (transistors) in a microprocessor environment

    NASA Technical Reports Server (NTRS)

    Patten, William Neff

    1989-01-01

    There is an evident need to discover a means of establishing reliable, implementable controls for systems that are plagued by nonlinear and, or uncertain, model dynamics. The development of a generic controller design tool for tough-to-control systems is reported. The method utilizes a moving grid, time infinite element based solution of the necessary conditions that describe an optimal controller for a system. The technique produces a discrete feedback controller. Real time laboratory experiments are now being conducted to demonstrate the viability of the method. The algorithm that results is being implemented in a microprocessor environment. Critical computational tasks are accomplished using a low cost, on-board, multiprocessor (INMOS T800 Transputers) and parallel processing. Progress to date validates the methodology presented. Applications of the technique to the control of highly flexible robotic appendages are suggested.

  13. Description of a dual fail operational redundant strapdown inertial measurement unit for integrated avionics systems research

    NASA Technical Reports Server (NTRS)

    Bryant, W. H.; Morrell, F. R.

    1981-01-01

    An experimental redundant strapdown inertial measurement unit (RSDIMU) is developed as a link to satisfy safety and reliability considerations in the integrated avionics concept. The unit includes four two degree-of-freedom tuned rotor gyros, and four accelerometers in a skewed and separable semioctahedral array. These sensors are coupled to four microprocessors which compensate sensor errors. These microprocessors are interfaced with two flight computers which process failure detection, isolation, redundancy management, and general flight control/navigation algorithms. Since the RSDIMU is a developmental unit, it is imperative that the flight computers provide special visibility and facility in algorithm modification.

  14. A rocket-borne data-manipulation experiment using a microprocessor

    NASA Technical Reports Server (NTRS)

    Davis, L. L.; Smith, L. G.; Voss, H. D.

    1979-01-01

    The development of a data-manipulation experiment using a Z-80 microprocessor is described. The instrumentation is included in the payloads of two Nike Apache sounding rockets used in an investigation of energetic particle fluxes. The data from an array of solid-state detectors and an electrostatic analyzer is processed to give the energy spectrum as a function of pitch angle. The experiment performed well in its first flight test: Nike Apache 14.543 was launched from Wallops Island at 2315 EST on 19 June 1978. The system was designed to be easily adaptable to other data-manipulation requirements and some suggestions for further development are included.

  15. LLL 8080 BASIC-II interpreter user's manual

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    McGoldrick, P.R.; Dickinson, J.; Allison, T.G.

    1978-04-03

    Scientists are finding increased applications for microprocessors as process controllers in their experiments. However, while microprocessors are small and inexpensive, they are difficult to program in machine or assembly language. A high-level language is needed to enable scientists to develop their own microcomputer programs for their experiments on location. Recognizing this need, LLL contracted to have such a language developed. This report describes the resulting LLL BASIC interpreter, which opeates with LLL's 8080-based MCS-8 microcomputer system. All numerical operations are done using Advanced Micro Device's Am9511 arithmetic processor chip or optionally by using a software simulation of that chip. 1more » figure.« less

  16. Fast computational scheme of image compression for 32-bit microprocessors

    NASA Technical Reports Server (NTRS)

    Kasperovich, Leonid

    1994-01-01

    This paper presents a new computational scheme of image compression based on the discrete cosine transform (DCT), underlying JPEG and MPEG International Standards. The algorithm for the 2-d DCT computation uses integer operations (register shifts and additions / subtractions only); its computational complexity is about 8 additions per image pixel. As a meaningful example of an on-board image compression application we consider the software implementation of the algorithm for the Mars Rover (Marsokhod, in Russian) imaging system being developed as a part of Mars-96 International Space Project. It's shown that fast software solution for 32-bit microprocessors may compete with the DCT-based image compression hardware.

  17. COED Transactions, Vol. IX, No. 6, June 1977. An Introductory Course in Microprocessors and Microcomputers.

    ERIC Educational Resources Information Center

    Marcovitz, Alan B., Ed.

    This paper describes an introductory course in microprocessors and microcomputers implemented at Grossmont College. The current state-of-the-art in the microprocessor field is discussed, with special emphasis on the 8-bit MOS single-chip processors which are the most commonly used devices. Objectives and guidelines for the course are presented,…

  18. Microprocessor-based single particle calibration of scintillation counter

    NASA Technical Reports Server (NTRS)

    Mazumdar, G. K. D.; Pathak, K. M.

    1985-01-01

    A microprocessor-base set-up is fabricated and tested for the single particle calibration of the plastic scintillator. The single particle response of the scintillator is digitized by an A/D converter, and a 8085 A based microprocessor stores the pulse heights. The digitized information is printed. Facilities for CRT display and cassette storing and recalling are also made available.

  19. COED Transactions, Vol. XI, No. 12, December 1979. Some Alternate Applications of Microprocessor Trainers in Support of Undergraduate Laboratories.

    ERIC Educational Resources Information Center

    Mitchell, Eugene E., Ed.

    Ways are described for the use of a microprocessor trainer in undergraduate laboratories. Listed are microcomputer applications that have been used as demonstrations and which provide signals for other experiments which are not related to microprocessors. Information and figures are provided for methods to do the following: direct generation of…

  20. Microprocessor-based integration of microfluidic control for the implementation of automated sensor monitoring and multithreaded optimization algorithms.

    PubMed

    Ezra, Elishai; Maor, Idan; Bavli, Danny; Shalom, Itai; Levy, Gahl; Prill, Sebastian; Jaeger, Magnus S; Nahmias, Yaakov

    2015-08-01

    Microfluidic applications range from combinatorial synthesis to high throughput screening, with platforms integrating analog perfusion components, digitally controlled micro-valves and a range of sensors that demand a variety of communication protocols. Currently, discrete control units are used to regulate and monitor each component, resulting in scattered control interfaces that limit data integration and synchronization. Here, we present a microprocessor-based control unit, utilizing the MS Gadgeteer open framework that integrates all aspects of microfluidics through a high-current electronic circuit that supports and synchronizes digital and analog signals for perfusion components, pressure elements, and arbitrary sensor communication protocols using a plug-and-play interface. The control unit supports an integrated touch screen and TCP/IP interface that provides local and remote control of flow and data acquisition. To establish the ability of our control unit to integrate and synchronize complex microfluidic circuits we developed an equi-pressure combinatorial mixer. We demonstrate the generation of complex perfusion sequences, allowing the automated sampling, washing, and calibrating of an electrochemical lactate sensor continuously monitoring hepatocyte viability following exposure to the pesticide rotenone. Importantly, integration of an optical sensor allowed us to implement automated optimization protocols that require different computational challenges including: prioritized data structures in a genetic algorithm, distributed computational efforts in multiple-hill climbing searches and real-time realization of probabilistic models in simulated annealing. Our system offers a comprehensive solution for establishing optimization protocols and perfusion sequences in complex microfluidic circuits.

  1. CP/M: A Family of 8- and 16-Bit Computer Operating Systems.

    ERIC Educational Resources Information Center

    Kildall, Gary

    1982-01-01

    Traces the development of the computer CP/M (Control Program for Microcomputers) and MP/M (Multiprogramming Monitor Microcomputers) operating system by Gary Kildall of Digital Research Company. Discusses the adaptation of these operating systems to the newly emerging 16 and 32 bit microprocessors. (Author/LC)

  2. Development of a real-time chemical injection system for air-assisted variable-rate sprayers

    USDA-ARS?s Scientific Manuscript database

    A chemical injection system is an effective method to minimize chemical waste and reduce the environmental pollution in pesticide spray applications. A microprocessor controlled injection system implementing a ceramic piston metering pump was developed to accurately dispense chemicals to be mixed wi...

  3. The Use of Tailored Testing with Instructional Programs. Final Report.

    ERIC Educational Resources Information Center

    Reckase, Mark D.

    A computerized testing system was implemented in conjunction with the Radar Technician Training Course at the Naval Training Center, Great Lakes, Illinois. The feasibility of the system and students' attitudes toward it were examined. The system, a multilevel, microprocessor-based computer network, administered tests in a sequential, fixed length…

  4. Security of Personal Computer Systems: A Management Guide.

    ERIC Educational Resources Information Center

    Steinauer, Dennis D.

    This report describes management and technical security considerations associated with the use of personal computer systems as well as other microprocessor-based systems designed for use in a general office environment. Its primary objective is to identify and discuss several areas of potential vulnerability and associated protective measures. The…

  5. Clearing a Path: The 16-Bit Operating System Jungle Offers Confusion, Not Standardization.

    ERIC Educational Resources Information Center

    Pournelle, Jerry

    1984-01-01

    Discusses the design and limited uses of the Pascal, MS-DOS, CP/M, and PC-DOS operating systems as standard operating systems for 16-bit microprocessors, especially with the more sophisticated microcomputers currently being developed. Advantages and disadvantages of Unix--a multitasking, multiuser operating system--as a standard operating system…

  6. An Innovative Method of Teaching Electronic System Design with PSoC

    ERIC Educational Resources Information Center

    Ye, Zhaohui; Hua, Chengying

    2012-01-01

    Programmable system-on-chip (PSoC), which provides a microprocessor and programmable analog and digital peripheral functions in a single chip, is very convenient for mixed-signal electronic system design. This paper presents the experience of teaching contemporary mixed-signal electronic system design with PSoC in the Department of Automation,…

  7. Heat pump system with selective space cooling

    DOEpatents

    Pendergrass, J.C.

    1997-05-13

    A reversible heat pump provides multiple heating and cooling modes and includes a compressor, an evaporator and heat exchanger all interconnected and charged with refrigerant fluid. The heat exchanger includes tanks connected in series to the water supply and a condenser feed line with heat transfer sections connected in counterflow relationship. The heat pump has an accumulator and suction line for the refrigerant fluid upstream of the compressor. Sub-cool transfer tubes associated with the accumulator/suction line reclaim a portion of the heat from the heat exchanger. A reversing valve switches between heating/cooling modes. A first bypass is operative to direct the refrigerant fluid around the sub-cool transfer tubes in the space cooling only mode and during which an expansion valve is utilized upstream of the evaporator/indoor coil. A second bypass is provided around the expansion valve. A programmable microprocessor activates the first bypass in the cooling only mode and deactivates the second bypass, and vice-versa in the multiple heating modes for said heat exchanger. In the heating modes, the evaporator may include an auxiliary outdoor coil for direct supplemental heat dissipation into ambient air. In the multiple heating modes, the condensed refrigerant fluid is regulated by a flow control valve. 4 figs.

  8. Heat pump system with selective space cooling

    DOEpatents

    Pendergrass, Joseph C.

    1997-01-01

    A reversible heat pump provides multiple heating and cooling modes and includes a compressor, an evaporator and heat exchanger all interconnected and charged with refrigerant fluid. The heat exchanger includes tanks connected in series to the water supply and a condenser feed line with heat transfer sections connected in counterflow relationship. The heat pump has an accumulator and suction line for the refrigerant fluid upstream of the compressor. Sub-cool transfer tubes associated with the accumulator/suction line reclaim a portion of the heat from the heat exchanger. A reversing valve switches between heating/cooling modes. A first bypass is operative to direct the refrigerant fluid around the sub-cool transfer tubes in the space cooling only mode and during which an expansion valve is utilized upstream of the evaporator/indoor coil. A second bypass is provided around the expansion valve. A programmable microprocessor activates the first bypass in the cooling only mode and deactivates the second bypass, and vice-versa in the multiple heating modes for said heat exchanger. In the heating modes, the evaporator may include an auxiliary outdoor coil for direct supplemental heat dissipation into ambient air. In the multiple heating modes, the condensed refrigerant fluid is regulated by a flow control valve.

  9. Microprocessors: Laboratory Simulation of Industrial Control Applications.

    ERIC Educational Resources Information Center

    Gedeon, David V.

    1981-01-01

    Describes a course to make technical managers more aware of computer technology and how data loggers, programmable controllers, and larger computer systems interact in a hierarchical configuration of manufacturing process control. (SK)

  10. A Monitoring System for Vegetable Greenhouses based on a Wireless Sensor Network

    PubMed Central

    Li, Xiu-hong; Cheng, Xiao; Yan, Ke; Gong, Peng

    2010-01-01

    A wireless sensor network-based automatic monitoring system is designed for monitoring the life conditions of greenhouse vegetatables. The complete system architecture includes a group of sensor nodes, a base station, and an internet data center. For the design of wireless sensor node, the JN5139 micro-processor is adopted as the core component and the Zigbee protocol is used for wireless communication between nodes. With an ARM7 microprocessor and embedded ZKOS operating system, a proprietary gateway node is developed to achieve data influx, screen display, system configuration and GPRS based remote data forwarding. Through a Client/Server mode the management software for remote data center achieves real-time data distribution and time-series analysis. Besides, a GSM-short-message-based interface is developed for sending real-time environmental measurements, and for alarming when a measurement is beyond some pre-defined threshold. The whole system has been tested for over one year and satisfactory results have been observed, which indicate that this system is very useful for greenhouse environment monitoring. PMID:22163391

  11. A COTS-Based Replacement Strategy for Aging Avionics Computers

    DTIC Science & Technology

    2001-12-01

    Communication Control Unit. A COTS-Based Replacement Strategy for Aging Avionics Computers COTS Microprocessor Real Time Operating System New Native Code...Native Code Objec ts Native Code Thread Real - Time Operating System Legacy Function x Virtual Component Environment Context Switch Thunk Add-in Replace

  12. Storing Data and Video on One Tape

    NASA Technical Reports Server (NTRS)

    Nixon, J. H.; Cater, J. P.

    1985-01-01

    Microprocessor-based system originally developed for anthropometric research merges digital data with video images for storage on video cassette recorder. Combined signals later retrieved and displayed simultaneously on television monitor. System also extracts digital portion of stored information and transfers it to solid-state memory.

  13. Embedded computer controlled premixing inline injection system for air-assisted variable-rate sprayers

    USDA-ARS?s Scientific Manuscript database

    Improvements to reduce chemical waste and environmental pollution for variable-rate sprayers used in orchards and ornamental nurseries require inline injection techniques. A microprocessor controlled premixing inline injection system implementing a ceramic piston chemical metering pump and two small...

  14. BROADBAND DIGITAL GEOPHYSICAL TELEMETRY SYSTEM.

    USGS Publications Warehouse

    Seeley, Robert L.; Daniels, Jeffrey J.

    1984-01-01

    A system has been developed to simultaneously sample and transmit digital data from five remote geophysical data receiver stations to a control station that processes, displays, and stores the data. A microprocessor in each remote station receives commands from the control station over a single telemetry channel.

  15. Intermittent/transient faults in digital systems

    NASA Technical Reports Server (NTRS)

    Masson, G. M.; Glazer, R. E.

    1982-01-01

    Containment set techniques are applied to 8085 microprocessor controllers so as to transform a typical control system into a slightly modified version, shown to be crashproof: after the departure of the intermittent/transient fault, return to one proper control algorithm is assured, assuming no permanent faults occur.

  16. Neural network application to comprehensive engine diagnostics

    NASA Technical Reports Server (NTRS)

    Marko, Kenneth A.

    1994-01-01

    We have previously reported on the use of neural networks for detection and identification of faults in complex microprocessor controlled powertrain systems. The data analyzed in those studies consisted of the full spectrum of signals passing between the engine and the real-time microprocessor controller. The specific task of the classification system was to classify system operation as nominal or abnormal and to identify the fault present. The primary concern in earlier work was the identification of faults, in sensors or actuators in the powertrain system as it was exercised over its full operating range. The use of data from a variety of sources, each contributing some potentially useful information to the classification task, is commonly referred to as sensor fusion and typifies the type of problems successfully addressed using neural networks. In this work we explore the application of neural networks to a different diagnostic problem, the diagnosis of faults in newly manufactured engines and the utility of neural networks for process control.

  17. Energy and time determine scaling in biological and computer designs

    PubMed Central

    Bezerra, George; Edwards, Benjamin; Brown, James; Forrest, Stephanie

    2016-01-01

    Metabolic rate in animals and power consumption in computers are analogous quantities that scale similarly with size. We analyse vascular systems of mammals and on-chip networks of microprocessors, where natural selection and human engineering, respectively, have produced systems that minimize both energy dissipation and delivery times. Using a simple network model that simultaneously minimizes energy and time, our analysis explains empirically observed trends in the scaling of metabolic rate in mammals and power consumption and performance in microprocessors across several orders of magnitude in size. Just as the evolutionary transitions from unicellular to multicellular animals in biology are associated with shifts in metabolic scaling, our model suggests that the scaling of power and performance will change as computer designs transition to decentralized multi-core and distributed cyber-physical systems. More generally, a single energy–time minimization principle may govern the design of many complex systems that process energy, materials and information. This article is part of the themed issue ‘The major synthetic evolutionary transitions’. PMID:27431524

  18. Energy and time determine scaling in biological and computer designs.

    PubMed

    Moses, Melanie; Bezerra, George; Edwards, Benjamin; Brown, James; Forrest, Stephanie

    2016-08-19

    Metabolic rate in animals and power consumption in computers are analogous quantities that scale similarly with size. We analyse vascular systems of mammals and on-chip networks of microprocessors, where natural selection and human engineering, respectively, have produced systems that minimize both energy dissipation and delivery times. Using a simple network model that simultaneously minimizes energy and time, our analysis explains empirically observed trends in the scaling of metabolic rate in mammals and power consumption and performance in microprocessors across several orders of magnitude in size. Just as the evolutionary transitions from unicellular to multicellular animals in biology are associated with shifts in metabolic scaling, our model suggests that the scaling of power and performance will change as computer designs transition to decentralized multi-core and distributed cyber-physical systems. More generally, a single energy-time minimization principle may govern the design of many complex systems that process energy, materials and information.This article is part of the themed issue 'The major synthetic evolutionary transitions'. © 2016 The Author(s).

  19. Purchasing a Microprocessor System for Administrative Use in Schools.

    ERIC Educational Resources Information Center

    Marshall, David G.

    1982-01-01

    Describes a series of decision-making steps regarding the purchase of microcomputers for administrative use in schools. Includes such topics as defining information needs and purchasing computer hardware and software. (Author/JJD)

  20. Data transmission system with distributed microprocessors

    DOEpatents

    Nambu, Shigeo

    1985-01-01

    A data transmission system having a common request line and a special request line in addition to a transmission line. The special request line has priority over the common request line. A plurality of node stations are multi-drop connected to the transmission line. Among the node stations, a supervising station is connected to the special request line and takes precedence over other slave stations to become a master station. The master station collects data from the slave stations. The station connected to the common request line can assign a master control function to any station requesting to be assigned the master control function within a short period of time. Each station has an auto response control circuit. The master station automatically collects data by the auto response controlling circuit independently of the microprocessors of the slave stations.

  1. Cell cycle-dependent regulation of Aurora kinase B mRNA by the Microprocessor complex.

    PubMed

    Jung, Eunsun; Seong, Youngmo; Seo, Jae Hong; Kwon, Young-Soo; Song, Hoseok

    2014-03-28

    Aurora kinase B regulates the segregation of chromosomes and the spindle checkpoint during mitosis. In this study, we showed that the Microprocessor complex, which is responsible for the processing of the primary transcripts during the generation of microRNAs, destabilizes the mRNA of Aurora kinase B in human cells. The Microprocessor-mediated cleavage kept Aurora kinase B at a low level and prevented premature entrance into mitosis. The cleavage was reduced during mitosis leading to the accumulation of Aurora kinase B mRNA and protein. In addition to Aurora kinase B mRNA, the processing of other primary transcripts of miRNAs were also decreased during mitosis. We found that the cleavage was dependent on an RNA helicase, DDX5, and the association of DDX5 and DDX17 with the Microprocessor was reduced during mitosis. Thus, we propose a novel mechanism by which the Microprocessor complex regulates stability of Aurora kinase B mRNA and cell cycle progression. Copyright © 2014 Elsevier Inc. All rights reserved.

  2. Gait and balance of transfemoral amputees using passive mechanical and microprocessor-controlled prosthetic knees.

    PubMed

    Kaufman, K R; Levine, J A; Brey, R H; Iverson, B K; McCrady, S K; Padgett, D J; Joyner, M J

    2007-10-01

    Microprocessor-controlled knee joints appeared on the market a decade ago. These joints are more sophisticated and more expensive than mechanical ones. The literature is contradictory regarding changes in gait and balance when using these sophisticated devices. This study employed a crossover design to assess the comparative performance of a passive mechanical knee prosthesis compared to a microprocessor-controlled knee joint in 15 subjects with an above-knee amputation. Objective measurements of gait and balance were obtained. Subjects demonstrated significantly improved gait characteristics after receiving the microprocessor-controlled prosthetic knee joint (p<0.01). Improvements in gait were a transition from a hyperextended knee to a flexed knee during loading response which resulted in a change from an internal knee flexor moment to a knee extensor moment. The participants' balance also improved (p<0.01). All conditions of the Sensory Organization Test (SOT) demonstrated improvements in equilibrium score. The composite score also increased. Transfemoral amputees using a microprocessor-controlled knee have significant improvements in gait and balance.

  3. Functional Anatomy of the Human Microprocessor.

    PubMed

    Nguyen, Tuan Anh; Jo, Myung Hyun; Choi, Yeon-Gil; Park, Joha; Kwon, S Chul; Hohng, Sungchul; Kim, V Narry; Woo, Jae-Sung

    2015-06-04

    MicroRNA (miRNA) maturation is initiated by Microprocessor composed of RNase III DROSHA and its cofactor DGCR8, whose fidelity is critical for generation of functional miRNAs. To understand how Microprocessor recognizes pri-miRNAs, we here reconstitute human Microprocessor with purified recombinant proteins. We find that Microprocessor is an ∼364 kDa heterotrimeric complex of one DROSHA and two DGCR8 molecules. Together with a 23-amino acid peptide from DGCR8, DROSHA constitutes a minimal functional core. DROSHA serves as a "ruler" by measuring 11 bp from the basal ssRNA-dsRNA junction. DGCR8 interacts with the stem and apical elements through its dsRNA-binding domains and RNA-binding heme domain, respectively, allowing efficient and accurate processing. DROSHA and DGCR8, respectively, recognize the basal UG and apical UGU motifs, which ensure proper orientation of the complex. These findings clarify controversies over the action mechanism of DROSHA and allow us to build a general model for pri-miRNA processing. Copyright © 2015 Elsevier Inc. All rights reserved.

  4. A Microprocessor-Based Real-Time Simulator of a Turbofan Engine

    DTIC Science & Technology

    1988-01-01

    NASA AVSCOM Technical Memorandum 100889 Technical Report 88-C-011 Lfl A Microprocessor-Based Real-Time Simulator of a Turbofan Engine CD I Jonathan S...Accession For NTIS GRA&I A MICROPROCESSOR-BASED REAL-TIME SIMULATOR DTIC TABUnannounced OF A TURBOFAN ENGINE Justifiaation, Jonathan S. Litt Propulsion...the F100 engine without augmentation (without afterburning). HYTESS is a simplified simulation written in FORTRAN of a generalized turbofan engine . To

  5. Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor

    DTIC Science & Technology

    2015-03-10

    for Public Release; Distribution Unlimited Final Report: Design and Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor The views...P.O. Box 12211 Research Triangle Park, NC 27709-2211 Superconductor technology, RSFQ, RQL, processor design, arithmetic units, high-performance...Demonstration of a 30 GHz 16-bit Superconductor RSFQ Microprocessor Report Title The major objective of the project was to design and demonstrate operation

  6. Energy expenditure and activity of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

    PubMed

    Kaufman, Kenton R; Levine, James A; Brey, Robert H; McCrady, Shelly K; Padgett, Denny J; Joyner, Michael J

    2008-07-01

    To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Repeated-measures design to evaluate comparative functional outcomes. Exercise physiology laboratory and community free-living environment. Subjects (N=15; 12 men, 3 women; age, 42+/-9 y; range, 26-57 y) with transfemoral amputation. Research participants were long-term users of a mechanical prosthesis (20+/-10 y as an amputee; range, 3-36 y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18+/-8 wk) before being retested. Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Subjects demonstrated significantly increased physical activity-related energy expenditure levels in the participant's free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life.

  7. Functional added value of microprocessor-controlled knee joints in daily life performance of Medicare Functional Classification Level-2 amputees.

    PubMed

    Theeven, Patrick; Hemmen, Bea; Rings, Frans; Meys, Guido; Brink, Peter; Smeets, Rob; Seelen, Henk

    2011-10-01

    To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. To assess the effects of using a microprocessor-controlled prosthetic knee joint on the functional performance of activities of daily living in persons with an above-knee leg amputation. Randomised cross-over trial. Forty-one persons with unilateral above-knee or knee disarticulation limb loss, classified as Medicare Functional Classification Level-2 (MFCL-2). Participants were measured in 3 conditions, i.e. using a mechanically controlled knee joint and two types of microprocessor-controlled prosthetic knee joints. Functional performance level was assessed using a test in which participants performed 17 simulated activities of daily living (Assessment of Daily Activity Performance in Transfemoral amputees test). Performance time was measured and self-perceived level of difficulty was scored on a visual analogue scale for each activity. High levels of within-group variability in functional performance obscured detection of any effects of using a microprocessor-controlled prosthetic knee joint. Data analysis after stratification of the participants into 3 subgroups, i.e. participants with a "low", "intermediate" and "high" functional mobility level, showed that the two higher functional subgroups performed significantly faster using microprocessor-controlled prosthetic knee joints. MFCL-2 amputees constitute a heterogeneous patient group with large variation in functional performance levels. A substantial part of this group seems to benefit from using a microprocessor-controlled prosthetic knee joint when performing activities of daily living.

  8. Universal control and measuring system for modern classic and amorphous magnetic materials single/on-line strip testers

    NASA Astrophysics Data System (ADS)

    Zemánek, Ivan; Havlíček, Václav

    2006-09-01

    A new universal control and measuring system for classic and amorphous soft magnetic materials single/on-line strip testing has been developed at the Czech Technical University in Prague. The measuring system allows to measure magnetization characteristic and specific power losses of different tested materials (strips) at AC magnetization of arbitrary magnetic flux density waveform at wide range of frequencies 20 Hz-20 kHz. The measuring system can be used for both single strip testing in laboratories and on-line strip testing during the production process. The measuring system is controlled by two-stage master-slave control system consisting of the external PC (master) completed by three special A/D measuring plug-in boards, and local executing control unit (slave) with one-chip microprocessor 8051, connected with PC by the RS232 serial line. The "user friendly" powerful control software implemented on the PC and the effective program code for the microprocessor give possibility for full automatic measurement with high measuring power and high measuring accuracy.

  9. Design of multifunction anti-terrorism robotic system based on police dog

    NASA Astrophysics Data System (ADS)

    You, Bo; Liu, Suju; Xu, Jun; Li, Dongjie

    2007-11-01

    Aimed at some typical constraints of police dogs and robots used in the areas of reconnaissance and counterterrorism currently, the multifunction anti-terrorism robotic system based on police dog has been introduced. The system is made up of two parts: portable commanding device and police dog robotic system. The portable commanding device consists of power supply module, microprocessor module, LCD display module, wireless data receiving and dispatching module and commanding module, which implements the remote control to the police dogs and takes real time monitor to the video and images. The police dog robotic system consists of microprocessor module, micro video module, wireless data transmission module, power supply module and offence weapon module, which real time collects and transmits video and image data of the counter-terrorism sites, and gives military attack based on commands. The system combines police dogs' biological intelligence with micro robot. Not only does it avoid the complexity of general anti-terrorism robots' mechanical structure and the control algorithm, but it also widens the working scope of police dog, which meets the requirements of anti-terrorism in the new era.

  10. Systems Engineering

    DTIC Science & Technology

    1989-05-01

    Faced with complaints about lengthy and costly developments , rapid obsolescence, and excessive costs of ownership, we have all heard the following...microwave integrated circuits raises similar system and sub-system issues. Microprocessor developments raise new questions regarding the trade-offs between...imply the need for and utilization of more specialists, but future avionics developments will also require systems-oriented engineess. By definition

  11. Aerospace Applications of Microprocessors

    NASA Technical Reports Server (NTRS)

    1980-01-01

    An assessment of the state of microprocessor applications is presented. Current and future requirements and associated technological advances which allow effective exploitation in aerospace applications are discussed.

  12. The automated counting of beating rates in individual cultured heart cells.

    PubMed

    Collins, G A; Dower, R; Walker, M J

    1981-12-01

    The effect of drugs on the beating rate of cultured heart cells can be monitored in a number of ways. The simultaneous automated measurement of beating rates of a number of cells allows drug effects to be rapidly quantified. A photoresistive detector placed on a television image of a cell, when coupled to operational amplifiers, gives binary signals that can be processed by a microprocessor. On this basis, we have devised a system that is capable of simultaneously monitoring the individual beating of six single cultured heart cells. A microprocessor automatically processes data obtained under different experimental conditions and records it in suitable descriptive formats such as dose-response curves and double reciprocal plots.

  13. A proposed microcomputer implementation of an Omega navigation processor

    NASA Technical Reports Server (NTRS)

    Abel, J. D.

    1976-01-01

    A microprocessor navigation systems using the Omega process is discussed. Several methods for correcting incoming sky waves are presented along with the hardware design which depends on a microcomputer. The control program is discussed, and block diagrams of the Omega processor and interface systems are presented.

  14. An electronic flow control system for a variable-rate tree sprayer

    USDA-ARS?s Scientific Manuscript database

    Precise modulation of nozzle flow rates is a critical measure to achieve variable-rate spray applications. An electronic flow rate control system accommodating with microprocessors and pulse width modulation (PWM) controlled solenoid valves was designed to manipulate the output of spray nozzles inde...

  15. Development of digital flow control system for multi-channel variable-rate sprayers

    USDA-ARS?s Scientific Manuscript database

    Precision modulation of nozzle flow rates is a critical step for variable-rate spray applications in orchards and ornamental nurseries. An automatic flow rate control system activated with microprocessors and pulse width modulation (PWM) controlled solenoid valves was developed to control flow rates...

  16. OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems.

    PubMed

    Stone, John E; Gohara, David; Shi, Guochun

    2010-05-01

    We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures.

  17. The Effect of a Microprocessor Prosthetic Foot on Function and Quality of Life in Transtibial Amputees Who Are Limited Community Ambulators

    DTIC Science & Technology

    2017-09-01

    parallel, randomized, controlled clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of...clinical trial designed to determine if a microprocessor controlled prosthetic foot (MPF), with greater range of motion and active power, will...Department of the Army position, policy or decision unless so designated by other documentation. CONTRACTING ORGANIZATION: University of Tennessee

  18. Formal proof of the AVM-1 microprocessor using the concept of generic interpreters

    NASA Technical Reports Server (NTRS)

    Windley, P.; Levitt, K.; Cohen, G. C.

    1991-01-01

    A microprocessor designated AVM-1 was designed to demonstrate the use of generic interpreters in verifying hierarchically decomposed microprocessor specifications. This report is intended to document the high-order language (HOL) code verifying AVM-1. The organization of the proof is discussed and some technical details concerning the execution of the proof scripts in HOL are presented. The proof scripts used to verify AVM-1 are also presented.

  19. Full temperature single event upset characterization of two microprocessor technologies

    NASA Technical Reports Server (NTRS)

    Nichols, Donald K.; Coss, James R.; Smith, L. S.; Rax, Bernard; Huebner, Mark

    1988-01-01

    Data for the 9450 I3L bipolar microprocessor and the 80C86 CMOS/epi (vintage 1985) microprocessor are presented, showing single-event soft errors for the full MIL-SPEC temperature range of -55 to 125 C. These data show for the first time that the soft-error cross sections continue to decrease with decreasing temperature at subzero temperatures. The temperature dependence of the two parts, however, is very different.

  20. PDSparc: A Drop-In Replacement for LEON3 Written Using Synopsys Processor Designer

    DTIC Science & Technology

    2015-09-24

    Kate   Thurmer  MIT  Lincoln  Laboratory,  Lexington,   MA,  USA Distribution A: Public Release   ABSTRACT   Microprocessors are the...enabled appliances has opened a significant new niche: the Application Specific Standard Product (ASSP) microprocessor . These processors usually start...out as soft-cores that are parameterized at design time to realize exclusively the specific needs of the application. The microprocessor is a small

  1. Hardware-Enabled Security Through On-Chip Reconfigurable Fabric

    DTIC Science & Technology

    2016-02-05

    SECURITY CLASSIFICATION OF: The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they... microprocessors in a way that they can be added and updated after fabrication, similar to software, while maintaining the efficiency and the security of...Progress The goal of this project was to enable hardware-based security techniques on future microprocessors in a way that they can be added and

  2. Aircraft interrogation and display system: A ground support equipment for digital flight systems

    NASA Technical Reports Server (NTRS)

    Glover, R. D.

    1982-01-01

    A microprocessor-based general purpose ground support equipment for electronic systems was developed. The hardware and software are designed to permit diverse applications in support of aircraft flight systems and simulation facilities. The implementation of the hardware, the structure of the software, describes the application of the system to an ongoing research aircraft project are described.

  3. Modernization of the Control Systems of High-Frequency, Brush-Free, and Collector Exciters of Turbogenerators

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Popov, E. N., E-mail: enpo@ruselmash.ru; Komkov, A. L.; Ivanov, S. L.

    Methods of modernizing the regulation systems of electric machinery exciters with high-frequency, brush-free, and collector exciters by means of microprocessor technology are examined. The main problems of modernization are to increase the response speed of a system and to use a system stabilizer to increase the stability of the power system.

  4. 49 CFR 661.7 - Waivers.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

  5. 49 CFR 661.7 - Waivers.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

  6. 49 CFR 661.7 - Waivers.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

  7. 49 CFR 661.7 - Waivers.

    Code of Federal Regulations, 2010 CFR

    2010-10-01

    ... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

  8. 49 CFR 661.7 - Waivers.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... requirements applies to microprocessors, computers, microcomputers, or software, or other such devices, which... a product or device which merely contains a microprocessor or microcomputer and is not used solely...

  9. Implementation of a microprocessor-based visual-evoked cortical potential recording and analysis system.

    PubMed

    Wilson, A; Fram, D; Sistar, J

    1981-06-01

    An Imsai 8080 microcomputer is being used to simultaneously generate a color graphics stimulus display and to record visual-evoked cortical potentials. A brief description of the hardware and software developed for this system is presented. Data storage and analysis techniques are also discussed.

  10. Flight Experiment Demonstration System (FEDS) analysis report

    NASA Technical Reports Server (NTRS)

    Shank, D. E.

    1986-01-01

    The purpose of the Flight Experiment Demonstration System (FEDS) was to show, in a simulated spacecraft environment, the feasibility of using a microprocessor to automate the onboard orbit determination functions. The software and hardware configuration used to support FEDS during the demonstration and the results of the demonstration are discussed.

  11. The comparison of transfemoral amputees using mechanical and microprocessor- controlled prosthetic knee under different walking speeds: A randomized cross-over trial.

    PubMed

    Cao, Wujing; Yu, Hongliu; Zhao, Weiliang; Meng, Qiaoling; Chen, Wenming

    2018-04-20

    The microprocessor-controlled prosthetic knees have been introduced to transfemoral amputees due to advances in biomedical engineering. A body of scientific literature has shown that the microprocessor-controlled prosthetic knees improve the gait and functional abilities of persons with transfemoral amputation. The aim of this study was to propose a new microprocessor-controlled prosthetic knee (MPK) and compare it with non-microprocessor-controlled prosthetic knees (NMPKs) under different walking speeds. The microprocessor-controlled prosthetic knee (i-KNEE) with hydraulic damper was developed. The comfortable self-selected walking speeds of 12 subjects with i-KNEE and NMPK were obtained. The maximum swing flexion knee angle and gait symmetry were compared in i-KNEE and NMPK condition. The comfortable self-selected walking speeds of some subjects were higher with i-KNEE while some were not. There was no significant difference in comfortable self-selected walking speed between the i-KNEE and the NMPK condition (P= 0.138). The peak prosthetic knee flexion during swing in the i-KNEE condition was between sixty and seventy degree under any walking speed. In the NMPK condition, the maximum swing flexion knee angle changed significantly. And it increased with walking speed. There is no significant difference in knee kinematic symmetry when the subjects wear the i-KNEE or NMPK. The results of this study indicated that the new microprocessor-controlled prosthetic knee was suitable for transfemoral amputees. The maximum swing flexion knee angle under different walking speeds showed different properties in the NMPK and i-KNEE condition. The i-KNEE was more adaptive to speed changes. There was little difference of comfortable self-selected walking speed between i-KNEE and NMPK condition.

  12. Microprocessor Controlled Isometric Contractions of Cat Gastrocnemius Muscle.

    DTIC Science & Technology

    1981-12-01

    A-A15 504 AIR FORCE INST OF TECH WRIGHT-PATTERSON AFS OH 5CHOO--ETC F/6 6/2 MICROPROCESSOR CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROC-ETC(U) D...CONTROLLED ISOMETRIC CONTRACTIONS OF CAT GASTROCNEMIUS MUSCLE THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of...1981 Appzoved for public release; distribution unlimited. AFIT/GE/EE/81D-4O \\ MICROPROCESSOR CONTROLLED ISOMETRIC COMUtCTIONS OF CAT GASTfOCNEMIUS i

  13. Global identification of target recognition and cleavage by the Microprocessor in human ES cells

    PubMed Central

    Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

    2014-01-01

    The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein–RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3′ overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. PMID:25326327

  14. Energy Expenditure and Activity of Transfemoral Amputees Using Mechanical and Microprocessor-Controlled Prosthetic Knees

    PubMed Central

    Kaufman, Kenton R.; Levine, James A.; Brey, Robert H.; McCrady, Shelly K.; Padgett, Denny J.; Joyner, Michael J.

    2009-01-01

    Objective To quantify the energy efficiency of locomotion and free-living physical activity energy expenditure of transfemoral amputees using a mechanical and microprocessor-controlled prosthetic knee. Design Repeated-measures design to evaluate comparative functional outcomes. Setting Exercise physiology laboratory and community free-living environment. Participants Subjects (N=15; 12 men, 3 women; age, 42±9y; range, 26 –57y) with transfemoral amputation. Intervention Research participants were long-term users of a mechanical prosthesis (20±10y as an amputee; range, 3–36y). They were fitted with a microprocessor-controlled knee prosthesis and allowed to acclimate (mean time, 18±8wk) before being retested. Main Outcome Measures Objective measurements of energy efficiency and total daily energy expenditure were obtained. The Prosthetic Evaluation Questionnaire was used to gather subjective feedback from the participants. Results Subjects demonstrated significantly increased physical activity–related energy expenditure levels in the participant’s free-living environment (P=.04) after wearing the microprocessor-controlled prosthetic knee joint. There was no significant difference in the energy efficiency of walking (P=.34). When using the microprocessor-controlled knee, the subjects expressed increased satisfaction in their daily lives (P=.02). Conclusions People ambulating with a microprocessor-controlled knee significantly increased their physical activity during daily life, outside the laboratory setting, and expressed an increased quality of life. PMID:18586142

  15. Stability of nano-fluids and their use for thermal management of a microprocessor: an experimental and numerical study

    NASA Astrophysics Data System (ADS)

    Shoukat, Ahmad Adnan; Shaban, Muhammad; Israr, Asif; Shah, Owaisur Rahman; Khan, Muhammad Zubair; Anwar, Muhammad

    2018-03-01

    We investigate the heat transfer effect of different types of Nano-fluids on the pin fin heat sinks used in computer's microprocessor. Nano-particles of Aluminum oxide have been used with volumetric concentrations of 0.002% and Silver oxide with volumetric concentrations of 0.001% in the base fluid of deionized water. We have also used Aluminum oxide with ethylene glycol at volumetric concentrations of 0.002%. We report the cooling rates of Nano-fluids for pin-fin heat to cool the microprocessor and compare these with the cooling rate of pure water. We use a microprocessor heat generator in this investigation. The base temperature is obtained using surface heater of power 130 W. The main purpose of this work is to minimize the base temperature, and increase the heat transfer rate of the water block and radiator. The temperature of the heat sink is maintained at 110 °C which is nearly equal to the observed computer microprocessor temperature. We also provide the base temperature at different Reynolds's number using the above mention Nano-fluids with different volumetric concentrations.

  16. A new study on the emission of EM waves from large EAS

    NASA Technical Reports Server (NTRS)

    Pathak, K. M.; Mazumdar, G. K. D.

    1985-01-01

    A method used in locating the core of individual cosmic ray showers is described. Using a microprocessor-based detecting system, the density distribution and hence, energy of each detected shower was estimated.

  17. Smart call box field operational test evaluation : subtest reports

    DOT National Transportation Integrated Search

    1997-05-01

    Smart call boxes are an enhanced version of devices used as emergency call boxes in California. The overall system consists of a microprocessor, a cellular communications transceiver, solar power sources, data collection devices, maintenance computer...

  18. Smart call box field operational test evaluation : summary report

    DOT National Transportation Integrated Search

    1997-05-01

    Smart call boxes are an enhanced version of devices used as emergency call boxes in California. The overall system consists of a microprocessor, a cellular communications transceiver, solar power sources, data collection devices, maintenance computer...

  19. OpenCL: A Parallel Programming Standard for Heterogeneous Computing Systems

    PubMed Central

    Stone, John E.; Gohara, David; Shi, Guochun

    2010-01-01

    We provide an overview of the key architectural features of recent microprocessor designs and describe the programming model and abstractions provided by OpenCL, a new parallel programming standard targeting these architectures. PMID:21037981

  20. Wireless sensor node for detection of freight train derailment

    NASA Astrophysics Data System (ADS)

    Costa, Andrea; Milani, Damiano; Resta, Ferruccio; Tomasini, Gisella

    2016-04-01

    The target of the research activity presented in this paper is to design, to realize and to test an autonomous sensor node able to measure the accelerations in correspondence of the axle box of a freight train. The final goal of the sensor is to identify the derailment conditions by observing the variations in the spectra of the box accelerations, around the frequencies associated to the wheel revolution and its multiples. The sensor node embeds an accelerometer, a microprocessor, a transmission system, a piezoelectric bimorph energy harvester and an integrated circuit for managing the power distribution to each component of the node. In particular, a mechanical filter to be applied to the node was specifically designed to increment the energy recovered by the harvester and to filter out the high frequency components of the axle-box acceleration, allowing the use of a more sensitive accelerometer. The harvesting system was setup by means of laboratory tests carried out with an electromechanical shaker and the sensor node was finally tested through field tests on freight trains.

  1. Radiation-hardened fast acquisition/weak signal tracking system and method

    NASA Technical Reports Server (NTRS)

    Winternitz, Luke (Inventor); Boegner, Gregory J. (Inventor); Sirotzky, Steve (Inventor)

    2009-01-01

    A global positioning system (GPS) receiver and method of acquiring and tracking GPS signals comprises an antenna adapted to receive GPS signals; an analog radio frequency device operatively connected to the antenna and adapted to convert the GPS signals from an analog format to a digital format; a plurality of GPS signal tracking correlators operatively connected to the analog RF device; a GPS signal acquisition component operatively connected to the analog RF device and the plurality of GPS signal tracking correlators, wherein the GPS signal acquisition component is adapted to calculate a maximum vector on a databit correlation grid; and a microprocessor operatively connected to the plurality of GPS signal tracking correlators and the GPS signal acquisition component, wherein the microprocessor is adapted to compare the maximum vector with a predetermined correlation threshold to allow the GPS signal to be fully acquired and tracked.

  2. Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

    NASA Technical Reports Server (NTRS)

    Trotter, J. D.

    1982-01-01

    The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

  3. Automatic multi-banking of memory for microprocessors

    NASA Technical Reports Server (NTRS)

    Wiker, G. A. (Inventor)

    1984-01-01

    A microprocessor system is provided with added memories to expand its address spaces beyond its address word length capacity by using indirect addressing instructions of a type having a detectable operations code and dedicating designated address spaces of memory to each of the added memories, one space to a memory. By decoding each operations code of instructions read from main memory into a decoder to identify indirect addressing instructions of the specified type, and then decoding the address that follows in a decoder to determine which added memory is associated therewith, the associated added memory is selectively enabled through a unit while the main memory is disabled to permit the instruction to be executed on the location to which the effective address of the indirect address instruction points, either before the indirect address is read from main memory or afterwards, depending on how the system is arranged by a switch.

  4. An Adaptable Power System with Software Control Algorithm

    NASA Technical Reports Server (NTRS)

    Castell, Karen; Bay, Mike; Hernandez-Pellerano, Amri; Ha, Kong

    1998-01-01

    A low cost, flexible and modular spacecraft power system design was developed in response to a call for an architecture that could accommodate multiple missions in the small to medium load range. Three upcoming satellites will use this design, with one launch date in 1999 and two in the year 2000. The design consists of modular hardware that can be scaled up or down, without additional cost, to suit missions in the 200 to 600 Watt orbital average load range. The design will be applied to satellite orbits that are circular, polar elliptical and a libration point orbit. Mission unique adaptations are accomplished in software and firmware. In designing this advanced, adaptable power system, the major goals were reduction in weight volume and cost. This power system design represents reductions in weight of 78 percent, volume of 86 percent and cost of 65 percent from previous comparable systems. The efforts to miniaturize the electronics without sacrificing performance has created streamlined power electronics with control functions residing in the system microprocessor. The power system design can handle any battery size up to 50 Amp-hour and any battery technology. The three current implementations will use both nickel cadmium and nickel hydrogen batteries ranging in size from 21 to 50 Amp-hours. Multiple batteries can be used by adding another battery module. Any solar cell technology can be used and various array layouts can be incorporated with no change in Power System Electronics (PSE) hardware. Other features of the design are the standardized interfaces between cards and subsystems and immunity to radiation effects up to 30 krad Total Ionizing Dose (TID) and 35 Mev/cm(exp 2)-kg for Single Event Effects (SEE). The control algorithm for the power system resides in a radiation-hardened microprocessor. A table driven software design allows for flexibility in mission specific requirements. By storing critical power system constants in memory, modifying the system code for other programs is simple. These constants can be altered also by ground command, or in response to an anomolous event. All critical power system functions have backup hardware functions to prevent a software or computer glitch from propagating. A number of battery charge control schemes can be implemented by selecting the proper control terms in the code. The architecture allows the design engineer to tune the system response to various system components and anticipated load profiles without costly alterations. A design trade was made with the size, weight and power dissipation of the electronics versus the performance of the power bus to load variations. Linear, fine control is maintained with a streamlined electronics design. This paper describes the hardware design as well as the software control algorithm. The challenges of closing the system control loop digitally is discussed. Control loop margin and power system performance is presented. Lab measurements are shown and compared to the system response of a hardware model running actual flight software.

  5. Microprocessors as a tool in determining correlation between sferics and tornado genesis: an update

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Witte, D.R.

    1980-09-01

    Sferics - atmospheric electromagnetic radiation - can be directly correlated, it is believed, to the genesis of tornadoes and other severe weather. Sferics are generated by lightning and other atmospheric disturbances that are not yet entirely understood. The recording and analysis of the patterns in which sferics events occur, it is hoped, will lead to accurate real-time prediction of tornadoes and other severe weather. Collection of the tremendous amount of sferics data generated by one storm system becomes cumbersome when correlation between at least two stations is necessary for triangulation. Microprocessor-based computing systems have made the task of data collectionmore » and manipulation inexpensive and manageable. The original paper on this subject delivered at MAECON '78 dealt with hardware interfacing. Presented were hardware and software tradeoffs, as well as design and construction techniques to yield a cost effective system. This updated paper presents an overview of where the data comes from, how it is collected, and some current manipulation and interpretation techniques used.« less

  6. 49 CFR 229.27 - Annual tests.

    Code of Federal Regulations, 2011 CFR

    2011-10-01

    ... DMU locomotive or an MU locomotive, equipped with a microprocessor-based event recorder that includes...) A microprocessor-based event recorder with a self-monitoring feature equipped to verify that all...

  7. Microprocessor utilization in search and rescue missions

    NASA Technical Reports Server (NTRS)

    Schwartz, M.; Bashkow, T.

    1978-01-01

    The position of an emergency transmitter may be determined by measuring the Doppler shift of the distress signal as received by an orbiting satellite. This requires the computation of an initial estimate and refinement of this estimate through an iterative, nonlinear, least squares estimation. A version of the algorithm was implemented and tested by locating a transmitter on the premises and obtaining observations from a satellite. The computer used was an IBM 360/95. The position was determined within the desired 10 km radius accuracy. The feasibility of performing the same task in real time using microprocessor technology, was determined. The least squares algorithm was implemented on an Intel 8080 microprocessor. The results indicate that a microprocessor can easily match the IBM implementation in accuracy and be performed inside the time limitations set.

  8. Continuous-Reading Cryogen Level Sensor

    NASA Technical Reports Server (NTRS)

    Barone, F. E.; Fox, E.; Macumber, S.

    1984-01-01

    Two pressure transducers used in system for measuring amount of cryogenic liquid in tank. System provides continuous measurements accurate within 0.03 percent. Sensors determine pressure in liquid and vapor in tank. Microprocessor uses pressure difference to compute mass of cryogenic liquid in tank. New system allows continuous sensing; unaffected by localized variations in composition and density as are capacitance-sensing schemes.

  9. Flight Experiment Demonstration System (FEDS): Mathematical specification

    NASA Technical Reports Server (NTRS)

    Shank, D. E.

    1984-01-01

    Computational models for the flight experiment demonstration system (FEDS) code 580 were developed. The FEDS is a modification of the automated orbit determination system which was developed during 1981 and 1982. The purpose of FEDS is to demonstrate, in a simulated spacecraft environment, the feasibility of using microprocessors to perform onboard orbit determination with limited ground support.

  10. Importance of balanced architectures in the design of high-performance imaging systems

    NASA Astrophysics Data System (ADS)

    Sgro, Joseph A.; Stanton, Paul C.

    1999-03-01

    Imaging systems employed in demanding military and industrial applications, such as automatic target recognition and computer vision, typically require real-time high-performance computing resources. While high- performances computing systems have traditionally relied on proprietary architectures and custom components, recent advances in high performance general-purpose microprocessor technology have produced an abundance of low cost components suitable for use in high-performance computing systems. A common pitfall in the design of high performance imaging system, particularly systems employing scalable multiprocessor architectures, is the failure to balance computational and memory bandwidth. The performance of standard cluster designs, for example, in which several processors share a common memory bus, is typically constrained by memory bandwidth. The symptom characteristic of this problem is failure to the performance of the system to scale as more processors are added. The problem becomes exacerbated if I/O and memory functions share the same bus. The recent introduction of microprocessors with large internal caches and high performance external memory interfaces makes it practical to design high performance imaging system with balanced computational and memory bandwidth. Real word examples of such designs will be presented, along with a discussion of adapting algorithm design to best utilize available memory bandwidth.

  11. System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

    NASA Technical Reports Server (NTRS)

    Hall, William A. (Inventor)

    1993-01-01

    A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

  12. Anti-Hassle Chip

    NASA Technical Reports Server (NTRS)

    1998-01-01

    With assistance from NASA's Ames Research Center, the iTV Corporation has developed a full custom microprocessor that enables access to the Internet through a $49 device. The microprocessor is supported with a compliment of design tools for customization and adaptation as either a licensable core or as a complete microprocessor. Other uses include cell phones, DVD (digital versatile disk) players, cable modems, video conferencing equipment, digital cameras, wireless LANs (Local Area Network) and WANs (Wide Area Network). iTV continues to design new, low-cost consumer products.

  13. Frequency Dependence of Single-event Upset in Advanced Commerical PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Frokh; Farmanesh, Farhad F.; Swift, Gary M.; Johnston, Allen H.

    2004-01-01

    This paper examines single-event upsets in advanced commercial SOI microprocessors in a dynamic mode, studying SEU sensitivity of General Purpose Registers (GPRs) with clock frequency. Results are presented for SOI processors with feature sizes of 0.18 microns and two different core voltages. Single-event upset from heavy ions is measured for advanced commercial microprocessors in a dynamic mode with clock frequency up to 1GHz. Frequency and core voltage dependence of single-event upsets in registers is discussed.

  14. A Fault-tolerant RISC Microprocessor for Spacecraft Applications

    NASA Technical Reports Server (NTRS)

    Timoc, Constantin; Benz, Harry

    1990-01-01

    Viewgraphs on a fault-tolerant RISC microprocessor for spacecraft applications are presented. Topics covered include: reduced instruction set computer; fault tolerant registers; fault tolerant ALU; and double rail CMOS logic.

  15. 49 CFR 229.23 - Periodic inspection: general.

    Code of Federal Regulations, 2012 CFR

    2012-10-01

    ... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

  16. 49 CFR 229.23 - Periodic inspection: general.

    Code of Federal Regulations, 2013 CFR

    2013-10-01

    ... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

  17. 49 CFR 229.23 - Periodic inspection: general.

    Code of Federal Regulations, 2014 CFR

    2014-10-01

    ... locomotive. (b) For each locomotive equipped with advanced microprocessor-based on-board electronic condition... April 2, or July 3 if it's a locomotive equipped with advanced microprocessor-based on-board electronic...

  18. An Undergraduate-Built Prototype Altitude Determination System (PADS) for High Altitude Research Balloons.

    NASA Astrophysics Data System (ADS)

    Verner, E.; Bruhweiler, F. C.; Abot, J.; Casarotto, V.; Dichoso, J.; Doody, E.; Esteves, F.; Morsch Filho, E.; Gonteski, D.; Lamos, M.; Leo, A.; Mulder, N.; Matubara, F.; Schramm, P.; Silva, R.; Quisberth, J.; Uritsky, G.; Kogut, A.; Lowe, L.; Mirel, P.; Lazear, J.

    2014-12-01

    In this project a multi-disciplinary undergraduate team from CUA, comprising majors in Physics, Mechanical Engineering, Electrical Engineering, and Biology, design, build, test, fly, and analyze the data from a prototype attitude determination system (PADS). The goal of the experiment is to determine if an inexpensive attitude determination system could be built for high altitude research balloons using MEMS gyros. PADS is a NASA funded project, built by students with the cooperation of CUA faculty, Verner, Bruhweiler, and Abot, along with the contributed expertise of researchers and engineers at NASA/GSFC, Kogut, Lowe, Mirel, and Lazear. The project was initiated through a course taught in CUA's School of Engineering, which was followed by a devoted effort by students during the summer of 2014. The project is an experiment to use 18 MEMS gyros, similar to those used in many smartphones, to produce an averaged positional error signal that could be compared with the motion of the fixed optical system as recorded through a string of optical images of stellar fields to be stored on a hard drive flown with the experiment. The optical system, camera microprocessor, and hard drive are enclosed in a pressure vessel, which maintains approximately atmospheric pressure throughout the balloon flight. The experiment uses multiple microprocessors to control the camera exposures, record gyro data, and provide thermal control. CUA students also participated in NASA-led design reviews. Four students traveled to NASA's Columbia Scientific Balloon Facility in Palestine, Texas to integrate PADS into a large balloon gondola containing other experiments, before being shipped, then launched in mid-August at Ft. Sumner, New Mexico. The payload is to fly at a float altitude of 40-45,000 m, and the flight last approximately 15 hours. The payload is to return to earth by parachute and the retrieved data are to be analyzed by CUA undergraduates. A description of the instrument is presented here as well as a preliminary analysis of the anticipated data, which were not available at the time of abstract submission. Acknowledgements: NASA grant NNX13AR61 under NASA's Undergraduate Student Instrument Program (USIP). Participating Brazilian students acknowledge support through Brazil's "Science without Borders" program.

  19. XMOS XC-2 Development Board for Mechanical Control and Data Collection

    NASA Technical Reports Server (NTRS)

    Jarnot, Robert F.; Bowden, William J.

    2011-01-01

    The scanning microwave limb sounder (SMLS) will use technological improvements in low-noise mixers to provide precise data on the Earth s atmospheric composition with high spatial resolution. This project focuses on the design and implementation of a realtime control system needed for airborne engineering tests of the SMLS. The system must coordinate the actuation of optical components using four motors with encoder readback, while collecting synchronized telemetric data from a GPS receiver and 3-axis gyrometric system. A graphical user interface for testing the control system was also designed using Python. Although the system could have been implemented with an FPGA(fieldprogrammable gate array)-based setup, a processor development kit manufactured by XMOS was chosen. The XMOS architecture allows parallel execution of multiple tasks on separate threads, making it ideal for this application. It is easily programmed using XC (a subset of C). The necessary communication interfaces were implemented in software, including Ethernet, with significant cost and time reduction compared to an FPGA-based approach. A simple approach to control the chopper, calibration mirror, and gimbal for the airborne SMLS was needed. The XMOS board allows for multiple threads and real-time data acquisition. The XC-2 development kit is an attractive choice for synchronized, real-time, event-driven applications. The XMOS is based on the transputer microprocessor architecture developed for parallel computing, which is being revamped in this new platform. The XMOS device has multiple cores capable of running parallel applications on separate threads. The threads communicate with each other via user-defined channels capable of transmitting data within the device. XMOS provides a C-based development environment using XC, which eliminates the need for custom tool kits associated with FPGA programming. The XC-2 has four cores and necessary hardware for Ethernet I/O.

  20. Hand-held survey probe

    DOEpatents

    Young, Kevin L [Idaho Falls, ID; Hungate, Kevin E [Idaho Falls, ID

    2010-02-23

    A system for providing operational feedback to a user of a detection probe may include an optical sensor to generate data corresponding to a position of the detection probe with respect to a surface; a microprocessor to receive the data; a software medium having code to process the data with the microprocessor and pre-programmed parameters, and making a comparison of the data to the parameters; and an indicator device to indicate results of the comparison. A method of providing operational feedback to a user of a detection probe may include generating output data with an optical sensor corresponding to the relative position with respect to a surface; processing the output data, including comparing the output data to pre-programmed parameters; and indicating results of the comparison.

  1. Advanced capability RFID system

    DOEpatents

    Gilbert, Ronald W.; Steele, Kerry D.; Anderson, Gordon A.

    2007-09-25

    A radio-frequency transponder device having an antenna circuit configured to receive radio-frequency signals and to return modulated radio-frequency signals via continuous wave backscatter, a modulation circuit coupled to the antenna circuit for generating the modulated radio-frequency signals, and a microprocessor coupled to the antenna circuit and the modulation circuit and configured to receive and extract operating power from the received radio-frequency signals and to monitor inputs on at least one input pin and to generate responsive signals to the modulation circuit for modulating the radio-frequency signals. The microprocessor can be configured to generate output signals on output pins to associated devices for controlling the operation thereof. Electrical energy can be extracted and stored in an optional electrical power storage device.

  2. Operation of commercial R3000 processors in the low earth orbit (LEO) space environment

    NASA Astrophysics Data System (ADS)

    Kaschmitter, J. L.; Shaeffer, D. L.; Colella, N. J.; McKnett, C. L.; Coakley, P. G.

    1991-12-01

    Spacecraft processors must operate with minimal degradation of performance in the LEO radiation environment, which includes the effects of total accumulated ionizing dose and single event phenomena (SEP) caused by protons and cosmic rays. Commercially available microprocessors can offer a number of advantages relative to radiation-hardened devices but are not normally designed to tolerate effects induced by the LEO environment. Extensive testing of the MIPS R3000 Reduced Instruction Set Computer (RISC) microprocessor family for operation in LEO environments is reported. The authors have characterized total dose and SEP effects for altitudes and inclinations of interest to systems operating in LEO, and they postulate techniques for detection and alleviation of SEP effects based on experimental results.

  3. Apparatus Reviews.

    ERIC Educational Resources Information Center

    School Science Review, 1981

    1981-01-01

    Reviews apparatus design and instructional uses for Fume Cupboard Monitor, Plant Tissue Culture Kit, various equipment for electronic systems course, Welwyn Microprocessor-Tutor, Sweep Function Generator SFG 606, and Harris manufacturers materials--Regulated Power Supply Units, Electronic Current and Voltage Meters, Gas Preparation Kit, and…

  4. Nearest Neighbor Searching in Binary Search Trees: Simulation of a Multiprocessor System.

    ERIC Educational Resources Information Center

    Stewart, Mark; Willett, Peter

    1987-01-01

    Describes the simulation of a nearest neighbor searching algorithm for document retrieval using a pool of microprocessors. Three techniques are described which allow parallel searching of a binary search tree as well as a PASCAL-based system, PASSIM, which can simulate these techniques. Fifty-six references are provided. (Author/LRW)

  5. A Microprocessor Development System for the Intel 8748 Microcomputer.

    DTIC Science & Technology

    1979-12-01

    their ready availability, it was decided to build the system on a 4 x 6 Vector plugboard with a 44 pin connect- or and which was predrilled for wirewrap...8748, additional sockets were provided in a 4 socket mother board. These sockets accept the standard 44 pin Vector plugboard . It is recommended that

  6. Comparing Online to Face-To-Face Delivery of Undergraduate Digital Circuits Content

    ERIC Educational Resources Information Center

    LaMeres, Brock J.; Plumb, Carolyn

    2014-01-01

    This paper presents a comparison of online to traditional face-to-face delivery of undergraduate digital systems material. Two specific components of digital content were compared and evaluated: a sophomore logic circuits course with no laboratory, and a microprocessor laboratory component of a junior-level computer systems course. For each of…

  7. Low cost airborne microwave landing system receiver, task 3

    NASA Technical Reports Server (NTRS)

    Hager, J. B.; Vancleave, J. R.

    1979-01-01

    Work performed on the low cost airborne Microwave Landing System (MLS) receiver is summarized. A detailed description of the prototype low cost MLS receiver is presented. This detail includes block diagrams, schematics, board assembly drawings, photographs of subassemblies, mechanical construction, parts lists, and microprocessor software. Test procedures are described and results are presented.

  8. Microprocessor control of multiple peak power tracking DC/DC converters for use with solar cell arrays

    NASA Technical Reports Server (NTRS)

    Frederick, Martin E. (Inventor); Jermakian, Joel (Inventor)

    1991-01-01

    A method and an apparatus is provided for efficiently controlling the power output of a solar cell array string or a plurality of solar cell array strings to achieve a maximum amount of output power from the strings under varying conditions of use. Maximum power output from a solar array string is achieved through control of a pulse width modulated DC/DC buck converter which transfers power from a solar array to a load or battery bus. The input voltage from the solar array to the converter is controlled by a pulse width modulation duty cycle, which in turn is controlled by a differential signal controller. By periodically adjusting the control voltage up or down by a small amount and comparing the power on the load or bus with that generated at different voltage values a maximum power output voltage may be obtained. The system is totally modular and additional solar array strings may be added to the system simply by adding converter boards to the system and changing some constants in the controller's control routines.

  9. DOE Office of Scientific and Technical Information (OSTI.GOV)

    Underwood, Keith D; Ulmer, Craig D.; Thompson, David

    Field programmable gate arrays (FPGAs) have been used as alternative computational de-vices for over a decade; however, they have not been used for traditional scientific com-puting due to their perceived lack of floating-point performance. In recent years, there hasbeen a surge of interest in alternatives to traditional microprocessors for high performancecomputing. Sandia National Labs began two projects to determine whether FPGAs wouldbe a suitable alternative to microprocessors for high performance scientific computing and,if so, how they should be integrated into the system. We present results that indicate thatFPGAs could have a significant impact on future systems. FPGAs have thepotentialtohave ordermore » of magnitude levels of performance wins on several key algorithms; however,there are serious questions as to whether the system integration challenge can be met. Fur-thermore, there remain challenges in FPGA programming and system level reliability whenusing FPGA devices.4 AcknowledgmentArun Rodrigues provided valuable support and assistance in the use of the Structural Sim-ulation Toolkit within an FPGA context. Curtis Janssen and Steve Plimpton provided valu-able insights into the workings of two Sandia applications (MPQC and LAMMPS, respec-tively).5« less

  10. 40 CFR Appendix F to Part 60 - Quality Assurance Procedures

    Code of Federal Regulations, 2012 CFR

    2012-07-01

    ... automatically adjust the data to the corrected calibration values (e.g., microprocessor control) must be... calibration values (e.g., microprocessor control), you must program your PM CEMS to record the unadjusted...

  11. Global identification of target recognition and cleavage by the Microprocessor in human ES cells.

    PubMed

    Seong, Youngmo; Lim, Do-Hwan; Kim, Augustine; Seo, Jae Hong; Lee, Young Sik; Song, Hoseok; Kwon, Young-Soo

    2014-11-10

    The Microprocessor plays an essential role in canonical miRNA biogenesis by facilitating cleavage of stem-loop structures in primary transcripts to yield pre-miRNAs. Although miRNA biogenesis has been extensively studied through biochemical and molecular genetic approaches, it has yet to be addressed to what extent the current miRNA biogenesis models hold true in intact cells. To address the issues of in vivo recognition and cleavage by the Microprocessor, we investigate RNAs that are associated with DGCR8 and Drosha by using immunoprecipitation coupled with next-generation sequencing. Here, we present global protein-RNA interactions with unprecedented sensitivity and specificity. Our data indicate that precursors of canonical miRNAs and miRNA-like hairpins are the major substrates of the Microprocessor. As a result of specific enrichment of nascent cleavage products, we are able to pinpoint the Microprocessor-mediated cleavage sites per se at single-nucleotide resolution. Unexpectedly, a 2-nt 3' overhang invariably exists at the ends of cleaved bases instead of nascent pre-miRNAs. Besides canonical miRNA precursors, we find that two novel miRNA-like structures embedded in mRNAs are cleaved to yield pre-miRNA-like hairpins, uncoupled from miRNA maturation. Our data provide a framework for in vivo Microprocessor-mediated cleavage and a foundation for experimental and computational studies on miRNA biogenesis in living cells. © The Author(s) 2014. Published by Oxford University Press on behalf of Nucleic Acids Research.

  12. Real-time and high accuracy frequency measurements for intermediate frequency narrowband signals

    NASA Astrophysics Data System (ADS)

    Tian, Jing; Meng, Xiaofeng; Nie, Jing; Lin, Liwei

    2018-01-01

    Real-time and accurate measurements of intermediate frequency signals based on microprocessors are difficult due to the computational complexity and limited time constraints. In this paper, a fast and precise methodology based on the sigma-delta modulator is designed and implemented by first generating the twiddle factors using the designed recursive scheme. This scheme requires zero times of multiplications and only half amounts of addition operations by using the discrete Fourier transform (DFT) and the combination of the Rife algorithm and Fourier coefficient interpolation as compared with conventional methods such as DFT and Fast Fourier Transform. Experimentally, when the sampling frequency is 10 MHz, the real-time frequency measurements with intermediate frequency and narrowband signals have a measurement mean squared error of ±2.4 Hz. Furthermore, a single measurement of the whole system only requires approximately 0.3 s to achieve fast iteration, high precision, and less calculation time.

  13. Precision control of multiple quantum cascade lasers for calibration systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Taubman, Matthew S., E-mail: Matthew.Taubman@pnnl.gov; Myers, Tanya L.; Pratt, Richard M.

    We present a precision, 1-A, digitally interfaced current controller for quantum cascade lasers, with demonstrated temperature coefficients for continuous and 40-kHz full-depth square-wave modulated operation, of 1–2 ppm/ °C and 15 ppm/ °C, respectively. High precision digital to analog converters (DACs) together with an ultra-precision voltage reference produce highly stable, precision voltages, which are selected by a multiplexer (MUX) chip to set output currents via a linear current regulator. The controller is operated in conjunction with a power multiplexing unit, allowing one of three lasers to be driven by the controller, while ensuring protection of controller and all lasers during operation, standby,more » and switching. Simple ASCII commands sent over a USB connection to a microprocessor located in the current controller operate both the controller (via the DACs and MUX chip) and the power multiplexer.« less

  14. Precision Control of Multiple Quantum Cascade Lasers for Calibration Systems

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Taubman, Matthew S.; Myers, Tanya L.; Pratt, Richard M.

    We present a precision, digitally interfaced current controller for quantum cascade lasers, with demonstrated DC and modulated temperature coefficients of 1- 2 ppm/ºC and 15 ppm/ºC respectively. High linearity digital to analog converters (DACs) together with an ultra-precision voltage reference, produce highly stable, precision voltages. These are in turn selected by a low charge-injection multiplexer (MUX) chip, which are then used to set output currents via a linear current regulator. The controller is operated in conjunction with a power multiplexing unit, allowing one of three lasers to be driven by the controller while ensuring protection of controller and all lasersmore » during operation, standby and switching. Simple ASCII commands sent over a USB connection to a microprocessor located in the current controller operate both the controller (via the DACs and MUX chip) and the power multiplexer.« less

  15. Evaluation of function, performance, and preference as transfemoral amputees transition from mechanical to microprocessor control of the prosthetic knee.

    PubMed

    Hafner, Brian J; Willingham, Laura L; Buell, Noelle C; Allyn, Katheryn J; Smith, Douglas G

    2007-02-01

    To evaluate differences in function, performance, and preference between mechanical and microprocessor prosthetic knee control technologies. A-B-A-B reversal design. Home, community, and laboratory environments. Twenty-one unilateral, transfemoral amputees. Mechanical control prosthetic knee versus microprocessor control prosthetic knee (Otto Bock C-Leg). Stair rating, hill rating and time, obstacle course time, divided attention task accuracy and time, Amputee Mobility Predictor score, step activity, Prosthesis Evaluation Questionnaire score, Medical Outcomes Study 36-Item Short-Form Health Survey score, self-reported frequency of stumbles and falls, and self-reported concentration required for ambulation. Stair descent score, hill descent time, and hill sound-side step length showed significant (P<.01) improvement with the C-Leg. Users reported a significant (P<.05) decrease in frequency of stumbles and falls, frustration with falling, and difficulty in multitasking while using the microprocessor knee. Subject satisfaction with the C-Leg was significantly (P<.001) greater than the mechanical control prosthesis. The study population showed improved performance when negotiating stairs and hills, reduced frequency of stumbling and falling, and a preference for the microprocessor control C-Leg as compared with the mechanical control prosthetic knee.

  16. Microprocessor Recruitment to Elongating RNA Polymerase II Is Required for Differential Expression of MicroRNAs.

    PubMed

    Church, Victoria A; Pressman, Sigal; Isaji, Mamiko; Truscott, Mary; Cizmecioglu, Nihal Terzi; Buratowski, Stephen; Frolov, Maxim V; Carthew, Richard W

    2017-09-26

    The cellular abundance of mature microRNAs (miRNAs) is dictated by the efficiency of nuclear processing of primary miRNA transcripts (pri-miRNAs) into pre-miRNA intermediates. The Microprocessor complex of Drosha and DGCR8 carries this out, but it has been unclear what controls Microprocessor's differential processing of various pri-miRNAs. Here, we show that Drosophila DGCR8 (Pasha) directly associates with the C-terminal domain of the RNA polymerase II elongation complex when it is phosphorylated by the Cdk9 kinase (pTEFb). When association is blocked by loss of Cdk9 activity, a global change in pri-miRNA processing is detected. Processing of pri-miRNAs with a UGU sequence motif in their apical junction domain increases, while processing of pri-miRNAs lacking this motif decreases. Therefore, phosphorylation of RNA polymerase II recruits Microprocessor for co-transcriptional processing of non-UGU pri-miRNAs that would otherwise be poorly processed. In contrast, UGU-positive pri-miRNAs are robustly processed by Microprocessor independent of RNA polymerase association. Copyright © 2017 The Author(s). Published by Elsevier Inc. All rights reserved.

  17. FPGA wavelet processor design using language for instruction-set architectures (LISA)

    NASA Astrophysics Data System (ADS)

    Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

    2007-04-01

    The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

  18. Microprocessors: the engines of the digital age

    PubMed Central

    2017-01-01

    The microprocessor—a computer central processing unit integrated onto a single microchip—has come to dominate computing across all of its scales from the tiniest consumer appliance to the largest supercomputer. This dominance has taken decades to achieve, but an irresistible logic made the ultimate outcome inevitable. The objectives of this Perspective paper are to offer a brief history of the development of the microprocessor and to answer questions such as: where did the microprocessor come from, where is it now, and where might it go in the future? PMID:28413353

  19. Evaluation of the performance of microprocessor-based colorimeter

    PubMed Central

    Randhawa, S. S.; Gupta, R. C.; Bhandari, A. K.; Malhotra, P. S.

    1992-01-01

    Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments. PMID:18924952

  20. Evaluation of the performance of microprocessor-based colorimeter.

    PubMed

    Randhawa, S S; Gupta, R C; Bhandari, A K; Malhotra, P S

    1992-01-01

    Colorimetric estimations have an important role in quantitative studies. An inexpensive and portable microprocessor-based colorimeter developed by the authors is described in this paper. The colorimeter uses a light emitting diode as the light source; a pinphotodiode as the detector and an 8085A microprocessor. Blood urea, glucose, total protein, albumin and bilirubin from patient blood samples were analysed with the instrument and results obtained were compared with assays of the same blood using a Spectronic 21. A good correlation was found between the results from the two instruments.

  1. Neutron beam irradiation study of workload dependence of SER in a microprocessor

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Michalak, Sarah E; Graves, Todd L; Hong, Ted

    It is known that workloads are an important factor in soft error rates (SER), but it is proving difficult to find differentiating workloads for microprocessors. We have performed neutron beam irradiation studies of a commercial microprocessor under a wide variety of workload conditions from idle, performing no operations, to very busy workloads resembling real HPC, graphics, and business applications. There is evidence that the mean times to first indication of failure, MTFIF defined in Section II, may be different for some of the applications.

  2. Microprogrammable Integrated Data Acquisition System-Fatigue Life Data Application

    DTIC Science & Technology

    1976-03-01

    Lt. James W. Sturges, successfully applied the Midas general system [Sturges, 1975] to the fatigue life data monitoring problem and proved its...life data problem . The Midas FLD system computer program generates the required signals in the proper sequence for effectively sampling the 8-channel...Integrated Data Acquisition System- Fatigue Life Data Application" ( Midas FLD) is a microprocessor based data acquisition system. It incorporates a Pro-Log

  3. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    SEU from heavy-ions is measured for SOI PowerPC microprocessors. Results for 0.13 micron PowerPC with 1.1V core voltages increases over 1.3V versions. This suggests that improvement in SEU for scaled devices may be reversed. In recent years there has been interest in the possible use of unhardened commercial microprocessors in space because of their superior performance compared to hardened processors. However, unhardened devices are susceptible to upset from radiation space. More information is needed on how they respond to radiation before they can be used in space. Only a limited number of advanced microprocessors have been subjected to radiation tests, which are designed with lower clock frequencies and higher internal core voltage voltages than recent devices [1-6]. However the trend for commercial Silicon-on-insulator (SOI) microprocessors is to reduce feature size and internal core voltage and increase the clock frequency. Commercial microprocessors with the PowerPC architecture are now available that use partially depleted SOI processes with feature size of 90 nm and internal core voltage as low as 1.0 V and clock frequency in the GHz range. Previously, we reported SEU measurements for SOI commercial PowerPCs with feature size of 0.18 and 0.13 m [7, 8]. The results showed an order of magnitude reduction in saturated cross section compared to CMOS bulk counterparts. This paper examines SEUs in advanced commercial SOI microprocessors, focusing on SEU sensitivity of D-Cache and hangs with feature size and internal core voltage. Results are presented for the Motorola SOI processor with feature sizes of 0.13 microns and internal core voltages of 1.3 and 1.1 V. These results are compared with results for the Motorola SOI processors with feature size of 0.18 microns and internal core voltage of 1.6 and 1.3 V.

  4. 78 FR 53500 - Petition for Exemption From the Federal Motor Vehicle Theft Prevention Standard; Chrysler

    Federal Register 2010, 2011, 2012, 2013, 2014

    2013-08-29

    ...) transceiver and a microprocessor and it initiates the ignition process by communicating with the BCM through SKIS. The microprocessor-based SKIS hardware and software also use electronic messages to communicate...

  5. Microprocessor Simulation: A Training Technique.

    ERIC Educational Resources Information Center

    Oscarson, David J.

    1982-01-01

    Describes the design and application of a microprocessor simulation using BASIC for formal training of technicians and managers and as a management tool. Illustrates the utility of the modular approach for the instruction and practice of decision-making techniques. (SK)

  6. Microprocessor mediates transcriptional termination of long noncoding RNA transcripts hosting microRNAs.

    PubMed

    Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J; Jopling, Catherine L

    2015-04-01

    MicroRNAs (miRNAs) play a major part in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with cotranscriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. Although most miRNAs are located within introns of protein-coding transcripts, a substantial minority of miRNAs originate from long noncoding (lnc) RNAs, for which transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lncRNA transcripts containing miRNAs (lnc-pri-miRNAs) do not use the canonical cleavage-and-polyadenylation pathway but instead use Microprocessor cleavage to terminate transcription. Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a new RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells.

  7. Microprocessor mediates transcriptional termination in long noncoding microRNA genes

    PubMed Central

    Dhir, Ashish; Dhir, Somdutta; Proudfoot, Nick J.; Jopling, Catherine L.

    2015-01-01

    MicroRNA (miRNA) play a major role in the post-transcriptional regulation of gene expression. Mammalian miRNA biogenesis begins with co-transcriptional cleavage of RNA polymerase II (Pol II) transcripts by the Microprocessor complex. While most miRNA are located within introns of protein coding genes, a substantial minority of miRNA originate from long non coding (lnc) RNA where transcript processing is largely uncharacterized. We show, by detailed characterization of liver-specific lnc-pri-miR-122 and genome-wide analysis in human cell lines, that most lnc-pri-miRNA do not use the canonical cleavage and polyadenylation (CPA) pathway, but instead use Microprocessor cleavage to terminate transcription. This Microprocessor inactivation leads to extensive transcriptional readthrough of lnc-pri-miRNA and transcriptional interference with downstream genes. Consequently we define a novel RNase III-mediated, polyadenylation-independent mechanism of Pol II transcription termination in mammalian cells. PMID:25730776

  8. Fault-Sensitivity and Wear-Out Analysis of VLSI Systems.

    DTIC Science & Technology

    1995-06-01

    DESCRIPTION MIXED-MODE HIERARCIAIFAULT DESCRIPTION FAULT SIMULATION TYPE OF FAULT TRANSIENT/STUCK-AT LOCATION/TIME * _AUTOMATIC FAULT INJECTION TRACE...4219-4224, December 1985. [15] J. Sosnowski, "Evaluation of transient hazards in microprocessor controll - ers," Digest, FTCS-16, The Sixteenth

  9. A new method for inferring carbon monoxide concentrations from gas filter radiometer data

    NASA Technical Reports Server (NTRS)

    Wallio, H. A.; Reichle, H. G., Jr.; Casas, J. C.; Gormsen, B. B.

    1981-01-01

    A method for inferring carbon monoxide concentrations from gas filter radiometer data is presented. The technique can closely approximate the results of more costly line-by-line radiative transfer calculations over a wide range of altitudes, ground temperatures, and carbon monoxide concentrations. The technique can also be used over a larger range of conditions than those used for the regression analysis. Because the influence of the carbon monoxide mixing ratio requires only addition, multiplication and a minimum of logic, the method can be implemented on very small computers or microprocessors.

  10. The proposed monitoring system for the Fermilab D0 colliding beams detector

    NASA Astrophysics Data System (ADS)

    Goodwin, Robert; Florian, Robert; Johnson, Marvin; Jones, Alan; Shea, Mike

    1986-06-01

    The Fermilab D0 Detector is a collaborative effort that includes seventeen universities and national laboratories. The monitoring and control system for this detector will be separate from the online detector data system. A distributed, stand-alone, microprocessor-based system is being designed to allow monitoring and control functions to be available to the collaborators at their home institutions during the design, fabrication, and testing phases of the project. Individual stations are VMEbus-based 68000 systems that are networked together during installation using an ARCnet (by Datapoint Corporation) Local Area Network. One station, perhaps a MicroVAX, would have a hard disk to store a backup copy of the distributed database located in non-volatile RAM in the local stations. This station would also serve as a gateway to the online system, so that data from the control system will be available for logging with the detector data. Apple Macintosh personal computers are being developed for use as the local control consoles. Each would be interfaced to ARCnet to provide access to all control system data. Through the use of bit-mapped graphics with multiple windows and pull-down menus, a cost effective, flexible display system can be provided, taking advantage of familiar modern software tools to support the operator interface.

  11. Large Scale Document Inversion using a Multi-threaded Computing System

    PubMed Central

    Jung, Sungbo; Chang, Dar-Jen; Park, Juw Won

    2018-01-01

    Current microprocessor architecture is moving towards multi-core/multi-threaded systems. This trend has led to a surge of interest in using multi-threaded computing devices, such as the Graphics Processing Unit (GPU), for general purpose computing. We can utilize the GPU in computation as a massive parallel coprocessor because the GPU consists of multiple cores. The GPU is also an affordable, attractive, and user-programmable commodity. Nowadays a lot of information has been flooded into the digital domain around the world. Huge volume of data, such as digital libraries, social networking services, e-commerce product data, and reviews, etc., is produced or collected every moment with dramatic growth in size. Although the inverted index is a useful data structure that can be used for full text searches or document retrieval, a large number of documents will require a tremendous amount of time to create the index. The performance of document inversion can be improved by multi-thread or multi-core GPU. Our approach is to implement a linear-time, hash-based, single program multiple data (SPMD), document inversion algorithm on the NVIDIA GPU/CUDA programming platform utilizing the huge computational power of the GPU, to develop high performance solutions for document indexing. Our proposed parallel document inversion system shows 2-3 times faster performance than a sequential system on two different test datasets from PubMed abstract and e-commerce product reviews. CCS Concepts •Information systems➝Information retrieval • Computing methodologies➝Massively parallel and high-performance simulations. PMID:29861701

  12. Large Scale Document Inversion using a Multi-threaded Computing System.

    PubMed

    Jung, Sungbo; Chang, Dar-Jen; Park, Juw Won

    2017-06-01

    Current microprocessor architecture is moving towards multi-core/multi-threaded systems. This trend has led to a surge of interest in using multi-threaded computing devices, such as the Graphics Processing Unit (GPU), for general purpose computing. We can utilize the GPU in computation as a massive parallel coprocessor because the GPU consists of multiple cores. The GPU is also an affordable, attractive, and user-programmable commodity. Nowadays a lot of information has been flooded into the digital domain around the world. Huge volume of data, such as digital libraries, social networking services, e-commerce product data, and reviews, etc., is produced or collected every moment with dramatic growth in size. Although the inverted index is a useful data structure that can be used for full text searches or document retrieval, a large number of documents will require a tremendous amount of time to create the index. The performance of document inversion can be improved by multi-thread or multi-core GPU. Our approach is to implement a linear-time, hash-based, single program multiple data (SPMD), document inversion algorithm on the NVIDIA GPU/CUDA programming platform utilizing the huge computational power of the GPU, to develop high performance solutions for document indexing. Our proposed parallel document inversion system shows 2-3 times faster performance than a sequential system on two different test datasets from PubMed abstract and e-commerce product reviews. •Information systems➝Information retrieval • Computing methodologies➝Massively parallel and high-performance simulations.

  13. Preliminary experience with a hospital blood pressure follow up clinic with nurse practitioner assessment and microprocessor based data retrieval.

    PubMed Central

    Rubin, P C; Curzio, J L; Kelman, A; Elliott, H L; Reid, J L

    1984-01-01

    Experience over two years with 376 hypertensive patients managed at a clinic where the primary observations are made by a trained nurse, clinical information is held on a microprocessor, and treatment follows a standard stepped care approach has been assessed. Blood pressure control after both one and two years was appreciably improved, with over 70% of patients having diastolic pressure below 90 mm Hg compared with 22% of patients when they first attended the new clinic. The non-attendance rate was half that of the conventional hospital outpatient clinic. A computer based record system with a nurse run hypertension clinic is acceptable to patients and offers the possibility of more effective long term control of blood pressure in large numbers of patients. PMID:6432180

  14. Multi-crop area estimation and mapping on a microprocessor/mainframe network

    NASA Technical Reports Server (NTRS)

    Sheffner, E.

    1985-01-01

    The data processing system is outlined for a 1985 test aimed at determining the performance characteristics of area estimation and mapping procedures connected with the California Cooperative Remote Sensing Project. The project is a joint effort of the USDA Statistical Reporting Service-Remote Sensing Branch, the California Department of Water Resources, NASA-Ames Research Center, and the University of California Remote Sensing Research Program. One objective of the program was to study performance when data processing is done on a microprocessor/mainframe network under operational conditions. The 1985 test covered the hardware, software, and network specifications and the integration of these three components. Plans for the year - including planned completion of PEDITOR software, testing of software on MIDAS, and accomplishment of data processing on the MIDAS-VAX-CRAY network - are discussed briefly.

  15. A Report of Bethune-Cookman College NASA JOVE Projects

    NASA Technical Reports Server (NTRS)

    Agba, Lawrence C.; David, Sunil K.; Rao, Narsing G.; Rahmani, Munir A.

    1997-01-01

    This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.

  16. OS Friendly Microprocessor Architecture

    DTIC Science & Technology

    2017-04-01

    fact or fiction. Austin ( TX ): The Virtualization Practice; [accessed 2012 July 26]. http://www.virtualization practice.com/type-0-hypervisor-fact......needed. Do not return it to the originator. ARL-SR-0370 ● APR 2017 US Army Research Laboratory OS Friendly Microprocessor

  17. Embedded algorithms within an FPGA-based system to process nonlinear time series data

    NASA Astrophysics Data System (ADS)

    Jones, Jonathan D.; Pei, Jin-Song; Tull, Monte P.

    2008-03-01

    This paper presents some preliminary results of an ongoing project. A pattern classification algorithm is being developed and embedded into a Field-Programmable Gate Array (FPGA) and microprocessor-based data processing core in this project. The goal is to enable and optimize the functionality of onboard data processing of nonlinear, nonstationary data for smart wireless sensing in structural health monitoring. Compared with traditional microprocessor-based systems, fast growing FPGA technology offers a more powerful, efficient, and flexible hardware platform including on-site (field-programmable) reconfiguration capability of hardware. An existing nonlinear identification algorithm is used as the baseline in this study. The implementation within a hardware-based system is presented in this paper, detailing the design requirements, validation, tradeoffs, optimization, and challenges in embedding this algorithm. An off-the-shelf high-level abstraction tool along with the Matlab/Simulink environment is utilized to program the FPGA, rather than coding the hardware description language (HDL) manually. The implementation is validated by comparing the simulation results with those from Matlab. In particular, the Hilbert Transform is embedded into the FPGA hardware and applied to the baseline algorithm as the centerpiece in processing nonlinear time histories and extracting instantaneous features of nonstationary dynamic data. The selection of proper numerical methods for the hardware execution of the selected identification algorithm and consideration of the fixed-point representation are elaborated. Other challenges include the issues of the timing in the hardware execution cycle of the design, resource consumption, approximation accuracy, and user flexibility of input data types limited by the simplicity of this preliminary design. Future work includes making an FPGA and microprocessor operate together to embed a further developed algorithm that yields better computational and power efficiency.

  18. ZEUS hardware control system

    NASA Astrophysics Data System (ADS)

    Loveless, R.; Erhard, P.; Ficenec, J.; Gather, K.; Heath, G.; Iacovacci, M.; Kehres, J.; Mobayyen, M.; Notz, D.; Orr, R.; Orr, R.; Sephton, A.; Stroili, R.; Tokushuku, K.; Vogel, W.; Whitmore, J.; Wiggers, L.

    1989-12-01

    The ZEUS collaboration is building a system to monitor, control and document the hardware of the ZEUS detector. This system is based on a network of VAX computers and microprocessors connected via ethernet. The database for the hardware values will be ADAMO tables; the ethernet connection will be DECNET, TCP/IP, or RPC. Most of the documentation will also be kept in ADAMO tables for easy access by users.

  19. Improved Planning and Programming for Energy Efficient New Army Facilities

    DTIC Science & Technology

    1988-10-01

    setpoints to occupant comfort must be considered carefully. Cutting off the HVAC system to the bedrooms during the day produced only small savings...functions of a building and minimizing the energy usage through optimization . It includes thermostats, time switches, programmable con- trollers...microprocessor systems, computers, and sensing devices that are linked with control and power components to manage energy use. This system optimizes load

  20. A portable real-time data processing system for standard meteorological radiosondes

    NASA Technical Reports Server (NTRS)

    Staffanson, F. L.

    1983-01-01

    The UMET-1 is a microprocessor-based portable system for automatic real-time processing of flight data transmitted from the standard RAWINSONDE upper atmosphere meteorological balloonsonde. The first 'target system' is described which was designed to receive data from a mobile tracking and telemetry receiving station (TRADAT), as the balloonsonde ascends to apogee. After balloon-burst, the UMET-1 produces user-ready hardcopy.

  1. Portable-Beacon Landing System for Helicopters

    NASA Technical Reports Server (NTRS)

    Davis, Thomas J.; Clary, George R.; Chisholm, John P.; Macdonald, Stanley L.

    1987-01-01

    Prototype beacon landing system (BLS) allows helicopters to make precise landings in all weather. BLS easily added to existing helicopter avionic equipment and readily deployed at remote sites. Small and light, system employs X-band radar and digital processing. Variety of beams pulsed sequentially by ground station after initial interrogation by weather radar of approaching helicopter. Airborne microprocessor processes pulses to determine glide slope, course deviation, and range.

  2. Microprocessor-Based Systems Control for the Rigidized Inflatable Get-Away-Special Experiment

    DTIC Science & Technology

    2004-03-01

    communications and faster data throughput increase, satellites are becoming larger. Larger satellite antennas help to provide the needed gain to...increase communications in space. Compounding the performance and size trade-offs are the payload weight and size limit imposed by the launch vehicles...increased communications capacity, and reduce launch costs. This thesis develops and implements the computer control system and power system to

  3. Installation package for integrated programmable electronic controller and hydronic subsystem - solar heating and cooling

    NASA Technical Reports Server (NTRS)

    1978-01-01

    A description is given of the Installation, Operation, and Maintenance Manual and information on the power panel and programmable microprocessor, a hydronic solar pump system and a hydronic heating hot water pumping system. These systems are integrated into various configurations for usages in solar energy management, control and monitoring, lighting control, data logging and other solar related applications.

  4. Sled Control and Safety System

    NASA Technical Reports Server (NTRS)

    Forrest, L. J.

    1982-01-01

    Computerized system for controlling motion of linear-track accelerator applied to other automated equipment, such as numerically-controlled machine tools and robot manipulators on assembly lines. System controls motions of sled with sine-wave signal created digitally by microprocessor. Dynamic parameters of sled motion are monitored so sled may be stopped safely if malfunction occurs. Sled is capable of sinusoidal accelerations up to 0.5 g with 125-kg load.

  5. A system for applying rapid warming or cooling stimuli to cells during patch clamp recording or ion imaging.

    PubMed

    Reid, G; Amuzescu, B; Zech, E; Flonta, M L

    2001-10-15

    We describe a system for superfusing small groups of cells at a precisely controlled and rapidly adjustable local temperature. Before being applied to the cell or cells under study, solutions are heated or cooled in a chamber of small volume ( approximately 150 microl) and large surface area, sandwiched between four small Peltier elements. The current through the Peltier elements is controlled by a microprocessor using a PID (proportional-integral-derivative) feedback algorithm. The chamber can be heated to at least 60 degrees C and cooled to 0 degrees C, changing its temperature at a maximum rate of about 7 degrees C per second; temperature ramps can be followed under feedback control at up to 4 degrees C per second. Temperature commands can be applied from the digital-to-analogue converter of any laboratory interface or generated digitally by the microprocessor. The peak-to-peak noise contributed by the system does not exceed that contributed by a patch pipette, holder and headstage, making it suitable for single channel as well as whole cell recordings.

  6. Bermuda Triangle: a subsystem of the 168/E interfacing scheme used by Group B at SLAC

    DOE Office of Scientific and Technical Information (OSTI.GOV)

    Oxoby, G.J.; Levinson, L.J.; Trang, Q.H.

    1979-12-01

    The Bermuda Triangle system is a method of interfacing several 168/E microprocessors to a central system for control of the processors and overlaying their memories. The system is a three-way interface with I/O ports to a large buffer memory, a PDP11 Unibus and a bus to the 168/E processors. Data may be transferred bidirectionally between any two ports. Two Bermuda Triangles are used, one for the program memory and one for the data memory. The program buffer memory stores the overlay programs for the 168/E, and the data buffer memory, the incoming raw data, the data portion of the overlays,more » and the outgoing processed events. This buffering is necessary since the memories of 168/E microprocessors are small compared to the main program and the amount of data being processed. The link to the computer facility is via a Unibus to IBM channel interface. A PDP11/04 controls the data flow. 7 figures, 4 tables. (RWR)« less

  7. 15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

    Code of Federal Regulations, 2012 CFR

    2012-01-01

    ... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

  8. 15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

    Code of Federal Regulations, 2010 CFR

    2010-01-01

    ... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

  9. 15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

    Code of Federal Regulations, 2013 CFR

    2013-01-01

    ... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

  10. 15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

    Code of Federal Regulations, 2011 CFR

    2011-01-01

    ... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

  11. Improved Training Program for Fall Prevention of Warfighters with Lower Extremity Trauma

    DTIC Science & Technology

    2016-10-01

    productive, active civilian life. The training program utilizes a microprocessor -controlled treadmill designed to deliver task- specific training...National Military Medical Center (WRNMMC), and Mayo. The fall prevention training program utilizes a microprocessor -controlled treadmill to deliver

  12. 15 CFR Supplement No. 1 to Part 744 - Military End-Use Examples for § 744.17

    Code of Federal Regulations, 2014 CFR

    2014-01-01

    ... part) of general-purpose microprocessors classified as ECCN 3A991.a.1 includes employing such microprocessors in the “use”, “development”, “production”, or deployment of: (1) Cruise missiles; (2) Electronic...

  13. Briefing: Microprocessors.

    ERIC Educational Resources Information Center

    Standing, Roy A.

    1982-01-01

    Reviews the basic concepts and technology behind the functions computers perform, describes the miniaturization of computer components, discusses the development of the microprocessor and the microcomputer, and makes projections concerning the future of the microcomputer market. Information is provided on the features, costs, and manufacturers of…

  14. Single-event upset in highly scaled commercial silicon-on-insulator PowerPc microprocessors

    NASA Technical Reports Server (NTRS)

    Irom, Farokh; Farmanesh, Farhad H.

    2004-01-01

    Single event upset effects from heavy ions are measured for Motorola and IBM silicon-on-insulator (SOI) microprocessors with different feature sizes, and core voltages. The results are compared with results for similar devices with build substrates. The cross sections of the SOI processors are lower than their bulk counterparts, but the threshold is about the same, even though the charge collections depth is more than an order of magnitude smaller in the SOI devices. The scaling of the cross section with reduction of feature size and core voltage dependence for SOI microprocessors discussed.

  15. Development of the self-learning machine for creating models of microprocessor of single-phase earth fault protection devices in networks with isolated neutral voltage above 1000 V

    NASA Astrophysics Data System (ADS)

    Utegulov, B. B.; Utegulov, A. B.; Meiramova, S.

    2018-02-01

    The paper proposes the development of a self-learning machine for creating models of microprocessor-based single-phase ground fault protection devices in networks with an isolated neutral voltage higher than 1000 V. Development of a self-learning machine for creating models of microprocessor-based single-phase earth fault protection devices in networks with an isolated neutral voltage higher than 1000 V. allows to effectively implement mathematical models of automatic change of protection settings. Single-phase earth fault protection devices.

  16. San Diego field operational test of smart call boxes : technical aspects

    DOT National Transportation Integrated Search

    1997-01-01

    Smart call boxes are devices similar to those used as emergency call boxes in California. The basic call box consists of a microprocessor, a cellular transceiver, and a solar power source. The smart call box system also includes data-collection devic...

  17. Microprocessor Control For Liquid-Cooled Garment

    NASA Technical Reports Server (NTRS)

    Weaver, Charles S.

    1990-01-01

    Automatic control system maintains temperature of water-cooled garment within comfort zone while wearer's level of physical activity varies. Uncomfortable overshoots and undershoots of temperature eliminated. Designed for use in space suit, adaptable to other protective garments and to enclosed environments operating according to similar principles.

  18. A mechanized process algebra for verification of device synchronization protocols

    NASA Technical Reports Server (NTRS)

    Schubert, E. Thomas

    1992-01-01

    We describe the formalization of a process algebra based on CCS within the Higher Order Logic (HOL) theorem-proving system. The representation of four types of device interactions and a correctness proof of the communication between a microprocessor and MMU is presented.

  19. Technology transfer of military space microprocessor developments

    NASA Astrophysics Data System (ADS)

    Gorden, C.; King, D.; Byington, L.; Lanza, D.

    1999-01-01

    Over the past 13 years the Air Force Research Laboratory (AFRL) has led the development of microprocessors and computers for USAF space and strategic missile applications. As a result of these Air Force development programs, advanced computer technology is available for use by civil and commercial space customers as well. The Generic VHSIC Spaceborne Computer (GVSC) program began in 1985 at AFRL to fulfill a deficiency in the availability of space-qualified data and control processors. GVSC developed a radiation hardened multi-chip version of the 16-bit, Mil-Std 1750A microprocessor. The follow-on to GVSC, the Advanced Spaceborne Computer Module (ASCM) program, was initiated by AFRL to establish two industrial sources for complete, radiation-hardened 16-bit and 32-bit computers and microelectronic components. Development of the Control Processor Module (CPM), the first of two ASCM contract phases, concluded in 1994 with the availability of two sources for space-qualified, 16-bit Mil-Std-1750A computers, cards, multi-chip modules, and integrated circuits. The second phase of the program, the Advanced Technology Insertion Module (ATIM), was completed in December 1997. ATIM developed two single board computers based on 32-bit reduced instruction set computer (RISC) processors. GVSC, CPM, and ATIM technologies are flying or baselined into the majority of today's DoD, NASA, and commercial satellite systems.

  20. Development of single cell protectors for sealed silver-zinc cells, phase 1

    NASA Technical Reports Server (NTRS)

    Imamura, M. S.; Donovan, R. L.; Lear, J. W.; Murray, B.

    1976-01-01

    A single cell protector (SCP) assembly capable of protecting a single silver-zinc (Ag Zn) battery cell was designed, fabricated, and tested. The SCP provides cell-level protection against overcharge and overdischarge by a bypass circuit. The bypass circuit consists of a magnetic-latching relay that is controlled by the high and low-voltage limit comparators. Although designed specifically for secondary Ag-Zn cells, the SCP is flexible enough to be adapted to other rechargeable cells. Eighteen SCPs were used in life testing of an 18-cell battery. The cells were sealed Ag-Zn system with inorganic separators. For comparison, another 18-cell battery was subjected to identical life test conditions, but with battery-level protection rather than cell-level. An alternative approach to the SCP design in the form of a microprocessor-based system was conceptually designed. The comparison of SCP and microprocessor approaches is also presented and a preferred approach for Ag-Zn battery protection is discussed.

  1. Automatic feedback to promote safe walking and speech loudness control in persons with multiple disabilities: two single-case studies.

    PubMed

    Lancioni, Giulio E; Singh, Nirbhay N; O'Reilly, Mark F; Green, Vanessa A; Alberti, Gloria; Boccasini, Adele; Smaldone, Angela; Oliva, Doretta; Bosco, Andrea

    2014-08-01

    Assessing automatic feedback technologies to promote safe travel and speech loudness control in two men with multiple disabilities, respectively. The men were involved in two single-case studies. In Study I, the technology involved a microprocessor, two photocells, and a verbal feedback device. The man received verbal alerting/feedback when the photocells spotted an obstacle in front of him. In Study II, the technology involved a sound-detecting unit connected to a throat and an airborne microphone, and to a vibration device. Vibration occurred when the man's speech loudness exceeded a preset level. The man included in Study I succeeded in using the automatic feedback in substitution of caregivers' alerting/feedback for safe travel. The man of Study II used the automatic feedback to successfully reduce his speech loudness. Automatic feedback can be highly effective in helping persons with multiple disabilities improve their travel and speech performance.

  2. Comparative biomechanical analysis of current microprocessor-controlled prosthetic knee joints.

    PubMed

    Bellmann, Malte; Schmalz, Thomas; Blumentritt, Siegmar

    2010-04-01

    To investigate and identify functional differences of 4 microprocessor-controlled prosthetic knee joints (C-Leg, Hybrid Knee [also called Energy Knee], Rheo Knee, Adaptive 2). Tested situations were walking on level ground, on stairs and ramps; additionally, the fall prevention potentials for each design were examined. The measuring technology used included an optoelectronic camera system combined with 2 forceplates as well as a mobile spiroergometric system. The study was conducted in a gait laboratory. Subjects with unilateral transfemoral amputations (N=9; mobility grade, 3-4; age, 22-49y) were tested. Participants were fitted and tested with 4 different microprocessor-controlled knee joints. Static prosthetic alignment, time distance parameters, kinematic and kinetic data and metabolic energy consumption. Compared with the Hybrid Knee and the Adaptive 2, the C-Leg offers clear advantages in the provision of adequate swing phase flexion resistances and terminal extension damping during level walking at various speeds, especially at higher walking speeds. The Rheo Knee provides sufficient terminal extension; however, swing phase flexion resistances seem to be too low. The values for metabolic energy consumption show only slight differences during level walking. The joint resistances generated for descending stairs and ramps relieve the contralateral side to varying degrees. When walking on stairs, safety-relevant technical differences between the investigated joint types can be observed. Designs with adequate internal resistances offer stability advantages when the foot is positioned on the step. Stumble recovery tests reveal that the different knee joint designs vary in their effectiveness in preventing the patient from falling. The patient benefits provided by the investigated electronic prosthetic knee joints differ considerably. The C-Leg appears to offer the amputee greater functional and safety-related advantages than the other tested knee joints. Reduced loading of the contralateral side has been demonstrated during ramp and stair descent. Metabolic energy consumption does not vary significantly between the tested knees. Hence, this parameter seems not to be a suitable criterion for assessing microprocessor-controlled knee components. Copyright 2010 American Congress of Rehabilitation Medicine. Published by Elsevier Inc. All rights reserved.

  3. Educational Implications of Microelectronics and Microprocessors.

    ERIC Educational Resources Information Center

    Harris, N. D. C., Ed.

    This conference report explores microelectronic technology, its effect on educational methods and objectives, and its implications for educator responsibilities. Two main areas were considered: the significance of the likely impact of the large scale introduction of microprocessors and microelectronics on commercial and industrial processes, the…

  4. Variable-thermoinsulation garments with a microprocessor temperature controller.

    PubMed

    Kurczewska, Agnieszka; Leánikowski, Jacek

    2008-01-01

    This paper presents the concept of active variable thermoinsulation clothing for users working in low temperatures. Those garments contain heating inserts regulated by a microprocessor temperature controller. This paper also presents the results of tests carried out on the newly designed garments.

  5. The quality of life analysis of knee prosthesis with complete microprocessor control in trans-femoral amputees.

    PubMed

    Saglam, Yavuz; Gulenc, Baris; Birisik, Fevzi; Ersen, Ali; Yilmaz Yalcinkaya, Ebru; Yazicioglu, Onder

    2017-12-01

    The aim of this study was to analyze the patient demographics, etiology of limb loss as well as reporting SF-36 scores for microprocessor prosthesis users in Turkish population. We reviewed 72 patients (61 male and 11 female; mean age: 37.7 ± 10.7) with uni-lateral, above knee amputation and a history of regular and microprocessor prosthesis use. All patients were called back for a last follow-up and they were asked to fill a self-administered general health status questionnaire (SF-36). According to the SF-36 results; physical component score (PCS) score was 46 ± 7.3 and mental components summary (MCS) score was 46.5 ± 9.1. These scores have statistical similarity with Turkish healthy controls, except SF (social functioning) sub-dimension. PCS score for women microprocessor users were significantly lower than men (43.3 vs. 48.7, p = 0.03), but MCS scores were similar in between genders (46 vs. 48.2, p = 0.13). Conventional prostheses usage time was positively correlated with physical function (PF) scores (r = 0.322, p = 0.010). Microprocessor prosthesis usage time was negatively correlated with role limitations due to emotional problem (RE) scores (r = -0,313, p = 0.009). The quality of life surveys were showed that the loss of an extremity have higher physical and psychological impact on women's physical scores. Overall, SF-36 results were similar in microprocessor using amputee's and Turkish normal controls. Level IV, therapeutic study. Copyright © 2017 Turkish Association of Orthopaedics and Traumatology. Production and hosting by Elsevier B.V. All rights reserved.

  6. Intelligent editor/printer enhancements

    NASA Technical Reports Server (NTRS)

    Woodfill, M. C.; Pheanis, D. C.

    1983-01-01

    Microprocessor support hardware, software, and cross assemblers relating to the Motorola 6800 and 6809 process systems were developed. Pinter controller and intelligent CRT development are discussed. The user's manual, design specifications for the MC6809 version of the intelligent printer controller card, and a 132-character by 64-line intelligent CRT display system using a Motorola 6809 MPU, and a one-line assembler and disassembler are provided.

  7. Multi-sensor Array for High Altitude Balloon Missions to the Stratosphere

    NASA Astrophysics Data System (ADS)

    Davis, Tim; McClurg, Bryce; Sohl, John

    2008-10-01

    We have designed and built a microprocessor controlled and expandable multi-sensor array for data collection on near space missions. Weber State University has started a high altitude research balloon program called HARBOR. This array has been designed to data log a base set of measurements for every flight and has room for six guest instruments. The base measurements are absolute pressure, on-board temperature, 3-axis accelerometer for attitude measurement, and 2-axis compensated magnetic compass. The system also contains a real time clock and circuitry for logging data directly to a USB memory stick. In typical operation the measurements will be cycled through in sequence and saved to the memory stick along with the clock's time stamp. The microprocessor can be reprogrammed to adapt to guest experiments with either analog or digital interfacing. This system will fly with every mission and will provide backup data collection for other instrumentation for which the primary task is measuring atmospheric pressure and temperature. The attitude data will be used to determine the orientation of the onboard camera systems to aid in identifying features in the images. This will make these images easier to use for any future GIS (geographic information system) remote sensing missions.

  8. Fast Initialization of Bubble-Memory Systems

    NASA Technical Reports Server (NTRS)

    Looney, K. T.; Nichols, C. D.; Hayes, P. J.

    1986-01-01

    Improved scheme several orders of magnitude faster than normal initialization scheme. State-of-the-art commercial bubble-memory device used. Hardware interface designed connects controlling microprocessor to bubblememory circuitry. System software written to exercise various functions of bubble-memory system in comparison made between normal and fast techniques. Future implementations of approach utilize E2PROM (electrically-erasable programable read-only memory) to provide greater system flexibility. Fastinitialization technique applicable to all bubble-memory devices.

  9. Developing prescribing guidelines for microprocessor-controlled prosthetic knees in the South East England.

    PubMed

    Sedki, Imad; Fisher, Keren

    2015-06-01

    Microprocessor-controlled prosthetic knees have gained increasing popularity over the last decade. Research supports their provision to address specific problems or to achieve certain rehabilitation goals. However, there are yet no agreed protocols or prescribing criteria to assist clinicians in the identification and appropriate selection of suitable users. The aim is to reach professionals' agreement on specific prescribing guidelines for microprocessor-controlled prosthetic knees. The study involved multidisciplinary teams from the Inter Regional Prosthetic Audit Group, representing nine Prosthetic Rehabilitation Centres in the South East England region. We used the Delphi technique with a total of three rounds to reach professionals' agreement. The prescribing guidelines were agreed and will be reviewed and updated depending on new research evidence and technical advances. This project is highly useful for professionals in a clinic setting to aid in appropriate patient selection and to justify the cost of prescribing microprocessor-controlled prosthetic knees. © The International Society for Prosthetics and Orthotics 2014.

  10. Microprocessor, Setx, Xrn2, and Rrp6 co-operate to induce premature termination of transcription by RNAPII.

    PubMed

    Wagschal, Alexandre; Rousset, Emilie; Basavarajaiah, Poornima; Contreras, Xavier; Harwig, Alex; Laurent-Chabalier, Sabine; Nakamura, Mirai; Chen, Xin; Zhang, Ke; Meziane, Oussama; Boyer, Frédéric; Parrinello, Hugues; Berkhout, Ben; Terzian, Christophe; Benkirane, Monsef; Kiernan, Rosemary

    2012-09-14

    Transcription elongation is increasingly recognized as an important mechanism of gene regulation. Here, we show that microprocessor controls gene expression in an RNAi-independent manner. Microprocessor orchestrates the recruitment of termination factors Setx and Xrn2, and the 3'-5' exoribonuclease, Rrp6, to initiate RNAPII pausing and premature termination at the HIV-1 promoter through cleavage of the stem-loop RNA, TAR. Rrp6 further processes the cleavage product, which generates a small RNA that is required to mediate potent transcriptional repression and chromatin remodeling at the HIV-1 promoter. Using chromatin immunoprecipitation coupled to high-throughput sequencing (ChIP-seq), we identified cellular gene targets whose transcription is modulated by microprocessor. Our study reveals RNAPII pausing and premature termination mediated by the co-operative activity of ribonucleases, Drosha/Dgcr8, Xrn2, and Rrp6, as a regulatory mechanism of RNAPII-dependent transcription elongation. Copyright © 2012 Elsevier Inc. All rights reserved.

  11. Inhibition of Microprocessor Function during the Activation of the Type I Interferon Response.

    PubMed

    Witteveldt, Jeroen; Ivens, Alasdair; Macias, Sara

    2018-06-12

    Type I interferons (IFNs) are central components of the antiviral response. Most cell types respond to viral infections by secreting IFNs, but the mechanisms that regulate correct expression of these cytokines are not completely understood. Here, we show that activation of the type I IFN response regulates the expression of miRNAs in a post-transcriptional manner. Activation of IFN expression alters the binding of the Microprocessor complex to pri-miRNAs, reducing its processing rate and thus leading to decreased levels of a subset of mature miRNAs in an IRF3-dependent manner. The rescue of Microprocessor function during the antiviral response downregulates the levels of IFN-β and IFN-stimulated genes. All these findings support a model by which the inhibition of Microprocessor activity is an essential step to induce a robust type I IFN response in mammalian cells. Copyright © 2018 The Author(s). Published by Elsevier Inc. All rights reserved.

  12. Gait asymmetry of transfemoral amputees using mechanical and microprocessor-controlled prosthetic knees.

    PubMed

    Kaufman, Kenton R; Frittoli, Serena; Frigo, Carlo A

    2012-06-01

    Amputees walk with an asymmetrical gait, which may lead to future musculoskeletal degenerative changes. The purpose of this study was to compare the gait asymmetry of active transfemoral amputees while using a passive mechanical knee joint or a microprocessor-controlled knee joint. Objective 3D gait measurements were obtained in 15 subjects (12 men and 3 women; age 42, range 26-57). Research participants were longtime users of a mechanical prosthesis (mean 20 years, range 3-36 years). Joint symmetry was calculated using a novel method that includes the entire waveform throughout the gait cycle. There was no significant difference in hip, knee and ankle kinematics symmetry when using the different knee prostheses. In contrast, the results demonstrated a significant improvement in lower extremity joint kinetics symmetry when using the microprocessor-controlled knee. Use of the microprocessor-controlled knee joint resulted in improved gait symmetry. These improvements may lead to a reduction in the degenerative musculoskeletal changes often experienced by amputees. Copyright © 2011 Elsevier Ltd. All rights reserved.

  13. Description and Applications for an Automated Inertial Azimuth Measuring System,

    DTIC Science & Technology

    specialized field environment. The present system consists of two integrated inertial sensors , an angle transfer system, a tiltmeter array and a...optical path. Highly sensitive tiltmeters are used to measure and correct for errors due to base motions of the inertial sensors . Data handling and...microprocessor. The inertial sensors use gimbal-mounted rate gyrocompasses to indicate the azimuths of two transfer mirrors with respect to true North. The

  14. Electronic and software subsystems for an autonomous roving vehicle. M.S. Thesis

    NASA Technical Reports Server (NTRS)

    Doig, G. A.

    1980-01-01

    The complete electronics packaging which controls the Mars roving vehicle is described in order to provide a broad overview of the systems that are part of that package. Some software debugging tools are also discussed. Particular emphasis is given to those systems that are controlled by the microprocessor. These include the laser mast, the telemetry system, the command link prime interface board, and the prime software.

  15. Intercommunications in Real Time, Redundant, Distributed Computer System

    NASA Technical Reports Server (NTRS)

    Zanger, H.

    1980-01-01

    An investigation into the applicability of fiber optic communication techniques to real time avionic control systems, in particular the total automatic flight control system used for the VSTOL aircraft is presented. The system consists of spatially distributed microprocessors. The overall control function is partitioned to yield a unidirectional data flow between the processing elements (PE). System reliability is enhanced by the use of triple redundancy. Some general overall system specifications are listed here to provide the necessary background for the requirements of the communications system.

  16. A preferential design approach for energy-efficient and robust implantable neural signal processing hardware.

    PubMed

    Narasimhan, Seetharam; Chiel, Hillel J; Bhunia, Swarup

    2009-01-01

    For implantable neural interface applications, it is important to compress data and analyze spike patterns across multiple channels in real time. Such a computational task for online neural data processing requires an innovative circuit-architecture level design approach for low-power, robust and area-efficient hardware implementation. Conventional microprocessor or Digital Signal Processing (DSP) chips would dissipate too much power and are too large in size for an implantable system. In this paper, we propose a novel hardware design approach, referred to as "Preferential Design" that exploits the nature of the neural signal processing algorithm to achieve a low-voltage, robust and area-efficient implementation using nanoscale process technology. The basic idea is to isolate the critical components with respect to system performance and design them more conservatively compared to the noncritical ones. This allows aggressive voltage scaling for low power operation while ensuring robustness and area efficiency. We have applied the proposed approach to a neural signal processing algorithm using the Discrete Wavelet Transform (DWT) and observed significant improvement in power and robustness over conventional design.

  17. A Low Noise, Microprocessor-Controlled, Internally Digitizing Rotating-Vane Electric Field Mill for Airborne Platforms

    NASA Technical Reports Server (NTRS)

    Bateman, M. G.; Stewart, M. F.; Blakeslee, R. J.; Podgorny, s. J.; Christian, H. J.; Mach, D. M.; Bailey, J. C.; Daskar, D.

    2006-01-01

    This paper reports on a new generation of aircraft-based rotating-vane style electric field mills designed and built at NASA's Marshall Spaceflight Center. The mills have individual microprocessors that digitize the electric field signal at the mill and respond to commands from the data system computer. The mills are very sensitive (1 V/m per bit), have a wide dynamic range (115 dB), and are very low noise (+/-1 LSB). Mounted on an aircraft, these mills can measure fields from +/-1 V/m to +/-500 kV/m. Once-per-second commanding from the data collection computer to each mill allows for precise timing and synchronization. The mills can also be commanded to execute a self-calibration in flight, which is done periodically to monitor the status and health of each mill.

  18. Study of limitations and attributes of microprocessor testing techniques

    NASA Technical Reports Server (NTRS)

    Mccaskill, R.; Sohl, W. E.

    1977-01-01

    All microprocessor units have a similar architecture from which a basic test philosophy can be adopted and used to develop an approach to test each module separately in order to verify the functionality of each module within the device using the input/output pins of the device and its instruction set; test for destructive interaction between functional modules; and verify all timing, status information, and interrupt operations of the device. Block and test flow diagrams are given for the 8080, 8008, 2901, 6800, and 1802 microprocessors. Manufacturers are listed and problems encountered in testing the modules are discussed. Test equipment and methods are described.

  19. Method and apparatus for reading free falling dosimeter punchcodes

    DOEpatents

    Langsted, James M.

    1992-12-22

    A punchcode reader is provided for reading data encoded in a punchcode hole array on a dosimeter. The dosimeter falls through a passage in the reader containing photosensor detectors disposed along the passage which provide output signals to a microprocessor. The signals are processed to determine the orientation of the dosimeter in the reader, the location and state of punchcode holes in a two row array thereby decoding the encoded data. Multiple rate of fall calculations are made, and if appropriate matching of the punchcode array is not obtained in three tries, an error signal is outputted to the operator. The punchcode reader also provides for storage of data from multiple dosimeters passed through the reader, and for the output of decoded data to an external display or a computer for further processing.

  20. Work and Programmable Automation.

    ERIC Educational Resources Information Center

    DeVore, Paul W.

    A new industrial era based on electronics and the microprocessor has arrived, an era that is being called intelligent automation. Intelligent automation, in the form of robots, replaces workers, and the new products, using microelectronic devices, require significantly less labor to produce than the goods they replace. The microprocessor thus…

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