Large-area low-temperature ultrananocrystaline diamond (UNCD) films and integration with CMOS devices for monolithically integrated diamond MEMD/NEMS-CMOS systems.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sumant, A.V.; Auciello, O.; Yuan, H.-C

2009-05-01

Because of exceptional mechanical, chemical, and tribological properties, diamond has a great potential to be used as a material for the development of high-performance MEMS and NEMS such as resonators and switches compatible with harsh environments, which involve mechanical motion and intermittent contact. Integration of such MEMS/NEMS devices with complementary metal oxide semiconductor (CMOS) microelectronics will provide a unique platform for CMOS-driven commercial MEMS/NEMS. The main hurdle to achieve diamond-CMOS integration is the relatively high substrate temperatures (600-800 C) required for depositing conventional diamond thin films, which are well above the CMOS operating thermal budget (400 C). Additionally, a materialsmore » integration strategy has to be developed to enable diamond-CMOS integration. Ultrananocrystalline diamond (UNCD), a novel material developed in thin film form at Argonne, is currently the only microwave plasma chemical vapor deposition (MPCVD) grown diamond film that can be grown at 400 C, and still retain exceptional mechanical, chemical, and tribological properties comparable to that of single crystal diamond. We have developed a process based on MPCVD to synthesize UNCD films on up to 200 mm in diameter CMOS wafers, which will open new avenues for the fabrication of monolithically integrated CMOS-driven MEMS/NEMS based on UNCD. UNCD films were grown successfully on individual Si-based CMOS chips and on 200 mm CMOS wafers at 400 C in a MPCVD system, using Ar-rich/CH4 gas mixture. The CMOS devices on the wafers were characterized before and after UNCD deposition. All devices were performing to specifications with very small degradation after UNCD deposition and processing. A threshold voltage degradation in the range of 0.08-0.44V and transconductance degradation in the range of 1.5-9% were observed.« less

Lanthanum Gadolinium Oxide: A New Electronic Device Material for CMOS Logic and Memory Devices

PubMed Central

Pavunny, Shojan P.; Scott, James F.; Katiyar, Ram S.

2014-01-01

A comprehensive study on the ternary dielectric, LaGdO3, synthesized and qualified in our laboratory as a novel high-k dielectric material for logic and memory device applications in terms of its excellent features that include a high linear dielectric constant (k) of ~22 and a large energy bandgap of ~5.6 eV, resulting in sufficient electron and hole band offsets of ~2.57 eV and ~1.91 eV, respectively, on silicon, good thermal stability with Si and lower gate leakage current densities within the International Technology Roadmap for Semiconductors (ITRS) specified limits at the sub-nanometer electrical functional thickness level, which are desirable for advanced complementary metal-oxide-semiconductor (CMOS), bipolar (Bi) and BiCMOS chips applications, is presented in this review article. PMID:28788589

Highly Flexible Hybrid CMOS Inverter Based on Si Nanomembrane and Molybdenum Disulfide.

PubMed

Das, Tanmoy; Chen, Xiang; Jang, Houk; Oh, Il-Kwon; Kim, Hyungjun; Ahn, Jong-Hyun

2016-11-01

2D semiconductor materials are being considered for next generation electronic device application such as thin-film transistors and complementary metal-oxide-semiconductor (CMOS) circuit due to their unique structural and superior electronics properties. Various approaches have already been taken to fabricate 2D complementary logics circuits. However, those CMOS devices mostly demonstrated based on exfoliated 2D materials show the performance of a single device. In this work, the design and fabrication of a complementary inverter is experimentally reported, based on a chemical vapor deposition MoS 2 n-type transistor and a Si nanomembrane p-type transistor on the same substrate. The advantages offered by such CMOS configuration allow to fabricate large area wafer scale integration of high performance Si technology with transition-metal dichalcogenide materials. The fabricated hetero-CMOS inverters which are composed of two isolated transistors exhibit a novel high performance air-stable voltage transfer characteristic with different supply voltages, with a maximum voltage gain of ≈16, and sub-nano watt power consumption. Moreover, the logic gates have been integrated on a plastic substrate and displayed reliable electrical properties paving a realistic path for the fabrication of flexible/transparent CMOS circuits in 2D electronics. © 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

NASA Astrophysics Data System (ADS)

Oukacha, Hassan

The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

Variation and Defect Tolerance for Nano Crossbars

NASA Astrophysics Data System (ADS)

Tunc, Cihan

With the extreme shrinking in CMOS technology, quantum effects and manufacturing issues are getting more crucial. Hence, additional shrinking in CMOS feature size seems becoming more challenging, difficult, and costly. On the other hand, emerging nanotechnology has attracted many researchers since additional scaling down has been demonstrated by manufacturing nanowires, Carbon nanotubes as well as molecular switches using bottom-up manufacturing techniques. In addition to the progress in manufacturing, developments in architecture show that emerging nanoelectronic devices will be promising for the future system designs. Using nano crossbars, which are composed of two sets of perpendicular nanowires with programmable intersections, it is possible to implement logic functions. In addition, nano crossbars present some important features as regularity, reprogrammability, and interchangeability. Combining these features, researchers have presented different effective architectures. Although bottom-up nanofabrication can greatly reduce manufacturing costs, due to low controllability in the manufacturing process, some critical issues occur. Bottom- up nanofabrication process results in high variation compared to conventional top- down lithography used in CMOS technology. In addition, an increased failure rate is expected. Variation and defect tolerance methods used for conventional CMOS technology seem inadequate for adapting to emerging nano technology because the variation and the defect rate for emerging nano technology is much more than current CMOS technology. Therefore, variations and defect tolerance methods for emerging nano technology are necessary for a successful transition. In this work, in order to tolerate variations for crossbars, we introduce a framework that is established based on reprogrammability and interchangeability features of nano crossbars. This framework is shown to be applicable for both FET-based and diode-based nano crossbars. We present a

1-dimension nano-material-based flexible device

NASA Astrophysics Data System (ADS)

Yang, Xing; Zhou, Zhaoying; Zheng, Fuzhong

2009-11-01

1D nano-material-based flexible devices has attracted considerable attention owing to the growing need of the high-sensitivity flexible sensor, portable consumer electronics etc.. In this paper, the 1D nano-materials-based flexible device on polyimide substrate was proposed. The bottom-up and top-down combined process were used for constructing the ZnO nanowire and the CNT-based flexible devices. Their electrical characteristics were also investigated. The measurement results demonstrate that the flexible device covered with a layer of Al2O3 has good ohm electrical contact behavior between the nano-material and micro-electrodes. The proposed 1D nano-material-based flexible device shows the application potential in the sensing fields.

Millimeter wave complementary metal-oxide-semiconductor on-chip hexagonal nano-ferrite circulator

NASA Astrophysics Data System (ADS)

Chao, Liu; Oukacha, Hassan; Fu, Enjin; Koomson, Valencia Joyner; Afsar, Mohammed N.

2015-05-01

Hexagonal ferrites such as M-type BaFe12O19 and SrFe12O19 have strong uniaxial anisotropic magnetic field and remanent magnetism. The nano-sized ferrite powder exhibits high compatibility and processability in composite material. New magnetic devices using the M-type ferrite materials can work in the tens of GHz frequency range from microwave to millimeter wave without the application of strong external magnetic field. The micro- and nano-sized hexagonal ferrite can be conveniently utilized to fabricate magnetic components integrated in CMOS integrated circuits as thin as several micrometers. The micro-fabrication method of such nano ferrite device is presented in this paper. A circulator working at 60 GHz is designed and integrated into the commercial CMOS process. The circulator exhibits distinct circulation properties in the frequency range from 56 GHz to 58 GHz.

CMOS-compatible photonic devices for single-photon generation

NASA Astrophysics Data System (ADS)

Xiong, Chunle; Bell, Bryn; Eggleton, Benjamin J.

2016-09-01

Sources of single photons are one of the key building blocks for quantum photonic technologies such as quantum secure communication and powerful quantum computing. To bring the proof-of-principle demonstration of these technologies from the laboratory to the real world, complementary metal-oxide-semiconductor (CMOS)-compatible photonic chips are highly desirable for photon generation, manipulation, processing and even detection because of their compactness, scalability, robustness, and the potential for integration with electronics. In this paper, we review the development of photonic devices made from materials (e.g., silicon) and processes that are compatible with CMOS fabrication facilities for the generation of single photons.

CMOS-based optical energy harvesting circuit for biomedical and Internet of Things devices

NASA Astrophysics Data System (ADS)

Nattakarn, Wuthibenjaphonchai; Ishizu, Takaaki; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a novel CMOS-based optical energy harvesting technology for implantable and Internet of Things (IoT) devices. In the proposed system, a CMOS energy-harvesting circuit accumulates a small amount of photoelectrically converted energy in an external capacitor, and intermittently supplies this power to a target device. Two optical energy-harvesting circuit types were implemented and evaluated. Furthermore, we developed a photoelectrically powered optical identification (ID) circuit that is suitable for IoT technology applications.

Total Ionizing Dose Effects in Bipolar and BiCMOS Devices

NASA Technical Reports Server (NTRS)

Chavez, Rosa M.; Rax, Bernard G.; Scheick, Leif Z.; Johnston, Allan H.

2005-01-01

This paper describes total ionizing dose (TID) test results performed at JPL. Bipolar and BiCMOS device samples were tested exhibiting significant degradation and failures at different irradiation levels. Linear technology which is susceptible to low-dose dependency (ELDRS) exhibited greater damage for devices tested under zero bias condition.

Latchup in CMOS devices from heavy ions

NASA Technical Reports Server (NTRS)

Soliman, K.; Nichols, D. K.

1983-01-01

It is noted that complementary metal oxide semiconductor (CMOS) microcircuits are inherently latchup prone. The four-layer n-p-n-p structures formed from the parasitic pnp and npn transistors make up a silicon controlled rectifier. If properly biased, this rectifier may be triggered 'ON' by electrical transients, ionizing radiation, or a single heavy ion. This latchup phenomenon might lead to a loss of functionality or device burnout. Results are presented from tests on 19 different device types from six manufacturers which investigate their latchup sensitivity with argon and krypton beams. The parasitic npnp paths are identified in general, and a qualitative rationale is given for latchup susceptibility, along with a latchup cross section for each type of device. Also presented is the correlation between bit-flip sensitivity and latchup susceptibility.

A triple quantum dot based nano-electromechanical memory device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pozner, R.; Lifshitz, E.; Solid State Institute, Technion-Israel Institute of Technology, Haifa 32000

Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, “ON” and “OFF” states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Consideringmore » realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.« less

TID Simulation of Advanced CMOS Devices for Space Applications

NASA Astrophysics Data System (ADS)

Sajid, Muhammad

2016-07-01

This paper focuses on Total Ionizing Dose (TID) effects caused by accumulation of charges at silicon dioxide, substrate/silicon dioxide interface, Shallow Trench Isolation (STI) for scaled CMOS bulk devices as well as at Buried Oxide (BOX) layer in devices based on Silicon-On-Insulator (SOI) technology to be operated in space radiation environment. The radiation induced leakage current and corresponding density/concentration electrons in leakage current path was presented/depicted for 180nm, 130nm and 65nm NMOS, PMOS transistors based on CMOS bulk as well as SOI process technologies on-board LEO and GEO satellites. On the basis of simulation results, the TID robustness analysis for advanced deep sub-micron technologies was accomplished up to 500 Krad. The correlation between the impact of technology scaling and magnitude of leakage current with corresponding total dose was established utilizing Visual TCAD Genius program.

Multi-scale Modeling and Analysis of Nano-RFID Systems on HPC Setup

NASA Astrophysics Data System (ADS)

Pathak, Rohit; Joshi, Satyadhar

In this paper we have worked out on some the complex modeling aspects such as Multi Scale modeling, MATLAB Sugar based modeling and have shown the complexities involved in the analysis of Nano RFID (Radio Frequency Identification) systems. We have shown the modeling and simulation and demonstrated some novel ideas and library development for Nano RFID. Multi scale modeling plays a very important role in nanotech enabled devices properties of which cannot be explained sometimes by abstraction level theories. Reliability and packaging still remains one the major hindrances in practical implementation of Nano RFID based devices. And to work on them modeling and simulation will play a very important role. CNTs is the future low power material that will replace CMOS and its integration with CMOS, MEMS circuitry will play an important role in realizing the true power in Nano RFID systems. RFID based on innovations in nanotechnology has been shown. MEMS modeling of Antenna, sensors and its integration in the circuitry has been shown. Thus incorporating this we can design a Nano-RFID which can be used in areas like human implantation and complex banking applications. We have proposed modeling of RFID using the concept of multi scale modeling to accurately predict its properties. Also we give the modeling of MEMS devices that are proposed recently that can see possible application in RFID. We have also covered the applications and the advantages of Nano RFID in various areas. RF MEMS has been matured and its devices are being successfully commercialized but taking it to limits of nano domains and integration with singly chip RFID needs a novel approach which is being proposed. We have modeled MEMS based transponder and shown the distribution for multi scale modeling for Nano RFID.

Indium-oxide nanoparticles for RRAM devices compatible with CMOS back-end-off-line

NASA Astrophysics Data System (ADS)

León Pérez, Edgar A. A.; Guenery, Pierre-Vincent; Abouzaid, Oumaïma; Ayadi, Khaled; Brottet, Solène; Moeyaert, Jérémy; Labau, Sébastien; Baron, Thierry; Blanchard, Nicholas; Baboux, Nicolas; Militaru, Liviu; Souifi, Abdelkader

2018-05-01

We report on the fabrication and characterization of Resistive Random Access Memory (RRAM) devices based on nanoparticles in MIM structures. Our approach is based on the use of indium oxide (In2O3) nanoparticles embedded in a dielectric matrix using CMOS-full-compatible fabrication processes in view of back-end-off-line integration for non-volatile memory (NVM) applications. A bipolar switching behavior has been observed using current-voltage measurements (I-V) for all devices. Very high ION/IOFF ratios have been obtained up to 108. Our results provide insights for further integration of In2O3 nanoparticles-based devices for NVM applications. He is currently a Postdoctoral Researcher in the Institute of Nanotechnologies of Lyon (INL), INSA de Lyon, France, in the Electronics Department. His current research include indium oxide nanoparticles for non-volatile memory applications, and the integrations of these devices in CMOS BEOL.

Hybrid CMOS/Molecular Integrated Circuits

NASA Astrophysics Data System (ADS)

Stan, M. R.; Rose, G. S.; Ziegler, M. M.

CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

Performance of current-in-plane pseudo-spin-valve devices on CMOS silicon-on-insulator underlayers

NASA Astrophysics Data System (ADS)

Katti, R. R.; Zou, D.; Reed, D.; Schipper, D.; Hynes, O.; Shaw, G.; Kaakani, H.

2003-05-01

Prior work has shown that current-in-plane (CIP) giant magnetoresistive (GMR) pseudo-spin-valve (PSV) devices grown on bulk Si wafers and bulk complementary metal-oxide semiconductor (CMOS) underlayers exhibit write and read characteristics that are suitable for application as nonvolatile memory devices. In this work, CIP GMR PSV devices fabricated on silicon-on-insulator CMOS underlayers are shown to support write and read performance. Reading and writing fields for selected devices are shown to be approximately 25%-50% that of unselected devices, which provides a margin for reading and writing specific bits in a memory without overwriting bits and without disturbing other bits. The switching characteristics of experimental devices were compared to and found to be similar with Landau-Lifschitz-Gilbert micromagnetic modeling results, which allowed inferring regions of reversible and irreversible rotations in magnetic reversal processes.

Nano-cone resistive memory for ultralow power operation.

PubMed

Kim, Sungjun; Jung, Sunghun; Kim, Min-Hwi; Kim, Tae-Hyeon; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

2017-03-24

SiN x -based nano-structure resistive memory is fabricated by fully silicon CMOS compatible process integration including particularly designed anisotropic etching for the construction of a nano-cone silicon bottom electrode (BE). Bipolar resistive switching characteristics have significantly reduced switching current and voltage and are demonstrated in a nano-cone BE structure, as compared with those in a flat BE one. We have verified by systematic device simulations that the main cause of reduction in the performance parameters is the high electric field being more effectively concentrated at the tip of the cone-shaped BE. The greatly improved nonlinearity of the nano-cone resistive memory cell will be beneficial in the ultra-high-density crossbar array.

Programmable Nano-Bio Interfaces for Functional Biointegrated Devices.

PubMed

Cai, Pingqiang; Leow, Wan Ru; Wang, Xiaoyuan; Wu, Yun-Long; Chen, Xiaodong

2017-07-01

A large amount of evidence has demonstrated the revolutionary role of nanosystems in the screening and shielding of biological systems. The explosive development of interfacing bioentities with programmable nanomaterials has conveyed the intriguing concept of nano-bio interfaces. Here, recent advances in functional biointegrated devices through the precise programming of nano-bio interactions are outlined, especially with regard to the rational assembly of constituent nanomaterials on multiple dimension scales (e.g., nanoparticles, nanowires, layered nanomaterials, and 3D-architectured nanomaterials), in order to leverage their respective intrinsic merits for different functions. Emerging nanotechnological strategies at nano-bio interfaces are also highlighted, such as multimodal diagnosis or "theragnostics", synergistic and sequential therapeutics delivery, and stretchable and flexible nanoelectronic devices, and their implementation into a broad range of biointegrated devices (e.g., implantable, minimally invasive, and wearable devices). When utilized as functional modules of biointegrated devices, these programmable nano-bio interfaces will open up a new chapter for precision nanomedicine. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Prediction and measurement of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Cliff, R. A.; Danchenko, V.; Stassinopoulos, E. G.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1976-01-01

The initial results obtained from the Complementary Metal Oxide Semiconductors Radiation Effects Measurement experiment are presented. Predictions of radiation damage to C-MOS devices are based on standard environment models and computational techniques. A comparison of the shifts in CMOS threshold potentials, that is, those measured in space to those obtained from the on the ground simulation experiment with Co 60, indicated that the measured space damage is greater than predicted by a factor of two for shields thicker than 100 mils (2.54 mm), but agrees well with predictions for the thinner shields.

Boolean and brain-inspired computing using spin-transfer torque devices

NASA Astrophysics Data System (ADS)

Fan, Deliang

Several completely new approaches (such as spintronic, carbon nanotube, graphene, TFETs, etc.) to information processing and data storage technologies are emerging to address the time frame beyond current Complementary Metal-Oxide-Semiconductor (CMOS) roadmap. The high speed magnetization switching of a nano-magnet due to current induced spin-transfer torque (STT) have been demonstrated in recent experiments. Such STT devices can be explored in compact, low power memory and logic design. In order to truly leverage STT devices based computing, researchers require a re-think of circuit, architecture, and computing model, since the STT devices are unlikely to be drop-in replacements for CMOS. The potential of STT devices based computing will be best realized by considering new computing models that are inherently suited to the characteristics of STT devices, and new applications that are enabled by their unique capabilities, thereby attaining performance that CMOS cannot achieve. The goal of this research is to conduct synergistic exploration in architecture, circuit and device levels for Boolean and brain-inspired computing using nanoscale STT devices. Specifically, we first show that the non-volatile STT devices can be used in designing configurable Boolean logic blocks. We propose a spin-memristor threshold logic (SMTL) gate design, where memristive cross-bar array is used to perform current mode summation of binary inputs and the low power current mode spintronic threshold device carries out the energy efficient threshold operation. Next, for brain-inspired computing, we have exploited different spin-transfer torque device structures that can implement the hard-limiting and soft-limiting artificial neuron transfer functions respectively. We apply such STT based neuron (or 'spin-neuron') in various neural network architectures, such as hierarchical temporal memory and feed-forward neural network, for performing "human-like" cognitive computing, which show more than

Advancement of CMOS Doping Technology in an External Development Framework

NASA Astrophysics Data System (ADS)

Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

2011-01-01

The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

NASA Astrophysics Data System (ADS)

Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

2014-01-01

This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gao, X.; Mamaluy, D.; Cyr, E. C.

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

(Invited) Comprehensive Assessment of Oxide Memristors As Post-CMOS Memory and Logic Devices

DOE PAGES

Gao, X.; Mamaluy, D.; Cyr, E. C.; ...

2016-05-10

As CMOS technology approaches the end of its scaling, oxide-based memristors have become one of the leading candidates for post-CMOS memory and logic devices. In orderTo facilitate the understanding of physical switching mechanisms and accelerate experimental development of memristors, we have developed a three-dimensional fully-coupled electrical and thermal transport model, which captures all the important processes that drive memristive switching and is applicable for simulating a wide range of memristors. Moreover, the model is applied to simulate the RESET and SET switching in a 3D filamentary TaOx memristor. Extensive simulations show that the switching dynamics of the bipolar device ismore » determined by thermally-activated field-dominant processes: with Joule heating, the raised temperature enables the movement of oxygen vacancies, and the field drift dominates the overall motion of vacancies. Simulated current-voltage hysteresis and device resistance profiles as a function of time and voltage during RESET and SET switching show good agreement with experimental measurement.« less

Graphene/Si CMOS hybrid hall integrated circuits.

PubMed

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-07-07

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

Water soluble nano-scale transient material germanium oxide for zero toxic waste based environmentally benign nano-manufacturing

NASA Astrophysics Data System (ADS)

Almuslem, A. S.; Hanna, A. N.; Yapici, T.; Wehbe, N.; Diallo, E. M.; Kutbee, A. T.; Bahabry, R. R.; Hussain, M. M.

2017-02-01

In the recent past, with the advent of transient electronics for mostly implantable and secured electronic applications, the whole field effect transistor structure has been dissolved in a variety of chemicals. Here, we show simple water soluble nano-scale (sub-10 nm) germanium oxide (GeO2) as the dissolvable component to remove the functional structures of metal oxide semiconductor devices and then reuse the expensive germanium substrate again for functional device fabrication. This way, in addition to transiency, we also show an environmentally friendly manufacturing process for a complementary metal oxide semiconductor (CMOS) technology. Every year, trillions of complementary metal oxide semiconductor (CMOS) electronics are manufactured and billions are disposed, which extend the harmful impact to our environment. Therefore, this is a key study to show a pragmatic approach for water soluble high performance electronics for environmentally friendly manufacturing and bioresorbable electronic applications.

CMOS Image Sensor Using SOI-MOS/Photodiode Composite Photodetector Device

NASA Astrophysics Data System (ADS)

Uryu, Yuko; Asano, Tanemasa

2002-04-01

A new photodetector device composed of a lateral junction photodiode and a metal-oxide-semiconductor field-effect-transistor (MOSFET), in which the output of the diode is fed through the body of the MOSFET, has been investigated. It is shown that the silicon-on-insulator (SOI)-MOSFET amplifies the junction photodiode current due to the lateral bipolar action. It is also shown that the presence of the electrically floating gate enhances the current amplification factor of the SOI-MOSFET. The output current of this composite device linearly responds by four orders of illumination intensity. As an application of the composite device, a complementary-metal-oxide-semiconductor (CMOS) line sensor incorporating the composite device is fabricated and its operation is demonstrated. The output signal of the line sensor using the composite device was two times larger than that using the lateral photodiode.

Characterizations of and Radiation Effects in Several Emerging CMOS Technologies

NASA Astrophysics Data System (ADS)

Shufeng Ren

As the conventional scaling of Si based CMOS is approaching its limit at 7 nm technology node, many perceive that the adoption of novel materials and/or device structures are inevitable to keep Moore's law going. High mobility channel materials such as III-V compound semiconductors or Ge are considered promising to replace Si in order to achieve high performance as well as low power consumption. However, interface and oxide traps have become a major obstacle for high-mobility semiconductors (such as Ge, GaAs, InGaAs, GaSb, etc) to replace Si CMOS technology. Therefore novel high-k dielectrics, such as epitaxially grown crystalline oxides, have been explored to be incorporated onto the high mobility channel materials. Moreover, to enable continued scaling, extremely scaled devices structures such as nanowire gate-all-around structure are needed in the near future. Moreover, as the CMOS industry moves into the 7 nm node and beyond, novel lithography techniques such as EUV are believed to be adopted soon, which can bring radiation damage to CMOS devices and circuit during the fabrication process. Therefore radiation hardening technology in future generations of CMOS devices has again become an interesting research topic to deal with the possible process-induced damage as well as damage caused by operating in radiation harsh environment such as outer space, nuclear plant, etc. In this thesis, the electrical properties of a few selected emerging novel CMOS devices are investigated, which include InGaAs based extremely scaled ultra-thin body nanowire gate-all-around MOSFETs, GOI (Ge On Insulator) CMOS with recessed channel and source/drain, GaAs MOSFETs with crystalline La based gate stack, and crystalline SrTiO3, are investigated to extend our understanding of their electrical characteristics, underlying physical mechanisms, and material properties. Furthermore, the radiation responses of these aforementioned novel devices are thoroughly investigated, with a focus on

Fabrication of 1-dimension nano-material-based device and its electrical characteristics

NASA Astrophysics Data System (ADS)

Yang, Xing; Zhou, Zhaoying; Zheng, Fuzhong; Zhang, Min

2008-12-01

In recent years, many kinds of 1-dimension nano-materials (Carbon nanotube, ZnO nanobelt and nanowire etc.) continue to emerge which exhibit distinct and unique electromechanical, piezoelectric, photoelectrical properties. In this paper, a 1-dimension nano-materials-based device was proposed. The bottom-up and top-down combined process were used for constructing CNT-array-based device and ZnO nanowire device. The electrical characteristics of the 1D nano-materials-based devices were also investigated. The measurement results of electrical characteristics demonstrate that it is ohm electrical contact behavior between the nano-material and micro-electrodes in the proposed device which also have the field effect. The proposed 1D nano-material-based device shows the application potential in the sensing fields.

Graphene/Si CMOS Hybrid Hall Integrated Circuits

PubMed Central

Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

2014-01-01

Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process. PMID:24998222

CAOS-CMOS camera.

PubMed

Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

2016-06-13

Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

Design rules for quantum imaging devices: experimental progress using CMOS single-photon detectors

NASA Astrophysics Data System (ADS)

Charbon, Edoardo; Gunther, Neil J.; Boiko, Dmitri L.; Beretta, Giordano B.

2006-08-01

We continue our previous program1 where we introduced a set of quantum-based design rules directed at quantum engineers who design single-photon quantum communications and quantum imaging devices. Here, we report on experimental progress using SPAD (single photon avalanche diode) arrays of our design and fabricated in CMOS (complementary metal oxide semiconductor) technology. Emerging high-resolution imaging techniques based on SPAD arrays have proven useful in a variety of disciplines including bio-fluorescence microscopy and 3D vision systems. They have also been particularly successful for intra-chip optical communications implemented entirely in CMOS technology. More importantly for our purposes, a very low dark count allows SPADs to detect rare photon events with a high dynamic range and high signal-to-noise ratio. Our CMOS SPADs support multi-channel detection of photon arrivals with picosecond accuracy, several million times per second, due to a very short detection cycle. The tiny chip area means they are suitable for highly miniaturized quantum imaging devices and that is how we employ them in this paper. Our quantum path integral analysis of the Young-Afshar-Wheeler interferometer showed that Bohr's complementarity principle was not violated due the previously overlooked effect of photon bifurcation within the lens--a phenomenon consistent with our quantum design rules--which accounts for the loss of which-path information in the presence of interference. In this paper, we report on our progress toward the construction of quantitative design rules as well as some proposed tests for quantum imaging devices using entangled photon sources with our SPAD imager.

A Low-Cost CMOS-MEMS Piezoresistive Accelerometer with Large Proof Mass

PubMed Central

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference. PMID:22164052

A low-cost CMOS-MEMS piezoresistive accelerometer with large proof mass.

PubMed

Khir, Mohd Haris Md; Qu, Peng; Qu, Hongwei

2011-01-01

This paper reports a low-cost, high-sensitivity CMOS-MEMS piezoresistive accelerometer with large proof mass. In the device fabricated using ON Semiconductor 0.5 μm CMOS technology, an inherent CMOS polysilicon thin film is utilized as the piezoresistive sensing material. A full Wheatstone bridge was constructed through easy wiring allowed by the three metal layers in the 0.5 μm CMOS technology. The device fabrication process consisted of a standard CMOS process for sensor configuration, and a deep reactive ion etching (DRIE) based post-CMOS microfabrication for MEMS structure release. A bulk single-crystal silicon (SCS) substrate is included in the proof mass to increase sensor sensitivity. In device design and analysis, the self heating of the polysilicon piezoresistors and its effect to the sensor performance is also discussed. With a low operating power of 1.5 mW, the accelerometer demonstrates a sensitivity of 0.077 mV/g prior to any amplification. Dynamic tests have been conducted with a high-end commercial calibrating accelerometer as reference.

A CMOS silicon spin qubit

PubMed Central

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; De Franceschi, S.

2016-01-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal–oxide–semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform. PMID:27882926

A CMOS silicon spin qubit.

PubMed

Maurand, R; Jehl, X; Kotekar-Patil, D; Corna, A; Bohuslavskyi, H; Laviéville, R; Hutin, L; Barraud, S; Vinet, M; Sanquer, M; De Franceschi, S

2016-11-24

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

A CMOS silicon spin qubit

NASA Astrophysics Data System (ADS)

Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

2016-11-01

Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

Full-wafer fabrication by nanostencil lithography of micro/nanomechanical mass sensors monolithically integrated with CMOS.

PubMed

Arcamone, J; van den Boogaart, M A F; Serra-Graells, F; Fraxedas, J; Brugger, J; Pérez-Murano, F

2008-07-30

Wafer-scale nanostencil lithography (nSL) is used to define several types of silicon mechanical resonators, whose dimensions range from 20 µm down to 200 nm, monolithically integrated with CMOS circuits. We demonstrate the simultaneous patterning by nSL of ∼2000 nanodevices per wafer by post-processing standard CMOS substrates using one single metal evaporation, pattern transfer to silicon and subsequent etch of the sacrificial layer. Resonance frequencies in the MHz range were measured in air and vacuum. As proof-of-concept towards an application as high performance sensors, CMOS integrated nano/micromechanical resonators are successfully implemented as ultra-sensitive areal mass sensors. These devices demonstrate the ability to monitor the deposition of gold layers whose average thickness is smaller than a monolayer. Their areal mass sensitivity is in the range of 10(-11) g cm(-2) Hz(-1), and their thickness resolution corresponds to approximately a thousandth of a monolayer.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

NASA Astrophysics Data System (ADS)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

Nano-Bio Quantum Technology for Device-Specific Materials

NASA Technical Reports Server (NTRS)

Choi, Sang H.

2009-01-01

The areas discussed are still under development: I. Nano structured materials for TE applications a) SiGe and Be.Te; b) Nano particles and nanoshells. II. Quantum technology for optical devices: a) Quantum apertures; b) Smart optical materials; c) Micro spectrometer. III. Bio-template oriented materials: a) Bionanobattery; b) Bio-fuel cells; c) Energetic materials.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1977-01-01

Accelerated life tests were performed on CMOS microcircuits to predict their long term reliability. The consistency of the CMOS microcircuit activation energy between the range of 125 C to 200 C and the range 200 C to 250 C was determined. Results indicate CMOS complexity and the amount of moisture detected inside the devices after testing influences time to failure of tested CMOS devices.

Prediction and measurement results of radiation damage to CMOS devices on board spacecraft

NASA Technical Reports Server (NTRS)

Stassinopoulos, E. G.; Danchenko, V.; Cliff, R. A.; Sing, M.; Brucker, G. J.; Ohanian, R. S.

1977-01-01

Final results from the CMOS Radiation Effects Measurement (CREM) experiment flown on Explorer 55 are presented and discussed, based on about 15 months of observations and measurements. Conclusions are given relating to long-range annealing, effects of operating temperature on semiconductor performance in space, biased and unbiased P-MOS device degradation, unbiased n-channel device performance, changes in device transconductance, and the difference in ionization efficiency between Co-60 gamma rays and 1-Mev Van de Graaff electrons. The performance of devices in a heavily shielded electronic subsystem box within the spacecraft is evaluated and compared. Environment models and computational methods and their impact on device-degradation estimates are being reviewed to determine whether they permit cost-effective design of spacecraft.

A Multipurpose CMOS Platform for Nanosensing

PubMed Central

Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L.; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

2016-01-01

This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μm × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW–229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus. PMID:27916911

A Multipurpose CMOS Platform for Nanosensing.

PubMed

Bonanno, Alberto; Sanginario, Alessandro; Marasso, Simone L; Miccoli, Beatrice; Bejtka, Katarzyna; Benetto, Simone; Demarchi, Danilo

2016-11-30

This paper presents a customizable sensing system based on functionalized nanowires (NWs) assembled onto complementary metal oxide semiconductor (CMOS) technology. The Micro-for-Nano (M4N) chip integrates on top of the electronics an array of aluminum microelectrodes covered with gold by means of a customized electroless plating process. The NW assembly process is driven by an array of on-chip dielectrophoresis (DEP) generators, enabling a custom layout of different nanosensors on the same microelectrode array. The electrical properties of each assembled NW are singularly sensed through an in situ CMOS read-out circuit (ROC) that guarantees a low noise and reliable measurement. The M4N chip is directly connected to an external microcontroller for configuration and data processing. The processed data are then redirected to a workstation for real-time data visualization and storage during sensing experiments. As proof of concept, ZnO nanowires have been integrated onto the M4N chip to validate the approach that enables different kind of sensing experiments. The device has been then irradiated by an external UV source with adjustable power to measure the ZnO sensitivity to UV-light exposure. A maximum variation of about 80% of the ZnO-NW resistance has been detected by the M4N system when the assembled 5 μ m × 500 nm single ZnO-NW is exposed to an estimated incident radiant UV-light flux in the range of 1 nW-229 nW. The performed experiments prove the efficiency of the platform conceived for exploiting any kind of material that can change its capacitance and/or resistance due to an external stimulus.

Spin-neurons: A possible path to energy-efficient neuromorphic computers

NASA Astrophysics Data System (ADS)

Sharad, Mrigank; Fan, Deliang; Roy, Kaushik

2013-12-01

Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices. Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and "thresholding" operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that "spin-neurons" (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.

CMOS Image Sensors: Electronic Camera On A Chip

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Structural and optical characterization of GaAs nano-crystals selectively grown on Si nano-tips by MOVPE.

PubMed

Skibitzki, Oliver; Prieto, Ivan; Kozak, Roksolana; Capellini, Giovanni; Zaumseil, Peter; Arroyo Rojas Dasilva, Yadira; Rossell, Marta D; Erni, Rolf; von Känel, Hans; Schroeder, Thomas

2017-03-01

We present the nanoheteroepitaxial growth of gallium arsenide (GaAs) on nano-patterned silicon (Si) (001) substrates fabricated using a CMOS technology compatible process. The selective growth of GaAs nano-crystals (NCs) was achieved at 570 °C by MOVPE. A detailed structure and defect characterization study of the grown nano-heterostructures was performed using scanning transmission electron microscopy, x-ray diffraction, micro-Raman, and micro-photoluminescence (μ-PL) spectroscopy. The results show single-crystalline, nearly relaxed GaAs NCs on top of slightly, by the SiO 2 -mask compressively strained Si nano-tips (NTs). Given the limited contact area, GaAs/Si nanostructures benefit from limited intermixing in contrast to planar GaAs films on Si. Even though a few growth defects (e.g. stacking faults, micro/nano-twins, etc) especially located at the GaAs/Si interface region were detected, the nanoheterostructures show intensive light emission, as investigated by μ-PL spectroscopy. Achieving well-ordered high quality GaAs NCs on Si NTs may provide opportunities for superior electronic, photonic, or photovoltaic device performances integrated on the silicon technology platform.

High-speed imaging using CMOS image sensor with quasi pixel-wise exposure

NASA Astrophysics Data System (ADS)

Sonoda, T.; Nagahara, H.; Endo, K.; Sugiyama, Y.; Taniguchi, R.

2017-02-01

Several recent studies in compressive video sensing have realized scene capture beyond the fundamental trade-off limit between spatial resolution and temporal resolution using random space-time sampling. However, most of these studies showed results for higher frame rate video that were produced by simulation experiments or using an optically simulated random sampling camera, because there are currently no commercially available image sensors with random exposure or sampling capabilities. We fabricated a prototype complementary metal oxide semiconductor (CMOS) image sensor with quasi pixel-wise exposure timing that can realize nonuniform space-time sampling. The prototype sensor can reset exposures independently by columns and fix these amount of exposure by rows for each 8x8 pixel block. This CMOS sensor is not fully controllable via the pixels, and has line-dependent controls, but it offers flexibility when compared with regular CMOS or charge-coupled device sensors with global or rolling shutters. We propose a method to realize pseudo-random sampling for high-speed video acquisition that uses the flexibility of the CMOS sensor. We reconstruct the high-speed video sequence from the images produced by pseudo-random sampling using an over-complete dictionary.

Applications and research on nano power electronics: an adventure beyond quantum electronics

NASA Astrophysics Data System (ADS)

Chakraborty, Arindam; Emadi, Ali

2005-06-01

This paper is a roadmap to the exhaustive role of the newly emerging field of nanotechnology in various application and research areas. Some of the today's important topics are plasma, dielectric layer semiconductor, and carbon nanoparticle based technologies. Carbon nanotubes are very useful for the purpose of fabricating nano opto power devices. The basic concept behind tunneling of electrons has been utilized to define another scope of this technology, and thus came many quantum scale tunneling devices and elements. Fabrication of crystal semiconductors of high quality along with oxides of nano aspect would give rise to superior device performance and find applications such as LEDs, LASER, VLSI technology and also in highly efficient solar cells. Many nano-research based organizations are fully devoted to develop nano power cells, which would give birth to new battery cells, tunneling devises, with high power quality, longer lives, and higher activation rates. Different electronics industries as well as the military organizations would be largely benefited due to this major component and system design ideas of 'Smart Power' technologies. The contribution of nano scale power electronics would be realized in various fields like switching devices, electromechanical systems and quantum science. Such a sophisticated technology will have great impact on the modernization of robotics; space systems, automotive systems and many other fields. The highly emerging field of nanomedicine according to specialists would bring a dramatic revolution in the present century. However nanomedicine is nothing but an integration of biology, medicine and technology. Thermoelectric materials as been referred earlier also are used in case of implantable medical equipments for generation of electric power sufficient for those equipments.

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE PAGES

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun; ...

2017-03-27

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

On the integration of ultrananocrystalline diamond (UNCD) with CMOS chip

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mi, Hongyi; Yuan, Hao -Chih; Seo, Jung -Hun

A low temperature deposition of high quality ultrananocrystalline diamond (UNCD) film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage V th, transconductance g m, cut-off frequency f T and maximum oscillation frequency f max.more » Finally, the results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.« less

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

PubMed

Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

2017-02-14

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

PubMed Central

Chakrabarti, B.; Lastras-Montaño, M. A.; Adam, G.; Prezioso, M.; Hoskins, B.; Cheng, K.-T.; Strukov, D. B.

2017-01-01

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit. PMID:28195239

Spin-neurons: A possible path to energy-efficient neuromorphic computers

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sharad, Mrigank; Fan, Deliang; Roy, Kaushik

Recent years have witnessed growing interest in the field of brain-inspired computing based on neural-network architectures. In order to translate the related algorithmic models into powerful, yet energy-efficient cognitive-computing hardware, computing-devices beyond CMOS may need to be explored. The suitability of such devices to this field of computing would strongly depend upon how closely their physical characteristics match with the essential computing primitives employed in such models. In this work, we discuss the rationale of applying emerging spin-torque devices for bio-inspired computing. Recent spin-torque experiments have shown the path to low-current, low-voltage, and high-speed magnetization switching in nano-scale magnetic devices.more » Such magneto-metallic, current-mode spin-torque switches can mimic the analog summing and “thresholding” operation of an artificial neuron with high energy-efficiency. Comparison with CMOS-based analog circuit-model of a neuron shows that “spin-neurons” (spin based circuit model of neurons) can achieve more than two orders of magnitude lower energy and beyond three orders of magnitude reduction in energy-delay product. The application of spin-neurons can therefore be an attractive option for neuromorphic computers of future.« less

Lifetime prediction of InGaZnO thin film transistor for the application of display device and BEOL-transistors

NASA Astrophysics Data System (ADS)

Kim, Sang Min; Cho, Won Ju; Yu, Chong Gun; Park, Jong Tae

2018-04-01

In this work, the lifetime prediction models of amorphous InGaZnO thin film transistors (a-IGZO TFTs) were suggested for the application of display device and BEOL (Back End Of line) transistors with embedded a-IGZO TFTs. Four different types of test devices according to the active layer thickness, source/drain electrode materials and thermal treatments have been used to verify the suggested model. The device lifetimes under high gate bias stress and hot carrier stress were extracted through fittings of the stretched-exponential equation for threshold voltage shifts and the current estimation method for drain current degradations. Our suggested lifetime prediction models could be used in any kinds of structures of a-IGZO TFTs for the application of display device and BEOL transistors. The a-IGZO TFTs with embedded ITO local conducting layer under source/drain is better for BEOL transistor application and a-IGZO TFTs with InGaZnO thin film as source/drain electrodes may be better for the application of display devices. From 1983 to 1985, he was a Researcher at Gold-Star Semiconductor, Inc., Korea, where he worked on the development of SRAM. He joined the Department of Electronics Engineering, University of Incheon, Incheon, Korea, in 1987, where he is a Professor. As a visiting scientist at Massachusetts Institute of Technology, Cambridge, in 1991, he conducted research in hot carrier reliability of CMOS. As a visiting scholar at University of California, Davis, in 2001, he conducted research on the device structure of Nano-scale SOI CMOS. His recent interests are device structure and reliability of Nano-scale CMOS devices, flash memory, and thin film transistors.

Integration of solid-state nanopores in a 0.5 μm cmos foundry process

PubMed Central

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-01-01

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor’s 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the N+ polysilicon/SiO2/N+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3 which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3. PMID:23519330

Mechanically Flexible and High-Performance CMOS Logic Circuits.

PubMed

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-10-13

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal-oxide-semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices.

Growth of carbon nanotubes on fully processed silicon-on-insulator CMOS substrates.

PubMed

Haque, M Samiul; Ali, S Zeeshan; Guha, P K; Oei, S P; Park, J; Maeng, S; Teo, K B K; Udrea, F; Milne, W I

2008-11-01

This paper describes the growth of Carbon Nanotubes (CNTs) both aligned and non-aligned on fully processed CMOS substrates containing high temperature tungsten metallization. While the growth method has been demonstrated in fabricating CNT gas sensitive layers for high temperatures SOI CMOS sensors, it can be employed in a variety of applications which require the use of CNTs or other nanomaterials with CMOS electronics. In our experiments we have grown CNTs both on SOI CMOS substrates and SOI CMOS microhotplates (suspended on membranes formed by post-CMOS deep RIE etching). The fully processed SOI substrates contain CMOS devices and circuits and additionally, some wafers contained high current LDMOSFETs and bipolar structures such as Lateral Insulated Gate Bipolar Transistors. All these devices were used as test structures to investigate the effect of additional post-CMOS processing such as CNT growth, membrane formation, high temperature annealing, etc. Electrical characterisation of the devices with CNTs were performed along with SEM and Raman spectroscopy. The CNTs were grown both at low and high temperatures, the former being compatible with Aluminium metallization while the latter being possible through the use of the high temperature CMOS metallization (Tungsten). In both cases we have found that there is no change in the electrical behaviour of the CMOS devices, circuits or the high current devices. A slight degradation of the thermal performance of the CMOS microhotplates was observed due to the extra heat dissipation path created by the CNT layers, but this is expected as CNTs exhibit a high thermal conductance. In addition we also observed that in the case of high temperature CNT growth a slight degradation in the manufacturing yield was observed. This is especially the case where large area membranes with a diameter in excess of 500 microns are used.

Spin pumping driven auto-oscillator for phase-encoded logic—device design and material requirements

NASA Astrophysics Data System (ADS)

Rakheja, S.; Kani, N.

2017-05-01

In this work, we propose a spin nano-oscillator (SNO) device where information is encoded in the phase (time-shift) of the output oscillations. The spin current required to set up the oscillations in the device is generated through spin pumping from an input nanomagnet that is precessing at RF frequencies. We discuss the operation of the SNO device, in which either the in-plane (IP) or out-of-plane (OOP) magnetization oscillations are utilized toward implementing ultra-low-power circuits. Using physical models of the nanomagnet dynamics and the spin transport through non-magnetic channels, we quantify the reliability of the SNO device using a "scaling ratio". Material requirements for the nanomagnet and the channel to ensure correct logic functionality are identified using the scaling ratio metric. SNO devices consume (2-5)× lower energy compared to CMOS devices and other spin-based devices with similar device sizes and material parameters. The analytical models presented in this work can be used to optimize the performance and scaling of SNO devices in comparison to CMOS devices at ultra-scaled technology nodes.

Monolithic integration of a plasmonic sensor with CMOS technology

NASA Astrophysics Data System (ADS)

Shakoor, Abdul; Cheah, Boon C.; Hao, Danni; Al-Rawhani, Mohammed; Nagy, Bence; Grant, James; Dale, Carl; Keegan, Neil; McNeil, Calum; Cumming, David R. S.

2017-02-01

Monolithic integration of nanophotonic sensors with CMOS detectors can transform the laboratory based nanophotonic sensors into practical devices with a range of applications in everyday life. In this work, by monolithically integrating an array of gold nanodiscs with the CMOS photodiode we have developed a compact and miniaturized nanophotonic sensor system having direct electrical read out. Doing so eliminates the need of expensive and bulky laboratory based optical spectrum analyzers used currently for measurements of nanophotonic sensor chips. The experimental optical sensitivity of the gold nanodiscs is measured to be 275 nm/RIU which translates to an electrical sensitivity of 5.4 V/RIU. This integration of nanophotonic sensors with the CMOS electronics has the potential to revolutionize personalized medical diagnostics similar to the way in which the CMOS technology has revolutionized the electronics industry.

Large Format CMOS-based Detectors for Diffraction Studies

NASA Astrophysics Data System (ADS)

Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

2013-03-01

Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

Development of a Cryostat to Characterize Nano-scale Superconducting Quantum Interference Devices

NASA Astrophysics Data System (ADS)

Longo, Mathew; Matheny, Matthew; Knudsen, Jasmine

2016-03-01

We have designed and constructed a low-noise vacuum cryostat to be used for the characterization of nano-scale superconducting quantum interference devices (SQUIDs). Such devices are very sensitive to magnetic fields and can measure changes in flux on the order of a single electron magnetic moment. As a part of the design process, we calculated the separation required between the cryogenic preamplifier and superconducting magnet, including a high-permeability magnetic shield, using a finite-element model of the apparatus. The cryostat comprises a vacuum cross at room temperature for filtered DC and shielded RF electrical connections, a thin-wall stainless steel support tube, a taper-sealed cryogenic vacuum can, and internal mechanical support and wiring for the nanoSQUID. The Dewar is modified with a room-temperature flange with a sliding seal for the cryostat. The flange supports the superconducting 3 Tesla magnet and thermometry wiring. Upon completion of the cryostat fabrication and Dewar modifications, operation of the nanoSQUIDs as transported from our collaborator's laboratory in Israel will be confirmed, as the lead forming the SQUID is sensitive to oxidation and the SQUIDs must be shipped in a vacuum container. After operation of the nanoSQUIDs is confirmed, the primary work of characterizing their high-speed properties will begin. This will include looking at the measurement of relaxation oscillations at high bandwidth in comparison to the theoretical predictions of the current model.

Nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, Erica

2012-02-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted cooling device. Using theoretical calculations and experimental inputs, we predict that the cooling power of such a device can approach 1kW/cm^2, on par with the best known techniques using standard lithography methods. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

PubMed

Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

2013-04-19

High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

Challenges of nickel silicidation in CMOS technologies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Breil, Nicolas; Lavoie, Christian; Ozcan, Ahmet

2015-04-01

In our paper, we review some of the key challenges associated with the Ni silicidation process in the most recent CMOS technologies. The introduction of new materials (e.g.SiGe), and of non-planar architectures bring some important changes that require fundamental investigation from a material engineering perspective. Following a discussion of the device architecture and silicide evolution through the last CMOS generations, we focus our study on a very peculiar defect, termed NiSi-Fangs. We describe a mechanism for the defect formation, and present a detailed material analysis that supports this mechanism. We highlight some of the possible metal enrichment processes of themore » nickel monosilicide such as oxidation or various RIE (Reactive Ion Etching) plasma process, leading to a metal source available for defect formation. Furthermore, we investigate the NiSi formation and re-formation silicidation differences between Si and SiGe materials, and between (1 0 0) and (1 1 1) orientations. Finally, we show that the thermal budgets post silicidation can lead to the formation of NiSi-Fangs if the structure and the processes are not optimized. Beyond the understanding of the defect and the discussion on the engineering solutions used to prevent its formation, the interest of this investigation also lies in the fundamental learning within the Ni–Pt–Si–Ge system and some additional perspective on Ni-based contacts to advanced microelectronic devices.« less

Mechanically Flexible and High-Performance CMOS Logic Circuits

PubMed Central

Honda, Wataru; Arie, Takayuki; Akita, Seiji; Takei, Kuniharu

2015-01-01

Low-power flexible logic circuits are key components required by the next generation of flexible electronic devices. For stable device operation, such components require a high degree of mechanical flexibility and reliability. Here, the mechanical properties of low-power flexible complementary metal–oxide–semiconductor (CMOS) logic circuits including inverter, NAND, and NOR are investigated. To fabricate CMOS circuits on flexible polyimide substrates, carbon nanotube (CNT) network films are used for p-type transistors, whereas amorphous InGaZnO films are used for the n-type transistors. The power consumption and voltage gain of CMOS inverters are <500 pW/mm at Vin = 0 V (<7.5 nW/mm at Vin = 5 V) and >45, respectively. Importantly, bending of the substrate is not found to cause significant changes in the device characteristics. This is also observed to be the case for more complex flexible NAND and NOR logic circuits for bending states with a curvature radius of 2.6 mm. The mechanical stability of these CMOS logic circuits makes them ideal candidates for use in flexible integrated devices. PMID:26459882

Memristor-CMOS hybrid integrated circuits for reconfigurable logic.

PubMed

Xia, Qiangfei; Robinett, Warren; Cumbie, Michael W; Banerjee, Neel; Cardinali, Thomas J; Yang, J Joshua; Wu, Wei; Li, Xuema; Tong, William M; Strukov, Dmitri B; Snider, Gregory S; Medeiros-Ribeiro, Gilberto; Williams, R Stanley

2009-10-01

Hybrid reconfigurable logic circuits were fabricated by integrating memristor-based crossbars onto a foundry-built CMOS (complementary metal-oxide-semiconductor) platform using nanoimprint lithography, as well as materials and processes that were compatible with the CMOS. Titanium dioxide thin-film memristors served as the configuration bits and switches in a data routing network and were connected to gate-level CMOS components that acted as logic elements, in a manner similar to a field programmable gate array. We analyzed the chips using a purpose-built testing system, and demonstrated the ability to configure individual devices, use them to wire up various logic gates and a flip-flop, and then reconfigure devices.

Novel Si-Ge-C Superlattices for More than Moore CMOS

DTIC Science & Technology

2016-03-31

diodes can be entirely formed by epitaxial growth, CMOS Active Pixel Sensors can be made with Fully-Depleted SOI CMOS . One important advantage of...a NMOS Transfer Gate (TG), which could be part of a 4T pixel APS. PPDs are preferred in CMOS image sensors for the ability of the pinning layer to...than Moore” with the creation of active photonic devices monolithically integrated with CMOS . Applications include Multispectral CMOS Image Sensors

Ion traps fabricated in a CMOS foundry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mehta, K. K.; Ram, R. J.; Eltony, A. M.

2014-07-28

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size.more » This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.« less

Electrical characteristics of silicon nanowire CMOS inverters under illumination.

PubMed

Yoo, Jeuk; Kim, Yoonjoong; Lim, Doohyeok; Kim, Sangsig

2018-02-05

In this study, we examine the electrical characteristics of complementary metal-oxide-semiconductor (CMOS) inverters with silicon nanowire (SiNW) channels on transparent substrates under illumination. The electrical characteristics vary with the wavelength and power of light due to the variation in the generation rates of the electric-hole pairs. Compared to conventional optoelectronic devices that sense the on/off states by the variation in the current, our device achieves the sensing of the on/off states with more precision by using the voltage variation induced by the wavelength or intensity of light. The device was fabricated on transparent substrates to maximize the light absorption using conventional CMOS technologies. The key difference between our SiNW CMOS inverters and conventional optoelectronic devices is the ability to control the flow of charge carriers more effectively. The improved sensitivity accomplished with the use of SiNW CMOS inverters allows better control of the on/off states.

The Spin Torque Lego - from spin torque nano-devices to advanced computing architectures

NASA Astrophysics Data System (ADS)

Grollier, Julie

2013-03-01

Spin transfer torque (STT), predicted in 1996, and first observed around 2000, brought spintronic devices to the realm of active elements. A whole class of new devices, based on the combined effects of STT for writing and Giant Magneto-Resistance or Tunnel Magneto-Resistance for reading has emerged. The second generation of MRAMs, based on spin torque writing : the STT-RAM, is under industrial development and should be out on the market in three years. But spin torque devices are not limited to binary memories. We will rapidly present how the spin torque effect also allows to implement non-linear nano-oscillators, spin-wave emitters, controlled stochastic devices and microwave nano-detectors. What is extremely interesting is that all these functionalities can be obtained using the same materials, the exact same stack, simply by changing the device geometry and its bias conditions. So these different devices can be seen as Lego bricks, each brick with its own functionality. During this talk, I will show how spin torque can be engineered to build new bricks, such as the Spintronic Memristor, an artificial magnetic nano-synapse. I will then give hints on how to assemble these bricks in order to build novel types of computing architectures, with a special focus on neuromorphic circuits. Financial support by the European Research Council Starting Grant NanoBrain (ERC 2010 Stg 259068) is acknowledged.

Polymer Nanofiber Based Reversible Nano-Switch/Sensor Diode (Nanosssd) Device

NASA Technical Reports Server (NTRS)

Theofylaktos, Onoufrios (Inventor); Meador, Michael A. (Inventor); Miranda, Felix A. (Inventor); Pinto, Nicholas (Inventor); Mueller, Carl H. (Inventor); Santos-Perez, Javier (Inventor)

2017-01-01

A nanostructure device is provided and performs dual functions as a nano-switching/sensing device. The nanostructure device includes a doped semiconducting substrate, an insulating layer disposed on the doped semiconducting substrate, an electrode formed on the insulating layer, and at least one polymer nanofiber deposited on the electrode. The at least one polymer nanofiber provides an electrical connection between the electrode and the substrate and is the electroactive element in the device.

Graphene Based Reversible Nano-Switch/Sensor Schottky Diode (NANOSSSD) Device

NASA Technical Reports Server (NTRS)

Miranda, Felix A. (Inventor); Theofylaktos, Onoufrios (Inventor); Pinto, Nicholas J. (Inventor); Mueller, Carl H. (Inventor); Santos, Javier (Inventor); Meador, Michael A. (Inventor)

2015-01-01

A nanostructure device is provided and performs dual functions as a nano-switching/sensing device. The nanostructure device includes a doped semiconducting substrate, an insulating layer disposed on the doped semiconducting substrate, an electrode formed on the insulating layer, and at least one layer of graphene formed on the electrode. The at least one layer of graphene provides an electrical connection between the electrode and the substrate and is the electroactive element in the device.

Nano-Electro-Mechanical (NEM) Relay Devices and Technology for Ultra-Low Energy Digital Integrated Circuits

DTIC Science & Technology

2013-05-01

number. 1. REPORT DATE 01 MAY 2013 2. REPORT TYPE 3. DATES COVERED 00-00- 2013 to 00-00- 2013 4. TITLE AND SUBTITLE Nano-Electro-Mechanical (NEM...18 Copyright © 2013 , by the author( s ). All rights reserved. Permission to make digital or hard copies of all or part of this work for personal or...E. Ismail, S .-H. Lo, G. A. Sai- Halasz, R . G. Viswanathan, H.-J. C. Wann, S . J. Wind, and H.- S . Wong, “CMOS scaling into the nanometer regime

Modeling and simulation of electronic structure, material interface and random doping in nano electronic devices

PubMed Central

Chen, Duan; Wei, Guo-Wei

2010-01-01

The miniaturization of nano-scale electronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), has given rise to a pressing demand in the new theoretical understanding and practical tactic for dealing with quantum mechanical effects in integrated circuits. Modeling and simulation of this class of problems have emerged as an important topic in applied and computational mathematics. This work presents mathematical models and computational algorithms for the simulation of nano-scale MOSFETs. We introduce a unified two-scale energy functional to describe the electrons and the continuum electrostatic potential of the nano-electronic device. This framework enables us to put microscopic and macroscopic descriptions in an equal footing at nano scale. By optimization of the energy functional, we derive consistently-coupled Poisson-Kohn-Sham equations. Additionally, layered structures are crucial to the electrostatic and transport properties of nano transistors. A material interface model is proposed for more accurate description of the electrostatics governed by the Poisson equation. Finally, a new individual dopant model that utilizes the Dirac delta function is proposed to understand the random doping effect in nano electronic devices. Two mathematical algorithms, the matched interface and boundary (MIB) method and the Dirichlet-to-Neumann mapping (DNM) technique, are introduced to improve the computational efficiency of nano-device simulations. Electronic structures are computed via subband decomposition and the transport properties, such as the I-V curves and electron density, are evaluated via the non-equilibrium Green's functions (NEGF) formalism. Two distinct device configurations, a double-gate MOSFET and a four-gate MOSFET, are considered in our three-dimensional numerical simulations. For these devices, the current fluctuation and voltage threshold lowering effect induced by the discrete dopant model are explored. Numerical convergence

Radiation imaging with a new scintillator and a CMOS camera

NASA Astrophysics Data System (ADS)

Kurosawa, S.; Shoji, Y.; Pejchal, J.; Yokota, Y.; Yoshikawa, A.

2014-07-01

A new imaging system consisting of a high-sensitivity complementary metal-oxide semiconductor (CMOS) sensor, a microscope and a new scintillator, Ce-doped Gd3(Al,Ga)5O12 (Ce:GAGG) grown by the Czochralski process, has been developed. The noise, the dark current and the sensitivity of the CMOS camera (ORCA-Flash4.0, Hamamatsu) was revised and compared to a conventional CMOS, whose sensitivity is at the same level as that of a charge coupled device (CCD) camera. Without the scintillator, this system had a good position resolution of 2.1 ± 0.4 μm and we succeeded in obtaining the alpha-ray images using 1-mm thick Ce:GAGG crystal. This system can be applied for example to high energy X-ray beam profile monitor, etc.

A CMOS Time-Resolved Fluorescence Lifetime Analysis Micro-System

PubMed Central

Rae, Bruce R.; Muir, Keith R.; Gong, Zheng; McKendry, Jonathan; Girkin, John M.; Gu, Erdan; Renshaw, David; Dawson, Martin D.; Henderson, Robert K.

2009-01-01

We describe a CMOS-based micro-system for time-resolved fluorescence lifetime analysis. It comprises a 16 × 4 array of single-photon avalanche diodes (SPADs) fabricated in 0.35 μm high-voltage CMOS technology with in-pixel time-gated photon counting circuitry and a second device incorporating an 8 × 8 AlInGaN blue micro-pixellated light-emitting diode (micro-LED) array bump-bonded to an equivalent array of LED drivers realized in a standard low-voltage 0.35 μm CMOS technology, capable of producing excitation pulses with a width of 777 ps (FWHM). This system replaces instrumentation based on lasers, photomultiplier tubes, bulk optics and discrete electronics with a PC-based micro-system. Demonstrator lifetime measurements of colloidal quantum dot and Rhodamine samples are presented. PMID:22291564

JPL CMOS Active Pixel Sensor Technology

NASA Technical Reports Server (NTRS)

Fossum, E. R.

1995-01-01

This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

Delta-Doped Back-Illuminated CMOS Imaging Arrays: Progress and Prospects

NASA Technical Reports Server (NTRS)

Hoenk, Michael E.; Jones, Todd J.; Dickie, Matthew R.; Greer, Frank; Cunningham, Thomas J.; Blazejewski, Edward; Nikzad, Shouleh

2009-01-01

In this paper, we report the latest results on our development of delta-doped, thinned, back-illuminated CMOS imaging arrays. As with charge-coupled devices, thinning and back-illumination are essential to the development of high performance CMOS imaging arrays. Problems with back surface passivation have emerged as critical to the prospects for incorporating CMOS imaging arrays into high performance scientific instruments, just as they did for CCDs over twenty years ago. In the early 1990's, JPL developed delta-doped CCDs, in which low temperature molecular beam epitaxy was used to form an ideal passivation layer on the silicon back surface. Comprising only a few nanometers of highly-doped epitaxial silicon, delta-doping achieves the stability and uniformity that are essential for high performance imaging and spectroscopy. Delta-doped CCDs were shown to have high, stable, and uniform quantum efficiency across the entire spectral range from the extreme ultraviolet through the near infrared. JPL has recently bump-bonded thinned, delta-doped CMOS imaging arrays to a CMOS readout, and demonstrated imaging. Delta-doped CMOS devices exhibit the high quantum efficiency that has become the standard for scientific-grade CCDs. Together with new circuit designs for low-noise readout currently under development, delta-doping expands the potential scientific applications of CMOS imaging arrays, and brings within reach important new capabilities, such as fast, high-sensitivity imaging with parallel readout and real-time signal processing. It remains to demonstrate manufacturability of delta-doped CMOS imaging arrays. To that end, JPL has acquired a new silicon MBE and ancillary equipment for delta-doping wafers up to 200mm in diameter, and is now developing processes for high-throughput, high yield delta-doping of fully-processed wafers with CCD and CMOS imaging devices.

CMOS Image Sensors for High Speed Applications.

PubMed

El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

2009-01-01

Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

Nano-array integrated monolithic devices: toward rational materials design and multi-functional performance by scalable nanostructures assembly

DOE PAGES

Wang, Sibo; Ren, Zheng; Guo, Yanbing; ...

2016-03-21

We report the scalable three-dimensional (3-D) integration of functional nanostructures into applicable platforms represents a promising technology to meet the ever-increasing demands of fabricating high performance devices featuring cost-effectiveness, structural sophistication and multi-functional enabling. Such an integration process generally involves a diverse array of nanostructural entities (nano-entities) consisting of dissimilar nanoscale building blocks such as nanoparticles, nanowires, and nanofilms made of metals, ceramics, or polymers. Various synthetic strategies and integration methods have enabled the successful assembly of both structurally and functionally tailored nano-arrays into a unique class of monolithic devices. The performance of nano-array based monolithic devices is dictated bymore » a few important factors such as materials substrate selection, nanostructure composition and nano-architecture geometry. Therefore, the rational material selection and nano-entity manipulation during the nano-array integration process, aiming to exploit the advantageous characteristics of nanostructures and their ensembles, are critical steps towards bridging the design of nanostructure integrated monolithic devices with various practical applications. In this article, we highlight the latest research progress of the two-dimensional (2-D) and 3-D metal and metal oxide based nanostructural integrations into prototype devices applicable with ultrahigh efficiency, good robustness and improved functionality. Lastly, selective examples of nano-array integration, scalable nanomanufacturing and representative monolithic devices such as catalytic converters, sensors and batteries will be utilized as the connecting dots to display a roadmap from hierarchical nanostructural assembly to practical nanotechnology implications ranging from energy, environmental, to chemical and biotechnology areas.« less

Nano-array integrated monolithic devices: toward rational materials design and multi-functional performance by scalable nanostructures assembly

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wang, Sibo; Ren, Zheng; Guo, Yanbing

We report the scalable three-dimensional (3-D) integration of functional nanostructures into applicable platforms represents a promising technology to meet the ever-increasing demands of fabricating high performance devices featuring cost-effectiveness, structural sophistication and multi-functional enabling. Such an integration process generally involves a diverse array of nanostructural entities (nano-entities) consisting of dissimilar nanoscale building blocks such as nanoparticles, nanowires, and nanofilms made of metals, ceramics, or polymers. Various synthetic strategies and integration methods have enabled the successful assembly of both structurally and functionally tailored nano-arrays into a unique class of monolithic devices. The performance of nano-array based monolithic devices is dictated bymore » a few important factors such as materials substrate selection, nanostructure composition and nano-architecture geometry. Therefore, the rational material selection and nano-entity manipulation during the nano-array integration process, aiming to exploit the advantageous characteristics of nanostructures and their ensembles, are critical steps towards bridging the design of nanostructure integrated monolithic devices with various practical applications. In this article, we highlight the latest research progress of the two-dimensional (2-D) and 3-D metal and metal oxide based nanostructural integrations into prototype devices applicable with ultrahigh efficiency, good robustness and improved functionality. Lastly, selective examples of nano-array integration, scalable nanomanufacturing and representative monolithic devices such as catalytic converters, sensors and batteries will be utilized as the connecting dots to display a roadmap from hierarchical nanostructural assembly to practical nanotechnology implications ranging from energy, environmental, to chemical and biotechnology areas.« less

Lab-on-CMOS Integration of Microfluidics and Electrochemical Sensors

PubMed Central

Huang, Yue; Mason, Andrew J.

2013-01-01

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms. PMID:23939616

Lab-on-CMOS integration of microfluidics and electrochemical sensors.

PubMed

Huang, Yue; Mason, Andrew J

2013-10-07

This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

NASA Astrophysics Data System (ADS)

Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

2018-04-01

In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

NASA Astrophysics Data System (ADS)

Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

2014-06-01

A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

Conceptual Design of a Nano-Networking Device

PubMed Central

Canovas-Carrasco, Sebastian; Garcia-Sanchez, Antonio-Javier; Garcia-Sanchez, Felipe; Garcia-Haro, Joan

2016-01-01

Nanotechnology is an emerging scientific area whose advances, among many others, have a positive direct impact on the miniaturization of electronics. This unique technology enables the possibility to design and build electronic components as well as complete devices (called nanomachines or nanodevices) at the nano scale. A nanodevice is expected to be an essential element able to operate in a nanonetwork, where a huge number of them would coordinate to acquire data, process the information gathered, and wirelessly transmit those data to end-points providing innovative services in many key scenarios, such as the human body or the environment. This paper is aimed at studying the feasibility of this type of device by carefully examining their main component parts, namely the nanoprocessor, nanomemory, nanoantenna, and nanogenerator. To this end, a thorough state-of-the-art review is conveyed to discuss, substantiate, and select the most suitable current technology (commercial or pre-commercial) for each component. Then, we further contribute by developing a complete conceptual nanodevice layout taking into consideration its ultra-small size (similar to a blood cell) and its very restricted capabilities (e.g., processing, memory storage, telecommunication, and energy management). The required resources as well as the power consumption are realistically estimated. PMID:27973430

Conceptual Design of a Nano-Networking Device.

PubMed

Canovas-Carrasco, Sebastian; Garcia-Sanchez, Antonio-Javier; Garcia-Sanchez, Felipe; Garcia-Haro, Joan

2016-12-11

Nanotechnology is an emerging scientific area whose advances, among many others, have a positive direct impact on the miniaturization of electronics. This unique technology enables the possibility to design and build electronic components as well as complete devices (called nanomachines or nanodevices) at the nano scale. A nanodevice is expected to be an essential element able to operate in a nanonetwork, where a huge number of them would coordinate to acquire data, process the information gathered, and wirelessly transmit those data to end-points providing innovative services in many key scenarios, such as the human body or the environment. This paper is aimed at studying the feasibility of this type of device by carefully examining their main component parts, namely the nanoprocessor, nanomemory, nanoantenna, and nanogenerator. To this end, a thorough state-of-the-art review is conveyed to discuss, substantiate, and select the most suitable current technology (commercial or pre-commercial) for each component. Then, we further contribute by developing a complete conceptual nanodevice layout taking into consideration its ultra-small size (similar to a blood cell) and its very restricted capabilities (e.g., processing, memory storage, telecommunication, and energy management). The required resources as well as the power consumption are realistically estimated.

A versatile nanotechnology to connect individual nano-objects for the fabrication of hybrid single-electron devices

NASA Astrophysics Data System (ADS)

Bernand-Mantel, A.; Bouzehouane, K.; Seneor, P.; Fusil, S.; Deranlot, C.; Brenac, A.; Notin, L.; Morel, R.; Petroff, F.; Fert, A.

2010-11-01

We report on the high yield connection of single nano-objects as small as a few nanometres in diameter to separately elaborated metallic electrodes, using a 'table-top' nanotechnology. Single-electron transport measurements validate that transport occurs through a single nano-object. The vertical geometry of the device natively allows an independent choice of materials for each electrode and the nano-object. In addition ferromagnetic materials can be used without encountering oxidation problems. The possibility of elaborating such hybrid nanodevices opens new routes for the democratization of spintronic studies in low dimensions.

Inductance analysis of superconducting quantum interference devices with 3D nano-bridge junctions

NASA Astrophysics Data System (ADS)

Wang, Hao; Yang, Ruoting; Li, Guanqun; Wu, Long; Liu, Xiaoyu; Chen, Lei; Ren, Jie; Wang, Zhen

2018-05-01

Superconducting quantum interference devices (SQUIDs) with 3D nano-bridge junctions can be miniaturized into nano-SQUIDs that are able to sense a few spins in a large magnetic field. Among all device parameters, the inductance is key to the performance of SQUIDs with 3D nano-bridge junctions. Here, we measured the critical-current magnetic flux modulation curves of 12 devices with three design types using a current strip-line directly coupled to the SQUID loop. A best flux modulation depth of 71% was achieved for our 3D Nb SQUID. From the modulation curves, we extracted the inductance values of the current stripe-line in each design and compared them with the corresponding simulation results of InductEX. In this way, London penetration depths of 110 and 420 nm were determined for our Nb (niobium) and NbN (niobium nitride) films, respectively. Furthermore, we showed that inductances of 11 and 119 pH for Nb and NbN 3D nano-bridge junctions, respectively, dominated the total inductance of our SQUID loops which are 23 pH for Nb and 255 pH for NbN. A screening parameter being equal to one suggests optimal critical currents of 89.6 and 8.1 μA for Nb and NbN SQUIDs, respectively. Additionally, intrinsic flux noise of 110 ± 40 nΦ0/(Hz)1/2 is calculated for the Nb SQUIDs with 3D nano-bridge junctions by Langevin simulation.

Interconnecting wearable devices with nano-biosensing implants through optical wireless communications

NASA Astrophysics Data System (ADS)

Johari, Pedram; Pandey, Honey; Jornet, Josep M.

2018-02-01

Major advancements in the fields of electronics, photonics and wireless communication have enabled the development of compact wearable devices, with applications in diverse domains such as fitness, wellness and medicine. In parallel, nanotechnology is enabling the development of miniature sensors that can detect events at the nanoscale with unprecedented accuracy. On this matter, in vivo implantable Surface Plasmon Resonance (SPR) nanosensors have been proposed to analyze circulating biomarkers in body fluids for the early diagnosis of a myriad of diseases, ranging from cardiovascular disorders to different types of cancer. In light of these results, in this paper, an architecture is proposed to bridge the gap between these two apparently disjoint paradigms, namely, the commercial wearable devices and the advanced nano-biosensing technologies. More specifically, this paper thoroughly assesses the feasibility of the wireless optical intercommunications of an SPR-based nanoplasmonic biochip -implanted subcutaneously in the wrist-, with a nanophotonic wearable smart band which is integrated by an array of nano-lasers and photon-detectors for distributed excitation and measurement of the nanoplasmonic biochip. This is done through a link budget analysis which captures the peculiarities of the intra-body optical channel at (sub) cellular level, the strength of the SPR nanosensor reflection, as well as the capabilities of the nanolasers (emission power, spectrum) and the nano photon-detectors (sensitivity and noise equivalent power). The proposed analysis guides the development of practical communication designs between the wearable devices and nano-biosensing implants, which paves the way through early-stage diagnosis of severe diseases.

CMOS dot matrix microdisplay

NASA Astrophysics Data System (ADS)

Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

2011-03-01

Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

Tunable nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, E. W.

2014-08-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted and tunable cooling device. Using two different approaches, the Nonequilibrium Green's Function (NEGF) method and experimental inputs, we predict that the cooling power of such a device can approach the order of kW/cm2, on par with the best known techniques using standard superlattice structures. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

ZnO Nano-Rod Devices for Intradermal Delivery and Immunization

PubMed Central

Nayak, Tapas R.; Wang, Hao; Pant, Aakansha; Zheng, Minrui; Junginger, Hans; Goh, Wei Jiang; Lee, Choon Keong; Zou, Shui; Alonso, Sylvie; Czarny, Bertrand; Storm, Gert; Sow, Chorng Haur; Lee, Chengkuo; Pastorin, Giorgia

2017-01-01

Intradermal delivery of antigens for vaccination is a very attractive approach since the skin provides a rich network of antigen presenting cells, which aid in stimulating an immune response. Numerous intradermal techniques have been developed to enhance penetration across the skin. However, these methods are invasive and/or affect the skin integrity. Hence, our group has devised zinc oxide (ZnO) nano-rods for non-destructive drug delivery. Chemical vapour deposition was used to fabricate aligned nano-rods on ZnO pre-coated silicon chips. The nano-rods’ length and diameter were found to depend on the temperature, time, quality of sputtered silicon chips, etc. Vertically aligned ZnO nano-rods with lengths of 30–35 µm and diameters of 200–300 nm were selected for in vitro human skin permeation studies using Franz cells with Albumin-fluorescein isothiocyanate (FITC) absorbed on the nano-rods. Fluorescence and confocal studies on the skin samples showed FITC penetration through the skin along the channels formed by the nano-rods. Bradford protein assay on the collected fluid samples indicated a significant quantity of Albumin-FITC in the first 12 h. Low antibody titres were observed with immunisation on Balb/c mice with ovalbumin (OVA) antigen coated on the nano-rod chips. Nonetheless, due to the reduced dimensions of the nano-rods, our device offers the additional advantage of excluding the simultaneous entrance of microbial pathogens. Taken together, these results showed that ZnO nano-rods hold the potential for a safe, non-invasive, and painless intradermal drug delivery. PMID:28617335

ZnO Nano-Rod Devices for Intradermal Delivery and Immunization.

PubMed

Nayak, Tapas R; Wang, Hao; Pant, Aakansha; Zheng, Minrui; Junginger, Hans; Goh, Wei Jiang; Lee, Choon Keong; Zou, Shui; Alonso, Sylvie; Czarny, Bertrand; Storm, Gert; Sow, Chorng Haur; Lee, Chengkuo; Pastorin, Giorgia

2017-06-15

Intradermal delivery of antigens for vaccination is a very attractive approach since the skin provides a rich network of antigen presenting cells, which aid in stimulating an immune response. Numerous intradermal techniques have been developed to enhance penetration across the skin. However, these methods are invasive and/or affect the skin integrity. Hence, our group has devised zinc oxide (ZnO) nano-rods for non-destructive drug delivery. Chemical vapour deposition was used to fabricate aligned nano-rods on ZnO pre-coated silicon chips. The nano-rods' length and diameter were found to depend on the temperature, time, quality of sputtered silicon chips, etc. Vertically aligned ZnO nano-rods with lengths of 30-35 µm and diameters of 200-300 nm were selected for in vitro human skin permeation studies using Franz cells with Albumin-fluorescein isothiocyanate (FITC) absorbed on the nano-rods. Fluorescence and confocal studies on the skin samples showed FITC penetration through the skin along the channels formed by the nano-rods. Bradford protein assay on the collected fluid samples indicated a significant quantity of Albumin-FITC in the first 12 h. Low antibody titres were observed with immunisation on Balb/c mice with ovalbumin (OVA) antigen coated on the nano-rod chips. Nonetheless, due to the reduced dimensions of the nano-rods, our device offers the additional advantage of excluding the simultaneous entrance of microbial pathogens. Taken together, these results showed that ZnO nano-rods hold the potential for a safe, non-invasive, and painless intradermal drug delivery.

RF upset susceptibilities of CMOS and low power Schottky D-type flip-flops

NASA Astrophysics Data System (ADS)

Kenneally, Daniel J.; Koellen, Daniel S.; Epshtein, Stan

A description is given of measurements of RF upset levels on two D-type flip-flops, the CD4013B and 54ALS74A, which are functionally identical but fabricated from different technologies: CMOS and low-power Schottky. Continuous-wave electromagnetic interference (CW EMI) from 1 MHz to 200 MHz was coupled into the clock, data, and collector bias, Vcc, ports of each device type while test vectors were used to verify normal operation and subsequent upsets. Both the CMOS and the Schottky devices show decreasing RF susceptibility with increasing frequencies from 1 to 200 MHz. The CMOS device roll-off is almost 18 dB/decade as compared to about 12 dB/decade for the Schottky device. The differences in the Vcc ports' susceptibilities are also apparent. The CMOS device's upset levels decrease steeply with increasing frequency at approximate roll-offs of 60 dB/decade up to 5 MHz and 15 dB/decade from 5 to 100 MHz. Over the same bands, the Schottky device susceptibility at the Vcc port remains strikingly constant at a 6-dBm upset level. Measurements on the clock and data ports seem to suggest that: (1) the CMOS device is `RF harder' than the Schottky device by 3 to 18 dB at least above the 5 to 10 MHz range and out to 100 MHz; and (2) below that range, the Schottky device may be `RF harder' by 3 to 6 dB, but there are not enough measurement data to confirm this performance below 5 MHz.

Plasmonic Structures for CMOS Photonics and Control of Spontaneous Emission

DTIC Science & Technology

2013-04-01

structures; v) developed CMOS Si photonic switching device based on the vanadium dioxide ( VO2 ) phase transition. vi) also engaged in a partnership with...CMOS Si photonic switching device based on the vanadium dioxide ( VO2 ) phase transition. vii. exploring approaches to enhance spontaneous emission in...size and bandwidth, we are exploring phase-change materials and, in particular, vanadium dioxide. VO2 undergoes an insulator-to-metal phase transition

Thin Film Complementary Metal Oxide Semiconductor (CMOS) Device Using a Single-Step Deposition of the Channel Layer

PubMed Central

Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wang, Zhenwei; Hedhili, M. N.; Wang, Q. X.; Alshareef, H. N.

2014-01-01

We report, for the first time, the use of a single step deposition of semiconductor channel layer to simultaneously achieve both n- and p-type transport in transparent oxide thin film transistors (TFTs). This effect is achieved by controlling the concentration of hydroxyl groups (OH-groups) in the underlying gate dielectrics. The semiconducting tin oxide layer was deposited at room temperature, and the maximum device fabrication temperature was 350°C. Both n and p-type TFTs showed fairly comparable performance. A functional CMOS inverter was fabricated using this novel scheme, indicating the potential use of our approach for various practical applications. PMID:24728223

Hyperspectral CMOS imager

NASA Astrophysics Data System (ADS)

Jerram, P. A.; Fryer, M.; Pratlong, J.; Pike, A.; Walker, A.; Dierickx, B.; Dupont, B.; Defernez, A.

2017-11-01

CCDs have been used for many years for Hyperspectral imaging missions and have been extremely successful. These include the Medium Resolution Imaging Spectrometer (MERIS) [1] on Envisat, the Compact High Resolution Imaging Spectrometer (CHRIS) on Proba and the Ozone Monitoring Instrument operating in the UV spectral region. ESA are also planning a number of further missions that are likely to use CCD technology (Sentinel 3, 4 and 5). However CMOS sensors have a number of advantages which means that they will probably be used for hyperspectral applications in the longer term. There are two main advantages with CMOS sensors: First a hyperspectral image consists of spectral lines with a large difference in intensity; in a frame transfer CCD the faint spectral lines have to be transferred through the part of the imager illuminated by intense lines. This can lead to cross-talk and whilst this problem can be reduced by the use of split frame transfer and faster line rates CMOS sensors do not require a frame transfer and hence inherently will not suffer from this problem. Second, with a CMOS sensor the intense spectral lines can be read multiple times within a frame to give a significant increase in dynamic range. We will describe the design, and initial test of a CMOS sensor for use in hyperspectral applications. This device has been designed to give as high a dynamic range as possible with minimum cross-talk. The sensor has been manufactured on high resistivity epitaxial silicon wafers and is be back-thinned and left relatively thick in order to obtain the maximum quantum efficiency across the entire spectral range

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

NASA Astrophysics Data System (ADS)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Microstructures and fatigue life of SnAgCu solder joints bearing Nano-Al particles in QFP devices

NASA Astrophysics Data System (ADS)

Zhang, Liang; Fan, Xi-ying; Guo, Yong-huan; He, Cheng-wen

2014-05-01

Microstructures and fatigue life of SnAgCu and SnAgCu bearing nano-Al particles in QFP (Quad flat package) devices were investigated, respectively. Results show that the addition of nano-Al particles into SnAgCu solder can refine the microstructures of matrix microstructure. Moreover, the nano-Al particles present in the solder matrix, act as obstacles which can create a back stress, resisting the motion of dislocations. In QFP device, it is found that the addition of nano-Al particles can increase the fatigue life by 32% compared with the SnAgCu solder joints during thermal cycling loading.

Novel nano materials for high performance logic and memory devices

NASA Astrophysics Data System (ADS)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

A highly efficient CMOS nanoplasmonic crystal enhanced slow-wave thermal emitter improves infrared gas-sensing devices

PubMed Central

Pusch, Andreas; De Luca, Andrea; Oh, Sang S.; Wuestner, Sebastian; Roschuk, Tyler; Chen, Yiguo; Boual, Sophie; Ali, Zeeshan; Phillips, Chris C.; Hong, Minghui; Maier, Stefan A.; Udrea, Florin; Hopper, Richard H.; Hess, Ortwin

2015-01-01

The application of plasmonics to thermal emitters is generally assisted by absorptive losses in the metal because Kirchhoff’s law prescribes that only good absorbers make good thermal emitters. Based on a designed plasmonic crystal and exploiting a slow-wave lattice resonance and spontaneous thermal plasmon emission, we engineer a tungsten-based thermal emitter, fabricated in an industrial CMOS process, and demonstrate its markedly improved practical use in a prototype non-dispersive infrared (NDIR) gas-sensing device. We show that the emission intensity of the thermal emitter at the CO2 absorption wavelength is enhanced almost 4-fold compared to a standard non-plasmonic emitter, which enables a proportionate increase in the signal-to-noise ratio of the CO2 gas sensor. PMID:26639902

Reliability evaluation of CMOS RAMs

NASA Astrophysics Data System (ADS)

Salvo, C. J.; Sasaki, A. T.

The results of an evaluation of the reliability of a 1K x 1 bit CMOS RAM and a 4K x 1 bit CMOS RAM for the USAF are reported. The tests consisted of temperature cycling, thermal shock, electrical overstress-static discharge and accelerated life test cells. The study indicates that the devices have high reliability potential for military applications. Use-temperature failure rates at 100 C were 0.54 x 10 to the -5th failures/hour for the 1K RAM and 0.21 x 10 to the -5th failures/hour for the 4K RAM. Only minimal electrostatic discharge damage was noted in the devices when they were subjected to multiple pulses at 1000 Vdc, and redesign of the 7 Vdc quiescent parameter of the 4K RAM is expected to raise its field threshold voltage.

Design and fabrication of vertically-integrated CMOS image sensors.

PubMed

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors.

Fully CMOS-compatible titanium nitride nanoantennas

DOE Office of Scientific and Technical Information (OSTI.GOV)

Briggs, Justin A., E-mail: jabriggs@stanford.edu; Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305; Naik, Gururaj V.

CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements onmore » plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.« less

Step-gate polysilicon nanowires field effect transistor compatible with CMOS technology for label-free DNA biosensor.

PubMed

Wenga, G; Jacques, E; Salaün, A-C; Rogel, R; Pichon, L; Geneste, F

2013-02-15

Currently, detection of DNA hybridization using fluorescence-based detection technique requires expensive optical systems and complex bioinformatics tools. Hence, the development of new low cost devices that enable direct and highly sensitive detection stimulates a lot of research efforts. Particularly, devices based on silicon nanowires are emerging as ultrasensitive electrical sensors for the direct detection of biological species thanks to their high surface to volume ratio. In this study, we propose innovative devices using step-gate polycrystalline silicon nanowire FET (poly-Si NW FETs), achieved with simple and low cost fabrication process, and used as ultrasensitive electronic sensor for DNA hybridization. The poly-SiNWs are synthesized using the sidewall spacer formation technique. The detailed fabrication procedure for a step-gate NWFET sensor is described in this paper. No-complementary and complementary DNA sequences were clearly discriminated and detection limit to 1 fM range is observed. This first result using this nano-device is promising for the development of low cost and ultrasensitive polysilicon nanowires based DNA sensors compatible with the CMOS technology. Copyright © 2012 Elsevier B.V. All rights reserved.

Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

NASA Astrophysics Data System (ADS)

Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

2017-05-01

Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems

DOEpatents

Welch, James D.

2003-09-23

Disclosed are semiconductor devices including at least one junction which is rectifying whether the semiconductor is caused to be N or P-type, by the presence of applied gate voltage field induced carriers in essentially intrinsic, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at substantially equal doping levels, essentially homogeneously simultaneously containing both N and P-type metallurgical dopants at different doping levels, and containing a single metallurgical doping type, and functional combinations thereof. In particular, inverting and non-inverting gate voltage channel induced semiconductor single devices with operating characteristics similar to conventional multiple device CMOS systems, which can be operated as modulators, are disclosed as are a non-latching SCR and an approach to blocking parasitic currents utilizing material(s) which form rectifying junctions with both N and P-type semiconductor whether metallurigically or field induced.

Electronic and optoelectronic nano-devices based on carbon nanotubes.

PubMed

Scarselli, M; Castrucci, P; De Crescenzi, M

2012-08-08

The discovery and understanding of nanoscale phenomena and the assembly of nanostructures into different devices are among the most promising fields of material science research. In this scenario, carbon nanostructures have a special role since, in having only one chemical element, they allow physical properties to be calculated with high precision for comparison with experiment. Carbon nanostructures, and carbon nanotubes (CNTs) in particular, have such remarkable electronic and structural properties that they are used as active building blocks for a large variety of nanoscale devices. We review here the latest advances in research involving carbon nanotubes as active components in electronic and optoelectronic nano-devices. Opportunities for future research are also identified.

Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

NASA Astrophysics Data System (ADS)

Sengupta, Abhronil; Banerjee, Aparajita; Roy, Kaushik

2016-12-01

Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet-heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

A dynamically tunable plasmonic multi-functional device based on graphene nano-sheet pair arrays

NASA Astrophysics Data System (ADS)

Wang, Wei; Meng, Zhao; Liang, Ruisheng; Chen, Shijie; Ding, Li; Wang, Faqiang; Liu, Hongzhan; Meng, Hongyun; Wei, Zhongchao

2018-05-01

Dynamically tunable plasmonic multi-functional is particularly desirable for various nanotechnological applications. In this paper, graphene nano-sheet pair arrays separated by a substrate, which can act as a dynamically tunable plasmonic band stop filter with transmission at resonance wavelength lower than 1%, a high sensitivity refractive index sensor with sensitivity up to 4879 nm/RIU, figure of merit of 40.66 and a two circuit optical switch with the modulation depth up to 0.998, are proposed and numerically investigated. These excellent optical performances are calculated by using FDTD numerical modeling and theoretical deduction. Simulation results show that a slight variation of chemical potential of the graphene nano-sheet can achieve significant resonance wavelength shifts. In additional, the resonance wavelength and transmission of this plasmonic device can be tuned easily by two voltages owing to the simple patterned graphene. These studies may have great potential in fabrication of multi-functional and dynamically tunable optoelectronic integrated devices.

324GHz CMOS VCO Using Linear Superimposition Technique

NASA Technical Reports Server (NTRS)

Daquan, Huang; LaRocca, Tim R.; Samoska, Lorene A; Fung, Andy; Chang, Frank

2007-01-01

Terahertz (frequencies ranged from 300GHz to 3THz) imaging and spectroscopic systems have drawn increasing attention recently due to their unique capabilities in detecting and possibly analyzing concealed objects. The generation of terahertz signals is nonetheless nontrivial and traditionally accomplished by using either free-electron radiation, optical lasers, Gunn diodes or fundamental oscillation by using III-V based HBT/HEMT technology[1-3]... We have substantially extended the operation range of deep-scaled CMOS by using a linear superimposition method, in which we have realized a 324GHz VCO in 90nm digital CMOS with 4GHz tuning range under 1V supply voltage. This may also pave the way for ultra-high data rate wireless communications beyond that of IEEE 802.15.3c and reach data rates comparable to that of fiber optical communications, such as OC768 (40Gbps) and beyond.

Users Guide on Scaled CMOS Reliability: NASA Electronic Parts and Packaging (NEPP) Program Office of Safety and Mission Assurance

NASA Technical Reports Server (NTRS)

White, Mark; Cooper, Mark; Johnston, Allan

2011-01-01

Reliability of advanced CMOS technology is a complex problem that is usually addressed from the standpoint of specific failure mechanisms rather than overall reliability of a finished microcircuit. A detailed treatment of CMOS reliability in scaled devices can be found in Ref. 1; it should be consulted for a more thorough discussion. The present document provides a more concise treatment of the scaled CMOS reliability problem, emphasizing differences in the recommended approach for these advanced devices compared to that of less aggressively scaled devices. It includes specific recommendations that can be used by flight projects that use advanced CMOS. The primary emphasis is on conventional memories, microprocessors, and related devices.

Accelerated life testing effects on CMOS microcircuit characteristics

NASA Technical Reports Server (NTRS)

1979-01-01

Modifications and additions to the present process of making CMOS microcircuits which are designed to provide protective layers on the chip to guard against moisture and contaminants were investigated. High and low temperature Si3N4 protective layers were tested on the CMOS microcircuits and no conclusive improvements in device reliability characteristics were evidenced.

Low Energy Dissipation Nano Device Research

NASA Astrophysics Data System (ADS)

Yu, Jenny

2015-03-01

The development of research on energy dissipation has been rapid in energy efficient area. Nano-material power FET is operated as an RF power amplifier, the transport is ballistic, noise is limited and power dissipation is minimized. The goal is Green-save energy by developing the Graphene and carbon nantube microwave and high performance devices. Higher performing RF amplifiers can have multiple impacts on broadly field, for example communication equipment, (such as mobile phone and RADAR); higher power density and lower power dissipation will improve spectral efficiency which translates into higher system level bandwidth and capacity for communications equipment. Thus, fundamental studies of power handling capabilities of new RF (nano)technologies can have broad, sweeping impact. Because it is critical to maximizing the power handling ability of grephene and carbon nanotube FET, the initial task focuses on measuring and understanding the mechanism of electrical breakdown. We aim specifically to determine how the breakdown voltage in graphene and nanotubes is related to the source-drain spacing, electrode material and thickness, and substrate, and thus develop reliable statistics on the breakdown mechanism and probability.

Fabrication of pseudo-spin-MOSFETs using a multi-project wafer CMOS chip

NASA Astrophysics Data System (ADS)

Nakane, R.; Shuto, Y.; Sukegawa, H.; Wen, Z. C.; Yamamoto, S.; Mitani, S.; Tanaka, M.; Inomata, K.; Sugahara, S.

2014-12-01

We demonstrate monolithic integration of pseudo-spin-MOSFETs (PS-MOSFETs) using vendor-made MOSFETs fabricated in a low-cost multi-project wafer (MPW) product and lab-made magnetic tunnel junctions (MTJs) formed on the topmost passivation film of the MPW chip. The tunneling magnetoresistance (TMR) ratio of the fabricated MTJs strongly depends on the surface roughness of the passivation film. Nevertheless, after the chip surface was atomically flattened by SiO2 deposition on it and successive chemical-mechanical polish (CMP) process for the surface, the fabricated MTJs on the chip exhibits a sufficiently large TMR ratio (>140%) adaptable to the PS-MOSFET application. The implemented PS-MOSFETs show clear modulation of the output current controlled by the magnetization configuration of the MTJs, and a maximum magnetocurrent ratio of 90% is achieved. These magnetocurrent behaviour is quantitatively consistent with those predicted by HSPICE simulations. The developed integration technique using a MPW CMOS chip would also be applied to monolithic integration of CMOS devices/circuits and other various functional devices/materials, which would open the door for exploring CMOS-based new functional hybrid circuits.

Rare-earth doped transparent nano-glass-ceramics: a new generation of photonic integrated devices

NASA Astrophysics Data System (ADS)

Rodríguez-Armas, Vicente Daniel; Tikhomirov, Victor K.; Méndez-Ramos, Jorge; Yanes, Angel C.; Del-Castillo, Javier; Furniss, David; Seddon, Angela B.

2007-05-01

We report on optical properties and prospect applications on rare-earth doped oxyfluoride precursor glass and ensuing nano-glass-ceramics. We find out the spectral optical gain of the nano-glass-ceramics and show that its flatness and breadth are advantageous as compared to contemporary used erbium doped optical amplifiers. We present the possibility of flat gain cross-section erbium doped waveguide amplifiers as short 'chip', all-optical, devices capable of dense wavelength division multiplexing, including the potential for direct writing of these devices inside bulk glasses for three-dimensional photonic integration. We carried out a comparative study of the up-conversion luminescence in Er 3+-doped and Yb 3+-Er 3+-Tm 3+ co-doped samples, which indicates that these materials can be used as green/red tuneable up-conversion phosphors and white light simulation respectively. Observed changes in the spectra of the up-conversion luminescence provide a tool for tuning the colour opening the way for producing 3-dimensional optical recording.

A novel multi-actuation CMOS RF MEMS switch

NASA Astrophysics Data System (ADS)

Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

2008-12-01

This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

Single photon detection using Geiger mode CMOS avalanche photodiodes

NASA Astrophysics Data System (ADS)

Lawrence, William G.; Stapels, Christopher; Augustine, Frank L.; Christian, James F.

2005-10-01

Geiger mode Avalanche Photodiodes fabricated using complementary metal-oxide-semiconductor (CMOS) fabrication technology combine high sensitivity detectors with pixel-level auxiliary circuitry. Radiation Monitoring Devices has successfully implemented CMOS manufacturing techniques to develop prototype detectors with active diameters ranging from 5 to 60 microns and measured detection efficiencies of up to 60%. CMOS active quenching circuits are included in the pixel layout. The actively quenched pixels have a quenching time less than 30 ns and a maximum count rate greater than 10 MHz. The actively quenched Geiger mode avalanche photodiode (GPD) has linear response at room temperature over six orders of magnitude. When operating in Geiger mode, these GPDs act as single photon-counting detectors that produce a digital output pulse for each photon with no associated read noise. Thermoelectrically cooled detectors have less than 1 Hz dark counts. The detection efficiency, dark count rate, and after-pulsing of two different pixel designs are measured and demonstrate the differences in the device operation. Additional applications for these devices include nuclear imaging and replacement of photomultiplier tubes in dosimeters.

A microfluidic device integrating dual CMOS polysilicon nanowire sensors for on-chip whole blood processing and simultaneous detection of multiple analytes.

PubMed

Kuan, Da-Han; Wang, I-Shun; Lin, Jiun-Rue; Yang, Chao-Han; Huang, Chi-Hsien; Lin, Yen-Hung; Lin, Chih-Ting; Huang, Nien-Tsu

2016-08-02

The hemoglobin-A1c test, measuring the ratio of glycated hemoglobin (HbA1c) to hemoglobin (Hb) levels, has been a standard assay in diabetes diagnosis that removes the day-to-day glucose level variation. Currently, the HbA1c test is restricted to hospitals and central laboratories due to the laborious, time-consuming whole blood processing and bulky instruments. In this paper, we have developed a microfluidic device integrating dual CMOS polysilicon nanowire sensors (MINS) for on-chip whole blood processing and simultaneous detection of multiple analytes. The micromachined polymethylmethacrylate (PMMA) microfluidic device consisted of a serpentine microchannel with multiple dam structures designed for non-lysed cells or debris trapping, uniform plasma/buffer mixing and dilution. The CMOS-fabricated polysilicon nanowire sensors integrated with the microfluidic device were designed for the simultaneous, label-free electrical detection of multiple analytes. Our study first measured the Hb and HbA1c levels in 11 clinical samples via these nanowire sensors. The results were compared with those of standard Hb and HbA1c measurement methods (Hb: the sodium lauryl sulfate hemoglobin detection method; HbA1c: cation-exchange high-performance liquid chromatography) and showed comparable outcomes. Finally, we successfully demonstrated the efficacy of the MINS device's on-chip whole blood processing followed by simultaneous Hb and HbA1c measurement in a clinical sample. Compared to current Hb and HbA1c sensing instruments, the MINS platform is compact and can simultaneously detect two analytes with only 5 μL of whole blood, which corresponds to a 300-fold blood volume reduction. The total assay time, including the in situ sample processing and analyte detection, was just 30 minutes. Based on its on-chip whole blood processing and simultaneous multiple analyte detection functionalities with a lower sample volume requirement and shorter process time, the MINS device can be

Monolithic optical phased-array transceiver in a standard SOI CMOS process.

PubMed

Abediasl, Hooman; Hashemi, Hossein

2015-03-09

Monolithic microwave phased arrays are turning mainstream in automotive radars and high-speed wireless communications fulfilling Gordon Moores 1965 prophecy to this effect. Optical phased arrays enable imaging, lidar, display, sensing, and holography. Advancements in fabrication technology has led to monolithic nanophotonic phased arrays, albeit without independent phase and amplitude control ability, integration with electronic circuitry, or including receive and transmit functions. We report the first monolithic optical phased array transceiver with independent control of amplitude and phase for each element using electronic circuitry that is tightly integrated with the nanophotonic components on one substrate using a commercial foundry CMOS SOI process. The 8 × 8 phased array chip includes thermo-optical tunable phase shifters and attenuators, nano-photonic antennas, and dedicated control electronics realized using CMOS transistors. The complex chip includes over 300 distinct optical components and over 74,000 distinct electrical components achieving the highest level of integration for any electronic-photonic system.

Design and fabrication of a CMOS-compatible MHP gas sensor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Ying; Yu, Jun, E-mail: junyu@dlut.edu.cn; Wu, Hao

2014-03-15

A novel micro-hotplate (MHP) gas sensor is designed and fabricated with a standard CMOS technology followed by post-CMOS processes. The tungsten plugging between the first and the second metal layer in the CMOS processes is designed as zigzag resistor heaters embedded in the membrane. In the post-CMOS processes, the membrane is released by front-side bulk silicon etching, and excellent adiabatic performance of the sensor is obtained. Pt/Ti electrode films are prepared on the MHP before the coating of the SnO{sub 2} film, which are promising to present better contact stability compared with Al electrodes. Measurements show that at room temperaturemore » in atmosphere, the device has a low power consumption of ∼19 mW and a rapid thermal response of 8 ms for heating up to 300 °C. The tungsten heater exhibits good high temperature stability with a slight fluctuation (<0.3%) in the resistance at an operation temperature of 300 °C under constant heating mode for 336 h, and a satisfactory temperature coefficient of resistance of about 1.9‰/°C.« less

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

NASA Astrophysics Data System (ADS)

Chung, Jae-Moon; Zhang, Xiaokun; Shang, Fei; Kim, Ji-Hoon; Wang, Xiao-Lin; Liu, Shuai; Yang, Baoguo; Xiang, Yong

2018-05-01

To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO-based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer ( 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm2/V s and the V th uniformity of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured V th shift of CL-ES-structured device significantly decreased to - 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (- 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor-based process for LCD fabrication is highly feasible.

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

PubMed Central

Skorka, Orit; Joseph, Dileepan

2011-01-01

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

Nano Superconducting Quantum Interference device: A powerful tool for nanoscale investigations

NASA Astrophysics Data System (ADS)

Granata, Carmine; Vettoliere, Antonio

2016-02-01

The magnetic sensing at nanoscale level is a promising and interesting research topic of nanoscience. Indeed, magnetic imaging is a powerful tool for probing biological, chemical and physical systems. The study of small spin cluster, like magnetic molecules and nanoparticles, single electron, cold atom clouds, is one of the most stimulating challenges of applied and basic research of the next years. In particular, the magnetic nanoparticle investigation plays a fundamental role for the modern material science and its relative technological applications like ferrofluids, magnetic refrigeration and biomedical applications, including drug delivery, hyper-thermia cancer treatment and magnetic resonance imaging contrast-agent. Actually, one of the most ambitious goals of the high sensitivity magnetometry is the detection of elementary magnetic moment or spin. In this framework, several efforts have been devoted to the development of a high sensitivity magnetic nanosensor pushing sensing capability to the individual spin level. Among the different magnetic sensors, Superconducting QUantum Interference Devices (SQUIDs) exhibit an ultra high sensitivity and are widely employed in numerous applications. Basically, a SQUID consists of a superconducting ring (sensitive area) interrupted by two Josephson junctions. In the recent years, it has been proved that the magnetic response of nano-objects can be effectively measured by using a SQUID with a very small sensitive area (nanoSQUID). In fact, the sensor noise, expressed in terms of the elementary magnetic moment (spin or Bohr magneton), is linearly dependent on the SQUID loop side length. For this reason, SQUIDs have been progressively miniaturized in order to improve the sensitivity up to few spin per unit of bandwidth. With respect to other techniques, nanoSQUIDs offer the advantage of direct measurement of magnetization changes in small spin systems. In this review, we focus on nanoSQUIDs and its applications. In

Monolithic CMOS imaging x-ray spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus; Kraft, Ralph; Gauron, Thomas; Murray, Stephen S.

2014-07-01

The Smithsonian Astrophysical Observatory (SAO) in collaboration with SRI/Sarnoff is developing monolithic CMOS detectors optimized for x-ray astronomy. The goal of this multi-year program is to produce CMOS x-ray imaging spectrometers that are Fano noise limited over the 0.1-10keV energy band while incorporating the many benefits of CMOS technology. These benefits include: low power consumption, radiation "hardness", high levels of integration, and very high read rates. Small format test devices from a previous wafer fabrication run (2011-2012) have recently been back-thinned and tested for response below 1keV. These devices perform as expected in regards to dark current, read noise, spectral response and Quantum Efficiency (QE). We demonstrate that running these devices at rates ~> 1Mpix/second eliminates the need for cooling as shot noise from any dark current is greatly mitigated. The test devices were fabricated on 15μm, high resistivity custom (~30kΩ-cm) epitaxial silicon and have a 16 by 192 pixel format. They incorporate 16μm pitch, 6 Transistor Pinned Photo Diode (6TPPD) pixels which have ~40μV/electron sensitivity and a highly parallel analog CDS signal chain. Newer, improved, lower noise detectors have just been fabricated (October 2013). These new detectors are fabricated on 9μm epitaxial silicon and have a 1k by 1k format. They incorporate similar 16μm pitch, 6TPPD pixels but have ~ 50% higher sensitivity and much (3×) lower read noise. These new detectors have undergone preliminary testing for functionality in Front Illuminated (FI) form and are presently being prepared for back thinning and packaging. Monolithic CMOS devices such as these, would be ideal candidate detectors for the focal planes of Solar, planetary and other space-borne x-ray astronomy missions. The high through-put, low noise and excellent low energy response, provide high dynamic range and good time resolution; bright, time varying x-ray features could be temporally and

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

PubMed Central

Feruglio, Sylvain; Lu, Guo-Neng; Garda, Patrick; Vasilescu, Gabriel

2008-01-01

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications. PMID:27873887

Fabrication and Characterization of a CMOS-MEMS Humidity Sensor.

PubMed

Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

2015-07-10

This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

Fabrication and Characterization of a CMOS-MEMS Humidity Sensor

PubMed Central

Dennis, John-Ojur; Ahmed, Abdelaziz-Yousif; Khir, Mohd-Haris

2015-01-01

This paper reports on the fabrication and characterization of a Complementary Metal Oxide Semiconductor-Microelectromechanical System (CMOS-MEMS) device with embedded microheater operated at relatively elevated temperatures (40 °C to 80 °C) for the purpose of relative humidity measurement. The sensing principle is based on the change in amplitude of the device due to adsorption or desorption of humidity on the active material layer of titanium dioxide (TiO2) nanoparticles deposited on the moving plate, which results in changes in the mass of the device. The sensor has been designed and fabricated through a standard 0.35 µm CMOS process technology and post-CMOS micromachining technique has been successfully implemented to release the MEMS structures. The sensor is operated in the dynamic mode using electrothermal actuation and the output signal measured using a piezoresistive (PZR) sensor connected in a Wheatstone bridge circuit. The output voltage of the humidity sensor increases from 0.585 mV to 30.580 mV as the humidity increases from 35% RH to 95% RH. The output voltage is found to be linear from 0.585 mV to 3.250 mV as the humidity increased from 35% RH to 60% RH, with sensitivity of 0.107 mV/% RH; and again linear from 3.250 mV to 30.580 mV as the humidity level increases from 60% RH to 95% RH, with higher sensitivity of 0.781 mV/% RH. On the other hand, the sensitivity of the humidity sensor increases linearly from 0.102 mV/% RH to 0.501 mV/% RH with increase in the temperature from 40 °C to 80 °C and a maximum hysteresis of 0.87% RH is found at a relative humidity of 80%. The sensitivity is also frequency dependent, increasing from 0.500 mV/% RH at 2 Hz to reach a maximum value of 1.634 mV/% RH at a frequency of 12 Hz, then decreasing to 1.110 mV/% RH at a frequency of 20 Hz. Finally, the CMOS-MEMS humidity sensor showed comparable response, recovery, and repeatability of measurements in three cycles as compared to a standard sensor that directly

Comparison of technologies for nano device prototyping with a special focus on ion beams: A review

NASA Astrophysics Data System (ADS)

Bruchhaus, L.; Mazarov, P.; Bischoff, L.; Gierak, J.; Wieck, A. D.; Hövel, H.

2017-03-01

Nano device prototyping (NDP) is essential for realizing and assessing ideas as well as theories in the form of nano devices, before they can be made available in or as commercial products. In this review, application results patterned similarly to those in the semiconductor industry (for cell phone, computer processors, or memory) will be presented. For NDP, some requirements are different: thus, other technologies are employed. Currently, in NDP, for many applications direct write Gaussian vector scan electron beam lithography (EBL) is used to define the required features in organic resists on this scale. We will take a look at many application results carried out by EBL, self-organized 3D epitaxy, atomic probe microscopy (scanning tunneling microscope/atomic force microscope), and in more detail ion beam techniques. For ion beam techniques, there is a special focus on those based upon liquid metal (alloy) ion sources, as recent developments have significantly increased their applicability for NDP.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states

NASA Astrophysics Data System (ADS)

Kim, Taeho; Hur, Ji-Hyun; Jeon, Sanghun

2016-05-01

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

Pulse I-V characterization of a nano-crystalline oxide device with sub-gap density of states.

PubMed

Kim, Taeho; Hur, Ji-Hyun; Jeon, Sanghun

2016-05-27

Understanding the charge trapping nature of nano-crystalline oxide semiconductor thin film transistors (TFTs) is one of the most important requirements for their successful application. In our investigation, we employed a fast-pulsed I-V technique for understanding the charge trapping phenomenon and for characterizing the intrinsic device performance of an amorphous/nano-crystalline indium-hafnium-zinc-oxide semiconductor TFT with varying density of states in the bulk. Because of the negligible transient charging effect with a very short pulse, the source-to-drain current obtained with the fast-pulsed I-V measurement was higher than that measured by the direct-current characterization method. This is because the fast-pulsed I-V technique provides a charge-trap free environment, suggesting that it is a representative device characterization methodology of TFTs. In addition, a pulsed source-to-drain current versus time plot was used to quantify the dynamic trapping behavior. We found that the charge trapping phenomenon in amorphous/nano-crystalline indium-hafnium-zinc-oxide TFTs is attributable to the charging/discharging of sub-gap density of states in the bulk and is dictated by multiple trap-to-trap processes.

Investigation of HV/HR-CMOS technology for the ATLAS Phase-II Strip Tracker Upgrade

NASA Astrophysics Data System (ADS)

Fadeyev, V.; Galloway, Z.; Grabas, H.; Grillo, A. A.; Liang, Z.; Martinez-Mckinney, F.; Seiden, A.; Volk, J.; Affolder, A.; Buckland, M.; Meng, L.; Arndt, K.; Bortoletto, D.; Huffman, T.; John, J.; McMahon, S.; Nickerson, R.; Phillips, P.; Plackett, R.; Shipsey, I.; Vigani, L.; Bates, R.; Blue, A.; Buttar, C.; Kanisauskas, K.; Maneuski, D.; Benoit, M.; Di Bello, F.; Caragiulo, P.; Dragone, A.; Grenier, P.; Kenney, C.; Rubbo, F.; Segal, J.; Su, D.; Tamma, C.; Das, D.; Dopke, J.; Turchetta, R.; Wilson, F.; Worm, S.; Ehrler, F.; Peric, I.; Gregor, I. M.; Stanitzki, M.; Hoeferkamp, M.; Seidel, S.; Hommels, L. B. A.; Kramberger, G.; Mandić, I.; Mikuž, M.; Muenstermann, D.; Wang, R.; Zhang, J.; Warren, M.; Song, W.; Xiu, Q.; Zhu, H.

2016-09-01

ATLAS has formed strip CMOS project to study the use of CMOS MAPS devices as silicon strip sensors for the Phase-II Strip Tracker Upgrade. This choice of sensors promises several advantages over the conventional baseline design, such as better resolution, less material in the tracking volume, and faster construction speed. At the same time, many design features of the sensors are driven by the requirement of minimizing the impact on the rest of the detector. Hence the target devices feature long pixels which are grouped to form a virtual strip with binary-encoded z position. The key performance aspects are radiation hardness compatibility with HL-LHC environment, as well as extraction of the full hit position with full-reticle readout architecture. To date, several test chips have been submitted using two different CMOS technologies. The AMS 350 nm is a high voltage CMOS process (HV-CMOS), that features the sensor bias of up to 120 V. The TowerJazz 180 nm high resistivity CMOS process (HR-CMOS) uses a high resistivity epitaxial layer to provide the depletion region on top of the substrate. We have evaluated passive pixel performance, and charge collection projections. The results strongly support the radiation tolerance of these devices to radiation dose of the HL-LHC in the strip tracker region. We also describe design features for the next chip submission that are motivated by our technology evaluation.

Resolution Properties of a Calcium Tungstate (CaWO4) Screen Coupled to a CMOS Imaging Detector

NASA Astrophysics Data System (ADS)

Koukou, Vaia; Martini, Niki; Valais, Ioannis; Bakas, Athanasios; Kalyvas, Nektarios; Lavdas, Eleftherios; Fountos, George; Kandarakis, Ioannis; Michail, Christos

2017-11-01

The aim of the current work was to assess the resolution properties of a calcium tungstate (CaWO4) screen (screen coating thickness: 50.09 mg/cm2, actual thickness: 167.2 μm) coupled to a high resolution complementary metal oxide semiconductor (CMOS) digital imaging sensor. A 2.7x3.6 cm2 CaWO4 sample was extracted from an Agfa Curix universal screen and was coupled directly with the active area of the active pixel sensor (APS) CMOS sensor. Experiments were performed following the new IEC 62220-1-1:2015 International Standard, using an RQA-5 beam quality. Resolution was assessed in terms of the Modulation Transfer Function (MTF), using the slanted-edge method. The CaWO4/CMOS detector configuration was found with linear response, in the exposure range under investigation. The final MTF was obtained through averaging the oversampled edge spread function (ESF), using a custom-made software developed by our team, according to the IEC 62220-1-1:2015. Considering the renewed interest in calcium tungstate for various applications, along with the resolution results of this work, CaWO4 could be also considered for use in X-ray imaging devices such as charged-coupled devices (CCD) and CMOS.

Small Pixel Hybrid CMOS X-ray Detectors

NASA Astrophysics Data System (ADS)

Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

2018-01-01

Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

An acquisition system for CMOS imagers with a genuine 10 Gbit/s bandwidth

NASA Astrophysics Data System (ADS)

Guérin, C.; Mahroug, J.; Tromeur, W.; Houles, J.; Calabria, P.; Barbier, R.

2012-12-01

This paper presents a high data throughput acquisition system for pixel detector readout such as CMOS imagers. This CMOS acquisition board offers a genuine 10 Gbit/s bandwidth to the workstation and can provide an on-line and continuous high frame rate imaging capability. On-line processing can be implemented either on the Data Acquisition Board or on the multi-cores workstation depending on the complexity of the algorithms. The different parts composing the acquisition board have been designed to be used first with a single-photon detector called LUSIPHER (800×800 pixels), developed in our laboratory for scientific applications ranging from nano-photonics to adaptive optics. The architecture of the acquisition board is presented and the performances achieved by the produced boards are described. The future developments (hardware and software) concerning the on-line implementation of algorithms dedicated to single-photon imaging are tackled.

Design and Fabrication of High-Efficiency CMOS/CCD Imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata

2007-01-01

An architecture for back-illuminated complementary metal oxide/semiconductor (CMOS) and charge-coupled-device (CCD) ultraviolet/visible/near infrared- light image sensors, and a method of fabrication to implement the architecture, are undergoing development. The architecture and method are expected to enable realization of the full potential of back-illuminated CMOS/CCD imagers to perform with high efficiency, high sensitivity, excellent angular response, and in-pixel signal processing. The architecture and method are compatible with next-generation CMOS dielectric-forming and metallization techniques, and the process flow of the method is compatible with process flows typical of the manufacture of very-large-scale integrated (VLSI) circuits. The architecture and method overcome all obstacles that have hitherto prevented high-yield, low-cost fabrication of back-illuminated CMOS/CCD imagers by use of standard VLSI fabrication tools and techniques. It is not possible to discuss the obstacles in detail within the space available for this article. Briefly, the obstacles are posed by the problems of generating light-absorbing layers having desired uniform and accurate thicknesses, passivation of surfaces, forming structures for efficient collection of charge carriers, and wafer-scale thinning (in contradistinction to diescale thinning). A basic element of the present architecture and method - the element that, more than any other, makes it possible to overcome the obstacles - is the use of an alternative starting material: Instead of starting with a conventional bulk-CMOS wafer that consists of a p-doped epitaxial silicon layer grown on a heavily-p-doped silicon substrate, one starts with a special silicon-on-insulator (SOI) wafer that consists of a thermal oxide buried between a lightly p- or n-doped, thick silicon layer and a device silicon layer of appropriate thickness and doping. The thick silicon layer is used as a handle: that is, as a mechanical support for the

CMOL/CMOS hardware architectures and performance/price for Bayesian memory - The building block of intelligent systems

NASA Astrophysics Data System (ADS)

Zaveri, Mazad Shaheriar

The semiconductor/computer industry has been following Moore's law for several decades and has reaped the benefits in speed and density of the resultant scaling. Transistor density has reached almost one billion per chip, and transistor delays are in picoseconds. However, scaling has slowed down, and the semiconductor industry is now facing several challenges. Hybrid CMOS/nano technologies, such as CMOL, are considered as an interim solution to some of the challenges. Another potential architectural solution includes specialized architectures for applications/models in the intelligent computing domain, one aspect of which includes abstract computational models inspired from the neuro/cognitive sciences. Consequently in this dissertation, we focus on the hardware implementations of Bayesian Memory (BM), which is a (Bayesian) Biologically Inspired Computational Model (BICM). This model is a simplified version of George and Hawkins' model of the visual cortex, which includes an inference framework based on Judea Pearl's belief propagation. We then present a "hardware design space exploration" methodology for implementing and analyzing the (digital and mixed-signal) hardware for the BM. This particular methodology involves: analyzing the computational/operational cost and the related micro-architecture, exploring candidate hardware components, proposing various custom hardware architectures using both traditional CMOS and hybrid nanotechnology - CMOL, and investigating the baseline performance/price of these architectures. The results suggest that CMOL is a promising candidate for implementing a BM. Such implementations can utilize the very high density storage/computation benefits of these new nano-scale technologies much more efficiently; for example, the throughput per 858 mm2 (TPM) obtained for CMOL based architectures is 32 to 40 times better than the TPM for a CMOS based multiprocessor/multi-FPGA system, and almost 2000 times better than the TPM for a PC

Development of a 750x750 pixels CMOS imager sensor for tracking applications

NASA Astrophysics Data System (ADS)

Larnaudie, Franck; Guardiola, Nicolas; Saint-Pé, Olivier; Vignon, Bruno; Tulet, Michel; Davancens, Robert; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Estribeau, Magali

2017-11-01

Solid-state optical sensors are now commonly used in space applications (navigation cameras, astronomy imagers, tracking sensors...). Although the charge-coupled devices are still widely used, the CMOS image sensor (CIS), which performances are continuously improving, is a strong challenger for Guidance, Navigation and Control (GNC) systems. This paper describes a 750x750 pixels CMOS image sensor that has been specially designed and developed for star tracker and tracking sensor applications. Such detector, that is featuring smart architecture enabling very simple and powerful operations, is built using the AMIS 0.5μm CMOS technology. It contains 750x750 rectangular pixels with 20μm pitch. The geometry of the pixel sensitive zone is optimized for applications based on centroiding measurements. The main feature of this device is the on-chip control and timing function that makes the device operation easier by drastically reducing the number of clocks to be applied. This powerful function allows the user to operate the sensor with high flexibility: measurement of dark level from masked lines, direct access to the windows of interest… A temperature probe is also integrated within the CMOS chip allowing a very precise measurement through the video stream. A complete electro-optical characterization of the sensor has been performed. The major parameters have been evaluated: dark current and its uniformity, read-out noise, conversion gain, Fixed Pattern Noise, Photo Response Non Uniformity, quantum efficiency, Modulation Transfer Function, intra-pixel scanning. The characterization tests are detailed in the paper. Co60 and protons irradiation tests have been also carried out on the image sensor and the results are presented. The specific features of the 750x750 image sensor such as low power CMOS design (3.3V, power consumption<100mW), natural windowing (that allows efficient and robust tracking algorithms), simple proximity electronics (because of the on

Design and simulation of multi-color infrared CMOS metamaterial absorbers

NASA Astrophysics Data System (ADS)

Cheng, Zhengxi; Chen, Yongping; Ma, Bin

2016-05-01

Metamaterial electromagnetic wave absorbers, which usually can be fabricated in a low weight thin film structure, have a near unity absorptivity in a special waveband, and therefore have been widely applied from microwave to optical waveband. To increase absorptance of CMOS MEMS devices in 2-5 μmm waveband, multi-color infrared metamaterial absorbers are designed with CSMC 0.5 μmm 2P3M and 0.18 μmm 1P6M CMOS technology in this work. Metal-insulator-metal (MIM) three-layer MMAs and Insulator-metal-insulator-metal (MIMI) four-layer MMAs are formed by CMOS metal interconnect layers and inter metal dielectrics layer. To broaden absorption waveband in 2-5μmm range, MMAs with a combination of different sizes cross bars are designed. The top metal layer is a periodic aluminum square array or cross bar array with width ranging from submicron to several microns. The absorption peak position and intensity of MMAs can be tuned by adjusting the top aluminum micro structure array. Post-CMOS process is adopted to fabricate MMAs. The infrared absorption spectra of MMAs are verified with finite element method simulation, and the effects of top metal structure sizes, patterns, and films thickness are also simulated and intensively discussed. The simulation results show that CMOS MEMS MMAs enhance infrared absorption in 2-20 μmm. The MIM broad MMA has an average absorptance of 0.22 in 2-5 μmm waveband, and 0.76 in 8-14 μm waveband. The CMOS metamaterial absorbers can be inherently integrated in many kinds of MEMS devices fabricated with CMOS technology, such as uncooled bolometers, infrared thermal emitters.

Laterally configured resistive switching device based on transition-metal nano-gap electrode on Gd oxide

DOE Office of Scientific and Technical Information (OSTI.GOV)

Kawakita, Masatoshi; Okabe, Kyota; Kimura, Takashi

2016-01-11

We have developed a fabrication process for a laterally configured resistive switching device based on a Gd oxide. A nano-gap electrode connected by a Gd oxide with the ideal interfaces has been created by adapting the electro-migration method in a metal/GdO{sub x} bilayer system. Bipolar set and reset operations have been clearly observed in the Pt/GdO{sub x} system similarly in the vertical device based on GdO{sub x}. Interestingly, we were able to observe a clear bipolar switching also in a ferromagnetic CoFeB nano-gap electrode with better stability compared to the Pt/GdO{sub x} device. The superior performance of the CoFeB/GdO{sub x}more » device implies the importance of the spin on the resistive switching.« less

Nanosecond-laser induced crosstalk of CMOS image sensor

NASA Astrophysics Data System (ADS)

Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

2018-02-01

The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

An integrated CMOS high voltage supply for lab-on-a-chip systems.

PubMed

Behnam, M; Kaigala, G V; Khorasani, M; Marshall, P; Backhouse, C J; Elliott, D G

2008-09-01

Electrophoresis is a mainstay of lab-on-a-chip (LOC) implementations of molecular biology procedures and is the basis of many medical diagnostics. High voltage (HV) power supplies are necessary in electrophoresis instruments and are a significant part of the overall system cost. This cost of instrumentation is a significant impediment to making LOC technologies more widely available. We believe one approach to overcoming this problem is to use microelectronic technology (complementary metal-oxide semiconductor, CMOS) to generate and control the HV. We present a CMOS-based chip (3 mm x 2.9 mm) that generates high voltages (hundreds of volts), switches HV outputs, and is powered by a 5 V input supply (total power of 28 mW) while being controlled using a standard computer serial interface. Microchip electrophoresis with laser induced fluorescence (LIF) detection is implemented using this HV CMOS chip. With the other advancements made in the LOC community (e.g. micro-fluidic and optical devices), these CMOS chips may ultimately enable 'true' LOC solutions where essentially all the microfluidics, photonics and electronics are on a single chip.

Nanos genes and their role in development and beyond.

PubMed

De Keuckelaere, Evi; Hulpiau, Paco; Saeys, Yvan; Berx, Geert; van Roy, Frans

2018-06-01

The hallmark of Nanos proteins is their typical (CCHC) 2 zinc finger motif (zf-nanos). Animals have one to four nanos genes. For example, the fruit fly and demosponge have only one nanos gene, zebrafish and humans have three, and Fugu rubripes has four. Nanos genes are mainly known for their evolutionarily preserved role in germ cell survival and pluripotency. Nanos proteins have been reported to bind the C-terminal RNA-binding domain of Pumilio to form a post-transcriptional repressor complex. Several observations point to a link between the miRNA-mediated repression complex and the Nanos/Pumilio complex. Repression of the E2F3 oncogene product is, indeed, mediated by cooperation between the Nanos/Pumilio complex and miRNAs. Another important interaction partner of Nanos is the CCR4-NOT deadenylase complex. Besides the tissue-specific contribution of Nanos proteins to normal development, their ectopic expression has been observed in several cancer cell lines and various human cancers. An inverse correlation between the expression levels of human Nanos1 and Nanos3 and E-cadherin was observed in several cancer cell lines. Loss of E-cadherin, an important cell-cell adhesion protein, contributes to tumor invasion and metastasis. Overexpression of Nanos3 induces epithelial-mesenchymal transition in lung cancer cell lines partly by repressing E-cadherin. Other than some most interesting data from Nanos knockout mice, little is known about mammalian Nanos proteins, and further research is needed. In this review, we summarize the main roles of Nanos proteins and discuss the emerging concept of Nanos proteins as oncofetal antigens.

Current-limiting challenges for all-spin logic devices

PubMed Central

Su, Li; Zhang, Youguang; Klein, Jacques-Olivier; Zhang, Yue; Bournel, Arnaud; Fert, Albert; Zhao, Weisheng

2015-01-01

All-spin logic device (ASLD) has attracted increasing interests as one of the most promising post-CMOS device candidates, thanks to its low power, non-volatility and logic-in-memory structure. Here we investigate the key current-limiting factors and develop a physics-based model of ASLD through nano-magnet switching, the spin transport properties and the breakdown characteristic of channel. First, ASLD with perpendicular magnetic anisotropy (PMA) nano-magnet is proposed to reduce the critical current (Ic0). Most important, the spin transport efficiency can be enhanced by analyzing the device structure, dimension, contact resistance as well as material parameters. Furthermore, breakdown current density (JBR) of spin channel is studied for the upper current limitation. As a result, we can deduce current-limiting conditions and estimate energy dissipation. Based on the model, we demonstrate ASLD with different structures and channel materials (graphene and copper). Asymmetric structure is found to be the optimal option for current limitations. Copper channel outperforms graphene in term of energy but seriously suffers from breakdown current limit. By exploring the current limit and performance tradeoffs, the optimization of ASLD is also discussed. This benchmarking model of ASLD opens up new prospects for design and implementation of future spintronics applications. PMID:26449410

Bias field tailored plasmonic nano-electrode for high-power terahertz photonic devices.

PubMed

Moon, Kiwon; Lee, Il-Min; Shin, Jun-Hwan; Lee, Eui Su; Kim, Namje; Lee, Won-Hui; Ko, Hyunsung; Han, Sang-Pil; Park, Kyung Hyun

2015-09-08

Photoconductive antennas with nano-structured electrodes and which show significantly improved performances have been proposed to satisfy the demand for compact and efficient terahertz (THz) sources. Plasmonic field enhancement was previously considered the dominant mechanism accounting for the improvements in the underlying physics. However, we discovered that the role of plasmonic field enhancement is limited and near-field distribution of bias field should be considered as well. In this paper, we clearly show that the locally enhanced bias field due to the size effect is much more important than the plasmonic enhanced absorption in the nano-structured electrodes for the THz emitters. Consequently, an improved nano-electrode design is presented by tailoring bias field distribution and plasmonic enhancement. Our findings will pave the way for new perspectives in the design and analysis of plasmonic nano-structures for more efficient THz photonic devices.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

NASA Astrophysics Data System (ADS)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Germanium CMOS potential from material and process perspectives: Be more positive about germanium

NASA Astrophysics Data System (ADS)

Toriumi, Akira; Nishimura, Tomonori

2018-01-01

CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is expected. This size scaling will end sooner or later, however, because the typical size is approaching the atomic distance level in crystalline Si. In addition, it is said that electron transport in FETs is ballistic or nearly ballistic, which means that the injection velocity at the virtual source is a physical parameter relevant for estimating the driving current. Channel-materials with higher carrier mobility than Si are nonetheless needed, and the carrier mobility in the channels is a parameter important with regard to increasing the injection velocity. Although the density of states in the channel has not been discussed often, it too is relevant for estimating the channel current. Both the mobility and the density of states are in principle related to the effective mass of the carrier. From this device physics viewpoint, we expect germanium (Ge) CMOS to be promising for scaling beyond the Si CMOS limit because the bulk mobility values of electrons and holes in Ge are much higher than those of electrons and holes in Si, and the electron effective mass in Ge is not much less than that in III-V compounds. There is a debate that Ge should be used for p-MOSFETs and III-V compounds for n-MOSFETs, but considering that the variability or nonuniformity of the FET performance in today’s CMOS LSIs is a big challenge, it seems that much more attention should be paid to the simplicity of the material design and of the processing steps. Nevertheless, Ge faces a number of challenges even in case that only the FET level is concerned. One of the big problems with Ge CMOS technology has been its poor performance in n-MOSFETs. While the hole mobility in p-FETs has been improved, the electron mobility in the inversion layer of Ge FETs remains a serious concern. If this is due to the inherent properties of Ge, only p-MOSFETs might be used for device applications. To make Ge CMOS devices

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

PubMed

Stefanov, Konstantin D; Clarke, Andrew S; Ivory, James; Holland, Andrew D

2018-01-03

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers.

PubMed

Chung, Jae-Moon; Zhang, Xiaokun; Shang, Fei; Kim, Ji-Hoon; Wang, Xiao-Lin; Liu, Shuai; Yang, Baoguo; Xiang, Yong

2018-05-29

To overcome the technological and economic obstacles of amorphous indium-gallium-zinc-oxide (a-IGZO)-based display backplane for industrial production, a clean etch-stopper (CL-ES) process is developed to fabricate a-IGZO-based thin film transistor (TFT) with improved uniformity and reproducibility on 8.5th generation glass substrates (2200 mm × 2500 mm). Compared with a-IGZO-based TFT with back-channel-etched (BCE) structure, a newly formed ES nano-layer (~ 100 nm) and a simultaneous etching of a-IGZO nano-layer (30 nm) and source-drain electrode layer are firstly introduced to a-IGZO-based TFT device with CL-ES structure to improve the uniformity and stability of device for large-area display. The saturation electron mobility of 8.05 cm 2 /V s and the V th uniformity of 0.72 V are realized on the a-IGZO-based TFT device with CL-ES structure. In the negative bias temperature illumination stress and positive bias thermal stress reliability testing under a ± 30 V bias for 3600 s, the measured V th shift of CL-ES-structured device significantly decreased to - 0.51 and + 1.94 V, which are much lower than that of BCE-structured device (- 3.88 V, + 5.58 V). The electrical performance of the a-IGZO-based TFT device with CL-ES structure implies that the economic transfer from a silicon-based TFT process to the metal oxide semiconductor-based process for LCD fabrication is highly feasible.

A comprehensive model on field-effect pnpn devices (Z2-FET)

NASA Astrophysics Data System (ADS)

Taur, Yuan; Lacord, Joris; Parihar, Mukta Singh; Wan, Jing; Martinie, Sebastien; Lee, Kyunghwa; Bawedin, Maryline; Barbe, Jean-Charles; Cristoloveanu, Sorin

2017-08-01

A comprehensive model for field-effect pnpn devices (Z2-FET) is presented. It is based on three current continuity equations coupled to two MOS equations. The model reproduces the characteristic S-shaped I-V curve when the device is driven by a current source. The negative resistance region at intermediate currents occurs as the center junction undergoes a steep transition from reverse to forward bias. Also playing a vital role are the mix and match of the minority carrier diffusion current and the generation recombination current. Physical insights to the key mechanisms at work are gained by regional approximations of the model, from which analytical expressions for the maximum and minimum voltages at the switching points are derived. From 1981 to 2001, he was with the Silicon Technology Department of IBM Thomas J. Watson Research Center, Yorktown Heights, New York, where he was Manager of Exploratory Devices and Processes. Areas in which he has worked and published include latchup-free 1-um CMOS, self-aligned TiSi2, 0.5-um CMOS and BiCMOS, shallow trench isolation, 0.25-um CMOS with n+/p + poly gates, SOI, low-temperature CMOS, and 0.1-um CMOS. Since October 2001, he has been a professor in the Department of Electrical and Computer Engineering, University of California, San Diego. Dr. Yuan Taur was elected a Fellow of the IEEE in 1998. He has served as Editor-in-Chief of the IEEE Electron Device Letters from 1999 to 2011. He authored or co-authored over 200 technical papers and holds 14 U.S. patents. He co-authored a book, ;Fundamentals of Modern VLSI Devices,; published by Cambridge University Press in 1998. The 2nd edition was published in 2009. Dr. Yuan Taur received IEEE Electron Devices Society's J. J. Ebers Award in 2012 ;for contributions to the advancement of several generations of CMOS process technologies.;

CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

PubMed

Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

2018-04-01

With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Energy efficient hybrid computing systems using spin devices

NASA Astrophysics Data System (ADS)

Sharad, Mrigank

Emerging spin-devices like magnetic tunnel junctions (MTJ's), spin-valves and domain wall magnets (DWM) have opened new avenues for spin-based logic design. This work explored potential computing applications which can exploit such devices for higher energy-efficiency and performance. The proposed applications involve hybrid design schemes, where charge-based devices supplement the spin-devices, to gain large benefits at the system level. As an example, lateral spin valves (LSV) involve switching of nanomagnets using spin-polarized current injection through a metallic channel such as Cu. Such spin-torque based devices possess several interesting properties that can be exploited for ultra-low power computation. Analog characteristic of spin current facilitate non-Boolean computation like majority evaluation that can be used to model a neuron. The magneto-metallic neurons can operate at ultra-low terminal voltage of ˜20mV, thereby resulting in small computation power. Moreover, since nano-magnets inherently act as memory elements, these devices can facilitate integration of logic and memory in interesting ways. The spin based neurons can be integrated with CMOS and other emerging devices leading to different classes of neuromorphic/non-Von-Neumann architectures. The spin-based designs involve `mixed-mode' processing and hence can provide very compact and ultra-low energy solutions for complex computation blocks, both digital as well as analog. Such low-power, hybrid designs can be suitable for various data processing applications like cognitive computing, associative memory, and currentmode on-chip global interconnects. Simulation results for these applications based on device-circuit co-simulation framework predict more than ˜100x improvement in computation energy as compared to state of the art CMOS design, for optimal spin-device parameters.

Real-time DNA Amplification and Detection System Based on a CMOS Image Sensor.

PubMed

Wang, Tiantian; Devadhasan, Jasmine Pramila; Lee, Do Young; Kim, Sanghyo

2016-01-01

In the present study, we developed a polypropylene well-integrated complementary metal oxide semiconductor (CMOS) platform to perform the loop mediated isothermal amplification (LAMP) technique for real-time DNA amplification and detection simultaneously. An amplification-coupled detection system directly measures the photon number changes based on the generation of magnesium pyrophosphate and color changes. The photon number decreases during the amplification process. The CMOS image sensor observes the photons and converts into digital units with the aid of an analog-to-digital converter (ADC). In addition, UV-spectral studies, optical color intensity detection, pH analysis, and electrophoresis detection were carried out to prove the efficiency of the CMOS sensor based the LAMP system. Moreover, Clostridium perfringens was utilized as proof-of-concept detection for the new system. We anticipate that this CMOS image sensor-based LAMP method will enable the creation of cost-effective, label-free, optical, real-time and portable molecular diagnostic devices.

Area efficient layout design of CMOS circuit for high-density ICs

NASA Astrophysics Data System (ADS)

Mishra, Vimal Kumar; Chauhan, R. K.

2018-01-01

Efficient layouts have been an active area of research to accommodate the greater number of devices fabricated on a given chip area. In this work a new layout of CMOS circuit is proposed, with an aim to improve its electrical performance and reduce the chip area consumed. The study shows that the design of CMOS circuit and SRAM cells comprising tapered body reduced source fully depleted silicon on insulator (TBRS FD-SOI)-based n- and p-type MOS devices. The proposed TBRS FD-SOI n- and p-MOSFET exhibits lower sub-threshold slope and higher Ion to Ioff ratio when compared with FD-SOI MOSFET and FinFET technology. Other parameters like power dissipation, delay time and signal-to-noise margin of CMOS inverter circuits show improvement when compared with available inverter designs. The above device design is used in 6-T SRAM cell so as to see the effect of proposed layout on high density integrated circuits (ICs). The SNM obtained from the proposed SRAM cell is 565 mV which is much better than any other SRAM cell designed at 50 nm gate length MOS device. The Sentaurus TCAD device simulator is used to design the proposed MOS structure.

Critical issues for the application of integrated MEMS/CMOS technologies to inertial measurement units

DOE Office of Scientific and Technical Information (OSTI.GOV)

Smith, J.H.; Ellis, J.R.; Montague, S.

1997-03-01

One of the principal applications of monolithically integrated micromechanical/microelectronic systems has been accelerometers for automotive applications. As integrated MEMS/CMOS technologies such as those developed by U.C. Berkeley, Analog Devices, and Sandia National Laboratories mature, additional systems for more sensitive inertial measurements will enter the commercial marketplace. In this paper, the authors will examine key technology design rules which impact the performance and cost of inertial measurement devices manufactured in integrated MEMS/CMOS technologies. These design parameters include: (1) minimum MEMS feature size, (2) minimum CMOS feature size, (3) maximum MEMS linear dimension, (4) number of mechanical MEMS layers, (5) MEMS/CMOS spacing.more » In particular, the embedded approach to integration developed at Sandia will be examined in the context of these technology features. Presently, this technology offers MEMS feature sizes as small as 1 {micro}m, CMOS critical dimensions of 1.25 {micro}m, MEMS linear dimensions of 1,000 {micro}m, a single mechanical level of polysilicon, and a 100 {micro}m space between MEMS and CMOS. This is applicable to modern precision guided munitions.« less

Verification of a SEU model for advanced 1-micron CMOS structures using heavy ions

NASA Technical Reports Server (NTRS)

Cable, J. S.; Carter, J. R.; Witteles, A. A.

1986-01-01

Modeling and test results are reported for 1 micron CMOS circuits. Analytical predictions are correlated with experimental data, and sensitivities to process and design variations are discussed. Unique features involved in predicting the SEU performance of these devices are described. The results show that the critical charge for upset exhibits a strong dependence on pulse width for very fast devices, and upset predictions must factor in the pulse shape. Acceptable SEU error rates can be achieved for a 1 micron bulk CMOS process. A thin retrograde well provides complete SEU immunity for N channel hits at normal incidence angle. Source interconnect resistance can be important parameter in determining upset rates, and Cf-252 testing can be a valuable tool for cost-effective SEU testing.

Bias field tailored plasmonic nano-electrode for high-power terahertz photonic devices

PubMed Central

Moon, Kiwon; Lee, Il-Min; Shin, Jun-Hwan; Lee, Eui Su; Kim, Namje; Lee, Won-Hui; Ko, Hyunsung; Han, Sang-Pil; Park, Kyung Hyun

2015-01-01

Photoconductive antennas with nano-structured electrodes and which show significantly improved performances have been proposed to satisfy the demand for compact and efficient terahertz (THz) sources. Plasmonic field enhancement was previously considered the dominant mechanism accounting for the improvements in the underlying physics. However, we discovered that the role of plasmonic field enhancement is limited and near-field distribution of bias field should be considered as well. In this paper, we clearly show that the locally enhanced bias field due to the size effect is much more important than the plasmonic enhanced absorption in the nano-structured electrodes for the THz emitters. Consequently, an improved nano-electrode design is presented by tailoring bias field distribution and plasmonic enhancement. Our findings will pave the way for new perspectives in the design and analysis of plasmonic nano-structures for more efficient THz photonic devices. PMID:26347288

High Performance Graphene Nano-ribbon Thermoelectric Devices by Incorporation and Dimensional Tuning of Nanopores

PubMed Central

Sharafat Hossain, Md; Al-Dirini, Feras; Hossain, Faruque M.; Skafidas, Efstratios

2015-01-01

Thermoelectric properties of Graphene nano-ribbons (GNRs) with nanopores (NPs) are explored for a range of pore dimensions in order to achieve a high performance two-dimensional nano-scale thermoelectric device. We reduce thermal conductivity of GNRs by introducing pores in them in order to enhance their thermoelectric performance. The electrical properties (Seebeck coefficient and conductivity) of the device usually degrade with pore inclusion; however, we tune the pore to its optimal dimension in order to minimize this degradation, enhancing the overall thermoelectric performance (high ZT value) of our device. We observe that the side channel width plays an important role to achieve optimal performance while the effect of pore length is less pronounced. This result is consistent with the fact that electronic conduction in GNRs is dominated along its edges. Ballistic transport regime is assumed and a semi-empirical method using Huckel basis set is used to obtain the electrical properties, while the phononic system is characterized by Tersoff empirical potential model. The proposed device structure has potential applications as a nanoscale local cooler and as a thermoelectric power generator. PMID:26083450

High Performance Graphene Nano-ribbon Thermoelectric Devices by Incorporation and Dimensional Tuning of Nanopores.

PubMed

Hossain, Md Sharafat; Al-Dirini, Feras; Hossain, Faruque M; Skafidas, Efstratios

2015-06-17

Thermoelectric properties of Graphene nano-ribbons (GNRs) with nanopores (NPs) are explored for a range of pore dimensions in order to achieve a high performance two-dimensional nano-scale thermoelectric device. We reduce thermal conductivity of GNRs by introducing pores in them in order to enhance their thermoelectric performance. The electrical properties (Seebeck coefficient and conductivity) of the device usually degrade with pore inclusion; however, we tune the pore to its optimal dimension in order to minimize this degradation, enhancing the overall thermoelectric performance (high ZT value) of our device. We observe that the side channel width plays an important role to achieve optimal performance while the effect of pore length is less pronounced. This result is consistent with the fact that electronic conduction in GNRs is dominated along its edges. Ballistic transport regime is assumed and a semi-empirical method using Huckel basis set is used to obtain the electrical properties, while the phononic system is characterized by Tersoff empirical potential model. The proposed device structure has potential applications as a nanoscale local cooler and as a thermoelectric power generator.

Low reflection and field localization over surface plasmon device with subwavelength patterned aluminum film

NASA Astrophysics Data System (ADS)

Yuan, Ying; Peng, Sha; Long, Huabao; Liu, Runhan; Wei, Dong; Zhang, Xinyu; Wang, Haiwei; Xie, Changsheng

2018-02-01

In this paper, we propose a new device composed of patterned sub-wavelength arrays to investigate surface plasmons (SPs) over sub-wavelength metal nano-structures. The device consists of silicon substrate and sub-wavelength patterns fabricated on a layer of aluminum film with nanometer thickness. Each sub-wavelength pattern formed in aluminum film is composed of a basic nano-square and twelve triangles for shaping single nano-pattern, which are uniformly distributed on the four sides of each square. Reflectance spectra and electric field distribution in infrared region are simulated. Numerical simulation results demonstrate that the device can efficiently lower its reflectance in infrared spectrum, and the response frequency can be controlled by only changing the device parameters such as square side length and then triangle vertex angle. Besides, the simulated electric field distribution of the device shows obviously field localization effect at the edges of aluminum film nano-structure. The electric filed around the tips of aluminum triangles is localized into sub-wavelength scale, so as to be beyond the common diffraction limitation. Our work will help to reveal the interesting properties of SPs device, and also bring new prospect of photonic device.

Detecting Nano-Scale Vibrations in Rotating Devices by Using Advanced Computational Methods

PubMed Central

del Toro, Raúl M.; Haber, Rodolfo E.; Schmittdiel, Michael C.

2010-01-01

This paper presents a computational method for detecting vibrations related to eccentricity in ultra precision rotation devices used for nano-scale manufacturing. The vibration is indirectly measured via a frequency domain analysis of the signal from a piezoelectric sensor attached to the stationary component of the rotating device. The algorithm searches for particular harmonic sequences associated with the eccentricity of the device rotation axis. The detected sequence is quantified and serves as input to a regression model that estimates the eccentricity. A case study presents the application of the computational algorithm during precision manufacturing processes. PMID:22399918

Upper-Bound Estimates Of SEU in CMOS

NASA Technical Reports Server (NTRS)

Edmonds, Larry D.

1990-01-01

Theory of single-event upsets (SEU) (changes in logic state caused by energetic charged subatomic particles) in complementary metal oxide/semiconductor (CMOS) logic devices extended to provide upper-bound estimates of rates of SEU when limited experimental information available and configuration and dimensions of SEU-sensitive regions of devices unknown. Based partly on chord-length-distribution method.

A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

PubMed

Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

2012-08-01

We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

CMOS image sensor for detection of interferon gamma protein interaction as a point-of-care approach.

PubMed

Marimuthu, Mohana; Kandasamy, Karthikeyan; Ahn, Chang Geun; Sung, Gun Yong; Kim, Min-Gon; Kim, Sanghyo

2011-09-01

Complementary metal oxide semiconductor (CMOS)-based image sensors have received increased attention owing to the possibility of incorporating them into portable diagnostic devices. The present research examined the efficiency and sensitivity of a CMOS image sensor for the detection of antigen-antibody interactions involving interferon gamma protein without the aid of expensive instruments. The highest detection sensitivity of about 1 fg/ml primary antibody was achieved simply by a transmission mechanism. When photons are prevented from hitting the sensor surface, a reduction in digital output occurs in which the number of photons hitting the sensor surface is approximately proportional to the digital number. Nanoscale variation in substrate thickness after protein binding can be detected with high sensitivity by the CMOS image sensor. Therefore, this technique can be easily applied to smartphones or any clinical diagnostic devices for the detection of several biological entities, with high impact on the development of point-of-care applications.

Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

NASA Astrophysics Data System (ADS)

Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

2017-12-01

With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

NASA Astrophysics Data System (ADS)

Es-Sakhi, Azzedin D.

Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias †

PubMed Central

Clarke, Andrew S.; Ivory, James; Holland, Andrew D.

2018-01-01

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths. PMID:29301379

Technology modules from micro- and nano-electronics for the life sciences.

PubMed

Birkholz, M; Mai, A; Wenger, C; Meliani, C; Scholz, R

2016-05-01

The capabilities of modern semiconductor manufacturing offer remarkable possibilities to be applied in life science research as well as for its commercialization. In this review, the technology modules available in micro- and nano-electronics are exemplarily presented for the case of 250 and 130 nm technology nodes. Preparation procedures and the different transistor types as available in complementary metal-oxide-silicon devices (CMOS) and BipolarCMOS (BiCMOS) technologies are introduced as key elements of comprehensive chip architectures. Techniques for circuit design and the elements of completely integrated bioelectronics systems are outlined. The possibility for life scientists to make use of these technology modules for their research and development projects via so-called multi-project wafer services is emphasized. Various examples from diverse fields such as (1) immobilization of biomolecules and cells on semiconductor surfaces, (2) biosensors operating by different principles such as affinity viscosimetry, impedance spectroscopy, and dielectrophoresis, (3) complete systems for human body implants and monitors for bioreactors, and (4) the combination of microelectronics with microfluidics either by chip-in-polymer integration as well as Si-based microfluidics are demonstrated from joint developments with partners from biotechnology and medicine. WIREs Nanomed Nanobiotechnol 2016, 8:355-377. doi: 10.1002/wnan.1367 For further resources related to this article, please visit the WIREs website. © 2015 Wiley Periodicals, Inc.

CMOS image sensor-based immunodetection by refractive-index change.

PubMed

Devadhasan, Jasmine P; Kim, Sanghyo

2012-01-01

A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

Neuromorphic Computing, Architectures, Models, and Applications. A Beyond-CMOS Approach to Future Computing, June 29-July 1, 2016, Oak Ridge, TN

DOE Office of Scientific and Technical Information (OSTI.GOV)

Potok, Thomas; Schuman, Catherine; Patton, Robert

The White House and Department of Energy have been instrumental in driving the development of a neuromorphic computing program to help the United States continue its lead in basic research into (1) Beyond Exascale—high performance computing beyond Moore’s Law and von Neumann architectures, (2) Scientific Discovery—new paradigms for understanding increasingly large and complex scientific data, and (3) Emerging Architectures—assessing the potential of neuromorphic and quantum architectures. Neuromorphic computing spans a broad range of scientific disciplines from materials science to devices, to computer science, to neuroscience, all of which are required to solve the neuromorphic computing grand challenge. In our workshopmore » we focus on the computer science aspects, specifically from a neuromorphic device through an application. Neuromorphic devices present a very different paradigm to the computer science community from traditional von Neumann architectures, which raises six major questions about building a neuromorphic application from the device level. We used these fundamental questions to organize the workshop program and to direct the workshop panels and discussions. From the white papers, presentations, panels, and discussions, there emerged several recommendations on how to proceed.« less

A Grand Challenge for CMOS Scaling: Alternate Gate Dielectrics

NASA Astrophysics Data System (ADS)

Wallace, Robert M.

2001-03-01

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.13 um complementary metal oxide semiconductor (CMOS) technology. The prospect of replacing SiO2 is a formidable task because the alternate gate dielectric must provide many properties that are, at a minimum, comparable to those of SiO2 yet with a much higher permittivity. A systematic examination of the required performance of gate dielectrics suggests that the key properties to consider in the selection an alternative gate dielectric candidate are (a) permittivity, band gap and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. We will review the performance requirements for materials associated with CMOS scaling, the challenges associated with these requirements, and the state-of-the-art in current research for alternate gate dielectrics. The requirements for process integration compatibility are remarkably demanding, and any serious candidates will emerge only through continued, intensive investigation.

Analysis of Preoperative Airway Examination with the CMOS Video Rhino-laryngoscope.

PubMed

Tsukamoto, Masanori; Hitosugi, Takashi; Yokoyama, Takeshi

2017-05-01

Endoscopy is one of the most useful clinical techniques in difficult airway management Comparing with the fibroptic endoscope, this compact device is easy to operate and can provide the clear image. In this study, we investigated its usefulness in the preoperative examination of endoscopy. Patients undergoing oral maxillofacial surgery were enrolled in this study. We performed preoperative airway examination by electronic endoscope (The CMOS video rhino-laryngoscope, KARL STORZ Endoscopy Japan, Tokyo). The system is composed of a videoendoscope, a compact video processor and a video recorder. In addition, the endoscope has a small color charge coupled device (CMOS) chip built into the tip of the endoscope. The outer diameter of the tip of this scope is 3.7 mm. In this study, electronic endoscope was used for preoperative airway examination in 7 patients. The preoperative airway examination with electronic endoscope was performed successfully in all the patients except one patient The patient had the symptoms such as nausea and vomiting at the examination. We could perform preoperative airway examination with excellent visualization and convenient recording of video sequence images with the CMOS video rhino-laryngoscope. It might be a especially useful device for the patients of difficult airways.

CMOS-Compatible Room-Temperature Rectifier Toward Terahertz Radiation Detection

NASA Astrophysics Data System (ADS)

Varlamava, Volha; De Amicis, Giovanni; Del Monte, Andrea; Perticaroli, Stefano; Rao, Rosario; Palma, Fabrizio

2016-08-01

In this paper, we present a new rectifying device, compatible with the technology of CMOS image sensors, suitable for implementing a direct-conversion detector operating at room temperature for operation at up to terahertz frequencies. The rectifying device can be obtained by introducing some simple modifications of the charge-storage well in conventional CMOS integrated circuits, making the proposed solution easy to integrate with the existing imaging systems. The rectifying device is combined with the different elements of the detector, composed of a 3D high-performance antenna and a charge-storage well. In particular, its position just below the edge of the 3D antenna takes maximum advantage of the high electric field concentrated by the antenna itself. In addition, the proposed structure ensures the integrity of the charge-storage well of the detector. In the structure, it is not necessary to use very scaled and costly technological nodes, since the CMOS transistor only provides the necessary integrated readout electronics. On-wafer measurements of RF characteristics of the designed junction are reported and discussed. The overall performances of the entire detector in terms of noise equivalent power (NEP) are evaluated by combining low-frequency measurements of the rectifier with numerical simulations of the 3D antenna and the semiconductor structure at 1 THz, allowing prediction of the achievable NEP.

Fabrication of the planar angular rotator using the CMOS process

NASA Astrophysics Data System (ADS)

Dai, Ching-Liang; Chang, Chien-Liu; Chen, Hung-Lin; Chang, Pei-Zen

2002-05-01

In this investigation we propose a novel planar angular rotator fabricated by the conventional complementary metal-oxide semiconductor (CMOS) process. Following the 0.6 μm single poly triple metal (SPTM) CMOS process, the device is completed by a simple maskless, post-process etching step. The rotor of the planar angular rotator rotates around its geometric center with electrostatic actuation. The proposed design adopts an intelligent mechanism including the slider-crank system to permit simultaneous motion. The CMOS planar angular rotator could be driven with driving voltages of around 40 V. The design proposed here has a shorter response time and longer life, without problems of friction and wear, compared to the more common planar angular micromotor.

Spoked-ring microcavities: enabling seamless integration of nanophotonics in unmodified advanced CMOS microelectronics chips

NASA Astrophysics Data System (ADS)

Wade, Mark T.; Shainline, Jeffrey M.; Orcutt, Jason S.; Ram, Rajeev J.; Stojanovic, Vladimir; Popovic, Milos A.

2014-03-01

We present the spoked-ring microcavity, a nanophotonic building block enabling energy-efficient, active photonics in unmodified, advanced CMOS microelectronics processes. The cavity is realized in the IBM 45nm SOI CMOS process - the same process used to make many commercially available microprocessors including the IBM Power7 and Sony Playstation 3 processors. In advanced SOI CMOS processes, no partial etch steps and no vertical junctions are available, which limits the types of optical cavities that can be used for active nanophotonics. To enable efficient active devices with no process modifications, we designed a novel spoked-ring microcavity which is fully compatible with the constraints of the process. As a modulator, the device leverages the sub-100nm lithography resolution of the process to create radially extending p-n junctions, providing high optical fill factor depletion-mode modulation and thereby eliminating the need for a vertical junction. The device is made entirely in the transistor active layer, low-loss crystalline silicon, which eliminates the need for a partial etch commonly used to create ridge cavities. In this work, we present the full optical and electrical design of the cavity including rigorous mode solver and FDTD simulations to design the Qlimiting electrical contacts and the coupling/excitation. We address the layout of active photonics within the mask set of a standard advanced CMOS process and show that high-performance photonic devices can be seamlessly monolithically integrated alongside electronics on the same chip. The present designs enable monolithically integrated optoelectronic transceivers on a single advanced CMOS chip, without requiring any process changes, enabling the penetration of photonics into the microprocessor.

VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

NASA Astrophysics Data System (ADS)

Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

2014-10-01

This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

In-situ comprehensive calibration of a tri-port nano-electro-mechanical device.

PubMed

Collin, E; Defoort, M; Lulla, K; Moutonet, T; Heron, J-S; Bourgeois, O; Bunkov, Yu M; Godfrin, H

2012-04-01

We report on experiments performed in vacuum and at cryogenic temperatures on a tri-port nano-electro-mechanical (NEMS) device. One port is a very nonlinear capacitive actuation, while the two others implement the magnetomotive scheme with a linear input force port and a (quasi-linear) output velocity port. We present an experimental method enabling a full characterization of the nanomechanical device harmonic response: the nonlinear capacitance function C(x) is derived, and the normal parameters k and m (spring constant and mass) of the mode under study are measured through a careful definition of the motion (in meters) and of the applied forces (in Newtons). These results are obtained with a series of purely electric measurements performed without disconnecting/reconnecting the device, and rely only on known dc properties of the circuit, making use of a thermometric property of the oscillator itself: we use the Young modulus of the coating metal as a thermometer, and the resistivity for Joule heating. The setup requires only three connecting lines without any particular matching, enabling the preservation of a high impedance NEMS environment even at MHz frequencies. The experimental data are fit to a detailed electrical and thermal model of the NEMS device, demonstrating a complete understanding of its dynamics. These methods are quite general and can be adapted (as a whole, or in parts) to a large variety of electromechanical devices. © 2012 American Institute of Physics

CMOS-APS Detectors for Solar Physics: Lessons Learned during the SWAP Preflight Calibration

NASA Astrophysics Data System (ADS)

de Groof, A.; Berghmans, D.; Nicula, B.; Halain, J.-P.; Defise, J.-M.; Thibert, T.; Schühle, U.

2008-05-01

CMOS-APS imaging detectors open new opportunities for remote sensing in solar physics beyond what classical CCDs can provide, offering far less power consumption, simpler electronics, better radiation hardness, and the possibility of avoiding a mechanical shutter. The SWAP telescope onboard the PROBA2 technology demonstration satellite of the European Space Agency will be the first actual implementation of a CMOS-APS detector for solar physics in orbit. One of the goals of the SWAP project is precisely to acquire experience with the CMOS-APS technology in a real-live space science context. Such a precursor mission is essential in the preparation of missions such as Solar Orbiter where the extra CMOS-APS functionalities will be hard requirements. The current paper concentrates on specific CMOS-APS issues that were identified during the SWAP preflight calibration measurements. We will discuss the different readout possibilities that the CMOS-APS detector of SWAP provides and their associated pros and cons. In particular we describe the “image lag” effect, which results in a contamination of each image with a remnant of the previous image. We have characterised this effect for the specific SWAP implementation and we conclude with a strategy on how to successfully circumvent the problem and actually take benefit of it for solar monitoring.

Opportunities of CMOS-MEMS integration through LSI foundry and open facility

NASA Astrophysics Data System (ADS)

Mita, Yoshio; Lebrasseur, Eric; Okamoto, Yuki; Marty, Frédéfic; Setoguchi, Ryota; Yamada, Kentaro; Mori, Isao; Morishita, Satoshi; Imai, Yoshiaki; Hosaka, Kota; Hirakawa, Atsushi; Inoue, Shu; Kubota, Masanori; Denoual, Matthieu

2017-06-01

Since the 2000s, several countries have established micro- and nanofabrication platforms for the research and education community as national projects. By combining such platforms with VLSI multichip foundry services, various integrated devices, referred to as “CMOS-MEMS”, can be realized without constructing an entire cleanroom. In this paper, we summarize MEMS-last postprocess schemes for CMOS devices on a bulk silicon wafer as well as on a silicon-on-insulator (SOI) wafer using an open-access cleanroom of the Nanotechnology Platform of MEXT Japan. The integration devices presented in this article are free-standing structures and postprocess isolated LSI devices. Postprocess issues are identified with their solutions, such as the reactive ion etching (RIE) lag for dry release and the impact of the deep RIE (DRIE) postprocess on transistor characteristics. Integration with nonsilicon materials is proposed as one of the future directions.

A CMOS Compatible, Forming Free TaO x ReRAM

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lohn, A. J.; Stevens, J. E.; Mickel, P. R.

2013-08-31

Resistive random access memory (ReRAM) has become a promising candidate for next-generation high-performance non-volatile memory that operates by electrically tuning resistance states via modulating vacancy concentrations. Here, we demonstrate a wafer-scale process for resistive switching in tantalum oxide that is completely CMOS compatible. The resulting devices are forming-free and with greater than 1x10 5 cycle endurance.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

PubMed

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

CMOS technology: a critical enabler for free-form electronics-based killer applications

NASA Astrophysics Data System (ADS)

Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

2016-05-01

Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

Thermo-activated nano-material for use in optical devices

NASA Astrophysics Data System (ADS)

Mias, Solon; Sudor, Jan; Camon, Henri

2007-05-01

In this paper we describe the use of thermo-activated PNIPAM nano-material in optical switching devices. In other publications, the PNIPAM is used either as a carrier for crystalline colloidal array self-assemblies or as micro-particles that serve as pigment bags. In this publication we use a simpler-to-fabricate pure PNIPAM solution in a semi-dilute regime. The PNIPAM devices produced are transparent at temperatures below a critical temperature of 32°C and become diffusing above this temperature. We show that at 632nm the transmission through the devices is about 75% in the transparent state while the additional attenuation achieved in the diffusing state is of the order of 38 dB. The experimental fall and rise times obtained are large (about 300ms and 5s respectively) due to the non-optimised thermal addressing scheme. In addition, spectral measurements taken in the infrared spectrum (700-1000nm) demonstrate that the cell response is flat over a large portion of the infrared spectrum in both the transparent and the diffusing states.

A new CMOS SiGeC avalanche photo-diode pixel for IR sensing

NASA Astrophysics Data System (ADS)

Augusto, Carlos; Forester, Lynn; Diniz, Pedro C.

2009-05-01

Near-infra-red sensing with silicon is limited by the bandgap of silicon, corresponding to a maximum wavelength of absorption of 1.1 μm. A new type of CMOS sensor is presented, which uses a SiGeC epitaxial film in conjunction with novel device architecture to extend absorption into the infra-red. The SiGeC film composition and thickness determine the spectrum of absorption; in particular for SiGeC superlattices, the layer ordering to create pseudo direct bandgaps is the critical parameter. In this new device architecture, the p-type SiGeC film is grown on an active region surrounded by STI, linked to the S/D region of an adjacent NMOS, under the STI by a floating N-Well. On a n-type active, a P-I-N device is formed, and on a p-type active, a P-I-P device is formed, each sensing different regions of the spectrum. The SiGeC films can be biased for avalanche operation, as the required vertical electric field is confined to the region near the heterojunction interface, thereby not affecting the gate oxide of the adjacent NMOS. With suitable heterojunction and doping profiles, the avalanche region can also be bandgap engineered, allowing for avalanche breakdown voltages that are compatible with CMOS devices.

Near-field nano-Raman imaging of Si device structures

NASA Astrophysics Data System (ADS)

Atesang, Jacob; Geer, Robert

2005-05-01

Apertureless-based, near-field Raman imaging holds the potential for nanoscale stress metrology in emerging Si devices. Preliminary application of near-field Raman imaging on Si device structures has demonstrated the potential for stress measurements. However, detailed investigations have not been published regarding the effect of tip radius on observed near-field enhancement. Such investigations are important to understand the fundamental limits regarding the signal-to-noise ratio of the measurement and the spatial resolution that can potentially be achieved before wide application to semiconductor metrology can be considered. Investigations are presented into near-field enhancement of Raman scattering from Si device structures using a modified near-field optical microscope (NSOM). The nano-Raman system utilizes an off-axis (45°) backscattering NSOM geometry with free-space collection optics. The spectroscopic configuration utilizes a single-bounce spectrometer incorporating a holographic notch filter assembly utilized as a secondary beam-splitter for an apertureless backscattering collection geometry. Near-field enhancement is observed for both Al- and Ag-coated probes. An inverse square power-law relationship is observed between near-field enhancement factor and tip radius.

Method for implementation of back-illuminated CMOS or CCD imagers

NASA Technical Reports Server (NTRS)

Pain, Bedabrata (Inventor)

2008-01-01

A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

A reversible bipolar WORM device based on AlOxNy thin film with Al nano phase embedded

NASA Astrophysics Data System (ADS)

Zhu, W.; Li, J.; Zhang, L.; Hu, X. C.

2017-03-01

An Al-rich AlOxNy thin film based reversible Write-Once-Read-Many-Times (WORM) memory device with MIS structure could transit from high resistance state (HRS, ∼1011 Ω) to low resistance state (LRS, ∼105 Ω) by sweeping voltage up to ∼20 V. The first switching could be recorded as writing process for WORM device which may relate to conductive path are formed through the thin film. The conductive path should be formed by both Al nano phase and oxygen vacancies. Among of them, Al nano phases are not easy to move, but oxygen vacancies could migrate under high E-field or at high temperature environment. Such conductive path is not sensitive to charging effect after it formed, but it could be broken by heating effect, which may relate to the migration of excess Al ions and oxygen vacancies at high temperature. After baking LRS (ON state) WORM device at 200 °C for 2 min, the conductivity will decrease to HRS which indicates conductive path is broken and device back to HRS (OFF state) again. This phenomenon could be recorded as recovery process. Both writing and recovery process related to migration of oxygen vacancies and could be repeated over 10 times in this study. It also indicates that there is no permanent breakdown occurred in MIS structured WORM device operation. We suggest that this conductive path only can be dissolved by a temperature sensitive electro-chemical action. This WORM device could maintain at LRS over 105 s with on-off ratio over 4 orders.

Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

NASA Astrophysics Data System (ADS)

Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

2010-10-01

Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

Cmos spdt switch for wlan applications

NASA Astrophysics Data System (ADS)

Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

2015-04-01

WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

The fabrication of a programmable via using phase-change material in CMOS-compatible technology.

PubMed

Chen, Kuan-Neng; Krusin-Elbaum, Lia

2010-04-02

We demonstrate an energy-efficient programmable via concept using indirectly heated phase-change material. This via structure has maximum phase-change volume to achieve a minimum on resistance for high performance logic applications. Process development and material investigations for this device structure are reported. The device concept is successfully demonstrated in a standard CMOS-compatible technology capable of multiple cycles between on/off states for reconfigurable applications.

CMOS image sensors as an efficient platform for glucose monitoring.

PubMed

Devadhasan, Jasmine Pramila; Kim, Sanghyo; Choi, Cheol Soo

2013-10-07

Complementary metal oxide semiconductor (CMOS) image sensors have been used previously in the analysis of biological samples. In the present study, a CMOS image sensor was used to monitor the concentration of oxidized mouse plasma glucose (86-322 mg dL(-1)) based on photon count variation. Measurement of the concentration of oxidized glucose was dependent on changes in color intensity; color intensity increased with increasing glucose concentration. The high color density of glucose highly prevented photons from passing through the polydimethylsiloxane (PDMS) chip, which suggests that the photon count was altered by color intensity. Photons were detected by a photodiode in the CMOS image sensor and converted to digital numbers by an analog to digital converter (ADC). Additionally, UV-spectral analysis and time-dependent photon analysis proved the efficiency of the detection system. This simple, effective, and consistent method for glucose measurement shows that CMOS image sensors are efficient devices for monitoring glucose in point-of-care applications.

Design and analysis of high gain and low noise figure CMOS low noise amplifier for Q-band nano-sensor application

NASA Astrophysics Data System (ADS)

Suganthi, K.; Malarvizhi, S.

2018-03-01

A high gain, low power, low Noise figure (NF) and wide band of milli-meter Wave (mmW) circuits design at 50 GHz are used for Radio Frequency (RF) front end. The fundamental necessity of a receiver front-end includes perfect output and input impedance matching and port-to-port isolation with high gain and low noise over the entire band of interest. In this paper, a design of Cascade-Cascode CMOS LNA circuit at 50 GHz for Q-band application is proposed. The design of Low noise amplifier at 50 GHz using Agilent ADS tool with microstrip lines which provides simplicity in fabrication and less chip area. The low off-leakage current Ioff can be maintained with high K-dielectrics CMOS structure. Nano-scale electronics can be achieved with increased robustness. The design has overall gain of 11.091 dB and noise figure of 2.673 dB for the Q-band of 48.3 GHz to 51.3 GHz. Impedance matching is done by T matching network and the obtained input and output reflection coefficients are S11 = <-10 dB and S22 = <-10 dB. Compared to Silicon (Si) material, Wide Band Gap semiconductor materials used attains higher junction temperatures which is well matched to ceramics used in packaging technology, the protection and reliability also can be achieved with the electronic packaging. The reverse transmission coefficient S21 is less than -21 dB has shown that LNA has better isolation between input and output, Stability factor greater than 1 and Power is also optimized in this design. Layout is designed, power gain of 4.6 dB is achieved and area is optimized which is nearly equal to 502 740 μm2. The observed results show that the proposed Cascade-Cascode LNA design can find its suitability in future milli-meter Wave Radar application.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

PubMed

Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

2012-05-07

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Improved Space Object Observation Techniques Using CMOS Detectors

NASA Astrophysics Data System (ADS)

Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

2013-08-01

CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, James; Gunawan, Ferry; Dosluoglu, Taner; Tower, John; McCaffrey, Niel

2002-08-01

High performance CMOS pixels are introduced; and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantagesof these options for scientific CMOS pixels are examined.Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Scientific CMOS Pixels

NASA Astrophysics Data System (ADS)

Janesick, J.; Gunawan, F.; Dosluoglu, T.; Tower, J.; McCaffrey, N.

High performance CMOS pixels are introduced and their development is discussed. 3T (3-transistor) photodiode, 5T pinned diode, 6T photogate and 6T photogate back illuminated CMOS pixels are examined in detail, and the latter three are considered as scientific pixels. The advantages and disadvantages of these options for scientific CMOS pixels are examined. Pixel characterization, which is used to gain a better understanding of CMOS pixels themselves, is also discussed.

Integrated Metamaterials and Nanophotonics in CMOS-Compatible Materials

NASA Astrophysics Data System (ADS)

Reshef, Orad

This thesis explores scalable nanophotonic devices in integrated, CMOS-compatible platforms. Our investigation focuses on two main projects: studying the material properties of integrated titanium dioxide (TiO2), and studying integrated metamaterials in silicon-on-insulator (SOI) technologies. We first describe the nanofabrication process for TiO2 photonic integrated circuits. We use this procedure to demonstrate polycrystalline anatase TiO2 ring resonators with high quality factors. We measure the thermo-optic coefficient of TiO2 and determine that it is negative, a unique property among CMOS-compatible dielectric photonic platforms. We also derive a transfer function for ring resonators in the presence of reflections and demonstrate using full-wave simulations that these reflections produce asymmetries in the resonances. For the second half of the dissertation, we design and demonstrate an SOI-based photonic-Dirac-cone metamaterial. Using a prism composed of this metamaterial, we measure its index of refraction and unambiguously determine that it is zero. Next, we take a single channel of this metamaterial to form a waveguide. Using interferometry, we independently confirm that the waveguide in this configuration preserves the dispersion profile of the aggregate medium, with a zero phase advance. We also characterize the waveguide, determining its propagation loss. Finally, we perform simulations to study nonlinear optical phenomena in zero-index media. We find that an isotropic refractive index near zero relaxes certain phase-matching constraints, allowing for more flexible configurations of nonlinear devices with dramatically reduced footprints. The outcomes of this work enable higher quality fabrication of scalable nanophotonic devices for use in nonlinear applications with passive temperature compensation. These devices are CMOS-compatible and can be integrated vertically for compact, device-dense industrial applications. It also provides access to a

Modeling the Charge Transport in Graphene Nano Ribbon Interfaces for Nano Scale Electronic Devices

NASA Astrophysics Data System (ADS)

Kumar, Ravinder; Engles, Derick

2015-05-01

In this research work we have modeled, simulated and compared the electronic charge transport for Metal-Semiconductor-Metal interfaces of Graphene Nano Ribbons (GNR) with different geometries using First-Principle calculations and Non-Equilibrium Green's Function (NEGF) method. We modeled junctions of Armchair GNR strip sandwiched between two Zigzag strips with (Z-A-Z) and Zigzag GNR strip sandwiched between two Armchair strips with (A-Z-A) using semi-empirical Extended Huckle Theory (EHT) within the framework of Non-Equilibrium Green Function (NEGF). I-V characteristics of the interfaces were visualized for various transport parameters. The distinct changes in conductance and I-V curves reported as the Width across layers, Channel length (Central part) was varied at different bias voltages from -1V to 1 V with steps of 0.25 V. From the simulated results we observed that the conductance through A-Z-A graphene junction is in the range of 10-13 Siemens whereas the conductance through Z-A-Z graphene junction is in the range of 10-5 Siemens. These suggested conductance controlled mechanisms for the charge transport in the graphene interfaces with different geometries is important for the design of graphene based nano scale electronic devices like Graphene FETs, Sensors.

CMOS Imager Has Better Cross-Talk and Full-Well Performance

NASA Technical Reports Server (NTRS)

Pain, Bedabrata; Cunningham, Thomas J.

2011-01-01

A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the

Prospects for charge sensitive amplifiers in scaled CMOS

NASA Astrophysics Data System (ADS)

O'Connor, Paul; De Geronimo, Gianluigi

2002-03-01

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

Robust Dehaze Algorithm for Degraded Image of CMOS Image Sensors.

PubMed

Qu, Chen; Bi, Du-Yan; Sui, Ping; Chao, Ai-Nong; Wang, Yun-Fei

2017-09-22

The CMOS (Complementary Metal-Oxide-Semiconductor) is a new type of solid image sensor device widely used in object tracking, object recognition, intelligent navigation fields, and so on. However, images captured by outdoor CMOS sensor devices are usually affected by suspended atmospheric particles (such as haze), causing a reduction in image contrast, color distortion problems, and so on. In view of this, we propose a novel dehazing approach based on a local consistent Markov random field (MRF) framework. The neighboring clique in traditional MRF is extended to the non-neighboring clique, which is defined on local consistent blocks based on two clues, where both the atmospheric light and transmission map satisfy the character of local consistency. In this framework, our model can strengthen the restriction of the whole image while incorporating more sophisticated statistical priors, resulting in more expressive power of modeling, thus, solving inadequate detail recovery effectively and alleviating color distortion. Moreover, the local consistent MRF framework can obtain details while maintaining better results for dehazing, which effectively improves the image quality captured by the CMOS image sensor. Experimental results verified that the method proposed has the combined advantages of detail recovery and color preservation.

Ultra low noise YBa{sub 2}Cu{sub 3}O{sub 7−δ} nano superconducting quantum interference devices implementing nanowires

DOE Office of Scientific and Technical Information (OSTI.GOV)

Arpaia, R.; CNR-SPIN, Dipartimento di Scienze Fisiche, Università degli Studi di Napoli “Federico II,” I-80125 Napoli; Arzeo, M.

2014-02-17

We present results on ultra low noise YBa{sub 2}Cu{sub 3}O{sub 7–δ} (YBCO) nano Superconducting QUantum Interference Devices (nanoSQUIDs). To realize such devices, we implemented high quality YBCO nanowires, working as weak links between two electrodes. We observe critical current modulation as a function of an externally applied magnetic field in the full temperature range below the transition temperature T{sub C}. The white flux noise below 1μΦ{sub 0}/√(Hz) at T=8 K makes our nanoSQUIDs very attractive for the detection of small spin systems.

Regenerative switching CMOS system

DOEpatents

Welch, James D.

1998-01-01

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a seriesed combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided.

Regenerative switching CMOS system

DOEpatents

Welch, J.D.

1998-06-02

Complementary Metal Oxide Semiconductor (CMOS) Schottky barrier Field Effect Transistor systems, which are a series combination of N and P-Channel MOSFETS, in which Source Schottky barrier junctions of the N and P-Channel Schottky barrier MOSFETS are electrically interconnected, (rather than the Drains as in conventional diffused junction CMOS), which Schottky barrier MOSFET system demonstrates Regenerative Inverting Switching Characteristics in use are disclosed. Both the N and P-Channel Schottky barrier MOSFET devices are unique in that they provide operational Drain Current vs. Drain to Source voltage as a function of Gate voltage only where the polarities of the Drain voltage and Gate voltage are opposite, referenced to the Source as a common terminal, and where the polarity of the voltage applied to the Gate is appropriate to cause Channel inversion. Experimentally derived results which demonstrate and verify the operation of N and P-Channel Schottky barrier MOSFETS actually fabricated on P and N-type Silicon respectively, by a common procedure using vacuum deposited Chromium as a Schottky barrier forming metal, are also provided. 14 figs.

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography.

PubMed

Seco, Joao; Depauw, Nicolas

2011-02-01

Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissue contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution of the CMOS detector for protons. The

Proof of principle study of the use of a CMOS active pixel sensor for proton radiography

DOE Office of Scientific and Technical Information (OSTI.GOV)

Seco, Joao; Depauw, Nicolas

2011-02-15

Purpose: Proof of principle study of the use of a CMOS active pixel sensor (APS) in producing proton radiographic images using the proton beam at the Massachusetts General Hospital (MGH). Methods: A CMOS APS, previously tested for use in s-ray radiation therapy applications, was used for proton beam radiographic imaging at the MGH. Two different setups were used as a proof of principle that CMOS can be used as proton imaging device: (i) a pen with two metal screws to assess spatial resolution of the CMOS and (ii) a phantom with lung tissue, bone tissue, and water to assess tissuemore » contrast of the CMOS. The sensor was then traversed by a double scattered monoenergetic proton beam at 117 MeV, and the energy deposition inside the detector was recorded to assess its energy response. Conventional x-ray images with similar setup at voltages of 70 kVp and proton images using commercial Gafchromic EBT 2 and Kodak X-Omat V films were also taken for comparison purposes. Results: Images were successfully acquired and compared to x-ray kVp and proton EBT2/X-Omat film images. The spatial resolution of the CMOS detector image is subjectively comparable to the EBT2 and Kodak X-Omat V film images obtained at the same object-detector distance. X-rays have apparent higher spatial resolution than the CMOS. However, further studies with different commercial films using proton beam irradiation demonstrate that the distance of the detector to the object is important to the amount of proton scatter contributing to the proton image. Proton images obtained with films at different distances from the source indicate that proton scatter significantly affects the CMOS image quality. Conclusion: Proton radiographic images were successfully acquired at MGH using a CMOS active pixel sensor detector. The CMOS demonstrated spatial resolution subjectively comparable to films at the same object-detector distance. Further work will be done in order to establish the spatial and energy resolution

New possibility on InZnO nano thin film for green emissive optoelectronic devices

NASA Astrophysics Data System (ADS)

Sugumaran, Sathish; Noor Bin Ahmad, Mohd; Faizal Jamlos, Mohd; Bellan, Chandar Shekar; Chandran, Sharmila; Sivaraj, Manoj

2016-04-01

Indium zinc oxide (InZnO) nano thin film was prepared from InZnO nanoparticles (NPs) by thermal evaporation technique. Fourier transform infrared spectroscopy showed the presence of metal-oxide bond. X-ray diffraction pattern revealed the mixed phase structure. The presence of elements In, Zn and O were identified from energy dispersive X-ray analysis. Size of the NPs was found to be 171 and 263 nm by transmission electron microscopy. Scanning electron microscopy image showed the spherical shape uniform morphology with uniform distribution grains. Photoluminescence spectrum exhibited a broad green emission for InZnO nano thin film. The acquired results of structure, smooth morphology and photoluminescence property suggested that the InZnO nano thin film to be a promising material for room temperature green emissive optoelectronic, laser diodes, solar cells and other optical devices.

Low temperature processed complementary metal oxide semiconductor (CMOS) device by oxidation effect from capping layer.

PubMed

Wang, Zhenwei; Al-Jawhari, Hala A; Nayak, Pradipta K; Caraveo-Frescas, J A; Wei, Nini; Hedhili, M N; Alshareef, H N

2015-04-20

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190 °C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field.

CMOS sensors for atmospheric imaging

NASA Astrophysics Data System (ADS)

Pratlong, Jérôme; Burt, David; Jerram, Paul; Mayer, Frédéric; Walker, Andrew; Simpson, Robert; Johnson, Steven; Hubbard, Wendy

2017-09-01

Recent European atmospheric imaging missions have seen a move towards the use of CMOS sensors for the visible and NIR parts of the spectrum. These applications have particular challenges that are completely different to those that have driven the development of commercial sensors for applications such as cell-phone or SLR cameras. This paper will cover the design and performance of general-purpose image sensors that are to be used in the MTG (Meteosat Third Generation) and MetImage satellites and the technology challenges that they have presented. We will discuss how CMOS imagers have been designed with 4T pixel sizes of up to 250 μm square achieving good charge transfer efficiency, or low lag, with signal levels up to 2M electrons and with high line rates. In both devices a low noise analogue read-out chain is used with correlated double sampling to suppress the readout noise and give a maximum dynamic range that is significantly larger than in standard commercial devices. Radiation hardness is a particular challenge for CMOS detectors and both of these sensors have been designed to be fully radiation hard with high latch-up and single-event-upset tolerances, which is now silicon proven on MTG. We will also cover the impact of ionising radiation on these devices. Because with such large pixels the photodiodes have a large open area, front illumination technology is sufficient to meet the detection efficiency requirements but with thicker than standard epitaxial silicon to give improved IR response (note that this makes latch up protection even more important). However with narrow band illumination reflections from the front and back of the dielectric stack on the top of the sensor produce Fabry-Perot étalon effects, which have been minimised with process modifications. We will also cover the addition of precision narrow band filters inside the MTG package to provide a complete imaging subsystem. Control of reflected light is also critical in obtaining the

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Demonstration of a Nano-Enabled Space Power System

NASA Technical Reports Server (NTRS)

Raffaelle, Ryne; Hunter, Roger C.; Baker, Christopher

2017-01-01

The Nano-Enabled Space Power System will demonstrate power systems with nanomaterial-enhanced components as are placement for CubeSat power generation, transmission, and storage. Successful flights of these nano-power systems will accelerate the use of this revolutionary technology in the aerospace industry. The use of nano materials in solar cells, wire harnesses,and lithium ion batteries can increase the device performance without significantly altering the devices physical dimensions or the devices operating range (temperature,voltage, current). In many cases, the use of nanomaterials widens the viable range of operating conditions, such as increased depth of discharge of lithium ion batteries, tunable bandgaps in solar cells, and increased flexure tolerance of wire harnesses.

Micro and nano devices in passive millimetre wave imaging systems

NASA Astrophysics Data System (ADS)

Appleby, R.

2013-06-01

The impact of micro and nano technology on millimetre wave imaging from the post war years to the present day is reviewed. In the 1950s whisker contacted diodes in mixers and vacuum tubes were used to realise both radiometers and radars but required considerable skill to realise the performance needed. Development of planar semiconductor devices such as Gunn and Schottky diodes revolutionised mixer performance and provided considerable improvement. The next major breakthrough was high frequency transistors based on gallium arsenide which were initially used at intermediate frequencies but later after further development at millimeter wave frequencies. More recently Monolithic Microwave Integrated circuits(MMICs) offer exceptional performance and the opportunity for innovative design in passive imaging systems. In the future the use of micro and nano technology will continue to drive system performance and we can expect to see integration of antennae, millimetre wave and sub millimetre wave circuits and signal processing.

A 32 x 32 capacitive micromachined ultrasonic transducer array manufactured in standard CMOS.

PubMed

Lemmerhirt, David F; Cheng, Xiaoyang; White, Robert; Rich, Collin A; Zhang, Man; Fowlkes, J Brian; Kripfgans, Oliver D

2012-07-01

As ultrasound imagers become increasingly portable and lower cost, breakthroughs in transducer technology will be needed to provide high-resolution, real-time 3-D imaging while maintaining the affordability needed for portable systems. This paper presents a 32 x 32 ultrasound array prototype, manufactured using a CMUT-in-CMOS approach whereby ultrasonic transducer elements and readout circuits are integrated on a single chip using a standard integrated circuit manufacturing process in a commercial CMOS foundry. Only blanket wet-etch and sealing steps are added to complete the MEMS devices after the CMOS process. This process typically yields better than 99% working elements per array, with less than ±1.5 dB variation in receive sensitivity among the 1024 individually addressable elements. The CMUT pulseecho frequency response is typically centered at 2.1 MHz with a -6 dB fractional bandwidth of 60%, and elements are arranged on a 250 μm hexagonal grid (less than half-wavelength pitch). Multiplexers and CMOS buffers within the array are used to make on-chip routing manageable, reduce the number of physical output leads, and drive the transducer cable. The array has been interfaced to a commercial imager as well as a set of custom transmit and receive electronics, and volumetric images of nylon fishing line targets have been produced.

Zinc oxide nano-rods based glucose biosensor devices fabrication

NASA Astrophysics Data System (ADS)

Wahab, H. A.; Salama, A. A.; El Saeid, A. A.; Willander, M.; Nur, O.; Battisha, I. K.

2018-06-01

ZnO is distinguished multifunctional material that has wide applications in biochemical sensor devices. For extracellular measurements, Zinc oxide nano-rods will be deposited on conducting plastic substrate with annealing temperature 150 °C (ZNRP150) and silver wire with annealing temperature 250 °C (ZNRW250), for the extracellular glucose concentration determination with functionalized ZNR-coated biosensors. It was performed in phosphate buffer saline (PBS) over the range from 1 μM to 10 mM and on human blood plasma. The prepared samples crystal structure and surface morphologies were characterized by XRD and field emission scanning electron microscope FESEM respectively.

A wafer-level vacuum package using glass-reflowed silicon through-wafer interconnection for nano/micro devices.

PubMed

Jin, Joo-Young; Yoo, Seung-Hyun; Yoo, Byung-Wook; Kim, Yong-Kweon

2012-07-01

We propose a vacuum wafer-level packaging (WLP) process using glass-reflowed silicon via for nano/micro devices (NMDs). A through-wafer interconnection (TWIn) substrate with silicon vias and reflowed glass is introduced to accomplish a vertical feed-through of device. NMDs are fabricated in the single crystal silicon (SCS) layer which is formed on the TWIn substrate by Au eutectic bonding including Cr adhesion layer. The WLPof the devices is achieved with the capping glass wafer anodically bonded to the SCS layer. In order to demonstrate the successful hermetic packaging, we fabricated the micro-Pirani gauge in the SCS layer, and packaged it in the wafer-level. The vacuum level inside the packaging was measured to be 3.1 Torr with +/- 0.12 Torr uncertainty, and the packaging leakage was not detected during 24 hour after the packaging.

A NANO enhancement to Moore's law

NASA Astrophysics Data System (ADS)

Wu, Jerry; Shen, Yin-Lin; Reinhardt, Kitt; Szu, Harold

2012-06-01

In the past 46 years, Intel Moore observed an exponential doubling in the number of transistors in every 18 months through the size reduction of individual transistor components since 1965. In this paper, we are exploring the nanotechnology impact upon the Law. Since we cannot break down the atomic size barrier, the fact implies a fundamental size limit at the atomic or Nanotechnology scale. This means, no more simple 18 month doubling as in Moore's Law, but other forms of transistor doubling may happen at a different slope in new directions. We are particularly interested in the Nano enhancement area. (i) 3-D: If the progress in shrinking the in-plane dimensions (2D) is to slow down, vertical integration (3D) can help increasing the areal device transistor density and keep us on the modified Moore's Law curve including the 3rd dimension. As the devices continue to shrink further into the 20 to 30 nm range, the consideration of thermal properties and transport in such nanoscale devices becomes increasingly important. (ii) Carbon Computing: Instead of traditional Transistors, the other types of transistors material are rapidly developed in Laboratories Worldwide, e.g. IBM Spintronics bandgap material and Samsung Nano-storage material, HD display Nanotechnology, which are modifying the classical Moore's Law. We shall consider the overall limitation of phonon engineering, fundamental information unit 'Qubyte' in quantum computing, Nano/Micro Electrical Mechanical System (NEMS), Carbon NanoTubes (CNTs), single layer Graphemes, single strip Nano-Ribbons, etc., and their variable degree of fabrication maturities for the computing and information processing applications.

Microlens performance limits in sub-2mum pixel CMOS image sensors.

PubMed

Huo, Yijie; Fesenmaier, Christian C; Catrysse, Peter B

2010-03-15

CMOS image sensors with smaller pixels are expected to enable digital imaging systems with better resolution. When pixel size scales below 2 mum, however, diffraction affects the optical performance of the pixel and its microlens, in particular. We present a first-principles electromagnetic analysis of microlens behavior during the lateral scaling of CMOS image sensor pixels. We establish for a three-metal-layer pixel that diffraction prevents the microlens from acting as a focusing element when pixels become smaller than 1.4 microm. This severely degrades performance for on and off-axis pixels in red, green and blue color channels. We predict that one-metal-layer or backside-illuminated pixels are required to extend the functionality of microlenses beyond the 1.4 microm pixel node.

Low Temperature Processed Complementary Metal Oxide Semiconductor (CMOS) Device by Oxidation Effect from Capping Layer

PubMed Central

Wang, Zhenwei; Al-Jawhari, Hala A.; Nayak, Pradipta K.; Caraveo-Frescas, J. A.; Wei, Nini; Hedhili, M. N.; Alshareef, H. N.

2015-01-01

In this report, both p- and n-type tin oxide thin-film transistors (TFTs) were simultaneously achieved using single-step deposition of the tin oxide channel layer. The tuning of charge carrier polarity in the tin oxide channel is achieved by selectively depositing a copper oxide capping layer on top of tin oxide, which serves as an oxygen source, providing additional oxygen to form an n-type tin dioxide phase. The oxidation process can be realized by annealing at temperature as low as 190°C in air, which is significantly lower than the temperature generally required to form tin dioxide. Based on this approach, CMOS inverters based entirely on tin oxide TFTs were fabricated. Our method provides a solution to lower the process temperature for tin dioxide phase, which facilitates the application of this transparent oxide semiconductor in emerging electronic devices field. PMID:25892711

A monolithic 640 × 512 CMOS imager with high-NIR sensitivity

NASA Astrophysics Data System (ADS)

Lauxtermann, Stefan; Fisher, John; McDougal, Michael

2014-06-01

In this paper we present first results from a backside illuminated CMOS image sensor that we fabricated on high resistivity silicon. Compared to conventional CMOS imagers, a thicker photosensitive membrane can be depleted when using silicon with low background doping concentration while maintaining low dark current and good MTF performance. The benefits of such a fully depleted silicon sensor are high quantum efficiency over a wide spectral range and a fast photo detector response. Combining these characteristics with the circuit complexity and manufacturing maturity available from a modern, mixed signal CMOS technology leads to a new type of sensor, with an unprecedented performance spectrum in a monolithic device. Our fully depleted, backside illuminated CMOS sensor was designed to operate at integration times down to 100nsec and frame rates up to 1000Hz. Noise in Integrate While Read (IWR) snapshot shutter operation for these conditions was simulated to be below 10e- at room temperature. 2×2 binning with a 4× increase in sensitivity and a maximum frame rate of 4000 Hz is supported. For application in hyperspectral imaging systems the full well capacity in each row can individually be programmed between 10ke-, 60ke- and 500ke-. On test structures we measured a room temperature dark current of 360pA/cm2 at a reverse bias of 3.3V. A peak quantum efficiency of 80% was measured with a single layer AR coating on the backside. Test images captured with the 50μm thick VGA imager between 30Hz and 90Hz frame rate show a strong response at NIR wavelengths.

Sticker-type ECG/PPG concurrent monitoring system hybrid integration of CMOS SoC and organic sensor device.

PubMed

Yongsu Lee; Hyeonwoo Lee; Seunghyup Yoo; Hoi-Jun Yoo

2016-08-01

The sticker-type sensor system is proposed targeting ECG/PPG concurrent monitoring for cardiovascular diseases. The stickers are composed of two types: Hub and Sensor-node (SN) sticker. Low-power CMOS SoC for measuring ECG and PPG signal is hybrid integrated with organic light emitting diodes (OLEDs) and organic photo detector (OPD). The sticker has only 2g weight and only consumes 141μW. The optical calibration loop is adopted for maintaining SNR of PPG signal higher than 30dB. The pulse arrival time (PAT) and SpO2 value can be extracted from various body parts and verified comparing with the reference device from 20 people in-vivo experiments.

Nano scale devices: Fabrication, actuation, and related fluidic dynamics

NASA Astrophysics Data System (ADS)

Jing, Hao

Using external actuating magnetic fields to manipulate magnetic parts is an efficient method to manipulate mesoscopic actable devices. Extensive researches have explored the potentials of self-assembly techniques based on capillary force, static charge force, drying, surface tension, and even dynamic fields as a low cost method for ordered 2D or 3D super-lattice structures for new materials and devices. But the ability of tunable patterning nano-particles for designed actable devices is still a requirement yet to be met. Utilizing anodized aluminum oxide (AAO) membranes as templates, soft-magnetic nanowires around 200 nm in diameter, 10 microns long have been fabricated. In this thesis, I describe a method to assemble these magnetic nanowires into a two dimension Wigner structure, of which the wire-wire distance is conveniently adjustable during the fabrication procedure. Using geometric tailored magnetic fields, we can plant these self-assembled magnetic nanowires with desired patterns into a thin soft polymer support layer. The final devices may be readily actuated by an external actuating magnetic field (a self-designed magnetic system, 3-dimensional force microscope (3DFM)) with precise patterns and frequencies in a micro-fluidic system. This method offers a general method to fabricate mesoscopic devices from a wide range of materials with magnetic dipoles to desired structures. And the actable devices themselves can find direct usage in low Re number flow mixing and bio-physical fluidic dynamic researches. The beating of cilia and flagella, slender cylinders 250 nanometers in diameter with lengths from 7 to 50 microns, is responsible for many important biological functions such as organism feeding, propulsion, for bacterial clearance in the lungs and for the right-left asymmetry in vertebrates. The hydrodynamics produced by these beating structures, including mixing, shear and extensional flows, is not understood. We developed an experimental model system for

Integrated on-chip solid state capacitor based on vertically aligned carbon nanofibers, grown using a CMOS temperature compatible process

NASA Astrophysics Data System (ADS)

Saleem, Amin M.; Andersson, Rickard; Desmaris, Vincent; Enoksson, Peter

2018-01-01

Complete miniaturized on-chip integrated solid-state capacitors have been fabricated based on conformal coating of vertically aligned carbon nanofibers (VACNFs), using a CMOS temperature compatible microfabrication processes. The 5 μm long VACNFs, operating as electrode, are grown on a silicon substrate and conformally coated by aluminum oxide dielectric using atomic layer deposition (ALD) technique. The areal (footprint) capacitance density value of 11-15 nF/mm2 is realized with high reproducibility. The CMOS temperature compatible microfabrication, ultra-low profile (less than 7 μm thickness) and high capacitance density would enables direct integration of micro energy storage devices on the active CMOS chip, multi-chip package and passives on silicon or glass interposer. A model is developed to calculate the surface area of VACNFs and the effective capacitance from the devices. It is thereby shown that 71% of surface area of the VACNFs has contributed to the measured capacitance, and by using the entire area the capacitance can potentially be increased.

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

PubMed Central

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-01-01

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption. PMID:27312225

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition

NASA Astrophysics Data System (ADS)

Niu, Gang; Kim, Hee-Dong; Roelofs, Robin; Perez, Eduardo; Schubert, Markus Andreas; Zaumseil, Peter; Costina, Ioan; Wenger, Christian

2016-06-01

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications.

PubMed

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-05-09

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm(2) V(-1) sec(-1), and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity.

Fabrication of Ultra-Thin Printed Organic TFT CMOS Logic Circuits Optimized for Low-Voltage Wearable Sensor Applications

PubMed Central

Takeda, Yasunori; Hayasaka, Kazuma; Shiwaku, Rei; Yokosawa, Koji; Shiba, Takeo; Mamada, Masashi; Kumaki, Daisuke; Fukuda, Kenjiro; Tokito, Shizuo

2016-01-01

Ultrathin electronic circuits that can be manufactured by using conventional printing technologies are key elements necessary to realize wearable health sensors and next-generation flexible electronic devices. Due to their low level of power consumption, complementary (CMOS) circuits using both types of semiconductors can be easily employed in wireless devices. Here, we describe ultrathin CMOS logic circuits, for which not only the source/drain electrodes but also the semiconductor layers were printed. Both p-type and n-type organic thin film transistor devices were employed in a D-flip flop circuit in the newly developed stacked structure and exhibited excellent electrical characteristics, including good carrier mobilities of 0.34 and 0.21 cm2 V−1 sec−1, and threshold voltages of nearly 0 V with low operating voltages. These printed organic CMOS D-flip flop circuits exhibit operating frequencies of 75 Hz and demonstrate great potential for flexible and printed electronics technology, particularly for wearable sensor applications with wireless connectivity. PMID:27157914

Remote optical sensing on the nanometer scale with a bowtie aperture nano-antenna on a fiber tip of scanning near-field optical microscopy

DOE Office of Scientific and Technical Information (OSTI.GOV)

Atie, Elie M.; Xie, Zhihua; El Eter, Ali

2015-04-13

Plasmonic nano-antennas have proven the outstanding ability of sensing chemical and physical processes down to the nanometer scale. Sensing is usually achieved within the highly confined optical fields generated resonantly by the nano-antennas, i.e., in contact to the nanostructures. In this paper, we demonstrate the sensing capability of nano-antennas to their larger scale environment, well beyond their plasmonic confinement volume, leading to the concept of “remote” (non contact) sensing on the nanometer scale. On the basis of a bowtie-aperture nano-antenna (BNA) integrated at the apex of a SNOM (Scanning Near-field Optical Microscopy) fiber tip, we introduce an ultra-compact, moveable, andmore » background-free optical nanosensor for the remote sensing of a silicon surface (up to distance of 300 nm). Sensitivity of the BNA to its large scale environment is high enough to expect the monitoring and control of the spacing between the nano-antenna and a silicon surface with sub-nanometer accuracy. This work paves the way towards an alternative class of nanopositioning techniques, based on the monitoring of diffraction-free plasmon resonance, that are alternative to nanomechanical and diffraction-limited optical interference-based devices.« less

Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

NASA Astrophysics Data System (ADS)

Zhang, Ying; Zhu, Hongbo; Zhang, Liang; Fu, Min

2016-09-01

The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q / C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18 μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

Assessment of a Low-Power 65 nm CMOS Technology for Analog Front-End Design

NASA Astrophysics Data System (ADS)

Manghisoni, Massimo; Gaioni, Luigi; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

2014-02-01

This work is concerned with the study of the analog properties of MOSFET devices belonging to a 65 nm CMOS technology with emphasis on intrinsic voltage gain and noise performance. This node appears to be a robust and promising solution to cope with the unprecedented requirements set by silicon vertex trackers in experiments upgrades and future colliders as well as by imaging detectors at light sources and free electron lasers. In this scaled-down technology, the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. An inversion level design methodology has been adopted to analyze data obtained from device measurements and provide a powerful tool to establish design criteria for detector front-ends in this nanoscale CMOS process. A comparison with data coming from less scaled technologies, such as 90 nm and 130 nm nodes, is also provided and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100 nm minimum feature size range.

Integration of micro-/nano-/quantum-scale photonic devices: scientific and technological considerations

NASA Astrophysics Data System (ADS)

Lee, El-Hang; Lee, Seung-Gol; O, Beom Hoan; Park, Se Geun

2004-08-01

Scientific and technological issues and considerations regarding the integration of miniaturized microphotonic devices, circuits and systems in micron, submicron, and quantum scale, are presented. First, we examine the issues regarding the miniaturization of photonic devices including the size effect, proximity effect, energy confinement effect, microcavity effect, optical and quantum interference effect, high field effect, nonlinear effect, noise effect, quantum optical effect, and chaotic effect. Secondly, we examine the issues regarding the interconnection including the optical alignment, minimizing the interconnection losses, and maintaining optical modes. Thirdly, we address the issues regarding the two-dimensional or three-dimensional integration either in a hybrid format or in a monolithic format between active devices and passive devices of varying functions. We find that the concept of optical printed circuit board (O-PCB) that we propose is highly attractive as a platform for micro/nano/quantum-scale photonic integration. We examine the technological issues to be addressed in the process of fabrication, characterization, and packaging for actual implementation of the miniaturization, interconnection and integration. Devices that we have used for our study include: mode conversion schemes, micro-ring and micro-racetrack resonator devices, multimode interference devices, lasers, vertical cavity surface emitting microlasers, and their arrays. Future prospects are also discussed.

Nano-extrusion: a promising tool for continuous manufacturing of solid nano-formulations.

PubMed

Baumgartner, Ramona; Eitzlmayr, Andreas; Matsko, Nadejda; Tetyczka, Carolin; Khinast, Johannes; Roblegg, Eva

2014-12-30

Since more than 40% of today's drugs have low stability, poor solubility and/or limited ability to cross certain biological barriers, new platform technologies are required to address these challenges. This paper describes a novel continuous process that converts a stabilized aqueous nano-suspension into a solid oral formulation in a single step (i.e., the NANEX process) in order to improve the solubility of a model drug (phenytoin). Phenytoin nano-suspensions were prepared via media milling using different stabilizers. A stable nano-suspension was obtained using Tween(®) 80 as a stabilizer. The matrix material (Soluplus(®)) was gravimetrically fed into the hot melt extruder. The suspension was introduced through a side feeding device and mixed with the molten polymer to immediately devolatilize the water in the nano-suspension. Phenytoin nano-crystals were dispersed and embedded in the molten polymer. Investigation of the nano-extrudates via transmission electron microscopy and atomic force microscopy showed that the nano-crystals were embedded de-aggregated in the extrudates. Furthermore, no changes in the crystallinity (due to the mechanical and thermal stress) occurred. The dissolution studies confirmed that the prepared nano-extrudates increased the solubility of nano-crystalline phenytoin, regardless of the polymer. Our work demonstrates that NANEX represents a promising new platform technology in the design of novel drug delivery systems to improve drug performance. Copyright © 2014 Elsevier B.V. All rights reserved.

Expanding Applications of the Nano Intravital Device as a Platform for Exploring Tumor Microenvironments

NASA Astrophysics Data System (ADS)

Padgen, Michael R.

The tumor microenvironment has been demonstrated to be a key determinant in the progression of cancer. Unfortunately, the mechanisms behind the different microenvironments (cytokine gradients, hypoxia, hypoglycemia, etc) have not been fully elucidated. Identifying these mechanisms can lead to targeted, individualized therapy to prevent metastasis. The Nano Intravital Device (NANIVID) is a microfabricated, implantable device designed to initiate specific microenvironments in vivo so that the time course of the effects can be observed. With both spatial and temporal control over the induced environments, the affected regions of the tumor can be compared to the rest of the tumor. The NANIVID was first used to establish cytokine gradients to monitor the migration of invasive cancer cells. The three projects that comprise this work expand the applications of the NANIVID to establish the device as a robust platform for investigating tumor microenvironment interactions. The first project released chemical mimics from the device to induce the cellular hypoxic response in tumors to determine how hypoxia affects the fate of disseminated tumor cells. The second project used the NANIVID in combination with an atomic force microscope to investigate the altered mechanics of migrating invasive cancer cells. The final project was to develop a cell counter to monitor the isolation of the invasive subpopulation of cells that were drawn into the device using a chemoattractant. These three projects demonstrate the potential of the NANIVID as a platform for investigating the tumor microenvironment.

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE PAGES

An, Mangmang; Chen, Chufeng; Gao, Chaosong; ...

2015-12-12

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

A low-noise CMOS pixel direct charge sensor, Topmetal-II-

DOE Office of Scientific and Technical Information (OSTI.GOV)

An, Mangmang; Chen, Chufeng; Gao, Chaosong

In this paper, we report the design and characterization of a CMOS pixel direct charge sensor, Topmetal-II-, fabricated in a standard 0.35 μm CMOS Integrated Circuit process. The sensor utilizes exposed metal patches on top of each pixel to directly collect charge. Each pixel contains a low-noise charge-sensitive preamplifier to establish the analog signal and a discriminator with tunable threshold to generate hits. The analog signal from each pixel is accessible through time-shared multiplexing over the entire array. Hits are read out digitally through a column-based priority logic structure. Tests show that the sensor achieved a <15e - analog noisemore » and a 200e - minimum threshold for digital readout per pixel. The sensor is capable of detecting both electrons and ions drifting in gas. Lastly, these characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments.« less

A Novel Nonviral Gene Delivery System: Multifunctional Envelope-Type Nano Device

NASA Astrophysics Data System (ADS)

Hatakeyama, Hiroto; Akita, Hidetaka; Kogure, Kentaro; Harashima, Hideyoshi

In this review we introduce a new concept for developing a nonviral gene delivery system which we call "Programmed Packaging." Based on this concept, we succeeded in developing a multifunctional envelope-type nano device (MEND), which exerts high transfection activities equivalent to those of an adenovirus in a dividing cell. The use of MEND has been extended to in vivo applications. PEG/peptide/DOPE ternary conjugate (PPD)-MEND, a new in vivo gene delivery system for the targeting of tumor cells that dissociates surface-modified PEG in tumor tissue by matrix metalloproteinase (MMP) and exerts significant transfection activities, was developed. In parallel with the development of MEND, a quantitative gene delivery system, Confocal Image-assisted 3-dimensionally integrated quantification (CIDIQ), also was developed. This method identified the rate-limiting step of the nonviral gene delivery system by comparing it with adenoviral-mediated gene delivery. The results of this analysis provide a new direction for the development of rational nonviral gene delivery systems.

Carbon Nanotube Integration with a CMOS Process

PubMed Central

Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

2010-01-01

This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

Active control of nano dimers response using piezoelectric effect

NASA Astrophysics Data System (ADS)

Mekkawy, Ahmed A.; Ali, Tamer A.; Badawi, Ashraf H.

2016-09-01

Nano devices can be used as building blocks for Internet of Nano-Things network devices, such as sensors/actuators, transceivers, and routers. Although nano particles response can be engineered to fit in different regimes, for such a nano particle to be used as an active nano device, its properties should be dynamically controlled. This controllability is a challenge, and there are many proposed techniques to tune nanoparticle response on the spot through a sort of control signal, wither that signal is optical (for all-optical systems) or electronic (for opto-electronic systems). This will allow the use of nano particles as nano-switches or as dynamic sensors that can pick different frequencies depending on surrounding conditions or depending on a smart decisions. In this work, we propose a piezoelectric substrate as an active control mediator to control plasmonic gaps in nano dimers. This method allows for integrating nano devices with regular electronics while communicating control signals to nano devices through applying electric signals to a piezoelectric material, in order to control the gaps between nano particles in a nano cluster. We do a full numerical study to the system, analyzing the piezoelectric control resolution (minimum gap change step) and its effect on a nanodimer response as a nanoantenna. This analysis considers the dielectric functions of materials within the visible frequencies range. The effects of different parameters, such as the piezoelectric geometrical structure and materials, on the gap control resolution and the operating frequency are studied.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

PubMed

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

2018-04-05

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

PubMed Central

Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun

2018-01-01

Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256×13 real-time radar image display with a throughput of 28.2 frames per second. PMID:29621170

Mechanical Computing Redux: Limitations at the Nanoscale

NASA Astrophysics Data System (ADS)

Liu, Tsu-Jae King

2014-03-01

Technology solutions for overcoming the energy efficiency limits of nanoscale complementary metal oxide semiconductor (CMOS) technology ultimately will be needed in order to address the growing issue of integrated-circuit chip power density. Off-state leakage current sets a fundamental lower limit in energy per operation for any voltage-level-based digital logic implemented with transistors (CMOS and beyond), which leads to practical limits for device density (i.e. cost) and operating frequency (i.e. system performance). Mechanical switches have zero off-state leakag and hence can overcome this fundamental limit. Contact adhesive force sets a lower limit for the switching energy of a mechanical switch, however, and also directly impacts its performance. This paper will review recent progress toward the development of nano-electro-mechanical relay technology and discuss remaining challenges for realizing the promise of mechanical computing for ultra-low-power computing. Supported by the Center for Energy Efficient Electronics Science (NSF Award 0939514).

Built-in self-test (BIST) techniques for millimeter wave CMOS transceivers

NASA Astrophysics Data System (ADS)

Mahzabeen, Tabassum

The seamless integration of complementary metal oxide semiconductor (CMOS) transceivers with a digital CMOS process enhances on-chip testability, thus reducing production and testing costs. Built in self testability also improves yield by offering on-chip compensation. This work focuses on built in self test techniques for CMOS based millimeter wave (mm-wave) transceivers. Built-in-self-test (BIST) using the loopback method is one cost-effective method for testing these transceivers. Since the loopback switch is always present during the normal operation of the transceiver, the requirement of the switch is different than for a conventional switch. The switch needs to have high isolation and high impedance during its OFF period. Two 80 GHz single pole single throw (SPST) switches have been designed, fabricated in standard CMOS process, and measured to connect the loopback path for BIST applications. The loopback switches in this work provide the required criteria for loopback BIST. A stand alone 80 GHz low noise amplifier (LNA) and the same LNA integrated with one of the loopback switches have been fabricated, and measured to observe the difference in performance when the loopback switch is present. Besides the loopback switch, substrate leakage also forms a path between the transmitter and receiver. Substrate leakage has been characterized as a function of distance between the transmitter and receiver for consideration in using the BIST method. A BIST algorithm has been developed to estimate the process variation in device sizes by probing a low frequency ring oscillator to estimate the device variation and map this variation to the 80 GHz LNA. Probing a low frequency circuit is cheaper compared to the probing of a millimeter wave circuit and reduces the testing costs. The performance of the LNA degrades due to variation in device size. Once the shift in the device size is being estimated (from the ring oscillator's shifted frequency), the LNA's performance can be

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

PubMed

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2011-10-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager

PubMed Central

Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

2012-01-01

Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm2 at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm2. Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm2 while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt. PMID:23136624

The integration of InGaP LEDs with CMOS on 200 mm silicon wafers

NASA Astrophysics Data System (ADS)

Wang, Bing; Lee, Kwang Hong; Wang, Cong; Wang, Yue; Made, Riko I.; Sasangka, Wardhana Aji; Nguyen, Viet Cuong; Lee, Kenneth Eng Kian; Tan, Chuan Seng; Yoon, Soon Fatt; Fitzgerald, Eugene A.; Michel, Jurgen

2017-02-01

The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems.

Flip-chip integrated silicon Mach-Zehnder modulator with a 28nm fully depleted silicon-on-insulator CMOS driver.

PubMed

Yong, Zheng; Shopov, Stefan; Mikkelsen, Jared C; Mallard, Robert; Mak, Jason C C; Voinigescu, Sorin P; Poon, Joyce K S

2017-03-20

We present a silicon electro-optic transmitter consisting of a 28nm ultra-thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) CMOS driver flip-chip integrated onto a Mach-Zehnder modulator. The Mach-Zehnder silicon optical modulator was optimized to have a 3dB bandwidth of around 25 GHz at -1V bias and a 50 Ω impedance. The UTBB FD-SOI CMOS driver provided a large output voltage swing around 5 V_pp to enable a high dynamic extinction ratio and a low device insertion loss. At 44 Gbps, the transmitter achieved a high extinction ratio of 6.4 dB at the modulator quadrature operation point. This result shows open eye diagrams at the highest bit rates and with the largest extinction ratios for silicon electro-optic transmitter using a CMOS driver.

Solar XUV Imaging and Non-dispersive Spectroscopy for Solar-C Enabled by Scientific CMOS APS Arrays

NASA Astrophysics Data System (ADS)

Stern, Robert A.; Lemen, J. R.; Shing, L.; Janesick, J.; Tower, J.

2009-05-01

Monolithic CMOS Advanced Pixel Sensor (APS) arrays are showing great promise as eventual replacements for the current workhorse of solar physics focal planes, the scientific CCD. CMOS APS devices have individually addressable pixels, increased radiation tolerance compared to CCDs, and require lower clock voltages, and thus lower power. However, commercially available CMOS chips, while suitable for use with intensifiers or fluorescent coatings, are generally not optimized for direct detection of EUV and X-ray photons. A high performance scientific CMOS array designed for these wavelengths will have significant new capabilities compared to CCDs, including the ability to read out small regions of the solar disk at high (sub sec) cadence, count single X-ray photons with Fano-limited energy resolution, and even operate at room temperature with good noise performance. Such capabilities will be crucial for future solar X-ray and EUV missions such as Solar-C. Sarnoff Corporation has developed scientific grade, monolithic CMOS arrays for X-ray imaging and photon counting. One prototype device, the "minimal" array, has 8 um pixels, is 15 to 25 um thick, is fabricated on high-resistivity ( 10 to 20 kohm-cm) Si wafers, and can be back-illuminated. These characteristics yield high quantum efficiency and high spatial resolution with minimal charge sharing among pixels, making it ideal for the detection of keV X-rays. When used with digital correlated double sampling, the array has demonstrated noise performance as low as 2 e, allowing single photon counting of X-rays over a range of temperatures. We report test results for this device in X-rays, and discuss the implications for future solar space missions.

Development of Smartphone based Optical Device

NASA Astrophysics Data System (ADS)

Jung, Youngkee

Due to the economy of scale, smartphones are becoming more affordable while their computing powers are increasing dramatically every year. Here we propose a ubiquitous and portable instrument for analyte quantitation by utilizing the characteristics of typical smartphone imaging system and specific design of transducers for different applications. Three testbeds included in this work are: quantitative colorimetric analysis, ultra-low radiant flux detection, and portable spectrometer. As a proof-of-principle for each device, 3-D printed cradle and theoretical simulation with MATLAB have been implemented. First example utilizes the native CMOS camera with their respective RGB channel data and perform an analyte quantitation for typical lateral flow devices (LFD). Histogram analysis method has been employed to detect the analyte concentration and calibration results show good correlation between perceived color change and analyte concentration. The second example shows the possibility of using a conventional CMOS camera for pico Watt level photon flux detection. Since most of consumer grade CMOS cameras cannot detect this level of light intensity and their dark current are relatively higher, a new algorithm called NREA (Noise Reduction by Ensemble Averaging) algorithm was developed to effectively reduce the noise level and increase the SNR (signal to noise ratio). This technique is effective for bioanalytical assays that has lower flux intensity such as fluorescence and luminescence. As a proof-of-principle, we tested the device with Pseudomonas fluorescens M3A and achieved a limit of detection of high 10? CFU/ml. In addition to basic schematic of detection model, another experiment with a silicon photomultiplier (SiPM) has been studied for more sensitive light detectability. Based on both the laser experiment and tw bioluminescent experiments, named Pseudomonas fluorescens M3A and NanoLuc, we found that the miniSM based device has a superior ability than the

Behavior of a nano-particle and a polymer molecule in a nano-scale four-roll mill

NASA Astrophysics Data System (ADS)

Vo, Minh; Papavassiliou, Dimitrios

2016-11-01

The four-roll mill device could be used to create a mixed flow from purely extensional stresses to completely rotational through the proper selection of speed and direction of each of the four cylindrical rollers. Considerable research has been done with this device for macroscale rheological studies.. In our study, the dissipative particle dynamics (DPD) method was employed to investigate the behavior of a nano-sphere and a polymer molecule in different conditions within a four-roll mill device. Hydrophilic properties of each roll were generated by adjusting interaction parameters and using bounce back boundary condition at the solid surface. All simulations were run up to 4x106 time steps at room temperature using the open source LAMMPS package. After the flow in the system reached equilibrium, a nano-sphere and then a polymer chain were released at the center of the simulation box. Their trajectories were recorded at different shear rate conditions. The propagation of nanosphere in different rotational flow will be discussed. Additionally, the deformation of polymer chains will be compared to that in a simple shear flow.

Meissner effect measurement of single indium particle using a customized on-chip nano-scale superconducting quantum interference device system

NASA Astrophysics Data System (ADS)

Wu, Long; Chen, Lei; Wang, Hao; Liu, Xiaoyu; Wang, Zhen

2017-04-01

As many emergent phenomena of superconductivity appear on a smaller scale and at lower dimension, commercial magnetic property measurement systems (MPMSs) no longer provide the sensitivity necessary to study the Meissner effect of small superconductors. The nano-scale superconducting quantum interference device (nano-SQUID) is considered one of the most sensitive magnetic sensors for the magnetic characterization of mesoscopic or microscopic samples. Here, we develop a customized on-chip nano-SQUID measurement system based on a pulsed current biasing method. The noise performance of our system is approximately 4.6 × 10-17 emu/Hz1/2, representing an improvement of 9 orders of magnitude compared with that of a commercial MPMS (~10-8 emu/Hz1/2). Furthermore, we demonstrate the measurement of the Meissner effect of a single indium (In) particle (of 47 μm in diameter) using our on-chip nano-SQUID system. The system enables the observation of the prompt superconducting transition of the Meissner effect of a single In particle, thereby providing more accurate characterization of the critical field Hc and temperature Tc. In addition, the retrapping field Hre as a function of temperature T of single In particle shows disparate behavior from that of a large ensemble.

Electroluminescence dependence on the organic thickness in ZnO nano rods/Alq3 heterostructure devices.

PubMed

Kan, Pengzhi; Wang, Yongsheng; Zhao, Suling; Xu, Zheng; Wang, Dawei

2011-04-01

ZnO nanorods are synthesised by a hydrothermal method on ITO glass. Their crystallization and morphology are detected by XRD and SEM, respectively. The results show that the ZnO nanorod array has grown primarily along a direction aligned perpendicular to the ITO substrate. The average height and diameter of the nanorods is about 130 nm and 30 nm, respectively. Then ZnO nano rods/Alq3 heterostructure LEDs are prepared by thermal evaporation of Alq3 molecules. The thicknesses of the Alq3 layers are 130 nm, 150 nm, 170 nm and 190 nm, respectively. The electroluminescence of the devices is detected under different DC bias voltages. The exciton emission of Alq3 is detected in all devices. When the thickness of Alq3 is 130 nm, the UV electroluminescence of ZnO is around 382 nm, and defect emissions around 670 nm and 740 nm are detected. Defect emissions of ZnO nanorods are prominent. When the thickness of Alq3 increases to over 170 nm, it is difficult to observe defect emissions from the ZnO nano rods. In such devices, the exciton emission of Alq3 is more prominent than other emissions under different bias voltage.

Single Molecule Nano-Metronome

PubMed Central

Buranachai, Chittanon; McKinney, Sean A.; Ha, Taekjip

2008-01-01

We constructed a DNA-based nano-mechanical device called the nano-metronome. Our device is made by introducing complementary single stranded overhangs at the two arms of the DNA four-way junction. The ticking rates of this stochastic metronome depend on ion concentrations and can be changed by a set of DNA-based switches to deactivate/reactivate the sticky end. Since the device displays clearly distinguishable responses even with a single basepair difference, it may lead to a single molecule sensor of minute sequence differences of a target DNA. PMID:16522050

Advancing the Technology of Monolithic CMOS detectors for their use as X-ray Imaging Spectrometers

NASA Astrophysics Data System (ADS)

Kenter, Almus

The Smithsonian Astrophysical Observatory (SAO) proposes a two year program to further advance the scientific capabilities of monolithic CMOS detectors for use as x-ray imaging spectrometers. This proposal will build upon the progress achieved with funding from a previous APRA proposal that ended in 2013. As part of that previous proposal, x- ray optimized, highly versatile, monolithic CMOS imaging detectors and technology were developed and tested. The performance and capabilities of these devices were then demonstrated, with an emphasis on the performance advantages these devices have over CCDs and other technologies. The developed SAO/SRI-Sarnoff CMOS devices incorporate: Low noise, high sensitivity ("gain") pixels; Highly parallel on-chip signal chains; Standard and very high resistivity (30,000Ohm-cm) Si; Back-Side thinning and passivation. SAO demonstrated the performance benefits of each of these features in these devices. This new proposal high-lights the performance of this previous generation of devices, and segues into new technology and capability. The high sensitivity ( 135uV/e) 6 Transistor (6T) Pinned Photo Diode (PPD) pixels provided a large charge to voltage conversion gain to the detect and resolve even small numbers of photo electrons produced by x-rays. The on-chip, parallel signal chain processed an entire row of pixels in the same time that a CCD requires to processes a single pixel. The resulting high speed operation ( 1000 times faster than CCD) provide temporal resolution while mitigating dark current and allowed room temperature operation. The high resistivity Si provided full (over) depletion for thicker devices which increased QE for higher energy x-rays. In this proposal, SAO will investigate existing NMOS and existing PMOS devices as xray imaging spectrometers. Conventional CMOS imagers are NMOS. NMOS devices collect and measure photo-electrons. In contrast, PMOS devices collect and measure photo-holes. PMOS devices have various

Laser as a Tool to Study Radiation Effects in CMOS

NASA Astrophysics Data System (ADS)

Ajdari, Bahar

Energetic particles from cosmic ray or terrestrial sources can strike sensitive areas of CMOS devices and cause soft errors. Understanding the effects of such interactions is crucial as the device technology advances, and chip reliability has become more important than ever. Particle accelerator testing has been the standard method to characterize the sensitivity of chips to single event upsets (SEUs). However, because of their costs and availability limitations, other techniques have been explored. Pulsed laser has been a successful tool for characterization of SEU behavior, but to this day, laser has not been recognized as a comparable method to beam testing. In this thesis, I propose a methodology of correlating laser soft error rate (SER) to particle beam gathered data. Additionally, results are presented showing a temperature dependence of SER and the "neighbor effect" phenomenon where due to the close proximity of devices a "weakening effect" in the ON state can be observed.

A reliable and controllable graphene doping method compatible with current CMOS technology and the demonstration of its device applications

NASA Astrophysics Data System (ADS)

Kim, Seonyeong; Shin, Somyeong; Kim, Taekwang; Du, Hyewon; Song, Minho; Kim, Ki Soo; Cho, Seungmin; Lee, Sang Wook; Seo, Sunae

2017-04-01

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

A CMOS high speed imaging system design based on FPGA

NASA Astrophysics Data System (ADS)

Tang, Hong; Wang, Huawei; Cao, Jianzhong; Qiao, Mingrui

2015-10-01

CMOS sensors have more advantages than traditional CCD sensors. The imaging system based on CMOS has become a hot spot in research and development. In order to achieve the real-time data acquisition and high-speed transmission, we design a high-speed CMOS imaging system on account of FPGA. The core control chip of this system is XC6SL75T and we take advantages of CameraLink interface and AM41V4 CMOS image sensors to transmit and acquire image data. AM41V4 is a 4 Megapixel High speed 500 frames per second CMOS image sensor with global shutter and 4/3" optical format. The sensor uses column parallel A/D converters to digitize the images. The CameraLink interface adopts DS90CR287 and it can convert 28 bits of LVCMOS/LVTTL data into four LVDS data stream. The reflected light of objects is photographed by the CMOS detectors. CMOS sensors convert the light to electronic signals and then send them to FPGA. FPGA processes data it received and transmits them to upper computer which has acquisition cards through CameraLink interface configured as full models. Then PC will store, visualize and process images later. The structure and principle of the system are both explained in this paper and this paper introduces the hardware and software design of the system. FPGA introduces the driven clock of CMOS. The data in CMOS is converted to LVDS signals and then transmitted to the data acquisition cards. After simulation, the paper presents a row transfer timing sequence of CMOS. The system realized real-time image acquisition and external controls.

Computational modeling and simulation study of electronic and thermal properties in semiconductor nanostructures

NASA Astrophysics Data System (ADS)

Paul, Abhijeet

2011-07-01

The technological progress in dimensional scaling has not only kept Silicon CMOS industry on Moore's law for the past five decades but has also benefited many other areas such as thermoelectricity, photo-voltaics, and energy storage. Extending CMOS beyond Si (More Moore, MM) and adding functional diversity to CMOS (More Than Moore, MTM) requires a thorough understanding of the basic electron and heat flow in semiconductors. Along with experiments computer modeling and simulation are playing an increasingly vital role in exploring the numerous possibilities in materials, devices and systems. With these aspects in mind the present work applies computational physics modeling and simulations to explore the, (i) electronic, (ii) thermal, and (iii) thermoelectric properties in nano-scale semiconductors. The electronic structure of zinc-blende and lead-chalcogenide nano-materials is calculated using an atomistic Tight-Binding model. The phonon dispersion in zinc-blende materials is obtained using the Modified Valence Force Field model. Electronic and thermal transport at the nano-scale is explored using Green's function method and Landauer's method. Thermoelectric properties of semiconductor nanostructures are calculated using Landauer's method. Using computer modeling and simulations the variation of the three physical properties (i-iii) are explored with varying size, transport orientation, shape, porosity, strain and alloying of nanostructures. The key findings are, (a) III-Vs and Ge with optimized strain and orientation can improve transistors' and thermoelectric performance, (b) porous Si nanowires provide a lucrative idea for enhancing the thermoelectric efficiency at room temperature, and (c) Si/Ge superlattice nanowires can be used for nano-scale tuning of lattice thermal conductivity by period control. The present work led to the development of two new interface trap density extraction methods in ultra-scaled FinFETs and correlation of the phonon shifts in Si

Label-free CMOS bio sensor with on-chip noise reduction scheme for real-time quantitative monitoring of biomolecules.

PubMed

Seong-Jin Kim; Euisik Yoon

2012-06-01

We present a label-free CMOS field-effect transistor sensing array to detect the surface potential change affected by the negative charge in DNA molecules for real-time monitoring and quantification. The proposed CMOS bio sensor includes a new sensing pixel architecture implemented with correlated double sampling for reducing offset fixed pattern noise and 1/f noise of the sensing devices. We incorporated non-surface binding detection which allows real-time continuous monitoring of DNA concentrations without immobilizing them on the sensing surface. Various concentrations of 19-bp oligonucleotides solution can be discriminated using the prototype device fabricated in 1- μm double-poly double-metal standard CMOS process. The detection limit was measured as 1.1 ng/μl with a dynamic range of 40 dB and the transient response time was measured less than 20 seconds.

Commercialisation of CMOS integrated circuit technology in multi-electrode arrays for neuroscience and cell-based biosensors.

PubMed

Graham, Anthony H D; Robbins, Jon; Bowen, Chris R; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

PubMed Central

Shokrani, Mohammad Reza; Hamidon, Mohd Nizar B.; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology. PMID:24782680

An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

PubMed

Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

2014-01-01

This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

Tunable nano-scale graphene-based devices in mid-infrared wavelengths composed of cylindrical resonators

NASA Astrophysics Data System (ADS)

Asgari, Somayyeh; Ghattan Kashani, Zahra; Granpayeh, Nosrat

2018-04-01

The performances of three optical devices including a refractive index sensor, a power splitter, and a 4-channel multi/demultiplexer based on graphene cylindrical resonators are proposed, analyzed, and simulated numerically by using the finite-difference time-domain method. The proposed sensor operates on the principle of the shift in resonance wavelength with a change in the refractive index of dielectric materials. The sensor sensitivity has been numerically derived. In addition, the performances of the power splitter and the multi/demultiplexer based on the variation of the resonance wavelengths of cylindrical resonator have been thoroughly investigated. The simulation results are in good agreement with the theoretical ones. Our studies demonstrate that the graphene based ultra-compact, nano-scale devices can be improved to be used as photonic integrated devices, optical switching, and logic gates.

Microactuateur electrothermique bistable: Etude d'implementation avec une technologie standard CMOS

NASA Astrophysics Data System (ADS)

Ressejac, Isabelle

The general objective of this Ph.D. thesis was to study the implementation of a new type of eletrothermal microactuator. This actuator presents the advantages to be bistable and fabricated in a standard CMOS process, allowing the integration of a microelectronics addressing circuit on the same substrate. Experimental research work, presented in this thesis, relate to the different steps carried out in order to implement this CMOS MEMS device: its theoretical conception, its fabrication with a standard CMOS technology, its micromachining as a post-process, its characterization and its electro-thermo-mechanical modeling. The device was designed and fabricated by using Mitel 1,5 mum CMOS technology and the Can-MEMS service which are both available via the Canadian Microelectronics Corporation. Fabricated monolithically within a standard CMOS process, our microactuator is suitable for large-scale integration due to its small dimensions (length ˜1000 mum and width ˜150 mum). It constitutes the basic component of a N by N matrix controlled by a microelectronic addressing system built on the same substrate. Initially, only one micromachining technique (involving TMAH) was used, and long etching times (>9 h) were requires} in order to release the microstructures. However, the passivation layer from the CMOS process could protect the underlying metal from the TMAH for a sufficient time (only ˜1--2 h). Consequently, we had to develop a micromachining strategy with shorter etching times to allow the complete release of the microstructures without damaging them. Post-processing begins with deposition (by sputtering) of a platinum layer intended to protect the abutment from subsequent etching. Our micromachining strategy is mainly based on the use of a hybrid etching process starting with a first anisotropic TMAH etching followed by a XeF2 isotropic etching. After micromachining, the released microactuator has a significant initial deflection with its tip reaching a height

Beyond detection: nuclear physics with a webcam in an educational setting

NASA Astrophysics Data System (ADS)

Pallone, Arthur

2015-03-01

Nuclear physics affects our daily lives in such diverse fields from medicine to art. I believe three obstacles - limited time, lack of subject familiarity and thus comfort on the part of educators, and equipment expense - must be overcome to produce a nuclear-educated populace. Educators regularly use webcams to actively engage students in scientific discovery as evidenced by a literature search for the term webcam paired with topics such as astronomy, biology, and physics. Inspired by YouTube videos that demonstrate alpha particle detection by modified webcams, I searched for examples that go beyond simple detection with only one education-oriented result - the determination of the in-air range of alphas using a modified CCD camera. Custom-built, radiation-hardened CMOS detectors exist in high energy physics and for soft x-ray detection. Commercial CMOS cameras are used for direct imaging in electron microscopy. I demonstrate charged-particle spectrometry with a slightly modified CMOS-based webcam. When used with inexpensive sources of radiation and free software, the webcam charged-particle spectrometer presents educators with a simple, low-cost technique to include nuclear physics in science education.

Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for AdvancedCMOS Devices

PubMed Central

Suzuki, Masamichi

2012-01-01

A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3) high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT) of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al) atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process. PMID:28817057

Electron-beam induced nano-etching of suspended graphene

PubMed Central

Sommer, Benedikt; Sonntag, Jens; Ganczarczyk, Arkadius; Braam, Daniel; Prinz, Günther; Lorke, Axel; Geller, Martin

2015-01-01

Besides its interesting physical properties, graphene as a two-dimensional lattice of carbon atoms promises to realize devices with exceptional electronic properties, where freely suspended graphene without contact to any substrate is the ultimate, truly two-dimensional system. The practical realization of nano-devices from suspended graphene, however, relies heavily on finding a structuring method which is minimally invasive. Here, we report on the first electron beam-induced nano-etching of suspended graphene and demonstrate high-resolution etching down to ~7 nm for line-cuts into the monolayer graphene. We investigate the structural quality of the etched graphene layer using two-dimensional (2D) Raman maps and demonstrate its high electronic quality in a nano-device: A 25 nm-wide suspended graphene nanoribbon (GNR) that shows a transport gap with a corresponding energy of ~60 meV. This is an important step towards fast and reliable patterning of suspended graphene for future ballistic transport, nano-electronic and nano-mechanical devices. PMID:25586495

Architecture design of resistor/FET-logic demultiplexer for hybrid CMOS/nanodevice circuit interconnect.

PubMed

Li, Shu; Zhang, Tong

2008-05-07

Hybrid nanoelectronics consisting of nanodevice crossbars on top of CMOS backplane circuits is emerging as one viable option to sustain Moore's law after the CMOS scaling limit is reached. One main design challenge in such hybrid nanoelectronics is the interface between the highly dense nanowires in nanodevice crossbars and relatively coarse microwires in the CMOS domain. Such an interface can be realized through a logic circuit called a demultiplexer (demux). In this context, all the prior work on demux design uses a single type of device, such as resistor, diode or field effect transistor (FET), to realize the demultiplexing function. However, different types of devices have their own advantages and disadvantages in terms of functionality, manufacturability, speed and power consumption. This makes none of them provide a satisfactory solution. To tackle this challenge, this work proposes to combine resistor with FET to implement the demux, leading to the hybrid resistor/FET-logic demux. Such hybrid demux architecture can make these two types of devices complement each other well to improve the overall demux design effectiveness. Furthermore, due to the inevitable fabrication process variations at the nanoscale, the effects of resistor conductance and FET threshold voltage variability are analyzed and evaluated based on computer simulations. The simulation results provide the requirement on the fabrication process to ensure a high demux reliability, and promise the hybrid resistor/FET-logic demux an improved addressability and process variance tolerance.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review.

PubMed

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J

2016-12-31

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

PubMed Central

Li, Haitao; Liu, Xiaowen; Li, Lin; Mu, Xiaoyi; Genov, Roman; Mason, Andrew J.

2016-01-01

Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS) instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design. PMID:28042860

CMOS-Compatible Fabrication for Photonic Crystal-Based Nanofluidic Structure.

PubMed

Peng, Wang; Chen, Youping; Ai, Wu; Zhang, Dailin; Song, Han; Xiong, Hui; Huang, Pengcheng

2017-12-01

Photonic crystal (PC)-based devices have been widely used since 1990s, while PC has just stepped into the research area of nanofluidic. In this paper, photonic crystal had been used as a complementary metal oxide semiconductors (CMOS) compatible part to create a nanofluidic structure. A nanofluidic structure prototype had been fabricated with CMOS-compatible techniques. The nanofluidic channels were sealed by direct bonding polydimethylsiloxane (PDMS) and the periodic gratings on photonic crystal structure. The PC was fabricated on a 4-in. Si wafer with Si 3 N 4 as the guided mode layer and SiO 2 film as substrate layer. The higher order mode resonance wavelength of PC-based nanofluidic structure had been selected, which can confine the enhanced electrical field located inside the nanochannel area. A design flow chart was used to guide the fabrication process. By optimizing the fabrication device parameters, the periodic grating of PC-based nanofluidic structure had a high-fidelity profile with fill factor at 0.5. The enhanced electric field was optimized and located within the channel area, and it can be used for PC-based nanofluidic applications with high performance.

A CMOS camera-based system for clinical photoplethysmographic applications

NASA Astrophysics Data System (ADS)

Humphreys, Kenneth; Markham, Charles; Ward, Tomas E.

2005-06-01

In this work an image-based photoplethysmography (PPG) system is developed and tested against a conventional finger-based system as commonly used in clinical practise. A PPG is essentially an optical instrument consisting of a near infrared (NIR) source and detector that is capable of tracking blood flow changes in body tissue. When used with a number of wavelengths in the NIR band blood oxygenation changes as well as other blood chemical signatures can be ascertained yielding a very useful device in the clinical realm. Conventionally such a device requires direct contact with the tissue under investigation which eliminates the possibility of its use for applications like wound management where the tissue oxygenation measurement could be extremely useful. To circumnavigate this shortcoming we have developed a CMOS camera-based system, which can successfully extract the PPG signal without contact with the tissue under investigation. A comparison of our results with conventional techniques has yielded excellent results.

Nano-Nucleation Characteristic of Cu-Ag Alloy Directly Electrodeposited on W Diffusion Barrier for Microelectronic Device Interconnect.

PubMed

Kim, Kang O; Kim, Sunjung

2016-05-01

Cu-Ag alloy interconnect is promising for ultra-large-scale integration (ULSI) microelectronic system of which device dimension keeps shrinking. In this study, seedless electrodeposition of Cu-Ag alloy directly on W diffusion barrier as interconnect technology is presented in respect of nano-nucleation control. Chemical equilibrium state of electrolyte was fundamentally investigated according to the pH of electrolyte because direct nano-nucleation of Cu-Ag alloy on W surface is challenging. Chelation behavior of Cu2+ and Ag+ ions with citrate (Cit) and ammonia ligands was dependent on the pH of electrolyte. The amount and kind of Cu- and Ag-based complexes determine the deposition rate, size, elemental composition, and surface morphology of Cu-Ag alloy nano-nuclei formed on W surface.

Monolithic integration of GMR sensors for standard CMOS-IC current sensing

NASA Astrophysics Data System (ADS)

De Marcellis, A.; Reig, C.; Cubells-Beltrán, M.-D.; Madrenas, J.; Santos, J. D.; Cardoso, S.; Freitas, P. P.

2017-09-01

In this work we report on the development of Giant Magnetoresistive (GMR) sensors for off-line current measurements in standard integrated circuits. An ASIC has been specifically designed and fabricated in the well-known AMS-0.35 μm CMOS technology, including the electronic circuitry for sensor interfacing. It implements an oscillating circuit performing a voltage-to-frequency conversion. Subsequently, a fully CMOS-compatible low temperature post-process has been applied for depositing the GMR sensing devices in a full-bridge configuration onto the buried current straps. Sensitivity and resolution of these sensors have been investigated achieving experimental results that show a detection sensitivity of about 100 Hz/mA, with a resolution of about 5 μA.

The prospects of transition metal dichalcogenides for ultimately scaled CMOS

NASA Astrophysics Data System (ADS)

Thiele, S.; Kinberger, W.; Granzner, R.; Fiori, G.; Schwierz, F.

2018-05-01

MOSFET gate length scaling has been a main source of progress in digital electronics for decades. Today, researchers still spend considerable efforts on reducing the gate length and on developing ultimately scaled MOSFETs, thereby exploring both new device architectures and alternative channel materials beyond Silicon such as two-dimensional TMDs (transition metal dichalcogenide). On the other hand, the envisaged scaling scenario for the next 15 years has undergone a significant change recently. While the 2013 ITRS edition required a continuation of aggressive gate length scaling for at least another 15 years, the 2015 edition of the ITRS suggests a deceleration and eventually a levelling off of gate length scaling and puts more emphasis on alternative options such as pitch scaling to keep Moore's Law alive. In the present paper, future CMOS scaling is discussed in the light of emerging two-dimensional MOSFET channel, in particular two-dimensional TMDs. To this end, the scaling scenarios of the 2013 and 2015 ITRS editions are considered and the scaling potential of TMD MOSFETs is investigated by means of quantum-mechanical device simulations. It is shown that for ultimately scaled MOSFETs as required in the 2013 ITRS, the heavy carrier effective masses of the Mo- and W-based TMDs are beneficial for the suppression of direct source-drain tunneling, while to meet the significantly relaxed scaling targets of the 2016 ITRS heavy-effective-mass channels are not needed.

Micro- and nano-scale optical devices for high density photonic integrated circuits at near-infrared wavelengths

NASA Astrophysics Data System (ADS)

Chatterjee, Rohit

In this research work, we explore fundamental silicon-based active and passive photonic devices that can be integrated together to form functional photonic integrated circuits. The devices which include power splitters, switches and lenses are studied starting from their physics, their design and fabrication techniques and finally from an experimental standpoint. The experimental results reveal high performance devices that are compatible with standard CMOS fabrication processes and can be easily integrated with other devices for near infrared telecom applications. In Chapter 2, a novel method for optical switching using nanomechanical proximity perturbation technique is described and demonstrated. The method which is experimentally demonstrated employs relatively low powers, small chip footprint and is compatible with standard CMOS fabrication processes. Further, in Chapter 3, this method is applied to develop a hitless bypass switch aimed at solving an important issue in current wavelength division multiplexing systems namely hitless switching of reconfigurable optical add drop multiplexers. Experimental results are presented to demonstrate the application of the nanomechanical proximity perturbation technique to practical situations. In Chapter 4, a fundamental photonic component namely the power splitter is described. Power splitters are important components for any photonic integrated circuits because they help split the power from a single light source to multiple devices on the same chip so that different operations can be performed simultaneously. The power splitters demonstrated in this chapter are based on multimode interference principles resulting in highly compact low loss and highly uniform power splitting to split the power of the light from a single channel to two and four channels. These devices can further be scaled to achieve higher order splitting such as 1x16 and 1x32 power splits. Finally in Chapter 5 we overcome challenges in device

Fabrication of arrayed Si nanowire-based nano-floating gate memory devices on flexible plastics.

PubMed

Yoon, Changjoon; Jeon, Youngin; Yun, Junggwon; Kim, Sangsig

2012-01-01

Arrayed Si nanowire (NW)-based nano-floating gate memory (NFGM) devices with Pt nanoparticles (NPs) embedded in Al2O3 gate layers are successfully constructed on flexible plastics by top-down approaches. Ten arrayed Si NW-based NFGM devices are positioned on the first level. Cross-linked poly-4-vinylphenol (PVP) layers are spin-coated on them as isolation layers between the first and second level, and another ten devices are stacked on the cross-linked PVP isolation layers. The electrical characteristics of the representative Si NW-based NFGM devices on the first and second levels exhibit threshold voltage shifts, indicating the trapping and detrapping of electrons in their NPs nodes. They have an average threshold voltage shift of 2.5 V with good retention times of more than 5 x 10(4) s. Moreover, most of the devices successfully retain their electrical characteristics after about one thousand bending cycles. These well-arrayed and stacked Si NW-based NFGM devices demonstrate the potential of nanowire-based devices for large-scale integration.

Design and image-quality performance of high resolution CMOS-based X-ray imaging detectors for digital mammography

NASA Astrophysics Data System (ADS)

Cha, B. K.; Kim, J. Y.; Kim, Y. J.; Yun, S.; Cho, G.; Kim, H. K.; Seo, C.-W.; Jeon, S.; Huh, Y.

2012-04-01

In digital X-ray imaging systems, X-ray imaging detectors based on scintillating screens with electronic devices such as charge-coupled devices (CCDs), thin-film transistors (TFT), complementary metal oxide semiconductor (CMOS) flat panel imagers have been introduced for general radiography, dental, mammography and non-destructive testing (NDT) applications. Recently, a large-area CMOS active-pixel sensor (APS) in combination with scintillation films has been widely used in a variety of digital X-ray imaging applications. We employed a scintillator-based CMOS APS image sensor for high-resolution mammography. In this work, both powder-type Gd2O2S:Tb and a columnar structured CsI:Tl scintillation screens with various thicknesses were fabricated and used as materials to convert X-ray into visible light. These scintillating screens were directly coupled to a CMOS flat panel imager with a 25 × 50 mm2 active area and a 48 μm pixel pitch for high spatial resolution acquisition. We used a W/Al mammographic X-ray source with a 30 kVp energy condition. The imaging characterization of the X-ray detector was measured and analyzed in terms of linearity in incident X-ray dose, modulation transfer function (MTF), noise-power spectrum (NPS) and detective quantum efficiency (DQE).

BiCMOS circuit technology for a 704 MHz ATM switch LSI

NASA Astrophysics Data System (ADS)

Ohtomo, Yusuke; Yasuda, Sadayuki; Togashi, Minoru; Ino, Masayuki; Tanabe, Yasuyuki; Inoue, Jun-Ichi; Nogawa, Masafumi; Hino, Shigeki

1994-05-01

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 micron BiCMOS technology. The LSI, composed of CMOS 15 K gate LOGIC, 8 Kb RAM, 1 Kb FIFO and ECL 1.6 K gate LOGIC, achieved an operation speed of 704-MHz with power dissipation of 7.2 W.

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

NASA Astrophysics Data System (ADS)

Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

1995-04-01

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

Design and implementation of a CMOS light pulse receiver cell array for spatial optical communications.

PubMed

Sarker, Md Shakowat Zaman; Itoh, Shinya; Hamai, Moeta; Takai, Isamu; Andoh, Michinori; Yasutomi, Keita; Kawahito, Shoji

2011-01-01

A CMOS light pulse receiver (LPR) cell for spatial optical communications is designed and evaluated by device simulations and a prototype chip implementation. The LPR cell consists of a pinned photodiode and four transistors. It works under sub-threshold region of a MOS transistor and the source terminal voltage which responds to the logarithm of the photo current are read out with a source follower circuit. For finding the position of the light spot on the focal plane, an image pixel array is embedded on the same plane of the LPR cell array. A prototype chip with 640 × 240 image pixels and 640 × 240 LPR cells is implemented with 0.18 μm CMOS technology. A proposed model of the transient response of the LPR cell agrees with the result of the device simulations and measurements. Both imaging at 60 fps and optical communication at the carrier frequency of 1 MHz are successfully performed. The measured signal amplitude and the calculation results of photocurrents show that the spatial optical communication up to 100 m is feasible using a 10 × 10 LED array.

1.05-GHz CMOS oscillator based on lateral- field-excited piezoelectric AlN contour- mode MEMS resonators.

PubMed

Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca

2010-01-01

This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contourmode resonators. The oscillator shows a phase noise level of -81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of -146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-microm complementary metaloxide- semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt 2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.

Portable design rules for bulk CMOS

NASA Technical Reports Server (NTRS)

Griswold, T. W.

1982-01-01

It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing

NASA Astrophysics Data System (ADS)

De Matteis, M.; De Blasi, M.; Vallicelli, E. A.; Zannoni, M.; Gervasi, M.; Bau, A.; Passerini, A.; Baschirotto, A.

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μ m technology (12 mm2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

A CMOS application-specified-integrated-circuit for 40 GHz high-electron-mobility-transistors automatic biasing.

PubMed

De Matteis, M; De Blasi, M; Vallicelli, E A; Zannoni, M; Gervasi, M; Bau, A; Passerini, A; Baschirotto, A

2017-02-01

This paper presents the design and the experimental results of a CMOS Automatic Control System (ACS) for the biasing of High-Electron-Mobility-Transistors (HEMT). The ACS is the first low-power mixed-signal Application-Specified-Integrated-Circuit (ASIC) able to automatically set and regulate the operating point of an off-chip 6 HEMT Low-Noise-Amplifiers (LNAs), hence it composes a two-chip system (the ACS+LNAs) to be used in the Large Scale Polarization Explorer (LSPE) stratospheric balloon for Cosmic Microwave Background (CMB) signal observation. The hereby presented ACS ASIC provides a reliable instrumentation for gradual and very stable LNAs characterization, switching-on, and operating point (<4 mV accuracy). Moreover, it simplifies the electronic instrumentation needed for biasing the LNAs, since it replaces several off-the-shelf and digital programmable device components. The ASIC prototype has been implemented in a CMOS 0.35 μm technology (12 mm 2 area occupancy). It operates at 4 kHz clock frequency. The power consumption of one-channel ASIC (biasing one LNA) is 3.6 mW, whereas 30 mW are consumed by a single LNA device.

Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

PubMed Central

Graham, Anthony H. D.; Robbins, Jon; Bowen, Chris R.; Taylor, John

2011-01-01

The adaptation of standard integrated circuit (IC) technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS) IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs) form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented. PMID:22163884

Development of a radiation-hard CMOS process

NASA Technical Reports Server (NTRS)

Power, W. L.

1983-01-01

It is recommended that various techniques be investigated which appear to have the potential for improving the radiation hardness of CMOS devices for prolonged space flight mission. The three key recommended processing techniques are: (1) making the gate oxide thin. It has been shown that radiation degradation is proportional to the cube of oxide thickness so that a relatively small reduction in thickness can greatly improve radiation resistance; (2) cleanliness and contamination control; and (3) to investigate different oxide growth (low temperature dry, TCE and HCL). All three produce high quality clean oxides, which are more radiation tolerant. Technique 2 addresses the reduction of metallic contamination. Technique 3 will produce a higher quality oxide by using slow growth rate conditions, and will minimize the effects of any residual sodium contamination through the introduction of hydrogen and chlorine into the oxide during growth.

Window-assisted nanosphere lithography for vacuum micro-nano-electronics

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Nannan; Institute of Electronic Engineering, Chinese Academy of Engineering Physics, Mianyang, 621900; Pang, Shucai

2015-04-15

Development of vacuum micro-nano-electronics is quite important for combining the advantages of vacuum tubes and solid-state devices but limited by the prevailing fabricating techniques which are expensive, time consuming and low-throughput. In this work, window-assisted nanosphere lithography (NSL) technique was proposed and enabled the low-cost and high-efficiency fabrication of nanostructures for vacuum micro-nano-electronic devices, thus allowing potential applications in many areas. As a demonstration, we fabricated high-density field emitter arrays which can be used as cold cathodes in vacuum micro-nano-electronic devices by using the window-assisted NSL technique. The details of the fabricating process have been investigated. This work provided amore » new and feasible idea for fabricating nanostructure arrays for vacuum micro-nano-electronic devices, which would spawn the development of vacuum micro-nano-electronics.« less

Fabrication and Electrical Characterization of Deep-Submicron Trench-Isolated CMOS Device Structures.

NASA Astrophysics Data System (ADS)

Perera, Asanga Hiran

effect of this resistance increase on a CMOS inverter switching speed was estimated. A first order empirical model to predict the series resistance was also formulated. Good correspondence was observed between results from the device simulator PISCES-2B and measured data for larger source-drain sizes.

Facile fabrication of efficient organic CMOS circuits.

PubMed

Dzwilewski, Andrzej; Matyba, Piotr; Edman, Ludvig

2010-01-14

Organic electronic circuits based on a combination of n- and p-type transistors (so-called CMOS circuits) are attractive, since they promise the realization of a manifold of versatile and low-cost electronic devices. Here, we report a novel photoinduced transformation method, which allows for a particularly straightforward fabrication of highly functional organic CMOS circuits. A solution-deposited single-layer film, comprising a mixture of the n-type semiconductor [6,6]-phenyl-C(61)-butyric acid methyl ester (PCBM) and the p-type semiconductor poly-3-hexylthiophene (P3HT) in a 3:1 mass ratio, was utilized as the common active material in an array of transistors. Selected film areas were exposed to laser light, with the result that the irradiated PCBM monomers were photochemically transformed into a low-solubility and high-mobility dimeric state. Thereafter, the entire film was developed via immersion into a developer solution, which selectively removed the nonexposed, and monomeric, PCBM component. The end result was that the transistors in the exposed film areas are n-type, as dimeric PCBM is the majority component in the active material, while the transistors in the nonexposed film areas are p-type, as P3HT is the sole remaining material. We demonstrate the merit of the method by utilizing the resulting combination of n-type and p-type transistors for the realization of CMOS inverters with a high gain of approximately 35.

Low mass MEMS/NEMS switch for a substitute of CMOS transistor using single-walled carbon nanotube thin film

NASA Astrophysics Data System (ADS)

Jang, Min-Woo

Power dissipation is a key factor for mobile devices and other low power applications. Complementary metal oxide semiconductor (CMOS) is the dominant integrated circuit (IC) technology responsible for a large part of this power dissipation. As the minimum feature size of CMOS devices enters into the sub 50 nanometer (nm) regime, power dissipation becomes much worse due to intrinsic physical limits. Many approaches have been studied to reduce power dissipation of deeply scaled CMOS ICs. One possible candidate is the electrostatic electromechanical switch, which could be fabricated with conventional CMOS processing techniques. They have critical advantages compared to CMOS devices such as almost zero standby leakage in the off-state due to the absence of a pn junction and a gate oxide, as well as excellent drive current in the on-state due to a metallic channel. Despite their excellent standby power dissipation, the electrostatic MEMS/NEMS switches have not been considered as a viable replacement for CMOS devices due to their large mechanical delay. Moreover, previous literature reveals that their pull-in voltage and switching speed are strongly proportional to each other. This reduces their potential advantage. However, in this work, we theoretically and experimentally demonstrated that the use of single-walled carbon nanotube (SWNT) with very low mass density and strong mechanical properties could provide a route to move off of the conventional trend with respect to the pull-in voltage / switching speed tradeoff observed in the literature. We fabricated 2-terminal fixed- beam switches with aligned composite SWNT thin films. In this work, layer-by-layer (LbL) self-assembly and dielectrophoresis were selected for aligned-composite SWNT thin film deposition. The dense membranes were successfully patterned to form submicron beams by e-beam lithography and oxygen plasma etching. Fixed-fixed beam switches using these membranes successfully operated with approximately 600

Design of a Nanoscale, CMOS-Integrable, Thermal-Guiding Structure for Boolean-Logic and Neuromorphic Computation.

PubMed

Loke, Desmond; Skelton, Jonathan M; Chong, Tow-Chong; Elliott, Stephen R

2016-12-21

One of the requirements for achieving faster CMOS electronics is to mitigate the unacceptably large chip areas required to steer heat away from or, more recently, toward the critical nodes of state-of-the-art devices. Thermal-guiding (TG) structures can efficiently direct heat by "meta-materials" engineering; however, some key aspects of the behavior of these systems are not fully understood. Here, we demonstrate control of the thermal-diffusion properties of TG structures by using nanometer-scale, CMOS-integrable, graphene-on-silica stacked materials through finite-element-methods simulations. It has been shown that it is possible to implement novel, controllable, thermally based Boolean-logic and spike-timing-dependent plasticity operations for advanced (neuromorphic) computing applications using such thermal-guide architectures.

Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

NASA Astrophysics Data System (ADS)

Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

2018-04-01

The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

PubMed

Hussain, Aftab M; Hussain, Muhammad M

2016-06-01

Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Fabricating a hybrid imaging device

NASA Technical Reports Server (NTRS)

Wadsworth, Mark (Inventor); Atlas, Gene (Inventor)

2003-01-01

A hybrid detector or imager includes two substrates fabricated under incompatible processes. An array of detectors, such as charged-coupled devices, are formed on the first substrate using a CCD fabrication process, such as a buried channel or peristaltic process. One or more charge-converting amplifiers are formed on a second substrate using a CMOS fabrication process. The two substrates are then bonded together to form a hybrid detector.

Design of a compact CMOS-compatible photonic antenna by topological optimization.

PubMed

Pita, Julián L; Aldaya, Ivan; Dainese, Paulo; Hernandez-Figueroa, Hugo E; Gabrielli, Lucas H

2018-02-05

Photonic antennas are critical in applications such as spectroscopy, photovoltaics, optical communications, holography, and sensors. In most of those applications, metallic antennas have been employed due to their reduced sizes. Nevertheless, compact metallic antennas suffer from high dissipative loss, wavelength-dependent radiation pattern, and they are difficult to integrate with CMOS technology. All-dielectric antennas have been proposed to overcome those disadvantages because, in contrast to metallic ones, they are CMOS-compatible, easier to integrate with typical silicon waveguides, and they generally present a broader wavelength range of operation. These advantages are achieved, however, at the expense of larger footprints that prevent dense integration and their use in massive phased arrays. In order to overcome this drawback, we employ topological optimization to design an all-dielectric compact antenna with vertical emission over a broad wavelength range. The fabricated device has a footprint of 1.78 µm × 1.78 µm and shows a shift in the direction of its main radiation lobe of only 4° over wavelengths ranging from 1470 nm to 1550 nm and a coupling efficiency bandwidth broader than 150 nm.

High Performance Transparent Transistor Memory Devices Using Nano-Floating Gate of Polymer/ZnO Nanocomposites

NASA Astrophysics Data System (ADS)

Shih, Chien-Chung; Lee, Wen-Ya; Chiu, Yu-Cheng; Hsu, Han-Wen; Chang, Hsuan-Chun; Liu, Cheng-Liang; Chen, Wen-Chang

2016-02-01

Nano-floating gate memory devices (NFGM) using metal nanoparticles (NPs) covered with an insulating polymer have been considered as a promising electronic device for the next-generation nonvolatile organic memory applications NPs. However, the transparency of the device with metal NPs is restricted to 60~70% due to the light absorption in the visible region caused by the surface plasmon resonance effects of metal NPs. To address this issue, we demonstrate a novel NFGM using the blends of hole-trapping poly (9-(4-vinylphenyl) carbazole) (PVPK) and electron-trapping ZnO NPs as the charge storage element. The memory devices exhibited a remarkably programmable memory window up to 60 V during the program/erase operations, which was attributed to the trapping/detrapping of charge carriers in ZnO NPs/PVPK composite. Furthermore, the devices showed the long-term retention time (>105 s) and WRER test (>200 cycles), indicating excellent electrical reliability and stability. Additionally, the fabricated transistor memory devices exhibited a relatively high transparency of 90% at the wavelength of 500 nm based on the spray-coated PEDOT:PSS as electrode, suggesting high potential for transparent organic electronic memory devices.

Subpixel mapping and test beam studies with a HV2FEI4v2 CMOS-Sensor-Hybrid Module for the ATLAS inner detector upgrade

NASA Astrophysics Data System (ADS)

Bisanz, T.; Große-Knetter, J.; Quadt, A.; Rieger, J.; Weingarten, J.

2017-08-01

The upgrade to the High Luminosity Large Hadron Collider will increase the instantaneous luminosity by more than a factor of 5, thus creating significant challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors since they allow for smaller pixel sizes and cost effective production. This article presents studies of a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer, forming a capacitively coupled pixel detector. The pixel pitch of the device under test is 33× 125 μm2, while the pixels of the read-out chip have a pitch of 50× 250 μm2. Three pixels of the CMOS device are connected to one read-out pixel, the information of which of these subpixels is hit is encoded in the amplitude of the output signal (subpixel encoding). Test beam measurements are presented that demonstrate the usability of this subpixel encoding scheme.

Azurin/CdSe-ZnS-Based Bio-Nano Hybrid Structure for Nanoscale Resistive Memory Device.

PubMed

Yagati, Ajay Kumar; Lee, Taek; Choi, Jeong-Woo

2017-07-15

In the present study, we propose a method for bio-nano hybrid formation by coupling a redox metalloprotein, Azurin, with CdSe-ZnS quantum dot for the development of a nanoscale resistive memory device. The covalent interaction between the two nanomaterials enables a strong and effective binding to form an azurin/CdSe-ZnS hybrid, and also enabled better controllability to couple with electrodes to examine the memory function properties. Morphological and optical properties were performed to confirm both hybrid formations and also their individual components. Current-Voltage (I-V) measurements on the hybrid nanostructures exhibited bistable current levels towards the memory function device, that and those characteristics were unnoticeable on individual nanomaterials. The hybrids showed good retention characteristics with high stability and durability, which is a promising feature for future nanoscale memory devices.

CMOS Rad-Hard Front-End Electronics for Precise Sensors Measurements

NASA Astrophysics Data System (ADS)

Sordo-Ibáñez, Samuel; Piñero-García, Blanca; Muñoz-Díaz, Manuel; Ragel-Morales, Antonio; Ceballos-Cáceres, Joaquín; Carranza-González, Luis; Espejo-Meana, Servando; Arias-Drake, Alberto; Ramos-Martos, Juan; Mora-Gutiérrez, José Miguel; Lagos-Florido, Miguel Angel

2016-08-01

This paper reports a single-chip solution for the implementation of radiation-tolerant CMOS front-end electronics (FEE) for applications requiring the acquisition of base-band sensor signals. The FEE has been designed in a 0.35μm CMOS process, and implements a set of parallel conversion channels with high levels of configurability to adapt the resolution, conversion rate, as well as the dynamic input range for the required application. Each conversion channel has been designed with a fully-differential implementation of a configurable-gain instrumentation amplifier, followed by an also configurable dual-slope ADC (DS ADC) up to 16 bits. The ASIC also incorporates precise thermal monitoring, sensor conditioning and error detection functionalities to ensure proper operation in extreme environments. Experimental results confirm that the proposed topologies, in conjunction with the applied radiation-hardening techniques, are reliable enough to be used without loss in the performance in environments with an extended temperature range (between -25 and 125 °C) and a total dose beyond 300 krad.

Advanced nano lithography via soft materials-derived and reversible nano-patterning methodology for molding of infrared nano lenses

NASA Astrophysics Data System (ADS)

Park, Jae Hong; Jang, Hyun Ik; Park, Jun Yong; Jeon, Seok Woo; Kim, Woo Choong; Kim, Hee Yeoun; Ahn, Chi Won

2015-03-01

The methodology suggested in this research provides the great possibility of creating nanostructures composed of various materials, such as soft polymer, hard polymer, and metal, as well as Si. Such nanostructures are required for a vast range of optical and display devices, photonic components, physical devices, energy devices including electrodes of secondary batteries, fuel cells, solar cells, and energy harvesters, biological devices including biochips, biomimetic or biosimilar structured devices, and mechanical devices including micro- or nano-scale sensors and actuators.

High-Performance Flexible Organic Nano-Floating Gate Memory Devices Functionalized with Cobalt Ferrite Nanoparticles.

PubMed

Jung, Ji Hyung; Kim, Sunghwan; Kim, Hyeonjung; Park, Jongnam; Oh, Joon Hak

2015-10-07

Nano-floating gate memory (NFGM) devices are transistor-type memory devices that use nanostructured materials as charge trap sites. They have recently attracted a great deal of attention due to their excellent performance, capability for multilevel programming, and suitability as platforms for integrated circuits. Herein, novel NFGM devices have been fabricated using semiconducting cobalt ferrite (CoFe2O4) nanoparticles (NPs) as charge trap sites and pentacene as a p-type semiconductor. Monodisperse CoFe2O4 NPs with different diameters have been synthesized by thermal decomposition and embedded in NFGM devices. The particle size effects on the memory performance have been investigated in terms of energy levels and particle-particle interactions. CoFe2O4 NP-based memory devices exhibit a large memory window (≈73.84 V), a high read current on/off ratio (read I(on)/I(off)) of ≈2.98 × 10(3), and excellent data retention. Fast switching behaviors are observed due to the exceptional charge trapping/release capability of CoFe2O4 NPs surrounded by the oleate layer, which acts as an alternative tunneling dielectric layer and simplifies the device fabrication process. Furthermore, the NFGM devices show excellent thermal stability, and flexible memory devices fabricated on plastic substrates exhibit remarkable mechanical and electrical stability. This study demonstrates a viable means of fabricating highly flexible, high-performance organic memory devices. © 2015 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Graphene nano-devices and nano-composites for structural, thermal and sensing applications

NASA Astrophysics Data System (ADS)

Yavari, Fazel

In this dissertation we have developed graphene-based nano-devices for applications in integrated circuits and gas sensors; as well as graphene-based nano-composites for applications in structures and thermal management. First, we have studied the bandgap of graphene for semiconductor applications. Graphene as a zero-bandgap material cannot be used in the semiconductor industry unless an effective method is developed to open the bandgap in this material. We have demonstrated that a bandgap of 0.206 eV can be opened in graphene by adsorption of water vapor molecules on its surface. Water molecules break the molecular symmetries of graphene resulting in a significant bandgap opening. We also illustrate that the lack of bandgap in graphene can be used to our advantage by making sensors that are able to detect low concentrations of gas molecules mixed in air. We have shown that 1-2 layers of graphene synthesized by chemical vapor deposition enables detection of trace amounts of NO 2 and NH3 in air at room temperature and atmospheric pressure. The gas species are detected by monitoring changes in electrical resistance of the graphene film due to gas adsorption. The sensor response time is inversely proportional to the gas concentration. Heating the film expels chemisorbed molecules from the graphene surface enabling reversible operation. The detection limits of ~100 parts-per-billion (ppb) for NO2 and ~500 ppb for NH3 obtained using this device are markedly superior to commercially available NO2 and NH3 detectors. This sensor is fabricated using individual graphene sheets that are exquisitely sensitive to the chemical environment. However, the fabrication and operation of devices that use individual nanostructures for sensing is complex, expensive and suffers from poor reliability due to contamination and large variability from sample-to-sample. To overcome these problems we have developed a gas sensor based on a porous 3D network of graphene sheets called graphene foam

Research-grade CMOS image sensors for demanding space applications

NASA Astrophysics Data System (ADS)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2004-06-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid-90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

Research-grade CMOS image sensors for demanding space applications

NASA Astrophysics Data System (ADS)

Saint-Pé, Olivier; Tulet, Michel; Davancens, Robert; Larnaudie, Franck; Magnan, Pierre; Corbière, Franck; Martin-Gonthier, Philippe; Belliot, Pierre

2017-11-01

Imaging detectors are key elements for optical instruments and sensors on board space missions dedicated to Earth observation (high resolution imaging, atmosphere spectroscopy...), Solar System exploration (micro cameras, guidance for autonomous vehicle...) and Universe observation (space telescope focal planes, guiding sensors...). This market has been dominated by CCD technology for long. Since the mid- 90s, CMOS Image Sensors (CIS) have been competing with CCDs for more and more consumer domains (webcams, cell phones, digital cameras...). Featuring significant advantages over CCD sensors for space applications (lower power consumption, smaller system size, better radiations behaviour...), CMOS technology is also expanding in this field, justifying specific R&D and development programs funded by national and European space agencies (mainly CNES, DGA, and ESA). All along the 90s and thanks to their increasingly improving performances, CIS have started to be successfully used for more and more demanding applications, from vision and control functions requiring low-level performances to guidance applications requiring medium-level performances. Recent technology improvements have made possible the manufacturing of research-grade CIS that are able to compete with CCDs in the high-performances arena. After an introduction outlining the growing interest of optical instruments designers for CMOS image sensors, this talk will present the existing and foreseen ways to reach high-level electro-optics performances for CIS. The developments of CIS prototypes built using an imaging CMOS process and of devices based on improved designs will be presented.

A safety monitoring system for taxi based on CMOS imager

NASA Astrophysics Data System (ADS)

Liu, Zhi

2005-01-01

CMOS image sensors now become increasingly competitive with respect to their CCD counterparts, while adding advantages such as no blooming, simpler driving requirements and the potential of on-chip integration of sensor, analogue circuitry, and digital processing functions. A safety monitoring system for taxi based on cmos imager that can record field situation when unusual circumstance happened is described in this paper. The monitoring system is based on a CMOS imager (OV7120), which can output digital image data through parallel pixel data port. The system consists of a CMOS image sensor, a large capacity NAND FLASH ROM, a USB interface chip and a micro controller (AT90S8515). The structure of whole system and the test data is discussed and analyzed in detail.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers.

PubMed

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-03-04

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications.

Dislocation-free Ge Nano-crystals via Pattern Independent Selective Ge Heteroepitaxy on Si Nano-Tip Wafers

PubMed Central

Niu, Gang; Capellini, Giovanni; Schubert, Markus Andreas; Niermann, Tore; Zaumseil, Peter; Katzer, Jens; Krause, Hans-Michael; Skibitzki, Oliver; Lehmann, Michael; Xie, Ya-Hong; von Känel, Hans; Schroeder, Thomas

2016-01-01

The integration of dislocation-free Ge nano-islands was realized via selective molecular beam epitaxy on Si nano-tip patterned substrates. The Si-tip wafers feature a rectangular array of nanometer sized Si tips with (001) facet exposed among a SiO2 matrix. These wafers were fabricated by complementary metal-oxide-semiconductor (CMOS) compatible nanotechnology. Calculations based on nucleation theory predict that the selective growth occurs close to thermodynamic equilibrium, where condensation of Ge adatoms on SiO2 is disfavored due to the extremely short re-evaporation time and diffusion length. The growth selectivity is ensured by the desorption-limited growth regime leading to the observed pattern independence, i.e. the absence of loading effect commonly encountered in chemical vapor deposition. The growth condition of high temperature and low deposition rate is responsible for the observed high crystalline quality of the Ge islands which is also associated with negligible Si-Ge intermixing owing to geometric hindrance by the Si nano-tip approach. Single island as well as area-averaged characterization methods demonstrate that Ge islands are dislocation-free and heteroepitaxial strain is fully relaxed. Such well-ordered high quality Ge islands present a step towards the achievement of materials suitable for optical applications. PMID:26940260

HF-Release of Sacrificial Layers in CMOS-integrated MOEMS structures

NASA Astrophysics Data System (ADS)

Döring, S.; Friedrichs, M.; Pufe, W.; Schulze, M.

2016-10-01

In this paper we will present details of the release process of SiO2 sacrificial layers we use within a multi-level MOEMS process developed by IPMS. Using such sacrificial layers gain a lot of benefits necessary for the production of high-end MOEMS devices like high surface quality and great surface planarity. However the HF-release of the sacrificial layer can be connected with specific issues. We present, which mechanisms are involved in the release process and how knowing them, can be the key for an optimized performance of the device. More-over we will present how to protect the CMOS backplane of our devices from unwanted HF attack during the release.

A multiscale simulation technique for molecular electronics: design of a directed self-assembled molecular n-bit shift register memory device.

PubMed

Lambropoulos, Nicholas A; Reimers, Jeffrey R; Crossley, Maxwell J; Hush, Noel S; Silverbrook, Kia

2013-12-20

A general method useful in molecular electronics design is developed that integrates modelling on the nano-scale (using quantum-chemical software) and on the micro-scale (using finite-element methods). It is applied to the design of an n-bit shift register memory that could conceivably be built using accessible technologies. To achieve this, the entire complex structure of the device would be built to atomic precision using feedback-controlled lithography to provide atomic-level control of silicon devices, controlled wet-chemical synthesis of molecular insulating pillars above the silicon, and controlled wet-chemical self-assembly of modular molecular devices to these pillars that connect to external metal electrodes (leads). The shift register consists of n connected cells that read data from an input electrode, pass it sequentially between the cells under the control of two external clock electrodes, and deliver it finally to an output device. The proposed cells are trimeric oligoporphyrin units whose internal states are manipulated to provide functionality, covalently connected to other cells via dipeptide linkages. Signals from the clock electrodes are conveyed by oligoporphyrin molecular wires, and μ-oxo porphyrin insulating columns are used as the supporting pillars. The developed multiscale modelling technique is applied to determine the characteristics of this molecular device, with in particular utilization of the inverted region for molecular electron-transfer processes shown to facilitate latching and control using exceptionally low energy costs per logic operation compared to standard CMOS shift register technology.

A multiscale simulation technique for molecular electronics: design of a directed self-assembled molecular n-bit shift register memory device

NASA Astrophysics Data System (ADS)

Lambropoulos, Nicholas A.; Reimers, Jeffrey R.; Crossley, Maxwell J.; Hush, Noel S.; Silverbrook, Kia

2013-12-01

A general method useful in molecular electronics design is developed that integrates modelling on the nano-scale (using quantum-chemical software) and on the micro-scale (using finite-element methods). It is applied to the design of an n-bit shift register memory that could conceivably be built using accessible technologies. To achieve this, the entire complex structure of the device would be built to atomic precision using feedback-controlled lithography to provide atomic-level control of silicon devices, controlled wet-chemical synthesis of molecular insulating pillars above the silicon, and controlled wet-chemical self-assembly of modular molecular devices to these pillars that connect to external metal electrodes (leads). The shift register consists of n connected cells that read data from an input electrode, pass it sequentially between the cells under the control of two external clock electrodes, and deliver it finally to an output device. The proposed cells are trimeric oligoporphyrin units whose internal states are manipulated to provide functionality, covalently connected to other cells via dipeptide linkages. Signals from the clock electrodes are conveyed by oligoporphyrin molecular wires, and μ-oxo porphyrin insulating columns are used as the supporting pillars. The developed multiscale modelling technique is applied to determine the characteristics of this molecular device, with in particular utilization of the inverted region for molecular electron-transfer processes shown to facilitate latching and control using exceptionally low energy costs per logic operation compared to standard CMOS shift register technology.

Design and function of molecular and bioelectronics devices.

PubMed

Krstic, Predrag; Forzani, Erica; Tao, Nongjian; Korkin, Anatoli

2007-10-24

from NGC2007. The NGC2007 meeting, which included two days of tutorials (Spring School) and a three day symposium, attracted approximately 400 participants from academic, industrial and governmental research institutions from 41 countries, and covered recent developments in the fabrication and functionality of nano-scale materials, devices and system architecture from advanced CMOS to molecular electronics, photonics, optoelectronics and magnetic materials and devices. The success of the conference would not have been possible without generous support from many sponsors and research institutions, especially from Arizona State University (conference host and co-organizer), International Science and Technology Center (ISTC), National Science Foundation (NSFT), Defense Advanced Research Agency (DARPA), Office of Naval Research, Army Research Office, Computational Chemistry List (CCL), Springer Publisher, City of Tempe, STMicroelectronics, Quarles & Brady LLP, Oak Ridge National Laboratory, Canadian Consulate in Phoenix, Salt River Project (SRP) and many other local, national and international and individual supporters. We would like to acknowledge the shared responsibility for this special issue of Nanotechnology on molecular and bioelectronics, and the highly professional support from Dr Nina Couzin, Dr Alex Wotherspoon and the Nanotechnology team from the IOP Publishing. We also acknowledge the exception made in allowing the publication of some material that is outside the normal scope of Nanotechnology.

Experimental evidence for a new single-event upset (SEU) mode in a CMOS SRAM obtained from model verification

NASA Technical Reports Server (NTRS)

Zoutendyk, J. A.; Smith, L. S.; Soli, G. A.; Lo, R. Y.

1987-01-01

Modeling of SEU has been done in a CMOS static RAM containing 1-micron-channel-length transistors fabricated from a p-well epilayer process using both circuit-simulation and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a novel SEU mode in an ON n-channel device is presented.

Advanced Simulation Technology to Design Etching Process on CMOS Devices

NASA Astrophysics Data System (ADS)

Kuboi, Nobuyuki

2015-09-01

Prediction and control of plasma-induced damage is needed to mass-produce high performance CMOS devices. In particular, side-wall (SW) etching with low damage is a key process for the next generation of MOSFETs and FinFETs. To predict and control the damage, we have developed a SiN etching simulation technique for CHxFy/Ar/O2 plasma processes using a three-dimensional (3D) voxel model. This model includes new concepts for the gas transportation in the pattern, detailed surface reactions on the SiN reactive layer divided into several thin slabs and C-F polymer layer dependent on the H/N ratio, and use of ``smart voxels''. We successfully predicted the etching properties such as the etch rate, polymer layer thickness, and selectivity for Si, SiO2, and SiN films along with process variations and demonstrated the 3D damage distribution time-dependently during SW etching on MOSFETs and FinFETs. We confirmed that a large amount of Si damage was caused in the source/drain region with the passage of time in spite of the existing SiO2 layer of 15 nm in the over etch step and the Si fin having been directly damaged by a large amount of high energy H during the removal step of the parasitic fin spacer leading to Si fin damage to a depth of 14 to 18 nm. By analyzing the results of these simulations and our previous simulations, we found that it is important to carefully control the dose of high energy H, incident energy of H, polymer layer thickness, and over-etch time considering the effects of the pattern structure, chamber-wall condition, and wafer open area ratio. In collaboration with Masanaga Fukasawa and Tetsuya Tatsumi, Sony Corporation. We thank Mr. T. Shigetoshi and Mr. T. Kinoshita of Sony Corporation for their assistance with the experiments.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics.

PubMed

Wei, Liping; Yan, Wenrong; Ho, Derek

2017-12-04

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices.

Recent Advances in Fluorescence Lifetime Analytical Microsystems: Contact Optics and CMOS Time-Resolved Electronics

PubMed Central

Yan, Wenrong; Ho, Derek

2017-01-01

Fluorescence spectroscopy has become a prominent research tool with wide applications in medical diagnostics and bio-imaging. However, the realization of combined high-performance, portable, and low-cost spectroscopic sensors still remains a challenge, which has limited the technique to the laboratories. A fluorescence lifetime measurement seeks to obtain the characteristic lifetime from the fluorescence decay profile. Time-correlated single photon counting (TCSPC) and time-gated techniques are two key variations of time-resolved measurements. However, commercial time-resolved analysis systems typically contain complex optics and discrete electronic components, which lead to bulkiness and a high cost. These two limitations can be significantly mitigated using contact sensing and complementary metal-oxide-semiconductor (CMOS) implementation. Contact sensing simplifies the optics, whereas CMOS technology enables on-chip, arrayed detection and signal processing, significantly reducing size and power consumption. This paper examines recent advances in contact sensing and CMOS time-resolved circuits for the realization of fully integrated fluorescence lifetime measurement microsystems. The high level of performance from recently reported prototypes suggests that the CMOS-based contact sensing microsystems are emerging as sound technologies for application-specific, low-cost, and portable time-resolved diagnostic devices. PMID:29207568

Scaling laws for nanoFET sensors

NASA Astrophysics Data System (ADS)

Zhou, Fu-Shan; Wei, Qi-Huo

2008-01-01

The sensitive conductance change of semiconductor nanowires and carbon nanotubes in response to the binding of charged molecules provides a novel sensing modality which is generally denoted as nanoFET sensors. In this paper, we study the scaling laws of nanoplate FET sensors by simplifying nanoplates as random resistor networks with molecular receptors sitting on lattice sites. Nanowire/tube FETs are included as the limiting cases where the device width goes small. Computer simulations show that the field effect strength exerted by the binding molecules has significant impact on the scaling behaviors. When the field effect strength is small, nanoFETs have little size and shape dependence. In contrast, when the field effect strength becomes stronger, there exists a lower detection threshold for charge accumulation FETs and an upper detection threshold for charge depletion FET sensors. At these thresholds, the nanoFET devices undergo a transition between low and large sensitivities. These thresholds may set the detection limits of nanoFET sensors, while they could be eliminated by designing devices with very short source-drain distance and large width.

Recent trends in hardware security exploiting hybrid CMOS-resistive memory circuits

NASA Astrophysics Data System (ADS)

Sahay, Shubham; Suri, Manan

2017-12-01

This paper provides a comprehensive review and insight of recent trends in the field of random number generator (RNG) and physically unclonable function (PUF) circuits implemented using different types of emerging resistive non-volatile (NVM) memory devices. We present a detailed review of hybrid RNG/PUF implementations based on the use of (i) Spin-Transfer Torque (STT-MRAM), and (ii) metal-oxide based (OxRAM), NVM devices. Various approaches on Hybrid CMOS-NVM RNG/PUF circuits are considered, followed by a discussion on different nanoscale device phenomena. Certain nanoscale device phenomena (variability/stochasticity etc), which are otherwise undesirable for reliable memory and storage applications, form the basis for low power and highly scalable RNG/PUF circuits. Detailed qualitative comparison and benchmarking of all implementations is performed.

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

NASA Astrophysics Data System (ADS)

Goiffon, Vincent; Magnan, Pierre; Bernard, Frédéric; Rolland, Guy; Saint-Pé, Olivier; Huger, Nicolas; Corbière, Franck

2008-02-01

We present here a study on both CMOS sensors and elementary structures (photodiodes and in-pixel MOSFETs) manufactured in a deep submicron process dedicated to imaging. We designed a test chip made of one 128×128-3T-pixel array with 10 μm pitch and more than 120 isolated test structures including photodiodes and MOSFETs with various implants and different sizes. All these devices were exposed to ionizing radiation up to 100 krad and their responses were correlated to identify the CMOS sensor weaknesses. Characterizations in darkness and under illumination demonstrated that dark current increase is the major sensor degradation. Shallow trench isolation was identified to be responsible for this degradation as it increases the number of generation centers in photodiode depletion regions. Consequences on hardness assurance and hardening-by-design are discussed.

CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

NASA Astrophysics Data System (ADS)

Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

2015-12-01

Frequency reference and timing control devices are ubiquitous in electronic applications. There is at least one resonator required for each of this device. Currently electromechanical resonators such as crystal resonator, ceramic resonator are the ultimate choices. This tendency will probably keep going for many more years. However, current market demands for small size, low power consumption, cheap and reliable products, has divulged many limitations of this type of resonators. They cannot be integrated into standard CMOS (Complement metaloxide- semiconductor) IC (Integrated Circuit) due to material and fabrication process incompatibility. Currently, these devices are off-chip and they require external circuitries to interface with the ICs. This configuration significantly increases the overall size and cost of the entire electronic system. In addition, extra external connection, especially at high frequency, will potentially create negative impacts on the performance of the entire system due to signal degradation and parasitic effects. Furthermore, due to off-chip packaging nature, these devices are quite expensive, particularly for high frequency and high quality factor devices. To address these issues, researchers have been intensively studying on an alternative for type of resonator by utilizing the new emerging MEMS (Micro-electro-mechanical systems) technology. Recent progress in this field has demonstrated a MEMS resonator with resonant frequency of 2.97 GHz and quality factor (measured in vacuum) of 42900. Despite this great achievement, this prototype is still far from being fully integrated into CMOS system due to incompatibility in fabrication process and its high series motional impedance. On the other hand, fully integrated MEMS resonator had been demonstrated but at lower frequency and quality factor. We propose a design and fabrication process for a low cost, high frequency and a high quality MEMS resonator, which can be integrated into a standard

Optical biosensors: a revolution towards quantum nanoscale electronics device fabrication.

PubMed

Dey, D; Goswami, T