Two-dimensional molybdenum disulphide nanosheet-covered metal nanoparticle array as a floating gate in multi-functional flash memories

NASA Astrophysics Data System (ADS)

Han, Su-Ting; Zhou, Ye; Chen, Bo; Zhou, Li; Yan, Yan; Zhang, Hua; Roy, V. A. L.

2015-10-01

Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal NPs-MoS2 floating gate flash memories were further proven to be multi-bit memory storage devices possessing a 3-bit storage capability and a good retention capability up to 104 s. We anticipate that these findings would provide scientific insight for the development of novel memory devices utilizing an atomically thin two-dimensional lattice structure.Semiconducting two-dimensional materials appear to be excellent candidates for non-volatile memory applications. However, the limited controllability of charge trapping behaviors and the lack of multi-bit storage studies in two-dimensional based memory devices require further improvement for realistic applications. Here, we report a flash memory consisting of metal NPs-molybdenum disulphide (MoS2) as a floating gate by introducing a metal nanoparticle (NP) (Ag, Au, Pt) monolayer underneath the MoS2 nanosheets. Controlled charge trapping and long data retention have been achieved in a metal (Ag, Au, Pt) NPs-MoS2 floating gate flash memory. This controlled charge trapping is hypothesized to be attributed to band bending and a built-in electric field ξbi between the interface of the metal NPs and MoS2. The metal

Floating-Gate Manipulated Graphene-Black Phosphorus Heterojunction for Nonvolatile Ambipolar Schottky Junction Memories, Memory Inverter Circuits, and Logic Rectifiers.

PubMed

Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing

2017-10-11

The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.

Floating-gate memory based on an organic metal-insulator-semiconductor capacitor

NASA Astrophysics Data System (ADS)

William, S.; Mabrook, M. F.; Taylor, D. M.

2009-08-01

A floating gate memory element is described which incorporates an evaporated gold film embedded in the gate dielectric of a metal-insulator-semiconductor capacitor based on poly(3-hexylthiophene). On exceeding a critical amplitude in the voltage sweep, hysteresis is observed in the capacitance-voltage (C-V) and current-voltage (I-V) characteristics of the device. The anticlockwise hysteresis in C-V is consistent with strong electron trapping during the positive cycle but little hole trapping during the negative cycle. We argue that the clockwise hysteresis observed in the negative cycle of the I-V plot, arises from leakage of trapped holes through the underlying insulator to the control gate.

Nanocrystals embedded in hafnium dioxide-based dielectrics as charge storage nodes of nano-floating gate memory

NASA Astrophysics Data System (ADS)

Lee, Pui Fai

2007-12-01

Nanocrystals (NC) embedded in dielectrics have attracted a great deal of attention recently because they can potentially be applied in nonvolatile, high-speed, high-density and low-power memory devices. This device benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors. The nanocrystal materials suitable for such an application can be either metals or semiconductors. Recent studies have shown that high-k dielectrics, instead of SiO2 , for the tunneling layer in nanocrystal floating gate memory can improve the trade-off between data retention and program efficiency due to the unique band alignment of high-k dielectrics in the programming and retention modes. In this project, HfAlO has been selected as the high- k dielectric for the nanocrystal floating gate memory structure. The trilayer structure (HfAlO/Ge-NC/HfAlO) on Si was fabricated by PLD. Results revealed that relatively low substrate temperature and growth rate are favourable for the formation of smaller-size Ge nanocrystals. Effects of size/density of the Ge nanocrystal, the tunneling and control oxide layer thicknesses and the oxygen partial pressure during their growth on the charge storage and charge retention characteristics have also been studied. The island structure of the Ge nanocrystal suggests that the growth is based on the Volmer-Webber mode. The self-organized Ge nanocrystals so formed were uniform in size (5--20 nm diameter) and distribution with a density approaching 1012--1013cm-2. Flat-band voltage shift (DeltaVFB) of about 3.6 V and good retention property have been achieved. By varying aggregation distance, sputtering gas pressure and ionization power of the nanocluster source, nanoclusters of Ge with different sizes can be formed. The memory effect of the trilayer structure so formed with 10 nm Ge nanoclusters are manifested by the counter-clockwise hysteresis loop in the C-V curves and a maximum flat-band voltage

Single layer of Ge quantum dots in HfO2 for floating gate memory capacitors.

PubMed

Lepadatu, A M; Palade, C; Slav, A; Maraloiu, A V; Lazanu, S; Stoica, T; Logofatu, C; Teodorescu, V S; Ciurea, M L

2017-04-28

High performance trilayer memory capacitors with a floating gate of a single layer of Ge quantum dots (QDs) in HfO 2 were fabricated using magnetron sputtering followed by rapid thermal annealing (RTA). The layer sequence of the capacitors is gate HfO 2 /floating gate of single layer of Ge QDs in HfO 2 /tunnel HfO 2 /p-Si wafers. Both Ge and HfO 2 are nanostructured by RTA at moderate temperatures of 600-700 °C. By nanostructuring at 600 °C, the formation of a single layer of well separated Ge QDs with diameters of 2-3 nm at a density of 4-5 × 10 15 m -2 is achieved in the floating gate (intermediate layer). The Ge QDs inside the intermediate layer are arranged in a single layer and are separated from each other by HfO 2 nanocrystals (NCs) about 8 nm in diameter with a tetragonal/orthorhombic structure. The Ge QDs in the single layer are located at the crossing of the HfO 2 NCs boundaries. In the intermediate layer, besides Ge QDs, a part of the Ge atoms is segregated by RTA at the HfO 2 NCs boundaries, while another part of the Ge atoms is present inside the HfO 2 lattice stabilizing the tetragonal/orthorhombic structure. The fabricated capacitors show a memory window of 3.8 ± 0.5 V and a capacitance-time characteristic with 14% capacitance decay in the first 3000-4000 s followed by a very slow capacitance decrease extrapolated to 50% after 10 years. This high performance is mainly due to the floating gate of a single layer of well separated Ge QDs in HfO 2 , distanced from the Si substrate by the tunnel oxide layer with a precise thickness.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

NASA Astrophysics Data System (ADS)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Unified random access memory (URAM) by integration of a nanocrystal floating gate for nonvolatile memory and a partially depleted floating body for capacitorless 1T-DRAM

NASA Astrophysics Data System (ADS)

Ryu, Seong-Wan; Han, Jin-Woo; Kim, Chung-Jin; Kim, Sungho; Choi, Yang-Kyu

2009-03-01

This paper describes a unified memory (URAM) that utilizes a nanocrystal SOI MOSFET for multi-functional applications of both nonvolatile memory (NVM) and capacitorless 1T-DRAM. By using a discrete storage node (Ag nanocrystal) as the floating gate of the NVM, high defect immunity and 2-bit/cell operation were achieved. The embedded nanocrystal NVM also showed 1T-DRAM operation (program/erase time = 100 ns) characteristics, which were realized by storing holes in the floating body of the SOI MOSFET, without requiring an external capacitor. Three-bit/cell operation was accomplished for different applications - 2-bits for nonvolatility and 1-bit for fast operation.

P-channel differential multiple-time programmable memory cells by laterally coupled floating metal gate fin field-effect transistors

NASA Astrophysics Data System (ADS)

Wang, Tai-Min; Chien, Wei-Yu; Hsu, Chia-Ling; Lin, Chrong Jung; King, Ya-Chin

2018-04-01

In this paper, we present a new differential p-channel multiple-time programmable (MTP) memory cell that is fully compatible with advanced 16 nm CMOS fin field-effect transistors (FinFET) logic processes. This differential MTP cell stores complementary data in floating gates coupled by a slot contact structure, which make different read currents possible on a single cell. In nanoscale CMOS FinFET logic processes, the gate dielectric layer becomes too thin to retain charges inside floating gates for nonvolatile data storage. By using a differential architecture, the sensing window of the cell can be extended and maintained by an advanced blanket boost scheme. The charge retention problem in floating gate cells can be improved by periodic restoring lost charges when significant read window narrowing occurs. In addition to high programming efficiency, this p-channel MTP cells also exhibit good cycling endurance as well as disturbance immunity. The blanket boost scheme can remedy the charge loss problem under thin gate dielectrics.

Nanocrystal floating gate memory with solution-processed indium-zinc-tin-oxide channel and colloidal silver nanocrystals

NASA Astrophysics Data System (ADS)

Hu, Quanli; Ha, Sang-Hyub; Lee, Hyun Ho; Yoon, Tae-Sik

2011-12-01

A nanocrystal (NC) floating gate memory with solution-processed indium-zinc-tin-oxide (IZTO) channel and silver (Ag) NCs embedded in thin gate dielectric layer (SiO2(30 nm)/Al2O3(3 nm)) was fabricated. Both the IZTO channel and colloidal Ag NC layers were prepared by spin-coating and subsequent annealing, and dip-coating process, respectively. A threshold voltage shift up to ~0.9 V, corresponding to the electron density of 6.5 × 1011 cm-2, at gate pulsing <=10 V was achieved by the charging of high density NCs. These results present the successful non-volatile memory characteristics of an oxide-semiconductor transistor fabricated through solution processes.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

NASA Astrophysics Data System (ADS)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

Nonvolatile floating gate organic memory device based on pentacene/CdSe quantum dot heterojuction

NASA Astrophysics Data System (ADS)

Shin, Ik-Soo; Kim, Jung-Min; Jeun, Jun-Ho; Yoo, Seok-Hyun; Ge, Ziyi; Hong, Jong-In; Ho Bang, Jin; Kim, Yong-Sang

2012-04-01

An organic floating-gate memory device using CdSe quantum dots (QDs) as a charge-trapping element was fabricated. CdSe QDs were localized beneath a pentacene without any tunneling insulator, and the QD layer played a role as hole-trapping sites. The band bending formed at the junction between pentacene and QD layers inhibited back-injection of holes trapped in CdSe into pentacene, which appeared as a hysteretic capacitance-voltage response during the operation of the device. Nearly, 60% of trapped charge was sustained even after 104 s in programmed state, and this long retention time can be potentially useful in practical applications of non-volatile memory.

Floating gate memory with charge storage dots array formed by Dps protein modified with site-specific binding peptides

NASA Astrophysics Data System (ADS)

Kamitake, Hiroki; Uenuma, Mutsunori; Okamoto, Naofumi; Horita, Masahiro; Ishikawa, Yasuaki; Yamashita, Ichro; Uraoka, Yukiharu

2015-05-01

We report a nanodot (ND) floating gate memory (NFGM) with a high-density ND array formed by a biological nano process. We utilized two kinds of cage-shaped proteins displaying SiO2 binding peptide (minTBP-1) on their outer surfaces: ferritin and Dps, which accommodate cobalt oxide NDs in their cavities. The diameters of the cobalt NDs were regulated by the cavity sizes of the proteins. Because minTBP-1 is strongly adsorbed on the SiO2 surface, high-density cobalt oxide ND arrays were obtained by a simple spin coating process. The densities of cobalt oxide ND arrays based on ferritin and Dps were 6.8 × 1011 dots cm-2 and 1.2 × 1012 dots cm-2, respectively. After selective protein elimination and embedding in a metal-oxide-semiconductor (MOS) capacitor, the charge capacities of both ND arrays were evaluated by measuring their C-V characteristics. The MOS capacitor embedded with the Dps ND array showed a wider memory window than the device embedded with the ferritin ND array. Finally, we fabricated an NFGM with a high-density ND array based on Dps, and confirmed its competent writing/erasing characteristics and long retention time.

Numerical model of a single nanocrystal devoted to the study of disordered nanocrystal floating gates of new flash memories

NASA Astrophysics Data System (ADS)

Leroy, Yann; Armeanu, Dumitru; Cordan, Anne-Sophie

2011-05-01

The improvement of our model concerning a single nanocrystal that belongs to a nanocrystal floating gate of a flash memory is presented. In order to extend the gate voltage range applicability of the model, the 3D continuum of states of either metallic or semiconducting electrodes is discretized into 2D subbands. Such an approach gives precise information about the mechanisms behind the charging or release processes of the nanocrystal. Then, the self-energy and screening effects of an electron within the nanocrystal are evaluated and introduced in the model. This enables a better determination of the operating point of the nanocrystal memory. The impact of those improvements on the charging or release time of the nanocrystal is discussed.

Stretchable carbon nanotube charge-trap floating-gate memory and logic devices for wearable electronics.

PubMed

Son, Donghee; Koo, Ja Hoon; Song, Jun-Kyul; Kim, Jaemin; Lee, Mincheol; Shim, Hyung Joon; Park, Minjoon; Lee, Minbaek; Kim, Ji Hoon; Kim, Dae-Hyeong

2015-05-26

Electronics for wearable applications require soft, flexible, and stretchable materials and designs to overcome the mechanical mismatch between the human body and devices. A key requirement for such wearable electronics is reliable operation with high performance and robustness during various deformations induced by motions. Here, we present materials and device design strategies for the core elements of wearable electronics, such as transistors, charge-trap floating-gate memory units, and various logic gates, with stretchable form factors. The use of semiconducting carbon nanotube networks designed for integration with charge traps and ultrathin dielectric layers meets the performance requirements as well as reliability, proven by detailed material and electrical characterizations using statistics. Serpentine interconnections and neutral mechanical plane layouts further enhance the deformability required for skin-based systems. Repetitive stretching tests and studies in mechanics corroborate the validity of the current approaches.

The floating-gate non-volatile semiconductor memory--from invention to the digital age.

PubMed

Sze, S M

2012-10-01

In the past 45 years (from 1967 to 2012), the non-volatile semiconductor memory (NVSM) has emerged from a floating-gate concept to the prime technology driver of the largest industry in the world-the electronics industry. In this paper, we briefly review the historical development of NVSM and project its future trends to the year 2020. In addition, we consider NVSM's wide-range of applications from the digital cellular phone to tablet computer to digital television. As the device dimension is scaled down to the deca-nanometer regime, we expect that many innovations will be made to meet the scaling challenges, and NVSM-inspired technology will continue to enrich and improve our lives for decades to come.

Push the flash floating gate memories toward the future low energy application

NASA Astrophysics Data System (ADS)

Della Marca, V.; Just, G.; Regnier, A.; Ogier, J.-L.; Simola, R.; Niel, S.; Postel-Pellerin, J.; Lalande, F.; Masoero, L.; Molas, G.

2013-01-01

In this paper the energy consumption of flash floating gate cell, during a channel hot electron operation, is investigated. We characterize the device using different ramp and box pulses on control gate, to find the best solution to have low energy consumption and good cell performances. We use a new dynamic method to measure the drain current absorption in order to evaluate the impact of different bias conditions, and to study the cell behavior. The programming window and the energy consumption are considered as fundamental parameters. Using this dynamic technique, three zones of work are found; it is possible to optimize the drain voltage during the programming operation to minimize the energy consumption. Moreover, the cell's performances are improved using the CHISEL effect, with a reverse body bias. After the study concerning the programming pulses adjusting, we show the results obtained by increasing the channel doping dose parameter. Considering a channel hot electron programming operation, it is important to focus our attention on the bitline leakage consumption contribution. We measured it for the unselected bitline cells, and we show the effects of the lightly doped drain implantation energy on the leakage current. In this way the impact of gate induced drain leakage in band-to-band tunneling regime decreases, improving the cell's performances in a memory array.

Suppressing the memory state of floating gate transistors with repeated femtosecond laser backside irradiations

NASA Astrophysics Data System (ADS)

Chambonneau, Maxime; Souiki-Figuigui, Sarra; Chiquet, Philippe; Della Marca, Vincenzo; Postel-Pellerin, Jérémy; Canet, Pierre; Portal, Jean-Michel; Grojo, David

2017-04-01

We demonstrate that infrared femtosecond laser pulses with intensity above the two-photon ionization threshold of crystalline silicon induce charge transport through the tunnel oxide in floating gate Metal-Oxide-Semiconductor transistor devices. With repeated irradiations of Flash memory cells, we show how the laser-produced free-electrons naturally redistribute on both sides of the tunnel oxide until the electric field of the transistor is suppressed. This ability enables us to determine in a nondestructive, rapid and contactless way the flat band and the neutral threshold voltages of the tested device. The physical mechanisms including nonlinear ionization, quantum tunneling of free-carriers, and flattening of the band diagram are discussed for interpreting the experiments. The possibility to control the carriers in memory transistors with ultrashort pulses holds promises for fast and remote device analyses (reliability, security, and defectivity) and for considerable developments in the growing field of ultrafast microelectronics.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory

NASA Astrophysics Data System (ADS)

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-01

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Synergistic High Charge-Storage Capacity for Multi-level Flexible Organic Flash Memory.

PubMed

Kang, Minji; Khim, Dongyoon; Park, Won-Tae; Kim, Jihong; Kim, Juhwan; Noh, Yong-Young; Baeg, Kang-Jun; Kim, Dong-Yu

2015-07-23

Electret and organic floating-gate memories are next-generation flash storage mediums for printed organic complementary circuits. While each flash memory can be easily fabricated using solution processes on flexible plastic substrates, promising their potential for on-chip memory organization is limited by unreliable bit operation and high write loads. We here report that new architecture could improve the overall performance of organic memory, and especially meet high storage for multi-level operation. Our concept depends on synergistic effect of electrical characterization in combination with a polymer electret (poly(2-vinyl naphthalene) (PVN)) and metal nanoparticles (Copper). It is distinguished from mostly organic nano-floating-gate memories by using the electret dielectric instead of general tunneling dielectric for additional charge storage. The uniform stacking of organic layers including various dielectrics and poly(3-hexylthiophene) (P3HT) as an organic semiconductor, followed by thin-film coating using orthogonal solvents, greatly improve device precision despite easy and fast manufacture. Poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] as high-k blocking dielectric also allows reduction of programming voltage. The reported synergistic organic memory devices represent low power consumption, high cycle endurance, high thermal stability and suitable retention time, compared to electret and organic nano-floating-gate memory devices.

Thermal Stress Analysis of Floating-Gate Tunneling Oxide Electrically Erasable Programmable Read Only Memory During Manufacturing Process

NASA Astrophysics Data System (ADS)

Zong, Xiang-fu; Wang, Xu; Weng, Yu-min; Yan, Ren-jin; Tang, Guo-an; Zhang, Zhao-qiang

1998-10-01

In this study, finite element modeling was used to evaluate the residual thermal stress in floating-gate tunneling oxide electrically erasable programmable read only memory (FLOTOX E2 PROMs) manufacturing process. Special attention is paid to the tunnel oxide region, in which high field electron injection is the basis to E2 PROMs operation. Calculated results show the presence of large stresses and stress gradients at the fringe. This may contribute to the invalidation of E2 PROMs. A possible failure mechanism of E2 PROM related to residual thermal stress-induced leakage is proposed.

Upsets in Erased Floating Gate Cells With High-Energy Protons

DOE PAGES

Gerardin, S.; Bagatin, M.; Paccagnella, A.; ...

2017-01-01

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

Endurance degradation and lifetime model of p-channel floating gate flash memory device with 2T structure

NASA Astrophysics Data System (ADS)

Wei, Jiaxing; Liu, Siyang; Liu, Xiaoqiang; Sun, Weifeng; Liu, Yuwei; Liu, Xiaohong; Hou, Bo

2017-08-01

The endurance degradation mechanisms of p-channel floating gate flash memory device with two-transistor (2T) structure are investigated in detail in this work. With the help of charge pumping (CP) measurements and Sentaurus TCAD simulations, the damages in the drain overlap region along the tunnel oxide interface caused by band-to-band (BTB) tunneling programming and the damages in the channel region resulted from Fowler-Nordheim (FN) tunneling erasure are verified respectively. Furthermore, the lifetime model of endurance characteristic is extracted, which can extrapolate the endurance degradation tendency and predict the lifetime of the device.

MemFlash device: floating gate transistors as memristive devices for neuromorphic computing

NASA Astrophysics Data System (ADS)

Riggert, C.; Ziegler, M.; Schroeder, D.; Krautschneider, W. H.; Kohlstedt, H.

2014-10-01

Memristive devices are promising candidates for future non-volatile memory applications and mixed-signal circuits. In the field of neuromorphic engineering these devices are especially interesting to emulate neuronal functionality. Therefore, new materials and material combinations are currently investigated, which are often not compatible with Si-technology processes. The underlying mechanisms of the device often remain unclear and are paired with low device endurance and yield. These facts define the current most challenging development tasks towards a reliable memristive device technology. In this respect, the MemFlash concept is of particular interest. A MemFlash device results from a diode configuration wiring scheme of a floating gate transistor, which enables the persistent device resistance to be varied according to the history of the charge flow through the device. In this study, we investigate the scaling conditions of the floating gate oxide thickness with respect to possible applications in the field of neuromorphic engineering. We show that MemFlash cells exhibit essential features with respect to neuromorphic applications. In particular, cells with thin floating gate oxides show a limited synaptic weight growth together with low energy dissipation. MemFlash cells present an attractive alternative for state-of-art memresitive devices. The emulation of associative learning is discussed by implementing a single MemFlash cell in an analogue circuit.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

A Method for Estimating the Probability of Floating Gate Prompt Charge Loss in a Radiation Environment

NASA Technical Reports Server (NTRS)

Edmonds, L. D.

2016-01-01

Because advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

NASA Astrophysics Data System (ADS)

Chiu, Shengfen; Xu, Yue; Ji, Xiaoli; Yan, Feng

2016-12-01

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65 nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.

Effect with high density nano dot type storage layer structure on 20 nm planar NAND flash memory characteristics

NASA Astrophysics Data System (ADS)

Sasaki, Takeshi; Muraguchi, Masakazu; Seo, Moon-Sik; Park, Sung-kye; Endoh, Tetsuo

2014-01-01

The merits, concerns and design principle for the future nano dot (ND) type NAND flash memory cell are clarified, by considering the effect of storage layer structure on NAND flash memory characteristics. The characteristics of the ND cell for a NAND flash memory in comparison with the floating gate type (FG) is comprehensively studied through the read, erase, program operation, and the cell to cell interference with device simulation. Although the degradation of the read throughput (0.7% reduction of the cell current) and slower program time (26% smaller programmed threshold voltage shift) with high density (10 × 1012 cm-2) ND NAND are still concerned, the suppress of the cell to cell interference with high density (10 × 1012 cm-2) plays the most important part for scaling and multi-level cell (MLC) operation in comparison with the FG NAND. From these results, the design knowledge is shown to require the control of the number of nano dots rather than the higher nano dot density, from the viewpoint of increasing its memory capacity by MLC operation and suppressing threshold voltage variability caused by the number of dots in the storage layer. Moreover, in order to increase its memory capacity, it is shown the tunnel oxide thickness with ND should be designed thicker (>3 nm) than conventional designed ND cell for programming/erasing with direct tunneling mechanism.

Floating Gate CMOS Dosimeter With Frequency Output

NASA Astrophysics Data System (ADS)

Garcia-Moreno, E.; Isern, E.; Roca, M.; Picos, R.; Font, J.; Cesari, J.; Pineda, A.

2012-04-01

This paper presents a gamma radiation dosimeter based on a floating gate sensor. The sensor is coupled with a signal processing circuitry, which furnishes a square wave output signal, the frequency of which depends on the total dose. Like any other floating gate dosimeter, it exhibits zero bias operation and reprogramming capabilities. The dosimeter has been designed in a standard 0.6 m CMOS technology. The whole dosimeter occupies a silicon area of 450 m250 m. The initial sensitivity to a radiation dose is Hz/rad, and to temperature and supply voltage is kHz/°C and 0.067 kHz/mV, respectively. The lowest detectable dose is less than 1 rad.

Floating gate transistors as biosensors (Conference Presentation)

NASA Astrophysics Data System (ADS)

Frisbie, C. Daniel

2016-11-01

Electrolyte gated transistors (EGTs) are a sub-class of thin film transistors that are extremely promising for biological sensing applications. These devices employ a solid electrolyte as the gate insulator; the very large capacitance of the electrolyte results in low voltage operation and high transconductance or gain. This talk will describe the fabrication of floating gate EGTs and their use as ricin sensors. The critical performance metrics for EGTs compared with other types of TFTs will also be reviewed.

Highly reliable top-gated thin-film transistor memory with semiconducting, tunneling, charge-trapping, and blocking layers all of flexible polymers.

PubMed

Wang, Wei; Hwang, Sun Kak; Kim, Kang Lib; Lee, Ju Han; Cho, Suk Man; Park, Cheolmin

2015-05-27

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Investing the effectiveness of retention performance in a non-volatile floating gate memory device with a core-shell structure of CdSe nanoparticles

NASA Astrophysics Data System (ADS)

Lee, Dong-Hoon; Kim, Jung-Min; Lim, Ki-Tae; Cho, Hyeong Jun; Bang, Jin Ho; Kim, Yong-Sang

2016-03-01

In this paper, we empirically investigate the retention performance of organic non-volatile floating gate memory devices with CdSe nanoparticles (NPs) as charge trapping elements. Core-structured CdSe NPs or core-shell-structured ZnS/CdSe NPs were mixed in PMMA and their performance in pentacene based device was compared. The NPs and self-organized thin tunneling PMMA inside the devices exhibited hysteresis by trapping hole during capacitance-voltage characterization. Despite of core-structured NPs showing a larger memory window, the retention time was too short to be adopted by an industry. By contrast core-shell structured NPs showed an improved retention time of >10000 seconds than core-structure NCs. Based on these results and the energy band structure, we propose the retention mechanism of each NPs. This investigation of retention performance provides a comparative and systematic study of the charging/discharging behaviors of NPs based memory devices. [Figure not available: see fulltext.

Impact of high-κ dielectric and metal nanoparticles in simultaneous enhancement of programming speed and retention time of nano-flash memory

NASA Astrophysics Data System (ADS)

Pavel, Akeed A.; Khan, Mehjabeen A.; Kirawanich, Phumin; Islam, N. E.

2008-10-01

A methodology to simulate memory structures with metal nanocrystal islands embedded as floating gate in a high-κ dielectric material for simultaneous enhancement of programming speed and retention time is presented. The computational concept is based on a model for charge transport in nano-scaled structures presented earlier, where quantum mechanical tunneling is defined through the wave impedance that is analogous to the transmission line theory. The effects of substrate-tunnel dielectric conduction band offset and metal work function on the tunneling current that determines the programming speed and retention time is demonstrated. Simulation results confirm that a high-κ dielectric material can increase programming current due to its lower conduction band offset with the substrate and also can be effectively integrated with suitable embedded metal nanocrystals having high work function for efficient data retention. A nano-memory cell designed with silver (Ag) nanocrystals embedded in Al 2O 3 has been compared with similar structure consisting of Si nanocrystals in SiO 2 to validate the concept.

Anomalous annealing of floating gate errors due to heavy ion irradiation

NASA Astrophysics Data System (ADS)

Yin, Yanan; Liu, Jie; Sun, Youmei; Hou, Mingdong; Liu, Tianqi; Ye, Bing; Ji, Qinggang; Luo, Jie; Zhao, Peixiong

2018-03-01

Using the heavy ions provided by the Heavy Ion Research Facility in Lanzhou (HIRFL), the annealing of heavy-ion induced floating gate (FG) errors in 34 nm and 25 nm NAND Flash memories has been studied. The single event upset (SEU) cross section of FG and the evolution of the errors after irradiation depending on the ion linear energy transfer (LET) values, data pattern and feature size of the device are presented. Different rates of annealing for different ion LET and different pattern are observed in 34 nm and 25 nm memories. The variation of the percentage of different error patterns in 34 nm and 25 nm memories with annealing time shows that the annealing of FG errors induced by heavy-ion in memories will mainly take place in the cells directly hit under low LET ion exposure and other cells affected by heavy ions when the ion LET is higher. The influence of Multiple Cell Upsets (MCUs) on the annealing of FG errors is analyzed. MCUs with high error multiplicity which account for the majority of the errors can induce a large percentage of annealed errors.

A triple quantum dot based nano-electromechanical memory device

DOE Office of Scientific and Technical Information (OSTI.GOV)

Pozner, R.; Lifshitz, E.; Solid State Institute, Technion-Israel Institute of Technology, Haifa 32000

Colloidal quantum dots (CQDs) are free-standing nano-structures with chemically tunable electronic properties. This tunability offers intriguing possibilities for nano-electromechanical devices. In this work, we consider a nano-electromechanical nonvolatile memory (NVM) device incorporating a triple quantum dot (TQD) cluster. The device operation is based on a bias induced motion of a floating quantum dot (FQD) located between two bound quantum dots (BQDs). The mechanical motion is used for switching between two stable states, “ON” and “OFF” states, where ligand-mediated effective interdot forces between the BQDs and the FQD serve to hold the FQD in each stable position under zero bias. Consideringmore » realistic microscopic parameters, our quantum-classical theoretical treatment of the TQD reveals the characteristics of the NVM.« less

Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

NASA Astrophysics Data System (ADS)

Jayanti, Srikant

Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

Floating-Point Units and Algorithms for field-programmable gate arrays

DOE Office of Scientific and Technical Information (OSTI.GOV)

Underwood, Keith D.; Hemmert, K. Scott

2005-11-01

The software that we are attempting to copyright is a package of floating-point unit descriptions and example algorithm implementations using those units for use in FPGAs. The floating point units are best-in-class implementations of add, multiply, divide, and square root floating-point operations. The algorithm implementations are sample (not highly flexible) implementations of FFT, matrix multiply, matrix vector multiply, and dot product. Together, one could think of the collection as an implementation of parts of the BLAS library or something similar to the FFTW packages (without the flexibility) for FPGAs. Results from this work has been published multiple times and wemore » are working on a publication to discuss the techniques we use to implement the floating-point units, For some more background, FPGAS are programmable hardware. "Programs" for this hardware are typically created using a hardware description language (examples include Verilog, VHDL, and JHDL). Our floating-point unit descriptions are written in JHDL, which allows them to include placement constraints that make them highly optimized relative to some other implementations of floating-point units. Many vendors (Nallatech from the UK, SRC Computers in the US) have similar implementations, but our implementations seem to be somewhat higher performance. Our algorithm implementations are written in VHDL and models of the floating-point units are provided in VHDL as well. FPGA "programs" make multiple "calls" (hardware instantiations) to libraries of intellectual property (IP), such as the floating-point unit library described here. These programs are then compiled using a tool called a synthesizer (such as a tool from Synplicity, Inc.). The compiled file is a netlist of gates and flip-flops. This netlist is then mapped to a particular type of FPGA by a mapper and then a place- and-route tool. These tools assign the gates in the netlist to specific locations on the specific type of FPGA chip used

Floating Gate sensor for in-vivo dosimetry in radiation therapies. Design and first characterization.

NASA Astrophysics Data System (ADS)

Faigon, A.; Martinez Vazquez, I.; Carbonetto, S.; García Inza, M.; G

2017-01-01

A floating gate dosimeter was designed and fabricated in a standard CMOS technology. The design guides and characterization are presented. The characterization included the controlled charging by tunneling of the floating gate, and its discharging under irradiation while measuring the transistor drain current whose change is the measure of the absorbed dose. The resolution of the obtained device is close to 1 cGy satisfying the requirements for most radiation therapies dosimetry. Pending statistical proofs, the dosimeter is a potential candidate for wide in-vivo control of radiotherapy treatments.

CMOS Active-Pixel Image Sensor With Simple Floating Gates

NASA Technical Reports Server (NTRS)

Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.

1996-01-01

Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.

Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

NASA Astrophysics Data System (ADS)

Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

2010-07-01

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

Disturb-Free Three-Dimensional Vertical Floating Gate NAND with Separated-Sidewall Control Gate

NASA Astrophysics Data System (ADS)

Seo, Moon-Sik; Endoh, Tetsuo

2012-02-01

Recently, the three-dimensional (3D) vertical floating gate (FG) type NAND cell arrays with the sidewall control gate (SCG) structure are receiving attention to overcome the reliability issues of charge trap (CT) type 3D NAND. In order to achieve the multilevel cell (MLC) operation for lower bit cost in 3D NAND, it is important to eliminate reliability issues, such as the Vth distribution with interference and disturbance problems and Vth shift with retention issues. In this paper, we intensively investigated the disturbance problems of the 3D vertical FG type NAND cell with separated-sidewall control gate (S-SCG) structure for the reliable MLC operation. Above all, we successfully demonstrate the fully suppressed disturbance problems, such as indirect programming of the unselected cells, hot electron injection of the edge cells and direct influence to the neighboring passing cells, by using the S-SCG with 30 nm pillar size.

Solution-processed nanoparticle super-float-gated organic field-effect transistor as un-cooled ultraviolet and infrared photon counter.

PubMed

Yuan, Yongbo; Dong, Qingfeng; Yang, Bin; Guo, Fawen; Zhang, Qi; Han, Ming; Huang, Jinsong

2013-01-01

High sensitivity photodetectors in ultraviolet (UV) and infrared (IR) range have broad civilian and military applications. Here we report on an un-cooled solution-processed UV-IR photon counter based on modified organic field-effect transistors. This type of UV detectors have light absorbing zinc oxide nanoparticles (NPs) sandwiched between two gate dielectric layers as a floating gate. The photon-generated charges on the floating gate cause high resistance regions in the transistor channel and tune the source-drain output current. This "super-float-gating" mechanism enables very high sensitivity photodetectors with a minimum detectable ultraviolet light intensity of 2.6 photons/μm(2)s at room temperature as well as photon counting capability. Based on same mechansim, infrared photodetectors with lead sulfide NPs as light absorbing materials have also been demonstrated.

Experimental Study of Floating-Gate-Type Metal-Oxide-Semiconductor Capacitors with Nanosize Triangular Cross-Sectional Tunnel Areas for Low Operating Voltage Flash Memory Application

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Guo, Ruofeng; Kamei, Takahiro; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Hayashida, Tetsuro; Sakamoto, Kunihiro; Ogura, Atsushi; Masahara, Meishoku

2012-06-01

The floating-gate (FG)-type metal-oxide-semiconductor (MOS) capacitors with planar (planar-MOS) and three-dimensional (3D) nanosize triangular cross-sectional tunnel areas (3D-MOS) have successfully been fabricated by introducing rapid thermal oxidation (RTO) and postdeposition annealing (PDA), and their electrical characteristics between the control gate (CG) and FG have been systematically compared. It was experimentally found in both planar- and 3D-MOS capacitors that the uniform and higher breakdown voltages are obtained by introducing RTO owing to the high-quality thermal oxide formation on the surface and etched edge regions of the n+ polycrystalline silicon (poly-Si) FG, and the leakage current is highly suppressed after PDA owing to the improved quality of the tetraethylorthosilicate (TEOS) silicon dioxide (SiO2) between CG and FG. Moreover, a lower breakdown voltage between CG and FG was obtained in the fabricated 3D-MOS capacitors as compared with that of planar-MOS capacitors thanks to the enhanced local electric field at the tips of triangular tunnel areas. The developed nanosize triangular cross-sectional tunnel area is useful for the fabrication of low operating voltage flash memories.

Observation of ambipolar switching in a silver nanoparticle single-electron transistor with multiple molecular floating gates

NASA Astrophysics Data System (ADS)

Yamamoto, Makoto; Shinohara, Shuhei; Tamada, Kaoru; Ishii, Hisao; Noguchi, Yutaka

2016-03-01

Ambipolar switching behavior was observed in a silver nanoparticle (AgNP)-based single-electron transistor (SET) with tetra-tert-butyl copper phthalocyanine (ttbCuPc) as a molecular floating gate. Depending on the wavelength of the incident light, the stability diagram shifted to the negative and positive directions along the gate voltage axis. These results were explained by the photoinduced charging of ttbCuPc molecules in the vicinity of AgNPs. Moreover, multiple device states were induced by the light irradiation at a wavelength of 600 nm, suggesting that multiple ttbCuPc molecules individually worked as a floating gate.

Effects of floating gate structures on the two-dimensional electron gas density and electron mobility in AlGaN/AlN/GaN heterostructure field-effect transistors

NASA Astrophysics Data System (ADS)

Zhao, Jingtao; Zhao, Zhenguo; Chen, Zidong; Lin, Zhaojun; Xu, Fukai

2017-12-01

In this study, we have investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with floating gate structures using the measured capacitancevoltage (C-V) and current-voltage (I-V) characteristics. It is found that the two-dimensional electron gas (2DEG) density under the central gate cannot be changed by the floating gate structures. However, the floating gate structures can cause the strain variation in the barrier layer, which lead to the non-uniform distribution of the polarization charges, then induce a polarization Coulomb field and scatter the 2DEG. More floating gate structures and closer distance between the floating gates and the central gate will result in stronger scattering effect of the 2DEG.

Energy-band engineering for tunable memory characteristics through controlled doping of reduced graphene oxide.

PubMed

Han, Su-Ting; Zhou, Ye; Yang, Qing Dan; Zhou, Li; Huang, Long-Biao; Yan, Yan; Lee, Chun-Sing; Roy, Vellaisamy A L

2014-02-25

Tunable memory characteristics are used in multioperational mode circuits where memory cells with various functionalities are needed in one combined device. It is always a challenge to obtain control over threshold voltage for multimode operation. On this regard, we use a strategy of shifting the work function of reduced graphene oxide (rGO) in a controlled manner through doping gold chloride (AuCl3) and obtained a gradient increase of rGO work function. By inserting doped rGO as floating gate, a controlled threshold voltage (Vth) shift has been achieved in both p- and n-type low voltage flexible memory devices with large memory window (up to 4 times for p-type and 8 times for n-type memory devices) in comparison with pristine rGO floating gate memory devices. By proper energy band engineering, we demonstrated a flexible floating gate memory device with larger memory window and controlled threshold voltage shifts.

Blanket Gate Would Address Blocks Of Memory

NASA Technical Reports Server (NTRS)

Lambe, John; Moopenn, Alexander; Thakoor, Anilkumar P.

1988-01-01

Circuit-chip area used more efficiently. Proposed gate structure selectively allows and restricts access to blocks of memory in electronic neural-type network. By breaking memory into independent blocks, gate greatly simplifies problem of reading from and writing to memory. Since blocks not used simultaneously, share operational amplifiers that prompt and read information stored in memory cells. Fewer operational amplifiers needed, and chip area occupied reduced correspondingly. Cost per bit drops as result.

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

PubMed Central

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-01-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air–SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand. PMID:28649986

Rewritable ghost floating gates by tunnelling triboelectrification for two-dimensional electronics

NASA Astrophysics Data System (ADS)

Kim, Seongsu; Kim, Tae Yun; Lee, Kang Hyuck; Kim, Tae-Ho; Cimini, Francesco Arturo; Kim, Sung Kyun; Hinchet, Ronan; Kim, Sang-Woo; Falconi, Christian

2017-06-01

Gates can electrostatically control charges inside two-dimensional materials. However, integrating independent gates typically requires depositing and patterning suitable insulators and conductors. Moreover, after manufacturing, gates are unchangeable. Here we introduce tunnelling triboelectrification for localizing electric charges in very close proximity of two-dimensional materials. As representative materials, we use chemical vapour deposition graphene deposited on a SiO2/Si substrate. The triboelectric charges, generated by friction with a Pt-coated atomic force microscope tip and injected through defects, are trapped at the air-SiO2 interface underneath graphene and act as ghost floating gates. Tunnelling triboelectrification uniquely permits to create, modify and destroy p and n regions at will with the spatial resolution of atomic force microscopes. As a proof of concept, we draw rewritable p/n+ and p/p+ junctions with resolutions as small as 200 nm. Our results open the way to time-variant two-dimensional electronics where conductors, p and n regions can be defined on demand.

Design of a reversible single precision floating point subtractor.

PubMed

Anantha Lakshmi, Av; Sudha, Gf

2014-01-04

In recent years, Reversible logic has emerged as a major area of research due to its ability to reduce the power dissipation which is the main requirement in the low power digital circuit design. It has wide applications like low power CMOS design, Nano-technology, Digital signal processing, Communication, DNA computing and Optical computing. Floating-point operations are needed very frequently in nearly all computing disciplines, and studies have shown floating-point addition/subtraction to be the most used floating-point operation. However, few designs exist on efficient reversible BCD subtractors but no work on reversible floating point subtractor. In this paper, it is proposed to present an efficient reversible single precision floating-point subtractor. The proposed design requires reversible designs of an 8-bit and a 24-bit comparator unit, an 8-bit and a 24-bit subtractor, and a normalization unit. For normalization, a 24-bit Reversible Leading Zero Detector and a 24-bit reversible shift register is implemented to shift the mantissas. To realize a reversible 1-bit comparator, in this paper, two new 3x3 reversible gates are proposed The proposed reversible 1-bit comparator is better and optimized in terms of the number of reversible gates used, the number of transistor count and the number of garbage outputs. The proposed work is analysed in terms of number of reversible gates, garbage outputs, constant inputs and quantum costs. Using these modules, an efficient design of a reversible single precision floating point subtractor is proposed. Proposed circuits have been simulated using Modelsim and synthesized using Xilinx Virtex5vlx30tff665-3. The total on-chip power consumed by the proposed 32-bit reversible floating point subtractor is 0.410 W.

FLOAT OPERATED RADIAL GATE HOIST ASSEMBLY LIST OF PARTS ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

FLOAT OPERATED RADIAL GATE HOIST ASSEMBLY - LIST OF PARTS - BASE-CRANK. WASTEWAY NO. 1. WELLTON-MOHAWK CANAL - STA. 99+23.50. United States Department of the Interior, Bureau of Reclamation; Gila Project, Arizona, Wellton-Mohawk Division. Drawing No. 50-D-2511, dated May 3, 1949, Denver Colorado. Sheet 1 of 2 - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

Using a Floating-Gate MOS Transistor as a Transducer in a MEMS Gas Sensing System

PubMed Central

Barranca, Mario Alfredo Reyes; Mendoza-Acevedo, Salvador; Flores-Nava, Luis M.; Avila-García, Alejandro; Vazquez-Acosta, E. N.; Moreno-Cadenas, José Antonio; Casados-Cruz, Gaspar

2010-01-01

Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane. PMID:22163478

FLOAT OPERATED RADIAL GATE INSTALLATION. WASTEWAY NO. 1. WELLTONMOHAWK CANAL ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

FLOAT OPERATED RADIAL GATE INSTALLATION. WASTEWAY NO. 1. WELLTON-MOHAWK CANAL - STA. 99+23.50. United States Department of the Interior, Bureau of Reclamation; Gila Project, Arizona, Wellton-Mohawk Division. Drawing No. 50-D-2497, dated March 8, 1949, Denver Colorado. Sheet 1 of 7 - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

Cycle of charge carrier states with formation and extinction of a floating gate in an ambipolar tetracyanoquaterthienoquinoid-based field-effect transistor

NASA Astrophysics Data System (ADS)

Itoh, Takuro; Toyota, Taro; Higuchi, Hiroyuki; Matsushita, Michio M.; Suzuki, Kentaro; Sugawara, Tadashi

2017-03-01

A tetracyanoquaterthienoquinoid (TCT4Q)-based field effect transistor is characterized by the ambipolar transfer characteristics and the facile shift of the threshold voltage induced by the bias stress. The trapping and detrapping kinetics of charge carriers was investigated in detail by the temperature dependence of the decay of source-drain current (ISD). We found a repeatable formation of a molecular floating gate is derived from a 'charge carrier-and-gate' cycle comprising four stages, trapping of mobile carriers, formation of a floating gate, induction of oppositely charged mobile carriers, and recombination between mobile and trapped carriers to restore the initial state.

A fully on-chip fast-transient NMOS low dropout voltage regulator with quasi floating gate pass element

NASA Astrophysics Data System (ADS)

Wang, Han; Gou, Chao; Luo, Kai

2017-04-01

This paper presents a fully on-chip NMOS low-dropout regulator (LDO) for portable applications with quasi floating gate pass element and fast transient response. The quasi floating gate structure makes the gate of the NMOS transistor only periodically charged or refreshed by the charge pump, which allows the charge pump to be a small economical circuit with small silicon area. In addition, a variable reference circuit is introduced enlarging the dynamic range of error amplifier during load transient. The proposed LDO has been implemented in a 0.35 μm BCD process. From experimental results, the regulator can operate with a minimum dropout voltage of 250 mV at a maximum 1 A load and {I}{{Q}} of 395 μA. Under full-range load current step, the voltage undershoot and overshoot of the proposed LDO are reduced to 50 and 26 mV, respectively.

Low-voltage all-inorganic perovskite quantum dot transistor memory

NASA Astrophysics Data System (ADS)

Chen, Zhiliang; Zhang, Yating; Zhang, Heng; Yu, Yu; Song, Xiaoxian; Zhang, Haiting; Cao, Mingxuan; Che, Yongli; Jin, Lufan; Li, Yifan; Li, Qingyan; Dai, Haitao; Yang, Junbo; Yao, Jianquan

2018-05-01

An all-inorganic cesium lead halide quantum dot (QD) based Au nanoparticle (NP) floating-gate memory with a solution processed layer-by-layer method is demonstrated. Easy synthesis at room temperature and excellent stability make all-inorganic CsPbBr3 perovskite QDs suitable as a semiconductor layer in low voltage nonvolatile transistor memory. The bipolarity of QDs has both electrons and holes stored in the Au NP floating gate, resulting in bidirectional shifts of initial threshold voltage according to the applied programing and erasing pulses. Under low operation voltage (±5 V), the memory achieved a great memory window (˜2.4 V), long retention time (>105 s), and stable endurance properties after 200 cycles. So the proposed memory device based on CsPbBr3 perovskite QDs has a great potential in the flash memory market.

Quantum Dot Gate Three-State and Nonvolatile Memory Field-Effect Transistors Using a ZnS/ZnMgS/ZnS Heteroepitaxial Stack as a Tunnel Insulator on Silicon-on-Insulator Substrates

NASA Astrophysics Data System (ADS)

Suarez, Ernesto; Chan, Pik-Yiu; Lingalugari, Murali; Ayers, John E.; Heller, Evan; Jain, Faquir

2013-11-01

This paper describes the use of II-VI lattice-matched gate insulators in quantum dot gate three-state and flash nonvolatile memory structures. Using silicon-on-insulator wafers we have fabricated GeO x -cladded Ge quantum dot (QD) floating gate nonvolatile memory field-effect transistor devices using ZnS-Zn0.95Mg0.05S-ZnS tunneling layers. The II-VI heteroepitaxial stack is nearly lattice-matched and is grown using metalorganic chemical vapor deposition on a silicon channel. This stack reduces the interface state density, improving threshold voltage variation, particularly in sub-22-nm devices. Simulations using self-consistent solutions of the Poisson and Schrödinger equations show the transfer of charge to the QD layers in three-state as well as nonvolatile memory cells.

MEMORIAL WALK WITH MEMORIALS, TOWARD ENTRANCE GATE. VIEW TO WEST. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

MEMORIAL WALK WITH MEMORIALS, TOWARD ENTRANCE GATE. VIEW TO WEST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

X-band T/R switch with body-floating multi-gate PDSOI NMOS transistors

NASA Astrophysics Data System (ADS)

Park, Mingyo; Min, Byung-Wook

2018-03-01

This paper presents an X-band transmit/receive switch using multi-gate NMOS transistors in a silicon-on-insulator CMOS process. For low loss and high power handling capability, floating body multi-gate NMOS transistors are adopted instead of conventional stacked NMOS transistors, resulting in 53% reduction of transistor area. Comparing to the stacked NMOS transistors, the multi gate transistor shares the source and drain region between stacked transistors, resulting in reduced chip area and parasitics. The impedance between bodies of gates in multi-gate NMOS transistors is assumed to be very large during design and confirmed after measurement. The measured input 1 dB compression point is 34 dBm. The measured insertion losses of TX and RX modes are respectively 1.7 dB and 2.0 dB at 11 GHz, and the measured isolations of TX and RX modes are >27 dB and >20 dB in X-band, respectively. The chip size is 0.086 mm2 without pads, which is 25% smaller than the T/R switch with stacked transistors.

Oleyl group-functionalized insulating gate transistors for measuring extracellular pH of floating cells

NASA Astrophysics Data System (ADS)

Imaizumi, Yuki; Goda, Tatsuro; Toya, Yutaro; Matsumoto, Akira; Miyahara, Yuji

2016-01-01

The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we aimed to extend this system toward floating cells such as T lymphocytes for investigating complement activation and pharmacokinetics through alternations in the plasma membrane integrity. We functionalized the surface of tantalum oxide gate insulator of ISFET with oleyl-tethered phosphonic acid for interacting with the plasma membranes of floating cells without affecting the cell signaling. The surface modification was characterized by X-ray photoelectron spectroscopy and water contact angle measurements. The Nernst response of -37.8 mV/pH was obtained for the surface-modified ISFET at 37 °C. The oleyl group-functionalized gate insulator successfully captured Jurkat T cells in a fluidic condition without acute cytotoxicity. The system was able to record the time course of pH changes at the cells/ISFET interface during the process of instant addition and withdrawal of ammonium chloride. Further, the plasma membrane injury of floating cells after exposure by detergent Triton™ X-100 was successfully determined using the modified ISFET with enhanced sensitivity as compared with conventional hemolysis assays.

Oleyl group-functionalized insulating gate transistors for measuring extracellular pH of floating cells

PubMed Central

Imaizumi, Yuki; Goda, Tatsuro; Toya, Yutaro; Matsumoto, Akira; Miyahara, Yuji

2016-01-01

Abstract The extracellular ionic microenvironment has a close relationship to biological activities such as by cellular respiration, cancer development, and immune response. A system composed of ion-sensitive field-effect transistors (ISFET), cells, and program-controlled fluidics has enabled the acquisition of real-time information about the integrity of the cell membrane via pH measurement. Here we aimed to extend this system toward floating cells such as T lymphocytes for investigating complement activation and pharmacokinetics through alternations in the plasma membrane integrity. We functionalized the surface of tantalum oxide gate insulator of ISFET with oleyl-tethered phosphonic acid for interacting with the plasma membranes of floating cells without affecting the cell signaling. The surface modification was characterized by X-ray photoelectron spectroscopy and water contact angle measurements. The Nernst response of −37.8 mV/pH was obtained for the surface-modified ISFET at 37 °C. The oleyl group-functionalized gate insulator successfully captured Jurkat T cells in a fluidic condition without acute cytotoxicity. The system was able to record the time course of pH changes at the cells/ISFET interface during the process of instant addition and withdrawal of ammonium chloride. Further, the plasma membrane injury of floating cells after exposure by detergent Triton™ X-100 was successfully determined using the modified ISFET with enhanced sensitivity as compared with conventional hemolysis assays. PMID:27877886

Photoresponses in Gold Nanoparticle Single-Electron Transistors with Molecular Floating Gates

NASA Astrophysics Data System (ADS)

Noguchi, Yutaka; Yamamoto, Makoto; Ishii, Hisao; Ueda, Rieko; Terui, Toshifumi; Imazu, Keisuke; Tamada, Kaoru; Sakano, Takeshi; Matsuda, Kenji

2013-11-01

We have proposed a simple method of activating advanced functions in single-electron transistors (SETs) based on the specific properties of individual molecules. As a prototype, we fabricated a copper phthalocyanine (CuPc)-doped SET. The device consists of a gold-nanoparticle (GNP)-based SET doped with CuPc as a photoresponsive floating gate. In this paper, we report the details of the photoresponses of the CuPc-doped SET, such as conductance switching, sensitivity to the wavelength of the incident light, and multiple induced states.

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

NASA Astrophysics Data System (ADS)

Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

2009-08-01

This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

Models for Total-Dose Radiation Effects in Non-Volatile Memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Campbell, Philip Montgomery; Wix, Steven D.

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models andmore » compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.« less

A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

2001-01-01

Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

A fast and low-power microelectromechanical system-based non-volatile memory device

PubMed Central

Lee, Sang Wook; Park, Seung Joo; Campbell, Eleanor E. B.; Park, Yung Woo

2011-01-01

Several new generation memory devices have been developed to overcome the low performance of conventional silicon-based flash memory. In this study, we demonstrate a novel non-volatile memory design based on the electromechanical motion of a cantilever to provide fast charging and discharging of a floating-gate electrode. The operation is demonstrated by using an electromechanical metal cantilever to charge a floating gate that controls the charge transport through a carbon nanotube field-effect transistor. The set and reset currents are unchanged after more than 11 h constant operation. Over 500 repeated programming and erasing cycles were demonstrated under atmospheric conditions at room temperature without degradation. Multinary bit programming can be achieved by varying the voltage on the cantilever. The operation speed of the device is faster than a conventional flash memory and the power consumption is lower than other memory devices. PMID:21364559

Nano-cone resistive memory for ultralow power operation.

PubMed

Kim, Sungjun; Jung, Sunghun; Kim, Min-Hwi; Kim, Tae-Hyeon; Bang, Suhyun; Cho, Seongjae; Park, Byung-Gook

2017-03-24

SiN x -based nano-structure resistive memory is fabricated by fully silicon CMOS compatible process integration including particularly designed anisotropic etching for the construction of a nano-cone silicon bottom electrode (BE). Bipolar resistive switching characteristics have significantly reduced switching current and voltage and are demonstrated in a nano-cone BE structure, as compared with those in a flat BE one. We have verified by systematic device simulations that the main cause of reduction in the performance parameters is the high electric field being more effectively concentrated at the tip of the cone-shaped BE. The greatly improved nonlinearity of the nano-cone resistive memory cell will be beneficial in the ultra-high-density crossbar array.

N-Channel field-effect transistors with floating gates for extracellular recordings.

PubMed

Meyburg, Sven; Goryll, Michael; Moers, Jürgen; Ingebrandt, Sven; Böcker-Meffert, Simone; Lüth, Hans; Offenhäusser, Andreas

2006-01-15

A field-effect transistor (FET) for recording extracellular signals from electrogenic cells is presented. The so-called floating gate architecture combines a complementary metal oxide semiconductor (CMOS)-type n-channel transistor with an independent sensing area. This concept allows the transistor and sensing area to be optimised separately. The devices are robust and can be reused several times. The noise level of the devices was smaller than of comparable non-metallised gate FETs. In addition to the usual drift of FET devices, we observed a long-term drift that has to be controlled for future long-term measurements. The device performance for extracellular signal recording was tested using embryonic rat cardiac myocytes cultured on fibronectin-coated chips. The extracellular cell signals were recorded before and after the addition of the cardioactive isoproterenol. The signal shapes of the measured action potentials were comparable to the non-metallised gate FETs previously used in similar experiments. The fabrication of the devices involved the process steps of standard CMOS that were necessary to create n-channel transistors. The implementation of a complete CMOS process would facilitate the integration of the logical circuits necessary for signal pre-processing on a chip, which is a prerequisite for a greater number of sensor spots in future layouts.

Microdose Induced Data Loss on Floating Gate Memories

NASA Technical Reports Server (NTRS)

Guertin, Steven M.; Nguyen, Duc M.; Patterson, Jeffrey D.

2006-01-01

Heavy ion irradiation of flash memories shows loss of stored data. The fluence dependence is indicative of microdose effects. Other qualitative factors identifying the effect as microdose are discussed. The data is presented, and compared to statistical results of a microdose target-based model.

Multi-level Capacitive Memory Effect in Metal/Oxide/Floating-Schottky Junction

NASA Astrophysics Data System (ADS)

Choi, Gahyun; Jung, Sungchul; Yoon, Hoon Hahn; Jeon, Youngeun; Park*, Kibog

2015-03-01

A memory computing (memcomputing) system can store and process information at the same physical location simultaneously. The essential components of memcomputing are passive devices with memory functionality, such as memristor, memcapacitor, and meminductor. We report the realization of a Schottky contact memcapacitor compatible with the current Si CMOS technology. Our memcapacitor is formed by depositing a stack of metal and oxide thin films on top of a Schottky contact. Here, the metal electrode of the Schottky contact is floating. The working principle of our memcapacitor is based on the fact that the depletion width of the Schottky contact varies according to the amount of charge stored in the floating metal electrode. The voltage pulse applied across the Metal/Oxide/Floating-Schottky junction controls charge flow in the Schottky contact and determines the amount of charge stored eventually. It is demonstrated experimentally that our memcapacitor exhibits hysteresis behaviors in capacitance-voltage curves and possesses multiple capacitance values that are switchable by the applied voltage pulse. Supported by NRF in South Korea (2013R1A1A2007070).

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement.

PubMed

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates.

A wearable multiplexed silicon nonvolatile memory array using nanocrystal charge confinement

PubMed Central

Kim, Jaemin; Son, Donghee; Lee, Mincheol; Song, Changyeong; Song, Jun-Kyul; Koo, Ja Hoon; Lee, Dong Jun; Shim, Hyung Joon; Kim, Ji Hoon; Lee, Minbaek; Hyeon, Taeghwan; Kim, Dae-Hyeong

2016-01-01

Strategies for efficient charge confinement in nanocrystal floating gates to realize high-performance memory devices have been investigated intensively. However, few studies have reported nanoscale experimental validations of charge confinement in closely packed uniform nanocrystals and related device performance characterization. Furthermore, the system-level integration of the resulting devices with wearable silicon electronics has not yet been realized. We introduce a wearable, fully multiplexed silicon nonvolatile memory array with nanocrystal floating gates. The nanocrystal monolayer is assembled over a large area using the Langmuir-Blodgett method. Efficient particle-level charge confinement is verified with the modified atomic force microscopy technique. Uniform nanocrystal charge traps evidently improve the memory window margin and retention performance. Furthermore, the multiplexing of memory devices in conjunction with the amplification of sensor signals based on ultrathin silicon nanomembrane circuits in stretchable layouts enables wearable healthcare applications such as long-term data storage of monitored heart rates. PMID:26763827

3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate

NASA Astrophysics Data System (ADS)

Oh, Jae-Sub; Yang, Seong-Dong; Lee, Sang-Youl; Kim, Young-Su; Kang, Min-Ho; Lim, Sung-Kyu; Lee, Hi-Deok; Lee, Ga-Won

2013-08-01

In this paper, a gate-all-around bandgap-engineered silicon-oxide-nitride-oxide-silicon device with a vertical silicon pillar structure and a Ti metal gate are demonstrated for a potential solution to overcome the scaling-down of flash memory device. The devices were fabricated using CMOS-compatible technology and exhibited well-behaved memory characteristics in terms of the program/erase window, retention, and endurance properties. Moreover, the integration of the Ti metal gate demonstrated a significant improvement in the erase characteristics due to the efficient suppression of the electron back tunneling through the blocking oxide.

The GaN trench gate MOSFET with floating islands: High breakdown voltage and improved BFOM

NASA Astrophysics Data System (ADS)

Shen, Lingyan; Müller, Stephan; Cheng, Xinhong; Zhang, Dongliang; Zheng, Li; Xu, Dawei; Yu, Yuehui; Meissner, Elke; Erlbacher, Tobias

2018-02-01

A novel GaN trench gate (TG) MOSFET with P-type floating islands (FLI) in drift region, which can suppress the electric field peak at bottom of gate trench during the blocking state and prevent premature breakdown in gate oxide, is proposed and investigated by TCAD simulations. The influence of thickness, position, doping concentration and length of the FLI on breakdown voltage (BV) and specific on-resistance (Ron_sp) is studied, providing useful guidelines for design of this new type of device. Using optimized parameters for the FLI, GaN FLI TG-MOSFET obtains a BV as high as 2464 V with a Ron_sp of 3.0 mΩ cm2. Compared to the conventional GaN TG-MOSFET with the same structure parameters, the Baliga figure of merit (BFOM) is enhanced by 150%, getting closer to theoretical limit for GaN devices.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations.

PubMed

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-27

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Graphene-ferroelectric metadevices for nonvolatile memory and reconfigurable logic-gate operations

NASA Astrophysics Data System (ADS)

Kim, Woo Young; Kim, Hyeon-Don; Kim, Teun-Teun; Park, Hyun-Sung; Lee, Kanghee; Choi, Hyun Joo; Lee, Seung Hoon; Son, Jaehyeon; Park, Namkyoo; Min, Bumki

2016-01-01

Memory metamaterials are artificial media that sustain transformed electromagnetic properties without persistent external stimuli. Previous memory metamaterials were realized with phase-change materials, such as vanadium dioxide or chalcogenide glasses, which exhibit memory behaviour with respect to electrically/optically induced thermal stimuli. However, they require a thermally isolated environment for longer retention or strong optical pump for phase-change. Here we demonstrate electrically programmable nonvolatile memory metadevices realised by the hybridization of graphene, a ferroelectric and meta-atoms/meta-molecules, and extend the concept further to establish reconfigurable logic-gate metadevices. For a memory metadevice having a single electrical input, amplitude, phase and even the polarization multi-states were clearly distinguishable with a retention time of over 10 years at room temperature. Furthermore, logic-gate functionalities were demonstrated with reconfigurable logic-gate metadevices having two electrical inputs, with each connected to separate ferroelectric layers that act as the multi-level controller for the doping level of the sandwiched graphene layer.

Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

PubMed

Bae, Jong-Ho; Lee, Jong-Ho

2016-05-01

A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

Improved Reading Gate For Vertical-Bloch-Line Memory

NASA Technical Reports Server (NTRS)

Wu, Jiin-Chuan; Stadler, Henry L.; Katti, Romney R.

1994-01-01

Improved design for reading gate of vertical-Bloch-line magnetic-bubble memory increases reliability of discrimination between binary ones and zeros. Magnetic bubbles that signify binary "1" and "0" produced by applying sufficiently large chopping currents to memory stripes. Bubbles then propagated differentially in bubble sorter. Method of discriminating between ones and zeros more reliable.

Cobalt germanide nanostructure formation and memory characteristic enhancement in silicon oxide films

NASA Astrophysics Data System (ADS)

Joo, Beom Soo; Kim, Hyunseung; Jang, Seunghun; Han, Dongwoo; Han, Moonsup

2018-08-01

We investigated nano-floating gate memory having a charge trap layer (CTL) composed of cobalt germanide nanostructure (ns-CoGe). A tunneling oxide layer; a CTL containing Co, Ge, and Si; and a blocking oxide layer were sequentially deposited on a p-type silicon substrate by RF magnetron sputtering and low-pressure chemical vapor deposition. We optimized the CTL formation conditions by rapid thermal annealing at a somewhat low temperature (about 830 °C) by considering the differences in Gibbs free energy and chemical enthalpy among the components. To characterize the charge storage properties, capacitance-voltage (C-V) measurements were performed. Further, we used X-ray photoelectron spectroscopy for chemical analysis of the CTL. In this work, we not only report that the C-V measurement shows a remarkable opening of the memory window for the ns-CoGe compared with those of nanostructures composed of Co or Ge alone, but also clarify that the improvement in the memory characteristics originates in the nanostructure formation, which consists mainly of Co-Ge bonds. We expect ns-CoGe to be a strong candidate for fabrication of next-generation memory devices.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

NASA Astrophysics Data System (ADS)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

SONOS Nonvolatile Memory Cell Programming Characteristics

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory is gaining favor over conventional EEPROM FLASH memory technology. This paper characterizes the SONOS write operation using a nonquasi-static MOSFET model. This includes floating gate charge and voltage characteristics as well as tunneling current, voltage threshold and drain current characterization. The characterization of the SONOS memory cell predicted by the model closely agrees with experimental data obtained from actual SONOS memory cells. The tunnel current, drain current, threshold voltage and read drain current all closely agreed with empirical data.

Development of highly reliable static random access memory for 40-nm embedded split gate-MONOS flash memory

NASA Astrophysics Data System (ADS)

Okamoto, Shin-ichi; Maekawa, Kei-ichi; Kawashima, Yoshiyuki; Shiba, Kazutoshi; Sugiyama, Hideki; Inoue, Masao; Nishida, Akio

2015-04-01

High quality static random access memory (SRAM) for 40-nm embedded MONOS flash memory with split gate (SG-MONOS) was developed. Marginal failure, which results in threshold voltage/drain current tailing and outliers of SRAM transistors, occurs when using a conventional SRAM structure. These phenomena can be explained by not only gate depletion but also partial depletion and percolation path formation in the MOS channel. A stacked poly-Si gate structure can suppress these phenomena and achieve high quality SRAM without any defects in the 6σ level and with high affinity to the 40-nm SG-MONOS process was developed.

Experimental study of three-dimensional fin-channel charge trapping flash memories with titanium nitride and polycrystalline silicon gates

NASA Astrophysics Data System (ADS)

Liu, Yongxun; Matsukawa, Takashi; Endo, Kazuhiko; O'uchi, Shinichi; Tsukada, Junichi; Yamauchi, Hiromi; Ishikawa, Yuki; Mizubayashi, Wataru; Morita, Yukinori; Migita, Shinji; Ota, Hiroyuki; Masahara, Meishoku

2014-01-01

Three-dimensional (3D) fin-channel charge trapping (CT) flash memories with different gate materials of physical-vapor-deposited (PVD) titanium nitride (TiN) and n+-polycrystalline silicon (poly-Si) have successfully been fabricated by using (100)-oriented silicon-on-insulator (SOI) wafers and orientation-dependent wet etching. Electrical characteristics of the fabricated flash memories including statistical threshold voltage (Vt) variability, endurance, and data retention have been comparatively investigated. It was experimentally found that a larger memory window and a deeper erase are obtained in PVD-TiN-gated metal-oxide-nitride-oxide-silicon (MONOS)-type flash memories than in poly-Si-gated poly-Si-oxide-nitride-oxide-silicon (SONOS)-type memories. The larger memory window and deeper erase of MONOS-type flash memories are contributed by the higher work function of the PVD-TiN metal gate than of the n+-poly-Si gate, which is effective for suppressing electron back tunneling during erase operation. It was also found that the initial Vt roll-off due to the short-channel effect (SCE) is directly related to the memory window roll-off when the gate length (Lg) is scaled down to 46 nm or less.

Modeling of Sonos Memory Cell Erase Cycle

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Ho, Fat D.

2010-01-01

Silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile semiconductor memories (NVSMS) have many advantages. These memories are electrically erasable programmable read-only memories (EEPROMs). They utilize low programming voltages, endure extended erase/write cycles, are inherently resistant to radiation, and are compatible with high-density scaled CMOS for low power, portable electronics. The SONOS memory cell erase cycle was investigated using a nonquasi-static (NQS) MOSFET model. The SONOS floating gate charge and voltage, tunneling current, threshold voltage, and drain current were characterized during an erase cycle. Comparisons were made between the model predictions and experimental device data.

An attention-gating recurrent working memory architecture for emergent speech representation

NASA Astrophysics Data System (ADS)

Elshaw, Mark; Moore, Roger K.; Klein, Michael

2010-06-01

This paper describes an attention-gating recurrent self-organising map approach for emergent speech representation. Inspired by evidence from human cognitive processing, the architecture combines two main neural components. The first component, the attention-gating mechanism, uses actor-critic learning to perform selective attention towards speech. Through this selective attention approach, the attention-gating mechanism controls access to working memory processing. The second component, the recurrent self-organising map memory, develops a temporal-distributed representation of speech using phone-like structures. Representing speech in terms of phonetic features in an emergent self-organised fashion, according to research on child cognitive development, recreates the approach found in infants. Using this representational approach, in a fashion similar to infants, should improve the performance of automatic recognition systems through aiding speech segmentation and fast word learning.

Direct protein detection with a nano-interdigitated array gate MOSFET.

PubMed

Tang, Xiaohui; Jonas, Alain M; Nysten, Bernard; Demoustier-Champagne, Sophie; Blondeau, Franoise; Prévot, Pierre-Paul; Pampin, Rémi; Godfroid, Edmond; Iñiguez, Benjamin; Colinge, Jean-Pierre; Raskin, Jean-Pierre; Flandre, Denis; Bayot, Vincent

2009-08-15

A new protein sensor is demonstrated by replacing the gate of a metal oxide semiconductor field effect transistor (MOSFET) with a nano-interdigitated array (nIDA). The sensor is able to detect the binding reaction of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein at a concentration lower than 1 ng/ml. The sensor exhibits a high selectivity and reproducible specific detection. We provide a simple model that describes the behavior of the sensor and explains the origin of its high sensitivity. The simulated and experimental results indicate that the drain current of nIDA-gate MOSFET sensor is significantly increased with the successive binding of the thiol layer, Iris and anti-Iris protein layers. It is found that the sensor detection limit can be improved by well optimizing the geometrical parameters of nIDA-gate MOSFET. This nanobiosensor, with real-time and label-free capabilities, can easily be used for the detection of other proteins, DNA, virus and cancer markers. Moreover, an on-chip associated electronics nearby the sensor can be integrated since its fabrication is compatible with complementary metal oxide semiconductor (CMOS) technology.

A sub-microwatt piezo-floating-gate sensor for long-term fatigue monitoring in biomechanical implants.

PubMed

Lajnef, Nizar; Chakrabartty, Shantanu; Elvin, Niell; Elvin, Alex

2006-01-01

In this paper we describe an implementation of a novel fatigue monitoring sensor based on integration of piezoelectric transduction with floating gate avalanche injection. The miniaturized sensor enables continuous battery-less monitoring and time-to-failure predictions of biomechanical implants. Measured results from a fabricated prototype in a 0.5 microm CMOS process indicate that the device can compute cumulative statistics of electrical signals generated by piezoelectric transducer, while consuming less that 1 microW of power. The ultra-low power operation makes the sensor attractive for integration with poly-vinylidene difluoride (PVDF) based transducers that have already proven to be biocompatible.

ENTRANCE GATE AND MEMORIAL AVENUE APPROACH, LOOKING INTO CEMETERY WITH ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

ENTRANCE GATE AND MEMORIAL AVENUE APPROACH, LOOKING INTO CEMETERY WITH ADMINISTRATION BUILDING IN BACKGROUND. VIEW TO NORTHWEST. - Mountain Home National Cemetery, Mountain Home, Washington County, TN

Impact of gate work-function on memory characteristics in Al2O3/HfOx/Al2O3/graphene charge-trap memory devices

NASA Astrophysics Data System (ADS)

Lee, Sejoon; Song, Emil B.; Kim, Sungmin; Seo, David H.; Seo, Sunae; Won Kang, Tae; Wang, Kang L.

2012-01-01

Graphene-based non-volatile memory devices composed of a single-layer graphene channel and an Al2O3/HfOx/Al2O3 charge-storage layer exhibit memory functionality. The impact of the gate material's work-function (Φ) on the memory characteristics is investigated using different types of metals [Ti (ΦTi = 4.3 eV) and Ni (ΦNi = 5.2 eV)]. The ambipolar carrier conduction of graphene results in an enlargement of memory window (ΔVM), which is ˜4.5 V for the Ti-gate device and ˜9.1 V for the Ni-gate device. The increase in ΔVM is attributed to the change in the flat-band condition and the suppression of electron back-injection within the gate stack.

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

NASA Astrophysics Data System (ADS)

Seto, Daisaku; Watanabe, Minoru

2015-09-01

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Organic transistor memory with a charge storage molecular double-floating-gate monolayer.

PubMed

Tseng, Chiao-Wei; Huang, Ding-Chi; Tao, Yu-Tai

2015-05-13

A flexible, low-voltage, and nonvolatile memory device was fabricated by implanting a functional monolayer on an aluminum oxide dielectric surface in a pentacene-based organic transistor. The monolayer-forming molecule contains a phosphonic acid group as the anchoring moiety and a charge-trapping core group flanked between two alkyl chain spacers as the charge trapping site. The memory characteristics strongly depend on the monolayer used due to the localized charge-trapping capability for different core groups, including the diacetylenic (DA) unit as the hole carrier trap, the naphthalenetetracarboxyldiimide (ND) unit as the electron carrier trap, and the one with both DA and ND units present, respectively. The device with the monolayer carrying both DA and ND groups has a larger memory window than that for the one containing DA only and a longer retention time than that for the one containing DA or ND only, giving a memory window of 1.4 V and a retention time around 10(9) s. This device with hybrid organic monolayer/inorganic dielectrics also exhibited rather stable device characteristics upon bending of the polymeric substrate.

Manipulating particles for micro- and nano-fluidics via floating electrodes and diffusiophoresis

NASA Astrophysics Data System (ADS)

Yalcin, Sinan Eren

The ability to accurately control micro- and nano-particles in a liquid is fundamentally useful for many applications in biology, medicine, pharmacology, tissue engineering, and microelectronics. Therefore, first particle manipulations are experimentally studied using electrodes attached to the bottom of a straight microchannel under an imposed DC or AC electric field. In contrast to a dielectric microchannel possessing a nearly-uniform surface charge, a floating electrode is polarized under the imposed electric field. The purpose is to create a non-uniform distribution of the induced surface charge, with a zero-net-surface charge along the floating electrode's surface. Such a field, in turn, generates an induced-charge electro-osmotic (ICED) flow near the metal strip. The demonstrations by using single and multiple floating electrodes at the bottom of a straight microchannel, with induced DC electric field, include particle enrichment, movement, trapping, reversal of motion, separation, and particle focusing. A flexible strategy for the on-demand control of the particle enrichment and positioning is also proposed and demonstrated by using a locally-controlled floating metal electrode. Then, under an externally imposed AC electric field, the particle deposition onto a floating electrode, which is placed in a closed circular cavity, has been experimentally investigated. In the second part of the study, another particle manipulation method was computationally investigated. The diffusiophoretic and electrodiffusiophoretic motion of a charged spherical particle in a nanopore is subjected to an axial electrolyte concentration gradient. The charged particle experiences electrophoresis because of the imposed electric field and the diffusiophoresis is caused solely by the imposed concentration gradient. Depending on the magnitude and direction of the imposed concentration gradient, the particle's electrophoretic motion can be accelerated, decelerated, and even reversed in

Controlling Working Memory Operations by Selective Gating: The Roles of Oscillations and Synchrony

PubMed Central

Dipoppa, Mario; Szwed, Marcin; Gutkin, Boris S.

2016-01-01

Working memory (WM) is a primary cognitive function that corresponds to the ability to update, stably maintain, and manipulate short-term memory (ST M) rapidly to perform ongoing cognitive tasks. A prevalent neural substrate of WM coding is persistent neural activity, the property of neurons to remain active after having been activated by a transient sensory stimulus. This persistent activity allows for online maintenance of memory as well as its active manipulation necessary for task performance. WM is tightly capacity limited. Therefore, selective gating of sensory and internally generated information is crucial for WM function. While the exact neural substrate of selective gating remains unclear, increasing evidence suggests that it might be controlled by modulating ongoing oscillatory brain activity. Here, we review experiments and models that linked selective gating, persistent activity, and brain oscillations, putting them in the more general mechanistic context of WM. We do so by defining several operations necessary for successful WM function and then discussing how such operations may be carried out by mechanisms suggested by computational models. We specifically show how oscillatory mechanisms may provide a rapid and flexible active gating mechanism for WM operations. PMID:28154616

Controlling Working Memory Operations by Selective Gating: The Roles of Oscillations and Synchrony.

PubMed

Dipoppa, Mario; Szwed, Marcin; Gutkin, Boris S

2016-01-01

Working memory (WM) is a primary cognitive function that corresponds to the ability to update, stably maintain, and manipulate short-term memory (ST M) rapidly to perform ongoing cognitive tasks. A prevalent neural substrate of WM coding is persistent neural activity , the property of neurons to remain active after having been activated by a transient sensory stimulus. This persistent activity allows for online maintenance of memory as well as its active manipulation necessary for task performance. WM is tightly capacity limited. Therefore, selective gating of sensory and internally generated information is crucial for WM function. While the exact neural substrate of selective gating remains unclear, increasing evidence suggests that it might be controlled by modulating ongoing oscillatory brain activity. Here, we review experiments and models that linked selective gating, persistent activity, and brain oscillations, putting them in the more general mechanistic context of WM. We do so by defining several operations necessary for successful WM function and then discussing how such operations may be carried out by mechanisms suggested by computational models. We specifically show how oscillatory mechanisms may provide a rapid and flexible active gating mechanism for WM operations.

State memory in solution gated epitaxial graphene

NASA Astrophysics Data System (ADS)

Butko, A. V.; Butko, V. Y.; Lebedev, S. P.; Lebedev, A. A.; Davydov, V. Y.; Smirnov, A. N.; Eliseyev, I. A.; Dunaevskiy, M. S.; Kumzerov, Y. A.

2018-06-01

We studied electrical transport in transistors fabricated on a surface of high quality epitaxial graphene with density of defects as low as 5·1010 cm-2 and observed quasistatic hysteresis with a time constant in a scale of hours. This constant is in a few orders of magnitude greater than the constant previously reported in CVD graphene. The hysteresis observed here can be described as a shift of ∼+2V of the Dirac point measured during a gate voltage increase from the position of the Dirac point measured during a gate voltage decrease. This hysteresis can be characterized as a nonvolatile quasistatic state memory effect in which the state of the gated graphene is determined by its initial state prior to entering the hysteretic region. Due to this effect the difference in resistance of the gated graphene measured in the hysteretic region at the same applied voltages can be as high as 70%. The observed effect can be explained by assuming that charge carriers in graphene and oppositely charged molecular ions from the solution form quasistable interfacial complexes at the graphene interface. These complexes likely preserve the initial state by preventing charge carriers in graphene from discharging in the hysteretic region.

Configurable unitary transformations and linear logic gates using quantum memories.

PubMed

Campbell, G T; Pinel, O; Hosseini, M; Ralph, T C; Buchler, B C; Lam, P K

2014-08-08

We show that a set of optical memories can act as a configurable linear optical network operating on frequency-multiplexed optical states. Our protocol is applicable to any quantum memories that employ off-resonant Raman transitions to store optical information in atomic spins. In addition to the configurability, the protocol also offers favorable scaling with an increasing number of modes where N memories can be configured to implement arbitrary N-mode unitary operations during storage and readout. We demonstrate the versatility of this protocol by showing an example where cascaded memories are used to implement a conditional cz gate.

3-D Observation of dopant distribution at NAND flash memory floating gate using Atom probe tomography

NASA Astrophysics Data System (ADS)

Lee, Ji-hyun; Chae, Byeong-Kyu; Kim, Joong-Jeong; Lee, Sun Young; Park, Chan Gyung

2015-01-01

Dopant control becomes more difficult and critical as silicon devices become smaller. We observed the dopant distribution in a thermally annealed polysilicon gate using Transmission Electron Microscopy (TEM) and Atom probe tomography (APT). Phosphorus was doped at the silicon-nitride-diffusion-barrier-layer-covered polycrystalline silicon gate. Carbon also incorporated at the gate for the enhancement of operation uniformity. The impurity distribution was observed using atom probe tomography. The carbon atoms had segregated at grain boundaries and suppressed silicon grain growth. Phosphorus atoms, on the other hand, tended to pile-up at the interface. A 1-nm-thick diffusion barrier effectively blocked P atom out-diffusion. [Figure not available: see fulltext.

GATE AND FLANKING FENCE AT ENTRANCE TO MEMORIAL WALK. VIEW ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

GATE AND FLANKING FENCE AT ENTRANCE TO MEMORIAL WALK. VIEW TO NORTHEAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

GETTYSBURG ADDRESS TABLET BESIDE ENTRANCE GATE AT MEMORIAL WALK. VIEW ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

GETTYSBURG ADDRESS TABLET BESIDE ENTRANCE GATE AT MEMORIAL WALK. VIEW TO EAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

DETAIL OF FENCE FLANKING GATE AT ENTRANCE TO MEMORIAL WALK. ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

DETAIL OF FENCE FLANKING GATE AT ENTRANCE TO MEMORIAL WALK. VIEW TO NORTHEAST. - Rock Island National Cemetery, Rock Island Arsenal, 0.25 mile north of southern tip of Rock Island, Rock Island, Rock Island County, IL

Microbial community evolution of black and stinking rivers during in situ remediation through micro-nano bubble and submerged resin floating bed technology.

PubMed

Sun, Yanmei; Wang, Shiwei; Niu, Junfeng

2018-06-01

Microbes play important roles during river remediation and the interaction mechanism illustration between microorganisms and sewage is of great significance to improve restoration technology. In this study, micro-nano bubble and submerged resin floating bed composite technology (MBSR) was firstly used to restore two black and stinking urban rivers. After restoration, the water pollution indices such as dissolved oxygen (DO), ammonia nitrogen (NH 4 + -N), total phosphorous (TP), chemical oxygen demand (COD Cr ), water clarity, and the number of facial coliform were significantly improved. Microbial community composition and relative abundance both varied and more aerobic microbes emerged after remediation. The microbial changes showed correlation with DO, NH 4 + -N, TP and COD Cr of the rivers. In summary, the MBSR treatment improved the physiochemical properties of the two black and stinking urban rivers probably through oxygen enrichment of micro-nano bubble and adsorption of submerged resin floating bed, which thereby stimulated functional microbes to degrade pollutants. Copyright © 2018 Elsevier Ltd. All rights reserved.

Synthesis and electron storage characteristics of isolated silver nanodots on/embedded in Al 2O 3 gate dielectric

NASA Astrophysics Data System (ADS)

Wang, Q.; Song, Z. T.; Liu, W. L.; Lin, C. L.; Wang, T. H.

2004-05-01

Monolayer-isolated silver (Ag) nanodots with the average diameter down to 7 nm are synthesized on Al 2O 3/Si substrate by vacuum electron-beam evaporation followed by annealing at 400 °C in N 2 ambient. Metal-insulator-silicon (MIS) structures with Ag nanodots embedded in Al 2O 3 gate dielectric are fabricated. Clear electron storage effect with the flatband voltage shift of 1.3 eV is observed through capacitance-conductance and conductance-voltage measurements. Our results demonstrate the feasibility of applying Ag nanodots for nanocrystal floating-gate memory devices.

Multibit Polycristalline Silicon-Oxide-Silicon Nitride-Oxide-Silicon Memory Cells with High Density Designed Utilizing a Separated Control Gate

NASA Astrophysics Data System (ADS)

Rok Kim, Kyeong; You, Joo Hyung; Dal Kwack, Kae; Kim, Tae Whan

2010-10-01

Unique multibit NAND polycrystalline silicon-oxide-silicon nitride-oxide-silicon (SONOS) memory cells utilizing a separated control gate (SCG) were designed to increase memory density. The proposed NAND SONOS memory device based on a SCG structure was operated as two bits, resulting in an increase in the storage density of the NVM devices in comparison with conventional single-bit memories. The electrical properties of the SONOS memory cells with a SCG were investigated to clarify the charging effects in the SONOS memory cells. When the program voltage was supplied to each gate of the NAND SONOS flash memory cells, the electrons were trapped in the nitride region of the oxide-nitride-oxide layer under the gate to supply the program voltage. The electrons were accumulated without affecting the other gate during the programming operation, indicating the absence of cross-talk between two trap charge regions. It is expected that the inference effect will be suppressed by the lower program voltage than the program voltage of the conventional NAND flash memory. The simulation results indicate that the proposed unique NAND SONOS memory cells with a SCG can be used to increase memory density.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

NASA Astrophysics Data System (ADS)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Gating of memory encoding of time-delayed cross-frequency MEG networks revealed by graph filtration based on persistent homology

PubMed Central

Hahm, Jarang; Lee, Hyekyoung; Park, Hyojin; Kang, Eunjoo; Kim, Yu Kyeong; Chung, Chun Kee; Kang, Hyejin; Lee, Dong Soo

2017-01-01

To explain gating of memory encoding, magnetoencephalography (MEG) was analyzed over multi-regional network of negative correlations between alpha band power during cue (cue-alpha) and gamma band power during item presentation (item-gamma) in Remember (R) and No-remember (NR) condition. Persistent homology with graph filtration on alpha-gamma correlation disclosed topological invariants to explain memory gating. Instruction compliance (R-hits minus NR-hits) was significantly related to negative coupling between the left superior occipital (cue-alpha) and the left dorsolateral superior frontal gyri (item-gamma) on permutation test, where the coupling was stronger in R than NR. In good memory performers (R-hits minus false alarm), the coupling was stronger in R than NR between the right posterior cingulate (cue-alpha) and the left fusiform gyri (item-gamma). Gating of memory encoding was dictated by inter-regional negative alpha-gamma coupling. Our graph filtration over MEG network revealed these inter-regional time-delayed cross-frequency connectivity serve gating of memory encoding. PMID:28169281

Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

PubMed Central

Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

2016-01-01

The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (<100 Hz) with a capacitor of merely 6 fF, which is hosted in an FG metal-oxide-semiconductor field-effect transistor. The FG-LIF neuron also has the advantage of low operation power (<30 pW/spike). Finally, the proposed circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

Radiation Effects on Advanced Flash Memories

NASA Technical Reports Server (NTRS)

Nguyen, D. N.; Guertin, S.; Swift, G. M.; Johnston, A. H.

1998-01-01

Flash memories have evolved very rapidly in recent ears. New design techniques such as multilevel storage have been proposed to increase storage density, and are now available commercially. Threshold voltage distributions for single- and three-level technologies are compared. In order to implement this technology special circuitry must be added to allow the amount of charge stored in the floating gate to be controlled within narrow limits during the writing and also to detect the different amounts of charge during reading.

Adult forebrain NMDA receptors gate social motivation and social memory.

PubMed

Jacobs, Stephanie; Tsien, Joe Z

2017-02-01

Motivation to engage in social interaction is critical to ensure normal social behaviors, whereas dysregulation in social motivation can contribute to psychiatric diseases such as schizophrenia, autism, social anxiety disorders and post-traumatic stress disorder (PTSD). While dopamine is well known to regulate motivation, its downstream targets are poorly understood. Given the fact that the dopamine 1 (D1) receptors are often physically coupled with the NMDA receptors, we hypothesize that the NMDA receptor activity in the adult forebrain principal neurons are crucial not only for learning and memory, but also for the proper gating of social motivation. Here, we tested this hypothesis by examining sociability and social memory in inducible forebrain-specific NR1 knockout mice. These mice are ideal for exploring the role of the NR1 subunit in social behavior because the NR1 subunit can be selectively knocked out after the critical developmental period, in which NR1 is required for normal development. We found that the inducible deletion of the NMDA receptors prior to behavioral assays impaired, not only object and social recognition memory tests, but also resulted in profound deficits in social motivation. Mice with ablated NR1 subunits in the forebrain demonstrated significant decreases in sociability compared to their wild type counterparts. These results suggest that in addition to its crucial role in learning and memory, the NMDA receptors in the adult forebrain principal neurons gate social motivation, independent of neuronal development. Copyright © 2016 Elsevier Inc. All rights reserved.

Auto- and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin

1989-01-01

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Auto- and hetero-associative memory using a 2-D optical logic gate

NASA Astrophysics Data System (ADS)

Chao, Tien-Hsin

1989-06-01

An optical associative memory system suitable for both auto- and hetero-associative recall is demonstrated. This system utilizes Hamming distance as the similarity measure between a binary input and a memory image with the aid of a two-dimensional optical EXCLUSIVE OR (XOR) gate and a parallel electronics comparator module. Based on the Hamming distance measurement, this optical associative memory performs a nearest neighbor search and the result is displayed in the output plane in real-time. This optical associative memory is fast and noniterative and produces no output spurious states as compared with that of the Hopfield neural network model.

Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Li, Y.; Zhong, Y. P.; Deng, Y. F.

2013-12-21

Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.

Learning to use working memory: a reinforcement learning gating model of rule acquisition in rats

PubMed Central

Lloyd, Kevin; Becker, Nadine; Jones, Matthew W.; Bogacz, Rafal

2012-01-01

Learning to form appropriate, task-relevant working memory representations is a complex process central to cognition. Gating models frame working memory as a collection of past observations and use reinforcement learning (RL) to solve the problem of when to update these observations. Investigation of how gating models relate to brain and behavior remains, however, at an early stage. The current study sought to explore the ability of simple RL gating models to replicate rule learning behavior in rats. Rats were trained in a maze-based spatial learning task that required animals to make trial-by-trial choices contingent upon their previous experience. Using an abstract version of this task, we tested the ability of two gating algorithms, one based on the Actor-Critic and the other on the State-Action-Reward-State-Action (SARSA) algorithm, to generate behavior consistent with the rats'. Both models produced rule-acquisition behavior consistent with the experimental data, though only the SARSA gating model mirrored faster learning following rule reversal. We also found that both gating models learned multiple strategies in solving the initial task, a property which highlights the multi-agent nature of such models and which is of importance in considering the neural basis of individual differences in behavior. PMID:23115551

95. Photocopied August 1978. CRIBS BEING FLOATED INTO PLACE FOR ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

95. Photocopied August 1978. CRIBS BEING FLOATED INTO PLACE FOR THE CONSTRUCTION OF THE SECOND SET (NOS. 13-16) OF COMPENSATING GATES. NOTE THE ORIGINAL FOUR GATES IN THE BACKGROUND, MAY 14, 1915. (587) - Michigan Lake Superior Power Company, Portage Street, Sault Ste. Marie, Chippewa County, MI

Applying n-bit floating point numbers and integers, and the n-bit filter of HDF5 to reduce file sizes of remote sensing products in memory-sensitive environments

NASA Astrophysics Data System (ADS)

Zinke, Stephan

2017-02-01

Memory sensitive applications for remote sensing data require memory-optimized data types in remote sensing products. Hierarchical Data Format version 5 (HDF5) offers user defined floating point numbers and integers and the n-bit filter to create data types optimized for memory consumption. The European Organisation for the Exploitation of Meteorological Satellites (EUMETSAT) applies a compaction scheme to the disseminated products of the Day and Night Band (DNB) data of Suomi National Polar-orbiting Partnership (S-NPP) satellite's instrument Visible Infrared Imager Radiometer Suite (VIIRS) through the EUMETSAT Advanced Retransmission Service, converting the original 32 bits floating point numbers to user defined floating point numbers in combination with the n-bit filter for the radiance dataset of the product. The radiance dataset requires a floating point representation due to the high dynamic range of the DNB. A compression factor of 1.96 is reached by using an automatically determined exponent size and an 8 bits trailing significand and thus reducing the bandwidth requirements for dissemination. It is shown how the parameters needed for user defined floating point numbers are derived or determined automatically based on the data present in a product.

Memory and learning behaviors mimicked in nanogranular SiO2-based proton conductor gated oxide-based synaptic transistors

NASA Astrophysics Data System (ADS)

Wan, Chang Jin; Zhu, Li Qiang; Zhou, Ju Mei; Shi, Yi; Wan, Qing

2013-10-01

In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements.In neuroscience, signal processing, memory and learning function are established in the brain by modifying ionic fluxes in neurons and synapses. Emulation of memory and learning behaviors of biological systems by nanoscale ionic/electronic devices is highly desirable for building neuromorphic systems or even artificial neural networks. Here, novel artificial synapses based on junctionless oxide-based protonic/electronic hybrid transistors gated by nanogranular phosphorus-doped SiO2-based proton-conducting films are fabricated on glass substrates by a room-temperature process. Short-term memory (STM) and long-term memory (LTM) are mimicked by tuning the pulse gate voltage amplitude. The LTM process in such an artificial synapse is due to the proton-related interfacial electrochemical reaction. Our results are highly desirable for building future neuromorphic systems or even artificial networks via electronic elements. Electronic supplementary information (ESI) available. See DOI: 10.1039/c3nr02987e

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

PubMed

Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

2012-08-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure

PubMed Central

2012-01-01

A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal–semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials. PMID:22853458

Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory

NASA Technical Reports Server (NTRS)

Oldham, Timothy R.; Suhail, Mohammed; Kuhn, Peter; Prinz, Erwin; Kim, Hak; LaBel, Kenneth A.

2004-01-01

We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.

High-performance black phosphorus top-gate ferroelectric transistor for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Lee, Young Tack; Hwang, Do Kyung; Choi, Won Kook

2016-10-01

Two-dimensional (2D) van der Waals (vdW) atomic crystals have been extensively studied and significant progress has been made. The newest 2D vdW material, called black phosphorus (BP), has attracted considerable attention due to its unique physical properties, such as its being a singlecomponent material like graphene, and its having a high mobility and direct band gap. Here, we report on a high-performance BP nanosheet based ferroelectric field effect transistor (FeFET) with a poly(vinylidenefluoride-trifluoroethylene) top-gate insulator for a nonvolatile memory application. The BP FeFETs show the highest linear hole mobility of 563 cm2/Vs and a clear memory window of more than 15 V. For more advanced nonvolatile memory circuit applications, two different types of resistive-load and complementary ferroelectric memory inverters were implemented, which showed distinct memory on/off switching characteristics.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

NASA Astrophysics Data System (ADS)

Wang, Xudong; Liu, Chunsen; Chen, Yan; Wu, Guangjian; Yan, Xiao; Huang, Hai; Wang, Peng; Tian, Bobo; Hong, Zhenchen; Wang, Yutao; Sun, Shuo; Shen, Hong; Lin, Tie; Hu, Weida; Tang, Minghua; Zhou, Peng; Wang, Jianlu; Sun, Jinglan; Meng, Xiangjian; Chu, Junhao; Li, Zheng

2017-06-01

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

Transparent photostable ZnO nonvolatile memory transistor with ferroelectric polymer and sputter-deposited oxide gate

NASA Astrophysics Data System (ADS)

Park, C. H.; Im, Seongil; Yun, Jungheum; Lee, Gun Hwan; Lee, Byoung H.; Sung, Myung M.

2009-11-01

We report on the fabrication of transparent top-gate ZnO nonvolatile memory thin-film transistors (NVM-TFTs) with 200 nm thick poly(vinylidene fluoride/trifluoroethylene) ferroelectric layer; semitransparent 10 nm thin AgOx and transparent 130 nm thick indium-zinc oxide (IZO) were deposited on the ferroelectric polymer as gate electrode by rf sputtering. Our semitransparent NVM-TFT with AgOx gate operates under low voltage write-erase (WR-ER) pulse of ±20 V, but shows some degradation in retention property. In contrast, our transparent IZO-gated device displays very good retention properties but requires anomalously higher pulse of ±70 V for WR and ER states. Both devices stably operated under visible illuminations.

Auto and hetero-associative memory using a 2-D optical logic gate

NASA Technical Reports Server (NTRS)

Chao, Tien-Hsin (Inventor)

1992-01-01

An optical system for auto-associative and hetero-associative recall utilizing Hamming distance as the similarity measure between a binary input image vector V(sup k) and a binary image vector V(sup m) in a first memory array using an optical Exclusive-OR gate for multiplication of each of a plurality of different binary image vectors in memory by the input image vector. After integrating the light of each product V(sup k) x V(sup m), a shortest Hamming distance detection electronics module determines which product has the lowest light intensity and emits a signal that activates a light emitting diode to illuminate a corresponding image vector in a second memory array for display. That corresponding image vector is identical to the memory image vector V(sup m) in the first memory array for auto-associative recall or related to it, such as by name, for hetero-associative recall.

[Effects of nano-selenium on the capability of learning memory and the activity of Se-protein of mice].

PubMed

Qin, Fenju; Ye, Yaxin; Yao, Xuemei

2008-07-01

To investigate the effects of Nano-Selenium on learning memory capability and activity of two kinds of Se-protein in brain and liver of mice, Na, SeO3 as the controls. The mice were administred two kinds of origin (doses of 1 microgSe/d, 2 microgSe/d, 4 microgSe/d) Se by intra-gastric injection respectively. The learning memory ability of the mice was measured by Y-type maze test. Activities of glutathione peroxidase (GSH-Px) and iodothyronine deiodinase (ID) in brain and liver were also measured. In comparison with the control groups of Na2 Se03, learning memory abilities were improved and activities of ID and GSH-Px (P < 0.01 or P < 0.05) of brain and liver were increased in Nano-Se treatment groups. Nano-Se could improve learning memory ability of mice, and enhance ID and GSH-Px activities of brain and liver in mice.

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

NASA Astrophysics Data System (ADS)

Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

2018-04-01

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

Charge storage and tunneling mechanism of Ni nanocrystals embedded HfOx film

NASA Astrophysics Data System (ADS)

Zhu, H. X.; Zhang, T.; Wang, R. X.; Zhang, Y. Y.; Li, L. T.; Qiu, X. Y.

2016-05-01

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfOx film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfOx matrix. Pt/Ni-NCs embedded HfOx/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 1012 electrons/cm2, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 104 cycles and excellent retention performance of 105 s, fulfilling the requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.

Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells.

PubMed

Paydavosi, Sarah; Aidala, Katherine E; Brown, Patrick R; Hashemi, Pouya; Supran, Geoffrey J; Osedach, Timothy P; Hoyt, Judy L; Bulović, Vladimir

2012-03-14

Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells. © 2012 American Chemical Society

Performance of FORTRAN floating-point operations on the Flex/32 multicomputer

NASA Technical Reports Server (NTRS)

Crockett, Thomas W.

1987-01-01

A series of experiments has been run to examine the floating-point performance of FORTRAN programs on the Flex/32 (Trademark) computer. The experiments are described, and the timing results are presented. The time required to execute a floating-point operation is found to vary considerbaly depending on a number of factors. One factor of particular interest from an algorithm design standpoint is the difference in speed between common memory accesses and local memory accesses. Common memory accesses were found to be slower, and guidelines are given for determinig when it may be cost effective to copy data from common to local memory.

Floating assembly of diatom Coscinodiscus sp. microshells.

PubMed

Wang, Yu; Pan, Junfeng; Cai, Jun; Zhang, Deyuan

2012-03-30

Diatoms have silica frustules with transparent and delicate micro/nano scale structures, two dimensional pore arrays, and large surface areas. Although, the diatom cells of Coscinodiscus sp. live underwater, we found that their valves can float on water and assemble together. Experiments show that the convex shape and the 40 nm sieve pores of the valves allow them to float on water, and that the buoyancy and the micro-range attractive forces cause the valves to assemble together at the highest point of water. As measured by AFM calibrated glass needles fixed in manipulator, the buoyancy force on a single floating valve may reach up to 10 μN in water. Turning the valves over, enlarging the sieve pores, reducing the surface tension of water, or vacuum pumping may cause the floating valves to sink. After the water has evaporated, the floating valves remained in their assembled state and formed a monolayer film. The bonded diatom monolayer may be valuable in studies on diatom based optical devices, biosensors, solar cells, and batteries, to better use the optical and adsorption properties of frustules. The floating assembly phenomenon can also be used as a self-assembly method for fabricating monolayer of circular plates. Copyright © 2012 Elsevier Inc. All rights reserved.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

NASA Astrophysics Data System (ADS)

Bala, Shashi; Khosla, Mamta

2018-04-01

A double-gate tunnel field-effect transistor (DG tunnel FET) has been designed and investigated for various channel materials such as silicon (Si), gallium arsenide (GaAs), alminium gallium arsenide (Al x Ga1‑x As) and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are compared on the basis of inverse subthreshold slope (SS), I ON/I OFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the Al x Ga1‑x As based DG tunnel FET provides a better I ON/I OFF current ratio (2.51 × 106) as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.

Power reduction by power gating in differential pair type spin-transfer-torque magnetic random access memories for low-power nonvolatile cache memories

NASA Astrophysics Data System (ADS)

Ohsawa, Takashi; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2014-01-01

Array operation currents in spin-transfer-torque magnetic random access memories (STT-MRAMs) that use four differential pair type magnetic tunnel junction (MTJ)-based memory cells (4T2MTJ, two 6T2MTJs and 8T2MTJ) are simulated and compared with that in SRAM. With L3 cache applications in mind, it is assumed that the memories are composed of 32 Mbyte capacity to be accessed in 64 byte in parallel. All the STT-MRAMs except for the 8T2MTJ one are designed with 32 bit fine-grained power gating scheme applied to eliminate static currents in the memory cells that are not accessed. The 8T2MTJ STT-MRAM, the cell’s design concept being not suitable for the fine-grained power gating, loads and saves 32 Mbyte data in 64 Mbyte unit per 1 Mbit sub-array in 2 × 103 cycles. It is shown that the array operation current of the 4T2MTJ STT-MRAM is 70 mA averaged in 15 ns write cycles at Vdd = 0.9 V. This is the smallest among the STT-MRAMs, about the half of the low standby power (LSTP) SRAM whose array operation current is totally dominated by the cells’ subthreshold leakage.

Light-Gated Memristor with Integrated Logic and Memory Functions.

PubMed

Tan, Hongwei; Liu, Gang; Yang, Huali; Yi, Xiaohui; Pan, Liang; Shang, Jie; Long, Shibing; Liu, Ming; Wu, Yihong; Li, Run-Wei

2017-11-28

Memristive devices are able to store and process information, which offers several key advantages over the transistor-based architectures. However, most of the two-terminal memristive devices have fixed functions once made and cannot be reconfigured for other situations. Here, we propose and demonstrate a memristive device "memlogic" (memory logic) as a nonvolatile switch of logic operations integrated with memory function in a single light-gated memristor. Based on nonvolatile light-modulated memristive switching behavior, a single memlogic cell is able to achieve optical and electrical mixed basic Boolean logic of reconfigurable "AND", "OR", and "NOT" operations. Furthermore, the single memlogic cell is also capable of functioning as an optical adder and digital-to-analog converter. All the memlogic outputs are memristive for in situ data storage due to the nonvolatile resistive switching and persistent photoconductivity effects. Thus, as a memdevice, the memlogic has potential for not only simplifying the programmable logic circuits but also building memristive multifunctional optoelectronics.

Study of the enhancement-mode AlGaN/GaN high electron mobility transistor with split floating gates

NASA Astrophysics Data System (ADS)

Wang, Hui; Wang, Ning; Jiang, Ling-Li; Zhao, Hai-Yue; Lin, Xin-Peng; Yu, Hong-Yu

2017-11-01

In this work, the charge storage based split floating gates (FGs) enhancement mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) are studied. The simulation results reveal that under certain density of two dimensional electron gas, the variation tendency of the threshold voltage (Vth) with the variation of the blocking dielectric thickness depends on the FG charge density. It is found that when the length sum and isolating spacing sum of the FGs both remain unchanged, the Vth shall decrease with the increasing FGs number but maintaining the device as E-mode. It is also reported that for the FGs HEMT, the failure of a FG will lead to the decrease of Vth as well as the increase of drain current, and the failure probability can be improved significantly with the increase of FGs number.

Electrowetting in a water droplet with a movable floating substrate

NASA Astrophysics Data System (ADS)

Shahzad, Amir; Masud, A. R.; Song, Jang-Kun

2016-05-01

Electrowetting (EW) enables facile manipulation of a liquid droplet on a hydrophobic surface. In this study, manipulation of an electrolyte droplet having a small floating object on it was investigated on a solid hydrophobic substrate under the EW process. Herein, the floating object exhibited a vertical motion under an applied electric field owing to the spreading and contraction of the droplet on its connecting substrates. The field-induced height variation of the floating object was significantly influenced by the thicknesses of the dielectric and hydrophobic materials. A small mass was also placed on the top floating object and its effect on the spreading of the droplet was observed. In this system, the height of the top floating object is precisely controllable under the application of an electric voltage. The proposed system is expected to be highly useful in the design of nano- and micro-oscillatory systems for microengineering.

Electrowetting in a water droplet with a movable floating substrate.

PubMed

Shahzad, Amir; Masud, A R; Song, Jang-Kun

2016-05-01

Electrowetting (EW) enables facile manipulation of a liquid droplet on a hydrophobic surface. In this study, manipulation of an electrolyte droplet having a small floating object on it was investigated on a solid hydrophobic substrate under the EW process. Herein, the floating object exhibited a vertical motion under an applied electric field owing to the spreading and contraction of the droplet on its connecting substrates. The field-induced height variation of the floating object was significantly influenced by the thicknesses of the dielectric and hydrophobic materials. A small mass was also placed on the top floating object and its effect on the spreading of the droplet was observed. In this system, the height of the top floating object is precisely controllable under the application of an electric voltage. The proposed system is expected to be highly useful in the design of nano- and micro-oscillatory systems for microengineering.

Nano-Satellite Avionics

NASA Technical Reports Server (NTRS)

Culver, Harry

1999-01-01

Abstract NASA's Goddard Space Flight Center (GSFC) is currently developing a new class of satellites called the nano-satellite (nano-sat). A major objective of this development effort is to provide the technology required to enable a constellation of tens to hundreds of nano-satellites to make both remote and in-situ measurements from space. The Nano-sat will be a spacecraft weighing a maximum of 10 kg, including the propellant mass, and producing at least 5 Watts of power to operate the spacecraft. The electronics are required to survive a total radiation dose rate of 100 krads for a mission lifetime of two years. There are many unique challenges that must be met in order to develop the avionics for such a spacecraft. The first challenge is to develop an architecture that will operate on the allotted 5 Watts and meet the diverging requirements of multiple missions. This architecture will need to incorporate a multitude of new advanced microelectronic technologies. The microelectronics developed must be a modular and scalable packaging of technology to solve the problem of developing a solution to both reduce cost and meet the requirements of various missions. This development will utilize the most cost effective approach, whether infusing commercially driven semiconductor devices into spacecraft applications or partnering with industry to design and develop low cost, low power, low mass, and high capacity data processing devices. This paper will discuss the nano-sat architecture and the major technologies that will be developed. The major technologies that will be covered include: (1) Light weight Low Power Electronics Packaging, (2) Radiation Hard/Tolerant, Low Power Processing Platforms, (3) High capacity Low Power Memory Systems (4) Radiation Hard reconfiguragble field programmable gate array (rFPGA)

MEMS Gate Structures for Electric Propulsion Applications

DTIC Science & Technology

2006-07-12

distance between gates of dual gate system V = grid voltage Dsheath = sheath thickness Va = anode voltage E = electric field Vemitter = emitter voltage Es...minutes. A hot pressed boron nitride target (4N) in the hexagonal phase (h- BN) was sputtered in a RF magnetron sputtering gun. To promote the nucleation...and nanoFETs. This paper concludes with a discussion on using MEMS gates for dual -grid electron field emission applications. II. Gate Design I I

On the simple random-walk models of ion-channel gate dynamics reflecting long-term memory.

PubMed

Wawrzkiewicz, Agata; Pawelek, Krzysztof; Borys, Przemyslaw; Dworakowska, Beata; Grzywna, Zbigniew J

2012-06-01

Several approaches to ion-channel gating modelling have been proposed. Although many models describe the dwell-time distributions correctly, they are incapable of predicting and explaining the long-term correlations between the lengths of adjacent openings and closings of a channel. In this paper we propose two simple random-walk models of the gating dynamics of voltage and Ca(2+)-activated potassium channels which qualitatively reproduce the dwell-time distributions, and describe the experimentally observed long-term memory quite well. Biological interpretation of both models is presented. In particular, the origin of the correlations is associated with fluctuations of channel mass density. The long-term memory effect, as measured by Hurst R/S analysis of experimental single-channel patch-clamp recordings, is close to the behaviour predicted by our models. The flexibility of the models enables their use as templates for other types of ion channel.

Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

PubMed

Takulapalli, Bharath R

2010-02-23

Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

Impact of strain on electronic and transport properties of 6 nm hydrogenated germanane nano-ribbon channel double gate field effect transistor

NASA Astrophysics Data System (ADS)

Meher Abhinav, E.; Sundararaj, Anuraj; Gopalakrishnan, Chandrasekaran; Kasmir Raja, S. V.; Chokhra, Saurabh

2017-11-01

In this work, chair like fully hydrogenated germanane (CGeH) nano-ribbon 6 nm short channel double gate field effect transistor (DG-FET) has been modeled and the impact of strain on the I-V characteristics of CGeH channel has been examined. The bond lengths, binding and formation energies of various hydrogenated geometries of buckled germanane channel were calculated using local density approximation (LDA) with Perdew-Zunger (PZ) and generalized gradient approximation (GGA) with Perdew Burke Ernzerhof (PBE) parameterization. From four various geometries, chair like structure is found to be more stable compared to boat like obtuse, stiruup structure and table like structure. The bandgap versus width, bandgap versus strain characteristics and I-V characteristics had been analyzed at room temperature using density functional theory (DFT). Using self consistent calculation it was observed that the electronic properties of nano-ribbon is independent of length and band structure, but dependent on edge type, strain [Uni-axial (ɛ xx ), bi-axial (ɛ xx   =  ɛ yy )] and width of the ribbon. The strain engineered hydrogenated germanane (GeH) showed wide direct bandgap (2.3 eV) which could help to build low noise electronic devices that operates at high frequencies. The observed bi-axial compression has high impact on the device transport characteristics with peak to valley ratio (PVR) of 2.14 and 380% increase in peak current compared to pristine CGeH device. The observed strain in CGeH DG-FET could facilitate in designing novel multiple-logic memory devices due to multiple negative differential resistance (NDR) regions.

Fabrication and electrical characterization of a MOS memory device containing self-assembled metallic nanoparticles

NASA Astrophysics Data System (ADS)

Sargentis, Ch.; Giannakopoulos, K.; Travlos, A.; Tsamakis, D.

2007-04-01

Floating gate devices with nanoparticles embedded in dielectrics have recently attracted much attention due to the fact that these devices operate as non-volatile memories with high speed, high density and low power consumption. In this paper, memory devices containing gold (Au) nanoparticles have been fabricated using e-gun evaporation. The Au nanoparticles are deposited on a very thin SiO 2 layer and are then fully covered by a HfO 2 layer. The HfO 2 is a high- k dielectric and gives good scalability to the fabricated devices. We studied the effect of the deposition parameters to the size and the shape of the Au nanoparticles using capacitance-voltage and conductance-voltage measurements, we demonstrated that the fabricated device can indeed operate as a low-voltage memory device.

Total Ionizing Dose Influence on the Single Event Effect Sensitivity in Samsung 8Gb NAND Flash Memories

NASA Astrophysics Data System (ADS)

Edmonds, Larry D.; Irom, Farokh; Allen, Gregory R.

2017-08-01

A recent model provides risk estimates for the deprogramming of initially programmed floating gates via prompt charge loss produced by an ionizing radiation environment. The environment can be a mixture of electrons, protons, and heavy ions. The model requires several input parameters. This paper extends the model to include TID effects in the control circuitry by including one additional parameter. Parameters intended to produce conservative risk estimates for the Samsung 8 Gb SLC NAND flash memory are given, subject to some qualifications.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Zhu, H. X.; Zhang, T.; Wang, R. X.

A nano-floating gate memory structure based on Ni nanocrystals (NCs) embedded HfO{sub x} film is deposited by means of radio-frequency magnetron sputtering. Microstructure investigations reveal that self-organized Ni-NCs with diameters of 4-8 nm are well dispersed in amorphous HfO{sub x} matrix. Pt/Ni-NCs embedded HfO{sub x}/Si/Ag capacitor structures exhibit voltage-dependent capacitance-voltage hysteresis, and a maximum flat-band voltage shift of 1.5 V, corresponding to a charge storage density of 6.0 × 10{sup 12} electrons/cm{sup 2}, is achieved. These capacitor memory cells exhibit good endurance characteristic up to 4 × 10{sup 4} cycles and excellent retention performance of 10{sup 5} s, fulfilling themore » requirements of next generation non-volatile memory devices. Schottky tunneling is proven to be responsible for electrons tunneling in these capacitors.« less

Modeling and analysis of sub-surface leakage current in nano-MOSFET under cutoff regime

NASA Astrophysics Data System (ADS)

Swami, Yashu; Rai, Sanjeev

2017-02-01

The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in nano-MOSFET circuits as threshold voltage, channel length, and gate oxide thickness are scaled down to nano-meter range. Precise leakage current valuation and meticulous modeling of the same at nano-meter technology scale is an increasingly a critical work in designing the low power nano-MOSFET circuits. We present a specific compact model for sub-threshold regime leakage current in bulk driven nano-MOSFETs. The proposed logical model is instigated and executed into the latest updated PTM bulk nano-MOSFET model and is found to be in decent accord with technology-CAD simulation data. This paper also reviews various transistor intrinsic leakage mechanisms for nano-MOSFET exclusively in weak inversion, like drain-induced barricade lowering (DIBL), gate-induced drain leakage (GIDL), gate oxide tunneling (GOT) leakage etc. The root cause of the sub-surface leakage current is mainly due to the nano-scale short channel length causing source-drain coupling even in sub-threshold domain. Consequences leading to carriers triumphing the barricade between the source and drain. The enhanced model effectively considers the following parameter dependence in the account for better-quality value-added results like drain-to-source bias (VDS), gate-to-source bias (VGS), channel length (LG), source/drain junction depth (Xj), bulk doping concentration (NBULK), and operating temperature (Top).

Titanium-tungsten nanocrystals embedded in a SiO(2)/Al(2)O(3) gate dielectric stack for low-voltage operation in non-volatile memory.

PubMed

Yang, Shiqian; Wang, Qin; Zhang, Manhong; Long, Shibing; Liu, Jing; Liu, Ming

2010-06-18

Titanium-tungsten nanocrystals (NCs) were fabricated by a self-assembly rapid thermal annealing (RTA) process. Well isolated Ti(0.46)W(0.54) NCs were embedded in the gate dielectric stack of SiO(2)/Al(2)O(3). A metal-oxide-semiconductor (MOS) capacitor was fabricated to investigate its application in a non-volatile memory (NVM) device. It demonstrated a large memory window of 6.2 V in terms of flat-band voltage (V(FB)) shift under a dual-directional sweeping gate voltage of - 10 to 10 V. A 1.1 V V(FB) shift under a low dual-directional sweeping gate voltage of - 4 to 4 V was also observed. The retention characteristic of this MOS capacitor was demonstrated by a 0.5 V memory window after 10(4) s of elapsed time at room temperature. The endurance characteristic was demonstrated by a program/erase cycling test.

Selector-free resistive switching memory cell based on BiFeO3 nano-island showing high resistance ratio and nonlinearity factor

PubMed Central

Jeon, Ji Hoon; Joo, Ho-Young; Kim, Young-Min; Lee, Duk Hyun; Kim, Jin-Soo; Kim, Yeon Soo; Choi, Taekjib; Park, Bae Ho

2016-01-01

Highly nonlinear bistable current-voltage (I–V) characteristics are necessary in order to realize high density resistive random access memory (ReRAM) devices that are compatible with cross-point stack structures. Up to now, such I–V characteristics have been achieved by introducing complex device structures consisting of selection elements (selectors) and memory elements which are connected in series. In this study, we report bipolar resistive switching (RS) behaviours of nano-crystalline BiFeO3 (BFO) nano-islands grown on Nb-doped SrTiO3 substrates, with large ON/OFF ratio of 4,420. In addition, the BFO nano-islands exhibit asymmetric I–V characteristics with high nonlinearity factor of 1,100 in a low resistance state. Such selector-free RS behaviours are enabled by the mosaic structures and pinned downward ferroelectric polarization in the BFO nano-islands. The high resistance ratio and nonlinearity factor suggest that our BFO nano-islands can be extended to an N × N array of N = 3,740 corresponding to ~107 bits. Therefore, our BFO nano-island showing both high resistance ratio and nonlinearity factor offers a simple and promising building block of high density ReRAM. PMID:27001415

More than Memory Impairment in Voltage-Gated Potassium Channel Complex Encephalopathy

PubMed Central

Bettcher, Brianne M.; Gelfand, Jeffrey M.; Irani, Sarosh R.; Neuhaus, John; Forner, Sven; Hess, Christopher P.; Geschwind, Michael D.

2014-01-01

Objective Autoimmune encephalopathies (AE) are a heterogeneous group of neurological disorders that affect cognition. Although memory difficulties are commonly endorsed, few reports of AE inclusively assess all cognitive domains in detail. Our aim was to perform an unbiased cognitive evaluation of AE patients with voltage-gated potassium channel complex antibodies (VGKCC-Abs) in order to delineate cognitive strengths and weaknesses. Methods We assessed serial VGKCC-Abs AE subjects (n=12) with a comprehensive evaluation of memory, executive functions, visuospatial skills, and language. Clinical MRI (n=10/12) was evaluated. Five subjects had serial cognitive testing available, permitting descriptive analysis of change. Results Subjects demonstrated mild to moderate impairment in memory (mean Z=−1.9) and executive functions (mean Z=−1.5), with variable impairments in language and sparing of visuospatial skills. MRI findings showed T2 hyperintensities in medial temporal lobe (10/10) and basal ganglia (2/10). Serial cognitive examination revealed heterogeneity in cognitive function; whereas most patients improved in one or more domains, residual impairments were observed in some patients. Conclusions This study augments prior neuropsychological analyses in VGKCC-Ab AE by identifying not only memory and executive function deficits, but also language impairments, with preservation of visuospatial functioning. This study further highlights the importance of domain-specific testing to parse out the complex cognitive phenotypes of VGKCC-Ab AE. PMID:24981998

Modeling of Nano-Scale Transistors and Memory Devices for Low Power Applications

NASA Astrophysics Data System (ADS)

Cao, Xi

As the featuring size of transistors scaled down to sub-20 nm, the continuous scaling of power has become one of the main challenges of the semiconductor industry. The power issue is raised by the barely scalable supply voltage and a limitation on the subthreshold swing (SS) of conventional metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, self-consistent quantum transport device simulators are developed to examine the nanoscale transistors based on black phosphorus (BP) materials. The scaling limit of double-gated BP MOSFETs is assessed. To reduce the SS below the thermionic limit for ultra-steep switching, tunnel FETs (TFETs) and vertical ballistic impact ionization FETs based on BP and its heterojunctions are investigated. Furthermore, the ferroelectric tunneling junction (FTJ) is modeled and examined for potential low power memory applications. For BP MOSFETs, the device physics at the ultimate scaling limit are examined. The performance of monolayer BP MOSFETs is projected to sub-10 nm and compared with the International Technology Roadmap for Semiconductors (ITRS) requirements. And the interplay of quantum mechanical effects and the highly anisotropic bandstructure of BP at this scale is investigated. By choice of layer number and crystalline direction, BP materials can offer a range of bandgap and effective mass values, which is attractive for TFET applications. Therefore, scaling behaviors of BP TFETs near and below the 10 nm scale are studied. The gate oxide thickness scaling and the effect of high-k dielectric are compared between the TFETs and the MOSFETs. For the TFETs with the gate lengths beyond 10 nm and at the sub-10 nm scale, the direct-source-to-drain tunneling issues are evaluated, and different strategies to achieve ultra-steep switching are specified. In a sub-10 nm graphene-BP-graphene heterojunction transistor, the sharp turnon behavior was observed, under a small source-drain bias of 0.1 V. The fast switch is

Design of a radiation tolerant system for total ionizing dose monitoring using floating gate and RadFET dosimeters

NASA Astrophysics Data System (ADS)

Ferraro, R.; Danzeca, S.; Brucoli, M.; Masi, A.; Brugger, M.; Dilillo, L.

2017-04-01

The need for upgrading the Total Ionizing Dose (TID) measurement resolution of the current version of the Radiation Monitoring system for the LHC complex has driven the research of new TID sensors. The sensors being developed nowadays can be defined as Systems On Chip (SOC) with both analog and digital circuitries embedded in the same silicon. A radiation tolerant TID Monitoring System (TIDMon) has been designed to allow the placement of the entire dosimeter readout electronics in very harsh environments such as calibration rooms and even in the mixed radiation field such as the one of the LHC complex. The objective of the TIDMon is to measure the effect of the TID on the new prototype of Floating Gate Dosimeter (FGDOS) without using long cables and with a reliable measurement system. This work introduces the architecture of the TIDMon, the radiation tolerance techniques applied on the controlling electronics as well as the design choices adopted for the system. Finally, results of several tests of TIDMon under different radiation environments such as gamma rays or mixed radiation field at CHARM are presented.

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

NASA Technical Reports Server (NTRS)

MacLeod, Todd C.; Phillips, Thomas A.; Ho, Fat D.

2005-01-01

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

An adaptable neuromorphic model of orientation selectivity based on floating gate dynamics

PubMed Central

Gupta, Priti; Markan, C. M.

2014-01-01

The biggest challenge that the neuromorphic community faces today is to build systems that can be considered truly cognitive. Adaptation and self-organization are the two basic principles that underlie any cognitive function that the brain performs. If we can replicate this behavior in hardware, we move a step closer to our goal of having cognitive neuromorphic systems. Adaptive feature selectivity is a mechanism by which nature optimizes resources so as to have greater acuity for more abundant features. Developing neuromorphic feature maps can help design generic machines that can emulate this adaptive behavior. Most neuromorphic models that have attempted to build self-organizing systems, follow the approach of modeling abstract theoretical frameworks in hardware. While this is good from a modeling and analysis perspective, it may not lead to the most efficient hardware. On the other hand, exploiting hardware dynamics to build adaptive systems rather than forcing the hardware to behave like mathematical equations, seems to be a more robust methodology when it comes to developing actual hardware for real world applications. In this paper we use a novel time-staggered Winner Take All circuit, that exploits the adaptation dynamics of floating gate transistors, to model an adaptive cortical cell that demonstrates Orientation Selectivity, a well-known biological phenomenon observed in the visual cortex. The cell performs competitive learning, refining its weights in response to input patterns resembling different oriented bars, becoming selective to a particular oriented pattern. Different analysis performed on the cell such as orientation tuning, application of abnormal inputs, response to spatial frequency and periodic patterns reveal close similarity between our cell and its biological counterpart. Embedded in a RC grid, these cells interact diffusively exhibiting cluster formation, making way for adaptively building orientation selective maps in silicon. PMID

An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor.

PubMed

Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

2017-06-14

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 V RMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame.

An LMS Programming Scheme and Floating-Gate Technology Enabled Trimmer-Less and Low Voltage Flame Detection Sensor

PubMed Central

Iglesias-Rojas, Juan Carlos; Gomez-Castañeda, Felipe; Moreno-Cadenas, Jose Antonio

2017-01-01

In this paper, a Least Mean Square (LMS) programming scheme is used to set the offset voltage of two operational amplifiers that were built using floating-gate transistors, enabling a 0.95 VRMS trimmer-less flame detection sensor. The programming scheme is capable of setting the offset voltage over a wide range of values by means of electron injection. The flame detection sensor consists of two programmable offset operational amplifiers; the first amplifier serves as a 26 μV offset voltage follower, whereas the second amplifier acts as a programmable trimmer-less voltage comparator. Both amplifiers form the proposed sensor, whose principle of functionality is based on the detection of the electrical changes produced by the flame ionization. The experimental results show that it is possible to measure the presence of a flame accurately after programming the amplifiers with a maximum of 35 LMS-algorithm iterations. Current commercial flame detectors are mainly used in absorption refrigerators and large industrial gas heaters, where a high voltage AC source and several mechanical trimmings are used in order to accurately measure the presence of the flame. PMID:28613250

Cognitive mechanisms associated with auditory sensory gating

PubMed Central

Jones, L.A.; Hills, P.J.; Dick, K.M.; Jones, S.P.; Bright, P.

2016-01-01

Sensory gating is a neurophysiological measure of inhibition that is characterised by a reduction in the P50 event-related potential to a repeated identical stimulus. The objective of this work was to determine the cognitive mechanisms that relate to the neurological phenomenon of auditory sensory gating. Sixty participants underwent a battery of 10 cognitive tasks, including qualitatively different measures of attentional inhibition, working memory, and fluid intelligence. Participants additionally completed a paired-stimulus paradigm as a measure of auditory sensory gating. A correlational analysis revealed that several tasks correlated significantly with sensory gating. However once fluid intelligence and working memory were accounted for, only a measure of latent inhibition and accuracy scores on the continuous performance task showed significant sensitivity to sensory gating. We conclude that sensory gating reflects the identification of goal-irrelevant information at the encoding (input) stage and the subsequent ability to selectively attend to goal-relevant information based on that previous identification. PMID:26716891

The Role of Working Memory Gating in Task Switching: A Procedural Version of the Reference-Back Paradigm

PubMed Central

Kessler, Yoav

2017-01-01

Models of working memory (WM) suggest that the contents of WM are separated from perceptual input by a gate, that enables shielding information against interference when closed, and allows for rapid updating when open. Recent work in the declarative WM domain provided evidence for this notion, demonstrating the behavioral cost of opening and closing the gate. The goal of the present work was to examine gating in procedural WM, namely in a task-switching experiment. In each trial, participants were presented with a digit and a task cue, indicating whether the required task was a parity or a magnitude decision. Critically, a colored frame around the stimulus indicated whether the task cue was relevant (attend trials), or whether it had to be ignored, and the previous task set should be applied regardless of the present cue (ignore trials). Switching between tasks, and between ignore and attend trials, was manipulated. The results of two experiments demonstrated that the cost of gate opening was eliminated in task switching trials, implying that both processes operate in parallel. PMID:29312095

Azurin/CdSe-ZnS-Based Bio-Nano Hybrid Structure for Nanoscale Resistive Memory Device.

PubMed

Yagati, Ajay Kumar; Lee, Taek; Choi, Jeong-Woo

2017-07-15

In the present study, we propose a method for bio-nano hybrid formation by coupling a redox metalloprotein, Azurin, with CdSe-ZnS quantum dot for the development of a nanoscale resistive memory device. The covalent interaction between the two nanomaterials enables a strong and effective binding to form an azurin/CdSe-ZnS hybrid, and also enabled better controllability to couple with electrodes to examine the memory function properties. Morphological and optical properties were performed to confirm both hybrid formations and also their individual components. Current-Voltage (I-V) measurements on the hybrid nanostructures exhibited bistable current levels towards the memory function device, that and those characteristics were unnoticeable on individual nanomaterials. The hybrids showed good retention characteristics with high stability and durability, which is a promising feature for future nanoscale memory devices.

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA Technical Reports Server (NTRS)

Bell, L. D.; Boer, E.; Ostraat, M.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.

2000-01-01

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Pentacene-based metal-insulator-semiconductor memory structures utilizing single walled carbon nanotubes as a nanofloating gate

NASA Astrophysics Data System (ADS)

Sleiman, A.; Rosamond, M. C.; Alba Martin, M.; Ayesh, A.; Al Ghaferi, A.; Gallant, A. J.; Mabrook, M. F.; Zeze, D. A.

2012-01-01

A pentacene-based organic metal-insulator-semiconductor memory device, utilizing single walled carbon nanotubes (SWCNTs) for charge storage is reported. SWCNTs were embedded, between SU8 and polymethylmethacrylate to achieve an efficient encapsulation. The devices exhibit capacitance-voltage clockwise hysteresis with a 6 V memory window at ± 30 V sweep voltage, attributed to charging and discharging of SWCNTs. As the applied gate voltage exceeds the SU8 breakdown voltage, charge leakage is induced in SU8 to allow more charges to be stored in the SWCNT nodes. The devices exhibited high storage density (˜9.15 × 1011 cm-2) and demonstrated 94% charge retention due to the superior encapsulation.

Quantum design rules for single molecule logic gates.

PubMed

Renaud, N; Hliwa, M; Joachim, C

2011-08-28

Recent publications have demonstrated how to implement a NOR logic gate with a single molecule using its interaction with two surface atoms as logical inputs [W. Soe et al., ACS Nano, 2011, 5, 1436]. We demonstrate here how this NOR logic gate belongs to the general family of quantum logic gates where the Boolean truth table results from a full control of the quantum trajectory of the electron transfer process through the molecule by very local and classical inputs practiced on the molecule. A new molecule OR gate is proposed for the logical inputs to be also single metal atoms, one per logical input.

Nonvolatile memory thin film transistors using CdSe/ZnS quantum dot-poly(methyl methacrylate) composite layer formed by a two-step spin coating technique

NASA Astrophysics Data System (ADS)

Chen, Ying-Chih; Huang, Chun-Yuan; Yu, Hsin-Chieh; Su, Yan-Kuin

2012-08-01

The nonvolatile memory thin film transistors (TFTs) using a core/shell CdSe/ZnS quantum dot (QD)-poly(methyl methacrylate) (PMMA) composite layer as the floating gate have been demonstrated, with the device configuration of n+-Si gate/SiO2 insulator/QD-PMMA composite layer/pentacene channel/Au source-drain being proposed. To achieve the QD-PMMA composite layer, a two-step spin coating technique was used to successively deposit QD-PMMA composite and PMMA on the insulator. After the processes, the variation of crystal quality and surface morphology of the subsequent pentacene films characterized by x-ray diffraction spectra and atomic force microscopy was correlated to the two-step spin coating. The crystalline size of pentacene was improved from 147.9 to 165.2 Å, while the degree of structural disorder was decreased from 4.5% to 3.1% after the adoption of this technique. In pentacene-based TFTs, the improvement of the performance was also significant, besides the appearances of strong memory characteristics. The memory behaviors were attributed to the charge storage/discharge effect in QD-PMMA composite layer. Under the programming and erasing operations, programmable memory devices with the memory window (Δ Vth) = 23 V and long retention time were obtained.

Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

NASA Astrophysics Data System (ADS)

Riente, Fabrizio; Ziemys, Grazvydas; Mattersdorfer, Clemens; Boche, Silke; Turvani, Giovanna; Raberg, Wolfgang; Luber, Sebastian; Breitkreutz-v. Gamm, Stephan

2017-05-01

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors.

PubMed

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B; Lindau, Manfred; Holowka, David A; Baird, Barbara A; Kan, Edwin C

2015-12-21

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry.

Non-Faradaic Electrochemical Detection of Exocytosis from Mast and Chromaffin Cells Using Floating-Gate MOS Transistors

PubMed Central

Jayant, Krishna; Singhai, Amit; Cao, Yingqiu; Phelps, Joshua B.; Lindau, Manfred; Holowka, David A.; Baird, Barbara A.; Kan, Edwin C.

2015-01-01

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transistor channel from the electrolyte for stable long-term recordings. We measured exocytosis from RBL-2H3 mast cells sensitized by IgE (bound to high-affinity surface receptors FcεRI) and stimulated using the antigen DNP-BSA. Quasi-static I-V measurements reflected a slow shift in surface potential () which was dependent on extracellular calcium ([Ca]o) and buffer strength, which suggests sensitivity to protons released during exocytosis. Fluorescent imaging of dextran-labeled vesicle release showed evidence of a similar time course, while un-sensitized cells showed no response to stimulation. Transient recordings revealed fluctuations with a rapid rise and slow decay. Chromaffin cells stimulated with high KCl showed both slow shifts and extracellular action potentials exhibiting biphasic and inverted capacitive waveforms, indicative of varying ion-channel distributions across the cell-transistor junction. Our approach presents a facile method to simultaneously monitor exocytosis and ion channel activity with high temporal sensitivity without the need for redox chemistry. PMID:26686301

1T Pixel Using Floating-Body MOSFET for CMOS Image Sensors.

PubMed

Lu, Guo-Neng; Tournier, Arnaud; Roy, François; Deschamps, Benoît

2009-01-01

We present a single-transistor pixel for CMOS image sensors (CIS). It is a floating-body MOSFET structure, which is used as photo-sensing device and source-follower transistor, and can be controlled to store and evacuate charges. Our investigation into this 1T pixel structure includes modeling to obtain analytical description of conversion gain. Model validation has been done by comparing theoretical predictions and experimental results. On the other hand, the 1T pixel structure has been implemented in different configurations, including rectangular-gate and ring-gate designs, and variations of oxidation parameters for the fabrication process. The pixel characteristics are presented and discussed.

Temperature driven structural-memory-effects in carbon nanotubes filled with Fe3C nano crystals

NASA Astrophysics Data System (ADS)

Boi, Filippo S.; Zhang, Xiaotian; Corrias, Anna

2018-02-01

We report the observation of novel temperature-driven structural-memory-effects in carbon nanotubes (CNTs) filled with Fe3C nano-crystals. These structural-transitions were measured by means of temperature (T) dependent x-ray diffraction (XRD) in the T-range from 298 K to 12 K. A clear reversible 2θ-shift in the 002-peak of the graphitic-CNTs-walls is found with the decrease of the temperature. As determined by Rietveld refinement, such 2θ-shift translates in a not previously reported decrease in the value of the CNT graphitic c-axis with the decrease of the temperature (from 298 K to 12 K). Also, a clear reversible 2θ-shift in the 031 and 131 diffraction-peaks of Fe3C is observed within the same T-range. Rietveld refinements confirm the existence of such memory-effect and also reveal a gradual decrease of the 010-axis of Fe3C with the decrease of the temperature. These observations imply that the observed structural-memory-effect is a characteristic of CNTs when Fe3C is the encapsulated ferromagnet. The generality of such memory-effects was further confirmed by additional measurements performed on other types of CNTs characterized by continuous Fe3C-filling. XRD measurements in the T-range from 298 K to 673 K revealed also an unusual reversible decrease of the Fe3C-peak intensities with the increase of the temperature. These observations can have important implications on the magnetic data recording applications of these nanostructures by helping in better understanding the unusual temperature-dependent magnetic instabilities of iron-based nano-crystals which have been recently reported in literature.

Instantons in Self-Organizing Logic Gates

NASA Astrophysics Data System (ADS)

Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano

2018-03-01

Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.

[Effects of nano-lead exposure on learning and memory as well as iron homeostasis in brain of offspring rats].

PubMed

Gao, Jing; Su, Hong; Yin, Jingwen; Cao, Fuyuan; Feng, Peipei; Liu, Nan; Xue, Ling; Zheng, Guoying; Li, Qingzhao; Zhang, Yanshu

2015-06-01

To investigate the effects of nano-lead exposure on learning and memory and iron homeostasis in the brain of the offspring rats on postnatal day 21 (PND21) and postnatal day 42 (PND42). Twenty adult pregnant female Sprague-Dawley rats were randomly divided into control group and nano-lead group. Rats in the nano-lead group were orally administrated 10 mg/kg nano-lead, while rats in the control group were administrated an equal volume of normal saline until PND21. On PND21, the offspring rats were weaned and given the same treatment as the pregnant rats until 42 days after birth. The learning and memory ability of offspring rats on PND21 and PND42 was evaluated by Morris water maze test. The hippocampus and cortex s amples of offspring rats on PND21 and PND42 were collected to determine iron and lead levels in the hippocampus and cortex by inductively coupled plasma-mass spectrometry. The distributions of iron in the hippocampus and cortex were observed by Perl's iron staining. The expression levels of ferritin, ferroportin 1 (FPN1), hephaestin (HP), and ceruloplasmin (CP) were measured by enzyme-linked immunosorbent assay. After nano-lead exposure, the iron content in the cortex of offspring rats on PND21 and PND42 in the nano-lead group was significantly higher than those in the control group (32.63 ± 6.03 µg/g vs 27.04 ± 5.82 µg/g, P<0.05; 46.20 ±10.60 µg/g vs 36.61 ± 10.2µg/g, P<0.05). The iron content in the hippocampus of offspring rats on PND42 in the nano-lead group was significantly higher than that in the control group (56.9 ± 4.37µg/g vs 37.71 ± 6.92µg/g, P<0.05). The Perl's staining showed massive iron deposition in the cortex and hippocampus in the nano-lead group. FPNl level in the cotfex of offspring rats on PND21 in the nano-lead group was significantly lower than that in the control group (3.64 ± 0.23 ng/g vs 4.99 ± 0.95 ng/g, P<0.05). FPN1 level in the hippocampus of offspring rats on PND42 in the nano-lead group was significantly

Working memory capacity affects the interference control of distractors at auditory gating.

PubMed

Tsuchida, Yukio; Katayama, Jun'ichi; Murohashi, Harumitsu

2012-05-10

It is important to understand the role of individual differences in working memory capacity (WMC). We investigated the relation between differences in WMC and N1 in event-related brain potentials as a measure of early selective attention for an auditory distractor in three-stimulus oddball tasks that required minimum memory. A high-WMC group (n=13) showed a smaller N1 in response to a distractor and target than did a low-WMC group (n=13) in the novel condition with high distraction. However, in the simple condition with low distraction, there was no difference in N1 between the groups. For all participants (n=52), the correlation between the scores for WMC and N1 peak amplitude was strong for distractors in the novel condition, whereas there was no relation in the simple condition. These results suggest that WMC can predict the interference control for a salient distractor at auditory gating even during a selective attention task. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.

On the Floating Point Performance of the i860 Microprocessor

NASA Technical Reports Server (NTRS)

Lee, King; Kutler, Paul (Technical Monitor)

1997-01-01

The i860 microprocessor is a pipelined processor that can deliver two double precision floating point results every clock. It is being used in the Touchstone project to develop a teraflop computer by the year 2000. With such high computational capabilities it was expected that memory bandwidth would limit performance on many kernels. Measured performance of three kernels showed performance is less than what memory bandwidth limitations would predict. This paper develops a model that explains the discrepancy in terms of memory latencies and points to some problems involved in moving data from memory to the arithmetic pipelines.

A Retina-Like Dual Band Organic Photosensor Array for Filter-Free Near-Infrared-to-Memory Operations.

PubMed

Wang, Hanlin; Liu, Hongtao; Zhao, Qiang; Ni, Zhenjie; Zou, Ye; Yang, Jie; Wang, Lifeng; Sun, Yanqiu; Guo, Yunlong; Hu, Wenping; Liu, Yunqi

2017-08-01

Human eyes use retina photoreceptor cells to absorb and distinguish photons from different wavelengths to construct an image. Mimicry of such a process and extension of its spectral response into the near-infrared (NIR) is indispensable for night surveillance, retinal prosthetics, and medical imaging applications. Currently, NIR organic photosensors demand optical filters to reduce visible interference, thus making filter-free and anti-visible NIR imaging a challenging task. To solve this limitation, a filter-free and conformal, retina-inspired NIR organic photosensor is presented. Featuring an integration of photosensing and floating-gate memory modules, the device possesses an acute color distinguishing capability. In general, the retina-like photosensor transduces NIR (850 nm) into nonvolatile memory and acts as a dynamic photoswitch under green light (550 nm). In doing this, a filter-free but color-distinguishing photosensor is demonstrated that selectively converts NIR optical signals into nonvolatile memory. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Ultralow-power non-volatile memory cells based on P(VDF-TrFE) ferroelectric-gate CMOS silicon nanowire channel field-effect transistors.

PubMed

Van, Ngoc Huynh; Lee, Jae-Hyun; Whang, Dongmok; Kang, Dae Joon

2015-07-21

Nanowire-based ferroelectric-complementary metal-oxide-semiconductor (NW FeCMOS) nonvolatile memory devices were successfully fabricated by utilizing single n- and p-type Si nanowire ferroelectric-gate field effect transistors (NW FeFETs) as individual memory cells. In addition to having the advantages of single channel n- and p-type Si NW FeFET memory, Si NW FeCMOS memory devices exhibit a direct readout voltage and ultralow power consumption. The reading state power consumption of this device is less than 0.1 pW, which is more than 10(5) times lower than the ON-state power consumption of single-channel ferroelectric memory. This result implies that Si NW FeCMOS memory devices are well suited for use in non-volatile memory chips in modern portable electronic devices, especially where low power consumption is critical for energy conservation and long-term use.

Nonvolatile memory thin-film transistors using biodegradable chicken albumen gate insulator and oxide semiconductor channel on eco-friendly paper substrate.

PubMed

Kim, So-Jung; Jeon, Da-Bin; Park, Jung-Ho; Ryu, Min-Ki; Yang, Jong-Heon; Hwang, Chi-Sun; Kim, Gi-Heon; Yoon, Sung-Min

2015-03-04

Nonvolatile memory thin-film transistors (TFTs) fabricated on paper substrates were proposed as one of the eco-friendly electronic devices. The gate stack was composed of chicken albumen gate insulator and In-Ga-Zn-O semiconducting channel layers. All the fabrication processes were performed below 120 °C. To improve the process compatibility of the synthethic paper substrate, an Al2O3 thin film was introduced as adhesion and barrier layers by atomic layer deposition. The dielectric properties of biomaterial albumen gate insulator were also enhanced by the preparation of Al2O3 capping layer. The nonvolatile bistabilities were realized by the switching phenomena of residual polarization within the albumen thin film. The fabricated device exhibited a counterclockwise hysteresis with a memory window of 11.8 V, high on/off ratio of approximately 1.1 × 10(6), and high saturation mobility (μsat) of 11.5 cm(2)/(V s). Furthermore, these device characteristics were not markedly degraded even after the delamination and under the bending situration. When the curvature radius was set as 5.3 cm, the ION/IOFF ratio and μsat were obtained to be 5.9 × 10(6) and 7.9 cm(2)/(V s), respectively.

Unifying Gate Synthesis and Magic State Distillation.

PubMed

Campbell, Earl T; Howard, Mark

2017-02-10

The leading paradigm for performing a computation on quantum memories can be encapsulated as distill-then-synthesize. Initially, one performs several rounds of distillation to create high-fidelity magic states that provide one good T gate, an essential quantum logic gate. Subsequently, gate synthesis intersperses many T gates with Clifford gates to realize a desired circuit. We introduce a unified framework that implements one round of distillation and multiquibit gate synthesis in a single step. Typically, our method uses the same number of T gates as conventional synthesis but with the added benefit of quadratic error suppression. Because of this, one less round of magic state distillation needs to be performed, leading to significant resource savings.

Formation of holographic memory for optically reconfigurable gate array by angle-multiplexing recording of multi-circuit information in liquid crystal composites

NASA Astrophysics Data System (ADS)

Ogiwara, Akifumi; Maekawa, Hikaru; Watanabe, Minoru; Moriwaki, Retsu

2014-02-01

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by the angle-multiplexing recording using a successive laser exposure in liquid crystal (LC) composites. The laser illumination system is constructed using the half mirror and photomask written by the different configuration contexts placed on the motorized stages under the control of a personal computer. The fabricated holographic memory implements a precise reconstruction of configuration contexts corresponding to the various logical circuits such as OR circuit and NOR circuit by the laser illumination at different incident angle in the HPDLC memory.

Novel organic semiconductors and a high capacitance gate dielectric for organic thin film transistors

NASA Astrophysics Data System (ADS)

Cai, Xiuyu

2007-12-01

Organic semiconductors are attracting more and more interest as a promising set of materials in the field of electronics research. This thesis focused on several new organic semiconductors and a novel high-kappa dielectric thin film (SrTiO3), which are two essential parts in Organic Thin Film Transistors (OTFTs). Structure and morphology of thin films of tricyanovinyl capped oligothiophenes were studied using atomic force microscopy and x-ray diffraction. Thin film transistors of one compound exhibited a reasonable electron mobility of 0.02 cm2/Vs. Temperature dependent measurements on the thin film transistor based on this compound revealed shallow trap states that were interpreted in terms of a multiple trap and release model. Moreover, inversion of the majority charge carrier type from electrons to holes was observed when the number of oligothiophene rings increased to six and ambipolar transport behavior was observed for tricyanovinyl sexithiophene. Another interesting organic semiconductor compound is the fluoalkylquarterthiophene, which showed ambipolar transport and large hysteresis in the transfer curve. Due to the bistable state at floating gate, the thin film transistor was exploited to study non-volatile floating gate memory effects. The temperature dependence of the retention time for this memory device revealed that the electron trapping was an activated process. Following the earlier work on hybrid acene-thiophene organic semiconductors, new compounds with similar structure were studied to reveal the mechanism of the air-stability exhibited by some compounds. They all formed highly crystalline thin films and showed reasonable device performances which are well correlated with the molecular structures, thin film microstructures, and solid state packing. The most air-stable compound had no observable degradation with exposure to air for 15 months. SrTiO3 was developed to be employed in OTFTs. Optimization of thin film growth was performed using reactive

Nano-scale surface morphology, wettability and osteoblast adhesion on nitrogen plasma-implanted NiTi shape memory alloy.

PubMed

Liu, X M; Wu, S L; Chu, Paul K; Chung, C Y; Chu, C L; Chan, Y L; Lam, K O; Yeung, K W K; Lu, W W; Cheung, K M C; Luk, K D K

2009-06-01

Plasma immersion ion implantation (PIII) is an effective method to increase the corrosion resistance and inhibit nickel release from orthopedic NiTi shape memory alloy. Nitrogen was plasma-implanted into NiTi using different pulsing frequencies to investigate the effects on the nano-scale surface morphology, structure, wettability, as well as biocompatibility. X-ray photoelectron spectroscopy (XPS) results show that the implantation depth of nitrogen increases with higher pulsing frequencies. Atomic force microscopy (AFM) discloses that the nano-scale surface roughness increases and surface features are changed from islands to spiky cones with higher pulsing frequencies. This variation in the nano surface structures leads to different surface free energy (SFE) monitored by contact angle measurements. The adhesion, spreading, and proliferation of osteoblasts on the implanted NiTi surface are assessed by cell culture tests. Our results indicate that the nano-scale surface morphology that is altered by the implantation frequencies impacts the surface free energy and wettability of the NiTi surfaces, and in turn affects the osteoblast adhesion behavior.

DefenseLink.mil - Special Report - Travels With Gates

Science.gov Websites

Force in Afghanistan to the NATO and partner-nation defense ministers here today.Story New Memorial Attends NATO Defense Ministers' Conference Gates Tours Netherlands American Cemetery and Memorial MEMORIAL DEDICATION - NATO officials dedicate a memorial to those who have lost their lives in alliance operations

Performance Evaluation and Improvement of Ferroelectric Field-Effect Transistor Memory

NASA Astrophysics Data System (ADS)

Yu, Hyung Suk

Flash memory is reaching scaling limitations rapidly due to reduction of charge in floating gates, charge leakage and capacitive coupling between cells which cause threshold voltage fluctuations, short retention times, and interference. Many new memory technologies are being considered as alternatives to flash memory in an effort to overcome these limitations. Ferroelectric Field-Effect Transistor (FeFET) is one of the main emerging candidates because of its structural similarity to conventional FETs and fast switching speed. Nevertheless, the performance of FeFETs have not been systematically compared and analyzed against other competing technologies. In this work, we first benchmark the intrinsic performance of FeFETs and other memories by simulations in order to identify the strengths and weaknesses of FeFETs. To simulate realistic memory applications, we compare memories on an array structure. For the comparisons, we construct an accurate delay model and verify it by benchmarking against exact HSPICE simulations. Second, we propose an accurate model for FeFET memory window since the existing model has limitations. The existing model assumes symmetric operation voltages but it is not valid for the practical asymmetric operation voltages. In this modeling, we consider practical operation voltages and device dimensions. Also, we investigate realistic changes of memory window over time and retention time of FeFETs. Last, to improve memory window and subthreshold swing, we suggest nonplanar junctionless structures for FeFETs. Using the suggested structures, we study the dimensional dependences of crucial parameters like memory window and subthreshold swing and also analyze key interference mechanisms.

A novel cyclic squamosamide analogue compound FLZ improves memory impairment in artificial senescence mice induced by chronic injection of D-galactose and NaNO2.

PubMed

Fang, Fang; Liu, Gengtao

2007-12-01

The aim of the present study was to access the protective effect of a novel synthesized squamosamide cyclic analogue, compound FLZ, on memory impairment in artificially senescent mice induced by chronic injection of D-galactose and sodium nitrite (NaNO(2)). Artificially senescent mouse model was induced by consecutive injection of D-galactose (120 mg/kg) and NaNO(2) (90 mg/kg) once daily for 60 days. Compound FLZ (75 and 150 mg/kg) was orally administered once daily for 30 days after D-galactose and NaNO(2) injection for 30 days. The water maze test was used to evaluate the learning and memory function of mice. The content of malondialdehyde (MDA) and the activities of superoxide dismutase (SOD) and glutathione peroxidase (GSH-Px) in serum were determined using different biochemical kits. The alterations in hippocampus morphology were assessed by light and electronic microscope. Immunoreactive cells of Bcl-2 in the hippocampus were counted by immunohistochemical staining, and Bcl-2 protein expression was analysed by Western blot method. The results indicate that injection of D-galactose and NaNO(2) induces memory impairment and neuronal damage in hippocampus of mice. In addition, serum SOD and GSH-Px activities decreased, while MDA level increased. Bcl-2-positive neurons and Bcl-2 protein expression in the hippocampus decreased remarkably. Oral administration of FLZ for 30 days significantly improved the cognitive deficits and the biochemical markers mentioned above, and also reduced the pathological alterations in mouse hippocampus. The results suggest that FLZ ameliorates memory deficits and pathological injury in artificially senescent mice induced by chronic injection of D-galactose and NaNO(2), indicating that FLZ is worth further studies for fighting antisenescence and dementia.

Graphene quantum dot (GQD)-induced photovoltaic and photoelectric memory elements in a pentacene/GQD field effect transistor as a probe of functional interface

NASA Astrophysics Data System (ADS)

Kim, Youngjun; Cho, Seongeun; Kim, Hyeran; Seo, Soonjoo; Lee, Hyun Uk; Lee, Jouhahn; Ko, Hyungduk; Chang, Mincheol; Park, Byoungnam

2017-09-01

Electric field-induced charge trapping and exciton dissociation were demonstrated at a penatcene/grapheme quantum dot (GQD) interface using a bottom contact bi-layer field effect transistor (FET) as an electrical nano-probe. Large threshold voltage shift in a pentacene/GQD FET in the dark arises from field-induced carrier trapping in the GQD layer or GQD-induced trap states at the pentacene/GQD interface. As the gate electric field increases, hysteresis characterized by the threshold voltage shift depending on the direction of the gate voltage scan becomes stronger due to carrier trapping associated with the presence of a GQD layer. Upon illumination, exciton dissociation and gate electric field-induced charge trapping simultaneously contribute to increase the threshold voltage window, which can potentially be exploited for photoelectric memory and/or photovoltaic devices through interface engineering.

Nanoscale Multigate TiN Metal Nanocrystal Memory Using High-k Blocking Dielectric and High-Work-Function Gate Electrode Integrated on Silcon-on-Insulator Substrate

NASA Astrophysics Data System (ADS)

Lu, Chi-Pei; Luo, Cheng-Kei; Tsui, Bing-Yue; Lin, Cha-Hsin; Tzeng, Pei-Jer; Wang, Ching-Chiun; Tsai, Ming-Jinn

2009-04-01

In this study, a charge-trapping-layer-engineered nanoscale n-channel trigate TiN nanocrystal nonvolatile memory was successfully fabricated on silicon-on-insulator (SOI) wafer. An Al2O3 high-k blocking dielectric layer and a P+ polycrystalline silicon gate electrode were used to obtain low operation voltage and suppress the back-side injection effect, respectively. TiN nanocrystals were formed by annealing TiN/Al2O3 nanolaminates deposited by an atomic layer deposition system. The memory characteristics of various samples with different TiN wetting layer thicknesses, post-deposition annealing times, and blocking oxide thicknesses were also investigated. The sample with a thicker wetting layer exhibited a much larger memory window than other samples owing to its larger nanocrystal size. Good retention with a mere 12% charge loss for up to 10 years and high endurance were also obtained. Furthermore, gate disturbance and read disturbance were measured with very small charge migrations after a 103 s stressing bias.

Leaky Integrate and Fire Neuron by Charge-Discharge Dynamics in Floating-Body MOSFET.

PubMed

Dutta, Sangya; Kumar, Vinay; Shukla, Aditya; Mohapatra, Nihar R; Ganguly, Udayan

2017-08-15

Neuro-biology inspired Spiking Neural Network (SNN) enables efficient learning and recognition tasks. To achieve a large scale network akin to biology, a power and area efficient electronic neuron is essential. Earlier, we had demonstrated an LIF neuron by a novel 4-terminal impact ionization based n+/p/n+ with an extended gate (gated-INPN) device by physics simulation. Excellent improvement in area and power compared to conventional analog circuit implementations was observed. In this paper, we propose and experimentally demonstrate a compact conventional 3-terminal partially depleted (PD) SOI- MOSFET (100 nm gate length) to replace the 4-terminal gated-INPN device. Impact ionization (II) induced floating body effect in SOI-MOSFET is used to capture LIF neuron behavior to demonstrate spiking frequency dependence on input. MHz operation enables attractive hardware acceleration compared to biology. Overall, conventional PD-SOI-CMOS technology enables very-large-scale-integration (VLSI) which is essential for biology scale (~10 11 neuron based) large neural networks.

Wasteway, intake side. The floatoperated radial gates are housed behind ...

Library of Congress Historic Buildings Survey, Historic Engineering Record, Historic Landscapes Survey

Wasteway, intake side. The float-operated radial gates are housed behind the concrete (below water level), view to the northwest - Wellton-Mohawk Irrigation System, Wasteway No. 1, Wellton-Mohawk Canal, North side of Wellton-Mohawk Canal, bounded by Gila River to North & the Union Pacific Railroad & Gila Mountains to south, Wellton, Yuma County, AZ

Type III Neuregulin-1 is required for normal sensorimotor gating, memory related behaviors and cortico-striatal circuit components

PubMed Central

Chen, Ying-Jiun J.; Johnson, Madeleine A.; Lieberman, Michael D.; Goodchild, Rose E.; Schobel, Scott; Lewandowski, Nicole; Rosoklija, Gorazd; Liu, Ruei-Che; Gingrich, Jay A.; Small, Scott; Moore, Holly; Dwork, Andrew J.; Talmage, David A.; Role, Lorna W.

2008-01-01

Neuregulin-1 (Nrg1)/erbB signaling regulates neuronal development, migration, myelination, and synaptic maintenance. The Nrg1 gene is a schizophrenia susceptibility gene. To understand the contribution of Nrg1 signaling to adult brain structure and behaviors, we have studied the regulation of Type III Nrg1 expression and evaluated the effect of decreased expression of the Type III Nrg1 isoforms. Type III Nrg1 is transcribed by a promoter distinct from those for other Nrg1 isoforms and, in the adult brain, is expressed in the medial prefrontal cortex, ventral hippocampus and ventral subiculum, regions involved in the regulation of sensorimotor gating and short term memory. Adult heterozygous mutant mice with a targeted disruption for Type III Nrg1 (Nrg1tm1.1Lwr+/-) have enlarged lateral ventricles and decreased dendritic spine density on subicular pyramidal neurons. MRI imaging of Type III Nrg1 heterozygous mice revealed hypo-function in the medial prefrontal cortex and the hippocampal CA1 and subiculum regions. Type III Nrg1 heterozygous mice also have impaired performance on delayed alternation memory tasks, and deficits in prepulse inhibition (PPI). Chronic nicotine treatment eliminated differences in PPI between Type III Nrg1 heterozygous mice and their wild type littermates. Our findings demonstrate a role of Type III Nrg1-signaling in the maintenance of cortico-striatal components, and in the neural circuits involved in sensorimotor gating and short term memory. PMID:18596162

Random Telegraph Signal-Like Fluctuation Created by Fowler-Nordheim Stress in Gate Induced Drain Leakage Current of the Saddle Type Dynamic Random Access Memory Cell Transistor

NASA Astrophysics Data System (ADS)

Kim, Heesang; Oh, Byoungchan; Kim, Kyungdo; Cha, Seon-Yong; Jeong, Jae-Goan; Hong, Sung-Joo; Lee, Jong-Ho; Park, Byung-Gook; Shin, Hyungcheol

2010-09-01

We generated traps inside gate oxide in gate-drain overlap region of recess channel type dynamic random access memory (DRAM) cell transistor through Fowler-Nordheim (FN) stress, and observed gate induced drain leakage (GIDL) current both in time domain and in frequency domain. It was found that the trap inside gate oxide could generate random telegraph signal (RTS)-like fluctuation in GIDL current. The characteristics of that fluctuation were similar to those of RTS-like fluctuation in GIDL current observed in the non-stressed device. This result shows the possibility that the trap causing variable retention time (VRT) in DRAM data retention time can be located inside gate oxide like channel RTS of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Novel nano materials for high performance logic and memory devices

NASA Astrophysics Data System (ADS)

Das, Saptarshi

After decades of relentless progress, the silicon CMOS industry is approaching a stall in device performance for both logic and memory devices due to fundamental scaling limitations. In order to reinforce the accelerating pace, novel materials with unique properties are being proposed on an urgent basis. This list includes one dimensional nanotubes, quasi one dimensional nanowires, two dimensional atomistically thin layered materials like graphene, hexagonal boron nitride and the more recently the rich family of transition metal di-chalcogenides comprising of MoS2, WSe2, WS2 and many more for logic applications and organic and inorganic ferroelectrics, phase change materials and magnetic materials for memory applications. Only time will tell who will win, but exploring these novel materials allow us to revisit the fundamentals and strengthen our understanding which will ultimately be beneficial for high performance device design. While there has been growing interest in two-dimensional (2D) crystals other than graphene, evaluating their potential usefulness for electronic applications is still in its infancies due to the lack of a complete picture of their performance potential. The fact that the 2-D layered semiconducting di-chalcogenides need to be connected to the "outside" world in order to capitalize on their ultimate potential immediately emphasizes the importance of a thorough understanding of the contacts. This thesis demonstrate that through a proper understanding and design of source/drain contacts and the right choice of number of MoS2 layers the excellent intrinsic properties of this 2D material can be harvested. A comprehensive experimental study on the dependence of carrier mobility on the layer thickness of back gated multilayer MoS 2 field effect transistors is also provided. A resistor network model that comprises of Thomas-Fermi charge screening and interlayer coupling is used to explain the non-monotonic trend in the extracted field effect

The Role of Anterior Nuclei of the Thalamus: A Subcortical Gate in Memory Processing: An Intracerebral Recording Study.

PubMed

Štillová, Klára; Jurák, Pavel; Chládek, Jan; Chrastina, Jan; Halámek, Josef; Bočková, Martina; Goldemundová, Sabina; Říha, Ivo; Rektor, Ivan

2015-01-01

To study the involvement of the anterior nuclei of the thalamus (ANT) as compared to the involvement of the hippocampus in the processes of encoding and recognition during visual and verbal memory tasks. We studied intracerebral recordings in patients with pharmacoresistent epilepsy who underwent deep brain stimulation (DBS) of the ANT with depth electrodes implanted bilaterally in the ANT and compared the results with epilepsy surgery candidates with depth electrodes implanted bilaterally in the hippocampus. We recorded the event-related potentials (ERPs) elicited by the visual and verbal memory encoding and recognition tasks. P300-like potentials were recorded in the hippocampus by visual and verbal memory encoding and recognition tasks and in the ANT by the visual encoding and visual and verbal recognition tasks. No significant ERPs were recorded during the verbal encoding task in the ANT. In the visual and verbal recognition tasks, the P300-like potentials in the ANT preceded the P300-like potentials in the hippocampus. The ANT is a structure in the memory pathway that processes memory information before the hippocampus. We suggest that the ANT has a specific role in memory processes, especially memory recognition, and that memory disturbance should be considered in patients with ANT-DBS and in patients with ANT lesions. ANT is well positioned to serve as a subcortical gate for memory processing in cortical structures.

Quantum ballistic analysis of transition metal dichalcogenides based double gate junctionless field effect transistor and its application in nano-biosensor

NASA Astrophysics Data System (ADS)

Shadman, Abir; Rahman, Ehsanur; Khosru, Quazi D. M.

2017-11-01

To reduce the thermal budget and the short channel effects in state of the art CMOS technology, Junctionless field effect transistor (JLFET) has been proposed in the literature. Numerous experimental, modeling, and simulation based works have been done on this new FET with bulk materials for various geometries until now. On the other hand, the two-dimensional layered material is considered as an alternative to current Si technology because of its ultra-thin body and high mobility. Very recently few simulation based works have been done on monolayer molybdenum disulfide based JLFET mainly to show the advantage of JLFET over conventional FET. However, no comprehensive simulation-based work has been done for double gate JLFET keeping in mind the prominent transition metal dichalcogenides (TMDC) to the authors' best knowledge. In this work, we have studied quantum ballistic drain current-gate voltage characteristics of such FETs within non-equilibrium Green's function (NEGF) framework. Our simulation results reveal that all these TMDC materials are viable options for implementing state of the art Junctionless MOSFET with emphasis on their performance at short gate lengths. Besides evaluating the prospect of TMDC materials in the digital logic application, the performance of Junctionless Double Gate trilayer TMDC heterostructure FET for the label-free electrical detection of biomolecules in dry environment has been investigated for the first time to the authors' best knowledge. The impact of charge neutral biomolecules on the electrical characteristics of the biosensor has been analyzed under dry environment situation. Our study shows that these materials could provide high sensitivity in the sub-threshold region as a channel material in nano-biosensor, a trend demonstrated by silicon on insulator FET sensor in the literature. Thus, going by the trend of replacing silicon with these novel materials in device level, TMDC heterostructure could be a viable alternative to

Depletion type floating gate p-channel MOS transistor for recording action potentials generated by cultured neurons.

PubMed

Cohen, Ariel; Spira, Micha E; Yitshaik, Shlomo; Borghs, Gustaaf; Shwartzglass, Ofer; Shappir, Joseph

2004-07-15

We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline silicon (PS) FG through 420A thermal oxide in an area which is located over the thick field oxide away from the transistor. The combination of coupling area pad having a diameter of 10 or 15 microm and sensing transistor with W/L of 50/0.5 microm results in capacitive coupling ratio of the neuron signal of about 0.5 together with relatively large transistor transconductance. The combination of the FG structure with a depletion type device, leads to the following advantages. (a) No need for dc bias between the solution in which the neurons are cultured and the transistor with expected consequences to the neuron as well as the silicon die durability. (b) The sensing area of the neuron activity is separated from the active area of the transistor. Thus, it is possible to design the sensing area and the channel area separately. (c) The channel area, which is the most sensitive part of the transistor, can be insulated and shielded from the ionic solution in which the neurons are cultured. (d) There is an option to add a switching transistor to the FG and use the FG also for the neuron stimulation.

Nano-textured high sensitivity ion sensitive field effect transistors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hajmirzaheydarali, M.; Sadeghipari, M.; Akbari, M.

2016-02-07

Nano-textured gate engineered ion sensitive field effect transistors (ISFETs), suitable for high sensitivity pH sensors, have been realized. Utilizing a mask-less deep reactive ion etching results in ultra-fine poly-Si features on the gate of ISFET devices where spacing of the order of 10 nm and less is achieved. Incorporation of these nano-sized features on the gate is responsible for high sensitivities up to 400 mV/pH in contrast to conventional planar structures. The fabrication process for this transistor is inexpensive, and it is fully compatible with standard complementary metal oxide semiconductor fabrication procedure. A theoretical modeling has also been presented to predict themore » extension of the diffuse layer into the electrolyte solution for highly featured structures and to correlate this extension with the high sensitivity of the device. The observed ultra-fine features by means of scanning electron microscopy and transmission electron microscopy tools corroborate the theoretical prediction.« less

The Role of Anterior Nuclei of the Thalamus: A Subcortical Gate in Memory Processing: An Intracerebral Recording Study

PubMed Central

Štillová, Klára; Jurák, Pavel; Chládek, Jan; Chrastina, Jan; Halámek, Josef; Bočková, Martina; Goldemundová, Sabina; Říha, Ivo; Rektor, Ivan

2015-01-01

Objective To study the involvement of the anterior nuclei of the thalamus (ANT) as compared to the involvement of the hippocampus in the processes of encoding and recognition during visual and verbal memory tasks. Methods We studied intracerebral recordings in patients with pharmacoresistent epilepsy who underwent deep brain stimulation (DBS) of the ANT with depth electrodes implanted bilaterally in the ANT and compared the results with epilepsy surgery candidates with depth electrodes implanted bilaterally in the hippocampus. We recorded the event-related potentials (ERPs) elicited by the visual and verbal memory encoding and recognition tasks. Results P300-like potentials were recorded in the hippocampus by visual and verbal memory encoding and recognition tasks and in the ANT by the visual encoding and visual and verbal recognition tasks. No significant ERPs were recorded during the verbal encoding task in the ANT. In the visual and verbal recognition tasks, the P300-like potentials in the ANT preceded the P300-like potentials in the hippocampus. Conclusions The ANT is a structure in the memory pathway that processes memory information before the hippocampus. We suggest that the ANT has a specific role in memory processes, especially memory recognition, and that memory disturbance should be considered in patients with ANT-DBS and in patients with ANT lesions. ANT is well positioned to serve as a subcortical gate for memory processing in cortical structures. PMID:26529407

A hardware-oriented algorithm for floating-point function generation

NASA Technical Reports Server (NTRS)

O'Grady, E. Pearse; Young, Baek-Kyu

1991-01-01

An algorithm is presented for performing accurate, high-speed, floating-point function generation for univariate functions defined at arbitrary breakpoints. Rapid identification of the breakpoint interval, which includes the input argument, is shown to be the key operation in the algorithm. A hardware implementation which makes extensive use of read/write memories is used to illustrate the algorithm.

Ultrasonic agitation-floating classification of nano-sized Ba-Mg ferrites particles formed by using self-propagating high temperature synthesis and fabrication of nickel-ferrites thin sheet by pulse-electroforming.

PubMed

Choi, Yong

2013-01-01

Nickel-nano-sized ferrites composites sheet for electromagnetic shielding was produced by pulse-electroforming in a modified nickel sulfamate solution. The ferrite particles were prepared by self-propagating high temperature synthesis (SHS) followed by mechanical milling, and classified with an ultrasonic agitation-floating unit to obtain about 100 nm in size. Average combustion temperature and combustion propagating rate during SHS reaction were 1190 K and 5.8 mm/sec at the oxygen pressure of 1.0 MPa, respectively. The nickel-ferrite composite sheet had preferred orientation which (100) pole clearly concentrated to normal direction, whereas, (110) and (111) poles tended to split to the longitudinal direction, respectively. Maximum magnetization, residual magnetization and coercive force of the nano-sized ferrites were 27.13 A x m2/kg, 6.4 A x m2/kg and 14.58 kA/m, respectively. Complex permeability of the composites decreased with an increase in frequency, and its real value (mu'r) had the maximum at about 0.3 GHz. The dielectric constants of the composites were epsilon'r = 6.7 and epsilon"r = 0.

Development and calibration of an air-floating six-axis force measurement platform using self-calibration

NASA Astrophysics Data System (ADS)

Huang, Bin; Wang, Xiaomeng; Li, Chengwei; Yi, Jiajing; Lu, Rongsheng; Tao, Jiayue

2016-09-01

This paper describes the design, working principle, as well as calibration of an air-floating six-axis force measurement platform, where the floating plate and nozzles were connected without contact, preventing inter-dimensional coupling and increasing precision significantly. The measurement repeatability error of the force size in the platform is less than 0.2% full scale (FS), which is significantly better than the precision of 1% FS in the six-axis force sensors on the current market. We overcame the difficulties of weight loading device in high-precision calibration by proposing a self-calibration method based on the floating plate gravity and met the calibration precision requirement of 0.02% FS. This study has general implications for the development and calibration of high-precision multi-axis force sensors. In particular, the air-floating six-axis force measurement platform could be applied to the calibration of some special sensors such as flexible tactile sensors and may be used as a micro-nano mechanical assembly platform for real-time assembly force testing.

Charge retention characteristics of silicide-induced crystallized polycrystalline silicon floating gate thin-film transistors for active matrix organic light-emitting diode.

PubMed

Park, Jae Hyo; Son, Se Wan; Byun, Chang Woo; Kim, Hyung Yoon; Joo, So Na; Lee, Yong Woo; Yun, Seung Jae; Joo, Seung Ki

2013-10-01

In this work, non-volatile memory thin-film transistor (NVM-TFT) was fabricated by nickel silicide-induced laterally crystallized (SILC) polycrystalline silicon (poly-Si) as the active layer. The nickel seed silicide-induced crystallized (SIC) poly-Si was used as storage layer which is embedded in the gate insulator. The novel unit pixel of active matrix organic light-emitting diode (AMOLED) using NVM-TFT is proposed and investigated the electrical and optical performance. The threshold voltage shift showed 17.2 V and the high reliability of retention characteristic was demonstrated until 10 years. The retention time can modulate the recharge refresh time of the unit pixel of AMOLED up to 5000 sec.

Locomotor activity, emotionality, sensori-motor gating, learning and memory in the APPswe/PS1dE9 mouse model of Alzheimer's disease.

PubMed

O'Leary, Timothy P; Hussin, Ahmed T; Gunn, Rhian K; Brown, Richard E

2018-06-02

The APPswe/PS1dE9 mouse (line 85) is a double transgenic model of Alzheimer's disease (AD) with familial amyloid precursor protein and presenilin-1 mutations. These mice develop age-related behavioral changes reflective of the neuropsychiatric symptoms (altered anxiety-like behaviour, hyperactivity) and cognitive dysfunction (impaired learning and memory) observed in AD. The APPswe/PS1dE9 mouse has been used to examine the efficacy of therapeutic interventions on behaviour, despite previous difficulties in replicating behavioural phenotypes. Therefore, the purpose of this study was to establish the reliability of these phenotypes by further characterizing the behaviour of male APPswe/PS1dE9 and wild-type mice between 7 and 14 months of age. Mice were tested on the open-field over 5-days to examine emotionality, locomotor activity and inter-session habituation. Mice were also tested on the repeated-reversal water maze task and spontaneous alternation on the Y-maze to assess working memory. Sensori-motor gating was examined with acoustic startle and pre-pulse inhibition. Lastly contextual and cued (trace) memory was assessed with fear conditioning. The results show that among non-cognitive behaviours, APPswe/PS1dE9 mice have normal locomotor activity, anxiety-like behavior, habituation and sensori-motor gating. However, APPswe/PS1dE9 mice show impaired working memory on the repeated-reversal water-maze and impaired memory in contextual but not trace-cued fear conditioning. These results indicate that the APPswe/PS1dE9 (line 85) mice have deficits in some types of hippocampal-dependent learning and memory and, at the ages tested, APPswe/PS1dE9 mice model cognitive dysfunction but not neuropsychiatric symptoms. Copyright © 2018. Published by Elsevier Inc.

A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations

NASA Astrophysics Data System (ADS)

Ibrahim, Walid; Beiu, Valeriu

As the sizes of (nano-)devices are aggressively scaled deep into the nanometer range, the design and manufacturing of future (nano-)circuits will become extremely complex and inevitably will introduce more defects while their functioning will be adversely affected by transient faults. Therefore, accurately calculating the reliability of future designs will become a very important aspect for (nano-)circuit designers as they investigate several design alternatives to optimize the trade-offs between the conflicting metrics of area-power-energy-delay versus reliability. This paper introduces a novel generic technique for the accurate calculation of the reliability of future nano-circuits. Our aim is to provide both educational and research institutions (as well as the semiconductor industry at a later stage) with an accurate and easy to use tool for closely comparing the reliability of different design alternatives, and for being able to easily select the design that best fits a set of given (design) constraints. Moreover, the reliability model generated by the tool should empower designers with the unique opportunity of understanding the influence individual gates play on the design’s overall reliability, and identifying those (few) gates which impact the design’s reliability most significantly.

The use of ZFP lossy floating point data compression in tornado-resolving thunderstorm simulations

NASA Astrophysics Data System (ADS)

Orf, L.

2017-12-01

In the field of atmospheric science, numerical models are used to produce forecasts of weather and climate and serve as virtual laboratories for scientists studying atmospheric phenomena. In both operational and research arenas, atmospheric simulations exploiting modern supercomputing hardware can produce a tremendous amount of data. During model execution, the transfer of floating point data from memory to the file system is often a significant bottleneck where I/O can dominate wallclock time. One way to reduce the I/O footprint is to compress the floating point data, which reduces amount of data saved to the file system. In this presentation we introduce LOFS, a file system developed specifically for use in three-dimensional numerical weather models that are run on massively parallel supercomputers. LOFS utilizes the core (in-memory buffered) HDF5 driver and includes compression options including ZFP, a lossy floating point data compression algorithm. ZFP offers several mechanisms for specifying the amount of lossy compression to be applied to floating point data, including the ability to specify the maximum absolute error allowed in each compressed 3D array. We explore different maximum error tolerances in a tornado-resolving supercell thunderstorm simulation for model variables including cloud and precipitation, temperature, wind velocity and vorticity magnitude. We find that average compression ratios exceeding 20:1 in scientifically interesting regions of the simulation domain produce visually identical results to uncompressed data in visualizations and plots. Since LOFS splits the model domain across many files, compression ratios for a given error tolerance can be compared across different locations within the model domain. We find that regions of high spatial variability (which tend to be where scientifically interesting things are occurring) show the lowest compression ratios, whereas regions of the domain with little spatial variability compress

A High-Performance Optical Memory Array Based on Inhomogeneity of Organic Semiconductors.

PubMed

Pei, Ke; Ren, Xiaochen; Zhou, Zhiwen; Zhang, Zhichao; Ji, Xudong; Chan, Paddy Kwok Leung

2018-03-01

Organic optical memory devices keep attracting intensive interests for diverse optoelectronic applications including optical sensors and memories. Here, flexible nonvolatile optical memory devices are developed based on the bis[1]benzothieno[2,3-d;2',3'-d']naphtho[2,3-b;6,7-b']dithiophene (BBTNDT) organic field-effect transistors with charge trapping centers induced by the inhomogeneity (nanosprouts) of the organic thin film. The devices exhibit average mobility as high as 7.7 cm 2 V -1 s -1 , photoresponsivity of 433 A W -1 , and long retention time for more than 6 h with a current ratio larger than 10 6 . Compared with the standard floating gate memory transistors, the BBTNDT devices can reduce the fabrication complexity, cost, and time. Based on the reasonable performance of the single device on a rigid substrate, the optical memory transistor is further scaled up to a 16 × 16 active matrix array on a flexible substrate with operating voltage less than 3 V, and it is used to map out 2D optical images. The findings reveal the potentials of utilizing [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives as organic semiconductors for high-performance optical memory transistors with a facile structure. A detailed study on the charge trapping mechanism in the derivatives of BTBT materials is also provided, which is closely related to the nanosprouts formed inside the organic active layer. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Scanning gate study of organic thin-film field-effect transistor

NASA Astrophysics Data System (ADS)

Aoki, N.; Sudou, K.; Matsusaki, K.; Okamoto, K.; Ochiai, Y.

2008-03-01

Scanning gate microscopy (SGM) has been applied for a study of organic thin-film field effect transistor (OFET). In contrast to one-dimensional nano-material such a carbon nanonube or nano-structure such a quantum point contact, visualization a transport characteristic of OFET channel is basically rather difficult since the channel width is much larger than the size of the SGM tip. Nevertheless, Schottky barriers are successfully visualized at the boundary between the metal electrodes and the OFET channel at ambient atmosphere.

CMOS gate array characterization procedures

NASA Astrophysics Data System (ADS)

Spratt, James P.

1993-09-01

Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

Distributed multiport memory architecture

NASA Technical Reports Server (NTRS)

Kohl, W. H. (Inventor)

1983-01-01

A multiport memory architecture is diclosed for each of a plurality of task centers connected to a command and data bus. Each task center, includes a memory and a plurality of devices which request direct memory access as needed. The memory includes an internal data bus and an internal address bus to which the devices are connected, and direct timing and control logic comprised of a 10-state ring counter for allocating memory devices by enabling AND gates connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter which serially shifts onto the command and data bus, a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.

Floating electrode dielectrophoresis.

PubMed

Golan, Saar; Elata, David; Orenstein, Meir; Dinnar, Uri

2006-12-01

In practice, dielectrophoresis (DEP) devices are based on micropatterned electrodes. When subjected to applied voltages, the electrodes generate nonuniform electric fields that are necessary for the DEP manipulation of particles. In this study, electrically floating electrodes are used in DEP devices. It is demonstrated that effective DEP forces can be achieved by using floating electrodes. Additionally, DEP forces generated by floating electrodes are different from DEP forces generated by excited electrodes. The floating electrodes' capabilities are explained theoretically by calculating the electric field gradients and demonstrated experimentally by using test-devices. The test-devices show that floating electrodes can be used to collect erythrocytes (red blood cells). DEP devices which contain many floating electrodes ought to have fewer connections to external signal sources. Therefore, the use of floating electrodes may considerably facilitate the fabrication and operation of DEP devices. It can also reduce device dimensions. However, the key point is that DEP devices can integrate excited electrodes fabricated by microtechnology processes and floating electrodes fabricated by nanotechnology processes. Such integration is expected to promote the use of DEP devices in the manipulation of nanoparticles.

An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors

NASA Astrophysics Data System (ADS)

Mirdha, P.; Parthasarathy, B.; Kondo, J.; Chan, P.-Y.; Heller, E.; Jain, F. C.

2018-02-01

Site-specific self-assembled colloidal quantum dots (QDs) will deposit in two layers only on p-type substrate to form a QD superlattice (QDSL). The QDSL structure has been integrated into the floating gate of a nonvolatile memory component and has demonstrated promising results in multi-bit storage, ease of fabrication, and memory retention. Additionally, multi-valued logic devices and circuits have been created by using QDSL structures which demonstrated ternary and quaternary logic. With increasing use of site-specific self-assembled QDSLs, fundamental understanding of silicon and germanium QDSL charge storage capability, self-assembly on specific surfaces, uniform distribution, and mini-band formation has to be understood for successful implementation in devices. In this work, we investigate the differences in electron charge storage by building metal-oxide semiconductor (MOS) capacitors and using capacitance and voltage measurements to quantify the storage capabilities. The self-assembly process and distribution density of the QDSL is done by obtaining atomic force microscopy (AFM) results on line samples. Additionally, we present a summary of the theoretical density of states in each of the QDSLs.

Memory operation mechanism of fullerene-containing polymer memory

DOE Office of Scientific and Technical Information (OSTI.GOV)

Nakajima, Anri, E-mail: anakajima@hiroshima-u.ac.jp; Fujii, Daiki

2015-03-09

The memory operation mechanism in fullerene-containing nanocomposite gate insulators was investigated while varying the kind of fullerene in a polymer gate insulator. It was cleared what kind of traps and which positions in the nanocomposite the injected electrons or holes are stored in. The reason for the difference in the easiness of programming was clarified taking the role of the charging energy of an injected electron into account. The dependence of the carrier dynamics on the kind of fullerene molecule was investigated. A nonuniform distribution of injected carriers occurred after application of a large magnitude programming voltage due to themore » width distribution of the polystyrene barrier between adjacent fullerene molecules. Through the investigations, we demonstrated a nanocomposite gate with fullerene molecules having excellent retention characteristics and a programming capability. This will lead to the realization of practical organic memories with fullerene-containing polymer nanocomposites.« less

Printable Top-Gate-Type Polymer Light-Emitting Transistors with Surfaces of Amorphous Fluoropolymer Insulators Modified by Vacuum Ultraviolet Light Treatment

NASA Astrophysics Data System (ADS)

Kajii, Hirotake; Terashima, Daiki; Kusumoto, Yusuke; Ikezoe, Ikuya; Ohmori, Yutaka

2013-04-01

We investigated the fabrication and electrical and optical properties of top-gate-type polymer light-emitting transistors with the surfaces of amorphous fluoropolymer insulators, CYTOP (Asahi Glass) modified by vacuum ultraviolet light (VUV) treatment. The surface energy of CYTOP, which has a good solution barrier property was increased by VUV irradiation, and the gate electrode was fabricated by solution processing on the CYTOP film using the Ag nano-ink. The influence of VUV irradiation on the optical properties of poly(9,9-dioctylfluorene-co-benzothiadiazole) (F8BT) films with various gate insulators was investigated to clarify the passivation effect of gate insulators. It was found that the poly(methyl methacrylate) (PMMA) film prevented the degradation of the F8BT layer under VUV irradiation because the PMMA film can absorb VUV. The solution-processed F8BT device with multilayer PMMA/CYTOP insulators utilizing a gate electrode fabricated using the Ag nano-ink exhibited both the ambipolar characteristics and yellow-green emission.

A floating-point/multiple-precision processor for airborne applications

NASA Technical Reports Server (NTRS)

Yee, R.

1982-01-01

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Ontogeny of sensorimotor gating and short-term memory processing throughout the adolescent period in rats.

PubMed

Goepfrich, Anja A; Friemel, Chris M; Pauen, Sabina; Schneider, Miriam

2017-06-01

Adolescence and puberty are highly susceptible developmental periods during which the neuronal organization and maturation of the brain is completed. The endocannabinoid (eCB) system, which is well known to modulate cognitive processing, undergoes profound and transient developmental changes during adolescence. With the present study we were aiming to examine the ontogeny of cognitive skills throughout adolescence in male rats and clarify the potential modulatory role of CB1 receptor signalling. Cognitive skills were assessed repeatedly every 10th day in rats throughout adolescence. All animals were tested for object recognition memory and prepulse inhibition of the acoustic startle reflex. Although cognitive performance in short-term memory as well as sensorimotor gating abilities were decreased during puberty compared to adulthood, both tasks were found to show different developmental trajectories throughout adolescence. A low dose of the CB1 receptor antagonist/inverse agonist SR141716 was found to improve recognition memory specifically in pubertal animals while not affecting behavioral performance at other ages tested. The present findings demonstrate that the developmental trajectory of cognitive abilities does not occur linearly for all cognitive processes and is strongly influenced by pubertal maturation. Developmental alterations within the eCB system at puberty onset may be involved in these changes in cognitive processing. Copyright © 2016 The Authors. Published by Elsevier Ltd.. All rights reserved.

Vertical bloch line memory

NASA Technical Reports Server (NTRS)

Katti, Romney R. (Inventor); Stadler, Henry L. (Inventor); Wu, Jiin-chuan (Inventor)

1995-01-01

A new read gate design for the vertical Bloch line (VBL) memory is disclosed which offers larger operating margin than the existing read gate designs. In the existing read gate designs, a current is applied to all the stripes. The stripes that contain a VBL pair are chopped, while the stripes that do not contain a VBL pair are not chopped. The information is then detected by inspecting the presence or absence of the bubble. The margin of the chopping current amplitude is very small, and sometimes non-existent. A new method of reading Vertical Bloch Line memory is also disclosed. Instead of using the wall chirality to separate the two binary states, the spatial deflection of the stripe head is used. Also disclosed herein is a compact memory which uses vertical Bloch line (VBL) memory technology for providing data storage. A three-dimensional arrangement in the form of stacks of VBL memory layers is used to achieve high volumetric storage density. High data transfer rate is achieved by operating all the layers in parallel. Using Hall effect sensing, and optical sensing via the Faraday effect to access the data from within the three-dimensional packages, an even higher data transfer rate can be achieved due to parallel operation within each layer.

Memory in a fractional-order cardiomyocyte model alters properties of alternans and spontaneous activity

NASA Astrophysics Data System (ADS)

Comlekoglu, T.; Weinberg, S. H.

2017-09-01

Cardiac memory is the dependence of electrical activity on the prior history of one or more system state variables, including transmembrane potential (Vm), ionic current gating, and ion concentrations. While prior work has represented memory either phenomenologically or with biophysical detail, in this study, we consider an intermediate approach of a minimal three-variable cardiomyocyte model, modified with fractional-order dynamics, i.e., a differential equation of order between 0 and 1, to account for history-dependence. Memory is represented via both capacitive memory, due to fractional-order Vm dynamics, that arises due to non-ideal behavior of membrane capacitance; and ionic current gating memory, due to fractional-order gating variable dynamics, that arises due to gating history-dependence. We perform simulations for varying Vm and gating variable fractional-orders and pacing cycle length and measure action potential duration (APD) and incidence of alternans, loss of capture, and spontaneous activity. In the absence of ionic current gating memory, we find that capacitive memory, i.e., decreased Vm fractional-order, typically shortens APD, suppresses alternans, and decreases the minimum cycle length (MCL) for loss of capture. However, in the presence of ionic current gating memory, capacitive memory can prolong APD, promote alternans, and increase MCL. Further, we find that reduced Vm fractional order (typically less than 0.75) can drive phase 4 depolarizations that promote spontaneous activity. Collectively, our results demonstrate that memory reproduced by a fractional-order model can play a role in alternans formation and pacemaking, and in general, can greatly increase the range of electrophysiological characteristics exhibited by a minimal model.

Analysis of power gating in different hierarchical levels of 2MB cache, considering variation

NASA Astrophysics Data System (ADS)

Jafari, Mohsen; Imani, Mohsen; Fathipour, Morteza

2015-09-01

This article reintroduces power gating technique in different hierarchical levels of static random-access memory (SRAM) design including cell, row, bank and entire cache memory in 16 nm Fin field effect transistor. Different structures of SRAM cells such as 6T, 8T, 9T and 10T are used in design of 2MB cache memory. The power reduction of the entire cache memory employing cell-level optimisation is 99.7% with the expense of area and other stability overheads. The power saving of the cell-level optimisation is 3× (1.2×) higher than power gating in cache (bank) level due to its superior selectivity. The access delay times are allowed to increase by 4% in the same energy delay product to achieve the best power reduction for each supply voltages and optimisation levels. The results show the row-level power gating is the best for optimising the power of the entire cache with lowest drawbacks. Comparisons of cells show that the cells whose bodies have higher power consumption are the best candidates for power gating technique in row-level optimisation. The technique has the lowest percentage of saving in minimum energy point (MEP) of the design. The power gating also improves the variation of power in all structures by at least 70%.

Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

DOE Office of Scientific and Technical Information (OSTI.GOV)

Ramalingam, Balavinayagam; Zheng, Haisheng; Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attainedmore » with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.« less

Thermal annealing and temperature dependences of memory effect in organic memory transistor

NASA Astrophysics Data System (ADS)

Ren, X. C.; Wang, S. M.; Leung, C. W.; Yan, F.; Chan, P. K. L.

2011-07-01

We investigate the annealing and thermal effects of organic non-volatile memory with floating silver nanoparticles by real-time transfer curve measurements. During annealing, the memory window shows shrinkage of 23% due to structural variation of the nanoparticles. However, by increasing the device operating temperature from 20 to 90 °C after annealing, the memory window demonstrates an enlargement up to 100%. The differences in the thermal responses are explained and confirmed by the co-existence of electron and hole traps. Our findings provide a better understanding of organic memory performances under various operating temperatures and validate their applications for temperature sensing or thermal memories.

Utilizing Controlled Vibrations in a Microgravity Environment to Understand and Promote Microstructural Homogeneity During Floating-Zone Crystal Growth

NASA Technical Reports Server (NTRS)

Anilkumar, A. V.; Bhowmick, J.; Grugel, R. N.

2001-01-01

Our previous experiments with NaNO3 float-zones revealed that steady thermocapillary flow can be balanced/offset by the controlled surface streaming flow induced by end-wall vibration. In the current experiments we are examining the effects of streaming flow on steadying/stabilizing nonsteady thermocapillary flow in such zones. To this effect we have set up a controlled NaNO3 half-zone experiment, where the processing parameters, like zone dimensions and temperature gradients, can be easily varied to generate nonsteady thermocapillary flows. In the present paper we present preliminary results of our investigations into stabilizing such flows by employing endwall vibration.

Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window

NASA Astrophysics Data System (ADS)

Kino, Hisashi; Fukushima, Takafumi; Tanaka, Tetsu

2018-04-01

Charge-trapping memory requires the increase of bit density per cell and a larger memory window for lower-power operation. A tunnel field-effect transistor (TFET) can achieve to increase the bit density per cell owing to its steep subthreshold slope. In addition, a TFET structure has an asymmetric structure, which is promising for achieving a larger memory window. A TFET with the N-type gate shows a higher electric field between the P-type source and the N-type gate edge than the conventional FET structure. This high electric field enables large amounts of charges to be injected into the charge storage layer. In this study, we fabricated silicon-oxide-nitride-oxide-semiconductor (SONOS) memory devices with the TFET structure and observed a steep subthreshold slope and a larger memory window.

40 CFR 65.45 - External floating roof converted into an internal floating roof.

Code of Federal Regulations, 2010 CFR

2010-07-01

... External floating roof converted into an internal floating roof. The owner or operator who elects to... 40 Protection of Environment 15 2010-07-01 2010-07-01 false External floating roof converted into an internal floating roof. 65.45 Section 65.45 Protection of Environment ENVIRONMENTAL PROTECTION...

CT image reconstruction with half precision floating-point values.

PubMed

Maaß, Clemens; Baer, Matthias; Kachelrieß, Marc

2011-07-01

Analytic CT image reconstruction is a computationally demanding task. Currently, the even more demanding iterative reconstruction algorithms find their way into clinical routine because their image quality is superior to analytic image reconstruction. The authors thoroughly analyze a so far unconsidered but valuable tool of tomorrow's reconstruction hardware (CPU and GPU) that allows implementing the forward projection and backprojection steps, which are the computationally most demanding parts of any reconstruction algorithm, much more efficiently. Instead of the standard 32 bit floating-point values (float), a recently standardized floating-point value with 16 bit (half) is adopted for data representation in image domain and in rawdata domain. The reduction in the total data amount reduces the traffic on the memory bus, which is the bottleneck of today's high-performance algorithms, by 50%. In CT simulations and CT measurements, float reconstructions (gold standard) and half reconstructions are visually compared via difference images and by quantitative image quality evaluation. This is done for analytical reconstruction (filtered backprojection) and iterative reconstruction (ordered subset SART). The magnitude of quantization noise, which is caused by a reduction in the data precision of both rawdata and image data during image reconstruction, is negligible. This is clearly shown for filtered backprojection and iterative ordered subset SART reconstruction. In filtered backprojection, the implementation of the backprojection should be optimized for low data precision if the image data are represented in half format. In ordered subset SART image reconstruction, no adaptations are necessary and the convergence speed remains unchanged. Half precision floating-point values allow to speed up CT image reconstruction without compromising image quality.

Gate-controlled quantum collimation in nanocolumn resonant tunneling transistors.

PubMed

Wensorra, J; Lepsa, M I; Trellenkamp, S; Moers, J; Indlekofer, K M; Lüth, H

2009-11-18

Nanoscaled resonant tunneling transistors (RTT) based on MBE-grown GaAs/AlAs double-barrier quantum well (DBQW) structures have been fabricated by a top-down approach using electron-beam lithographic definition of the vertical nanocolumns. In the preparation process, a reproducible mask alignment accuracy of below 10 nm has been achieved and the all-around metal gate at the level of the DBQW structure has been positioned at a distance of about 20 nm relative to the semiconductor nanocolumn. Due to the specific doping profile n++/i/n++ along the transistor nanocolumn, a particular confining potential is established for devices with diameters smaller than 70 nm, which causes a collimation effect of the propagating electrons. Under these conditions, room temperature optimum performance of the nano-RTTs is achieved with peak-to-valley current ratios above 2 and a peak current swing factor of about 6 for gate voltages between -6 and +6 V. These values indicate that our nano-RTTs can be successfully used in low power fast nanoelectronic circuits.

Synthesizing Biomolecule-based Boolean Logic Gates

PubMed Central

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2012-01-01

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

Synthesizing biomolecule-based Boolean logic gates.

PubMed

Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

2013-02-15

One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

Attention Gating in Short-Term Visual Memory.

ERIC Educational Resources Information Center

Reeves, Adam; Sperling, George

1986-01-01

An experiment is conducted showing that an attention shift to a stream of numerals presented in rapid serial visual presentation mode produces not a total loss, but a systematic distortion of order. An attention gating model (AGM) is developed from a more general attention model. (Author/LMO)

Reciprocal Interaction of Dendrite Geometry and Nuclear Calcium-VEGFD Signaling Gates Memory Consolidation and Extinction.

PubMed

Hemstedt, Thekla J; Bengtson, C Peter; Ramírez, Omar; Oliveira, Ana M M; Bading, Hilmar

2017-07-19

Nuclear calcium is an important signaling end point in synaptic excitation-transcription coupling that is critical for long-term neuroadaptations. Here, we show that nuclear calcium acting via a target gene, VEGFD, is required for hippocampus-dependent fear memory consolidation and extinction in mice. Nuclear calcium-VEGFD signaling upholds the structural integrity and complexity of the dendritic arbor of CA1 neurons that renders those cells permissive for the efficient generation of synaptic input-evoked nuclear calcium transients driving the expression of plasticity-related genes. Therefore, the gating of memory functions rests on the reciprocally reinforcing maintenance of an intact dendrite geometry and a functional synapse-to-nucleus communication axis. In psychiatric and neurodegenerative disorders, therapeutic application of VEGFD may help to stabilize dendritic structures and network connectivity, which may prevent cognitive decline and could boost the efficacy of extinction-based exposure therapies. SIGNIFICANCE STATEMENT This study uncovers a reciprocal relationship between dendrite geometry, the ability to generate nuclear calcium transients in response to synaptic inputs, and the subsequent induction of expression of plasticity-related and dendritic structure-preserving genes. Insufficient nuclear calcium signaling in CA1 hippocampal neurons and, consequently, reduced expression of the nuclear calcium target gene VEGFD, a dendrite maintenance factor, leads to reduced-complexity basal dendrites of CA1 neurons, which severely compromises the animals' consolidation of both memory and extinction memory. The structure-protective function of VEGFD may prove beneficial in psychiatric disorders as well as neurodegenerative and aging-related conditions that are associated with loss of neuronal structures, dysfunctional excitation-transcription coupling, and cognitive decline. Copyright © 2017 the authors 0270-6474/17/376946-10$15.00/0.

Nonvolatile gate effect in a ferroelectric-semiconductor quantum well.

PubMed

Stolichnov, Igor; Colla, Enrico; Setter, Nava; Wojciechowski, Tomasz; Janik, Elzbieta; Karczewski, Grzegorz

2006-12-15

Field effect transistors with ferroelectric gates would make ideal rewritable nonvolatile memories were it not for the severe problems in integrating the ferroelectric oxide directly on the semiconductor channel. We propose a powerful way to avoid these problems using a gate material that is ferroelectric and semiconducting simultaneously. First, ferroelectricity in semiconductor (Cd,Zn)Te films is proven and studied using modified piezoforce scanning probe microscopy. Then, a rewritable field effect device is demonstrated by local poling of the (Cd,Zn)Te layer of a (Cd,Zn)Te/CdTe quantum well, provoking a reversible, nonvolatile change in the resistance of the 2D electron gas. The results point to a potential new family of nanoscale one-transistor memories.

Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drain-underlap structure

NASA Astrophysics Data System (ADS)

Yoon, Young Jun; Seo, Jae Hwa; Kang, In Man

2018-04-01

In this work, we present a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on an asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor (TFET) for DRAM applications. The n-doped boosting layer and gate2 drain-underlap structure is employed in the device to obtain an excellent 1T-DRAM performance. The n-doped layer inserted between the source and channel regions improves the sensing margin because of a high rate of increase in the band-to-band tunneling (BTBT) probability. Furthermore, because the gate2 drain-underlap structure reduces the recombination rate that occurs between the gate2 and drain regions, a device with a gate2 drain-underlap length (L G2_D-underlap) of 10 nm exhibited a longer retention performance. As a result, by applying the n-doped layer and gate2 drain-underlap structure, the proposed device exhibited not only a high sensing margin of 1.11 µA/µm but also a long retention time of greater than 100 ms at a temperature of 358 K (85 °C).

Skyrmion-based multi-channel racetrack

NASA Astrophysics Data System (ADS)

Song, Chengkun; Jin, Chendong; Wang, Jinshuai; Xia, Haiyan; Wang, Jianbo; Liu, Qingfang

2017-11-01

Magnetic skyrmions are promising for the application of racetrack memories, logic gates, and other nano-devices, owing to their topologically protected stability, small size, and low driving current. In this work, we propose a skyrmion-based multi-channel racetrack memory where the skyrmion moves in the selected channel by applying voltage-controlled magnetic anisotropy gates. It is demonstrated numerically that a current-dependent skyrmion Hall effect can be restrained by the additional potential of the voltage-controlled region, and the skyrmion velocity and moving channel in the racetrack can be operated by tuning the voltage-controlled magnetic anisotropy, gate position, and current density. Our results offer a potential application of racetrack memory based on skyrmions.

Utilizing Controlled Vibrations in a Microgravity Environment to Understand and Promote Microstructural Homogeneity During Float-Zone Crystal Growth

NASA Technical Reports Server (NTRS)

Anilkumar, A. V.; Bhowmick, J.; Grugel, R. N.a

2000-01-01

Our previous experiments with NaNO3 float-zones revealed that steady thermocapillary flow can be balanced/offset by the controlled surface streaming flow induced by end-wall vibration. In the current experiments we are examining the effects of streaming flow on steadying/stabilizing nonsteady thermocapillary flow in such zones. To this effect we have set up a controlled NaNO3 half-zone experiment, where the processing parameters, like zone dimensions and temperature gradients, can be easily varied to generate nonsteady thermocapillary flows. In the present paper we present preliminary results of our investigations into stabilizing such flows by employing end-wall vibration.

Superior model for fault tolerance computation in designing nano-sized circuit systems

DOE Office of Scientific and Technical Information (OSTI.GOV)

Singh, N. S. S., E-mail: narinderjit@petronas.com.my; Muthuvalu, M. S., E-mail: msmuthuvalu@gmail.com; Asirvadam, V. S., E-mail: vijanth-sagayan@petronas.com.my

2014-10-24

As CMOS technology scales nano-metrically, reliability turns out to be a decisive subject in the design methodology of nano-sized circuit systems. As a result, several computational approaches have been developed to compute and evaluate reliability of desired nano-electronic circuits. The process of computing reliability becomes very troublesome and time consuming as the computational complexity build ups with the desired circuit size. Therefore, being able to measure reliability instantly and superiorly is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into the development of an automated reliability evaluation tool based on the generalizationmore » of Probabilistic Gate Model (PGM) and Boolean Difference-based Error Calculator (BDEC) models. The Matlab-based tool allows users to significantly speed-up the task of reliability analysis for very large number of nano-electronic circuits. Secondly, by using the developed automated tool, the paper explores into a comparative study involving reliability computation and evaluation by PGM and, BDEC models for different implementations of same functionality circuits. Based on the reliability analysis, BDEC gives exact and transparent reliability measures, but as the complexity of the same functionality circuits with respect to gate error increases, reliability measure by BDEC tends to be lower than the reliability measure by PGM. The lesser reliability measure by BDEC is well explained in this paper using distribution of different signal input patterns overtime for same functionality circuits. Simulation results conclude that the reliability measure by BDEC depends not only on faulty gates but it also depends on circuit topology, probability of input signals being one or zero and also probability of error on signal lines.« less

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

DOE Office of Scientific and Technical Information (OSTI.GOV)

Gala, F.; Zollo, G.

2014-06-19

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Atomistic characterization of SAM coatings as gate insulators in Si-based FET devices

NASA Astrophysics Data System (ADS)

Gala, F.; Zollo, G.

2014-06-01

Many nano-material systems are currently under consideration as possible candidates for gate dielectric insulators in both metal-oxide-semiconductor (MOSFET) and organic (OFET) field-effect transistors. In this contribution, the possibility of employing self-assembled monolayers (SAMs) of hydroxylated octadecyltrichlorosilane (OTS) chains on a (111) Si substrate as gate dielectrics is discussed; in particular ab initio theoretical simulations have been employed to study the structural properties, work function modifications, and the insulating properties of OTS thin film coatings on Si substrates.

Nanogranular SiO2 proton gated silicon layer transistor mimicking biological synapses

NASA Astrophysics Data System (ADS)

Liu, M. J.; Huang, G. S.; Feng, P.; Guo, Q. L.; Shao, F.; Tian, Z. A.; Li, G. J.; Wan, Q.; Mei, Y. F.

2016-06-01

Silicon on insulator (SOI)-based transistors gated by nanogranular SiO2 proton conducting electrolytes were fabricated to mimic synapse behaviors. This SOI-based device has both top proton gate and bottom buried oxide gate. Electrical transfer properties of top proton gate show hysteresis curves different from those of bottom gate, and therefore, excitatory post-synaptic current and paired pulse facilitation (PPF) behavior of biological synapses are mimicked. Moreover, we noticed that PPF index can be effectively tuned by the spike interval applied on the top proton gate. Synaptic behaviors and functions, like short-term memory, and its properties are also experimentally demonstrated in our device. Such SOI-based electronic synapses are promising for building neuromorphic systems.

Analog and RF performance of a multigate FinFET at nano scale

NASA Astrophysics Data System (ADS)

Kumar, Abhishek

2016-12-01

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.

Gating based on internal/external signals with dynamic correlation updates.

PubMed

Wu, Huanmei; Zhao, Qingya; Berbeco, Ross I; Nishioka, Seiko; Shirato, Hiroki; Jiang, Steve B

2008-12-21

Precise localization of mobile tumor positions in real time is critical to the success of gated radiotherapy. Tumor positions are usually derived from either internal or external surrogates. Fluoroscopic gating based on internal surrogates, such as implanted fiducial markers, is accurate however requiring a large amount of imaging dose. Gating based on external surrogates, such as patient abdominal surface motion, is non-invasive however less accurate due to the uncertainty in the correlation between tumor location and external surrogates. To address these complications, we propose to investigate an approach based on hybrid gating with dynamic internal/external correlation updates. In this approach, the external signal is acquired at high frequency (such as 30 Hz) while the internal signal is sparsely acquired (such as 0.5 Hz or less). The internal signal is used to validate and update the internal/external correlation during treatment. Tumor positions are derived from the external signal based on the newly updated correlation. Two dynamic correlation updating algorithms are introduced. One is based on the motion amplitude and the other is based on the motion phase. Nine patients with synchronized internal/external motion signals are simulated retrospectively to evaluate the effectiveness of hybrid gating. The influences of different clinical conditions on hybrid gating, such as the size of gating windows, the optimal timing for internal signal acquisition and the acquisition frequency are investigated. The results demonstrate that dynamically updating the internal/external correlation in or around the gating window will reduce false positive with relatively diminished treatment efficiency. This improvement will benefit patients with mobile tumors, especially greater for early stage lung cancers, for which the tumors are less attached or freely floating in the lung.

Fabrication of a Silicon Nanowire on a Bulk Substrate by Use of a Plasma Etching and Total Ionizing Dose Effects on a Gate-All-Around Field-Effect Transistor

NASA Technical Reports Server (NTRS)

Moon, Dong-Il; Han, Jin-Woo; Meyyappan, Meyya

2016-01-01

The gate all around transistor is investigated through experiment. The suspended silicon nanowire for the next generation is fabricated on bulk substrate by plasma etching method. The scallop pattern generated by Bosch process is utilized to form a floating silicon nanowire. By combining anisotropic and istropic silicon etch process, the shape of nanowire is accurately controlled. From the suspended nanowire, the gate all around transistor is demonstrated. As the silicon nanowire is fully surrounded by the gate, the device shows excellent electrostatic characteristics.

Multifunctional carbon nano-paper composite

NASA Astrophysics Data System (ADS)

Zhang, Zhichun; Chu, Hetao; Wang, Kuiwen; Liu, Yanjv; Leng, Jinsong

2013-08-01

Carbon Nanotube (CNT), for its excellent mechanical, electrical properties and nano size, large special surface physical property, become the most promising material. But carbon nanotube can still fabricated in micro dimension, and can't be made into macro size, so to the carbon nanotube filled composite can't explore the properties of the CNT. Carbon nano-paper is made of pure CNT, with micro pore, and it turn micro sized CNT into macro shaped membrane. Based on the piezo-resistivity and electrical conductivity of the carbon nano-paper, we used the carbon nano-paper as functional layers fabricate functional composite, and studies its strain sensing, composite material deicing and shape memory polymer (SMP) material electric actuation performance. The results shown that the resin can pregnant the nano paper, and there was good bond for nano paper and composite. The functional composite can monitoring the strain with high sensitivity comparing to foil strain gauge. The functional composite can be heated via the carbon nano paper with low power supply and high heating rate. The composite has good deicing and heat actuation performance to composite material. For the good strain sensing, electric conductivity and self-heating character of the carbon nano-paper composite, it can be used for self sensing, anti lightning strike and deicing of composite materials in aircrafts and wind turbine blades.

Fixed-Rate Compressed Floating-Point Arrays.

PubMed

Lindstrom, Peter

2014-12-01

Current compression schemes for floating-point data commonly take fixed-precision values and compress them to a variable-length bit stream, complicating memory management and random access. We present a fixed-rate, near-lossless compression scheme that maps small blocks of 4(d) values in d dimensions to a fixed, user-specified number of bits per block, thereby allowing read and write random access to compressed floating-point data at block granularity. Our approach is inspired by fixed-rate texture compression methods widely adopted in graphics hardware, but has been tailored to the high dynamic range and precision demands of scientific applications. Our compressor is based on a new, lifted, orthogonal block transform and embedded coding, allowing each per-block bit stream to be truncated at any point if desired, thus facilitating bit rate selection using a single compression scheme. To avoid compression or decompression upon every data access, we employ a software write-back cache of uncompressed blocks. Our compressor has been designed with computational simplicity and speed in mind to allow for the possibility of a hardware implementation, and uses only a small number of fixed-point arithmetic operations per compressed value. We demonstrate the viability and benefits of lossy compression in several applications, including visualization, quantitative data analysis, and numerical simulation.

Preparation and application of functionalized nano drug carriers.

PubMed

Gong, Rudong; Chen, Gaimin

2016-05-01

Targeting at category memory characteristics and preparation methods of functionalized nano drugs, preparation technology of functionalized nano drug carriers is studied, and then important role of functionalized nano drug carrier in preparation of medicine is studied. Carry out the relevant literature search with computer, change limited language in the paper to Chinese and necessarily remove repetitive studies. After first review of 1260 retrieved literature, it can be found that nano drug is with accurate quantity, relatively good targeting, specificity and absorbency. Necessary research of nano drug carriers can prevent and treat disease to a certain extent. Preparation of functionalized nanocarrier is simple and convenient, which can improve frequency of use of nano preparation technology and provide better development space for medical use. Therefore, nanocarriers should be combined with drugs with relatively strong specificity in clinics, in order to be able to conduct effective research on nanometer intelligent drug, effectively promote long-term development of nano biotechnology, and then provide favorable, reliable basis for clinical diagnosis and treatment.

The mathematics of a quantum Hamiltonian computing half adder Boolean logic gate.

PubMed

Dridi, G; Julien, R; Hliwa, M; Joachim, C

2015-08-28

The mathematics behind the quantum Hamiltonian computing (QHC) approach of designing Boolean logic gates with a quantum system are given. Using the quantum eigenvalue repulsion effect, the QHC AND, NAND, OR, NOR, XOR, and NXOR Hamiltonian Boolean matrices are constructed. This is applied to the construction of a QHC half adder Hamiltonian matrix requiring only six quantum states to fullfil a half Boolean logical truth table. The QHC design rules open a nano-architectronic way of constructing Boolean logic gates inside a single molecule or atom by atom at the surface of a passivated semi-conductor.

Autonomous Microstructure EM-APEX Floats

DTIC Science & Technology

2016-01-01

Autonomous Microstructure_EM-APEX_Float 4/8/16 at 3:21 PM 1 Title: Autonomous Microstructure EM-APEX Floats Authors: Ren-Chieh Lien1,2...Street Seattle, WA 98105 rcl@uw.edu Abstract: Fast responding FP-07 thermistors have been incorporated on profiling EM-APEX floats to measure...storage board. The raw and processed temperature observations are stored on a microSD card. Results from eight microstructure EM-APEX floats

Majority logic gate for 3D magnetic computing.

PubMed

Eichwald, Irina; Breitkreutz, Stephan; Ziemys, Grazvydas; Csaba, György; Porod, Wolfgang; Becherer, Markus

2014-08-22

For decades now, microelectronic circuits have been exclusively built from transistors. An alternative way is to use nano-scaled magnets for the realization of digital circuits. This technology, known as nanomagnetic logic (NML), may offer significant improvements in terms of power consumption and integration densities. Further advantages of NML are: non-volatility, radiation hardness, and operation at room temperature. Recent research focuses on the three-dimensional (3D) integration of nanomagnets. Here we show, for the first time, a 3D programmable magnetic logic gate. Its computing operation is based on physically field-interacting nanometer-scaled magnets arranged in a 3D manner. The magnets possess a bistable magnetization state representing the Boolean logic states '0' and '1.' Magneto-optical and magnetic force microscopy measurements prove the correct operation of the gate over many computing cycles. Furthermore, micromagnetic simulations confirm the correct functionality of the gate even for a size in the nanometer-domain. The presented device demonstrates the potential of NML for three-dimensional digital computing, enabling the highest integration densities.

Modular Adder Designs Using Optimal Reversible and Fault Tolerant Gates in Field-Coupled QCA Nanocomputing

NASA Astrophysics Data System (ADS)

Bilal, Bisma; Ahmed, Suhaib; Kakkar, Vipan

2018-02-01

The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.

Dynamic memory of a single voltage-gated potassium ion channel: A stochastic nonequilibrium thermodynamic analysis

DOE Office of Scientific and Technical Information (OSTI.GOV)

Banerjee, Kinshuk, E-mail: kbpchem@gmail.com

2015-05-14

In this work, we have studied the stochastic response of a single voltage-gated potassium ion channel to a periodic external voltage that keeps the system out-of-equilibrium. The system exhibits memory, resulting from time-dependent driving, that is reflected in terms of dynamic hysteresis in the current-voltage characteristics. The hysteresis loop area has a maximum at some intermediate voltage frequency and disappears in the limits of low and high frequencies. However, the (average) dissipation at long-time limit increases and finally goes to saturation with rising frequency. This raises the question: how diminishing hysteresis can be associated with growing dissipation? To answer this,more » we have studied the nonequilibrium thermodynamics of the system and analyzed different thermodynamic functions which also exhibit hysteresis. Interestingly, by applying a temporal symmetry analysis in the high-frequency limit, we have analytically shown that hysteresis in some of the periodic responses of the system does not vanish. On the contrary, the rates of free energy and internal energy change of the system as well as the rate of dissipative work done on the system show growing hysteresis with frequency. Hence, although the current-voltage hysteresis disappears in the high-frequency limit, the memory of the ion channel is manifested through its specific nonequilibrium thermodynamic responses.« less

Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices

NASA Astrophysics Data System (ADS)

Breuer, Thomas; Nielen, Lutz; Roesgen, Bernd; Waser, Rainer; Rana, Vikas; Linn, Eike

2016-04-01

Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 106 cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Enhanced biosensing resolution with foundry fabricated individually addressable dual-gated ISFETs.

PubMed

Duarte-Guevara, Carlos; Lai, Fei-Lung; Cheng, Chun-Wen; Reddy, Bobby; Salm, Eric; Swaminathan, Vikhram; Tsui, Ying-Kit; Tuan, Hsiao Chin; Kalnitsky, Alex; Liu, Yi-Shao; Bashir, Rashid

2014-08-19

The adaptation of semiconductor technologies for biological applications may lead to a new era of inexpensive, sensitive, and portable diagnostics. At the core of these developing technologies is the ion-sensitive field-effect transistor (ISFET), a biochemical to electrical transducer with seamless integration to electronic systems. We present a novel structure for a true dual-gated ISFET that is fabricated with a silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process by Taiwan Semiconductor Manufacturing Company (TSMC). In contrast to conventional SOI ISFETs, each transistor has an individually addressable back-gate and a gate oxide that is directly exposed to the solution. The elimination of the commonly used floating gate architecture reduces the chance of electrostatic discharge and increases the potential achievable transistor density. We show that when operated in a "dual-gate" mode, the transistor response can exhibit sensitivities to pH changes beyond the Nernst limit. This enhancement in sensitivity was shown to increase the sensor's signal-to-noise ratio, allowing the device to resolve smaller pH changes. An improved resolution can be used to enhance small signals and increase the sensor accuracy when monitoring small pH dynamics in biological reactions. As a proof of concept, we demonstrate that the amplified sensitivity and improved resolution result in a shorter detection time and a larger output signal of a loop-mediated isothermal DNA amplification reaction (LAMP) targeting a pathogenic bacteria gene, showing benefits of the new structure for biosensing applications.

Tethered float liquid level sensor

DOEpatents

Daily, III, William Dean

2016-09-06

An apparatus for sensing the level of a liquid includes a float, a tether attached to the float, a pulley attached to the tether, a rotation sensor connected to the pulley that senses vertical movement of said float and senses the level of the liquid.

Molecular controlled of quantum nano systems

NASA Astrophysics Data System (ADS)

Paltiel, Yossi

2014-03-01

A century ago quantum mechanics created a conceptual revolution whose fruits are now seen in almost any aspect of our day-to-day life. Lasers, transistors and other solid state and optical devices represent the core technology of current computers, memory devices and communication systems. However, all these examples do not exploit fully the quantum revolution as they do not take advantage of the coherent wave-like properties of the quantum wave function. Controlled coherent system and devices at ambient temperatures are challenging to realize. We are developing a novel nano tool box with control coupling between the quantum states and the environment. This tool box that combines nano particles with organic molecules enables the integration of quantum properties with classical existing devices at ambient temperatures. The nano particles generate the quantum states while the organic molecules control the coupling and therefore the energy, charge, spin, or quasi particle transfer between the layers. Coherent effects at ambient temperatures can be measured in the strong coupling regime. In the talk I will present our nano tool box and show studies of charge transfer, spin transfer and energy transfer in the hybrid layers as well as collective transfer phenomena. These enable the realization of room temperature operating quantum electro optical devices. For example I will present in details, our recent development of a new type of chiral molecules based magnetless universal memory exploiting selective spin transfer.

Deterministic quantum controlled-PHASE gates based on non-Markovian environments

NASA Astrophysics Data System (ADS)

Zhang, Rui; Chen, Tian; Wang, Xiang-Bin

2017-12-01

We study the realization of the quantum controlled-PHASE gate in an atom-cavity system beyond the Markovian approximation. The general description of the dynamics for the atom-cavity system without any approximation is presented. When the spectral density of the reservoir has the Lorentz form, by making use of the memory backflow from the reservoir, we can always construct the deterministic quantum controlled-PHASE gate between a photon and an atom, no matter the atom-cavity coupling strength is weak or strong. While, the phase shift in the output pulse hinders the implementation of quantum controlled-PHASE gates in the sub-Ohmic, Ohmic or super-Ohmic reservoirs.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

NASA Astrophysics Data System (ADS)

Yu, Jie; Chen, Kun-ji; Ma, Zhong-yuan; Zhang, Xin-xin; Jiang, Xiao-fan; Wu, Yang-qing; Huang, Xin-fan; Oda, Shunri

2016-09-01

Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8 × 1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration. Project supported by the State Key Development Program for Basic Research of China (Grant No. 2010CB934402) and the National Natural Science Foundation of China (Grant Nos. 11374153, 61571221, and 61071008).

Modulation of nano-selenium on tetrodotoxin-sensitive voltage-gated sodium currents in rat dorsal root ganglion neurons.

PubMed

Yuan, Huijun; Lan, Tonghan; Lin, Jiarui

2005-01-01

Nano-Selenium, a novel Nano technology production, was demonstrated to be useful in medical and scientific researches. Here, we investigated the effects of Nano-Selenium on tetrodotoxin-sensitive (TTX-S) voltage-dependent Na⁺channels in isolated rat dorsal root ganglion neurons, using whole-cell patch-clamp method. Nano-Selenium irreversibly decreased TTX-S Na⁺current (INa) in a concentration-dependent manner and shifted the maximum of the current/voltage relationship from -67mV to -52mV, without modifying the threshold potential of the current. Nano-Selenium shifted the steady-state activation and inactivation curves to the left. In the contrast of Na2SeO3, the inhibition effect of 1nM Nano-Se was much stronger. The cell treated with 1nM Na2SeO3firstly, still respond to futher addition of 1nM Nano-Selenium. These results prove Nano-Selenium to be a novel antiagonist, acted within the channel pore, not on or near the exterior surface of the channel protein where it would experience the membrane electric field, which possesses a distinct binding site from Na2SeO3.

Quantum random access memory.

PubMed

Giovannetti, Vittorio; Lloyd, Seth; Maccone, Lorenzo

2008-04-25

A random access memory (RAM) uses n bits to randomly address N=2(n) distinct memory cells. A quantum random access memory (QRAM) uses n qubits to address any quantum superposition of N memory cells. We present an architecture that exponentially reduces the requirements for a memory call: O(logN) switches need be thrown instead of the N used in conventional (classical or quantum) RAM designs. This yields a more robust QRAM algorithm, as it in general requires entanglement among exponentially less gates, and leads to an exponential decrease in the power needed for addressing. A quantum optical implementation is presented.

Role of Non-Volatile Memories in Automotive and IoT Markets

DTIC Science & Technology

2017-03-01

Role of Non-Volatile Memories in Automotive and IoT Markets Vipin Tiwari Director, Business Development and Product Marketing SST – A Wholly Own...automotive and Internet of Things (IoT) markets . Keywords: Embedded flash; Microcontrollers, Automotive; Internet of Things, IoT; Non-volatile memories...variou s types of non-volatile memories available in the market , bu t the floating-poly based embedded flash memories have been around the longest and

The Association of Schizophrenia Risk -Amino Acid Oxidase Polymorphisms With Sensorimotor Gating, Working Memory and Personality in Healthy Males

PubMed Central

Roussos, Panos; Giakoumaki, Stella G; Adamaki, Eva; Anastasios, Georgakopoulos; Nikos, Robakis K; Bitsios, Panos

2011-01-01

There is evidence supporting a role for the -amino acid oxidase (DAO) locus in schizophrenia. This study aimed to determine the relationship of five single-nucleotide polymorphisms (SNPs) within the DAO gene identified as promising schizophrenia risk genes (rs4623951, rs2111902, rs3918346, rs3741775, and rs3825251) to acoustic startle, prepulse inhibition (PPI), working memory, and personality dimensions. A highly homogeneous study entry cohort (n=530) of healthy, young male army conscripts (n=703) originating from the Greek LOGOS project (Learning On Genetics Of Schizophrenia Spectrum) underwent PPI of the acoustic startle reflex, working memory, and personality assessment. The QTPHASE from the UNPHASED package was used for the association analysis of each SNP or haplotype data, with p-values corrected for multiple testing by running 10 000 permutations of the data. The rs4623951_T-rs3741775_G and rs4623951_T-rs2111902_T diplotypes were associated with reduced PPI and worse performance in working memory tasks and a personality pattern characterized by attenuated anxiety. Median stratification analysis of the risk diplotype group (ie, those individuals homozygous for the T and G alleles (TG+)) showed reduced PPI and working memory performance only in TG+ individuals with high trait anxiety. The rs4623951_T allele, which is the DAO polymorphism most strongly associated with schizophrenia, might tag a haplotype that affects PPI, cognition, and personality traits in general population. Our findings suggest an influence of the gene in the neural substrate mediating sensorimotor gating and working memory, especially when combined with high anxiety and further validate DAO as a candidate gene for schizophrenia and spectrum disorders. PMID:21471957

Local Gate Control of a Carbon Nanotube Double Quantum Dot

DTIC Science & Technology

2016-04-04

Nanotube Double Quantum Dot N. Mason,*† M. J. Biercuk,* C. M. Marcus† We have measured carbon nanotube quantum dots with multiple electro- static gates and...computation. Carbon nanotubes have been considered lead- ing candidates for nanoscale electronic applica- tions (1, 2). Previous measurements of nano- tube...electronics have shown electron confine- ment (quantum dot) effects such as single- electron charging and energy-level quantization (3–5). Nanotube

14 CFR 27.753 - Main float design.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Main float design. 27.753 Section 27.753... STANDARDS: NORMAL CATEGORY ROTORCRAFT Design and Construction Floats and Hulls § 27.753 Main float design. (a) Bag floats. Each bag float must be designed to withstand— (1) The maximum pressure differential...

14 CFR 29.753 - Main float design.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Main float design. 29.753 Section 29.753... STANDARDS: TRANSPORT CATEGORY ROTORCRAFT Design and Construction Floats and Hulls § 29.753 Main float design. (a) Bag floats. Each bag float must be designed to withstand— (1) The maximum pressure differential...

Solid state engine using nitinol memory alloy

DOEpatents

Golestaneh, Ahmad A.

1981-01-01

A device for converting heat energy to mechanical energy includes a reservoir of a hot fluid and a rotor assembly mounted thereabove so a portion of it dips into the hot fluid. The rotor assembly may include a shaft having four spokes extending radially outwardly therefrom at right angles to each other, a floating ring and four flexible elements composed of a thermal memory material having a critical temperature between the temperature of the hot fluid and that of the ambient atmosphere extending between the ends of the spokes and the floating ring. Preferably, the flexible elements are attached to the floating ring through curved leaf springs. Energetic shape recovery of the flexible elements in the hot fluid causes the rotor assembly to rotate.

Solid state engine using nitinol memory alloy

DOEpatents

Golestaneh, A.A.

1980-01-21

A device for converting heat energy to mechanical energy includes a reservoir of a hot fluid and a rotor assembly mounted thereabove so a portion of it dips into the hot fluid. The rotor assembly may include a shaft having four spokes extending radially outwardly therefrom at right angles to each other, a floating ring and four flexible elements composed of a thermal memory material having a critical temperature between the temperature of the hot fluid and that of the ambient atmosphere extending between the ends of the spokes and the floating ring. Preferably, the flexible elements are attached to the floating ring through curved leaf springs. Energetic shape recovery of the flexible elements in the hot fluid causes the rotor assembly to rotate.

Float Zone Workshop

NASA Technical Reports Server (NTRS)

Naumann, R. J.

1980-01-01

A summary of the Analytical Float Zone Experiment System (AFZES) concept is presented. The types of experiments considered for such a facility are discussed. Reports from various industrial producers and users of float zone material are presented. Special emphasis is placed on state-of-the-art developments in low gravity manufacturing and their applications to space processing.

Highly Efficient Spin-Current Operation in a Cu Nano-Ring

NASA Astrophysics Data System (ADS)

Murphy, Benedict A.; Vick, Andrew J.; Samiepour, Marjan; Hirohata, Atsufumi

2016-11-01

An all-metal lateral spin-valve structure has been fabricated with a medial Copper nano-ring to split the diffusive spin-current path. We have demonstrated significant modulation of the non-local signal by the application of a magnetic field gradient across the nano-ring, which is up to 30% more efficient than the conventional Hanle configuration at room temperature. This was achieved by passing a dc current through a current-carrying bar to provide a locally induced Ampère field. We have shown that in this manner a lateral spin-valve gains an additional functionality in the form of three-terminal gate operation for future spintronic logic.

Modeling and simulation of electronic structure, material interface and random doping in nano electronic devices

PubMed Central

Chen, Duan; Wei, Guo-Wei

2010-01-01

The miniaturization of nano-scale electronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), has given rise to a pressing demand in the new theoretical understanding and practical tactic for dealing with quantum mechanical effects in integrated circuits. Modeling and simulation of this class of problems have emerged as an important topic in applied and computational mathematics. This work presents mathematical models and computational algorithms for the simulation of nano-scale MOSFETs. We introduce a unified two-scale energy functional to describe the electrons and the continuum electrostatic potential of the nano-electronic device. This framework enables us to put microscopic and macroscopic descriptions in an equal footing at nano scale. By optimization of the energy functional, we derive consistently-coupled Poisson-Kohn-Sham equations. Additionally, layered structures are crucial to the electrostatic and transport properties of nano transistors. A material interface model is proposed for more accurate description of the electrostatics governed by the Poisson equation. Finally, a new individual dopant model that utilizes the Dirac delta function is proposed to understand the random doping effect in nano electronic devices. Two mathematical algorithms, the matched interface and boundary (MIB) method and the Dirichlet-to-Neumann mapping (DNM) technique, are introduced to improve the computational efficiency of nano-device simulations. Electronic structures are computed via subband decomposition and the transport properties, such as the I-V curves and electron density, are evaluated via the non-equilibrium Green's functions (NEGF) formalism. Two distinct device configurations, a double-gate MOSFET and a four-gate MOSFET, are considered in our three-dimensional numerical simulations. For these devices, the current fluctuation and voltage threshold lowering effect induced by the discrete dopant model are explored. Numerical convergence

Controllable Hysteresis and Threshold Voltage of Single-Walled Carbon Nano-tube Transistors with Ferroelectric Polymer Top-Gate Insulators

PubMed Central

Sun, Yi-Lin; Xie, Dan; Xu, Jian-Long; Zhang, Cheng; Dai, Rui-Xuan; Li, Xian; Meng, Xiang-Jian; Zhu, Hong-Wei

2016-01-01

Double-gated field effect transistors have been fabricated using the SWCNT networks as channel layer and the organic ferroelectric P(VDF-TrFE) film spin-coated as top gate insulators. Standard photolithography process has been adopted to achieve the patterning of organic P(VDF-TrFE) films and top-gate electrodes, which is compatible with conventional CMOS process technology. An effective way for modulating the threshold voltage in the channel of P(VDF-TrFE) top-gate transistors under polarization has been reported. The introduction of functional P(VDF-TrFE) gate dielectric also provides us an alternative method to suppress the initial hysteresis of SWCNT networks and obtain a controllable ferroelectric hysteresis behavior. Applied bottom gate voltage has been found to be another effective way to highly control the threshold voltage of the networked SWCNTs based FETs by electrostatic doping effect. PMID:26980284

Logic gates realized by nonvolatile GeTe/Sb2Te3 super lattice phase-change memory with a magnetic field input

NASA Astrophysics Data System (ADS)

Lu, Bin; Cheng, Xiaomin; Feng, Jinlong; Guan, Xiawei; Miao, Xiangshui

2016-07-01

Nonvolatile memory devices or circuits that can implement both storage and calculation are a crucial requirement for the efficiency improvement of modern computer. In this work, we realize logic functions by using [GeTe/Sb2Te3]n super lattice phase change memory (PCM) cell in which higher threshold voltage is needed for phase change with a magnetic field applied. First, the [GeTe/Sb2Te3]n super lattice cells were fabricated and the R-V curve was measured. Then we designed the logic circuits with the super lattice PCM cell verified by HSPICE simulation and experiments. Seven basic logic functions are first demonstrated in this letter; then several multi-input logic gates are presented. The proposed logic devices offer the advantages of simple structures and low power consumption, indicating that the super lattice PCM has the potential in the future nonvolatile central processing unit design, facilitating the development of massive parallel computing architecture.

Scaling properties of ballistic nano-transistors

PubMed Central

2011-01-01

Recently, we have suggested a scale-invariant model for a nano-transistor. In agreement with experiments a close-to-linear thresh-old trace was found in the calculated ID - VD-traces separating the regimes of classically allowed transport and tunneling transport. In this conference contribution, the relevant physical quantities in our model and its range of applicability are discussed in more detail. Extending the temperature range of our studies it is shown that a close-to-linear thresh-old trace results at room temperatures as well. In qualitative agreement with the experiments the ID - VG-traces for small drain voltages show thermally activated transport below the threshold gate voltage. In contrast, at large drain voltages the gate-voltage dependence is weaker. As can be expected in our relatively simple model, the theoretical drain current is larger than the experimental one by a little less than a decade. PMID:21711899

Multi-element logic gates for trapped-ion qubits

NASA Astrophysics Data System (ADS)

Tan, T. R.; Gaebler, J. P.; Lin, Y.; Wan, Y.; Bowler, R.; Leibfried, D.; Wineland, D. J.

2015-12-01

Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. In the field of quantum information processing (QIP) and quantum networking, various proposals discuss the possibility of hybrid architectures where specific tasks are delegated to the most suitable subsystem. For example, in quantum networks, it may be advantageous to transfer information from a subsystem that has good memory properties to another subsystem that is more efficient at transporting information between nodes in the network. For trapped ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. Ions of different elements have previously been used in QIP experiments for sympathetic cooling, creation of entanglement through dissipation, and quantum non-demolition measurement of one species with another. Here we demonstrate an entangling quantum gate between ions of different elements which can serve as an important building block of QIP, quantum networking, precision spectroscopy, metrology, and quantum simulation. A geometric phase gate between a 9Be+ ion and a 25Mg+ ion is realized through an effective spin-spin interaction generated by state-dependent forces induced with laser beams. Combined with single-qubit gates and same-species entangling gates, this mixed-element entangling gate provides a complete set of gates over such a hybrid system for universal QIP. Using a sequence of such gates, we demonstrate a CNOT (controlled-NOT) gate and a SWAP gate. We further demonstrate the robustness of these gates against thermal excitation and show improved detection in quantum logic spectroscopy. We also observe a strong violation of a CHSH (Clauser-Horne-Shimony-Holt)-type Bell inequality on entangled states composed of different ion species.

Multi-element logic gates for trapped-ion qubits.

PubMed

Tan, T R; Gaebler, J P; Lin, Y; Wan, Y; Bowler, R; Leibfried, D; Wineland, D J

2015-12-17

Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. In the field of quantum information processing (QIP) and quantum networking, various proposals discuss the possibility of hybrid architectures where specific tasks are delegated to the most suitable subsystem. For example, in quantum networks, it may be advantageous to transfer information from a subsystem that has good memory properties to another subsystem that is more efficient at transporting information between nodes in the network. For trapped ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. Ions of different elements have previously been used in QIP experiments for sympathetic cooling, creation of entanglement through dissipation, and quantum non-demolition measurement of one species with another. Here we demonstrate an entangling quantum gate between ions of different elements which can serve as an important building block of QIP, quantum networking, precision spectroscopy, metrology, and quantum simulation. A geometric phase gate between a (9)Be(+) ion and a (25)Mg(+) ion is realized through an effective spin-spin interaction generated by state-dependent forces induced with laser beams. Combined with single-qubit gates and same-species entangling gates, this mixed-element entangling gate provides a complete set of gates over such a hybrid system for universal QIP. Using a sequence of such gates, we demonstrate a CNOT (controlled-NOT) gate and a SWAP gate. We further demonstrate the robustness of these gates against thermal excitation and show improved detection in quantum logic spectroscopy. We also observe a strong violation of a CHSH (Clauser-Horne-Shimony-Holt)-type Bell inequality on entangled states composed of different ion species.

[Nano-particles--pharmaceutical "dwarves" with know-how].

PubMed

Ziegler, Andreas S

2008-12-01

Self-cleaning surface coatings, tooth paste with repair effect, mini fuel cells and extremely small data memories, which contain the knowledge of whole libraries: After "micro" in the 1980ies and "electronic" in the 1990ies, "nano" is the technological keyword of this decade. The new nano-materials fascinate laymen and experts alike. Also in pharmacy the advance into dimensions unattainable so far, paved the way for the formulation of new pharmaceutical preparations. The nanotechnology offers innovative answers to previously unresolved galenic and/or biopharmaceutical questions and offers unexpected possibilities for drug targeting.

Nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, Erica

2012-02-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted cooling device. Using theoretical calculations and experimental inputs, we predict that the cooling power of such a device can approach 1kW/cm^2, on par with the best known techniques using standard lithography methods. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

Field programmable gate array-assigned complex-valued computation and its limits

DOE Office of Scientific and Technical Information (OSTI.GOV)

Bernard-Schwarz, Maria, E-mail: maria.bernardschwarz@ni.com; Institute of Applied Physics, TU Wien, Wiedner Hauptstrasse 8, 1040 Wien; Zwick, Wolfgang

We discuss how leveraging Field Programmable Gate Array (FPGA) technology as part of a high performance computing platform reduces latency to meet the demanding real time constraints of a quantum optics simulation. Implementations of complex-valued operations using fixed point numeric on a Virtex-5 FPGA compare favorably to more conventional solutions on a central processing unit. Our investigation explores the performance of multiple fixed point options along with a traditional 64 bits floating point version. With this information, the lowest execution times can be estimated. Relative error is examined to ensure simulation accuracy is maintained.

Electrically floating, near vertical incidence, skywave antenna

DOEpatents

Anderson, Allen A.; Kaser, Timothy G.; Tremblay, Paul A.; Mays, Belva L.

2014-07-08

An Electrically Floating, Near Vertical Incidence, Skywave (NVIS) Antenna comprising an antenna element, a floating ground element, and a grounding element. At least part of said floating ground element is positioned between said antenna element and said grounding element. The antenna is separated from the floating ground element and the grounding element by one or more electrical insulators. The floating ground element is separated from said antenna and said grounding element by one or more electrical insulators.

NULL Convention Floating Point Multiplier

PubMed Central

Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation. PMID:25879069

NULL convention floating point multiplier.

PubMed

Albert, Anitha Juliette; Ramachandran, Seshasayanan

2015-01-01

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.

Stabilized floating platforms

DOEpatents

Thomas, David G.

1976-01-01

The subject invention is directed to a floating platform for supporting nuclear reactors and the like at selected offshore sites. The platform is provided with a stabilizer mechanism which significantly reduces the effects of wave action upon the platform and which comprises a pair of relatively small floats attached by rigid booms to the platform at locations spaced therefrom for reducing wave pitch, acceleration, and the resonance period of the wave.

Fabrication of Nano-Crossbar Resistive Switching Memory Based on the Copper-Tantalum Pentoxide-Platinum Device Structure

NASA Astrophysics Data System (ADS)

Olga Gneri, Paula; Jardim, Marcos

Resistive switching memory has been of interest lately not only for its simple metal-insulator-metal (MIM) structure but also for its promising ease of scalability an integration into current CMOS technologies like the Field Programmable Gate Arrays and other non-volatile memory applications. There are several resistive switching MIM combinations but under this scope of research, attention will be paid to the bipolar resistive switching characteristics and fabrication of Tantalum Pentaoxide sandwiched between platinum and copper. By changing the polarity of the voltage bias, this metal-insulator-metal (MIM) device can be switched between a high resistive state (OFF) and low resistive state (ON). The change in states is induced by an electrochemical metallization process, which causes a formation or dissolution of Cu metal filamentary paths in the Tantalum Pentaoxide insulator. There is very little thorough experimental information about the Cu-Ta 2O5-Pt switching characteristics when scaled to nanometer dimensions. In this light, the MIM structure was fabricated in a two-dimensional crossbar format. Also, with the limited available resources, a multi-spacer technique was formulated to localize the active device area in this MIM configuration to less than 20nm. This step is important in understanding the switching characteristics and reliability of this structure when scaled to nanometer dimensions.

33 CFR 144.01-1 - Life floats.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Life floats. 144.01-1 Section 144... CONTINENTAL SHELF ACTIVITIES LIFESAVING APPLIANCES Manned Platforms § 144.01-1 Life floats. Each manned platform shall be provided with at least two approved life floats. The life floats shall have sufficient...

33 CFR 144.01-1 - Life floats.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 33 Navigation and Navigable Waters 2 2011-07-01 2011-07-01 false Life floats. 144.01-1 Section 144... CONTINENTAL SHELF ACTIVITIES LIFESAVING APPLIANCES Manned Platforms § 144.01-1 Life floats. Each manned platform shall be provided with at least two approved life floats. The life floats shall have sufficient...

33 CFR 144.01-1 - Life floats.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 33 Navigation and Navigable Waters 2 2014-07-01 2014-07-01 false Life floats. 144.01-1 Section 144... CONTINENTAL SHELF ACTIVITIES LIFESAVING APPLIANCES Manned Platforms § 144.01-1 Life floats. Each manned platform shall be provided with at least two approved life floats. The life floats shall have sufficient...

33 CFR 144.01-1 - Life floats.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 33 Navigation and Navigable Waters 2 2012-07-01 2012-07-01 false Life floats. 144.01-1 Section 144... CONTINENTAL SHELF ACTIVITIES LIFESAVING APPLIANCES Manned Platforms § 144.01-1 Life floats. Each manned platform shall be provided with at least two approved life floats. The life floats shall have sufficient...

33 CFR 144.01-1 - Life floats.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 33 Navigation and Navigable Waters 2 2013-07-01 2013-07-01 false Life floats. 144.01-1 Section 144... CONTINENTAL SHELF ACTIVITIES LIFESAVING APPLIANCES Manned Platforms § 144.01-1 Life floats. Each manned platform shall be provided with at least two approved life floats. The life floats shall have sufficient...

14 CFR 23.753 - Main float design.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Main float design. 23.753 Section 23.753... STANDARDS: NORMAL, UTILITY, ACROBATIC, AND COMMUTER CATEGORY AIRPLANES Design and Construction Floats and Hulls § 23.753 Main float design. Each seaplane main float must meet the requirements of § 23.521. [Doc...

Reducing float coal dust

PubMed Central

Patts, J.R.; Colinet, J.F.; Janisko, S.J.; Barone, T.L.; Patts, L.D.

2016-01-01

Controlling float coal dust in underground coal mines before dispersal into the general airstream can reduce the risk of mine explosions while potentially achieving a more effective and efficient use of rock dust. A prototype flooded-bed scrubber was evaluated for float coal dust control in the return of a continuous miner section. The scrubber was installed inline between the face ventilation tubing and an exhausting auxiliary fan. Airborne and deposited dust mass measurements were collected over three days at set distances from the fan exhaust to assess changes in float coal dust levels in the return due to operation of the scrubber. Mass-based measurements were collected on a per-cut basis and normalized on the basis of per ton mined by the continuous miner. The results show that average float coal dust levels measured under baseline conditions were reduced by more than 90 percent when operating the scrubber. PMID:28018004

Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure

PubMed Central

Khan, Z. N.; Ahmed, S.; Ali, M.

2016-01-01

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. PMID:27571412

Light-induced negative differential resistance in gate-controlled graphene-silicon photodiode

NASA Astrophysics Data System (ADS)

Liu, Wei; Guo, Hongwei; Li, Wei; Wan, Xia; Bodepudi, Srikrishna Chanakya; Shehzad, Khurram; Xu, Yang

2018-05-01

In this letter, we investigated light-induced negative differential resistance (L-NDR) effects in a hybrid photodiode formed by a graphene-silicon (GS) junction and a neighboring graphene-oxide-Si (GOS) capacitor. We observed two distinct L-NDR effects originating from the gate-dependent surface recombination and the potential-well-induced confinement of photo-carriers in the GOS region. We verified this by studying the gate-controlled GS diode, which can distinguish the photocurrent from the GS region with that from the GOS region (gate). A large peak-to-valley ratio of up to 12.1 has been obtained for the L-NDR due to gate-dependent surface recombination. Such strong L-NDR effect provides an opportunity to further engineer the optoelectronic properties of GS junctions along with exploring its potential applications in photodetectors, photo-memories, and position sensitive devices.

System and method for floating-substrate passive voltage contrast

DOEpatents

Jenkins, Mark W [Albuquerque, NM; Cole, Jr., Edward I.; Tangyunyong, Paiboon [Albuquerque, NM; Soden, Jerry M [Placitas, NM; Walraven, Jeremy A [Albuquerque, NM; Pimentel, Alejandro A [Albuquerque, NM

2009-04-28

A passive voltage contrast (PVC) system and method are disclosed for analyzing ICs to locate defects and failure mechanisms. During analysis a device side of a semiconductor die containing the IC is maintained in an electrically-floating condition without any ground electrical connection while a charged particle beam is scanned over the device side. Secondary particle emission from the device side of the IC is detected to form an image of device features, including electrical vias connected to transistor gates or to other structures in the IC. A difference in image contrast allows the defects or failure mechanisms be pinpointed. Varying the scan rate can, in some instances, produce an image reversal to facilitate precisely locating the defects or failure mechanisms in the IC. The system and method are useful for failure analysis of ICs formed on substrates (e.g. bulk semiconductor substrates and SOI substrates) and other types of structures.

Rise of Racetrack Memory! Domain Wall Spin-Orbitronics

NASA Astrophysics Data System (ADS)

Parkin, Stuart

Memory-storage devices based on the current controlled motion of a series of domain walls (DWs) in magnetic racetracks promise performance and reliability beyond that of conventional magnetic disk drives and solid state storage devices (1). Racetracks that are formed from atomically thin, perpendicularly magnetized nano-wires, interfaced with adjacent metal layers with high spin-orbit coupling, give rise to domain walls that exhibit a chiral Néel structure (2). These DWs can be moved very efficiently with current via chiral spin-orbit torques (2,3). Record-breaking current-induced DW speeds exceeding 1,000 m/sec are found in synthetic antiferromagnetic structures (3) in which the net magnetization of the DWs is tuned to almost zero, making them ``invisible''. Based on these recent discoveries, Racetrack Memory devices have the potential to operate on picosecond timescales and at densities more than 100 times greater than other memory technologies. (1) S.S.P. Parkin et al., Science 320, 5873 (2008); S.S.P. Parkin and S.-H. Yang, Nat. Nano. 10, 195 (2015). (2) K.-S. Ryu metal. Nat. Nano. 8, 527 (2013). (3) S.-H. Yang, K.-S. Ryu and S.S.P. Parkin, Nat. Nano. 10, 221 (2015). (4). S.S.P. Parkin, Phys. Rev. Lett. 67, 3598 (1991).

Have Floating Rates Been a Success?

ERIC Educational Resources Information Center

Higham, David

1983-01-01

Floating exchange rates have not lived up to all expectations, but neither have they performed as badly as some critics have suggested. Examined are the impact of floating rates on balance of payments adjustment, domestic economic policy, and inflation and the claim that floating rates have displayed excessive fluctuations. (Author/RM)

Error correction in short time steps during the application of quantum gates

DOE Office of Scientific and Technical Information (OSTI.GOV)

Castro, L.A. de, E-mail: leonardo.castro@usp.br; Napolitano, R.D.J.

2016-04-15

We propose a modification of the standard quantum error-correction method to enable the correction of errors that occur due to the interaction with a noisy environment during quantum gates without modifying the codification used for memory qubits. Using a perturbation treatment of the noise that allows us to separate it from the ideal evolution of the quantum gate, we demonstrate that in certain cases it is necessary to divide the logical operation in short time steps intercalated by correction procedures. A prescription of how these gates can be constructed is provided, as well as a proof that, even for themore » cases when the division of the quantum gate in short time steps is not necessary, this method may be advantageous for reducing the total duration of the computation.« less

On floats and float tests

NASA Technical Reports Server (NTRS)

Seewald, Friedrich

1931-01-01

The principal source of information on float resistance is the model test. In view of the insuperable difficulties opposing any attempt at theoretical treatment of the resistance problem, particularly at attitudes which tend toward satisfactory take-off, such as the transitory stage to planing, the towing test is and will remain the primary method for some time.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

NASA Astrophysics Data System (ADS)

Nedic, Stanko; Tea Chun, Young; Hong, Woong-Ki; Chu, Daping; Welland, Mark

2014-01-01

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ˜16.5 V, a high drain current on/off ratio of ˜105, a gate leakage current below ˜300 pA, and excellent retention characteristics for over 104 s.

Group-Velocity-Controlled and Gate-Tunable Directional Excitation of Polaritons in Graphene-Boron Nitride Heterostructures

NASA Astrophysics Data System (ADS)

Jiang, Yuyu; Lin, Xiao; Low, Tony; Zhang, Baile; Chen, Hongsheng

2018-05-01

A fundamental building block in nano-photonics is the ability to directionally excite highly squeezed optical mode dynamically, particularly with an electrical bias. Such capabilities would enable the active manipulation of light propagation for information processing and transfer. However, when the optical source is built-in, it remains challenging to steer the excitation directionality in a flexible way. Here, we reveal a novel mechanism for tunable directional excitation of highly squeezed polaritons in graphene-hexagonal boron nitride (hBN) heterostructures. The effect relies on controlling the sign of the group velocity of the coupled plasmon-phonon polaritons, which can be flipped by simply tuning the chemical potential of graphene (through electrostatic gating) in the heterostructures. Graphene-hBN heterostructure thus present a promising platform toward nano-photonic circuits and nano-devices with electrically reconfigurable functionalities.

Nonvolatile ferroelectric memory based on PbTiO3 gated single-layer MoS2 field-effect transistor

NASA Astrophysics Data System (ADS)

Shin, Hyun Wook; Son, Jong Yeog

2018-01-01

We fabricated ferroelectric non-volatile random access memory (FeRAM) based on a field effect transistor (FET) consisting of a monolayer MoS2 channel and a ferroelectric PbTiO3 (PTO) thin film of gate insulator. An epitaxial PTO thin film was deposited on a Nb-doped SrTiO3 (Nb:STO) substrate via pulsed laser deposition. A monolayer MoS2 sheet was exfoliated from a bulk crystal and transferred to the surface of the PTO/Nb:STO. Structural and surface properties of the PTO thin film were characterized by X-ray diffraction and atomic force microscopy, respectively. Raman spectroscopy analysis was performed to identify the single-layer MoS2 sheet on the PTO/Nb:STO. We obtained mobility value (327 cm2/V·s) of the MoS2 channel at room temperature. The MoS2-PTO FeRAM FET showed a wide memory window with 17 kΩ of resistance variation which was attributed to high remnant polarization of the epitaxially grown PTO thin film. According to the fatigue resistance test for the FeRAM FET, however, the resistance states gradually varied during the switching cycles of 109. [Figure not available: see fulltext.

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE PAGES

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.; ...

2014-10-15

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Atomic layer deposition TiO 2-Al 2O 3 stack: An improved gate dielectric on Ga-polar GaN metal oxide semiconductor capacitors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Wei, Daming; Edgar, James H.; Briggs, Dayrl P.

This research focuses on the benefits and properties of TiO 2-Al 2O 3 nano-stack thin films deposited on Ga 2O 3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films’ structure, composition, and electrical properties. The gate dielectrics were approximately 15 nm thick and contained 5.1 nm TiO 2, 7.1 nm Al 2O 3 and 2 nm Ga 2O 3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectronmore » spectroscopy (XPS) depth profile, was negligible for GaN pretreated by thermal oxidation in O 2 for 30 minutes at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nano-stack, as determined by atomic force microscopy. The dielectric constant of TiO 2-Al 2O 3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al 2O 3 (8~9) on GaN. In addition, the nano-stack's capacitance-voltage (C-V) hysteresis was small, with a total trap density of 8.74 × 10 11 cm -2. The gate leakage current density (J=2.81× 10 -8 A/cm 2) was low at +1 V gate bias. These results demonstrate the promising potential of plasma ALD deposited TiO 2/Al 2O 3 for serving as the gate oxide on Ga 2O 3/GaN based MOS devices.« less

Systems and methods for detecting a failure event in a field programmable gate array

NASA Technical Reports Server (NTRS)

Ng, Tak-Kwong (Inventor); Herath, Jeffrey A. (Inventor)

2009-01-01

An embodiment generally relates to a method of self-detecting an error in a field programmable gate array (FPGA). The method includes writing a signature value into a signature memory in the FPGA and determining a conclusion of a configuration refresh operation in the FPGA. The method also includes reading an outcome value from the signature memory.

Analytical study of nano-scale logical operations

NASA Astrophysics Data System (ADS)

Patra, Moumita; Maiti, Santanu K.

2018-07-01

A complete analytical prescription is given to perform three basic (OR, AND, NOT) and two universal (NAND, NOR) logic gates at nano-scale level using simple tailor made geometries. Two different geometries, ring-like and chain-like, are taken into account where in each case the bridging conductor is coupled to a local atomic site through a dangling bond whose site energy can be controlled by means of external gate electrode. The main idea is that when injecting electron energy matches with site energy of local atomic site transmission probability drops exactly to zero, whereas the junction exhibits finite transmission for other energies. Utilizing this prescription we perform logical operations, and, we strongly believe that the proposed results can be verified in laboratory. Finally, we numerically compute two-terminal transmission probability considering general models and the numerical results match exactly well with our analytical findings.

Skyrmion domain wall collision and domain wall-gated skyrmion logic

NASA Astrophysics Data System (ADS)

Xing, Xiangjun; Pong, Philip W. T.; Zhou, Yan

2016-08-01

Skyrmions and domain walls are significant spin textures of great technological relevance to magnetic memory and logic applications, where they can be used as carriers of information. The unique topology of skyrmions makes them display emergent dynamical properties as compared with domain walls. Some studies have demonstrated that the two topologically inequivalent magnetic objects could be interconverted by using cleverly designed geometric structures. Here, we numerically address the skyrmion domain wall collision in a magnetic racetrack by introducing relative motion between the two objects based on a specially designed junction. An electric current serves as the driving force that moves a skyrmion toward a trapped domain wall pair. We see different types of collision dynamics depending on the driving parameters. Most importantly, the modulation of skyrmion transport using domain walls is realized in this system, allowing a set of domain wall-gated logical NOT, NAND, and NOR gates to be constructed. This work provides a skyrmion-based spin-logic architecture that is fully compatible with racetrack memories.

Another expert system rule inference based on DNA molecule logic gates

NASA Astrophysics Data System (ADS)

WÄ siewicz, Piotr

2013-10-01

With the help of silicon industry microfluidic processors were invented utilizing nano membrane valves, pumps and microreactors. These so called lab-on-a-chips combined together with molecular computing create molecular-systems-ona- chips. This work presents a new approach to implementation of molecular inference systems. It requires the unique representation of signals by DNA molecules. The main part of this work includes the concept of logic gates based on typical genetic engineering reactions. The presented method allows for constructing logic gates with many inputs and for executing them at the same quantity of elementary operations, regardless of a number of input signals. Every microreactor of the lab-on-a-chip performs one unique operation on input molecules and can be connected by dataflow output-input connections to other ones.

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeod, Todd C.; Ho, Fat Duen

2005-01-01

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

H-terminated diamond field effect transistor with ferroelectric gate insulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Karaya, Ryota; Furuichi, Hiroki; Nakajima, Takashi

2016-06-13

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50 mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory windowmore » width was 19 V, when the gate voltage was swept from 20 to −20 V. The maximum on/off current ratio and the linear mobility were 10{sup 8} and 398 cm{sup 2}/V s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE gate and obtained an on/off current ratio of 10{sup 3} without applying a DC gate voltage.« less

Verification of floating-point software

NASA Technical Reports Server (NTRS)

Hoover, Doug N.

1990-01-01

Floating point computation presents a number of problems for formal verification. Should one treat the actual details of floating point operations, or accept them as imprecisely defined, or should one ignore round-off error altogether and behave as if floating point operations are perfectly accurate. There is the further problem that a numerical algorithm usually only approximately computes some mathematical function, and we often do not know just how good the approximation is, even in the absence of round-off error. ORA has developed a theory of asymptotic correctness which allows one to verify floating point software with a minimum entanglement in these problems. This theory and its implementation in the Ariel C verification system are described. The theory is illustrated using a simple program which finds a zero of a given function by bisection. This paper is presented in viewgraph form.

Protected quantum computing: interleaving gate operations with dynamical decoupling sequences.

PubMed

Zhang, Jingfu; Souza, Alexandre M; Brandao, Frederico Dias; Suter, Dieter

2014-02-07

Implementing precise operations on quantum systems is one of the biggest challenges for building quantum devices in a noisy environment. Dynamical decoupling attenuates the destructive effect of the environmental noise, but so far, it has been used primarily in the context of quantum memories. Here, we experimentally demonstrate a general scheme for combining dynamical decoupling with quantum logical gate operations using the example of an electron-spin qubit of a single nitrogen-vacancy center in diamond. We achieve process fidelities >98% for gate times that are 2 orders of magnitude longer than the unprotected dephasing time T2.

Repeat-until-success cubic phase gate for universal continuous-variable quantum computation

DOE Office of Scientific and Technical Information (OSTI.GOV)

Marshall, Kevin; Pooser, Raphael; Siopsis, George

2015-03-24

We report that to achieve universal quantum computation using continuous variables, one needs to jump out of the set of Gaussian operations and have a non-Gaussian element, such as the cubic phase gate. However, such a gate is currently very difficult to implement in practice. Here we introduce an experimentally viable “repeat-until-success” approach to generating the cubic phase gate, which is achieved using sequential photon subtractions and Gaussian operations. Ultimately, we find that our scheme offers benefits in terms of the expected time until success, as well as the fact that we do not require any complex off-line resource state,more » although we require a primitive quantum memory.« less

The floating anchored craniotomy

PubMed Central

Gutman, Matthew J.; How, Elena; Withers, Teresa

2017-01-01

Background: The “floating anchored” craniotomy is a technique utilized at our tertiary neurosurgery institution in which a traditional decompressive craniectomy has been substituted for a floating craniotomy. The hypothesized advantages of this technique include adequate decompression, reduction in the intracranial pressure, obviating the need for a secondary cranioplasty, maintained bone protection, preventing the syndrome of the trephined, and a potential reduction in axonal stretching. Methods: The bone plate is re-attached via multiple loosely affixed vicryl sutures, enabling decompression, but then ensuring the bone returns to its anatomical position once cerebral edema has subsided. Results: From the analysis of 57 consecutive patients analyzed at our institution, we have found that the floating anchored craniotomy is comparable to decompressive craniectomy for intracranial pressure reduction and has some significant theoretical advantages. Conclusions: Despite the potential advantages of techniques that avoid the need for a second cranioplasty, they have not been widely adopted and have been omitted from trials examining the utility of decompressive surgery. This retrospective analysis of prospectively collected data suggests that the floating anchored craniotomy may be applicable instead of decompressive craniectomy. PMID:28713633

A comparison of the Cray-2 performance before and after the installation of memory pseudo-banking

NASA Technical Reports Server (NTRS)

Schmickley, Ronald D.; Bailey, David H.

1987-01-01

A suite of 13 large Fortran benchmark codes were run on a Cray-2 configured with memory pseudo-banking circuits, and floating point operation rates were measured for each under a variety of system load configurations. These were compared with similar flop measurements taken on the same system before installation of the pseudo-banking. A useful memory access efficiency parameter was defined and calculated for both sets of performance rates, allowing a crude quantitative measure of the improvement in efficiency due to pseudo-banking. Programs were categorized as either highly scalar (S) or highly vectorized (V) and either memory-intensive or register-intensive, giving 4 categories: S-memory, S-register, V-memory, and V-register. Using flop rates as a simple quantifier of these 4 categories, a scatter plot of efficiency gain vs Mflops roughly illustrates the improvement in floating point processing speed due to pseudo-banking. On the Cray-2 system tested this improvement ranged from 1 percent for S-memory codes to about 12 percent for V-memory codes. No significant gains were made for V-register codes, which was to be expected.

Ionic Liquid Gating Control of Spin Reorientation Transition and Switching of Perpendicular Magnetic Anisotropy.

PubMed

Zhao, Shishun; Wang, Lei; Zhou, Ziyao; Li, Chunlei; Dong, Guohua; Zhang, Le; Peng, Bin; Min, Tai; Hu, Zhongqiang; Ma, Jing; Ren, Wei; Ye, Zuo-Guang; Chen, Wei; Yu, Pu; Nan, Ce-Wen; Liu, Ming

2018-05-29

Electric field (E-field) modulation of perpendicular magnetic anisotropy (PMA) switching, in an energy-efficient manner, is of great potential to realize magnetoelectric (ME) memories and other ME devices. Voltage control of the spin-reorientation transition (SRT) that allows the magnetic moment rotating between the out-of-plane and the in-plane direction is thereby crucial. In this work, a remarkable magnetic anisotropy field change up to 1572 Oe is achieved under a small operation voltage of 4 V through ionic liquid (IL) gating control of SRT in Au/[DEME] + [TFSI] - /Pt/(Co/Pt) 2 /Ta capacitor heterostructures at room temperature, corresponding to a large ME coefficient of 378 Oe V -1 . As revealed by both ferromagnetic resonance measurements and magnetic domain evolution observation, the magnetization can be switched stably and reversibly between the out-of-plane and in-plane directions via IL gating. The key mechanism, revealed by the first-principles calculation, is that the IL gating process influences the interfacial spin-orbital coupling as well as net Rashba magnetic field between the Co and Pt layers, resulting in the modulation of the SRT and in-plane/out-of-plane magnetization switching. This work demonstrates a unique IL-gated PMA with large ME tunability and paves a way toward IL gating spintronic/electronic devices such as voltage tunable PMA memories. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 49 Transportation 4 2010-10-01 2010-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 49 Transportation 4 2011-10-01 2011-10-01 false Gate arm and gate mechanism. 234.255 Section 234... Maintenance, Inspection, and Testing Inspections and Tests § 234.255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be...

14 CFR 25.753 - Main float design.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Main float design. 25.753 Section 25.753 Aeronautics and Space FEDERAL AVIATION ADMINISTRATION, DEPARTMENT OF TRANSPORTATION AIRCRAFT AIRWORTHINESS STANDARDS: TRANSPORT CATEGORY AIRPLANES Design and Construction Floats and Hulls § 25.753 Main float design...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 49 Transportation 4 2013-10-01 2013-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 49 Transportation 4 2014-10-01 2014-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c...

49 CFR 234.255 - Gate arm and gate mechanism.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 49 Transportation 4 2012-10-01 2012-10-01 false Gate arm and gate mechanism. 234.255 Section 234....255 Gate arm and gate mechanism. (a) Each gate arm and gate mechanism shall be inspected at least once each month. (b) Gate arm movement shall be observed for proper operation at least once each month. (c...

Reprogrammable field programmable gate array with integrated system for mitigating effects of single event upsets

NASA Technical Reports Server (NTRS)

Ng, Tak-kwong (Inventor); Herath, Jeffrey A. (Inventor)

2010-01-01

An integrated system mitigates the effects of a single event upset (SEU) on a reprogrammable field programmable gate array (RFPGA). The system includes (i) a RFPGA having an internal configuration memory, and (ii) a memory for storing a configuration associated with the RFPGA. Logic circuitry programmed into the RFPGA and coupled to the memory reloads a portion of the configuration from the memory into the RFPGA's internal configuration memory at predetermined times. Additional SEU mitigation can be provided by logic circuitry on the RFPGA that monitors and maintains synchronized operation of the RFPGA's digital clock managers.

Dual-Gated Active Metasurface at 1550 nm with Wide (>300°) Phase Tunability.

PubMed

Kafaie Shirmanesh, Ghazaleh; Sokhoyan, Ruzan; Pala, Ragip A; Atwater, Harry A

2018-05-09

Active metasurfaces composed of electrically reconfigurable nanoscale subwavelength antenna arrays can enable real-time control of scattered light amplitude and phase. Achievement of widely tunable phase and amplitude in chip-based active metasurfaces operating at or near 1550 nm wavelength has considerable potential for active beam steering, dynamic hologram rendition, and realization of flat optics with reconfigurable focal lengths. Previously, electrically tunable conducting oxide-based reflectarray metasurfaces have demonstrated dynamic phase control of reflected light with a maximum phase shift of 184° ( Nano Lett. 2016 , 16 , 5319 ). Here, we introduce a dual-gated reflectarray metasurface architecture that enables much wider (>300°) phase tunability. We explore light-matter interactions with dual-gated metasurface elements that incorporate two independent voltage-controlled MOS field effect channels connected in series to form a single metasurface element that enables wider phase tunability. Using indium tin oxide (ITO) as the active metasurface material and a composite hafnia/alumina gate dielectric, we demonstrate a prototype dual-gated metasurface with a continuous phase shift from 0 to 303° and a relative reflectance modulation of 89% under applied voltage bias of 6.5 V.

40 CFR 63.1063 - Floating roof requirements.

Code of Federal Regulations, 2010 CFR

2010-07-01

... the point of refloating the floating roof shall be continuous and shall be performed as soon as... 40 Protection of Environment 10 2010-07-01 2010-07-01 false Floating roof requirements. 63.1063...) National Emission Standards for Storage Vessels (Tanks)-Control Level 2 § 63.1063 Floating roof...

Evaluation of Magnetoresistive RAM for Space Applications

NASA Technical Reports Server (NTRS)

Heidecker, Jason

2014-01-01

Magnetoresistive random-access memory (MRAM) is a non-volatile memory that exploits electronic spin, rather than charge, to store data. Instead of moving charge on and off a floating gate to alter the threshold voltage of a CMOS transistor (creating different bit states), MRAM uses magnetic fields to flip the polarization of a ferromagnetic material thus switching its resistance and bit state. These polarized states are immune to radiation-induced upset, thus making MRAM very attractive for space application. These magnetic memory elements also have infinite data retention and erase/program endurance. Presented here are results of reliability testing of two space-qualified MRAM products from Aeroflex and Honeywell.

Cellular defibrillation: interaction of micro-scale electric fields with voltage-gated ion channels.

PubMed

Kargol, Armin; Malkinski, Leszek; Eskandari, Rahmatollah; Carter, Maya; Livingston, Daniel

2015-09-01

We study the effect of micro-scale electric fields on voltage-gated ion channels in mammalian cell membranes. Such micro- and nano-scale electric fields mimic the effects of multiferroic nanoparticles that were recently proposed [1] as a novel way of controlling the function of voltage-sensing biomolecules such as ion channels. This article describes experimental procedures and initial results that reveal the effect of the electric field, in close proximity of cells, on the ion transport through voltage-gated ion channels. We present two configurations of the whole-cell patch-clamping apparatus that were used to detect the effect of external stimulation on ionic currents and discuss preliminary results that indicate modulation of the ionic currents consistent with the applied stimulus.

Program Converts VAX Floating-Point Data To UNIX

NASA Technical Reports Server (NTRS)

Alves, Marcos; Chapman, Bruce; Chu, Eugene

1996-01-01

VAX Floating Point to Host Floating Point Conversion (VAXFC) software converts non-ASCII files to unformatted floating-point representation of UNIX machine. This is done by reading bytes bit by bit, converting them to floating-point numbers, then writing results to another file. Useful when data files created by VAX computer must be used on other machines. Written in C language.

Fredkin and Toffoli Gates Implemented in Oregonator Model of Belousov-Zhabotinsky Medium

NASA Astrophysics Data System (ADS)

Adamatzky, Andrew

A thin-layer Belousov-Zhabotinsky (BZ) medium is a powerful computing device capable for implementing logical circuits, memory, image processors, robot controllers, and neuromorphic architectures. We design the reversible logical gates — Fredkin gate and Toffoli gate — in a BZ medium network of excitable channels with subexcitable junctions. Local control of the BZ medium excitability is an important feature of the gates’ design. An excitable thin-layer BZ medium responds to a localized perturbation with omnidirectional target or spiral excitation waves. A subexcitable BZ medium responds to an asymmetric perturbation by producing traveling localized excitation wave-fragments similar to dissipative solitons. We employ interactions between excitation wave-fragments to perform the computation. We interpret the wave-fragments as values of Boolean variables. The presence of a wave-fragment at a given site of a circuit represents the logical truth, absence of the wave-fragment — logically false. Fredkin gate consists of ten excitable channels intersecting at 11 junctions, eight of which are subexcitable. Toffoli gate consists of six excitable channels intersecting at six junctions, four of which are subexcitable. The designs of the gates are verified using numerical integration of two-variable Oregonator equations.

Constrained Chebyshev approximations to some elementary functions suitable for evaluation with floating point arithmetic

NASA Technical Reports Server (NTRS)

Manos, P.; Turner, L. R.

1972-01-01

Approximations which can be evaluated with precision using floating-point arithmetic are presented. The particular set of approximations thus far developed are for the function TAN and the functions of USASI FORTRAN excepting SQRT and EXPONENTIATION. These approximations are, furthermore, specialized to particular forms which are especially suited to a computer with a small memory, in that all of the approximations can share one general purpose subroutine for the evaluation of a polynomial in the square of the working argument.

Attenuated effect of tungsten carbide nanoparticles on voltage-gated sodium current of hippocampal CA1 pyramidal neurons.

PubMed

Shan, Dehong; Xie, Yongling; Ren, Guogang; Yang, Zhuo

2013-02-01

Nanomaterials and relevant products are now being widely used in the world, and their safety becomes a great concern for the general public. Tungsten carbide nanoparticles (nano-WC) are widely used in metallurgy, aeronautics and astronautics, however our knowledge regarding the influence of nano-WC on neurons is still lacking. The aim of this study was to investigate the impact of nano-WC on tetrodotoxin (TTX)-sensitive voltage-activated sodium current (I(Na)) of hippocampal CA1 pyramidal neurons. Results showed that acute exposure of nano-WC attenuated the peak amplitudes of I(Na) in a concentration-dependent manner. The minimal effective concentration was 10(-5)g/ml. The exposure of nano-WC significantly decreased current amplitudes of the current-voltage curves of I(Na) from -50 to+50 mV, shifted the steady-state activation and inactivation curves of I(Na) negatively and delayed the recovery of I(Na) from inactivation state. After exposure to nano-WC, the peak amplitudes, overshoots and the V-thresholds of action potentials (APs) were markedly reduced. These results suggested that exposure of nano-WC could influence some characteristics of APs evoked from the hippocampal CA1 neurons by modifying the kinetics of voltage-gated sodium channels (VGSCs). Copyright © 2012 Elsevier Ltd. All rights reserved.

Alpha power gates relevant information during working memory updating.

PubMed

Manza, Peter; Hau, Chui Luen Vera; Leung, Hoi-Chung

2014-04-23

Human working memory (WM) is inherently limited, so we must filter out irrelevant information in our environment or our mind while retaining limited important relevant contents. Previous work suggests that neural oscillations in the alpha band (8-14 Hz) play an important role in inhibiting incoming distracting information during attention and selective encoding tasks. However, whether alpha power is involved in inhibiting no-longer-relevant content or in representing relevant WM content is still debated. To clarify this issue, we manipulated the amount of relevant/irrelevant information using a task requiring spatial WM updating while measuring neural oscillatory activity via EEG and localized current sources across the scalp using a surface Laplacian transform. An initial memory set of two, four, or six spatial locations was to be memorized over a delay until an updating cue was presented indicating that only one or three locations remained relevant for a subsequent recognition test. Alpha amplitude varied with memory maintenance and updating demands among a cluster of left frontocentral electrodes. Greater postcue alpha power was associated with the high relevant load conditions (six and four dots cued to reduce to three relevant) relative to the lower load conditions (four and two dots reduced to one). Across subjects, this difference in alpha power was correlated with condition differences in performance accuracy. In contrast, no significant effects of irrelevant load were observed. These findings demonstrate that, during WM updating, alpha power reflects maintenance of relevant memory contents rather than suppression of no-longer-relevant memory traces.

Temperature variations at nano-scale level in phase transformed nanocrystalline NiTi shape memory alloys adjacent to graphene layers.

PubMed

Amini, Abbas; Cheng, Chun; Naebe, Minoo; Church, Jeffrey S; Hameed, Nishar; Asgari, Alireza; Will, Frank

2013-07-21

The detection and control of the temperature variation at the nano-scale level of thermo-mechanical materials during a compression process have been challenging issues. In this paper, an empirical method is proposed to predict the temperature at the nano-scale level during the solid-state phase transition phenomenon in NiTi shape memory alloys. Isothermal data was used as a reference to determine the temperature change at different loading rates. The temperature of the phase transformed zone underneath the tip increased by ∼3 to 40 °C as the loading rate increased. The temperature approached a constant with further increase in indentation depth. A few layers of graphene were used to enhance the cooling process at different loading rates. Due to the presence of graphene layers the temperature beneath the tip decreased by a further ∼3 to 10 °C depending on the loading rate. Compared with highly polished NiTi, deeper indentation depths were also observed during the solid-state phase transition, especially at the rate dependent zones. Larger superelastic deformations confirmed that the latent heat transfer through the deposited graphene layers allowed a larger phase transition volume and, therefore, more stress relaxation and penetration depth.

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; Bailey, Mark; Ho, Fat Duen

2004-01-01

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Quasi-classical modeling of molecular quantum-dot cellular automata multidriver gates

NASA Astrophysics Data System (ADS)

Rahimi, Ehsan; Nejad, Shahram Mohammad

2012-05-01

Molecular quantum-dot cellular automata (mQCA) has received considerable attention in nanoscience. Unlike the current-based molecular switches, where the digital data is represented by the on/off states of the switches, in mQCA devices, binary information is encoded in charge configuration within molecular redox centers. The mQCA paradigm allows high device density and ultra-low power consumption. Digital mQCA gates are the building blocks of circuits in this paradigm. Design and analysis of these gates require quantum chemical calculations, which are demanding in computer time and memory. Therefore, developing simple models to probe mQCA gates is of paramount importance. We derive a semi-classical model to study the steady-state output polarization of mQCA multidriver gates, directly from the two-state approximation in electron transfer theory. The accuracy and validity of this model are analyzed using full quantum chemistry calculations. A complete set of logic gates, including inverters and minority voters, are implemented to provide an appropriate test bench in the two-dot mQCA regime. We also briefly discuss how the QCADesigner tool could find its application in simulation of mQCA devices.

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

NASA Technical Reports Server (NTRS)

Phillips, Thomas A.; MacLeond, Todd C.; Sayyah, Rana; Ho, Fat Duen

2009-01-01

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Modeling International Space Station (ISS) Floating Potentials

NASA Technical Reports Server (NTRS)

Ferguson, Dale C.; Gardner, Barbara

2002-01-01

The floating potential of the International Space Station (ISS) as a function of the electron current collection of its high voltage solar array panels is derived analytically. Based on Floating Potential Probe (FPP) measurements of the ISS potential and ambient plasma characteristics, it is shown that the ISS floating potential is a strong function of the electron temperature of the surrounding plasma. While the ISS floating potential has so far not attained the pre-flight predicted highly negative values, it is shown that for future mission builds, ISS must continue to provide two-fault tolerant arc-hazard protection for astronauts on EVA.

Electrical properties of nano-resistors made from the Zr-doped HfO2 high-k dielectric film

NASA Astrophysics Data System (ADS)

Zhang, Shumao; Kuo, Yue

2018-03-01

Electrical properties of nano-sized resistors made from the breakdown of the metal-oxide-semiconductor capacitor composed of the amorphous high-k gate dielectric have been investigated under different stress voltages and temperatures. The effective resistance of nano-resistors in the device was estimated from the I-V curve in the high voltage range. It decreased with the increase of the number of resistors. The resistance showed complicated temperature dependence, i.e. it neither behaves like a conductor nor a semiconductor. In the low voltage operation range, the charge transfer was controlled by the Schottky barrier at the nano-resistor/Si interface. The barrier height decreased with the increase of stress voltage, which was probably caused by the change of the nano-resistor composition. Separately, it was observed that the barrier height was dependent on the temperature, which was probably due to the dynamic nano-resistor formation process and the inhomogeneous barrier height distribution. The unique electrical characteristics of this new type of nano-resistors are important for many electronic and optoelectronic applications.

Does It Sink or Float?

ERIC Educational Resources Information Center

McDonald, Judith Richards

2012-01-01

This activity is designed to teach prekindergarten to second grade students about the concept of sink or float through an inquiry activity. Students will use familiar objects to predict and test the properties of sink and float. Background information is offered to teachers to assist them with this activity. This lesson begins with an engaging…

14 CFR 29.757 - Hull and auxiliary float strength.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false Hull and auxiliary float strength. 29.757... AIRCRAFT AIRWORTHINESS STANDARDS: TRANSPORT CATEGORY ROTORCRAFT Design and Construction Floats and Hulls § 29.757 Hull and auxiliary float strength. The hull, and auxiliary floats if used, must withstand the...

Rapid Obtaining of Nano-Hydroxyapatite Bioactive Films on NiTi Shape Memory Alloy by Electrodeposition Process

NASA Astrophysics Data System (ADS)

Lobo, A. O.; Otubo, J.; Matsushima, J. T.; Corat, E. J.

2011-07-01

Nano-hydroxyapatite (n-HA) crystalline films have been developed in this study by electrodeposition method on NiTi shape memory alloy (SMA). The electrodeposition of the n-HA films was carried out using 0.042 mol/L Ca(NO3)2 · 4H2O + 0.025 mol/L (NH4) · 2HPO4 electrolytes by applying a constant potential of -2.0 V for 120 min and keeping the solution temperature at 70 °C. The characterization of n-HA films is of special importance since bioactive properties related to n-HA have been directly identified with its specific composition and crystalline structure. AFM, XRD, EDX, FEG-SEM and Raman spectroscopy shows a homogeneous film, with high crystallinity, special composition, and bioactivity properties (Ca/P = 1.93) of n-HA on NiTi SMA surfaces. The n-HA coating with special structure would benefit the use of NiTi alloy in orthopedic applications.

Fast quantum logic gates with trapped-ion qubits

NASA Astrophysics Data System (ADS)

Schäfer, V. M.; Ballance, C. J.; Thirumalai, K.; Stephenson, L. J.; Ballance, T. G.; Steane, A. M.; Lucas, D. M.

2018-03-01

Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural ‘speed limit’ of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds—less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually

Fast quantum logic gates with trapped-ion qubits.

PubMed

Schäfer, V M; Ballance, C J; Thirumalai, K; Stephenson, L J; Ballance, T G; Steane, A M; Lucas, D M

2018-02-28

Quantum bits (qubits) based on individual trapped atomic ions are a promising technology for building a quantum computer. The elementary operations necessary to do so have been achieved with the required precision for some error-correction schemes. However, the essential two-qubit logic gate that is used to generate quantum entanglement has hitherto always been performed in an adiabatic regime (in which the gate is slow compared with the characteristic motional frequencies of the ions in the trap), resulting in logic speeds of the order of 10 kilohertz. There have been numerous proposals of methods for performing gates faster than this natural 'speed limit' of the trap. Here we implement one such method, which uses amplitude-shaped laser pulses to drive the motion of the ions along trajectories designed so that the gate operation is insensitive to the optical phase of the pulses. This enables fast (megahertz-rate) quantum logic that is robust to fluctuations in the optical phase, which would otherwise be an important source of experimental error. We demonstrate entanglement generation for gate times as short as 480 nanoseconds-less than a single oscillation period of an ion in the trap and eight orders of magnitude shorter than the memory coherence time measured in similar calcium-43 hyperfine qubits. The power of the method is most evident at intermediate timescales, at which it yields a gate error more than ten times lower than can be attained using conventional techniques; for example, we achieve a 1.6-microsecond-duration gate with a fidelity of 99.8 per cent. Faster and higher-fidelity gates are possible at the cost of greater laser intensity. The method requires only a single amplitude-shaped pulse and one pair of beams derived from a continuous-wave laser. It offers the prospect of combining the unrivalled coherence properties, operation fidelities and optical connectivity of trapped-ion qubits with the submicrosecond logic speeds that are usually associated

Tunable nano Peltier cooling device from geometric effects using a single graphene nanoribbon

NASA Astrophysics Data System (ADS)

Li, Wan-Ju; Yao, Dao-Xin; Carlson, E. W.

2014-08-01

Based on the phenomenon of curvature-induced doping in graphene we propose a class of Peltier cooling devices, produced by geometrical effects, without gating. We show how a graphene nanoribbon laid on an array of curved nano cylinders can be used to create a targeted and tunable cooling device. Using two different approaches, the Nonequilibrium Green's Function (NEGF) method and experimental inputs, we predict that the cooling power of such a device can approach the order of kW/cm2, on par with the best known techniques using standard superlattice structures. The structure proposed here helps pave the way toward designing graphene electronics which use geometry rather than gating to control devices.

Stools - floating

MedlinePlus

... diagnosis. Alternative Names Floating stools Images Lower digestive anatomy References Schiller LR, Sellin JH. Diarrhea. In: Feldman M, Friedman LS, Brandt LJ, eds. Sleisenger and Fordtran's Gastrointestinal and Liver Disease . 10th ed. Philadelphia, PA: Elsevier Saunders; 2016: ...

Floating point arithmetic in future supercomputers

NASA Technical Reports Server (NTRS)

Bailey, David H.; Barton, John T.; Simon, Horst D.; Fouts, Martin J.

1989-01-01

Considerations in the floating-point design of a supercomputer are discussed. Particular attention is given to word size, hardware support for extended precision, format, and accuracy characteristics. These issues are discussed from the perspective of the Numerical Aerodynamic Simulation Systems Division at NASA Ames. The features believed to be most important for a future supercomputer floating-point design include: (1) a 64-bit IEEE floating-point format with 11 exponent bits, 52 mantissa bits, and one sign bit and (2) hardware support for reasonably fast double-precision arithmetic.

Synchronized femtosecond laser pulse switching system based nano-patterning technology

NASA Astrophysics Data System (ADS)

Sohn, Ik-Bu; Choi, Hun-Kook; Yoo, Dongyoon; Noh, Young-Chul; Sung, Jae-Hee; Lee, Seong-Ku; Ahsan, Md. Shamim; Lee, Ho

2017-07-01

This paper demonstrates the design and development of a synchronized femtosecond laser pulse switching system and its applications in nano-patterning of transparent materials. Due to synchronization, we are able to control the location of each irradiated laser pulse in any kind of substrate. The control over the scanning speed and scanning step of the laser beam enables us to pattern periodic micro/nano-metric holes, voids, and/or lines in various materials. Using the synchronized laser system, we pattern synchronized nano-holes on the surface of and inside various transparent materials including fused silica glass and polymethyl methacrylate to replicate any image or pattern on the surface of or inside (transparent) materials. We also investigate the application areas of the proposed synchronized femtosecond laser pulse switching system in a diverse field of science and technology, especially in optical memory, color marking, and synchronized micro/nano-scale patterning of materials.

Float processing of high-temperature complex silicate glasses and float baths used for same

NASA Technical Reports Server (NTRS)

Cooper, Reid Franklin (Inventor); Cook, Glen Bennett (Inventor)

2000-01-01

A float glass process for production of high melting temperature glasses utilizes a binary metal alloy bath having the combined properties of a low melting point, low reactivity with oxygen, low vapor pressure, and minimal reactivity with the silicate glasses being formed. The metal alloy of the float medium is exothermic with a solvent metal that does not readily form an oxide. The vapor pressure of both components in the alloy is low enough to prevent deleterious vapor deposition, and there is minimal chemical and interdiffusive interaction of either component with silicate glasses under the float processing conditions. Alloys having the desired combination of properties include compositions in which gold, silver or copper is the solvent metal and silicon, germanium or tin is the solute, preferably in eutectic or near-eutectic compositions.

A Programmable and Configurable Mixed-Mode FPAA SoC

DTIC Science & Technology

2016-03-17

A Programmable and Configurable Mixed-Mode FPAA SoC Sahil Shah, Sihwan Kim, Farhan Adil, Jennifer Hasler, Suma George, Michelle Collins, Richard...Abstract: The authors present a Floating-Gate based, System-On-Chip large-scale Field- Programmable Analog Array IC that integrates divergent concepts...Floating-Gate, SoC, Command Word Classification This paper presents a Floating-Gate (FG) based, System- On-Chip (SoC) large-scale Field- Programmable

WindWaveFloat (WWF): Final Scientific Report

DOE Office of Scientific and Technical Information (OSTI.GOV)

Alla Weinstein; Roddier, Dominique; Banister, Kevin

2012-03-30

Principle Power Inc. and National Renewable Energy Lab (NREL) have completed a contract to assess the technical and economic feasibility of integrating wave energy converters into the WindFloat, resulting in a new concept called the WindWaveFloat (WWF). The concentration of several devices on one platform could offer a potential for both economic and operational advantages. Wind and wave energy converters can share the electrical cable and power transfer equipment to transport the electricity to shore. Access to multiple generation devices could be simplified, resulting in cost saving at the operational level. Overall capital costs may also be reduced, provided thatmore » the design of the foundation can be adapted to multiple devices with minimum modifications. Finally, the WindWaveFloat confers the ability to increase energy production from individual floating support structures, potentially leading to a reduction in levelized energy costs, an increase in the overall capacity factor, and greater stability of the electrical power delivered to the grid. The research conducted under this grant investigated the integration of several wave energy device types into the WindFloat platform. Several of the resulting system designs demonstrated technical feasibility, but the size and design constraints of the wave energy converters (technical and economic) make the WindWaveFloat concept economically unfeasible at this time. Not enough additional generation could be produced to make the additional expense associated with wave energy conversion integration into the WindFloat worthwhile.« less

Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

NASA Astrophysics Data System (ADS)

Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

2018-04-01

Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

NASA Astrophysics Data System (ADS)

Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

2018-04-01

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

40 CFR 65.44 - External floating roof (EFR).

Code of Federal Regulations, 2013 CFR

2013-07-01

... external floating roof except for automatic bleeder vents (vacuum breaker vents) and rim space vents does... floating roof shall meet the following specifications: (i) Except for automatic bleeder vents (vacuum breaker vents) and rim space vents, each opening in the noncontact external floating roof shall provide a...

40 CFR 65.44 - External floating roof (EFR).

Code of Federal Regulations, 2014 CFR

2014-07-01

... external floating roof except for automatic bleeder vents (vacuum breaker vents) and rim space vents does... floating roof shall meet the following specifications: (i) Except for automatic bleeder vents (vacuum breaker vents) and rim space vents, each opening in the noncontact external floating roof shall provide a...

40 CFR 65.44 - External floating roof (EFR).

Code of Federal Regulations, 2012 CFR

2012-07-01

... external floating roof except for automatic bleeder vents (vacuum breaker vents) and rim space vents does... floating roof shall meet the following specifications: (i) Except for automatic bleeder vents (vacuum breaker vents) and rim space vents, each opening in the noncontact external floating roof shall provide a...

Floating plant dominance as a stable state

PubMed Central

Scheffer, Marten; Szabó, Sándor; Gragnani, Alessandra; van Nes, Egbert H.; Rinaldi, Sergio; Kautsky, Nils; Norberg, Jon; Roijackers, Rudi M. M.; Franken, Rob J. M.

2003-01-01

Invasion by mats of free-floating plants is among the most important threats to the functioning and biodiversity of freshwater ecosystems ranging from temperate ponds and ditches to tropical lakes. Dark, anoxic conditions under thick floating-plant cover leave little opportunity for animal or plant life, and they can have large negative impacts on fisheries and navigation in tropical lakes. Here, we demonstrate that floating-plant dominance can be a self-stabilizing ecosystem state, which may explain its notorious persistence in many situations. Our results, based on experiments, field data, and models, represent evidence for alternative domains of attraction in ecosystems. An implication of our findings is that nutrient enrichment reduces the resilience of freshwater systems against a shift to floating-plant dominance. On the other hand, our results also suggest that a single drastic harvest of floating plants can induce a permanent shift to an alternative state dominated by rooted, submerged growth forms. PMID:12634429

Ultraclean single, double, and triple carbon nanotube quantum dots with recessed Re bottom gates

NASA Astrophysics Data System (ADS)

Jung, Minkyung; Schindele, Jens; Nau, Stefan; Weiss, Markus; Baumgartner, Andreas; Schoenenberger, Christian

2014-03-01

Ultraclean carbon nanotubes (CNTs) that are free from disorder provide a promising platform to manipulate single electron or hole spins for quantum information. Here, we demonstrate that ultraclean single, double, and triple quantum dots (QDs) can be formed reliably in a CNT by a straightforward fabrication technique. The QDs are electrostatically defined in the CNT by closely spaced metallic bottom gates deposited in trenches in Silicon dioxide by sputter deposition of Re. The carbon nanotubes are then grown by chemical vapor deposition (CVD) across the trenches and contacted using conventional electron beam lithography. The devices exhibit reproducibly the characteristics of ultraclean QDs behavior even after the subsequent electron beam lithography and chemical processing steps. We demonstrate the high quality using CNT devices with two narrow bottom gates and one global back gate. Tunable by the gate voltages, the device can be operated in four different regimes: i) fully p-type with ballistic transport between the outermost contacts (over a length of 700 nm), ii) clean n-type single QD behavior where a QD can be induced by either the left or the right bottom gate, iii) n-type double QD and iv) triple bipolar QD where the middle QD has opposite doping (p-type). Research at Basel is supported by the NCCR-Nano, NCCR-QIST, ERC project QUEST, and FP7 project SE2ND.

100-nm gate lithography for double-gate transistors

NASA Astrophysics Data System (ADS)

Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

2001-09-01

The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

40 CFR 65.44 - External floating roof (EFR).

Code of Federal Regulations, 2010 CFR

2010-07-01

... design requirements. The owner or operator who elects to control storage vessel regulated material emissions by using an external floating roof shall comply with the design requirements listed in paragraphs (a)(1) through (3) of this section. (1) The external floating roof shall be designed to float on the...

40 CFR 65.44 - External floating roof (EFR).

Code of Federal Regulations, 2011 CFR

2011-07-01

... design requirements. The owner or operator who elects to control storage vessel regulated material emissions by using an external floating roof shall comply with the design requirements listed in paragraphs (a)(1) through (3) of this section. (1) The external floating roof shall be designed to float on the...

Materials and methods for the preparation of nanocomposites

DOEpatents

Nag, Angshuman; Talapin, Dmitri V.

2018-01-30

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a method for making the same in a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, phase change layers, and sensor devices.

Logic-Gate Functions in Chemomechanical Materials.

PubMed

Schneider, Hans-Jörg

2017-09-06

Chemomechanical polymers that change their shape or volume on stimulation by multiple external chemical signals, particularly on the basis of selective molecular recognition, are discussed. Several examples illustrate how such materials, usually in the form of hydrogels, can be used for the design of chemically triggered valves or artificial muscles and applied, for example, in self-healing materials or drug delivery. The most attractive feature of such materials is that they can combine sensor and actuator within single units, from nano- to macrosize. Simultaneous action of a cofactor allows selective response in the sense of AND logic gates by, for example, amino acids and peptides, which without the presence of a second effector do not induce any changes. © 2017 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim.

Novelty modulates human striatal activation and prefrontal-striatal effective connectivity during working memory encoding.

PubMed

Geiger, Lena S; Moessnang, Carolin; Schäfer, Axel; Zang, Zhenxiang; Zangl, Maria; Cao, Hengyi; van Raalten, Tamar R; Meyer-Lindenberg, Andreas; Tost, Heike

2018-05-11

The functional role of the basal ganglia (BG) in the gating of suitable motor responses to the cortex is well established. Growing evidence supports an analogous role of the BG during working memory encoding, a task phase in which the "input-gating" of relevant materials (or filtering of irrelevant information) is an important mechanism supporting cognitive capacity and the updating of working memory buffers. One important aspect of stimulus relevance is the novelty of working memory items, a quality that is understudied with respect to its effects on corticostriatal function and connectivity. To this end, we used functional magnetic resonance imaging (fMRI) in 74 healthy volunteers performing an established Sternberg working memory task with different task phases (encoding vs. retrieval) and degrees of stimulus familiarity (novel vs. previously trained). Activation analyses demonstrated a highly significant engagement of the anterior striatum, in particular during the encoding of novel working memory items. Dynamic causal modeling (DCM) of corticostriatal circuit connectivity identified a selective positive modulatory influence of novelty encoding on the connection from the dorsolateral prefrontal cortex (DLPFC) to the anterior striatum. These data extend prior research by further underscoring the relevance of the BG for human cognitive function and provide a mechanistic account of the DLPFC as a plausible top-down regulatory element of striatal function that may facilitate the "input-gating" of novel working memory materials.

Memory-Based Structured Application Specific Integrated Circuit (ASIC) Study

DTIC Science & Technology

2008-10-01

memory interface, arbiter/ schedulers for rescheduling the memory requests according to some schedule policy, and memory channels for communicating...between the power-savings and the wakeup overhead with respect to both wakeup power and wakeup delay. For example, dream mode can save 50% more static...power than sleep mode, but at the expense of twice the wake delay and three times the wakeup energy. The user can specify power-gating modes for various components.

A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA.

PubMed

Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool

2017-12-01

Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.

A Decoherence-Free Quantum Memory Using Trapped Ions

DTIC Science & Technology

2016-09-22

superpo- sitions. Robust quantum memories are there- fore essential to realizing the potential gains of quantum computing (3). However, inter- action of a...tolerant quantum logic (13, 14). These properties suggest that DFSs will be intrinsic to future quantum computing architectures. Logic gates on DFS...practi- cal quantum computing will in any case re- quire logic gates of a much higher fidelity than those used in this work. We therefore expect that, once

Multi-bit dark state memory: Double quantum dot as an electronic quantum memory

NASA Astrophysics Data System (ADS)

Aharon, Eran; Pozner, Roni; Lifshitz, Efrat; Peskin, Uri

2016-12-01

Quantum dot clusters enable the creation of dark states which preserve electrons or holes in a coherent superposition of dot states for a long time. Various quantum logic devices can be envisioned to arise from the possibility of storing such trapped particles for future release on demand. In this work, we consider a double quantum dot memory device, which enables the preservation of a coherent state to be released as multiple classical bits. Our unique device architecture uses an external gating for storing (writing) the coherent state and for retrieving (reading) the classical bits, in addition to exploiting an internal gating effect for the preservation of the coherent state.

Core-Shell Zn x Cd1- x Se/Zn y Cd1- y Se Quantum Dots for Nonvolatile Memory and Electroluminescent Device Applications

NASA Astrophysics Data System (ADS)

Al-Amoody, Fuad; Suarez, Ernesto; Rodriguez, Angel; Heller, E.; Huang, Wenli; Jain, F.

2011-08-01

This paper presents a floating quantum dot (QD) gate nonvolatile memory device using high-energy-gap Zn y Cd1- y Se-cladded Zn x Cd1- x Se quantum dots ( y > x) with tunneling layers comprising nearly lattice-matched semiconductors (e.g., ZnS/ZnMgS) on Si channels. Also presented is the fabrication of an electroluminescent (EL) device with embedded cladded ZnCdSe quantum dots. These ZnCdSe quantum dots were embedded between indium tin oxide (ITO) on glass and a top Schottky metal electrode deposited on a thin CsF barrier. These QDs, which were nucleated in a photo-assisted microwave plasma (PMP) metalorganic chemical vapor deposition (MOCVD) reactor, were grown between the source and drain regions on a p-type silicon substrate of the nonvolatile memory device. The composition of QD cladding, which relates to the value of y in Zn y Cd1- y Se, was engineered by the intensity of ultraviolet light, which controlled the incorporation of zinc in ZnCdSe. The QD quality is comparable to those deposited by other methods. Characteristics and modeling of the II-VI quantum dots as well as two diverse types of devices are presented in this paper.

Silver nano particles ameliorate learning and spatial memory of male Wistar rats by prevention of amyloid fibril-induced neurotoxicity.

PubMed

Ramshini, H; Moghaddasi, A-S; Aldaghi, L-S; Mollania, N; Ebrahim-Habibi, A

2017-12-08

Alzheimer's disease (AD) is a chronic degenerative disease characterized by the presence of amyloid plaques and neurofibrillary tangles (NFTs), which results into memory and learning impairments. In the present study, we showed that the aggregates formed by a protein that has no link with Alzheimer's disease, namely the hen egg white lysozyme (HEWL), were cytotoxic and decreased spatial learning and memory in rats. The effect of Ag-nano particles (Ag-NPs) was investigated on disruption of amyloid aggregation and preservation of cognitive behavior of rats. Twenty-four male Wistar rats were divided into 4 groups including a control group, and injected with either scopolamine, lysozyme or aggregates pre-incubated with Ag-NPs. Rats' behavior was monitored using Morris water maze (MWM) twenty days after injections. HEWL aggregation in the presence and absence of the Ag-NPs was assayed by Thioflavin T binding, atomic force microscopy and cell-based cytotoxicity assay. Ag-NPs were capable to directly disrupt HEWL oligomerization and the resulting aggregates were non-toxic. We also showed that rats of the Ag-NPs group found MWM test platform in less time and with less distance traveled, in comparison with lysozyme group. Ag-NPs also increased the percentage of time elapsed and the distance swum in the target quadrant in the rat model of AD, in probe test. These observations suggest that Ag-NPs improved spatial learning and memory by inhibiting amyloid fibril-induced neurotoxicity. Furthermore, we suggest using model proteins as a valid tool to investigate the pathogenesis of Alzheimer's disease.

Floating drug delivery systems: a review.

PubMed

Arora, Shweta; Ali, Javed; Ahuja, Alka; Khar, Roop K; Baboota, Sanjula

2005-10-19

The purpose of writing this review on floating drug delivery systems (FDDS) was to compile the recent literature with special focus on the principal mechanism of floatation to achieve gastric retention. The recent developments of FDDS including the physiological and formulation variables affecting gastric retention, approaches to design single-unit and multiple-unit floating systems, and their classification and formulation aspects are covered in detail. This review also summarizes the in vitro techniques, in vivo studies to evaluate the performance and application of floating systems, and applications of these systems. These systems are useful to several problems encountered during the development of a pharmaceutical dosage form.

46 CFR 160.027-3 - Additional requirements for life floats.

Code of Federal Regulations, 2010 CFR

2010-10-01

... 46 Shipping 6 2010-10-01 2010-10-01 false Additional requirements for life floats. 160.027-3..., CONSTRUCTION, AND MATERIALS: SPECIFICATIONS AND APPROVAL LIFESAVING EQUIPMENT Life Floats for Merchant Vessels § 160.027-3 Additional requirements for life floats. (a) Each life float must have a platform designed...

46 CFR 160.027-3 - Additional requirements for life floats.

Code of Federal Regulations, 2011 CFR

2011-10-01

... 46 Shipping 6 2011-10-01 2011-10-01 false Additional requirements for life floats. 160.027-3..., CONSTRUCTION, AND MATERIALS: SPECIFICATIONS AND APPROVAL LIFESAVING EQUIPMENT Life Floats for Merchant Vessels § 160.027-3 Additional requirements for life floats. (a) Each life float must have a platform designed...

46 CFR 160.027-3 - Additional requirements for life floats.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 46 Shipping 6 2014-10-01 2014-10-01 false Additional requirements for life floats. 160.027-3..., CONSTRUCTION, AND MATERIALS: SPECIFICATIONS AND APPROVAL LIFESAVING EQUIPMENT Life Floats for Merchant Vessels § 160.027-3 Additional requirements for life floats. (a) Each life float must have a platform designed...

46 CFR 160.027-3 - Additional requirements for life floats.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 46 Shipping 6 2013-10-01 2013-10-01 false Additional requirements for life floats. 160.027-3..., CONSTRUCTION, AND MATERIALS: SPECIFICATIONS AND APPROVAL LIFESAVING EQUIPMENT Life Floats for Merchant Vessels § 160.027-3 Additional requirements for life floats. (a) Each life float must have a platform designed...

46 CFR 160.027-3 - Additional requirements for life floats.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 46 Shipping 6 2012-10-01 2012-10-01 false Additional requirements for life floats. 160.027-3..., CONSTRUCTION, AND MATERIALS: SPECIFICATIONS AND APPROVAL LIFESAVING EQUIPMENT Life Floats for Merchant Vessels § 160.027-3 Additional requirements for life floats. (a) Each life float must have a platform designed...

Future float zone development in industry

NASA Technical Reports Server (NTRS)

Sandfort, R. M.

1980-01-01

The present industrial requirements for float zone silicon are summarized. Developments desired by the industry in the future are reported. The five most significant problems faced today by the float zone crystal growth method in industry are discussed. They are economic, large diameter, resistivity uniformity, control of carbon, and swirl defects.

Nano-technology and nano-toxicology.

PubMed

Maynard, Robert L

2012-01-01

Rapid developments in nano-technology are likely to confer significant benefits on mankind. But, as with perhaps all new technologies, these benefits are likely to be accompanied by risks, perhaps by new risks. Nano-toxicology is developing in parallel with nano-technology and seeks to define the hazards and risks associated with nano-materials: only when risks have been identified they can be controlled. This article discusses the reasons for concern about the potential effects on health of exposure to nano-materials and relates these to the evidence of the effects on health of the ambient aerosol. A number of hypotheses are proposed and the dangers of adopting unsubstantiated hypotheses are stressed. Nano-toxicology presents many challenges and will need substantial financial support if it is to develop at a rate sufficient to cope with developments in nano-technology.

Nano-technology and nano-toxicology

PubMed Central

Maynard, Robert L.

2012-01-01

Rapid developments in nano-technology are likely to confer significant benefits on mankind. But, as with perhaps all new technologies, these benefits are likely to be accompanied by risks, perhaps by new risks. Nano-toxicology is developing in parallel with nano-technology and seeks to define the hazards and risks associated with nano-materials: only when risks have been identified they can be controlled. This article discusses the reasons for concern about the potential effects on health of exposure to nano-materials and relates these to the evidence of the effects on health of the ambient aerosol. A number of hypotheses are proposed and the dangers of adopting unsubstantiated hypotheses are stressed. Nano-toxicology presents many challenges and will need substantial financial support if it is to develop at a rate sufficient to cope with developments in nano-technology. PMID:22662021

Hydrodynamic and Aerodynamic Tests of Models of Floats for Single-float Seaplanes NACA Models 41-D, 41-E, 61-A, 73, and 73-A

NASA Technical Reports Server (NTRS)

Parkinson, J B; HOUSE R O

1938-01-01

Tests were made in the NACA tank and in the NACA 7 by 10 foot wind tunnel on two models of transverse step floats and three models of pointed step floats considered to be suitable for use with single float seaplanes. The object of the program was the reduction of water resistance and spray of single float seaplanes without reducing the angle of dead rise believed to be necessary for the satisfactory absorption of the shock loads. The results indicated that all the models have less resistance and spray than the model of the Mark V float and that the pointed step floats are somewhat superior to the transverse step floats in these respects. Models 41-D, 61-A, and 73 were tested by the general method over a wide range of loads and speeds. The results are presented in the form of curves and charts for use in design calculations.

Effect of nanocomposite gate-dielectric properties on pentacene microstructure and field-effect transistor characteristics.

PubMed

Lee, Wen-Hsi; Wang, Chun-Chieh

2010-02-01

In this study, the effect of surface energy and roughness of the nanocomposite gate dielectric on pentacene morphology and electrical properties of pentacene OTFT are reported. Nanoparticles TiO2 were added in the polyimide matrix to form a nanocomposite which has a significantly different surface characteristic from polyimide, leading to a discrepancy in the structural properties of pentacene growth. A growth mode of pentacene deposited on the nanocomposite is proposed to explain successfully the effect of surface properties of nanocomposite gate dielectric such as surface energy and roughness on the pentacene morphology and electrical properties of OTFT. To obtain the lower surface energy and smoother surface of nanocomposite gate dielectric that is responsible for the desired crystalline, microstructure of pentacene and electrical properties of device, a bottom contact OTFT-pentacene deposited on the double-layer nanocomposite gate dielectric consisting of top smoothing layer of the neat polyimide and bottom layer of (PI+ nano-TiO2 particles) nanocomposite has been successfully demonstrated to exhibit very promising performance including high current on to off ratio of about 6 x 10(5), threshold voltage of -10 V and moderately high filed mobility of 0.15 cm2V(-1)s(-1).

Improvements in floating point addition/subtraction operations

DOEpatents

Farmwald, P.M.

1984-02-24

Apparatus is described for decreasing the latency time associated with floating point addition and subtraction in a computer, using a novel bifurcated, pre-normalization/post-normalization approach that distinguishes between differences of floating point exponents.

Characterization of poly(vinyl acetate) based floating matrix tablets.

PubMed

Strübing, Sandra; Metz, Hendrik; Mäder, Karsten

2008-03-03

Floating Kollidon SR matrix tablets containing Propranolol HCl were developed and characterized with respect to drug release characteristics and floating strength. Kollidon SR was able to delay Propranolol HCl release efficiently. Drug release kinetics was evaluated using the Korsmeyer-Peppas model and found to be governed by Fickian diffusion. Tablet floating started immediately and continued for 24 h. It was possible to monitor the floating strength of the matrix devices using a simple experimental setup. Floating strength was related to Kollidon SR level with improved floating characteristics for samples with a high polymer/drug ratio. Swelling characteristics of the tablets were analyzed by applying the equation according to Therien-Aubin et al. The influence of the polymer content on swelling characteristics was found to be only marginal. Furthermore, the new method of benchtop MRI was introduced to study the water diffusion and swelling behaviour non-invasively and continuously.

Investigating enhanced thermoelectric performance of graphene-based nano-structures.

PubMed

Hossain, Md Sharafat; Huynh, Duc Hau; Jiang, Liming; Rahman, Sharmin; Nguyen, Phuong Duc; Al-Dirini, Feras; Hossain, Faruque; Bahk, Je-Hyeong; Skafidas, Efstratios

2018-03-08

Recently, it has been demonstrated that graphene nano-ribbons (GNRs) exhibit superior thermoelectric performance compared to graphene sheets. However, the underlying mechanism behind this enhancement has not been systematically investigated and significant opportunity remains for further enhancement of the thermoelectric performance of GNRs by optimizing their charge carrier concentration. In this work, we modulate the carrier concentration of graphene-based nano-structures using a gate voltage and investigate the resulting carrier-concentration-dependent thermoelectric parameters using the Boltzmann transport equations. We investigate the effect of energy dependent scattering time and the role of substrate-induced charge carrier fluctuation in optimizing the Seebeck coefficient and power factor. Our approach predicts the scattering mechanism and the extent of the charge carrier fluctuation in different samples and explains the enhancement of thermoelectric performance of GNR samples. Subsequently, we propose a route towards the enhancement of thermoelectric performance of graphene-based devices which can also be applied to other two-dimensional materials.

Near-Field Thermal Radiation for Solar Thermophotovoltaics and High Temperature Thermal Logic and Memory Applications

NASA Astrophysics Data System (ADS)

Elzouka, Mahmoud

This dissertation investigates Near-Field Thermal Radiation (NFTR) applied to MEMS-based concentrated solar thermophotovoltaics (STPV) energy conversion and thermal memory and logics. NFTR is the exchange of thermal radiation energy at nano/microscale; when separation between the hot and cold objects is less than dominant radiation wavelength (˜1 mum). NFTR is particularly of interest to the above applications due to its high rate of energy transfer, exceeding the blackbody limit by orders of magnitude, and its strong dependence on separation gap size, surface nano/microstructure and material properties. Concentrated STPV system converts solar radiation to electricity using heat as an intermediary through a thermally coupled absorber/emitter, which causes STPV to have one of the highest solar-to-electricity conversion efficiency limits (85.4%). Modeling of a near-field concentrated STPV microsystem is carried out to investigate the use of STPV based solid-state energy conversion as high power density MEMS power generator. Numerical results for In 0.18Ga0.82Sb PV cell illuminated with tungsten emitter showed significant enhancement in energy transfer, resulting in output power densities as high as 60 W/cm2; 30 times higher than the equivalent far-field power density. On thermal computing, this dissertation demonstrates near-field heat transfer enabled high temperature NanoThermoMechanical memory and logics. Unlike electronics, NanoThermoMechanical memory and logic devices use heat instead of electricity to record and process data; hence they can operate in harsh environments where electronics typically fail. NanoThermoMechanical devices achieve memory and thermal rectification functions through the coupling of near-field thermal radiation and thermal expansion in microstructures, resulting in nonlinear heat transfer between two temperature terminals. Numerical modeling of a conceptual NanoThermoMechanical is carried out; results include the dynamic response under

Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters

NASA Technical Reports Server (NTRS)

Krasowski, Michael J.

2011-01-01

A circuit topography is used to create usable, digital logic gates using N (negatively doped) channel junction field effect transistors (JFETs), load resistors, level shifting resistors, and supply rails whose values are based on the DC parametric distributions of these JFETs. This method has direct application to the current state-of-the-art in high-temperature (300 to 500 C and higher) silicon carbide (SiC) device production, and defines an adaptation to the logic gate described in U.S. Patent 7,688,117 in that, by removing the level shifter from the output of the gate structure described in the patent (and applying it to the input of the same gate), a source-coupled gate topography is created. This structure allows for the construction AND/OR (sum of products) arrays that use far fewer transistors and resistors than the same array as constructed from the gates described in the aforementioned patent. This plays a central role when large multiplexer constructs are necessary; for example, as in the construction of memory. This innovation moves the resistive level shifter from the output of the basic gate structure to the front as if the input is now configured as what would be the output of the preceding gate, wherein the output is the two level shifting resistors. The output of this innovation can now be realized as the lone follower transistor with its source node as the gate output. Additionally, one may leave intact the resistive level shifter on the new gate topography. A source-coupled to direct-coupled logic translator will be the result.

Floating nut retention system

NASA Technical Reports Server (NTRS)

Charles, J. F.; Theakston, H. A. (Inventor)

1980-01-01

A floating nut retention system includes a nut with a central aperture. An inner retainer plate has an opening which is fixedly aligned with the nut aperture. An outer retainer member is formed of a base plate having an opening and a surface adjacent to a surface of the inner retainer plate. The outer retainer member includes a securing mechanism for retaining the inner retainer plate adjacent to the outer retainer member. The securing mechanism enables the inner retainer plate to float with respect to the outer retainer number, while simultaneously forming a bearing surface for inner retainer plate.

Influence of different types of low substituted hydroxypropyl cellulose on tableting, disintegration, and floating behaviour of floating drug delivery systems

PubMed Central

Diós, Péter; Pernecker, Tivadar; Nagy, Sándor; Pál, Szilárd; Dévay, Attila

2014-01-01

The object of the present study is to evaluate the effect of application of low-substituted hydroxypropyl cellulose (L-HPC) 11 and B1 as excipients promoting floating in gastroretentive tablets. Directly compressed tablets were formed based on experimental design. Face-centred central composite design was applied with two factors and 3 levels, where amount of sodium alginate (X1) and L-HPC (X2) were the numerical factors. Applied types of L-HPCs and their 1:1 mixture were included in a categorical factor (X3). Studied parameters were floating lag time, floating time, floating force, swelling behaviour of tablets and dissolution of paracetamol, which was used as a model active substance. Due to their physical character, L-HPCs had different water uptake and flowability. Lower flowability and lower water uptake was observed after 60 min at L-HPC 11 compared to L-HPC B1. Shorter floating times were detected at L-HPC 11 and L-HPC mixtures with 0.5% content of sodium alginate, whereas alginate was the only significant factor. Evaluating results of drug release and swelling studies on floating tablets revealed correlation, which can serve to help to understand the mechanism of action of L-HPCs in the field development of gastroretentive dosage forms. PMID:26702261

Multi-wavelength access gate for WDM-formatted words in optical RAM row architectures

NASA Astrophysics Data System (ADS)

Fitsios, D.; Alexoudi, T.; Vagionas, C.; Miliou, A.; Kanellos, G. T.; Pleros, N.

2013-03-01

Optical RAM has emerged as a promising solution for overcoming the "Memory Wall" of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOAbased multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multiwavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bit channels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.

Floating Magnet Demonstration.

ERIC Educational Resources Information Center

Wake, Masayoshi

1990-01-01

A room-temperature demonstration of a floating magnet using a high-temperature superconductor is described. The setup and operation of the apparatus are described. The technical details of the effect are discussed. (CW)

Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide

NASA Astrophysics Data System (ADS)

Sangwan, Vinod K.; Lee, Hong-Sub; Bergeron, Hadallia; Balla, Itamar; Beck, Megan E.; Chen, Kan-Sheng; Hersam, Mark C.

2018-02-01

Memristors are two-terminal passive circuit elements that have been developed for use in non-volatile resistive random-access memory and may also be useful in neuromorphic computing. Memristors have higher endurance and faster read/write times than flash memory and can provide multi-bit data storage. However, although two-terminal memristors have demonstrated capacity for basic neural functions, synapses in the human brain outnumber neurons by more than a thousandfold, which implies that multi-terminal memristors are needed to perform complex functions such as heterosynaptic plasticity. Previous attempts to move beyond two-terminal memristors, such as the three-terminal Widrow-Hoff memristor and field-effect transistors with nanoionic gates or floating gates, did not achieve memristive switching in the transistor. Here we report the experimental realization of a multi-terminal hybrid memristor and transistor (that is, a memtransistor) using polycrystalline monolayer molybdenum disulfide (MoS2) in a scalable fabrication process. The two-dimensional MoS2 memtransistors show gate tunability in individual resistance states by four orders of magnitude, as well as large switching ratios, high cycling endurance and long-term retention of states. In addition to conventional neural learning behaviour of long-term potentiation/depression, six-terminal MoS2 memtransistors have gate-tunable heterosynaptic functionality, which is not achievable using two-terminal memristors. For example, the conductance between a pair of floating electrodes (pre- and post-synaptic neurons) is varied by a factor of about ten by applying voltage pulses to modulatory terminals. In situ scanning probe microscopy, cryogenic charge transport measurements and device modelling reveal that the bias-induced motion of MoS2 defects drives resistive switching by dynamically varying Schottky barrier heights. Overall, the seamless integration of a memristor and transistor into one multi-terminal device could

Investigation of Tank 241-AW-104 Composite Floating Layer

DOE Office of Scientific and Technical Information (OSTI.GOV)

Meznarich, H. K.; Bolling, S. D.; Lachut, J. S.

Seven grab samples and one field blank were taken from Tank 241-AW-104 (AW-104) on June 2, 2017, and received at 222-S Laboratory on June 5, 2017. A visible layer with brown solids was observed floating on the top of two surface tank waste samples (4AW-17-02 and 4AW 17 02DUP). The floating layer from both samples was collected, composited, and submitted for chemical analyses and solid phase characterization in order to understand the composition of the floating layer. Tributyl phosphate and tridecane were higher in the floating layer than in the aqueous phase. Density in the floating layer was slightly lowermore » than the mean density of all grab samples. Sodium nitrate and sodium carbonate were major components with a trace of gibbsite and very small size agglomerates were present in the solids of the floating layer. The supernate consisted of organics, soluble salt, and particulates.« less

Striatal contributions to declarative memory retrieval

PubMed Central

Scimeca, Jason M.; Badre, David

2012-01-01

Declarative memory is known to depend on the medial temporal lobe memory system. Recently, there has been renewed focus on the relationship between the basal ganglia and declarative memory, including the involvement of striatum. However, the contribution of striatum to declarative memory retrieval remains unknown. Here, we review neuroimaging and neuropsychological evidence for the involvement of the striatum in declarative memory retrieval. From this review, we propose that, along with the prefrontal cortex (PFC), the striatum primarily supports cognitive control of memory retrieval. We conclude by proposing three hypotheses for the specific role of striatum in retrieval: (1) Striatum modulates the re-encoding of retrieved items in accord with their expected utility (adaptive encoding), (2) striatum selectively admits information into working memory that is expected to increase the likelihood of successful retrieval (adaptive gating), and (3) striatum enacts adjustments in cognitive control based on the outcome of retrieval (reinforcement learning). PMID:22884322

A neural mechanism for background information-gated learning based on axonal-dendritic overlaps.

PubMed

Mainetti, Matteo; Ascoli, Giorgio A

2015-03-01

Experiencing certain events triggers the acquisition of new memories. Although necessary, however, actual experience is not sufficient for memory formation. One-trial learning is also gated by knowledge of appropriate background information to make sense of the experienced occurrence. Strong neurobiological evidence suggests that long-term memory storage involves formation of new synapses. On the short time scale, this form of structural plasticity requires that the axon of the pre-synaptic neuron be physically proximal to the dendrite of the post-synaptic neuron. We surmise that such "axonal-dendritic overlap" (ADO) constitutes the neural correlate of background information-gated (BIG) learning. The hypothesis is based on a fundamental neuroanatomical constraint: an axon must pass close to the dendrites that are near other neurons it contacts. The topographic organization of the mammalian cortex ensures that nearby neurons encode related information. Using neural network simulations, we demonstrate that ADO is a suitable mechanism for BIG learning. We model knowledge as associations between terms, concepts or indivisible units of thought via directed graphs. The simplest instantiation encodes each concept by single neurons. Results are then generalized to cell assemblies. The proposed mechanism results in learning real associations better than spurious co-occurrences, providing definitive cognitive advantages.

A Neural Mechanism for Background Information-Gated Learning Based on Axonal-Dendritic Overlaps

PubMed Central

Mainetti, Matteo; Ascoli, Giorgio A.

2015-01-01

Experiencing certain events triggers the acquisition of new memories. Although necessary, however, actual experience is not sufficient for memory formation. One-trial learning is also gated by knowledge of appropriate background information to make sense of the experienced occurrence. Strong neurobiological evidence suggests that long-term memory storage involves formation of new synapses. On the short time scale, this form of structural plasticity requires that the axon of the pre-synaptic neuron be physically proximal to the dendrite of the post-synaptic neuron. We surmise that such “axonal-dendritic overlap” (ADO) constitutes the neural correlate of background information-gated (BIG) learning. The hypothesis is based on a fundamental neuroanatomical constraint: an axon must pass close to the dendrites that are near other neurons it contacts. The topographic organization of the mammalian cortex ensures that nearby neurons encode related information. Using neural network simulations, we demonstrate that ADO is a suitable mechanism for BIG learning. We model knowledge as associations between terms, concepts or indivisible units of thought via directed graphs. The simplest instantiation encodes each concept by single neurons. Results are then generalized to cell assemblies. The proposed mechanism results in learning real associations better than spurious co-occurrences, providing definitive cognitive advantages. PMID:25767887

Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

PubMed

Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

2016-07-26

A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

Optimization of a PCRAM Chip for high-speed read and highly reliable reset operations

NASA Astrophysics Data System (ADS)

Li, Xiaoyun; Chen, Houpeng; Li, Xi; Wang, Qian; Fan, Xi; Hu, Jiajun; Lei, Yu; Zhang, Qi; Tian, Zhen; Song, Zhitang

2016-10-01

The widely used traditional Flash memory suffers from its performance limits such as its serious crosstalk problems, and increasing complexity of floating gate scaling. Phase change random access memory (PCRAM) becomes one of the most potential nonvolatile memories among the new memory techniques. In this paper, a 1M-bit PCRAM chip is designed based on the SMIC 40nm CMOS technology. Focusing on the read and write performance, two new circuits with high-speed read operation and highly reliable reset operation are proposed. The high-speed read circuit effectively reduces the reading time from 74ns to 40ns. The double-mode reset circuit improves the chip yield. This 1M-bit PCRAM chip has been simulated on cadence. After layout design is completed, the chip will be taped out for post-test.

Wide memory window in graphene oxide charge storage nodes

NASA Astrophysics Data System (ADS)

Wang, Shuai; Pu, Jing; Chan, Daniel S. H.; Cho, Byung Jin; Loh, Kian Ping

2010-04-01

Solution-processable, isolated graphene oxide (GO) monolayers have been used as a charge trapping dielectric in TaN gate/Al2O3/isolated GO sheets/SiO2/p-Si memory device (TANOS). The TANOS type structure serves as memory device with the threshold voltage controlled by the amount of charge trapped in the GO sheet. Capacitance-Voltage hysteresis curves reveal a 7.5 V memory window using the sweep voltage of -5-14 V. Thermal reduction in the GO to graphene reduces the memory window to 1.4 V. The unique charge trapping properties of GO points to the potential applications in flexible organic memory devices.

14 CFR 29.757 - Hull and auxiliary float strength.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 14 Aeronautics and Space 1 2011-01-01 2011-01-01 false Hull and auxiliary float strength. 29.757 Section 29.757 Aeronautics and Space FEDERAL AVIATION ADMINISTRATION, DEPARTMENT OF TRANSPORTATION... § 29.757 Hull and auxiliary float strength. The hull, and auxiliary floats if used, must withstand the...

Nanophotonic photon echo memory based on rare-earth-doped crystals

NASA Astrophysics Data System (ADS)

Zhong, Tian; Kindem, Jonathan; Miyazono, Evan; Faraon, Andrei; Caltech nano quantum optics Team

2015-03-01

Rare earth ions (REIs) are promising candidates for implementing solid-state quantum memories and quantum repeater devices. Their high spectral stability and long coherence times make REIs a good choice for integration in an on-chip quantum nano-photonic platform. We report the coupling of the 883 nm transition of Neodymium (Nd) to a Yttrium orthosilicate (YSO) photonic crystal nano-beam resonator, achieving Purcell enhanced spontaneous emission by 21 times and increased optical absorption. Photon echoes were observed in nano-beams of different doping concentrations, yielding optical coherence times T2 up to 80 μs that are comparable to unprocessed bulk samples. This indicates the remarkable coherence properties of Nd are preserved during nanofabrication, therefore opening the possibility of efficient on-chip optical quantum memories. The nano-resonator with mode volume of 1 . 6(λ / n) 3 was fabricated using focused ion beam, and a quality factor of 3200 was measured. Purcell enhanced absorption of 80% by an ensemble of ~ 1 × 106 ions in the resonator was measured, which fulfills the cavity impedance matching condition that is necessary to achieve quantum storage of photons with unity efficiency.

Improved memory characteristics by NH3-nitrided GdO as charge storage layer for nonvolatile memory applications

NASA Astrophysics Data System (ADS)

Liu, L.; Xu, J. P.; Ji, F.; Chen, J. X.; Lai, P. T.

2012-07-01

Charge-trapping memory capacitor with nitrided gadolinium oxide (GdO) as charge storage layer (CSL) is fabricated, and the influence of post-deposition annealing in NH3 on its memory characteristics is investigated. Transmission electron microscopy, x-ray photoelectron spectroscopy, and x-ray diffraction are used to analyze the cross-section and interface quality, composition, and crystallinity of the stack gate dielectric, respectively. It is found that nitrogen incorporation can improve the memory window and achieve a good trade-off among the memory properties due to NH3-annealing-induced reasonable distribution profile of a large quantity of deep-level bulk traps created in the nitrided GdO film and reduction of shallow traps near the CSL/SiO2 interface.

Control of Turing patterns and their usage as sensors, memory arrays, and logic gates

NASA Astrophysics Data System (ADS)

Muzika, František; Schreiber, Igor

2013-10-01

We study a model system of three diffusively coupled reaction cells arranged in a linear array that display Turing patterns with special focus on the case of equal coupling strength for all components. As a suitable model reaction we consider a two-variable core model of glycolysis. Using numerical continuation and bifurcation techniques we analyze the dependence of the system's steady states on varying rate coefficient of the recycling step while the coupling coefficients of the inhibitor and activator are fixed and set at the ratios 100:1, 1:1, and 4:5. We show that stable Turing patterns occur at all three ratios but, as expected, spontaneous transition from the spatially uniform steady state to the spatially nonuniform Turing patterns occurs only in the first case. The other two cases possess multiple Turing patterns, which are stabilized by secondary bifurcations and coexist with stable uniform periodic oscillations. For the 1:1 ratio we examine modular spatiotemporal perturbations, which allow for controllable switching between the uniform oscillations and various Turing patterns. Such modular perturbations are then used to construct chemical computing devices utilizing the multiple Turing patterns. By classifying various responses we propose: (a) a single-input resettable sensor capable of reading certain value of concentration, (b) two-input and three-input memory arrays capable of storing logic information, (c) three-input, three-output logic gates performing combinations of logical functions OR, XOR, AND, and NAND.

Air-Deployable Profiling Floats for Tropical Cyclone Research

NASA Astrophysics Data System (ADS)

Jayne, S. R.; Robbins, P.; Owens, B.; Ekholm, A.; Dufour, J. E.; Sanabia, E.

2016-02-01

The development of a smaller profiling float that can be launched from Hurricane Hunter aircraft offers the opportunity to monitor the upper-ocean thermal structure over a time span of many months. These Argo-type profiling floats can be deployed in advance of, or during, a tropical cyclone from any aircraft equipped with an A-sized (AXBT) launch tube, or from the stern ramp of a C-130. The floats have the same dimensions as an AXBT and weigh about 8.5 kg. Upon deployment, the floats parachute to the surface, detach and automatically begin their programmed mission. The recorded temperature data is averaged over 1-meter bins that are reported back via the Iridium satellite phone network, which is then automatically processed and posted to the GTS. The floats are also reprogrammable via the 2-way communication afforded by Iridium. We report on the results of deployments during the 2014 and 2015 hurricane seasons. Unique observations of the ocean response from Hurricane Ignacio are particularly noteworthy and will be presented. Further plans for continued development of floats include measuring salinity (from an inductive conductivity sensor) and observations of the surface wave field (measured by an onboard accelerometer) will also be described.

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

NASA Technical Reports Server (NTRS)

Pang, Jackson; Pingree, Paula J.; Torgerson, J. Leigh

2006-01-01

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

33 CFR 144.01-15 - Alternates for life floats.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Alternates for life floats. 144... for life floats. (a) Approved lifeboats, approved life rafts or approved inflatable life rafts may be used in lieu of approved life floats for either all or part of the capacity required. When either...

33 CFR 144.01-15 - Alternates for life floats.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 33 Navigation and Navigable Waters 2 2011-07-01 2011-07-01 false Alternates for life floats. 144... for life floats. (a) Approved lifeboats, approved life rafts or approved inflatable life rafts may be used in lieu of approved life floats for either all or part of the capacity required. When either...

An Analysis of the Full-Floating Journal Bearing

NASA Technical Reports Server (NTRS)

Shaw, M C; Nussdorfer, T J , Jr

1947-01-01

An analysis of the operating characteristics of a full-floating journal bearing, a bearing in which a floating sleeve is located between the journal and bearing surfaces, is presented together with charts from which the performance of such bearings may be predicted. Examples are presented to illustrate the use of these charts and a limited number of experiments conducted upon a glass full-floating bearing are reported to verify some results of the analysis.

A novel optical gating method for laser gated imaging

NASA Astrophysics Data System (ADS)

Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

2013-06-01

For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride-trifluoroethylene gate insulator

NASA Astrophysics Data System (ADS)

Karaya, Ryota; Baba, Ikki; Mori, Yosuke; Matsumoto, Tsubasa; Nakajima, Takashi; Tokuda, Norio; Kawae, Takeshi

2017-10-01

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride-trifluoroethylene (VDF-TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF-TrFE/B-doped diamond layered structure showed ideal behavior as a metal-ferroelectric-semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to -20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF-TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.

Dangling-bond logic gates on a Si(100)-(2 × 1)-H surface.

PubMed

Kawai, Hiroyo; Ample, Francisco; Wang, Qing; Yeo, Yong Kiat; Saeys, Mark; Joachim, Christian

2012-03-07

Atomic-scale Boolean logic gates (LGs) with two inputs and one output (i.e. OR, NOR, AND, NAND) were designed on a Si(100)-(2 × 1)-H surface and connected to the macroscopic scale by metallic nano-pads physisorbed on the Si(100)-(2 × 1)-H surface. The logic inputs are provided by saturating and unsaturating two surface Si dangling bonds, which can, for example, be achieved by adding and extracting two hydrogen atoms per input. Quantum circuit design rules together with semi-empirical elastic-scattering quantum chemistry transport calculations were used to determine the output current intensity of the proposed switches and LGs when they are interconnected to the metallic nano-pads by surface atomic-scale wires. Our calculations demonstrate that the proposed devices can reach ON/OFF ratios of up to 2000 for a running current in the 10 µA range.

46 CFR 131.870 - Life floats and buoyant apparatus.

Code of Federal Regulations, 2012 CFR

2012-10-01

... 46 Shipping 4 2012-10-01 2012-10-01 false Life floats and buoyant apparatus. 131.870 Section 131... OPERATIONS Markings for Fire Equipment and Emergency Equipment § 131.870 Life floats and buoyant apparatus. (a) The name of the vessel must be plainly marked or painted on each life float or buoyant apparatus...

46 CFR 131.870 - Life floats and buoyant apparatus.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 46 Shipping 4 2013-10-01 2013-10-01 false Life floats and buoyant apparatus. 131.870 Section 131... OPERATIONS Markings for Fire Equipment and Emergency Equipment § 131.870 Life floats and buoyant apparatus. (a) The name of the vessel must be plainly marked or painted on each life float or buoyant apparatus...

46 CFR 131.870 - Life floats and buoyant apparatus.

Code of Federal Regulations, 2014 CFR

2014-10-01

... 46 Shipping 4 2014-10-01 2014-10-01 false Life floats and buoyant apparatus. 131.870 Section 131... OPERATIONS Markings for Fire Equipment and Emergency Equipment § 131.870 Life floats and buoyant apparatus. (a) The name of the vessel must be plainly marked or painted on each life float or buoyant apparatus...

46 CFR 131.870 - Life floats and buoyant apparatus.

Code of Federal Regulations, 2011 CFR

2011-10-01

... OPERATIONS Markings for Fire Equipment and Emergency Equipment § 131.870 Life floats and buoyant apparatus. (a) The name of the vessel must be plainly marked or painted on each life float or buoyant apparatus... 46 Shipping 4 2011-10-01 2011-10-01 false Life floats and buoyant apparatus. 131.870 Section 131...

46 CFR 131.870 - Life floats and buoyant apparatus.

Code of Federal Regulations, 2010 CFR

2010-10-01

... OPERATIONS Markings for Fire Equipment and Emergency Equipment § 131.870 Life floats and buoyant apparatus. (a) The name of the vessel must be plainly marked or painted on each life float or buoyant apparatus... 46 Shipping 4 2010-10-01 2010-10-01 false Life floats and buoyant apparatus. 131.870 Section 131...

Potential of water surface-floating microalgae for biodiesel production: Floating-biomass and lipid productivities.

PubMed

Muto, Masaki; Nojima, Daisuke; Yue, Liang; Kanehara, Hideyuki; Naruse, Hideaki; Ujiro, Asuka; Yoshino, Tomoko; Matsunaga, Tadashi; Tanaka, Tsuyoshi

2017-03-01

Microalgae have been accepted as a promising feedstock for biodiesel production owing to their capability of converting solar energy into lipids through photosynthesis. However, the high capital and operating costs, and high energy consumption, are hampering commercialization of microalgal biodiesel. In this study, the surface-floating microalga, strain AVFF007 (tentatively identified as Botryosphaerella sudetica), which naturally forms a biofilm on surfaces, was characterized for use in biodiesel production. The biofilm could be conveniently harvested from the surface of the water by adsorbing onto a polyethylene film. The lipid productivity of strain AVFF007 was 46.3 mg/L/day, allowing direct comparison to lipid productivities of other microalgal species. The moisture content of the surface-floating biomass was 86.0 ± 1.2%, which was much lower than that of the biomass harvested using centrifugation. These results reveal the potential of this surface-floating microalgal species as a biodiesel producer, employing a novel biomass harvesting and dewatering strategy. Copyright © 2016 The Society for Biotechnology, Japan. Published by Elsevier B.V. All rights reserved.

Floating seal system for rotary devices

DOEpatents

Banasiuk, Hubert A.

1983-01-01

This invention relates to a floating seal system for rotary devices to reduce gas leakage around the rotary device in a duct and across the face of the rotary device to an adjacent duct. The peripheral seal bodies are made of resilient material having a generally U-shaped cross section wherein one of the legs is secured to a support member and the other of the legs forms a contacting seal against the rotary device. The legs of the peripheral seal form an extended angle of intersection of about 10.degree. to about 30.degree. in the unloaded condition to provide even sealing forces around the periphery of the rotary device. The peripheral seal extends around the periphery of the support member except where intersected by radial seals which reduce gas leakage across the face of the rotary device and between adjacent duct portions. The radial seal assembly is fabricated from channel bars, the smaller channel bar being secured to the divider of the support member and a larger inverted rigid floating channel bar having its legs freely movable over the legs of the smaller channel bar forming therewith a tubular channel. A resilient flexible tube is positioned within the tubular channel for substantially its full length to reduce gas leakage across the tubular channel. A spacer extends beyond the face of the floating channel near each end of the floating channel a distance to provide desired clearance between the floating channel and the face of the rotary device.

Floating seal system for rotary devices

DOEpatents

Banasiuk, H.A.

1983-08-23

This invention relates to a floating seal system for rotary devices to reduce gas leakage around the rotary device in a duct and across the face of the rotary device to an adjacent duct. The peripheral seal bodies are made of resilient material having a generally U-shaped cross section wherein one of the legs is secured to a support member and the other of the legs forms a contacting seal against the rotary device. The legs of the peripheral seal form an extended angle of intersection of about 10[degree] to about 30[degree] in the unloaded condition to provide even sealing forces around the periphery of the rotary device. The peripheral seal extends around the periphery of the support member except where intersected by radial seals which reduce gas leakage across the face of the rotary device and between adjacent duct portions. The radial seal assembly is fabricated from channel bars, the smaller channel bar being secured to the divider of the support member and a larger inverted rigid floating channel bar having its legs freely movable over the legs of the smaller channel bar forming therewith a tubular channel. A resilient flexible tube is positioned within the tubular channel for substantially its full length to reduce gas leakage across the tubular channel. A spacer extends beyond the face of the floating channel near each end of the floating channel a distance to provide desired clearance between the floating channel and the face of the rotary device. 5 figs.

33 CFR 144.01-10 - Equipment for life floats.

Code of Federal Regulations, 2010 CFR

2010-07-01

... 33 Navigation and Navigable Waters 2 2010-07-01 2010-07-01 false Equipment for life floats. 144.01... for life floats. (a) Each lifefloat shall be provided with a painter. This painter shall be a manila... 1/2 inch in diameter. (b) Each life float must have a water light of an approved automatic electric...

33 CFR 144.01-10 - Equipment for life floats.

Code of Federal Regulations, 2011 CFR

2011-07-01

... 33 Navigation and Navigable Waters 2 2011-07-01 2011-07-01 false Equipment for life floats. 144.01... for life floats. (a) Each lifefloat shall be provided with a painter. This painter shall be a manila... 1/2 inch in diameter. (b) Each life float must have a water light of an approved automatic electric...

33 CFR 144.01-10 - Equipment for life floats.

Code of Federal Regulations, 2014 CFR

2014-07-01

... 33 Navigation and Navigable Waters 2 2014-07-01 2014-07-01 false Equipment for life floats. 144.01... for life floats. (a) Each lifefloat shall be provided with a painter. This painter shall be a manila... 1/2 inch in diameter. (b) Each life float must have a water light of an approved automatic electric...

33 CFR 144.01-10 - Equipment for life floats.

Code of Federal Regulations, 2013 CFR

2013-07-01

... 33 Navigation and Navigable Waters 2 2013-07-01 2013-07-01 false Equipment for life floats. 144.01... for life floats. (a) Each lifefloat shall be provided with a painter. This painter shall be a manila... 1/2 inch in diameter. (b) Each life float must have a water light of an approved automatic electric...

33 CFR 144.01-10 - Equipment for life floats.

Code of Federal Regulations, 2012 CFR

2012-07-01

... 33 Navigation and Navigable Waters 2 2012-07-01 2012-07-01 false Equipment for life floats. 144.01... for life floats. (a) Each lifefloat shall be provided with a painter. This painter shall be a manila... 1/2 inch in diameter. (b) Each life float must have a water light of an approved automatic electric...

Research on stability of nozzle-floating plate institution

NASA Astrophysics Data System (ADS)

Huang, Bin; Tao, Jiayue; Yi, Jiajing; Chen, Shijing

2016-01-01

In this paper, air hammer instability of nozzle-floating plate institution in gas lubricated force sensor were studied. Through establishment of the theoretical model for the analysis of the nozzle-floating plate institution stability, combined with air hammer stability judgment theorems, we had some simulation research on the radius of the nozzle, the radius of the pressure chamber, pressure chamber depth, orifice radius and the relationship between air supply pressure and bearing capacity, in order to explore the instability mechanism of nozzle-floating plate institution. For conducting experimental observations for the stability of two groups nozzle-floating plate institution, which have typical structural parameters conducted experimental observations. We set up a special experimental device, verify the correctness of the theoretical study and simulation results. This paper shows that in the nozzle-floating plate institution, increasing the nozzle diameter, reduced pressure chamber radius, reducing the depth of the pressure chamber and increase the supply orifice radius, and other measures is conducive to system stability. Results of this study have important implications for research and design of gas lubricated force sensor.

Environment parameters and basic functions for floating-point computation

NASA Technical Reports Server (NTRS)

Brown, W. S.; Feldman, S. I.

1978-01-01

A language-independent proposal for environment parameters and basic functions for floating-point computation is presented. Basic functions are proposed to analyze, synthesize, and scale floating-point numbers. The model provides a small set of parameters and a small set of axioms along with sharp measures of roundoff error. The parameters and functions can be used to write portable and robust codes that deal intimately with the floating-point representation. Subject to underflow and overflow constraints, a number can be scaled by a power of the floating-point radix inexpensively and without loss of precision. A specific representation for FORTRAN is included.

A Content-Addressable Memory structure using quantum cells in nanotechnology with energy dissipation analysis

NASA Astrophysics Data System (ADS)

Sadoghifar, Ali; Heikalabad, Saeed Rasouli

2018-05-01

Quantum-dot cellular automata is one of the recent new technologies at the nanoscale that can be a suitable replacement for CMOS technology. The circuits constructed in QCA technology have desirable features such as low power consumption, high speed and small size. These features can be more distinct in memory structures. In this paper, we design a new structure for content addressable memory cell in QCA. For this purpose, first, a unique gate is introduced for mask operation in QCA and then this gate is used to improve the performance of CAM. These structures are evaluated with QCADesigner simulator.

Materials and methods for the preparation of nanocomposites

DOEpatents

Talapin, Dmitri V.; Kovalenko, Maksym V.; Lee, Jong-Soo; Jiang, Chengyang

2016-05-24

Disclosed herein is an isolable colloidal particle comprising a nanoparticle and an inorganic capping agent bound to the surface of the nanoparticle, a solution of the same, a method for making the same from a biphasic solvent mixture, and the formation of structures and solids from the isolable colloidal particle. The process can yield photovoltaic cells, piezoelectric crystals, thermoelectric layers, optoelectronic layers, light emitting diodes, ferroelectric layers, thin film transistors, floating gate memory devices, imaging devices, phase change layers, and sensor devices.

Floating Solar Photovoltaics Gaining Ground | State, Local, and Tribal

Science.gov Websites

Gaining Ground January 24, 2017 by Alison Holm Floating solar photovoltaic (PV) systems, so-called flotovoltaics (a trademarked term) or floating solar, represent an emerging application in which PV panels are sited on bodies of water. The PV panel technology used for floating solar applications is very similar

Electrically Erasable Programmable Integrated Circuits for Replacement of Obsolete TTL Logic

DTIC Science & Technology

1991-12-01

different discrete devices" [7]. Fowler-Nordheim Tunneling Simplified Theory. Electrons in polysilicon are usually prevented from entering SiO 2 by an...overcomes the energy barrier, the tunneling electrons will not return to the polysilicon but will be carried by the electric field, causing a current to flow...Floating Gate Transistors A floating gate transistor is an insulated-gate field effect transistor (FET) that has a gate, usually made of polysilicon , which

Optical imaging through turbid media with a degenerate four-wave mixing correlation time gate

DOEpatents

Sappey, Andrew D.

1998-04-14

Optical imaging through turbid media is demonstrated using a degenerate four-wave mixing correlation time gate. An apparatus and method for detecting ballistic and/or snake light while rejecting unwanted diffusive light for imaging structures within highly scattering media are described. Degenerate four-wave mixing (DFWM) of a doubled YAG laser in rhodamine 590 is used to provide an ultrafast correlation time gate to discriminate against light that has undergone multiple scattering and therefore has lost memory of the structures within the scattering medium. Images have been obtained of a test cross-hair pattern through highly turbid suspensions of whole milk in water that are opaque to the naked eye, which demonstrates the utility of DFWM for imaging through turbid media. Use of DFWM as an ultrafast time gate for the detection of ballistic and/or snake light in optical mammography is discussed.

Comparative evaluation of single and bilayered lamotrigine floating tablets

PubMed Central

Lakshmi, PK; Sridhar, M; Shruthi, B

2013-01-01

Aim: The purpose of this study was to prepare lamotrigine (LM) bilayered and single layered floating tablets and to compare their release profiles. Materials and Methods: LM floating tablets were prepared by direct compression method. Drug, hydroxy propyl methyl cellulose K4M, lactose monohydrate and polyvinylpyrrolidone K30 constitute controlled release layer components and floating layer components includes polymers and sodium bicarbonate. The prepared tablets were evaluated for physicochemical parameters such as hardness, friability, weight variation, thickness, floating lag time (FLT), floating time, in vitro buoyancy study, in vitro release studies. The drug-polymer interaction was studied by fourier transform infrared and differential scanning calorimetry. Results and Discussion: The FLT of all the formulations were within the prescribed limits (<3 min). When ethyl cellulose was used as floating layer component, tablets showed good buoyancy effect but eroded within 6-8 h. Hence it was replaced with hydroxypropyl cellulose -M hydrophilic polymer, which showed good FLT and floating duration for 16 h. Formulation LFC4 was found to be optimized with dissolution profile of zero order kinetics showing fickian diffusion. A comparative study of bilayered and single layered tablets of LM showed a highest similarity factor of 83.03, difference factor of 2.74 and t-test (P < 0.05) indicates that there is no significant difference between them. Conclusion: Though bilayered tablet possess many advantages, single layered tablet would be economical, cost-effective and reproducible for large scale production in the industry. However, the results of present study demonstrated that the in vitro development of bilayered gastro retentive floating tablets with controlled drug release profile for LM is feasible. PMID:24167788

Floating arterial thrombus related stroke treated by intravenous thrombolysis.

PubMed

Vanacker, P; Cordier, M; Janbieh, J; Federau, C; Michel, P

2014-01-01

The effects of intravenous thrombolysis on floating thrombi in cervical and intracranial arteries of acute ischemic stroke patients are unknown. Similarly, the best prevention methods of early recurrences remain controversial. This study aimed to describe the clinical and radiological outcome of thrombolyzed strokes with floating thrombi. We retrospectively analyzed all thrombolyzed stroke patients in our institution between 2003 and 2010 with floating thrombi on acute CT-angiography before the intravenous thrombolysis. The floating thrombus was diagnosed if an elongated thrombus of at least 5 mm length, completely surrounded by contrast on supra-aortic neck or intracerebral arteries, was present on CT-angiography. Demographics, vascular risk factors, and comorbidities were recorded and stroke etiology was determined after a standardized workup. Repeat arterial imaging was performed by CTA at 24 h or before if clinical worsening was noted and then by Doppler and MRA during the first week and at four months. Of 409 thrombolyzed stroke patients undergoing acute CT Angiography, seven (1.7%) had a floating thrombus; of these seven, six had it in the anterior circulation. Demographics, risk factors and stroke severity of these patients were comparable to the other thrombolyzed patients. After intravenous thrombolysis, the floating thrombi resolved completely at 24 h in four of the patients, whereas one had an early recurrent stroke and one developed progressive worsening. One patient developed early occlusion of the carotid artery with floating thrombus and subsequently a TIA. The two patients with a stable floating thrombus had no clinical recurrences. In the literature, only one of four reported cases were found to have a thrombolysis-related early recurrence. Long-term outcome seemed similar in thrombolyzed patients with floating thrombus, despite a possible increase of very early recurrence. It remains to be established whether acute mechanical thrombectomy could be

Growth of low temperature silicon nano-structures for electronic and electrical energy generation applications.

PubMed

Gabrielyan, Nare; Saranti, Konstantina; Manjunatha, Krishna Nama; Paul, Shashi

2013-02-15

This paper represents the lowest growth temperature for silicon nano-wires (SiNWs) via a vapour-liquid-solid method, which has ever been reported in the literature. The nano-wires were grown using plasma-enhanced chemical vapour deposition technique at temperatures as low as 150°C using gallium as the catalyst. This study investigates the structure and the size of the grown silicon nano-structure as functions of growth temperature and catalyst layer thickness. Moreover, the choice of the growth temperature determines the thickness of the catalyst layer to be used.The electrical and optical characteristics of the nano-wires were tested by incorporating them in photovoltaic solar cells, two terminal bistable memory devices and Schottky diode. With further optimisation of the growth parameters, SiNWs, grown by our method, have promising future for incorporation into high performance electronic and optical devices.

Quantum memory and gates using a Λ -type quantum emitter coupled to a chiral waveguide

NASA Astrophysics Data System (ADS)

Li, Tao; Miranowicz, Adam; Hu, Xuedong; Xia, Keyu; Nori, Franco

2018-06-01

By coupling a Λ -type quantum emitter to a chiral waveguide, in which the polarization of a photon is locked to its propagation direction, we propose a controllable photon-emitter interface for quantum networks. We show that this chiral system enables the swap gate and a hybrid-entangling gate between the emitter and a flying single photon. It also allows deterministic storage and retrieval of single-photon states with high fidelities and efficiencies. In short, this chirally coupled emitter-photon interface can be a critical building block toward a large-scale quantum network.

Dragging a floating horizontal cylinder

NASA Astrophysics Data System (ADS)

Lee, Duck-Gyu; Kim, Ho-Young

2010-11-01

A cylinder immersed in a fluid stream experiences a drag, and it is well known that the drag coefficient is a function of the Reynolds number only. Here we study the force exerted on a long horizontal cylinder that is dragged perpendicular to its axis while floating on an air-water interface with a high Reynolds number. In addition to the flow-induced drag, the floating body is subjected to capillary forces along the contact line where the three phases of liquid/solid/gas meet. We first theoretically predict the meniscus profile around the horizontally moving cylinder assuming the potential flow, and show that the profile is in good agreement with that obtained experimentally. Then we compare our theoretical predictions and experimental measurement results for the drag coefficient of a floating horizontal cylinder that is given by a function of the Weber number and the Bond number. This study can help us to understand the horizontal motion of partially submerged objects at air-liquid interface, such as semi-aquatic insects and marine plants.

Can flexibility help you float?

NASA Astrophysics Data System (ADS)

Burton, L. J.; Bush, J. W. M.

2012-10-01

We consider the role of flexibility in the weight-bearing characteristics of bodies floating at an interface. Specifically, we develop a theoretical model for a two-dimensional thin floating plate that yields the maximum stable plate load and optimal stiffness for weight support. Plates small relative to the capillary length are primarily supported by surface tension, and their weight-bearing potential does not benefit from flexibility. Above a critical size comparable to the capillary length, flexibility assists interfacial flotation. For plates on the order of and larger than the capillary length, deflection from an initially flat shape increases the force resulting from hydrostatic pressure, allowing the plate to support a greater load. In this large plate limit, the shape that bears the most weight is a semicircle, which displaces the most fluid above the plate for a fixed plate length. Exact results for maximum weight-bearing plate shapes are compared to analytic approximations made in the limits of large and small plate sizes. The value of flexibility for floating to a number of biological organisms is discussed in light of our study.

Load-Dependent Increases in Delay-Period Alpha-Band Power Track the Gating of Task-Irrelevant Inputs to Working Memory.

PubMed

Heinz, Andrew J; Johnson, Jeffrey S

2017-01-01

Studies exploring the role of neural oscillations in cognition have revealed sustained increases in alpha-band power (ABP) during the delay period of verbal and visual working memory (VWM) tasks. There have been various proposals regarding the functional significance of such increases, including the inhibition of task-irrelevant cortical areas as well as the active retention of information in VWM. The present study examines the role of delay-period ABP in mediating the effects of interference arising from on-going visual processing during a concurrent VWM task. Specifically, we reasoned that, if set-size dependent increases in ABP represent the gating out of on-going task-irrelevant visual inputs, they should be predictive with respect to some modulation in visual evoked potentials resulting from a task-irrelevant delay period probe stimulus. In order to investigate this possibility, we recorded the electroencephalogram while subjects performed a change detection task requiring the retention of two or four novel shapes. On a portion of trials, a novel, task-irrelevant bilateral checkerboard probe was presented mid-way through the delay. Analyses focused on examining correlations between set-size dependent increases in ABP and changes in the magnitude of the P1, N1 and P3a components of the probe-evoked response and how such increases might be related to behavior. Results revealed that increased delay-period ABP was associated with changes in the amplitude of the N1 and P3a event-related potential (ERP) components, and with load-dependent changes in capacity when the probe was presented during the delay. We conclude that load-dependent increases in ABP likely play a role in supporting short-term retention by gating task-irrelevant sensory inputs and suppressing potential sources of disruptive interference.

Load-Dependent Increases in Delay-Period Alpha-Band Power Track the Gating of Task-Irrelevant Inputs to Working Memory

PubMed Central

Heinz, Andrew J.; Johnson, Jeffrey S.

2017-01-01

Studies exploring the role of neural oscillations in cognition have revealed sustained increases in alpha-band power (ABP) during the delay period of verbal and visual working memory (VWM) tasks. There have been various proposals regarding the functional significance of such increases, including the inhibition of task-irrelevant cortical areas as well as the active retention of information in VWM. The present study examines the role of delay-period ABP in mediating the effects of interference arising from on-going visual processing during a concurrent VWM task. Specifically, we reasoned that, if set-size dependent increases in ABP represent the gating out of on-going task-irrelevant visual inputs, they should be predictive with respect to some modulation in visual evoked potentials resulting from a task-irrelevant delay period probe stimulus. In order to investigate this possibility, we recorded the electroencephalogram while subjects performed a change detection task requiring the retention of two or four novel shapes. On a portion of trials, a novel, task-irrelevant bilateral checkerboard probe was presented mid-way through the delay. Analyses focused on examining correlations between set-size dependent increases in ABP and changes in the magnitude of the P1, N1 and P3a components of the probe-evoked response and how such increases might be related to behavior. Results revealed that increased delay-period ABP was associated with changes in the amplitude of the N1 and P3a event-related potential (ERP) components, and with load-dependent changes in capacity when the probe was presented during the delay. We conclude that load-dependent increases in ABP likely play a role in supporting short-term retention by gating task-irrelevant sensory inputs and suppressing potential sources of disruptive interference. PMID:28555099

Vertical pump with free floating check valve

DOEpatents

Lindsay, Malcolm

1980-01-01

A vertical pump with a bottom discharge having a free floating check valve isposed in the outlet plenum thereof. The free floating check valve comprises a spherical member with a hemispherical cage-like member attached thereto which is capable of allowing forward or reverse flow under appropriate conditions while preventing reverse flow under inappropriate conditions.

Whatever Floats Your Boat: A Design Challenge

ERIC Educational Resources Information Center

Kornoelje, Joanne; Roman, Harry T.

2012-01-01

This article presents a simple design challenge, based on the PBS program "Design Squad's" "Watercraft" activity that will prove engaging to most technology and engineering students. In this floating boat challenge, students are to build a boat that can float and support 25 pennies for at least 10 seconds--without leaking, sinking, or tipping…

Gating of the designed trimeric/tetrameric voltage-gated H+ channel

PubMed Central

Fujiwara, Yuichiro; Kurokawa, Tatsuki; Takeshita, Kohei; Nakagawa, Atsushi; Larsson, H Peter; Okamura, Yasushi

2013-01-01

The voltage-gated H+ channel functions as a dimer, a configuration that is different from standard tetrameric voltage-gated channels. Each channel protomer has its own permeation pathway. The C-terminal coiled-coil domain has been shown to be necessary for both dimerization and cooperative gating in the two channel protomers. Here we report the gating cooperativity in trimeric and tetrameric Hv channels engineered by altering the hydrophobic core sequence of the coiled-coil assembly domain. Trimeric and tetrameric channels exhibited more rapid and less sigmoidal kinetics of activation of H+ permeation than dimeric channels, suggesting that some channel protomers in trimers and tetramers failed to produce gating cooperativity observed in wild-type dimers. Multimerization of trimer and tetramer channels were confirmed by the biochemical analysis of proteins, including crystallography. These findings indicate that the voltage-gated H+ channel is optimally designed as a dimeric channel on a solid foundation of the sequence pattern of the coiled-coil core, with efficient cooperative gating that ensures sustained and steep voltage-dependent H+ conductance in blood cells. PMID:23165764

Changing Patterns of the Floating Population in China during 2000-2010*

PubMed Central

Liang, Zai; Li, Zhen; Ma, Zhongdong