21 CFR 120.25 - Process verification for certain processors.

Code of Federal Regulations, 2011 CFR

2011-04-01

... 21 Food and Drugs 2 2011-04-01 2011-04-01 false Process verification for certain processors. 120.25 Section 120.25 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) FOOD FOR HUMAN CONSUMPTION HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) SYSTEMS...

21 CFR 120.25 - Process verification for certain processors.

Code of Federal Regulations, 2012 CFR

2012-04-01

... 21 Food and Drugs 2 2012-04-01 2012-04-01 false Process verification for certain processors. 120.25 Section 120.25 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) FOOD FOR HUMAN CONSUMPTION HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) SYSTEMS...

21 CFR 120.25 - Process verification for certain processors.

Code of Federal Regulations, 2014 CFR

2014-04-01

... 21 Food and Drugs 2 2014-04-01 2014-04-01 false Process verification for certain processors. 120.25 Section 120.25 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) FOOD FOR HUMAN CONSUMPTION HAZARD ANALYSIS AND CRITICAL CONTROL POINT (HACCP) SYSTEMS...

Ground Terminal Processor Interface Board for Skynet Uplink Synchronization Trials

DTIC Science & Technology

1997-11-01

I1 National DMfense Defence nationale GROUND TERMINAL PROCESSOR INTERFACE BOARD FOR SKYNET UPLINK SYNCHRONIZATION TRIALS by Caroline Tom 19980126...National D6fense Defence nationale GROUND TERMINAL PROCESSOR INTERFACE BOARD FOR SKYNET UPLINK SYNCHRONIZATION TRIALS by Caroline Tom MilSat...aspects of uplink synchronization for extremely-high-frequency (EHF) spread spectrum satellite communications (SATCOM). Requirements of the GT subsystem

Distributed processor allocation for launching applications in a massively connected processors complex

DOEpatents

Pedretti, Kevin

2008-11-18

A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

Real-time trajectory optimization on parallel processors

NASA Technical Reports Server (NTRS)

Psiaki, Mark L.

1993-01-01

A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

Neighborhood fast food restaurants and fast food consumption: A national study

PubMed Central

2011-01-01

Background Recent studies suggest that neighborhood fast food restaurant availability is related to greater obesity, yet few studies have investigated whether neighborhood fast food restaurant availability promotes fast food consumption. Our aim was to estimate the effect of neighborhood fast food availability on frequency of fast food consumption in a national sample of young adults, a population at high risk for obesity. Methods We used national data from U.S. young adults enrolled in wave III (2001-02; ages 18-28) of the National Longitudinal Study of Adolescent Health (n = 13,150). Urbanicity-stratified multivariate negative binomial regression models were used to examine cross-sectional associations between neighborhood fast food availability and individual-level self-reported fast food consumption frequency, controlling for individual and neighborhood characteristics. Results In adjusted analysis, fast food availability was not associated with weekly frequency of fast food consumption in non-urban or low- or high-density urban areas. Conclusions Policies aiming to reduce neighborhood availability as a means to reduce fast food consumption among young adults may be unsuccessful. Consideration of fast food outlets near school or workplace locations, factors specific to more or less urban settings, and the role of individual lifestyle attitudes and preferences are needed in future research. PMID:21740571

PREMAQ: A NEW PRE-PROCESSOR TO CMAQ FOR AIR-QUALITY FORECASTING

EPA Science Inventory

A new pre-processor to CMAQ (PREMAQ) has been developed as part of the national air-quality forecasting system. PREMAQ combines the functionality of MCIP and parts of SMOKE in a single real-time processor. PREMAQ was specifically designed to link NCEP's Eta model with CMAQ, and...

Fast Food Jobs. National Study of Fast Food Employment.

ERIC Educational Resources Information Center

Charner, Ivan; Fraser, Bryna Shore

A study examined employment in the fast-food industry. The national survey collected data from employees at 279 fast-food restaurants from seven companies. Female employees outnumbered males by two to one. The ages of those fast-food employees in the survey sample ranged from 14 to 71, with fully 70 percent being in the 16- to 20-year-old age…

A wireless electronic monitoring system for securing milk from farm to processor

NASA Astrophysics Data System (ADS)

Womble, Phillip; Hopper, Lindsay; Thompson, Chris; Alexander, Suraj M.; Crist, William; Payne, Fred; Stombaugh, Tim; Paschal, Jon; Moore, Ryan; Luck, Brian; Tabayehnejab, Nasrin

2008-04-01

The Department of Homeland Security and the Department of Health and Human Services have targeted bulk food contamination as a focus for attention. The contamination of bulk food poses a high consequence threat to our society. Milk transport falls into three of the 17 targeted NIPP (National Infrastructure Protection Plan) sectors including agriculture-food, public health, and commercial facilities. Minimal security safeguards have been developed for bulk milk transport. The current manual methods of securing milk are paper intensive and prone to errors. The bulk milk transportation sector requires a security enhancement that will both reduce recording errors and enable normal transport activities to occur while providing security against unauthorized access. Milk transportation companies currently use voluntary seal programs that utilize plastic, numbered seals on milk transport tank openings. Our group has developed a Milk Transport Security System which is an electromechanical access control and communication system that assures the secure transport of milk, milk samples, milk data, and security data between locations and specifically between dairy farms, transfer stations, receiving stations, and milk plants. It includes a security monitoring system installed on the milk transport tank, a hand held device, optional printers, data server, and security evaluation software. The system operates automatically and requires minimal or no attention by the bulk milk hauler/sampler. The system is compatible with existing milk transport infrastructure, and has the support of the milk producers, milk transportation companies, milk marketing agencies, and dairy processors. The security protocol developed is applicable for transport of other bulk foods both nationally and internationally. This system adds significantly to the national security infrastructure for bulk food transport. We are currently demonstrating the system in central Kentucky and will report on the results

Stream Processors

NASA Astrophysics Data System (ADS)

Erez, Mattan; Dally, William J.

Stream processors, like other multi core architectures partition their functional units and storage into multiple processing elements. In contrast to typical architectures, which contain symmetric general-purpose cores and a cache hierarchy, stream processors have a significantly leaner design. Stream processors are specifically designed for the stream execution model, in which applications have large amounts of explicit parallel computation, structured and predictable control, and memory accesses that can be performed at a coarse granularity. Applications in the streaming model are expressed in a gather-compute-scatter form, yielding programs with explicit control over transferring data to and from on-chip memory. Relying on these characteristics, which are common to many media processing and scientific computing applications, stream architectures redefine the boundary between software and hardware responsibilities with software bearing much of the complexity required to manage concurrency, locality, and latency tolerance. Thus, stream processors have minimal control consisting of fetching medium- and coarse-grained instructions and executing them directly on the many ALUs. Moreover, the on-chip storage hierarchy of stream processors is under explicit software control, as is all communication, eliminating the need for complex reactive hardware mechanisms.

2-D Acousto-Optic Signal Processors for Simultaneous Spectrum Analysis and Direction Finding

DTIC Science & Technology

1990-11-01

National Dfense Defence nationale 2-D ACOUSTO - OPTIC SIGNAL PROCESSORS FOR SIMULTANEOUS SPECTRUM ANALYSIS 00 AND DIRECTION FINDING (U) by NM Jim P.Y...Wr pdft .1w I0~1111191 3 05089 National DIfense Defence nationale 2-D ACOUSTO - OPTIC SIGNAL PROCESSORS FOR SIMULTANEOUS SPECTRUM ANALYSIS AND DIRECTION...Processing, J.T. Tippet et al., Eds., Chapter 38, pp. 715-748, MIT Press, Cambridge 1965. [6] A.E. Spezio," Acousto - optics for Electronic Warfare

Array processor architecture

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Green Secure Processors: Towards Power-Efficient Secure Processor Design

NASA Astrophysics Data System (ADS)

Chhabra, Siddhartha; Solihin, Yan

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Food & Nutrition | National Agricultural Library

Science.gov Websites

News Contact Us Search  Log inRegister Home Home Food & Nutrition Data from: The data of change years. Ag Data Commons 2x zip html National Animal Nutrition Program (NANP) Feed Composition Database degrees related to agriculture; USDA partner institution snapshots; Food and nutrition research; 4-H

Guest editorial, special issue on new food processing technologies and food safety

USDA-ARS?s Scientific Manuscript database

The microflora of foods is very significant to food producers, processors and consumers and the food manufacturers including distributors are responding to consumers’ demand for food products that are safe, fresher and convenient for use. In some cases foods may be improperly processed and/or contam...

50 CFR 648.6 - Dealer/processor permits.

Code of Federal Regulations, 2013 CFR

2013-10-01

... 50 Wildlife and Fisheries 12 2013-10-01 2013-10-01 false Dealer/processor permits. 648.6 Section 648.6 Wildlife and Fisheries FISHERY CONSERVATION AND MANAGEMENT, NATIONAL OCEANIC AND ATMOSPHERIC ADMINISTRATION, DEPARTMENT OF COMMERCE FISHERIES OF THE NORTHEASTERN UNITED STATES General Provisions § 648.6...

Simulating Synchronous Processors

DTIC Science & Technology

1988-06-01

34f Fvtvru m LABORATORY FOR INMASSACHUSETTSFCOMPUTER SCIENCE TECHNOLOGY MIT/LCS/TM-359 SIMULATING SYNCHRONOUS PROCESSORS Jennifer Lundelius Welch...PROJECT TASK WORK UNIT Arlington, VA 22217 ELEMENT NO. NO. NO ACCESSION NO. 11. TITLE Include Security Classification) Simulating Synchronous Processors...necessary and identify by block number) In this paper we show how a distributed system with synchronous processors and asynchro- nous message delays can

Hybrid Electro-Optic Processor

DTIC Science & Technology

1991-07-01

This report describes the design of a hybrid electro - optic processor to perform adaptive interference cancellation in radar systems. The processor is...modulator is reported. Included is this report is a discussion of the design, partial fabrication in the laboratory, and partial testing of the hybrid electro ... optic processor. A follow on effort is planned to complete the construction and testing of the processor. The work described in this report is the

Opportunities and challenges in developing a whole-of-government national food and nutrition policy: lessons from Australia's National Food Plan.

PubMed

Carey, Rachel; Caraher, Martin; Lawrence, Mark; Friel, Sharon

2016-01-01

The present article tracks the development of the Australian National Food Plan as a 'whole of government' food policy that aimed to integrate elements of nutrition and sustainability alongside economic objectives. The article uses policy analysis to explore the processes of consultation and stakeholder involvement in the development of the National Food Plan, focusing on actors from the sectors of industry, civil society and government. Existing documentation and submissions to the Plan were used as data sources. Models of health policy analysis and policy streams were employed to analyse policy development processes. Australia. Australian food policy stakeholders. The development of the Plan was influenced by powerful industry groups and stakeholder engagement by the lead ministry favoured the involvement of actors representing the food and agriculture industries. Public health nutrition and civil society relied on traditional methods of policy influence, and the public health nutrition movement failed to develop a unified cross-sector alliance, while the private sector engaged in different ways and presented a united front. The National Food Plan failed to deliver an integrated food policy for Australia. Nutrition and sustainability were effectively sidelined due to the focus on global food production and positioning Australia as a food 'superpower' that could take advantage of the anticipated 'dining boom' as incomes rose in the Asia-Pacific region. New forms of industry influence are emerging in the food policy arena and public health nutrition will need to adopt new approaches to influencing public policy.

Hybrid Optical Processor

DTIC Science & Technology

1990-08-01

LCTVs) ..................... 17 2.14 JOINT FOURIER TRANSFORM PROCESSOR .................. 18 2.15 HOLOGRAPHIC ASSOCIATIVE MEMORY USING A MICRO ...RADC-TR-90-256 Final Technical Report August1990 AD-A227 163 HYBRID OPTICAL PROCESSOR Dove Electronics, Inc. J.F. Dove, F.T .S. Yu, C. Eldering...ANM SUSUE & FUNDING NUMBERS C - F19628-87-C-0086 HYBRID OPTICAL PROCESSOR PE - 61102F PR - 2305 &AUThNOA TA - J7 J.F. Dove, F.T.S. Yu, C. Eldering WU

Sequence information signal processor

DOEpatents

Peterson, John C.; Chow, Edward T.; Waterman, Michael S.; Hunkapillar, Timothy J.

1999-01-01

An electronic circuit is used to compare two sequences, such as genetic sequences, to determine which alignment of the sequences produces the greatest similarity. The circuit includes a linear array of series-connected processors, each of which stores a single element from one of the sequences and compares that element with each successive element in the other sequence. For each comparison, the processor generates a scoring parameter that indicates which segment ending at those two elements produces the greatest degree of similarity between the sequences. The processor uses the scoring parameter to generate a similar scoring parameter for a comparison between the stored element and the next successive element from the other sequence. The processor also delivers the scoring parameter to the next processor in the array for use in generating a similar scoring parameter for another pair of elements. The electronic circuit determines which processor and alignment of the sequences produce the scoring parameter with the highest value.

Multithreading in vector processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Evaluating natural antimicrobials for food application, in natural antimicrobials for food safety and quality

USDA-ARS?s Scientific Manuscript database

The microflora of foods is of practical significance to producers, processors and consumers. Food manufacturers and distributors are responding to consumers’ demand for food products that are safe, fresher and convenient for use. In some cases foods may be improperly processed and/or contaminated wi...

Food Sustainability - National Site for the Regional IPM Centers

Science.gov Websites

brochure; 280 KB pdf). United States Department of Agriculture - National Institute of Food and Agriculture . Regional IPM Centers are sponsored by the USDA National Institute of Food and Agriculture. Last update

Hardware multiplier processor

DOEpatents

Pierce, Paul E.

1986-01-01

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Hardware multiplier processor

DOEpatents

Pierce, P.E.

A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

Array processor architecture connection network

NASA Technical Reports Server (NTRS)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1982-01-01

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

Color sensor and neural processor on one chip

NASA Astrophysics Data System (ADS)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

Processor register error correction management

DOEpatents

Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

2016-12-27

Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

NASA Astrophysics Data System (ADS)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

Cache Energy Optimization Techniques For Modern Processors

DOE Office of Scientific and Technical Information (OSTI.GOV)

Mittal, Sparsh

2013-01-01

newcomers and veterans in the field of cache power management. It will help graduate students, CAD tool developers and designers in understanding the need of energy efficiency in modern computing systems. Further, it will be useful for researchers in gaining insights into algorithms and techniques for micro-architectural and system-level energy optimization using dynamic cache reconfiguration. We sincerely believe that the ``food for thought'' presented in this book will inspire the readers to develop even better ideas for designing ``green'' processors of tomorrow.« less

40 CFR 791.45 - Processors.

Code of Federal Regulations, 2010 CFR

2010-07-01

...) When a test rule or subsequent Federal Register notice pertaining to a test rule expressly obligates processors as well as manufacturers to assume direct testing and data reimbursement responsibilities. (2... processors voluntarily agree to reimburse manufacturers for a portion of test costs. Only those processors...

Monitoring occurrence and persistence of Listeria monocytogenes in foods and food processing environments in the Republic of Ireland.

PubMed

Leong, Dara; Alvarez-Ordóñez, Avelino; Jordan, Kieran

2014-01-01

Although rates of listeriosis are low in comparison to other foodborne pathogenic illness, listeriosis poses a significant risk to human health as the invasive form can have a mortality rate as high as 30%. Food processors, especially those who produce ready-to-eat (RTE) products, need to be vigilant against Listeria monocytogenes, the causative pathogen of listeriosis, and as such, the occurrence of L. monocytogenes in food and in the food processing environment needs to be carefully monitored. To examine the prevalence and patterns of contamination in food processing facilities in Ireland, 48 food processors submitted 8 samples every 2 months from March 2013 to March 2014 to be analyzed for L. monocytogenes. No positive samples were detected at 38% of the processing facilities tested. Isolates found at the remaining 62% of facilities were characterized by serotyping and Pulsed Field Gel Electrophoresis (PFGE). A general L. monocytogenes prevalence of 4.6% was seen in all samples analyzed with similar rates seen in food and environmental samples. Differences in prevalence were seen across different food processors, food sectors, sampling months etc. and PFGE analysis allowed for the examination of contamination patterns and for the identification of several persistent strains. Seven of the food processing facilities tested showed contamination with persistent strains and evidence of bacterial transfer from the processing environment to food (the same pulsotype found in both) was seen in four of the food processing facilities tested.

Monitoring occurrence and persistence of Listeria monocytogenes in foods and food processing environments in the Republic of Ireland

PubMed Central

Leong, Dara; Alvarez-Ordóñez, Avelino; Jordan, Kieran

2014-01-01

Although rates of listeriosis are low in comparison to other foodborne pathogenic illness, listeriosis poses a significant risk to human health as the invasive form can have a mortality rate as high as 30%. Food processors, especially those who produce ready-to-eat (RTE) products, need to be vigilant against Listeria monocytogenes, the causative pathogen of listeriosis, and as such, the occurrence of L. monocytogenes in food and in the food processing environment needs to be carefully monitored. To examine the prevalence and patterns of contamination in food processing facilities in Ireland, 48 food processors submitted 8 samples every 2 months from March 2013 to March 2014 to be analyzed for L. monocytogenes. No positive samples were detected at 38% of the processing facilities tested. Isolates found at the remaining 62% of facilities were characterized by serotyping and Pulsed Field Gel Electrophoresis (PFGE). A general L. monocytogenes prevalence of 4.6% was seen in all samples analyzed with similar rates seen in food and environmental samples. Differences in prevalence were seen across different food processors, food sectors, sampling months etc. and PFGE analysis allowed for the examination of contamination patterns and for the identification of several persistent strains. Seven of the food processing facilities tested showed contamination with persistent strains and evidence of bacterial transfer from the processing environment to food (the same pulsotype found in both) was seen in four of the food processing facilities tested. PMID:25191314

Food security in South Africa: a review of national surveys.

PubMed

Labadarios, Demetre; McHiza, Zandile June-Rose; Steyn, Nelia Patricia; Gericke, Gerda; Maunder, Eleni Maria Winifred; Davids, Yul Derek; Parker, Whadi-ah

2011-12-01

To assess the status of food security--i.e., access to food, food availability and food utilization--in South Africa. A systematic search of national surveys that used the Community Childhood Hunger Identification Project (CCHIP) index to measure food security in South Africa over a period of 10 years (1999-2008) was conducted. Anthropometric data for children aged 1-9 years were used to assess food utilization, and household food inventory data were used to assess food availability. Only three national surveys had used the CCHIP index, namely, the 1999 and 2005 National Food Consumption Surveys (NFCS) and the 2008 South African Social Attitudes Survey. These surveys showed a relatively large decrease in food insecurity between 1999 and 2008. However, the consistent emerging trend indicated that in poorer households women were either feeding their children a poor diet or skipping meals so their children could eat. In terms of food access and availability, the 1999 NFCS showed that households that enjoyed food security consumed an average of 16 different food items over 24 hours, whereas poorer households spent less money on food and consumed fewer than 8 different food items. Moreover, children had low mean scores for dietary diversity (3.58; standard deviation, SD: ± 1.37) and dietary variety (5.52; SD: ± 2.54) scores. In terms of food utilization, the NFCS showed that stunting in children decreased from 21.6% in 1999 to 18% in 2005. The South African government must implement measures to improve the undesirably high level of food insecurity in poorer households.

Food security in South Africa: a review of national surveys

PubMed Central

Labadarios, Demetre; Steyn, Nelia Patricia; Gericke, Gerda; Maunder, Eleni Maria Winifred; Davids, Yul Derek; Parker, Whadi-ah

2011-01-01

Abstract Objective To assess the status of food security – i.e. access to food, food availability and food utilization – in South Africa. Methods A systematic search of national surveys that used the Community Childhood Hunger Identification Project (CCHIP) index to measure food security in South Africa over a period of 10 years (1999–2008) was conducted. Anthropometric data for children aged 1–9 years were used to assess food utilization, and household food inventory data were used to assess food availability. Findings Only three national surveys had used the CCHIP index, namely, the 1999 and 2005 National Food Consumption Surveys (NFCS) and the 2008 South African Social Attitudes Survey. These surveys showed a relatively large decrease in food insecurity between 1999 and 2008. However, the consistent emerging trend indicated that in poorer households women were either feeding their children a poor diet or skipping meals so their children could eat. In terms of food access and availability, the 1999 NFCS showed that households that enjoyed food security consumed an average of 16 different food items over 24 hours, whereas poorer households spent less money on food and consumed fewer than 8 different food items. Moreover, children had low mean scores for dietary diversity (3.58; standard deviation, SD: ± 1.37) and dietary variety (5.52; SD: ± 2.54) scores. In terms of food utilization, the NFCS showed that stunting in children decreased from 21.6% in 1999 to 18% in 2005. Conclusion The South African government must implement measures to improve the undesirably high level of food insecurity in poorer households. PMID:22271946

National water, food, and trade modeling framework: The case of Egypt.

PubMed

Abdelkader, A; Elshorbagy, A; Tuninetti, M; Laio, F; Ridolfi, L; Fahmy, H; Hoekstra, A Y

2018-10-15

This paper introduces a modeling framework for the analysis of real and virtual water flows at national scale. The framework has two components: (1) a national water model that simulates agricultural, industrial and municipal water uses, and available water and land resources; and (2) an international virtual water trade model that captures national virtual water exports and imports related to trade in crops and animal products. This National Water, Food & Trade (NWFT) modeling framework is applied to Egypt, a water-poor country and the world's largest importer of wheat. Egypt's food and water gaps and the country's food (virtual water) imports are estimated over a baseline period (1986-2013) and projected up to 2050 based on four scenarios. Egypt's food and water gaps are growing rapidly as a result of steep population growth and limited water resources. The NWFT modeling framework shows the nexus of the population dynamics, water uses for different sectors, and their compounding effects on Egypt's food gap and water self-sufficiency. The sensitivity analysis reveals that for solving Egypt's water and food problem non-water-based solutions like educational, health, and awareness programs aimed at lowering population growth will be an essential addition to the traditional water resources development solution. Both the national and the global models project similar trends of Egypt's food gap. The NWFT modeling framework can be easily adapted to other nations and regions. Copyright © 2018. Published by Elsevier B.V.

Optical Associative Processors For Visual Perception"

NASA Astrophysics Data System (ADS)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

Food Costs...From Farm to Retail.

ERIC Educational Resources Information Center

Dunham, Denis

This report focuses on food costs for 1985. Some of the information included in the report includes an analysis of food cost trends, percentages of the food dollar that goes to the farmer, and how much of the food dollar goes to food processors and marketers. Some of the highlights of the study are the following: (1) food prices rose slowly in…

Food insecurity in veteran households: findings from nationally representative data.

PubMed

Miller, Daniel P; Larson, Mary Jo; Byrne, Thomas; DeVoe, Ellen

2016-07-01

The present study is the first to use nationally representative data to compare rates of food insecurity among households with veterans of the US Armed Forces and non-veteran households. We used data from the 2005-2013 waves of the Current Population Survey - Food Security Supplement to identify rates of food insecurity and very low food security in veteran and non-veteran households. We estimated the odds and probability of food insecurity in veteran and non-veteran households in uncontrolled and controlled models. We replicated these results after separating veteran households by their most recent period of service. We weighted models to create nationally representative estimates. Nationally representative data from the 2005-2013 waves of the Current Population Survey - Food Security Supplement. US households (n 388 680). Uncontrolled models found much lower rates of food insecurity (8·4 %) and very low food security (3·3 %) among veteran households than in non-veteran households (14·4 % and 5·4 %, respectively), with particularly low rates among households with older veterans. After adjustment, average rates of food insecurity and very low food security were not significantly different for veteran households. However, the probability of food insecurity was significantly higher among some recent veterans and significantly lower for those who served during the Vietnam War. Although adjusting eliminated many differences between veteran and non-veteran households, veterans who served from 1975 and onwards may be at higher risk for food insecurity and should be the recipients of targeted outreach to improve nutritional outcomes.

Implementation of kernels on the Maestro processor

NASA Astrophysics Data System (ADS)

Suh, Jinwoo; Kang, D. I. D.; Crago, S. P.

Currently, most microprocessors use multiple cores to increase performance while limiting power usage. Some processors use not just a few cores, but tens of cores or even 100 cores. One such many-core microprocessor is the Maestro processor, which is based on Tilera's TILE64 processor. The Maestro chip is a 49-core, general-purpose, radiation-hardened processor designed for space applications. The Maestro processor, unlike the TILE64, has a floating point unit (FPU) in each core for improved floating point performance. The Maestro processor runs at 342 MHz clock frequency. On the Maestro processor, we implemented several widely used kernels: matrix multiplication, vector add, FIR filter, and FFT. We measured and analyzed the performance of these kernels. The achieved performance was up to 5.7 GFLOPS, and the speedup compared to single tile was up to 49 using 49 tiles.

Neurovision processor for designing intelligent sensors

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

USDA's National Food and Nutrient Analysis Program (NFNAP) produces high-quality data for USDA food composition databases: Two decades of collaboration.

PubMed

Haytowitz, David B; Pehrsson, Pamela R

2018-01-01

For nearly 20years, the National Food and Nutrient Analysis Program (NFNAP) has expanded and improved the quantity and quality of data in US Department of Agriculture's (USDA) food composition databases (FCDB) through the collection and analysis of nationally representative food samples. NFNAP employs statistically valid sampling plans, the Key Foods approach to identify and prioritize foods and nutrients, comprehensive quality control protocols, and analytical oversight to generate new and updated analytical data for food components. NFNAP has allowed the Nutrient Data Laboratory to keep up with the dynamic US food supply and emerging scientific research. Recently generated results for nationally representative food samples show marked changes compared to previous database values for selected nutrients. Monitoring changes in the composition of foods is critical in keeping FCDB up-to-date, so that they remain a vital tool in assessing the nutrient intake of national populations, as well as for providing dietary advice. Published by Elsevier Ltd.

Feasibility of Community Food Item Collection for the National Children's Study.

EPA Science Inventory

Background: The National Children’s Study proposes to investigate the role of environmental influences on health outcomes in pregnant women and children. A specific area of concern is contaminant exposure through the ingestion of solid foods. National food contaminant database...

Parallel processor for real-time structural control

NASA Astrophysics Data System (ADS)

Tise, Bert L.

1993-07-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-to-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection to host computer, parallelizing code generator, and look- up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating- point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An OpenWindows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.

Parallel processor for real-time structural control

DOE Office of Scientific and Technical Information (OSTI.GOV)

Tise, B.L.

1992-01-01

A parallel processor that is optimized for real-time linear control has been developed. This modular system consists of A/D modules, D/A modules, and floating-point processor modules. The scalable processor uses up to 1,000 Motorola DSP96002 floating-point processors for a peak computational rate of 60 GFLOPS. Sampling rates up to 625 kHz are supported by this analog-in to analog-out controller. The high processing rate and parallel architecture make this processor suitable for computing state-space equations and other multiply/accumulate-intensive digital filters. Processor features include 14-bit conversion devices, low input-output latency, 240 Mbyte/s synchronous backplane bus, low-skew clock distribution circuit, VME connection tomore » host computer, parallelizing code generator, and look-up-tables for actuator linearization. This processor was designed primarily for experiments in structural control. The A/D modules sample sensors mounted on the structure and the floating-point processor modules compute the outputs using the programmed control equations. The outputs are sent through the D/A module to the power amps used to drive the structure's actuators. The host computer is a Sun workstation. An Open Windows-based control panel is provided to facilitate data transfer to and from the processor, as well as to control the operating mode of the processor. A diagnostic mode is provided to allow stimulation of the structure and acquisition of the structural response via sensor inputs.« less

Feasibility of Community Food Item Collection for the National Children's Study

EPA Science Inventory

The National Children’s Study proposes to investigate the role of contaminants on health outcomes in pregnant women and children. A specific area of concern is contaminant exposure through the ingestion of solid foods. National food contaminant databases may miss environmental ex...

Rectangular Array Of Digital Processors For Planning Paths

NASA Technical Reports Server (NTRS)

Kemeny, Sabrina E.; Fossum, Eric R.; Nixon, Robert H.

1993-01-01

Prototype 24 x 25 rectangular array of asynchronous parallel digital processors rapidly finds best path across two-dimensional field, which could be patch of terrain traversed by robotic or military vehicle. Implemented as single-chip very-large-scale integrated circuit. Excepting processors on edges, each processor communicates with four nearest neighbors along paths representing travel to north, south, east, and west. Each processor contains delay generator in form of 8-bit ripple counter, preset to 1 of 256 possible values. Operation begins with choice of processor representing starting point. Transmits signals to nearest neighbor processors, which retransmits to other neighboring processors, and process repeats until signals propagated across entire field.

US Food Industry Progress During the National Salt Reduction Initiative: 2009-2014.

PubMed

Curtis, Christine J; Clapp, Jenifer; Niederman, Sarah A; Ng, Shu Wen; Angell, Sonia Y

2016-10-01

To assess the US packaged food industry's progress from 2009 to 2014, when the National Salt Reduction Initiative had voluntary, category-specific sodium targets with the goal of reducing sodium in packaged and restaurant foods by 25% over 5 years. Using the National Salt Reduction Initiative Packaged Food Database, we assessed target achievement and change in sales-weighted mean sodium density in top-selling products in 61 food categories in 2009 (n = 6336), 2012 (n = 6898), and 2014 (n = 7396). In 2009, when the targets were established, no categories met National Salt Reduction Initiative 2012 or 2014 targets. By 2014, 26% of categories met 2012 targets and 3% met 2014 targets. From 2009 to 2014, the sales-weighted mean sodium density declined significantly in almost half of all food categories (43%; 26/61 categories). Overall, sales-weighted mean sodium density declined significantly (by 6.8%; P < .001). National target setting with monitoring through a partnership of local, state, and national health organizations proved feasible, but industry progress was modest. The US Food and Drug Administration's proposed voluntary targets will be an important step in achieving more substantial sodium reductions.

Optimal processor assignment for pipeline computations

NASA Technical Reports Server (NTRS)

Nicol, David M.; Simha, Rahul; Choudhury, Alok N.; Narahari, Bhagirath

1991-01-01

The availability of large scale multitasked parallel architectures introduces the following processor assignment problem for pipelined computations. Given a set of tasks and their precedence constraints, along with their experimentally determined individual responses times for different processor sizes, find an assignment of processor to tasks. Two objectives are of interest: minimal response given a throughput requirement, and maximal throughput given a response time requirement. These assignment problems differ considerably from the classical mapping problem in which several tasks share a processor; instead, it is assumed that a large number of processors are to be assigned to a relatively small number of tasks. Efficient assignment algorithms were developed for different classes of task structures. For a p processor system and a series parallel precedence graph with n constituent tasks, an O(np2) algorithm is provided that finds the optimal assignment for the response time optimization problem; it was found that the assignment optimizing the constrained throughput in O(np2log p) time. Special cases of linear, independent, and tree graphs are also considered.

Lenslet array processors.

PubMed

Glaser, I

1982-04-01

By combining a lenslet array with masks it is possible to obtain a noncoherent optical processor capable of computing in parallel generalized 2-D discrete linear transformations. We present here an analysis of such lenslet array processors (LAP). The effect of several errors, including optical aberrations, diffraction, vignetting, and geometrical and mask errors, are calculated, and guidelines to optical design of LAP are derived. Using these results, both ultimate and practical performances of LAP are compared with those of competing techniques.

Automobile Crash Sensor Signal Processor

DOT National Transportation Integrated Search

1973-11-01

The crash sensor signal processor described interfaces between an automobile-installed doppler radar and an air bag activating solenoid or equivalent electromechanical device. The processor utilizes both digital and analog techniques to produce an ou...

Processor architecture for airborne SAR systems

NASA Technical Reports Server (NTRS)

Glass, C. M.

1983-01-01

Digital processors for spaceborne imaging radars and application of the technology developed for airborne SAR systems are considered. Transferring algorithms and implementation techniques from airborne to spaceborne SAR processors offers obvious advantages. The following topics are discussed: (1) a quantification of the differences in processing algorithms for airborne and spaceborne SARs; and (2) an overview of three processors for airborne SAR systems.

Analog Processor To Solve Optimization Problems

NASA Technical Reports Server (NTRS)

Duong, Tuan A.; Eberhardt, Silvio P.; Thakoor, Anil P.

1993-01-01

Proposed analog processor solves "traveling-salesman" problem, considered paradigm of global-optimization problems involving routing or allocation of resources. Includes electronic neural network and auxiliary circuitry based partly on concepts described in "Neural-Network Processor Would Allocate Resources" (NPO-17781) and "Neural Network Solves 'Traveling-Salesman' Problem" (NPO-17807). Processor based on highly parallel computing solves problem in significantly less time.

Enabling Future Robotic Missions with Multicore Processors

NASA Technical Reports Server (NTRS)

Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

2011-01-01

Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

Ultra-Reliable Digital Avionics (URDA) processor

NASA Astrophysics Data System (ADS)

Branstetter, Reagan; Ruszczyk, William; Miville, Frank

1994-10-01

Texas Instruments Incorporated (TI) developed the URDA processor design under contract with the U.S. Air Force Wright Laboratory and the U.S. Army Night Vision and Electro-Sensors Directorate. TI's approach couples advanced packaging solutions with advanced integrated circuit (IC) technology to provide a high-performance (200 MIPS/800 MFLOPS) modular avionics processor module for a wide range of avionics applications. TI's processor design integrates two Ada-programmable, URDA basic processor modules (BPM's) with a JIAWG-compatible PiBus and TMBus on a single F-22 common integrated processor-compatible form-factor SEM-E avionics card. A separate, high-speed (25-MWord/second 32-bit word) input/output bus is provided for sensor data. Each BPM provides a peak throughput of 100 MIPS scalar concurrent with 400-MFLOPS vector processing in a removable multichip module (MCM) mounted to a liquid-flowthrough (LFT) core and interfacing to a processor interface module printed wiring board (PWB). Commercial RISC technology coupled with TI's advanced bipolar complementary metal oxide semiconductor (BiCMOS) application specific integrated circuit (ASIC) and silicon-on-silicon packaging technologies are used to achieve the high performance in a miniaturized package. A Mips R4000-family reduced instruction set computer (RISC) processor and a TI 100-MHz BiCMOS vector coprocessor (VCP) ASIC provide, respectively, the 100 MIPS of a scalar processor throughput and 400 MFLOPS of vector processing throughput for each BPM. The TI Aladdim ASIC chipset was developed on the TI Aladdin Program under contract with the U.S. Army Communications and Electronics Command and was sponsored by the Advanced Research Projects Agency with technical direction from the U.S. Army Night Vision and Electro-Sensors Directorate.

Communications systems and methods for subsea processors

DOEpatents

Gutierrez, Jose; Pereira, Luis

2016-04-26

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

Experimental testing of the noise-canceling processor.

PubMed

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

7 CFR 1215.14 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who owns...

Cross-Continental Comparison of National Food Consumption Survey Methods—A Narrative Review

PubMed Central

De Keyzer, Willem; Bracke, Tatiana; McNaughton, Sarah A.; Parnell, Winsome; Moshfegh, Alanna J.; Pereira, Rosangela A.; Lee, Haeng-Shin; van’t Veer, Pieter; De Henauw, Stefaan; Huybrechts, Inge

2015-01-01

Food consumption surveys are performed in many countries. Comparison of results from those surveys across nations is difficult because of differences in methodological approaches. While consensus about the preferred methodology associated with national food consumption surveys is increasing, no inventory of methodological aspects across continents is available. The aims of the present review are (1) to develop a framework of key methodological elements related to national food consumption surveys, (2) to create an inventory of these properties of surveys performed in the continents North-America, South-America, Asia and Australasia, and (3) to discuss and compare these methodological properties cross-continentally. A literature search was performed using a fixed set of search terms in different databases. The inventory was completed with all accessible information from all retrieved publications and corresponding authors were requested to provide additional information where missing. Surveys from ten individual countries, originating from four continents are listed in the inventory. The results are presented according to six major aspects of food consumption surveys. The most common dietary intake assessment method used in food consumption surveys worldwide is the 24-HDR (24 h dietary recall), occasionally administered repeatedly, mostly using interview software. Only three countries have incorporated their national food consumption surveys into continuous national health and nutrition examination surveys. PMID:25984745

Discrete Choice Model of Food Store Trips Using National Household Food Acquisition and Purchase Survey (FoodAPS).

PubMed

Hillier, Amy; Smith, Tony E; Whiteman, Eliza D; Chrisinger, Benjamin W

2017-09-27

Where households across income levels shop for food is of central concern within a growing body of research focused on where people live relative to where they shop, what they purchase and eat, and how those choices influence the risk of obesity and chronic disease. We analyzed data from the National Household Food Acquisition and Purchase Survey (FoodAPS) using a conditional logit model to determine where participants shop for food to be prepared and eaten at home and how individual and household characteristics of food shoppers interact with store characteristics and distance from home in determining store choice. Store size, whether or not it was a full-service supermarket, and the driving distance from home to the store constituted the three significant main effects on store choice. Overall, participants were more likely to choose larger stores, conventional supermarkets rather than super-centers and other types of stores, and stores closer to home. Interaction effects show that participants receiving Supplemental Nutrition Assistance Program (SNAP) were even more likely to choose larger stores. Hispanic participants were more likely than non-Hispanics to choose full-service supermarkets while White participants were more likely to travel further than non-Whites. This study demonstrates the value of explicitly spatial discrete choice models and provides evidence of national trends consistent with previous smaller, local studies.

Discrete Choice Model of Food Store Trips Using National Household Food Acquisition and Purchase Survey (FoodAPS)

PubMed Central

Hillier, Amy; Smith, Tony E.; Whiteman, Eliza D.

2017-01-01

Where households across income levels shop for food is of central concern within a growing body of research focused on where people live relative to where they shop, what they purchase and eat, and how those choices influence the risk of obesity and chronic disease. We analyzed data from the National Household Food Acquisition and Purchase Survey (FoodAPS) using a conditional logit model to determine where participants shop for food to be prepared and eaten at home and how individual and household characteristics of food shoppers interact with store characteristics and distance from home in determining store choice. Store size, whether or not it was a full-service supermarket, and the driving distance from home to the store constituted the three significant main effects on store choice. Overall, participants were more likely to choose larger stores, conventional supermarkets rather than super-centers and other types of stores, and stores closer to home. Interaction effects show that participants receiving Supplemental Nutrition Assistance Program (SNAP) were even more likely to choose larger stores. Hispanic participants were more likely than non-Hispanics to choose full-service supermarkets while White participants were more likely to travel further than non-Whites. This study demonstrates the value of explicitly spatial discrete choice models and provides evidence of national trends consistent with previous smaller, local studies. PMID:28953221

Global food terror in Japan: media shaping risk perception, the nation, and women.

PubMed

Rosenberger, Nancy

2009-01-01

This article traces the Japanese media's response to Chinese poison pot-stickers (gyoza) in Japan's food system as they debate and guide consumer-citizens' feelings of increasing vulnerability as individuals in the global market, the nation, and families. Global food becomes a key metaphor for threats to national borders and the need for national food, yet simultaneously for inevitable risk to globally attuned stomachs that can be controlled only by alert housewives and education of the young. Food terror effectively signals citizens' lack of protection in risk society, but leaves unsaid important differences among consumer-citizens to save themselves with scarce Japanese-made food.

Parallel processor-based raster graphics system architecture

DOEpatents

Littlefield, Richard J.

1990-01-01

An apparatus for generating raster graphics images from the graphics command stream includes a plurality of graphics processors connected in parallel, each adapted to receive any part of the graphics command stream for processing the command stream part into pixel data. The apparatus also includes a frame buffer for mapping the pixel data to pixel locations and an interconnection network for interconnecting the graphics processors to the frame buffer. Through the interconnection network, each graphics processor may access any part of the frame buffer concurrently with another graphics processor accessing any other part of the frame buffer. The plurality of graphics processors can thereby transmit concurrently pixel data to pixel locations in the frame buffer.

USDA's National Food and Nutrient Analysis Program (NFNAP) Produces High-Quality Data for USDA Food Composition Databases: Two Decades of Collaboration

USDA-ARS?s Scientific Manuscript database

For nearly 20 years, the National Food and Nutrient Analysis Program (NFNAP) has expanded and improved the quantity and quality of data in US Department of Agriculture’s (USDA) food composition databases through the collection and analysis of nationally representative food samples. This manuscript d...

Multimode power processor

DOEpatents

O'Sullivan, G.A.; O'Sullivan, J.A.

1999-07-27

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources. 31 figs.

Multimode power processor

DOEpatents

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

PixonVision real-time video processor

NASA Astrophysics Data System (ADS)

Puetter, R. C.; Hier, R. G.

2007-09-01

PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

Cross-continental comparison of national food consumption survey methods--a narrative review

USDA-ARS?s Scientific Manuscript database

Food consumption surveys are performed in many countries. Comparison of results from those surveys across nations is difficult because of differences in methodological approaches. While consensus about the preferred methodology associated with national food consumption surveys is increasing, no in...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 926.13 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... RECORDKEEPING REQUIREMENTS APPLICABLE TO CRANBERRIES NOT SUBJECT TO THE CRANBERRY MARKETING ORDER § 926.13 Processor. Processor means any person who receives or acquires fresh or frozen cranberries or cranberries in... uses such cranberries or concentrate, with or without other ingredients, in the production of a product...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 9 2010-01-01 2009-01-01 true Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 9 2011-01-01 2011-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 9 2013-01-01 2013-01-01 false Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 9 2012-01-01 2012-01-01 false Fluid milk processor. 1160.108 Section 1160.108... Agreements and Orders; Milk), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

7 CFR 1160.108 - Fluid milk processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 9 2014-01-01 2013-01-01 true Fluid milk processor. 1160.108 Section 1160.108... AGREEMENTS AND ORDERS; MILK), DEPARTMENT OF AGRICULTURE FLUID MILK PROMOTION PROGRAM Fluid Milk Promotion Order Definitions § 1160.108 Fluid milk processor. (a) Fluid milk processor means any person who...

Modeling heterogeneous processor scheduling for real time systems

NASA Technical Reports Server (NTRS)

Leathrum, J. F.; Mielke, R. R.; Stoughton, J. W.

1994-01-01

A new model is presented to describe dataflow algorithms implemented in a multiprocessing system. Called the resource/data flow graph (RDFG), the model explicitly represents cyclo-static processor schedules as circuits of processor arcs which reflect the order that processors execute graph nodes. The model also allows the guarantee of meeting hard real-time deadlines. When unfolded, the model identifies statically the processor schedule. The model therefore is useful for determining the throughput and latency of systems with heterogeneous processors. The applicability of the model is demonstrated using a space surveillance algorithm.

Ionizing Solutions to Future Processor Demands for Safe Food

USDA-ARS?s Scientific Manuscript database

Food Irradiation is a safe and effective U.S. Food and Drug Administration (FDA) approved process that can be used to disinfest or delay the maturation of fruits and vegetables, improve the microbiological safety of shellfish, eggs, raw meat and poultry, spices, and seeds used for sprouting. FDA ap...

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

NASA Technical Reports Server (NTRS)

Fijany, Amir (Inventor); Bejczy, Antal K. (Inventor)

1994-01-01

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Comparison of food consumption in Indian adults between national and sub-national dietary data sources.

PubMed

Aleksandrowicz, Lukasz; Tak, Mehroosh; Green, Rosemary; Kinra, Sanjay; Haines, Andy

2017-04-01

Accurate data on dietary intake are important for public health, nutrition and agricultural policy. The National Sample Survey is widely used by policymakers in India to estimate nutritional outcomes in the country, but has not been compared with other dietary data sources. To assess relative differences across available Indian dietary data sources, we compare intake of food groups across six national and sub-national surveys between 2004 and 2012, representing various dietary intake estimation methodologies, including Household Consumption Expenditure Surveys (HCES), FFQ, food balance sheets (FBS), and 24-h recall (24HR) surveys. We matched data for relevant years, regions and economic groups, for ages 16-59. One set of national HCES and the 24HR showed a decline in food intake in India between 2004-2005 and 2011-2012, whereas another HCES and FBS showed an increase. Differences in intake were smallest between the two HCES (1 % relative difference). Relative to these, FFQ and FBS had higher intake (13 and 35 %), and the 24HR lower intake (-9 %). Cereal consumption had high agreement across comparisons (average 5 % difference), whereas fruit and nuts, eggs, meat and fish and sugar had the least (120, 119, 56 and 50 % average differences, respectively). Spearman's coefficients showed high correlation of ranked food group intake across surveys. The underlying methods of the compared data highlight possible sources of under- or over-estimation, and influence their relevance for addressing various research questions and programmatic needs.

A fully reconfigurable photonic integrated signal processor

NASA Astrophysics Data System (ADS)

Liu, Weilin; Li, Ming; Guzzon, Robert S.; Norberg, Erik J.; Parker, John S.; Lu, Mingzhi; Coldren, Larry A.; Yao, Jianping

2016-03-01

Photonic signal processing has been considered a solution to overcome the inherent electronic speed limitations. Over the past few years, an impressive range of photonic integrated signal processors have been proposed, but they usually offer limited reconfigurability, a feature highly needed for the implementation of large-scale general-purpose photonic signal processors. Here, we report and experimentally demonstrate a fully reconfigurable photonic integrated signal processor based on an InP-InGaAsP material system. The proposed photonic signal processor is capable of performing reconfigurable signal processing functions including temporal integration, temporal differentiation and Hilbert transformation. The reconfigurability is achieved by controlling the injection currents to the active components of the signal processor. Our demonstration suggests great potential for chip-scale fully programmable all-optical signal processing.

78 FR 4830 - National Advisory Committee on Microbiological Criteria for Foods; Reestablishment

Federal Register 2010, 2011, 2012, 2013, 2014

2013-01-23

... DEPARTMENT OF AGRICULTURE Food Safety and Inspection Service [Docket No. FSIS-2012-0040] National Advisory Committee on Microbiological Criteria for Foods; Reestablishment AGENCY: Food Safety and... Committee on Microbiological Criteria for Foods (NACMCF). The Committee is being reestablished in...

Effect of processor temperature on film dosimetry

DOE Office of Scientific and Technical Information (OSTI.GOV)

Srivastava, Shiv P.; Das, Indra J., E-mail: idas@iupui.edu

2012-07-01

Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d{sub max.}, 10 Multiplication-Sign 10 cm{sup 2}, 100 cm) to a given dose. Anmore » automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4-40.6 Degree-Sign C (85-105 Degree-Sign F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.« less

76 FR 44573 - Child and Adult Care Food Program: National Average Payment Rates, Day Care Home Food Service...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-26

... DEPARTMENT OF AGRICULTURE Food and Nutrition Service Child and Adult Care Food Program: National Average Payment Rates, Day Care Home Food Service Payment Rates, and Administrative Reimbursement Rates for Sponsoring Organizations of Day Care Homes for the Period July 1, 2011 Through June 30, 2012...

78 FR 45176 - Child and Adult Care Food Program: National Average Payment Rates, Day Care Home Food Service...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-07-26

... DEPARTMENT OF AGRICULTURE Food and Nutrition Service Child and Adult Care Food Program: National Average Payment Rates, Day Care Home Food Service Payment Rates, and Administrative Reimbursement Rates for Sponsoring Organizations of Day Care Homes for the Period July 1, 2013 Through June 30, 2014...

76 FR 43254 - Child and Adult Care Food Program: National Average Payment Rates, Day Care Home Food Service...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-07-20

... DEPARTMENT OF AGRICULTURE Food and Nutrition Service Child and Adult Care Food Program: National Average Payment Rates, Day Care Home Food Service Payment Rates, and Administrative Reimbursement Rates for Sponsoring Organizations of Day Care Homes for the Period July 1, 2011 Through June 30, 2012...

Food Service Perspectives on National School Lunch Program Implementation.

PubMed

Tabak, Rachel G; Moreland-Russell, Sarah

2015-09-01

Explore barriers and facilitators to implementation of the new National School Lunch Program (NSLP) policy guidelines. Interviews with eight food service directors using an interview guide informed by the Consolidated Framework for Implementation Research. Food service personnel; parents, teachers, school staff; and students were important stakeholders. Characteristics of the new NSLP policy guidelines were reported to create increased demands; resources alleviated some barriers. Directors reported increased food and labor costs, food sourcing challenges, decreased student participation, and organizational constraints as barriers to implementation. Creativity in menu planning facilitated success. Factors within the food service department, characteristics of implementing individuals and the new NSLP policy guidelines, and stakeholder involvement in the implementation process relate to successful implementation.

Multiple Embedded Processors for Fault-Tolerant Computing

NASA Technical Reports Server (NTRS)

Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

2005-01-01

A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

The National Food and Nutrient Analysis Program: A decade of progress

PubMed Central

Haytowitz, David B.; Pehrsson, Pamela R.; Holden, Joanne M.

2009-01-01

The National Food and Nutrient Analysis Program (NFNAP) was designed to expand the quantity and improve the quality of data in the United States Department of Agriculture (USDA) food composition databases through the collection and analysis of nationally representative samples of foods and beverages. This paper describes some of the findings from the NFNAP and its impact on the food composition databases produced by USDA. The NFNAP employs statistically valid sampling plans, comprehensive quality control, and USDA analytical oversight as part of the program to generate new and updated analytical data for food components. USDA food consumption and composition data were used to target those foods that are major contributors of nutrients of public health significance to the U.S. diet (454 Key Foods). Foods were ranked using a scoring system, divided into quartiles, and reviewed to determine the impact of changes in their composition compared to historical values. Foods were purchased from several types of locations, such as retail outlets and fast food restaurants in different geographic areas as determined by the sampling plan, then composited and sent for analysis to commercial laboratories and cooperators, along with quality control materials. Comparisons were made to assess differences between new NFNAP means generated from original analytical data and historical means. Recently generated results for nationally representative food samples show marked changes compared to database values for selected nutrients from unknown or non-representative sampling. A number of changes were observed in many high consumption foods, e.g. the vitamin A value for cooked carrots decreased from 1,225 to 860 RAE/100g; the fat value for fast food French fried potatoes increased by 13% (14.08 to 17.06 g/100g). Trans fatty acids in margarine have decreased as companies reformulate their products in response to the required addition of trans fatty acids content on the nutrition label

Never Trust Your Word Processor

ERIC Educational Resources Information Center

Linke, Dirk

2009-01-01

In this article, the author talks about the auto correction mode of word processors that leads to a number of problems and describes an example in biochemistry exams that shows how word processors can lead to mistakes in databases and in papers. The author contends that, where this system is applied, spell checking should not be left to a word…

Programmable DNA-Mediated Multitasking Processor.

PubMed

Shu, Jian-Jun; Wang, Qi-Wen; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

2015-04-30

Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

Multi-Core Processor Memory Contention Benchmark Analysis Case Study

NASA Technical Reports Server (NTRS)

Simon, Tyler; McGalliard, James

2009-01-01

Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

The National Cancer Institute diet history questionnaire: validation of pyramid food servings.

PubMed

Millen, Amy E; Midthune, Douglas; Thompson, Frances E; Kipnis, Victor; Subar, Amy F

2006-02-01

The performance of the National Cancer Institute's food frequency questionnaire, the Diet History Questionnaire (DHQ), in estimating servings of 30 US Department of Agriculture Food Guide Pyramid food groups was evaluated in the Eating at America's Table Study (1997-1998), a nationally representative sample of men and women aged 20-79 years. Participants who completed four nonconsecutive, telephone-administered 24-hour dietary recalls (n = 1,301) were mailed a DHQ; 965 respondents completed both the 24-hour dietary recalls and the DHQ. The US Department of Agriculture's Pyramid Servings Database was used to estimate intakes of pyramid servings for both diet assessment tools. The correlation (rho) between DHQ-reported intake and true intake and the attenuation factor (lambda) were estimated using a measurement error model with repeat 24-hour dietary recalls as the reference instrument. Correlations for energy-adjusted pyramid servings of foods ranged from 0.43 (other starchy vegetables) to 0.84 (milk) among women and from 0.42 (eggs) to 0.80 (total dairy food) among men. The mean rho and lambda after energy adjustment were 0.62 and 0.60 for women and 0.63 and 0.66 for men, respectively. This food frequency questionnaire validation study of foods measured in pyramid servings allowed for a measure of food intake consistent with national dietary guidance.

Food Service Perspectives on National School Lunch Program Implementation

PubMed Central

Tabak, Rachel G.; Moreland-Russell, Sarah

2015-01-01

Objectives Explore barriers and facilitators to implementation of the new National School Lunch Program (NSLP) policy guidelines. Methods Interviews with eight food service directors using an interview guide informed by the Consolidated Framework for Implementation Research. Results Food service personnel; parents, teachers, school staff; and students were important stakeholders. Characteristics of the new NSLP policy guidelines were reported to create increased demands; resources alleviated some barriers. Directors reported increased food and labor costs, food sourcing challenges, decreased student participation, and organizational constraints as barriers to implementation. Creativity in menu planning facilitated success. Conclusions Factors within the food service department, characteristics of implementing individuals and the new NSLP policy guidelines, and stakeholder involvement in the implementation process relate to successful implementation. PMID:26417607

Limit characteristics of digital optoelectronic processor

NASA Astrophysics Data System (ADS)

Kolobrodov, V. G.; Tymchik, G. S.; Kolobrodov, M. S.

2018-01-01

In this article, the limiting characteristics of a digital optoelectronic processor are explored. The limits are defined by diffraction effects and a matrix structure of the devices for input and output of optical signals. The purpose of a present research is to optimize the parameters of the processor's components. The developed physical and mathematical model of DOEP allowed to establish the limit characteristics of the processor, restricted by diffraction effects and an array structure of the equipment for input and output of optical signals, as well as to optimize the parameters of the processor's components. The diameter of the entrance pupil of the Fourier lens is determined by the size of SLM and the pixel size of the modulator. To determine the spectral resolution, it is offered to use a concept of an optimum phase when the resolved diffraction maxima coincide with the pixel centers of the radiation detector.

The Indian National Food Security Act, 2013: a commentary.

PubMed

Varadharajan, Kiruba Sankar; Thomas, Tinku; Kurpad, Anura

2014-06-01

The National Food Security Act (NFSA) 2013, passed recently by the Indian Parliament, aims to ensure food security in India, chiefly by providing cereals at subsidized prices through the Targeted Public Distribution System (TPDS) for about two-thirds of households. The predominant line of criticism of the NFSA has been the costs of such an ambitious rights-based approach in the context of decelerating economic growth and growing fiscal deficits. We argue that the food subsidy has been increasing through the last few decades and is set to climb even higher with this act but that the incremental costs, at about 0.2% of gross domestic product, are not as high as claimed. Further, recent evidence of increasing utilization of the TPDS and decreasing corruption add credence to the act's premise that significant income transfers to poor households can be achieved, thereby promoting food security as well as dietary diversity. Several concerns remain to be addressed in the design and implementation of the act, including its proposed coverage, a cereal-centric approach, the identification of beneficiaries, and its adaptability at the state level. If these are resolved effectively, the act can prove to be a significant step forward in India's long-drawn-out battle against undernutrition and food insecurity. Finally, the NFSA also provides a fresh opportunity to reform and strengthen the TPDS, which has been an integral component of India's strategy to achieve food security at the national level.

Testing and operating a multiprocessor chip with processor redundancy

DOEpatents

Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

2014-10-21

A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Database for LDV Signal Processor Performance Analysis

NASA Technical Reports Server (NTRS)

Baker, Glenn D.; Murphy, R. Jay; Meyers, James F.

1989-01-01

A comparative and quantitative analysis of various laser velocimeter signal processors is difficult because standards for characterizing signal bursts have not been established. This leaves the researcher to select a signal processor based only on manufacturers' claims without the benefit of direct comparison. The present paper proposes the use of a database of digitized signal bursts obtained from a laser velocimeter under various configurations as a method for directly comparing signal processors.

Communications Processor Operating System Study. Executive Summary,

DTIC Science & Technology

1980-11-01

AD-A095 b36 ROME AIR DEVELOPMENT CENTER GRIFFISS AFB NY F/e 17/2 COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY. EXECUTIVE SUMM—ETC(U) NOV 80 J...COMMUNICATIONS PROCESSOR OPERATING SYSTEM STUDY Julian Gitlih SPTIC ELECTE«^ FEfi 2 6 1981^ - E APPROVED FOR PUBLIC RELEASE; DISTRIBUTION UNLIMITED "a O...Subtitle) EXECUTIVE^SUMMARY 0F> COMMUNICATIONS PROCESSOR OPERATING SYSTEM $t - • >X W tdLl - ’•• • 7 AUTHORf«! ! , Julian

Soft-core processor study for node-based architectures.

DOE Office of Scientific and Technical Information (OSTI.GOV)

Van Houten, Jonathan Roger; Jarosz, Jason P.; Welch, Benjamin James

2008-09-01

Node-based architecture (NBA) designs for future satellite projects hold the promise of decreasing system development time and costs, size, weight, and power and positioning the laboratory to address other emerging mission opportunities quickly. Reconfigurable Field Programmable Gate Array (FPGA) based modules will comprise the core of several of the NBA nodes. Microprocessing capabilities will be necessary with varying degrees of mission-specific performance requirements on these nodes. To enable the flexibility of these reconfigurable nodes, it is advantageous to incorporate the microprocessor into the FPGA itself, either as a hardcore processor built into the FPGA or as a soft-core processor builtmore » out of FPGA elements. This document describes the evaluation of three reconfigurable FPGA based processors for use in future NBA systems--two soft cores (MicroBlaze and non-fault-tolerant LEON) and one hard core (PowerPC 405). Two standard performance benchmark applications were developed for each processor. The first, Dhrystone, is a fixed-point operation metric. The second, Whetstone, is a floating-point operation metric. Several trials were run at varying code locations, loop counts, processor speeds, and cache configurations. FPGA resource utilization was recorded for each configuration. Cache configurations impacted the results greatly; for optimal processor efficiency it is necessary to enable caches on the processors. Processor caches carry a penalty; cache error mitigation is necessary when operating in a radiation environment.« less

Changes in Food Intake in Australia: Comparing the 1995 and 2011 National Nutrition Survey Results Disaggregated into Basic Foods.

PubMed

Ridoutt, Bradley; Baird, Danielle; Bastiaans, Kathryn; Hendrie, Gilly; Riley, Malcolm; Sanguansri, Peerasak; Syrette, Julie; Noakes, Manny

2016-05-25

As nations seek to address obesity and diet-related chronic disease, understanding shifts in food intake over time is an imperative. However, quantifying intake of basic foods is not straightforward because of the diversity of raw and cooked wholefoods, processed foods and mixed dishes actually consumed. In this study, data from the Australian national nutrition surveys of 1995 and 2011, each involving more than 12,000 individuals and covering more than 4500 separate foods, were coherently disaggregated into basic foods, with cooking and processing factors applied where necessary. Although Australians are generally not eating in a manner consistent with national dietary guidelines, there have been several positive changes. Australians are eating more whole fruit, a greater diversity of vegetables, more beans, peas and pulses, less refined sugar, and they have increased their preference for brown and wholegrain cereals. Adult Australians have also increased their intake of nuts and seeds. Fruit juice consumption markedly declined, especially for younger Australians. Cocoa consumption increased and shifts in dairy product intake were mixed, reflecting one of several important differences between age and gender cohorts. This study sets the context for more detailed research at the level of specific foods to understand individual and household differences.

Changes in Food Intake in Australia: Comparing the 1995 and 2011 National Nutrition Survey Results Disaggregated into Basic Foods

PubMed Central

Ridoutt, Bradley; Baird, Danielle; Bastiaans, Kathryn; Hendrie, Gilly; Riley, Malcolm; Sanguansri, Peerasak; Syrette, Julie; Noakes, Manny

2016-01-01

As nations seek to address obesity and diet-related chronic disease, understanding shifts in food intake over time is an imperative. However, quantifying intake of basic foods is not straightforward because of the diversity of raw and cooked wholefoods, processed foods and mixed dishes actually consumed. In this study, data from the Australian national nutrition surveys of 1995 and 2011, each involving more than 12,000 individuals and covering more than 4500 separate foods, were coherently disaggregated into basic foods, with cooking and processing factors applied where necessary. Although Australians are generally not eating in a manner consistent with national dietary guidelines, there have been several positive changes. Australians are eating more whole fruit, a greater diversity of vegetables, more beans, peas and pulses, less refined sugar, and they have increased their preference for brown and wholegrain cereals. Adult Australians have also increased their intake of nuts and seeds. Fruit juice consumption markedly declined, especially for younger Australians. Cocoa consumption increased and shifts in dairy product intake were mixed, reflecting one of several important differences between age and gender cohorts. This study sets the context for more detailed research at the level of specific foods to understand individual and household differences. PMID:28231135

Sodium content in processed foods in Argentina: compliance with the national law.

PubMed

Allemandi, Lorena; Tiscornia, María Victoria; Ponce, Miguel; Castronuovo, Luciana; Dunford, Elizabeth; Schoj, Verónica

2015-06-01

Despite the body of evidence that documents the unfavorable effects of excessive sodium consumption on blood pressure and cardiovascular health, public health efforts to decrease sodium consumption have been limited to a few countries. Argentina is the first country in Latin America to regulate sodium content of processed foods by means of a national law. The objective of this cross-sectional quantitative study is to provide a baseline comparison against the reduction targets set by the national law before its entry into force. Data were collected in February 2014 in a leading supermarket chain located in Buenos Aires. Nutrient data from package labels were analysed for 1,320 products within 14 food groups during the study period. To compare sodium concentration levels with the established maximum levels we matched the collected food groups with the food groups included in the law resulting in a total of 292 products. Data analysis was conducted using SPSS version 20 software. Food groups with the highest median sodium content were sauces and spreads (866.7 mg/100 g), meat and meat products (750 mg/100 g) and snack foods (644 mg/100 g). Categories with the highest sodium content were appetizers (1,415 mg/100 g), sausages (1,050 mg/100 g) and ready-made meals (940.7 mg/100 g). We also found large variability within products from the same food categories. Products included in the national law correspond to 22.1% (n=292) of the surveyed foods. From the 18 food groups, 15 showed median sodium values below the established targets. Products exceeding the established maximum levels correspond to 15.1% (n=44) of the products included in the analysis. This study is the first analysis of food labels to determine sodium concentrations of processed foods in Argentina and to provide a baseline against the national law standards. Upon the completion of this analysis, maximum levels have been achieved by most of the food groups included in the law. Thus, the introduction of

An optical/digital processor - Hardware and applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Sterling, W. M.

1975-01-01

A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD2PO4) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased-array radar data processing, synthetic-aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Quality-control materials in the USDA National Food and Nutrient Analysis Program (NFNAP).

PubMed

Phillips, Katherine M; Patterson, Kristine Y; Rasor, Amy S; Exler, Jacob; Haytowitz, David B; Holden, Joanne M; Pehrsson, Pamela R

2006-03-01

The US Department of Agriculture (USDA) Nutrient Data Laboratory (NDL) develops and maintains the USDA National Nutrient Databank System (NDBS). Data are released from the NDBS for scientific and public use through the USDA National Nutrient Database for Standard Reference (SR) ( http://www.ars.usda.gov/ba/bhnrc/ndl ). In 1997 the NDL initiated the National Food and Nutrient Analysis Program (NFNAP) to update and expand its food-composition data. The program included: 1) nationwide probability-based sampling of foods; 2) central processing and archiving of food samples; 3) analysis of food components at commercial, government, and university laboratories; 4) incorporation of new analytical data into the NDBS; and 5) dissemination of these data to the scientific community. A key feature and strength of the NFNAP was a rigorous quality-control program that enabled independent verification of the accuracy and precision of analytical results. Custom-made food-control composites and/or commercially available certified reference materials were sent to the laboratories, blinded, with the samples. Data for these materials were essential to ongoing monitoring of analytical work, to identify and resolve suspected analytical problems, to ensure the accuracy and precision of results for the NFNAP food samples.

A digital retina-like low-level vision processor.

PubMed

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Simulation of a master-slave event set processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Comfort, J.C.

1984-03-01

Event set manipulation may consume a considerable amount of the computation time spent in performing a discrete-event simulation. One way of minimizing this time is to allow event set processing to proceed in parallel with the remainder of the simulation computation. The paper describes a multiprocessor simulation computer, in which all non-event set processing is performed by the principal processor (called the host). Event set processing is coordinated by a front end processor (the master) and actually performed by several other functionally identical processors (the slaves). A trace-driven simulation program modeling this system was constructed, and was run with tracemore » output taken from two different simulation programs. Output from this simulation suggests that a significant reduction in run time may be realized by this approach. Sensitivity analysis was performed on the significant parameters to the system (number of slave processors, relative processor speeds, and interprocessor communication times). A comparison between actual and simulation run times for a one-processor system was used to assist in the validation of the simulation. 7 references.« less

The GF-3 SAR Data Processor

PubMed Central

Han, Bing; Ding, Chibiao; Zhong, Lihua; Liu, Jiayin; Qiu, Xiaolan; Hu, Yuxin; Lei, Bin

2018-01-01

The Gaofen-3 (GF-3) data processor was developed as a workstation-based GF-3 synthetic aperture radar (SAR) data processing system. The processor consists of two vital subsystems of the GF-3 ground segment, which are referred to as data ingesting subsystem (DIS) and product generation subsystem (PGS). The primary purpose of DIS is to record and catalogue GF-3 raw data with a transferring format, and PGS is to produce slant range or geocoded imagery from the signal data. This paper presents a brief introduction of the GF-3 data processor, including descriptions of the system architecture, the processing algorithms and its output format. PMID:29534464

Middle School Pupil Writing and the Word Processor.

ERIC Educational Resources Information Center

Ediger, Marlow

Pupils in middle schools should have ample opportunities to write with the use of word processors. Legible writing in longhand will always be necessary in selected situations but, nevertheless, much drudgery is taken care of when using a word processor. Word processors tend to be very user friendly in that few mechanical skills are needed by the…

The computational structural mechanics testbed generic structural-element processor manual

NASA Technical Reports Server (NTRS)

Stanley, Gary M.; Nour-Omid, Shahram

1990-01-01

The usage and development of structural finite element processors based on the CSM Testbed's Generic Element Processor (GEP) template is documented. By convention, such processors have names of the form ESi, where i is an integer. This manual is therefore intended for both Testbed users who wish to invoke ES processors during the course of a structural analysis, and Testbed developers who wish to construct new element processors (or modify existing ones).

Multiple core computer processor with globally-accessible local memories

DOE Office of Scientific and Technical Information (OSTI.GOV)

Shalf, John; Donofrio, David; Oliker, Leonid

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality ofmore » processor cores.« less

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2012 CFR

2012-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2014 CFR

2014-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2013 CFR

2013-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2011 CFR

2011-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

7 CFR 1435.310 - Sharing processors' allocations with producers.

Code of Federal Regulations, 2010 CFR

2010-01-01

... CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.310 Sharing processors' allocations with producers. (a) Every sugar beet and sugarcane processor must provide CCC a certification that: (1) The processor...

A data base processor semantics specification package

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1983-01-01

A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

Acoustooptic linear algebra processors - Architectures, algorithms, and applications

NASA Technical Reports Server (NTRS)

Casasent, D.

1984-01-01

Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

76 FR 66195 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-10-26

... DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration 50 CFR Part 679 [Docket No. 101126521-0640-02] RIN 0648-XA791 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National...

76 FR 4552 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-01-26

... DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration 50 CFR Part 679 [Docket No. 0910131363-0087-02] RIN 0648-XA176 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National...

75 FR 8840 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-26

... DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration 50 CFR Part 679 [Docket No. 0810141351-9087-02] RIN 0648-XU65 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National Marine...

77 FR 3638 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-01-25

... DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration 50 CFR Part 679 [Docket No. 101126521-0640-02] RIN 0648-XA955 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National...

75 FR 59157 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-09-27

... DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration 50 CFR Part 679 [Docket No. 0910131363-0087-02] RIN 0648-XZ27 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National Marine...

78 FR 7280 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-01

... DEPARTMENT OF COMMERCE National Oceanic and Atmospheric Administration 50 CFR Part 679 [Docket No. 111213751-2102-02] RIN 0648-XC465 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Pot Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National...

Factors which influence the consumption of street foods and fast foods in South Africa-a national survey

PubMed Central

2011-01-01

Background Very little is known about street food and fast food consumption patterns in South Africa despite this being a large sector of the national economy in terms of employment provided and sales of food. The objective of this study was to determine the use of street foods and fast foods purchased by South Africans living in different provinces and geographic areas. Methods A cross-sectional survey was conducted. Structured interview-administered questionnaires in 11 official languages were conducted at the participants' homes. A nationally representative sample (n = 3287) was drawn from all ethnic groups, and provinces including participants 16 years and older. Logistic regression was done to evaluate factors impacting on fast food consumption. Results Frequent (2 ≥ times/week) street food consumption ranged from 1.8% in Northern Cape to 20.6% in Limpopo; frequent (2 ≥ times/week) fast food consumption ranged between 1.5% in North West Province to 14.7% in Gauteng. The highest intake of street food was in the medium socio-economic category (14.7%) while the highest intake of fast foods was in the high socio-economic category (13.2%). Overall, fruit was the most commonly purchased street food by all ethnic groups over the previous week although this practice was highest in black participants (35.8%). Purchases of soft drinks ranged from 4.8% in whites to 16.4% in blacks and savoury snacks from 2.3% to 14.5% in whites and blacks, respectively. Consumption of fast foods and street foods were influenced by a number of socio-demographic factors including ownership of major home appliances. Frequent fast food consumers had a significantly higher dietary diversity score (4.69; p < 0.0001) while frequent street food consumers had a significantly lower score (3.81; p < 0.0001). Conclusions A large percentage of the population purchase street foods and fast foods. This is of some concern when one notes the high prevalence of soft drink consumption in terms of its

An overview of microbial food safety programs in beef, pork, and poultry from farm to processing in Canada.

PubMed

Rajić, Andrijana; Waddell, Lisa A; Sargeant, Jan M; Read, Susan; Farber, Jeff; Firth, Martin J; Chambers, Albert

2007-05-01

Canada's vision for the agri-food industry in the 21st century is the establishment of a national food safety system employing hazard analysis and critical control point (HACCP) principles and microbiological verification tools, with traceability throughout the gate-to-plate continuum. Voluntary on-farm food safety (OFFS) programs, based in part on HACCP principles, provide producers with guidelines for good production practices focused on general hygiene and biosecurity. OFFS programs in beef cattle, swine, and poultry are currently being evaluated through a national recognition program of the Canadian Food Inspection Agency. Mandatory HACCP programs in federal meat facilities include microbial testing for generic Escherichia coli to verify effectiveness of the processor's dressing procedure, specific testing of ground meat for E. coli O157:H7, with zero tolerance for this organism in the tested lot, and Salmonella testing of raw products. Health Canada's policy on Listeria monocytogenes divides ready-to-eat products into three risk categories, with products previously implicated as the source of an outbreak receiving the highest priority for inspection and compliance. A national mandatory identification program to track livestock from the herd of origin to carcass inspection has been established. Can-Trace, a data standard for all food commodities, has been designed to facilitate tracking foods from the point of origin to the consumer. Although much work has already been done, a coherent national food safety strategy and concerted efforts by all stakeholders are needed to realize this vision. Cooperation of many government agencies with shared responsibility for food safety and public health will be essential.

Sodium Content of Foods Contributing to Sodium Intake: Comparison between Selected Foods from the CDC Packaged Food Database and the USDA National Nutrient Database for Standard Reference

PubMed Central

Maalouf, Joyce; Cogswell, Mary E.; Yuan, Keming; Martin, Carrie; Gillespie, Cathleen; Ahuja, Jaspreet KC; Pehrsson, Pamela; Merritt, Robert

2015-01-01

The sodium concentration (mg/100g) for 23 of 125 Sentinel Foods (e.g. white bread) were identified in the 2009 CDC Packaged Food Database (PFD) and compared with data in the USDA’s 2013 National Nutrient Database for Standard Reference(SR 26). Sentinel Foods are foods identified by USDA to be monitored as primary indicators to assess the changes in the sodium content of commercially processed foods from stores and restaurants. Overall, 937 products were evaluated in the CDC PFD, and between 3 (one brand of ready-to-eat cereal) and 126 products (white bread) were evaluated per selected food. The mean sodium concentrations of 17 of the 23 (74%) selected foods in the CDC PFD were 90%–110% of the mean sodium concentrations in SR 26 and differences in sodium concentration were statistically significant for 6 Sentinel Foods. The sodium concentration of most of the Sentinel Foods, as selected in the PFD, appeared to represent the sodium concentrations of the corresponding food category. The results of our study help improve the understanding of how nutrition information compares between national analytic values and the label and whether the selected Sentinel Foods represent their corresponding food category as indicators for assessment of change of the sodium content in the food supply. PMID:26484010

Impact of the Global Food Safety Initiative on Food Safety Worldwide: Statistical Analysis of a Survey of International Food Processors.

PubMed

Crandall, Philip G; Mauromoustakos, Andy; O'Bryan, Corliss A; Thompson, Kevin C; Yiannas, Frank; Bridges, Kerry; Francois, Catherine

2017-10-01

In 2000, the Consumer Goods Forum established the Global Food Safety Initiative (GFSI) to increase the safety of the world's food supply and to harmonize food safety regulations worldwide. In 2013, a university research team in conjunction with Diversey Consulting (Sealed Air), the Consumer Goods Forum, and officers of GFSI solicited input from more than 15,000 GFSI-certified food producers worldwide to determine whether GFSI certification had lived up to these expectations. A total of 828 usable questionnaires were analyzed, representing about 2,300 food manufacturing facilities and food suppliers in 21 countries, mainly across Western Europe, Australia, New Zealand, and North America. Nearly 90% of these certified suppliers perceived GFSI as being beneficial for addressing their food safety concerns, and respondents were eight times more likely to repeat the certification process knowing what it entailed. Nearly three-quarters (74%) of these food manufacturers would choose to go through the certification process again even if certification were not required by one of their current retail customers. Important drivers for becoming GFSI certified included continuing to do business with an existing customer, starting to do business with new customer, reducing the number of third-party food safety audits, and continuing improvement of their food safety program. Although 50% or fewer respondents stated that they saw actual increases in sales, customers, suppliers, or employees, significantly more companies agreed than disagreed that there was an increase in these key performance indicators in the year following GFSI certification. A majority of respondents (81%) agreed that there was a substantial investment in staff time since certification, and 50% agreed there was a significant capital investment. This survey is the largest and most representative of global food manufacturers conducted to date.

Food Safety in the National School Lunch Program. USDA Food and Nutrition Service

ERIC Educational Resources Information Center

US Department of Agriculture, 2010

2010-01-01

Schools that serve meals under the National School Lunch Program (NSLP) and School Breakfast Program (SBP) are required to maintain proper sanitation and health standards in conformance with all applicable State and local laws and regulations. In addition, schools are required to obtain two school food safety inspections per school year, which are…

The CSM testbed matrix processors internal logic and dataflow descriptions

NASA Technical Reports Server (NTRS)

Regelbrugge, Marc E.; Wright, Mary A.

1988-01-01

This report constitutes the final report for subtask 1 of Task 5 of NASA Contract NAS1-18444, Computational Structural Mechanics (CSM) Research. This report contains a detailed description of the coded workings of selected CSM Testbed matrix processors (i.e., TOPO, K, INV, SSOL) and of the arithmetic utility processor AUS. These processors and the current sparse matrix data structures are studied and documented. Items examined include: details of the data structures, interdependence of data structures, data-blocking logic in the data structures, processor data flow and architecture, and processor algorithmic logic flow.

The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

NASA Technical Reports Server (NTRS)

Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

2007-01-01

Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

Embedded processor extensions for image processing

NASA Astrophysics Data System (ADS)

Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

2008-04-01

The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

A novel VLSI processor architecture for supercomputing arrays

NASA Technical Reports Server (NTRS)

Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

1993-01-01

Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

Design of a MIMD neural network processor

NASA Astrophysics Data System (ADS)

Saeks, Richard E.; Priddy, Kevin L.; Pap, Robert M.; Stowell, S.

1994-03-01

The Accurate Automation Corporation (AAC) neural network processor (NNP) module is a fully programmable multiple instruction multiple data (MIMD) parallel processor optimized for the implementation of neural networks. The AAC NNP design fully exploits the intrinsic sparseness of neural network topologies. Moreover, by using a MIMD parallel processing architecture one can update multiple neurons in parallel with efficiency approaching 100 percent as the size of the network increases. Each AAC NNP module has 8 K neurons and 32 K interconnections and is capable of 140,000,000 connections per second with an eight processor array capable of over one billion connections per second.

National Chemistry Week 2000: JCE Resources in Food Chemistry

NASA Astrophysics Data System (ADS)

Jacobsen, Erica K.

2000-10-01

November brings another National Chemistry Week, and this year's theme is food chemistry. I was asked to collect and evaluate JCE resources for use with this theme, a project that took me deep into past issues of JCE and yielded many treasures. Here we present the results of searches for food chemistry information and activities. While the selected articles are mainly at the high school and college levels, there are some excellent ones for the elementary school level and some that can be adapted for younger students. The focus of all articles is on the chemistry of food itself. Activities that only use food to demonstrate a principle other than food chemistry are not included. Articles that cover household products such as cleansers and pharmaceuticals are also not included. Each article has been characterized as a demonstration, experiment, calculation, activity, or informational item; several fit more than one classification. Also included are keywords and an evaluation as to which levels the article may serve.

Distance Learning for Food Security and Rural Development: A Perspective from the United Nations Food and Agriculture Organization.

ERIC Educational Resources Information Center

McLean, Scott; Gasperini, Lavinia; Rudgard, Stephen

2002-01-01

The distance learning experiences of the United Nations Food and Agriculture Organization led to the following suggestions for applying distance learning strategies to the challenges of food security and rural development: use distance learning for the right reasons, be sensitive to context, use existing infrastructure, engage stakeholders, and…

The School Food Environment and Student BMI and Food Consumption: 2004 to 2007 National Data

PubMed Central

Terry-McElrath, Yvonne M.; O’Malley, Patrick M.; Delva, Jorge; Johnston, Lloyd D.

2009-01-01

Purpose This study identifies trends in the availability of various food choices in United States’ middle and high schools from 2004–2007, and examines the potential associations between such food availability and students’ self-reported eating habits and BMI-related outcomes. Methods Data are based on nationally representative samples of 78,442 students in 684 secondary schools surveyed from 2004 to 2007 as part of the Youth, Education, and Society (YES) study and the Monitoring the Future (MTF) study. In the YES study, school administrators and food service managers completed self-administered questionnaires on their school’s food environment. In the MTF study, students in the same schools completed self-administered questionnaires, providing data used to construct BMI and food consumption measures. Results Overall, there was a decrease in the availability of regular sugar/fat food items in both middle and high schools, and some indication of an increase high school availability of reduced fat food items through school lunch or a la carte. Some minimal evidence was found for relationships between the school food environment and student BMI-related outcomes and food consumption measures. Conclusions United States secondary schools are making progress in the types of foods offered to students, with food items of lower nutritional value becoming less prevalent in recent years. Continued monitoring of food environment trends may help clarify if and how such factors relate to youth health outcomes. PMID:19699436

7 CFR 3402.4 - Food and agricultural sciences areas targeted for National Needs Graduate and Postdoctoral...

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 15 2014-01-01 2014-01-01 false Food and agricultural sciences areas targeted for... AGRICULTURE FOOD AND AGRICULTURAL SCIENCES NATIONAL NEEDS GRADUATE AND POSTGRADUATE FELLOWSHIP GRANTS PROGRAM Program Description § 3402.4 Food and agricultural sciences areas targeted for National Needs Graduate and...

7 CFR 3402.4 - Food and agricultural sciences areas targeted for National Needs Graduate and Postdoctoral...

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 15 2013-01-01 2013-01-01 false Food and agricultural sciences areas targeted for... AGRICULTURE FOOD AND AGRICULTURAL SCIENCES NATIONAL NEEDS GRADUATE AND POSTGRADUATE FELLOWSHIP GRANTS PROGRAM Program Description § 3402.4 Food and agricultural sciences areas targeted for National Needs Graduate and...

7 CFR 3402.4 - Food and agricultural sciences areas targeted for National Needs Graduate and Postdoctoral...

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 15 2011-01-01 2011-01-01 false Food and agricultural sciences areas targeted for... AGRICULTURE FOOD AND AGRICULTURAL SCIENCES NATIONAL NEEDS GRADUATE AND POSTGRADUATE FELLOWSHIP GRANTS PROGRAM Program Description § 3402.4 Food and agricultural sciences areas targeted for National Needs Graduate and...

7 CFR 3402.4 - Food and agricultural sciences areas targeted for National Needs Graduate and Postdoctoral...

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 15 2012-01-01 2012-01-01 false Food and agricultural sciences areas targeted for... AGRICULTURE FOOD AND AGRICULTURAL SCIENCES NATIONAL NEEDS GRADUATE AND POSTGRADUATE FELLOWSHIP GRANTS PROGRAM Program Description § 3402.4 Food and agricultural sciences areas targeted for National Needs Graduate and...

Coding, testing and documentation of processors for the flight design system

NASA Technical Reports Server (NTRS)

1980-01-01

The general functional design and implementation of processors for a space flight design system are briefly described. Discussions of a basetime initialization processor; conic, analytical, and precision coasting flight processors; and an orbit lifetime processor are included. The functions of several utility routines are also discussed.

MBASIC batch processor architectural overview

NASA Technical Reports Server (NTRS)

Reynolds, S. M.

1978-01-01

The MBASIC (TM) batch processor, a language translator designed to operate in the MBASIC (TM) environment is described. Features include: (1) a CONVERT TO BATCH command, usable from the ready mode; and (2) translation of the users program in stages through several levels of intermediate language and optimization. The processor is to be designed and implemented in both machine-independent and machine-dependent sections. The architecture is planned so that optimization processes are transparent to the rest of the system and need not be included in the first design implementation cycle.

Design of RISC Processor Using VHDL and Cadence

NASA Astrophysics Data System (ADS)

Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

Real time processor for array speckle interferometry

NASA Astrophysics Data System (ADS)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-02-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Real time processor for array speckle interferometry

NASA Technical Reports Server (NTRS)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-01-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Noncoherent parallel optical processor for discrete two-dimensional linear transformations.

PubMed

Glaser, I

1980-10-01

We describe a parallel optical processor, based on a lenslet array, that provides general linear two-dimensional transformations using noncoherent light. Such a processor could become useful in image- and signal-processing applications in which the throughput requirements cannot be adequately satisfied by state-of-the-art digital processors. Experimental results that illustrate the feasibility of the processor by demonstrating its use in parallel optical computation of the two-dimensional Walsh-Hadamard transformation are presented.

Advanced Multiple Processor Configuration Study. Final Report.

ERIC Educational Resources Information Center

Clymer, S. J.

This summary of a study on multiple processor configurations includes the objectives, background, approach, and results of research undertaken to provide the Air Force with a generalized model of computer processor combinations for use in the evaluation of proposed flight training simulator computational designs. An analysis of a real-time flight…

Food Insecurity and Mental Disorders in a National Sample of U.S. Adolescents

PubMed Central

McLaughlin, Katie A.; Green, Jennifer Greif; Alegría, Margarita; Costello, E. Jane; Gruber, Michael J.; Sampson, Nancy A.; Kessler, Ronald C.

2013-01-01

Objective To examine whether food insecurity is associated with past-year DSM-IV mental disorders after controlling for standard indicators of family socioeconomic status (SES) in a U.S. national sample of adolescents. Method Data were drawn from 6,483 adolescent–parent pairs who participated in the National Comorbidity Survey Replication Adolescent Supplement, a national survey of adolescents 13 to 17 years old. Frequency and severity of food insecurity were assessed with questions based on the U.S. Department of Agriculture’s Food Security Scale (standardized to a mean of 0, variance of 1). DSM-IV mental disorders were assessed with the World Health Organization Composite International Diagnostic Interview. Associations of food insecurity with DSM-IV/Composite International Diagnostic Interview diagnoses were estimated with logistic regression models controlling for family SES (parental education, household income, relative deprivation, community-level inequality, and subjective social status). Results Food insecurity was highest in adolescents with the lowest SES. Controlling simultaneously for other aspects of SES, standardized food insecurity was associated with an increased odds of past-year mood, anxiety, behavior, and substance disorders. A 1 standard deviation increase in food insecurity was associated with a 14%increase in the odds of past-year mental disorder, even after controlling for extreme poverty. The association between food insecurity and mood disorders was strongest in adolescents living in families with a low household income and high relative deprivation. Conclusions Food insecurity is associated with a wide range of adolescent mental disorders independently of other aspects of SES. Expansion of social programs aimed at decreasing family economic strain might be one useful policy approach for improving youth mental health. PMID:23200286

A Medical Language Processor for Two Indo-European Languages

PubMed Central

Nhan, Ngo Thanh; Sager, Naomi; Lyman, Margaret; Tick, Leo J.; Borst, François; Su, Yun

1989-01-01

The syntax and semantics of clinical narrative across Indo-European languages are quite similar, making it possible to envison a single medical language processor that can be adapted for different European languages. The Linguistic String Project of New York University is continuing the development of its Medical Language Processor in this direction. The paper describes how the processor operates on English and French.

Software-Reconfigurable Processors for Spacecraft

NASA Technical Reports Server (NTRS)

Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

2005-01-01

A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

Position of the American Dietetic Association: food irradiation.

PubMed

Wood, O B; Bruhn, C M

2000-02-01

Food irradiation has been identified a sa safe technology to reduce the risk of foodborne illness as part of high-quality food production, processing, handling, and preparation. Food irradiation's history of scientific research , evaluation, and testing spans more than 40 countries around the world and it has been endorsed or support by numerous national and international food and organizations and professional groups. Food irradiation utilizes a source of ionizing energy that passes through food to destroy harmful bacteria and other organism. Often referred to as "cold pasteurization," food irradiation offers negligible loss of nutrients or sensory qualities in food as it does not substantially raise the temperature of the food during processing. Food irradiation does not replace proper food production, processing, handling, or preparation, nor can it enhance the quality of or prevent contact with foodborne bacteria after irradiation. In the United States, manufacturers are required to identify irradiated food sold to consumers with an international symbol (Radura) and and terminology describing the process on product labels. In addiction, food irradiation facilities are thoroughly regulated and monitored for worker and environmental safety. Members of The American Dietetic Association (ADA) and other food, nutrition, and health professionals have a responsibility to educate consumers, food processors, manufacturers and retailers about the safety and application of the technology. When consumers are educated about food irradiation, many prefer irradiated products because of their increased safety. It is the position of ADA that food irradiation enhances the safety and quality of the food supply and helps protect consumers from foodborne illness. The ADA encourages the government, food manufactures, food commodity groups, and qualified food and nutrition professionals to work together to educate consumers about this additional food safety tool and make this choice

21 CFR 108.35 - Thermal processing of low-acid foods packaged in hermetically sealed containers.

Code of Federal Regulations, 2010 CFR

2010-04-01

... authorized employee of the Food and Drug Administration to inspect the commercial processor's manufacturing... 21 Food and Drugs 2 2010-04-01 2010-04-01 false Thermal processing of low-acid foods packaged in hermetically sealed containers. 108.35 Section 108.35 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT...

Baseband processor development for the Advanced Communications Satellite Program

NASA Technical Reports Server (NTRS)

Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

Air-Lubricated Thermal Processor For Dry Silver Film

NASA Astrophysics Data System (ADS)

Siryj, B. W.

1980-09-01

Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

Automatic film processors' quality control test in Greek military hospitals.

PubMed

Lymberis, C; Efstathopoulos, E P; Manetou, A; Poudridis, G

1993-04-01

The two major military radiology installations (Athens, Greece) using a total of 15 automatic film processors were assessed using the 21-step-wedge method. The results of quality control in all these processors are presented. The parameters measured under actual working conditions were base and fog, contrast and speed. Base and fog as well as speed displayed large variations with average values generally higher than acceptable, whilst contrast displayed greater stability. Developer temperature was measured daily during the test and was found to be outside the film manufacturers' recommended limits in nine of the 15 processors. In only one processor did film passing time vary on an every day basis and this was due to maloperation. Developer pH test was not part of the daily monitoring service being performed every 5 days for each film processor and found to be in the range 9-12; 10 of the 15 processors presented pH values outside the limits specified by the film manufacturers.

Using the Word Processor in Writing Groups.

ERIC Educational Resources Information Center

Melia, Josie

Writing groups can use word processors or microcomputers in many different types of writing activities. Four hour-long sessions at a word processor with the help of a skilled word processing tutor have been found to be sufficient to provide a working knowledge of word processing. When two or three students enrolled in a writing class are assigned…

Food Insecurity among American Indians and Alaska Natives: A National Profile using the Current Population Survey-Food Security Supplement.

PubMed

Jernigan, Valarie Blue Bird; Huyser, Kimberly R; Valdes, Jimmy; Simonds, Vanessa Watts

2017-01-01

Food insecurity increases the risk for obesity, diabetes, hypertension, and cancer-conditions highly prevalent among American Indians and Alaska Natives (AI/ANs). Using the Current Population Survey Food Security Supplement, we analyzed the food insecurity trends of AI/ANs compared to other racial and ethnic groups in the United States from 2000 to 2010. From 2000 to 2010, 25% of AI/ANs remained consistently food insecure and AI/ANs were twice as likely to be food insecure compared to whites. Urban AI/ANs were more likely to experience food insecurity than rural AI/ANs. Our findings highlight the need for national and tribal policies that expand food assistance programs; promote and support increased access to healthy foods and community food security, in both rural and urban areas; and reduce the burden of diet-related disparities on low-income and racial/ethnic minority populations.

Packaging food for radiation processing

NASA Astrophysics Data System (ADS)

Komolprasert, Vanee

2016-12-01

Irradiation can play an important role in reducing pathogens that cause food borne illness. Food processors and food safety experts prefer that food be irradiated after packaging to prevent post-irradiation contamination. Food irradiation has been studied for the last century. However, the implementation of irradiation on prepackaged food still faces challenges on how to assess the suitability and safety of these packaging materials used during irradiation. Irradiation is known to induce chemical changes to the food packaging materials resulting in the formation of breakdown products, so called radiolysis products (RP), which may migrate into foods and affect the safety of the irradiated foods. Therefore, the safety of the food packaging material (both polymers and adjuvants) must be determined to ensure safety of irradiated packaged food. Evaluating the safety of food packaging materials presents technical challenges because of the range of possible chemicals generated by ionizing radiation. These challenges and the U.S. regulations on food irradiation are discussed in this article.

Food insecurity and mental disorders in a national sample of U.S. adolescents.

PubMed

McLaughlin, Katie A; Green, Jennifer Greif; Alegría, Margarita; Jane Costello, E; Gruber, Michael J; Sampson, Nancy A; Kessler, Ronald C

2012-12-01

To examine whether food insecurity is associated with past-year DSM-IV mental disorders after controlling for standard indicators of family socioeconomic status (SES) in a U.S. national sample of adolescents. Data were drawn from 6,483 adolescent-parent pairs who participated in the National Comorbidity Survey Replication Adolescent Supplement, a national survey of adolescents 13 to 17 years old. Frequency and severity of food insecurity were assessed with questions based on the U.S. Department of Agriculture's Food Security Scale (standardized to a mean of 0, variance of 1). DSM-IV mental disorders were assessed with the World Health Organization Composite International Diagnostic Interview. Associations of food insecurity with DSM-IV/Composite International Diagnostic Interview diagnoses were estimated with logistic regression models controlling for family SES (parental education, household income, relative deprivation, community-level inequality, and subjective social status). Food insecurity was highest in adolescents with the lowest SES. Controlling simultaneously for other aspects of SES, standardized food insecurity was associated with an increased odds of past-year mood, anxiety, behavior, and substance disorders. A 1 standard deviation increase in food insecurity was associated with a 14% increase in the odds of past-year mental disorder, even after controlling for extreme poverty. The association between food insecurity and mood disorders was strongest in adolescents living in families with a low household income and high relative deprivation. Food insecurity is associated with a wide range of adolescent mental disorders independently of other aspects of SES. Expansion of social programs aimed at decreasing family economic strain might be one useful policy approach for improving youth mental health. Copyright © 2012 American Academy of Child and Adolescent Psychiatry. Published by Elsevier Inc. All rights reserved.

Geospace simulations on the Cell BE processor

NASA Astrophysics Data System (ADS)

Germaschewski, K.; Raeder, J.; Larson, D.

2008-12-01

OpenGGCM (Open Geospace General circulation Model) is an established numerical code that simulates the Earth's space environment. The most computing intensive part is the MHD (magnetohydrodynamics) solver that models the plasma surrounding Earth and its interaction with Earth's magnetic field and the solar wind flowing in from the sun. Like other global magnetosphere codes, OpenGGCM's realism is limited by computational constraints on grid resolution. We investigate porting of the MHD solver to the Cell BE architecture, a novel inhomogeneous multicore architecture capable of up to 230 GFlops per processor. Realizing this high performance on the Cell processor is a programming challenge, though. We implemented the MHD solver using a multi-level parallel approach: On the coarsest level, the problem is distributed to processors based upon the usual domain decomposition approach. Then, on each processor, the problem is divided into 3D columns, each of which is handled by the memory limited SPEs (synergistic processing elements) slice by slice. Finally, SIMD instructions are used to fully exploit the vector/SIMD FPUs in each SPE. Memory management needs to be handled explicitly by the code, using DMA to move data from main memory to the per-SPE local store and vice versa. We obtained excellent performance numbers, a speed-up of a factor of 25 compared to just using the main processor, while still keeping the numerical implementation details of the code maintainable.

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

NASA Astrophysics Data System (ADS)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

Characterization of NIST food-matrix Standard Reference Materials for their vitamin C content.

PubMed

Thomas, Jeanice B; Yen, James H; Sharpless, Katherine E

2013-05-01

The vitamin C concentrations in three food-matrix Standard Reference Materials (SRMs) from the National Institute of Standards and Technology (NIST) have been determined by liquid chromatography (LC) with absorbance detection. These materials (SRM 1549a Whole Milk Powder, SRM 1849a Infant/Adult Nutritional Formula, and SRM 3233 Fortified Breakfast Cereal) have been characterized to support analytical measurements made by food processors that are required to provide information about their products' vitamin C content on the labels of products distributed in the United States. The SRMs are primarily intended for use in validating analytical methods for the determination of selected vitamins, elements, fatty acids, and other nutrients in these materials and in similar matrixes. They can also be used for quality assurance in the characterization of test samples or in-house control materials, and for establishing measurement traceability. Within-day precision of the LC method used to measure vitamin C in the food-matrix SRMs characterized in this study ranged from 2.7% to 6.5%.

Optical backplane interconnect switch for data processors and computers

NASA Technical Reports Server (NTRS)

Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

1989-01-01

An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

PubMed

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

NASA Astrophysics Data System (ADS)

Hudec, Ján; Gramatová, Elena

2015-07-01

The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.

Feasibility of optically interconnected parallel processors using wavelength division multiplexing

DOE Office of Scientific and Technical Information (OSTI.GOV)

Deri, R.J.; De Groot, A.J.; Haigh, R.E.

1996-03-01

New national security demands require enhanced computing systems for nearly ab initio simulations of extremely complex systems and analyzing unprecedented quantities of remote sensing data. This computational performance is being sought using parallel processing systems, in which many less powerful processors are ganged together to achieve high aggregate performance. Such systems require increased capability to communicate information between individual processor and memory elements. As it is likely that the limited performance of today`s electronic interconnects will prevent the system from achieving its ultimate performance, there is great interest in using fiber optic technology to improve interconnect communication. However, little informationmore » is available to quantify the requirements on fiber optical hardware technology for this application. Furthermore, we have sought to explore interconnect architectures that use the complete communication richness of the optical domain rather than using optics as a simple replacement for electronic interconnects. These considerations have led us to study the performance of a moderate size parallel processor with optical interconnects using multiple optical wavelengths. We quantify the bandwidth, latency, and concurrency requirements which allow a bus-type interconnect to achieve scalable computing performance using up to 256 nodes, each operating at GFLOP performance. Our key conclusion is that scalable performance, to {approx}150 GFLOPS, is achievable for several scientific codes using an optical bus with a small number of WDM channels (8 to 32), only one WDM channel received per node, and achievable optoelectronic bandwidth and latency requirements. 21 refs. , 10 figs.« less

APRON: A Cellular Processor Array Simulation and Hardware Design Tool

NASA Astrophysics Data System (ADS)

Barr, David R. W.; Dudek, Piotr

2009-12-01

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

Flood replenishment: a new method of processor control.

PubMed

Frank, E D; Gray, J E; Wilken, D A

1980-01-01

In mechanized radiographic film processors that process medium to low volumes of film, roll films, and those that process single-emulsion films from nuclear medicine scans, computed tomography, and ultrasound, it is difficult to maintain the developer solution at a stable processing level. We describe our experience using flood replenishment, which is a method in which developer replenisher containing starter solution is introduced in the processor at timed intervals, independent of the number of films being processed. By this process, a stable level of developer activity is maintained in a processor used to develop a medium to low volume of single-emulsion film.

Control structures for high speed processors

NASA Technical Reports Server (NTRS)

Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

1982-01-01

A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

Graphics Processor Units (GPUs)

NASA Technical Reports Server (NTRS)

Wyrwas, Edward J.

2017-01-01

This presentation will include information about Graphics Processor Units (GPUs) technology, NASA Electronic Parts and Packaging (NEPP) tasks, The test setup, test parameter considerations, lessons learned, collaborations, a roadmap, NEPP partners, results to date, and future plans.

Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

NASA Technical Reports Server (NTRS)

Downie, John D.; Goodman, Joseph W.

1989-01-01

The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

7 CFR 3402.4 - Food and agricultural sciences areas targeted for National Needs Graduate and Postdoctoral...

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 15 2010-01-01 2010-01-01 false Food and agricultural sciences areas targeted for..., AND EXTENSION SERVICE, DEPARTMENT OF AGRICULTURE FOOD AND AGRICULTURAL SCIENCES NATIONAL NEEDS... sciences areas targeted for National Needs Graduate and Postdoctoral Fellowship Grants Program support...

SPROC: A multiple-processor DSP IC

NASA Technical Reports Server (NTRS)

Davis, R.

1991-01-01

A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

Fault tolerant, radiation hard, high performance digital signal processor

NASA Technical Reports Server (NTRS)

Holmann, Edgar; Linscott, Ivan R.; Maurer, Michael J.; Tyler, G. L.; Libby, Vibeke

1990-01-01

An architecture has been developed for a high-performance VLSI digital signal processor that is highly reliable, fault-tolerant, and radiation-hard. The signal processor, part of a spacecraft receiver designed to support uplink radio science experiments at the outer planets, organizes the connections between redundant arithmetic resources, register files, and memory through a shuffle exchange communication network. The configuration of the network and the state of the processor resources are all under microprogram control, which both maps the resources according to algorithmic needs and reconfigures the processing should a failure occur. In addition, the microprogram is reloadable through the uplink to accommodate changes in the science objectives throughout the course of the mission. The processor will be implemented with silicon compiler tools, and its design will be verified through silicon compilation simulation at all levels from the resources to full functionality. By blending reconfiguration with redundancy the processor implementation is fault-tolerant and reliable, and possesses the long expected lifetime needed for a spacecraft mission to the outer planets.

A systematic review of sub-national food insecurity research in South Africa: Missed opportunities for policy insights.

PubMed

Misselhorn, Alison; Hendriks, Sheryl L

2017-01-01

Food insecurity is an intractable problem in South Africa. The country has a tradition of evidence-based decision making, grounded in the findings of national surveys. However, the rich insights from sub-national surveys remain a largely untapped resource for understandings of the contextual experience of food insecurity. A web-based search identified 169 sub-national food insecurity studies conducted in the post-apartheid period between 1994 and 2014. The systematic review found that the studies used 27 different measures of food insecurity, confounding the comparative analysis of food insecurity at this level. While social grants have brought a measure of poverty relief at household level, unaffordable diets were the root cause of food insecurity. The increasing consumption of cheaper, more available and preferred 'globalised' foods with high energy content and low nutritional value lead to overweight and obesity alongside child stunting. Unless a comparable set of indicators is used in such surveys, they are not able to provide comparable information on the scope and scale of the problem. Policy makers should be engaging with researchers to learn from these studies, while researchers need to share this wealth of sub-national study findings with government to strengthen food security planning, monitoring, and evaluation at all levels.

A systematic review of sub-national food insecurity research in South Africa: Missed opportunities for policy insights

PubMed Central

Misselhorn, Alison

2017-01-01

Food insecurity is an intractable problem in South Africa. The country has a tradition of evidence-based decision making, grounded in the findings of national surveys. However, the rich insights from sub-national surveys remain a largely untapped resource for understandings of the contextual experience of food insecurity. A web-based search identified 169 sub-national food insecurity studies conducted in the post-apartheid period between 1994 and 2014. The systematic review found that the studies used 27 different measures of food insecurity, confounding the comparative analysis of food insecurity at this level. While social grants have brought a measure of poverty relief at household level, unaffordable diets were the root cause of food insecurity. The increasing consumption of cheaper, more available and preferred ‘globalised’ foods with high energy content and low nutritional value lead to overweight and obesity alongside child stunting. Unless a comparable set of indicators is used in such surveys, they are not able to provide comparable information on the scope and scale of the problem. Policy makers should be engaging with researchers to learn from these studies, while researchers need to share this wealth of sub-national study findings with government to strengthen food security planning, monitoring, and evaluation at all levels. PMID:28829787

Processing techniques for software based SAR processors

NASA Technical Reports Server (NTRS)

Leung, K.; Wu, C.

1983-01-01

Software SAR processing techniques defined to treat Shuttle Imaging Radar-B (SIR-B) data are reviewed. The algorithms are devised for the data processing procedure selection, SAR correlation function implementation, multiple array processors utilization, cornerturning, variable reference length azimuth processing, and range migration handling. The Interim Digital Processor (IDP) originally implemented for handling Seasat SAR data has been adapted for the SIR-B, and offers a resolution of 100 km using a processing procedure based on the Fast Fourier Transformation fast correlation approach. Peculiarities of the Seasat SAR data processing requirements are reviewed, along with modifications introduced for the SIR-B. An Advanced Digital SAR Processor (ADSP) is under development for use with the SIR-B in the 1986 time frame as an upgrade for the IDP, which will be in service in 1984-5.

The emerging conceptualization of groups as information processors.

PubMed

Hinsz, V B; Tindale, R S; Vollrath, D A

1997-01-01

A selective review of research highlights the emerging view of groups as information processors. In this review, the authors include research on processing objectives, attention, encoding, storage, retrieval, processing, response, feedback, and learning in small interacting task groups. The groups as information processors perspective underscores several characteristic dimensions of variability in group performance of cognitive tasks, namely, commonality-uniqueness of information, convergence-diversity of ideas, accentuation-attenuation of cognitive processes, and belongingness-distinctiveness of members. A combination of contributions framework provides an additional conceptualization of information processing in groups. The authors also address implications, caveats, and questions for future research and theory regarding groups as information processors.

Multitask neurovision processor with extensive feedback and feedforward connections

NASA Astrophysics Data System (ADS)

Gupta, Madan M.; Knopf, George K.

1991-11-01

A multi-task neuro-vision parameter which performs a variety of information processing operations associated with the early stages of biological vision is presented. The network architecture of this neuro-vision processor, called the positive-negative (PN) neural processor, is loosely based on the neural activity fields exhibited by thalamic and cortical nervous tissue layers. The computational operation performed by the processor arises from the strength of the recurrent feedback among the numerous positive and negative neural computing units. By adjusting the feedback connections it is possible to generate diverse dynamic behavior that may be used for short-term visual memory (STVM), spatio-temporal filtering (STF), and pulse frequency modulation (PFM). The information attributes that are to be processes may be regulated by modifying the feedforward connections from the signal space to the neural processor.

High-performance ultra-low power VLSI analog processor for data compression

NASA Technical Reports Server (NTRS)

Tawel, Raoul (Inventor)

1996-01-01

An apparatus for data compression employing a parallel analog processor. The apparatus includes an array of processor cells with N columns and M rows wherein the processor cells have an input device, memory device, and processor device. The input device is used for inputting a series of input vectors. Each input vector is simultaneously input into each column of the array of processor cells in a pre-determined sequential order. An input vector is made up of M components, ones of which are input into ones of M processor cells making up a column of the array. The memory device is used for providing ones of M components of a codebook vector to ones of the processor cells making up a column of the array. A different codebook vector is provided to each of the N columns of the array. The processor device is used for simultaneously comparing the components of each input vector to corresponding components of each codebook vector, and for outputting a signal representative of the closeness between the compared vector components. A combination device is used to combine the signal output from each processor cell in each column of the array and to output a combined signal. A closeness determination device is then used for determining which codebook vector is closest to an input vector from the combined signals, and for outputting a codebook vector index indicating which of the N codebook vectors was the closest to each input vector input into the array.

Software-defined reconfigurable microwave photonics processor.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José

2015-06-01

We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

Ssip-a processor interconnection simulator

DOE Office of Scientific and Technical Information (OSTI.GOV)

Navaux, P.; Weber, R.; Prezzi, J.

1982-01-01

Recent growing interest in multiple processor architectures has given rise to the study of procesor-memory interconnections for the determination of better architectures. This paper concerns the development of the SSIP-sistema simulador de interconexao de processadores (processor interconnection simulating system) which allows the evaluation of different interconnection structures comparing its performance in order to provide parameters which would help the designer to define an architcture. A wide spectrum of systems may be evaluated, and their behaviour observed due to the features incorporated into the simulator program. The system modelling and the simulator program implementation are described. Some results that can bemore » obtained are shown, along with the discussion of their usefulness. 12 references.« less

DFT algorithms for bit-serial GaAs array processor architectures

NASA Technical Reports Server (NTRS)

Mcmillan, Gary B.

1988-01-01

Systems and Processes Engineering Corporation (SPEC) has developed an innovative array processor architecture for computing Fourier transforms and other commonly used signal processing algorithms. This architecture is designed to extract the highest possible array performance from state-of-the-art GaAs technology. SPEC's architectural design includes a high performance RISC processor implemented in GaAs, along with a Floating Point Coprocessor and a unique Array Communications Coprocessor, also implemented in GaAs technology. Together, these data processors represent the latest in technology, both from an architectural and implementation viewpoint. SPEC has examined numerous algorithms and parallel processing architectures to determine the optimum array processor architecture. SPEC has developed an array processor architecture with integral communications ability to provide maximum node connectivity. The Array Communications Coprocessor embeds communications operations directly in the core of the processor architecture. A Floating Point Coprocessor architecture has been defined that utilizes Bit-Serial arithmetic units, operating at very high frequency, to perform floating point operations. These Bit-Serial devices reduce the device integration level and complexity to a level compatible with state-of-the-art GaAs device technology.

A National Evaluation of the Impact of State Policies on Competitive Foods in Schools

ERIC Educational Resources Information Center

Fernandes, Meenakshi M.

2013-01-01

Background: Since 2003, many states have introduced policies to improve the nutritional content and restrict the availability of competitive foods, which are foods offered outside of the National School Lunch and Breakfast Programs. This article evaluates the impact of 2 types of state-level policies on the availability of competitive foods in a…

A high-accuracy optical linear algebra processor for finite element applications

NASA Technical Reports Server (NTRS)

Casasent, D.; Taylor, B. K.

1984-01-01

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

Implementing wavelet inverse-transform processor with surface acoustic wave device.

PubMed

Lu, Wenke; Zhu, Changchun; Liu, Qinghong; Zhang, Jingduan

2013-02-01

The objective of this research was to investigate the implementation schemes of the wavelet inverse-transform processor using surface acoustic wave (SAW) device, the length function of defining the electrodes, and the possibility of solving the load resistance and the internal resistance for the wavelet inverse-transform processor using SAW device. In this paper, we investigate the implementation schemes of the wavelet inverse-transform processor using SAW device. In the implementation scheme that the input interdigital transducer (IDT) and output IDT stand in a line, because the electrode-overlap envelope of the input IDT is identical with the one of the output IDT (i.e. the two transducers are identical), the product of the input IDT's frequency response and the output IDT's frequency response can be implemented, so that the wavelet inverse-transform processor can be fabricated. X-112(0)Y LiTaO(3) is used as a substrate material to fabricate the wavelet inverse-transform processor. The size of the wavelet inverse-transform processor using this implementation scheme is small, so its cost is low. First, according to the envelope function of the wavelet function, the length function of the electrodes is defined, then, the lengths of the electrodes can be calculated from the length function of the electrodes, finally, the input IDT and output IDT can be designed according to the lengths and widths for the electrodes. In this paper, we also present the load resistance and the internal resistance as the two problems of the wavelet inverse-transform processor using SAW devices. The solutions to these problems are achieved in this study. When the amplifiers are subjected to the input end and output end for the wavelet inverse-transform processor, they can eliminate the influence of the load resistance and the internal resistance on the output voltage of the wavelet inverse-transform processor using SAW device. Copyright © 2012 Elsevier B.V. All rights reserved.

Fuel processors for fuel cell APU applications

NASA Astrophysics Data System (ADS)

Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

Food Group Preferences of Elementary School Children Participating in the National School Lunch Program

ERIC Educational Resources Information Center

Cashman, Linda; Tripurana, Madhuri; Englund, Tim; Bergman, Ethan A.

2010-01-01

Purpose/Objectives: The purpose of the study was to assess the food group preferences of second through fifth grade children based on ethnic background, gender, and grade. Food group preferences were determined by the amount of various food groups consumed in meals served as part of the National School Lunch Program at selected schools. Research…

Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

DOEpatents

Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

2009-03-17

A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

Satellite on-board real-time SAR processor prototype

NASA Astrophysics Data System (ADS)

Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

2017-11-01

A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

Radio astronomy Explorer B antenna aspect processor

NASA Technical Reports Server (NTRS)

Miller, W. H.; Novello, J.; Reeves, C. C.

1972-01-01

The antenna aspect system used on the Radio Astronomy Explorer B spacecraft is described. This system consists of two facsimile cameras, a data encoder, and a data processor. Emphasis is placed on the discussion of the data processor, which contains a data compressor and a source encoder. With this compression scheme a compression ratio of 8 is achieved on a typical line of camera data. These compressed data are then convolutionally encoded.

Optimal partitioning of random programs across two processors

NASA Technical Reports Server (NTRS)

Nicol, D. M.

1986-01-01

The optimal partitioning of random distributed programs is discussed. It is concluded that the optimal partitioning of a homogeneous random program over a homogeneous distributed system either assigns all modules to a single processor, or distributes the modules as evenly as possible among all processors. The analysis rests heavily on the approximation which equates the expected maximum of a set of independent random variables with the set's maximum expectation. The results are strengthened by providing an approximation-free proof of this result for two processors under general conditions on the module execution time distribution. It is also shown that use of this approximation causes two of the previous central results to be false.

77 FR 38463 - Implementation of National Organic Program (NOP); Sunset Review (2012) Amendments to Pectin on...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-06-28

... operations to reformulate their products until October 21, 2012. SUPPLEMENTARY INFORMATION: The Organic Foods... processors are currently using amidated, non-organic pectin in their products. The industry indicated that these processors would need time to reformulate these products using either non-amidated, non-organic...

CoNNeCT Baseband Processor Module

NASA Technical Reports Server (NTRS)

Yamamoto, Clifford K; Jedrey, Thomas C.; Gutrich, Daniel G.; Goodpasture, Richard L.

2011-01-01

A document describes the CoNNeCT Baseband Processor Module (BPM) based on an updated processor, memory technology, and field-programmable gate arrays (FPGAs). The BPM was developed from a requirement to provide sufficient computing power and memory storage to conduct experiments for a Software Defined Radio (SDR) to be implemented. The flight SDR uses the AT697 SPARC processor with on-chip data and instruction cache. The non-volatile memory has been increased from a 20-Mbit EEPROM (electrically erasable programmable read only memory) to a 4-Gbit Flash, managed by the RTAX2000 Housekeeper, allowing more programs and FPGA bit-files to be stored. The volatile memory has been increased from a 20-Mbit SRAM (static random access memory) to a 1.25-Gbit SDRAM (synchronous dynamic random access memory), providing additional memory space for more complex operating systems and programs to be executed on the SPARC. All memory is EDAC (error detection and correction) protected, while the SPARC processor implements fault protection via TMR (triple modular redundancy) architecture. Further capability over prior BPM designs includes the addition of a second FPGA to implement features beyond the resources of a single FPGA. Both FPGAs are implemented with Xilinx Virtex-II and are interconnected by a 96-bit bus to facilitate data exchange. Dedicated 1.25- Gbit SDRAMs are wired to each Xilinx FPGA to accommodate high rate data buffering for SDR applications as well as independent SpaceWire interfaces. The RTAX2000 manages scrub and configuration of each Xilinx.

Concept of a programmable maintenance processor applicable to multiprocessing systems

NASA Technical Reports Server (NTRS)

Glover, Richard D.

1988-01-01

A programmable maintenance processor concept applicable to multiprocessing systems has been developed at the NASA Ames Research Center's Dryden Flight Research Facility. This stand-alone-processor is intended to provide support for system and application software testing as well as hardware diagnostics. An initial machanization has been incorporated into the extended aircraft interrogation and display system (XAIDS) which is multiprocessing general-purpose ground support equipment. The XAIDS maintenance processor has independent terminal and printer interfaces and a dedicated magnetic bubble memory that stores system test sequences entered from the terminal. This report describes the hardware and software embodied in this processor and shows a typical application in the check-out of a new XAIDS.

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Optoelectronic processors with scanning CCD photodetectors

NASA Astrophysics Data System (ADS)

Esepkina, N. A.; Lavrov, A. P.; Anan'ev, M. N.; Blagodarnyi, V. S.; Ivanov, S. I.; Mansyrev, M. I.; Molodyakov, S. A.

1995-10-01

Two new types of optoelectronic radio-signal processors were investigated. Charge-coupled device (CCD) photodetectors are used in these processors under continuous scanning conditions, i.e. in a time delay and storage mode. One of these processors is based on a CCD photodetector array with a reference-signal amplitude transparency and the other is an adaptive acousto-optical signal processor with linear frequency modulation. The processor with the transparency performs multichannel discrete—analogue convolution of an input signal with a corresponding kernel of the transformation determined by the transparency. If a light source is an array of light-emitting diodes of special (stripe) geometry, the optical stages of the processor can be made from optical fibre components and the whole processor then becomes a rigid 'sandwich' (a compact hybrid optoelectronic microcircuit). A report is given also of a study of a prototype processor with optical fibre components for the reception of signals from a system with antenna aperture synthesis, which forms a radio image of the Earth.

Performance of the Cell processor for biomolecular simulations

NASA Astrophysics Data System (ADS)

De Fabritiis, G.

2007-06-01

The new Cell processor represents a turning point for computing intensive applications. Here, I show that for molecular dynamics it is possible to reach an impressive sustained performance in excess of 30 Gflops with a peak of 45 Gflops for the non-bonded force calculations, over one order of magnitude faster than a single core standard processor.

Sensory impacts of food-packaging interactions.

PubMed

Duncan, Susan E; Webster, Janet B

2009-01-01

Sensory changes in food products result from intentional or unintentional interactions with packaging materials and from failure of materials to protect product integrity or quality. Resolving sensory issues related to plastic food packaging involves knowledge provided by sensory scientists, materials scientists, packaging manufacturers, food processors, and consumers. Effective communication among scientists and engineers from different disciplines and industries can help scientists understand package-product interactions. Very limited published literature describes sensory perceptions associated with food-package interactions. This article discusses sensory impacts, with emphasis on oxidation reactions, associated with the interaction of food and materials, including taints, scalping, changes in food quality as a function of packaging, and examples of material innovations for smart packaging that can improve sensory quality of foods and beverages. Sensory evaluation is an important tool for improved package selection and development of new materials.

Reconfigurable signal processor designs for advanced digital array radar systems

NASA Astrophysics Data System (ADS)

Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

2017-05-01

The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

Seasonal food use by white-tailed deer at Valley Forge National Historical Park, Pennsylvania, USA

NASA Astrophysics Data System (ADS)

Cypher, Brian L.; Yahner, Richard H.; Cypher, Ellen A.

1988-03-01

Food habits of white-tailed deer ( Odocoileus virginianus) were examined from January to November 1984 via fecal-pellet analysis at Valley Forge National Historical Park (VFNHP), which represents an “island” habitat for deer surrounded by extensive urbanization, in southeastern Pennsylvania. In addition, use of fields by deer was compared to food habits. Herbaceous vegetation (forbs, leaves of woody plants, and conifer needles) was the predominant food type in all seasons except fall. Acorns and graminoids (grasses and sedges) were important food resources in fall and spring, respectively. Use of woody browse (twigs) was similar among seasons. Field use was relatively high during fall, winter without snow cover (<20 cm), and spring when food resources in fields were readily available. In contrast, use of fields was lowest in summer when preferred woodland foods were available and in winter with snow cover when food in fields was not readily accessible. Patterns of food-type use by deer at VFNHP indicate the year-round importance of nonwoody foods and field habitats to deer populations on public lands such as national parks in the northeastern United States.

Implementation and Assessment of Advanced Analog Vector-Matrix Processor

NASA Technical Reports Server (NTRS)

Gary, Charles K.; Bualat, Maria G.; Lum, Henry, Jr. (Technical Monitor)

1994-01-01

This paper discusses the design and implementation of an analog optical vecto-rmatrix coprocessor with a throughput of 128 Mops for a personal computer. Vector matrix calculations are inherently parallel, providing a promising domain for the use of optical calculators. However, to date, digital optical systems have proven too cumbersome to replace electronics, and analog processors have not demonstrated sufficient accuracy in large scale systems. The goal of the work described in this paper is to demonstrate a viable optical coprocessor for linear operations. The analog optical processor presented has been integrated with a personal computer to provide full functionality and is the first demonstration of an optical linear algebra processor with a throughput greater than 100 Mops. The optical vector matrix processor consists of a laser diode source, an acoustooptical modulator array to input the vector information, a liquid crystal spatial light modulator to input the matrix information, an avalanche photodiode array to read out the result vector of the vector matrix multiplication, as well as transport optics and the electronics necessary to drive the optical modulators and interface to the computer. The intent of this research is to provide a low cost, highly energy efficient coprocessor for linear operations. Measurements of the analog accuracy of the processor performing 128 Mops are presented along with an assessment of the implications for future systems. A range of noise sources, including cross-talk, source amplitude fluctuations, shot noise at the detector, and non-linearities of the optoelectronic components are measured and compared to determine the most significant source of error. The possibilities for reducing these sources of error are discussed. Also, the total error is compared with that expected from a statistical analysis of the individual components and their relation to the vector-matrix operation. The sufficiency of the measured accuracy of the

New Local, National and Regional Cereal Price Indices for Improved Identification of Food Insecurity

NASA Technical Reports Server (NTRS)

Brown, Molly E.; Tondel, Fabien; Thorne, Jennifer A.; Essam, Timothy; Mann, Bristol F.; Stabler, Blake; Eilerts, Gary

2011-01-01

Large price increases over a short time period can be indicative of a deteriorating food security situation. Food price indices developed by the United Nations Food and Agriculture Organization (FAO) are used to monitor food price trends at a global level, but largely reflect supply and demand conditions in export markets. However, reporting by the United States Agency for International Development (USAID)'s Famine Early Warning Systems Network (FEWS NET) indicates that staple cereal prices in many markets of the developing world, especially in surplus-producing areas, often have a delayed and variable response to international export market price trends. Here we present new price indices compiled for improved food security monitoring and assessment, and specifically for monitoring conditions of food access across diverse food insecure regions. We found that cereal price indices constructed using market prices within a food insecure region showed significant differences from the international cereals price, and had a variable price dispersion across markets within each marketshed. Using satellite-derived remote sensing information that estimates local production and the FAO Cereals Index as predictors, we were able to forecast movements of the local or national price indices in the remote, arid and semi-arid countries of the 38 countries examined. This work supports the need for improved decision-making about targeted aid and humanitarian relief, by providing earlier early warning of food security crises.

Optical systolic array processor using residue arithmetic

NASA Technical Reports Server (NTRS)

Jackson, J.; Casasent, D.

1983-01-01

The use of residue arithmetic to increase the accuracy and reduce the dynamic range requirements of optical matrix-vector processors is evaluated. It is determined that matrix-vector operations and iterative algorithms can be performed totally in residue notation. A new parallel residue quantizer circuit is developed which significantly improves the performance of the systolic array feedback processor. Results are presented of a computer simulation of this system used to solve a set of three simultaneous equations.

FPGA wavelet processor design using language for instruction-set architectures (LISA)

NASA Astrophysics Data System (ADS)

Meyer-Bäse, Uwe; Vera, Alonzo; Rao, Suhasini; Lenk, Karl; Pattichis, Marios

2007-04-01

The design of an microprocessor is a long, tedious, and error-prone task consisting of typically three design phases: architecture exploration, software design (assembler, linker, loader, profiler), architecture implementation (RTL generation for FPGA or cell-based ASIC) and verification. The Language for instruction-set architectures (LISA) allows to model a microprocessor not only from instruction-set but also from architecture description including pipelining behavior that allows a design and development tool consistency over all levels of the design. To explore the capability of the LISA processor design platform a.k.a. CoWare Processor Designer we present in this paper three microprocessor designs that implement a 8/8 wavelet transform processor that is typically used in today's FBI fingerprint compression scheme. We have designed a 3 stage pipelined 16 bit RISC processor (NanoBlaze). Although RISC μPs are usually considered "fast" processors due to design concept like constant instruction word size, deep pipelines and many general purpose registers, it turns out that DSP operations consume essential processing time in a RISC processor. In a second step we have used design principles from programmable digital signal processor (PDSP) to improve the throughput of the DWT processor. A multiply-accumulate operation along with indirect addressing operation were the key to achieve higher throughput. A further improvement is possible with today's FPGA technology. Today's FPGAs offer a large number of embedded array multipliers and it is now feasible to design a "true" vector processor (TVP). A multiplication of two vectors can be done in just one clock cycle with our TVP, a complete scalar product in two clock cycles. Code profiling and Xilinx FPGA ISE synthesis results are provided that demonstrate the essential improvement that a TVP has compared with traditional RISC or PDSP designs.

Geospace simulations using modern accelerator processor technology

NASA Astrophysics Data System (ADS)

Germaschewski, K.; Raeder, J.; Larson, D. J.

2009-12-01

OpenGGCM (Open Geospace General Circulation Model) is a well-established numerical code simulating the Earth's space environment. The most computing intensive part is the MHD (magnetohydrodynamics) solver that models the plasma surrounding Earth and its interaction with Earth's magnetic field and the solar wind flowing in from the sun. Like other global magnetosphere codes, OpenGGCM's realism is currently limited by computational constraints on grid resolution. OpenGGCM has been ported to make use of the added computational powerof modern accelerator based processor architectures, in particular the Cell processor. The Cell architecture is a novel inhomogeneous multicore architecture capable of achieving up to 230 GFLops on a single chip. The University of New Hampshire recently acquired a PowerXCell 8i based computing cluster, and here we will report initial performance results of OpenGGCM. Realizing the high theoretical performance of the Cell processor is a programming challenge, though. We implemented the MHD solver using a multi-level parallelization approach: On the coarsest level, the problem is distributed to processors based upon the usual domain decomposition approach. Then, on each processor, the problem is divided into 3D columns, each of which is handled by the memory limited SPEs (synergistic processing elements) slice by slice. Finally, SIMD instructions are used to fully exploit the SIMD FPUs in each SPE. Memory management needs to be handled explicitly by the code, using DMA to move data from main memory to the per-SPE local store and vice versa. We use a modern technique, automatic code generation, which shields the application programmer from having to deal with all of the implementation details just described, keeping the code much more easily maintainable. Our preliminary results indicate excellent performance, a speed-up of a factor of 30 compared to the unoptimized version.

Effect of poor control of film processors on mammographic image quality.

PubMed

Kimme-Smith, C; Sun, H; Bassett, L W; Gold, R H

1992-11-01

With the increasingly stringent standards of image quality in mammography, film processor quality control is especially important. Current methods are not sufficient for ensuring good processing. The authors used a sensitometer and densitometer system to evaluate the performance of 22 processors at 16 mammographic facilities. Standard sensitometric values of two films were established, and processor performance was assessed for variations from these standards. Developer chemistry of each processor was analyzed and correlated with its sensitometric values. Ten processors were retested, and nine were found to be out of calibration. The developer components of hydroquinone, sulfites, bromide, and alkalinity varied the most, and low concentrations of hydroquinone were associated with lower average gradients at two facilities. Use of the sensitometer and densitometer system helps identify out-of-calibration processors, but further study is needed to correlate sensitometric values with developer component values. The authors believe that present quality control would be improved if sensitometric or other tests could be used to identify developer components that are out of calibration.

Benchmarking NWP Kernels on Multi- and Many-core Processors

NASA Astrophysics Data System (ADS)

Michalakes, J.; Vachharajani, M.

2008-12-01

Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

NASA Astrophysics Data System (ADS)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Power processor for a 30cm ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.

1974-01-01

A thermal vacuum power processor for the NASA Lewis 30cm Mercury Ion Engine was designed, fabricated and tested to determine compliance with electrical specifications. The power processor breadboard used the silicon controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to an ion engine. The power processor includes a digital interface unit to process all input commands and internal telemetry signals so that operation is compatible with a central computer system. The breadboard was tested in a thermal vacuum environment. Integration tests were performed with the ion engine and demonstrate operational compatibility and reliable operation without any component failures. Electromagnetic interference data were also recorded on the design to provide information on the interaction with total spacecraft.

Fault detection and bypass in a sequence information signal processor

NASA Technical Reports Server (NTRS)

Peterson, John C. (Inventor); Chow, Edward T. (Inventor)

1992-01-01

The invention comprises a plurality of scan registers, each such register respectively associated with a processor element; an on-chip comparator, encoder and fault bypass register. Each scan register generates a unitary signal the logic state of which depends on the correctness of the input from the previous processor in the systolic array. These unitary signals are input to a common comparator which generates an output indicating whether or not an error has occurred. These unitary signals are also input to an encoder which identifies the location of any fault detected so that an appropriate multiplexer can be switched to bypass the faulty processor element. Input scan data can be readily programmed to fully exercise all of the processor elements so that no fault can remain undetected.

[Improving speech comprehension using a new cochlear implant speech processor].

PubMed

Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

2009-06-01

The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

A general natural-language text processor for clinical radiology.

PubMed Central

Friedman, C; Alderson, P O; Austin, J H; Cimino, J J; Johnson, S B

1994-01-01

OBJECTIVE: Development of a general natural-language processor that identifies clinical information in narrative reports and maps that information into a structured representation containing clinical terms. DESIGN: The natural-language processor provides three phases of processing, all of which are driven by different knowledge sources. The first phase performs the parsing. It identifies the structure of the text through use of a grammar that defines semantic patterns and a target form. The second phase, regularization, standardizes the terms in the initial target structure via a compositional mapping of multi-word phrases. The third phase, encoding, maps the terms to a controlled vocabulary. Radiology is the test domain for the processor and the target structure is a formal model for representing clinical information in that domain. MEASUREMENTS: The impression sections of 230 radiology reports were encoded by the processor. Results of an automated query of the resultant database for the occurrences of four diseases were compared with the analysis of a panel of three physicians to determine recall and precision. RESULTS: Without training specific to the four diseases, recall and precision of the system (combined effect of the processor and query generator) were 70% and 87%. Training of the query component increased recall to 85% without changing precision. PMID:7719797

ELIPS: Toward a Sensor Fusion Processor on a Chip

NASA Technical Reports Server (NTRS)

Daud, Taher; Stoica, Adrian; Tyson, Thomas; Li, Wei-te; Fabunmi, James

1998-01-01

The paper presents the concept and initial tests from the hardware implementation of a low-power, high-speed reconfigurable sensor fusion processor. The Extended Logic Intelligent Processing System (ELIPS) processor is developed to seamlessly combine rule-based systems, fuzzy logic, and neural networks to achieve parallel fusion of sensor in compact low power VLSI. The first demonstration of the ELIPS concept targets interceptor functionality; other applications, mainly in robotics and autonomous systems are considered for the future. The main assumption behind ELIPS is that fuzzy, rule-based and neural forms of computation can serve as the main primitives of an "intelligent" processor. Thus, in the same way classic processors are designed to optimize the hardware implementation of a set of fundamental operations, ELIPS is developed as an efficient implementation of computational intelligence primitives, and relies on a set of fuzzy set, fuzzy inference and neural modules, built in programmable analog hardware. The hardware programmability allows the processor to reconfigure into different machines, taking the most efficient hardware implementation during each phase of information processing. Following software demonstrations on several interceptor data, three important ELIPS building blocks (a fuzzy set preprocessor, a rule-based fuzzy system and a neural network) have been fabricated in analog VLSI hardware and demonstrated microsecond-processing times.

Miniature Fuel Processors for Portable Fuel Cell Power Supplies

DOE Office of Scientific and Technical Information (OSTI.GOV)

Holladay, Jamie D.; Jones, Evan O.; Palo, Daniel R.

2003-06-02

Miniature and micro-scale fuel processors are discussed. The enabling technologies for these devices are the novel catalysts and the micro-technology-based designs. The novel catalyst allows for methanol reforming at high gas hourly space velocities of 50,000 hr-1 or higher, while maintaining a carbon monoxide levels at 1% or less. The micro-technology-based designs enable the devices to be extremely compact and lightweight. The miniature fuel processors can nominally provide between 25-50 watts equivalent of hydrogen which is ample for soldier or personal portable power supplies. The integrated processors have a volume less than 50 cm3, a mass less than 150 grams,more » and thermal efficiencies of up to 83%. With reasonable assumptions on fuel cell efficiencies, anode gas and water management, parasitic power loss, etc., the energy density was estimated at 1700 Whr/kg. The miniature processors have been demonstrated with a carbon monoxide clean-up method and a fuel cell stack. The micro-scale fuel processors have been designed to provide up to 0.3 watt equivalent of power with efficiencies over 20%. They have a volume of less than 0.25 cm3 and a mass of less than 1 gram.« less

On nonlinear finite element analysis in single-, multi- and parallel-processors

NASA Technical Reports Server (NTRS)

Utku, S.; Melosh, R.; Islam, M.; Salama, M.

1982-01-01

Numerical solution of nonlinear equilibrium problems of structures by means of Newton-Raphson type iterations is reviewed. Each step of the iteration is shown to correspond to the solution of a linear problem, therefore the feasibility of the finite element method for nonlinear analysis is established. Organization and flow of data for various types of digital computers, such as single-processor/single-level memory, single-processor/two-level-memory, vector-processor/two-level-memory, and parallel-processors, with and without sub-structuring (i.e. partitioning) are given. The effect of the relative costs of computation, memory and data transfer on substructuring is shown. The idea of assigning comparable size substructures to parallel processors is exploited. Under Cholesky type factorization schemes, the efficiency of parallel processing is shown to decrease due to the occasional shared data, just as that due to the shared facilities.

Consumer acceptance of irradiated food: theory and reality

NASA Astrophysics Data System (ADS)

Bruhn, Christine M.

1998-06-01

For years most consumers have expressed less concern about food irradiation than other food processing technologies. Attitude studies have demonstrated that when given science-based information, from 60% to 90% of consumers prefer the advantages irradiation processing provides. When information is accompanied by samples, acceptance may increase to 99%. Information on irradiation should include product benefits, safety and wholesomeness, address environmental safety issues, and include endorsements by recognized health authorities. Educational and marketing programs should now be directed toward retailers and processors. Given the opportunity, consumers will buy high quality, safety-enhanced irradiated food.

Taking the cooking out of food: nutrition & the national curriculum.

PubMed

Stitt, S; Jepson, M; Paulson-Box, E

1995-01-01

This is a discussion paper which generates some important research questions for educationalists. The teaching of food skills are at danger of being lost from the school cirriculum by changes imposed by the National Curriculum. This sinister (i.e., unexplained/undefined) development generates potential problems for the teaching of cookery and for the food and eating traditions of British society. The central concern for nutrition educationalists is that cooking is becoming more and more de-domesticated and consequently will become more systemised, more mass produced; in which case, young people need not be educated in basic cooking skills.

Multibus-based parallel processor for simulation

NASA Technical Reports Server (NTRS)

Ogrady, E. P.; Wang, C.-H.

1983-01-01

A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

Meteorological Processors and Accessory Programs

EPA Pesticide Factsheets

Surface and upper air data, provided by NWS, are important inputs for air quality models. Before these data are used in some of the EPA dispersion models, meteorological processors are used to manipulate the data.

The Engineer Topographic Laboratories /ETL/ hybrid optical/digital image processor

NASA Astrophysics Data System (ADS)

Benton, J. R.; Corbett, F.; Tuft, R.

1980-01-01

An optical-digital processor for generalized image enhancement and filtering is described. The optical subsystem is a two-PROM Fourier filter processor. Input imagery is isolated, scaled, and imaged onto the first PROM; this input plane acts like a liquid gate and serves as an incoherent-to-coherent converter. The image is transformed onto a second PROM which also serves as a filter medium; filters are written onto the second PROM with a laser scanner in real time. A solid state CCTV camera records the filtered image, which is then digitized and stored in a digital image processor. The operator can then manipulate the filtered image using the gray scale and color remapping capabilities of the video processor as well as the digital processing capabilities of the minicomputer.

A word processor optimized for preparing journal articles and student papers.

PubMed

Wolach, A H; McHale, M A

2001-11-01

A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

78 FR 4346 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-01-22

.../Processors Using Trawl Gear in the Western Regulatory Area of the Gulf of Alaska AGENCY: National Marine... (C/Ps) using trawl gear in the Western Regulatory Area of the Gulf of Alaska (GOA). This action is... apportioned to C/Ps using trawl gear in the Western Regulatory Area of the GOA. DATES: Effective 1200 hours...

78 FR 23683 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-04-22

... Catcher/Processors Using Trawl Gear in the Central Regulatory Area of the Gulf of Alaska AGENCY: National... (C/Ps) using trawl gear in the Central Regulatory Area of the Gulf of Alaska (GOA). This action is... apportioned to C/Ps using trawl gear in the Central Regulatory Area of the GOA. DATES: Effective 1200 hours...

77 FR 9589 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-02-17

.../Processors Using Trawl Gear in the Western Regulatory Area of the Gulf of Alaska AGENCY: National Marine... (C/Ps) using trawl gear in the Western Regulatory Area of the Gulf of Alaska (GOA). This action is... apportioned to C/Ps using trawl gear in the Western Regulatory Area of the GOA. DATES: Effective 1200 hrs...

78 FR 54592 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-09-05

... Catcher/Processors Using Trawl Gear in the Central Regulatory Area of the Gulf of Alaska AGENCY: National... (C/Ps) using trawl gear in the Central Regulatory Area of the Gulf of Alaska (GOA). This action is... gear in the Central Regulatory Area of the GOA. DATES: Effective 1200 hours, Alaska local time (A.l.t...

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

Ethernet-Enabled Power and Communication Module for Embedded Processors

NASA Technical Reports Server (NTRS)

Perotti, Jose; Oostdyk, Rebecca

2010-01-01

The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

77 FR 19525 - National School Lunch Program: School Food Service Account Revenue Amendments Related to the...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-04-02

... National School Lunch Program: School Food Service Account Revenue Amendments Related to the Healthy, Hunger-Free Kids Act of 2010; Approval of Information Collection Request AGENCY: Food and Nutrition Service, USDA. ACTION: Interim final rule; approval of information collection request. SUMMARY: The Food...

Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

NASA Astrophysics Data System (ADS)

Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

2018-02-01

We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, G. H.

1985-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90 percent for sufficiently large problems.

Finite elements and the method of conjugate gradients on a concurrent processor

NASA Technical Reports Server (NTRS)

Lyzenga, G. A.; Raefsky, A.; Hager, B. H.

1984-01-01

An algorithm for the iterative solution of finite element problems on a concurrent processor is presented. The method of conjugate gradients is used to solve the system of matrix equations, which is distributed among the processors of a MIMD computer according to an element-based spatial decomposition. This algorithm is implemented in a two-dimensional elastostatics program on the Caltech Hypercube concurrent processor. The results of tests on up to 32 processors show nearly linear concurrent speedup, with efficiencies over 90% for sufficiently large problems.

Extended performance electric propulsion power processor design study. Volume 1: Executive summary

NASA Technical Reports Server (NTRS)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30cm ion thruster power processor with a beam supply rating of 2.2kW to 10kW. Extensions in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. Preliminary electrical design, mechanical design, and thermal analysis were performed on a 6kW power transformer for the beam supply. Bi-Mod mechanical, structural, and thermal control configurations were evaluated for the power processor, and preliminary estimates of mechanical weight were determined. A program development plan was formulated that outlines the work breakdown structure for the development, qualification and fabrication of the power processor flight hardware.

Conditions for space invariance in optical data processors used with coherent or noncoherent light.

PubMed

Arsenault, H R

1972-10-01

The conditions for space invariance in coherent and noncoherent optical processors are considered. All linear optical processors are shown to belong to one of two types. The conditions for space invariance are more stringent for noncoherent processors than for coherent processors, so that a system that is linear in coherent light may be nonlinear in noncoherent light. However, any processor that is linear in noncoherent light is also linear in the coherent limit.

Food safety considerations for innovative nutrition solutions.

PubMed

Byrd-Bredbenner, Carol; Cohn, Marjorie Nolan; Farber, Jeffrey M; Harris, Linda J; Roberts, Tanya; Salin, Victoria; Singh, Manpreet; Jaferi, Azra; Sperber, William H

2015-07-01

Failure to secure safe and affordable food to the growing global population leads far too often to disastrous consequences. Among specialists and other individuals, food scientists have a key responsibility to improve and use science-based tools to address risk and advise food handlers and manufacturers with best-practice recommendations. With collaboration from production agriculture, food processors, state and federal agencies, and consumers, it is critical to implement science-based strategies that address food safety and that have been evaluated for effectiveness in controlling and/or eliminating hazards. It is an open question whether future food safety concerns will shift in priority given the imperatives to supply sufficient food. This report brings together leading food safety experts to address these issues with a focus on three areas: economic, social, and policy aspects of food safety; production and postharvest technology for safe food; and innovative public communication for food safety and nutrition. © 2015 New York Academy of Sciences.

Seasonal Difference in National School Lunch Program Participation and Its Impacts on Household Food Security.

PubMed

Huang, Jin; Kim, Youngmi; Barnidge, Ellen

2016-11-20

The National School Lunch Program (NSLP) is one of the most important food assistance programs in the United States to ensure children's food security and healthy development. Previous studies have offered mixed results and challenges in estimating the effects of program participation. This study assesses NSLP's effect on household food security using data from the Survey of Income and Program Participation (SIPP). SIPP collects information on food security that covers four reference months, including both summer (June, July, August) and nonsummer months. The number of summer months in these four reference months varies by SIPP rotation group. These unique features allow this study to address the potential selection bias in the research of NSLP and food security by examining a seasonal difference in program participation. The analysis found that one more summer month in the reference period increases the difference in low food security rates by about 1.5 percentage points between recipients and nonrecipients eligible for free or reduced-price lunch. Findings have important social work and health policy implications for increasing food security among low-income households with children. © 2016 National Association of Social Workers.

Accuracy of the lattice-Boltzmann method using the Cell processor

NASA Astrophysics Data System (ADS)

Harvey, M. J.; de Fabritiis, G.; Giupponi, G.

2008-11-01

Accelerator processors like the new Cell processor are extending the traditional platforms for scientific computation, allowing orders of magnitude more floating-point operations per second (flops) compared to standard central processing units. However, they currently lack double-precision support and support for some IEEE 754 capabilities. In this work, we develop a lattice-Boltzmann (LB) code to run on the Cell processor and test the accuracy of this lattice method on this platform. We run tests for different flow topologies, boundary conditions, and Reynolds numbers in the range Re=6 350 . In one case, simulation results show a reduced mass and momentum conservation compared to an equivalent double-precision LB implementation. All other cases demonstrate the utility of the Cell processor for fluid dynamics simulations. Benchmarks on two Cell-based platforms are performed, the Sony Playstation3 and the QS20/QS21 IBM blade, obtaining a speed-up factor of 7 and 21, respectively, compared to the original PC version of the code, and a conservative sustained performance of 28 gigaflops per single Cell processor. Our results suggest that choice of IEEE 754 rounding mode is possibly as important as double-precision support for this specific scientific application.

Potential of minicomputer/array-processor system for nonlinear finite-element analysis

NASA Technical Reports Server (NTRS)

Strohkorb, G. A.; Noor, A. K.

1983-01-01

The potential of using a minicomputer/array-processor system for the efficient solution of large-scale, nonlinear, finite-element problems is studied. A Prime 750 is used as the host computer, and a software simulator residing on the Prime is employed to assess the performance of the Floating Point Systems AP-120B array processor. Major hardware characteristics of the system such as virtual memory and parallel and pipeline processing are reviewed, and the interplay between various hardware components is examined. Effective use of the minicomputer/array-processor system for nonlinear analysis requires the following: (1) proper selection of the computational procedure and the capability to vectorize the numerical algorithms; (2) reduction of input-output operations; and (3) overlapping host and array-processor operations. A detailed discussion is given of techniques to accomplish each of these tasks. Two benchmark problems with 1715 and 3230 degrees of freedom, respectively, are selected to measure the anticipated gain in speed obtained by using the proposed algorithms on the array processor.

Scheduling time-critical graphics on multiple processors

NASA Technical Reports Server (NTRS)

Meyer, Tom W.; Hughes, John F.

1995-01-01

This paper describes an algorithm for the scheduling of time-critical rendering and computation tasks on single- and multiple-processor architectures, with minimal pipelining. It was developed to manage scientific visualization scenes consisting of hundreds of objects, each of which can be computed and displayed at thousands of possible resolution levels. The algorithm generates the time-critical schedule using progressive-refinement techniques; it always returns a feasible schedule and, when allowed to run to completion, produces a near-optimal schedule which takes advantage of almost the entire multiple-processor system.

Food Insecurity and Mental Disorders in a National Sample of U.S. Adolescents

ERIC Educational Resources Information Center

McLaughlin, Katie A.; Green, Jennifer Greif; Alegria, Margarita; Costello, E. Jane; Gruber, Michael J.; Sampson, Nancy A.; Kessler, Ronald C.

2012-01-01

Objective: To examine whether food insecurity is associated with past-year "DSM-IV" mental disorders after controlling for standard indicators of family socioeconomic status (SES) in a U.S. national sample of adolescents. Method: Data were drawn from 6,483 adolescent-parent pairs who participated in the National Comorbidity Survey Replication…

SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

ERIC Educational Resources Information Center

Moyer, Ruth A.

Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

Software for embedded processors: Problems and solutions

NASA Astrophysics Data System (ADS)

Bogaerts, J. A. C.

1990-08-01

Data Acquistion systems in HEP experiments use a wide spectrum of computers to cope with two major problems: high event rates and a large data volume. They do this by using special fast trigger processors at the source to reduce the event rate by several orders of magnitude. The next stage of a data acquisition system consists of a network of fast but conventional microprocessors which are embedded in high speed bus systems where data is still further reduced, filtered and merged. In the final stage complete events are farmed out to a another collection of processors, which reconstruct the events and perhaps achieve a further event rejection by a small factor, prior to recording onto magnetic tape. Detectors are monitored by analyzing a fraction of the data. This may be done for individual detectors at an early state of the data acquisition or it may be delayed till the complete events are available. A network of workstations is used for monitoring, displays and run control. Software for trigger processors must have a simple structure. Rejection algorithms are carefully optimized, and overheads introduced by system software cannot be tolerated. The embedded microprocessors have to co-operate, and need to be synchronized with the preceding and following stages. Real time kernels are typically used to solve synchronization and communication problems. Applications are usually coded in C, which is reasonably efficient and allows direct control over low level hardware functions. Event reconstruction software is very similar or even identical to offline software, predominantly written in FORTRAN. With the advent of powerful RISC processors, and with manufacturers tending to adopt open bus architectures, there is a move towards commercial processors and hence the introduction of the UNIX operating system. Building and controlling such a heterogeneous data acquisition system puts a heavy strain on the software. Communications is now as important as CPU capacity and I

A National Study of the Association between Food Environments and County-Level Health Outcomes

ERIC Educational Resources Information Center

Ahern, Melissa; Brown, Cheryl; Dukas, Stephen

2011-01-01

Purpose: This national, county-level study examines the relationship between food availability and access, and health outcomes (mortality, diabetes, and obesity rates) in both metro and non-metro areas. Methods: This is a secondary, cross-sectional analysis using Food Environment Atlas and CDC data. Linear regression models estimate relationships…

First Results of an “Artificial Retina” Processor Prototype

DOE PAGES

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; ...

2016-11-15

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. Also, the prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHzmore » crossing rate.« less

First Results of an “Artificial Retina” Processor Prototype

DOE Office of Scientific and Technical Information (OSTI.GOV)

Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro

We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. Also, the prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHzmore » crossing rate.« less

Retail food environments, shopping experiences, First Nations and the provincial Norths.

PubMed

Burnett, Kristin; Skinner, Kelly; Hay, Travis; LeBlanc, Joseph; Chambers, Lori

2017-10-01

This paper looks at the market food environments of First Nations communities located in the provincial Norths by examining the potential retail competition faced by the North West Company (NWC) and by reporting on the grocery shopping experiences of people living in northern Canada. We employed two methodological approaches to assess northern retail food environments. First, we mapped food retailers in the North to examine the breadth of retail competition in the provincial Norths, focussing specifically on those communities without year-round road access. Second, we surveyed people living in communities in northern Canada about their retail and shopping experiences. Fifty-four percent of communities in the provincial Norths and Far North without year-round road access did not have a grocery store that competed with the NWC. The provinces with the highest percentage of northern communities without retail competition were Ontario (87%), Saskatchewan (83%) and Manitoba (72%). Respondents to the survey (n = 92) expressed concern about their shopping experiences in three main areas: the cost of food, food quality and freshness, and availability of specific foods. There is limited retail competition in the provincial Norths. In Manitoba, Saskatchewan and Ontario, the NWC has no store competition in at least 70% of northern communities. Consumers living in northern Canada find it difficult to afford nutritious foods and would like access to a wider selection of perishable foods in good condition.

Efficient Parallel Algorithms on Restartable Fail-Stop Processors

DTIC Science & Technology

1991-01-01

resource (memory), and ( 3 ) that processors, memory and their interconnection must be The model of parallel computation known as the Par- perfectly...setting), arid ure an(I restart errors. We describe these arguments if] [AAtPS 871 (in a deterministic setting). Fault-tolerance Section 3 . of...grannmarity at the processor level --- for recent work on where Al is the nmber of failures during this step’s gate granilarities see [All 90, Pip 85

A Simple and Affordable TTL Processor for the Classroom

ERIC Educational Resources Information Center

Feinberg, Dave

2007-01-01

This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

Interactive Digital Signal Processor

NASA Technical Reports Server (NTRS)

Mish, W. H.

1985-01-01

Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.

Computer program documentation for the pasture/range condition assessment processor

NASA Technical Reports Server (NTRS)

Mcintyre, K. S.; Miller, T. G. (Principal Investigator)

1982-01-01

The processor which drives for the RANGE software allows the user to analyze LANDSAT data containing pasture and rangeland. Analysis includes mapping, generating statistics, calculating vegetative indexes, and plotting vegetative indexes. Routines for using the processor are given. A flow diagram is included.

Safe and Efficient Support for Embeded Multi-Processors in ADA

NASA Astrophysics Data System (ADS)

Ruiz, Jose F.

2010-08-01

New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 8 2012-01-01 2012-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements and Orders; Fruits, Vegetables, Nuts), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 8 2013-01-01 2013-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS AND ORDERS; FRUITS, VEGETABLES, NUTS), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2010 CFR

2010-01-01

... 7 Agriculture 8 2010-01-01 2010-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements and Orders; Fruits, Vegetables, Nuts), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 8 2014-01-01 2014-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS AND ORDERS; FRUITS, VEGETABLES, NUTS), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

7 CFR 989.13 - Processor.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 8 2011-01-01 2011-01-01 false Processor. 989.13 Section 989.13 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (Marketing Agreements and Orders; Fruits, Vegetables, Nuts), DEPARTMENT OF AGRICULTURE RAISINS PRODUCED FROM GRAPES GROWN IN...

Neighborhood deprivation and access to fast-food retailing: a national study.

PubMed

Pearce, Jamie; Blakely, Tony; Witten, Karen; Bartie, Phil

2007-05-01

Obesogenic environments may be an important contextual explanation for the growing obesity epidemic, including its unequal social distribution. The objective of this study was to determine whether geographic access to fast-food outlets varied by neighborhood deprivation and school socioeconomic ranking, and whether any such associations differed to those for access to healthier food outlets. Data were collected on the location of fast-food outlets, supermarkets, and convenience stores across New Zealand. The data were geocoded and geographic information systems used to calculate travel distances from each census meshblock (i.e., neighborhood), and each school, to the closest fast-food outlet. Median travel distances are reported by a census-based index of socioeconomic deprivation for each neighborhood, and by a Ministry of Education measure of socioeconomic circumstances for each school. Analyses were repeated for outlets selling healthy food to allow comparisons. At the national level, statistically significant negative associations were found between neighborhood access to the nearest fast-food outlet and neighborhood deprivation (p<0.001) for both multinational fast-food outlets and locally operated outlets. The travel distances to both types of fast food outlet were at least twice as far in the least socially deprived neighborhoods compared to the most deprived neighborhoods. A similar pattern was found for outlets selling healthy food such as supermarkets and smaller food outlets (p<0.001). These relationships were broadly linear with travel distances tending to be shorter in more-deprived neighborhoods. There is a strong association between neighborhood deprivation and geographic access to fast food outlets in New Zealand, which may contribute to the understanding of environmental causes of obesity. However, outlets potentially selling healthy food (e.g., supermarkets) are patterned by deprivation in a similar way. These findings highlight the importance of

75 FR 7403 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook...

Federal Register 2010, 2011, 2012, 2013, 2014

2010-02-19

.... 0810141351-9087-02] RIN 0648-XU36 Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook-and-Line Gear in the Bering Sea and Aleutian Islands Management Area AGENCY: National... using hook-and-line gear in the Bering Sea and Aleutian Islands management area (BSAI). This action is...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2013 CFR

2013-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2014 CFR

2014-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2012 CFR

2012-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2010 CFR

2010-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

7 CFR 1435.306 - Allocation of marketing allotments to processors.

Code of Federal Regulations, 2011 CFR

2011-01-01

...) COMMODITY CREDIT CORPORATION, DEPARTMENT OF AGRICULTURE LOANS, PURCHASES, AND OTHER OPERATIONS SUGAR PROGRAM Flexible Marketing Allotments For Sugar § 1435.306 Allocation of marketing allotments to processors. (a) Each sugar beet processor's allocation, other than a new entrant's, of the beet allotment will be...

Target salt 2025: a global overview of national programs to encourage the food industry to reduce salt in foods.

PubMed

Webster, Jacqui; Trieu, Kathy; Dunford, Elizabeth; Hawkes, Corinna

2014-08-21

Reducing population salt intake has been identified as a priority intervention to reduce non-communicable diseases. Member States of the World Health Organization have agreed to a global target of a 30% reduction in salt intake by 2025. In countries where most salt consumed is from processed foods, programs to engage the food industry to reduce salt in products are being developed. This paper provides a comprehensive overview of national initiatives to encourage the food industry to reduce salt. A systematic review of the literature was supplemented by key informant questionnaires to inform categorization of the initiatives. Fifty nine food industry salt reduction programs were identified. Thirty eight countries had targets for salt levels in foods and nine countries had introduced legislation for some products. South Africa and Argentina have both introduced legislation limiting salt levels across a broad range of foods. Seventeen countries reported reductions in salt levels in foods-the majority in bread. While these trends represent progress, many countries have yet to initiate work in this area, others are at early stages of implementation and further monitoring is required to assess progress towards achieving the global target.

A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

NASA Astrophysics Data System (ADS)

Veiga, Alejandro; Grunfeld, Christian

2016-02-01

The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

76 FR 76874 - Implementation of Regulations Required Under Title XI of the Food, Conservation and Energy Act of...

Federal Register 2010, 2011, 2012, 2013, 2014

2011-12-09

..., including those that could improve food safety. Although there were many comments received in favor of this... agreement if the grower failed to comply with the processor's internal food safety or animal welfare... reputations if required to allow a grower to operate following a breach involving food safety or animal...

A distributed fault-tolerant signal processor /FTSP/

NASA Astrophysics Data System (ADS)

Bonneau, R. J.; Evett, R. C.; Young, M. J.

1980-01-01

A digital fault-tolerant signal processor (FTSP), an example of a self-repairing programmable system is analyzed. The design configuration is discussed in terms of fault tolerance, system-level fault detection, isolation and common memory. Special attention is given to the FDIR (fault detection isolation and reconfiguration) logic, noting that the reconfiguration decisions are based on configuration, summary status, end-around tests, and north marker/synchro data. Several mechanisms of fault detection are described which initiate reconfiguration at different levels. It is concluded that the reliability of a signal processor can be significantly enhanced by the use of fault-tolerant techniques.

An innovative on-board processor for lightsats

NASA Technical Reports Server (NTRS)

Henshaw, R. M.; Ballard, B. W.; Hayes, J. R.; Lohr, D. A.

1990-01-01

The Applied Physics Laboratory (APL) has developed a flightworthy custom microprocessor that increases capability and reduces development costs of lightsat science instruments. This device, called the FRISC (FORTH Reduced Instruction Set Computer), directly executes the high-level language called FORTH, which is ideally suited to the multitasking control and data processing environment of a spaceborne instrument processor. The FRISC will be flown as the onboard processor in the Magnetic Field Experiment on the Freja satllite. APL has achieved a significant increase in onboard processing capability with no increase in cost when compared to the magnetometer instrument on Freja's predecessor, the Viking satellite.

Spaceborne Processor Array

NASA Technical Reports Server (NTRS)

Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

2008-01-01

A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

Timing of Introduction of Complementary Foods to US Infants, National Health and Nutrition Examination Survey 2009-2014.

PubMed

Barrera, Chloe M; Hamner, Heather C; Perrine, Cria G; Scanlon, Kelley S

2018-03-01

Although there has been inconsistency in recommendations regarding the optimal time for introducing complementary foods, most experts agree that introduction should not occur before 4 months. Despite recommendations, studies suggest that 20% to 40% of US infants are introduced to foods at younger than 4 months. Previous studies focused on the introduction of solid foods and are not nationally representative. Our aims were to provide a nationally representative estimate of the timing of introduction of complementary foods and to describe predictors of early (<4 months) introduction. We conducted a cross-sectional analysis of 2009-2014 National Health and Nutrition Examination Survey data. The study included 1,482 children aged 6 to 36 months. Timing of first introduction to complementary foods (anything other than breast milk or formula) was analyzed. Prevalence estimates of first introduction to complementary foods are presented by month. Logistic regression was used to assess characteristics associated with early (<4 months) introduction. In this sample, 16.3% of US infants were introduced to complementary foods at <4 months, 38.3% between 4 and <6 months, 32.5% between 6 and <7 months, and 12.9% at ≥7 months of age. In unadjusted analyses, early introduction varied by breastfeeding status; race/Hispanic origin; Special Supplemental Nutrition Program for Women, Infants, and Children participation; and maternal age. In adjusted analyses, only breastfeeding status remained significant; infants who never breastfed or stopped at <4 months were more likely (odds ratio 2.27; 95% CI 1.62 to 3.18) to be introduced to complementary foods early than infants who breastfed ≥4 months. Despite using a broader definition of complementary foods, this analysis found a lower prevalence of early introduction in this nationally representative sample than previous studies that included only solids. However, many young children were still introduced to complementary foods earlier

Backend Control Processor for a Multi-Processor Relational Database Computer System.

DTIC Science & Technology

1984-12-01

SCHOOL OF ENGI. UNCRSIFID MPONTIFF DEC 84 AFXT/GCS/ENG/84D-22 F/O 9/2 L ommhhhhmhhml mhhhommhhhhhm i-2 8 -- U0. 11111= Q. 2 111.8IIII- 1111111..6...THESIS Presented to the Faculty of the School of Engineering of the Air Force Institute of Technology Air University In Partial Fulfillment of the...development of a Backend Multi-Processor Relational Database Computer System. This thesis addresses a single component of this system, the Backend Control

The national employment guarantee scheme and inequities in household spending on food and non-food determinants of health in rural India.

PubMed

Dilip, T R; Dandona, Rakhi; Dandona, Lalit

2013-10-15

Inequities in a population in spending on food and non-food items can contribute to disparities in health status. The Mahatma Gandhi National Rural Employment Guarantee Scheme (MGNREGS) was launched in rural India in 2006, aimed at providing at least 100 days of manual work to a member in needy households. We used nationally representative data from the consumer expenditure surveys of 2004-05 and 2009-10 and the employment survey of 2009-10 conducted by National Sample Survey Organisation to assess the effect of MGNREGS in reducing inequities in consumption of food and non-food items between poor and non-poor households in the states of India. Variations among the states in implementation of MGNREGS were examined using the employment and unemployment survey data, and compared with official programme data up to 2012-13. Inequity in spending on food and non-food items was assessed using the ratio of monthly per capita consumer expenditure (MPCE) between the most vulnerable (labourer) and least vulnerable categories of households. The survey data suggested 1.42 billion person-days of MGNRGES employment in the 2009-10 financial year, whereas the official programme data reported 2.84 billion person-days. According to the official data, the person-days of MGNRGES employment decreased by 43.3% from 2009-10 to 2012-13 for the 9 large less developed states of India. Survey data revealed that the average number of MGNREGS work days in a year per household varied from 42 days in Rajasthan to less than 10 days in 14 of the 20 major states in India in 2009-10. Rajasthan with the highest implementation of MGNRGES among the 9 less developed states of India had the highest relative decline of 10.4% in the food spending inequity from 2004-05 to 2009-10 between the most vulnerable and less vulnerable households. The changes in inequity for non-food spending did not have any particular pattern across the less developed states. In the most vulnerable category, the households in

A national study of the association between food environments and county-level health outcomes.

PubMed

Ahern, Melissa; Brown, Cheryl; Dukas, Stephen

2011-01-01

This national, county-level study examines the relationship between food availability and access, and health outcomes (mortality, diabetes, and obesity rates) in both metro and non-metro areas. This is a secondary, cross-sectional analysis using Food Environment Atlas and CDC data. Linear regression models estimate relationships between food availability and access variables (direct-to-consumer farm sales, per capita grocery stores, full-service restaurants, fast food restaurants, and convenience stores) with health outcomes. Controls include smoking, race/ethnicity, gender, age, education, poverty, primary care availability, recreational facility availability, and mobility/distance-from-grocery-store. Non-metro findings: Lower adjusted mortality rates were associated with more per capita full-service restaurants and grocery stores, and greater per capita direct farm sales. Lower adjusted diabetes rates were associated with a lower per capita supply of fast food restaurants and convenience stores, and more per capita full-service restaurants and grocery stores. Lower adjusted obesity rates were associated with more per capita full-service restaurants and grocery stores. Unexpectedly, obesity rates were positively associated with per capita grocery stores and negatively associated with fast food restaurants. Metro findings: More per capita full-service restaurants, grocery stores, and direct farm sales are associated with positive health outcomes; fast food restaurants and convenience stores are associated with negative health outcomes. The food access/availability environment is an important determinant of health outcomes in metro and non-metro areas. Future research should focus on more refined specifications that capture variability across non-metro settings. © 2011 National Rural Health Association.

Aligning food-processing policies to promote healthier fat consumption in India

PubMed Central

Downs, Shauna M.; Marie Thow, Anne; Ghosh-Jerath, Suparna; Leeder, Stephen R.

2015-01-01

India is undergoing a shift in consumption from traditional foods to processed foods high in sugar, salt and fat. Partially hydrogenated vegetable oils (PHVOs) high in trans-fat are often used in processed foods in India given their low cost and extended shelf life. The World Health Organization has called for the elimination of PHVOs from the global food supply and recommends their replacement with polyunsaturated fat to maximize health benefits. This study examined barriers to replacing industrially produced trans-fat in the Indian food supply and systematically identified potential policy solutions to assist the government in encouraging its removal and replacement with healthier polyunsaturated fat. A combination of food supply chain analysis and semi-structured interviews with key stakeholders was conducted. The main barriers faced by the food-processing sector in terms of reducing use of trans-fat and replacing it with healthier oils in India were the low availability and high cost of oils high in polyunsaturated fats leading to a reliance on palm oil (high in saturated fat) and the low use of those healthier oils in product reformulation. Improved integration between farmers and processors, investment in technology and pricing strategies to incentivize use of healthier oils for product reformulation were identified as policy options. Food processors have trouble accessing sufficient affordable healthy oils for product reformulation, but existing incentives aimed at supporting food processing could be tweaked to ensure a greater supply of healthy oils with the potential to improve population health. PMID:24399031

Self-checking self-repairing computer nodes using the mirror processor

NASA Technical Reports Server (NTRS)

Tamir, Yuval

1992-01-01

Circuitry added to fault-tolerant systems for concurrent error deduction usually reduces performance. Using a technique called micro rollback, it is possible to eliminate most of the performance penalty of concurrent error detection. Error detection is performed in parallel with intermodule communication, and erroneous state changes are later undone. The author reports on the design and implementation of a VLSI RISC microprocessor, called the Mirror Processor (MP), which is capable of micro rollback. In order to achieve concurrent error detection, two MP chips operate in lockstep, comparing external signals and a signature of internal signals every clock cycle. If a mismatch is detected, both processors roll back to the beginning of the cycle when the error occurred. In some cases the erroneous state is corrected by copying a value from the fault-free processor to the faulty processor. The architecture, microarchitecture, and VLSI implementation of the MP, emphasizing its error-detection, error-recovery, and self-diagnosis capabilities, are described.

Mechanically verified hardware implementing an 8-bit parallel IO Byzantine agreement processor

NASA Technical Reports Server (NTRS)

Moore, J. Strother

1992-01-01

Consider a network of four processors that use the Oral Messages (Byzantine Generals) Algorithm of Pease, Shostak, and Lamport to achieve agreement in the presence of faults. Bevier and Young have published a functional description of a single processor that, when interconnected appropriately with three identical others, implements this network under the assumption that the four processors step in synchrony. By formalizing the original Pease, et al work, Bevier and Young mechanically proved that such a network achieves fault tolerance. We develop, formalize, and discuss a hardware design that has been mechanically proven to implement their processor. In particular, we formally define mapping functions from the abstract state space of the Bevier-Young processor to a concrete state space of a hardware module and state a theorem that expresses the claim that the hardware correctly implements the processor. We briefly discuss the Brock-Hunt Formal Hardware Description Language which permits designs both to be proved correct with the Boyer-Moore theorem prover and to be expressed in a commercially supported hardware description language for additional electrical analysis and layout. We briefly describe our implementation.

Healthful Nutrition of Foods in Navajo Nation Stores: Availability and Pricing.

PubMed

Kumar, Gayathri; Jim-Martin, Sonlatsa; Piltch, Emily; Onufrak, Stephen; McNeil, Carrie; Adams, Laura; Williams, Nancy; Blanck, Heidi M; Curley, Larry

2016-09-01

Low availability and affordability of healthier foods in food stores on the Navajo Nation (NN) may be a community-level risk factor for the high prevalence of obesity among the Navajo people. This study assessed the availability and pricing of foods and beverages in supermarkets and convenience stores throughout the NN. Descriptive study design using the Nutrition Environment Measurement Survey in Stores audit tool. Supermarkets (n = 13) and convenience stores (n = 50) on NN and border-town supermarkets (n = 9). Not applicable. Availability and pricing of healthy and less-healthy foods. Descriptive and χ(2) analyses. Navajo convenience stores offered fewer healthier food options compared to Navajo supermarkets. In Navajo convenience stores, 100% whole grain products, reduced-fat cheese, lean meats, reduced-fat chips, and fat-free or light hot dogs were available in fewer stores than their corresponding less-healthy versions (all with p < .05). In both Navajo supermarkets and convenience stores, 100% whole wheat bread, lean cold cuts, and reduced-fat cheese were all more expensive per unit than their corresponding less-healthy versions (all with p < .05). According to this study, healthier foods are not as readily available in Navajo convenience stores as they are in Navajo supermarkets. Improving access to and affordability of healthier foods in reservation stores of all sizes may support healthy eating among Navajo residents. © 2016 by American Journal of Health Promotion, Inc.

7 CFR 2.66 - Director, National Institute of Food and Agriculture.

Code of Federal Regulations, 2012 CFR

2012-01-01

... 7 Agriculture 1 2012-01-01 2012-01-01 false Director, National Institute of Food and Agriculture. 2.66 Section 2.66 Agriculture Office of the Secretary of Agriculture DELEGATIONS OF AUTHORITY BY THE SECRETARY OF AGRICULTURE AND GENERAL OFFICERS OF THE DEPARTMENT Delegations of Authority by the Under...

7 CFR 2.66 - Director, National Institute of Food and Agriculture.

Code of Federal Regulations, 2013 CFR

2013-01-01

... 7 Agriculture 1 2013-01-01 2013-01-01 false Director, National Institute of Food and Agriculture. 2.66 Section 2.66 Agriculture Office of the Secretary of Agriculture DELEGATIONS OF AUTHORITY BY THE SECRETARY OF AGRICULTURE AND GENERAL OFFICERS OF THE DEPARTMENT Delegations of Authority by the Under...

7 CFR 2.66 - Director, National Institute of Food and Agriculture.

Code of Federal Regulations, 2011 CFR

2011-01-01

... 7 Agriculture 1 2011-01-01 2011-01-01 false Director, National Institute of Food and Agriculture. 2.66 Section 2.66 Agriculture Office of the Secretary of Agriculture DELEGATIONS OF AUTHORITY BY THE SECRETARY OF AGRICULTURE AND GENERAL OFFICERS OF THE DEPARTMENT Delegations of Authority by the Under...

7 CFR 2.66 - Director, National Institute of Food and Agriculture.

Code of Federal Regulations, 2014 CFR

2014-01-01

... 7 Agriculture 1 2014-01-01 2014-01-01 false Director, National Institute of Food and Agriculture. 2.66 Section 2.66 Agriculture Office of the Secretary of Agriculture DELEGATIONS OF AUTHORITY BY THE SECRETARY OF AGRICULTURE AND GENERAL OFFICERS OF THE DEPARTMENT Delegations of Authority by the Under...

Retail food environments, shopping experiences, First Nations and the provincial Norths

PubMed Central

Kristin, Burnett; Kelly, Skinner; Travis, Hay; Joseph, LeBlanc; Lori, Chambers

2017-01-01

Abstract Introduction: This paper looks at the market food environments of First Nations communities located in the provincial Norths by examining the potential retail competition faced by the North West Company (NWC) and by reporting on the grocery shopping experiences of people living in northern Canada. Methods: We employed two methodological approaches to assess northern retail food environments. First, we mapped food retailers in the North to examine the breadth of retail competition in the provincial Norths, focussing specifically on those communities without year-round road access. Second, we surveyed people living in communities in northern Canada about their retail and shopping experiences. Results: Fifty-four percent of communities in the provincial Norths and Far North without year-round road access did not have a grocery store that competed with the NWC. The provinces with the highest percentage of northern communities without retail competition were Ontario (87%), Saskatchewan (83%) and Manitoba (72%). Respondents to the survey (n = 92) expressed concern about their shopping experiences in three main areas: the cost of food, food quality and freshness, and availability of specific foods. Conclusion: There is limited retail competition in the provincial Norths. In Manitoba, Saskatchewan and Ontario, the NWC has no store competition in at least 70% of northern communities. Consumers living in northern Canada find it difficult to afford nutritious foods and would like access to a wider selection of perishable foods in good condition. PMID:29043760

77 FR 11776 - Fisheries of the Exclusive Economic Zone Off Alaska; Pacific Cod by Catcher/Processors Using Hook...

Federal Register 2010, 2011, 2012, 2013, 2014

2012-02-28

.../Processors Using Hook-and-Line Gear in the Central Regulatory Area of the Gulf of Alaska AGENCY: National... (C/Ps) using hook-and-line gear in the Central Regulatory Area of the Gulf of Alaska (GOA). This... catch apportioned to C/Ps using hook-and-line gear in the Central Regulatory Area of the GOA. DATES...

The ATLAS Level-1 Calorimeter Trigger: PreProcessor implementation and performance

NASA Astrophysics Data System (ADS)

Åsman, B.; Achenbach, R.; Allbrooke, B. M. M.; Anders, G.; Andrei, V.; Büscher, V.; Bansil, H. S.; Barnett, B. M.; Bauss, B.; Bendtz, K.; Bohm, C.; Bracinik, J.; Brawn, I. P.; Brock, R.; Buttinger, W.; Caputo, R.; Caughron, S.; Cerrito, L.; Charlton, D. G.; Childers, J. T.; Curtis, C. J.; Daniells, A. C.; Davis, A. O.; Davygora, Y.; Dorn, M.; Eckweiler, S.; Edmunds, D.; Edwards, J. P.; Eisenhandler, E.; Ellis, K.; Ermoline, Y.; Föhlisch, F.; Faulkner, P. J. W.; Fedorko, W.; Fleckner, J.; French, S. T.; Gee, C. N. P.; Gillman, A. R.; Goeringer, C.; Hülsing, T.; Hadley, D. R.; Hanke, P.; Hauser, R.; Heim, S.; Hellman, S.; Hickling, R. S.; Hidvégi, A.; Hillier, S. J.; Hofmann, J. I.; Hristova, I.; Ji, W.; Johansen, M.; Keller, M.; Khomich, A.; Kluge, E.-E.; Koll, J.; Laier, H.; Landon, M. P. J.; Lang, V. S.; Laurens, P.; Lepold, F.; Lilley, J. N.; Linnemann, J. T.; Müller, F.; Müller, T.; Mahboubi, K.; Martin, T. A.; Mass, A.; Meier, K.; Meyer, C.; Middleton, R. P.; Moa, T.; Moritz, S.; Morris, J. D.; Mudd, R. D.; Narayan, R.; zur Nedden, M.; Neusiedl, A.; Newman, P. R.; Nikiforov, A.; Ohm, C. C.; Perera, V. J. O.; Pfeiffer, U.; Plucinski, P.; Poddar, S.; Prieur, D. P. F.; Qian, W.; Rieck, P.; Rizvi, E.; Sankey, D. P. C.; Schäfer, U.; Scharf, V.; Schmitt, K.; Schröder, C.; Schultz-Coulon, H.-C.; Schumacher, C.; Schwienhorst, R.; Silverstein, S. B.; Simioni, E.; Snidero, G.; Staley, R. J.; Stamen, R.; Stock, P.; Stockton, M. C.; Tan, C. L. A.; Tapprogge, S.; Thomas, J. P.; Thompson, P. D.; Thomson, M.; True, P.; Watkins, P. M.; Watson, A. T.; Watson, M. F.; Weber, P.; Wessels, M.; Wiglesworth, C.; Williams, S. L.

2012-12-01

The PreProcessor system of the ATLAS Level-1 Calorimeter Trigger (L1Calo) receives about 7200 analogue signals from the electromagnetic and hadronic components of the calorimetric detector system. Lateral division results in cells which are pre-summed to so-called Trigger Towers of size 0.1 × 0.1 along azimuth (phi) and pseudorapidity (η). The received calorimeter signals represent deposits of transverse energy. The system consists of 124 individual PreProcessor modules that digitise the input signals for each LHC collision, and provide energy and timing information to the digital processors of the L1Calo system, which identify physics objects forming much of the basis for the full ATLAS first level trigger decision. This paper describes the architecture of the PreProcessor, its hardware realisation, functionality, and performance.

The 3D laser radar vision processor system

NASA Astrophysics Data System (ADS)

Sebok, T. M.

1990-10-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

The 3D laser radar vision processor system

NASA Technical Reports Server (NTRS)

Sebok, T. M.

1990-01-01

Loral Defense Systems (LDS) developed a 3D Laser Radar Vision Processor system capable of detecting, classifying, and identifying small mobile targets as well as larger fixed targets using three dimensional laser radar imagery for use with a robotic type system. This processor system is designed to interface with the NASA Johnson Space Center in-house Extra Vehicular Activity (EVA) Retriever robot program and provide to it needed information so it can fetch and grasp targets in a space-type scenario.

Compact propane fuel processor for auxiliary power unit application

NASA Astrophysics Data System (ADS)

Dokupil, M.; Spitta, C.; Mathiak, J.; Beckhaus, P.; Heinzel, A.

With focus on mobile applications a fuel cell auxiliary power unit (APU) using liquefied petroleum gas (LPG) is currently being developed at the Centre for Fuel Cell Technology (Zentrum für BrennstoffzellenTechnik, ZBT gGmbH). The system is consisting of an integrated compact and lightweight fuel processor and a low temperature PEM fuel cell for an electric power output of 300 W. This article is presenting the current status of development of the fuel processor which is designed for a nominal hydrogen output of 1 k Wth,H2 within a load range from 50 to 120%. A modular setup was chosen defining a reformer/burner module and a CO-purification module. Based on the performance specifications, thermodynamic simulations, benchmarking and selection of catalysts the modules have been developed and characterised simultaneously and then assembled to the complete fuel processor. Automated operation results in a cold startup time of about 25 min for nominal load and carbon monoxide output concentrations below 50 ppm for steady state and dynamic operation. Also fast transient response of the fuel processor at load changes with low fluctuations of the reformate gas composition have been achieved. Beside the development of the main reactors the transfer of the fuel processor to an autonomous system is of major concern. Hence, concepts for packaging have been developed resulting in a volume of 7 l and a weight of 3 kg. Further a selection of peripheral components has been tested and evaluated regarding to the substitution of the laboratory equipment.

Treecode with a Special-Purpose Processor

NASA Astrophysics Data System (ADS)

Makino, Junichiro

1991-08-01

We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

Power processor for a 20CM ion thruster

NASA Technical Reports Server (NTRS)

Biess, J. J.; Schoenfeld, A. D.; Cohen, E.

1973-01-01

A power processor breadboard for the JPL 20CM Ion Engine was designed, fabricated, and tested to determine compliance with the electrical specification. The power processor breadboard used the silicon-controlled rectifier (SCR) series resonant inverter as the basic power stage to process all the power to the ion engine. The breadboard power processor was integrated with the JPL 20CM ion engine and complete testing was performed. The integration tests were performed without any silicon-controlled rectifier failure. This demonstrated the ruggedness of the series resonant inverter in protecting the switching elements during arcing in the ion engine. A method of fault clearing the ion engine and returning back to normal operation without elaborate sequencing and timing control logic was evolved. In this method, the main vaporizer was turned off and the discharge current limit was reduced when an overload existed on the screen/accelerator supply. After the high voltage returned to normal, both the main vaporizer and the discharge were returned to normal.

A light hydrocarbon fuel processor producing high-purity hydrogen

NASA Astrophysics Data System (ADS)

Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The

Merged ozone profiles from four MIPAS processors

NASA Astrophysics Data System (ADS)

Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

2017-04-01

The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

Demonstration of two-qubit algorithms with a superconducting quantum processor.

PubMed

DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

2009-07-09

Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

NASA Technical Reports Server (NTRS)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

Time Manager Software for a Flight Processor

NASA Technical Reports Server (NTRS)

Zoerne, Roger

2012-01-01

Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

Target Salt 2025: A Global Overview of National Programs to Encourage the Food Industry to Reduce Salt in Foods

PubMed Central

Webster, Jacqui; Trieu, Kathy; Dunford, Elizabeth; Hawkes, Corinna

2014-01-01

Reducing population salt intake has been identified as a priority intervention to reduce non-communicable diseases. Member States of the World Health Organization have agreed to a global target of a 30% reduction in salt intake by 2025. In countries where most salt consumed is from processed foods, programs to engage the food industry to reduce salt in products are being developed. This paper provides a comprehensive overview of national initiatives to encourage the food industry to reduce salt. A systematic review of the literature was supplemented by key informant questionnaires to inform categorization of the initiatives. Fifty nine food industry salt reduction programs were identified. Thirty eight countries had targets for salt levels in foods and nine countries had introduced legislation for some products. South Africa and Argentina have both introduced legislation limiting salt levels across a broad range of foods. Seventeen countries reported reductions in salt levels in foods—the majority in bread. While these trends represent progress, many countries have yet to initiate work in this area, others are at early stages of implementation and further monitoring is required to assess progress towards achieving the global target. PMID:25195640

A Course on Reconfigurable Processors

ERIC Educational Resources Information Center

Shoufan, Abdulhadi; Huss, Sorin A.

2010-01-01

Reconfigurable computing is an established field in computer science. Teaching this field to computer science students demands special attention due to limited student experience in electronics and digital system design. This article presents a compact course on reconfigurable processors, which was offered at the Technische Universitat Darmstadt,…

PATCH image processor user's manual

NASA Technical Reports Server (NTRS)

Nieves, M. J. (Principal Investigator)

1980-01-01

The patch image processor extracts patches in various size (32 x 32, 64 x 64, 128 x 128, and 256 x 256 pixels) from full frame LANDSAT imagery data. With the patches that are extracted, a patch image mosaic is created in the image processing system, IMDACS, format.

RISC Processors and High Performance Computing

NASA Technical Reports Server (NTRS)

Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

1995-01-01

This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

Watchdog activity monitor (WAM) for use wth high coverage processor self-test

NASA Technical Reports Server (NTRS)

Tulpule, Bhalchandra R. (Inventor); Crosset, III, Richard W. (Inventor); Versailles, Richard E. (Inventor)

1988-01-01

A high fault coverage, instruction modeled self-test for a signal processor in a user environment is disclosed. The self-test executes a sequence of sub-tests and issues a state transition signal upon the execution of each sub-test. The self-test may be combined with a watchdog activity monitor (WAM) which provides a test-failure signal in the presence of a counted number of state transitions not agreeing with an expected number. An independent measure of time may be provided in the WAM to increase fault coverage by checking the processor's clock. Additionally, redundant processor systems are protected from inadvertent unsevering of a severed processor using a unique unsever arming technique and apparatus.

Electrical Prototype Power Processor for the 30-cm Mercury electric propulsion engine

NASA Technical Reports Server (NTRS)

Biess, J. J.; Frye, R. J.

1978-01-01

An Electrical Prototpye Power Processor has been designed to the latest electrical and performance requirements for a flight-type 30-cm ion engine and includes all the necessary power, command, telemetry and control interfaces for a typical electric propulsion subsystem. The power processor was configured into seven separate mechanical modules that would allow subassembly fabrication, test and integration into a complete power processor unit assembly. The conceptual mechanical packaging of the electrical prototype power processor unit demonstrated the relative location of power, high voltage and control electronic components to minimize electrical interactions and to provide adequate thermal control in a vacuum environment. Thermal control was accomplished with a heat pipe simulator attached to the base of the modules.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

NASA Technical Reports Server (NTRS)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

The Event Based Language and Its Multiple Processor Implementations.

DTIC Science & Technology

1980-01-01

10 6.1 "Recursive" Linear Fibonacci ................................................ 105 6.2 The Readers Writers Problem...kinds. Examples of such systems are: C.mmp [Wu-72], Pluribus [He-73], Data Flow [ De -75], the boolean n-cube parallel machine [Su-77], and the MuNet [Wa...concurrency within programs; therefore, we hate concentrated on two types of systems which seem suitable: a processor network, and a data flow processor [ De -77

Rational calculation accuracy in acousto-optical matrix-vector processor

NASA Astrophysics Data System (ADS)

Oparin, V. V.; Tigin, Dmitry V.

1994-01-01

The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

Fabrication Security and Trust of Domain-Specific ASIC Processors

DTIC Science & Technology

2016-10-30

embedded in the design. For example , an ASIC processor potentially has a 10-1,000X performance advantage over its FPGA and GPP counterparts, but...paper by summarizing our lessons learned from this project and suggests a few research directions. II. DOMAIN-SPECIFIC ASIC PROCESSORS As Figure 1 has...sponsored by the Assistant Secretary of Defense for Research & Engineering under Air Force Contract #FA8721-05-C-0002. Opinions, interpretations

78 FR 9529 - National School Lunch Program and School Breakfast Program: Nutrition Standards for All Foods...

Federal Register 2010, 2011, 2012, 2013, 2014

2013-02-08

...This rule proposes to amend the National School Lunch Program and School Breakfast Program regulations consistent with amendments made in the Healthy, Hunger-Free Kids Act of 2010 (HHFKA). The HHFKA requires that the Secretary promulgate proposed regulations to establish nutrition standards for foods sold in schools other than those foods provided under the Child Nutrition Act of 1966 (CNA) and the Richard B. Russell National School Lunch Act (NSLA). The HHFKA amends the CNA, requiring that such standards shall be consistent with the most recent Dietary Guidelines for Americans and that the Secretary shall consider authoritative scientific recommendations for nutrition standards; existing school nutrition standards, including voluntary standards for beverages and snack foods; current State and local standards; the practical application of the nutrition standards; and special exemptions for infrequent school-sponsored fundraisers (other than fundraising through vending machines, school stores, snack bars, a la carte sales and any other exclusions determined by the Secretary). The HHFKA also amended the NSLA to require that schools participating in the National School Lunch Program make potable water available to children at no charge in the place where lunches are served during the meal service. These proposed changes are intended to improve the health and well-being of the Nation's children, increase consumption of healthful foods during the school day and create an environment that reinforces the development of healthy eating habits.

Impact of the National Food Supplementary Program for Children on Household Food Security and Maternal Weight Status in Iran.

PubMed

Ghodsi, Delaram; Omidvar, Nasrin; Eini-Zinab, Hassan; Rashidian, Arash; Raghfar, Hossein

2016-01-01

Food aid programs are strategies that aim to improve nutritional status and to tackle food insecurity. This study aimed to evaluate the effect of a National Food Supplementary Program for Children on households' food security. The study sample included 359 mothers of children aged 6-72 months under the coverage of the program in two provinces of Iran. Demographic and socioeconomic characteristics of the households and percentage of supplementary food items consumed by target child were assessed by a questionnaire and checklist. Data on household food security were collected by locally adapted Household Food Insecurity Access Scale at the baseline of the study and 6 months thereafter. At the baseline, only 4.7% of families were food secure, while 43.5% were severely food insecure, and these proportions were changed to 7.9% and 38%, respectively ( P < 0.001), at the end of the study. Odds of having worse food insecurity in households with medium and high wealth index was 65% and 87% lower than those with low wealth index, respectively (odds ratio [OR] = 0.35, 95% confidence interval [CI]: 0.2-0.61, and OR = 0.23, 95% CI: 0.12-0.43). Food sharing was common among more than 95% of the studied households. Mean maternal body mass index (BMI) increased significantly after 6 months ( P < 0.001). However, there was no significant association between mother's BMI and household food security in the baseline and at the end of the study ( P > 0.05). Findings show that the food supplementary program for children can also improve the household food security status. Further research is needed to assess other factors that affect the effectiveness of this kind of programs.

Configurable Multi-Purpose Processor

NASA Technical Reports Server (NTRS)

Valencia, J. Emilio; Forney, Chirstopher; Morrison, Robert; Birr, Richard

2010-01-01

Advancements in technology have allowed the miniaturization of systems used in aerospace vehicles. This technology is driven by the need for next-generation systems that provide reliable, responsive, and cost-effective range operations while providing increased capabilities such as simultaneous mission support, increased launch trajectories, improved launch, and landing opportunities, etc. Leveraging the newest technologies, the command and telemetry processor (CTP) concept provides for a compact, flexible, and integrated solution for flight command and telemetry systems and range systems. The CTP is a relatively small circuit board that serves as a processing platform for high dynamic, high vibration environments. The CTP can be reconfigured and reprogrammed, allowing it to be adapted for many different applications. The design is centered around a configurable field-programmable gate array (FPGA) device that contains numerous logic cells that can be used to implement traditional integrated circuits. The FPGA contains two PowerPC processors running the Vx-Works real-time operating system and are used to execute software programs specific to each application. The CTP was designed and developed specifically to provide telemetry functions; namely, the command processing, telemetry processing, and GPS metric tracking of a flight vehicle. However, it can be used as a general-purpose processor board to perform numerous functions implemented in either hardware or software using the FPGA s processors and/or logic cells. Functionally, the CTP was designed for range safety applications where it would ultimately become part of a vehicle s flight termination system. Consequently, the major functions of the CTP are to perform the forward link command processing, GPS metric tracking, return link telemetry data processing, error detection and correction, data encryption/ decryption, and initiate flight termination action commands. Also, the CTP had to be designed to survive and

Application of convolve-multiply-convolve SAW processor for satellite communications

NASA Technical Reports Server (NTRS)

Lie, Y. S.; Ching, M.

1991-01-01

There is a need for a satellite communications receiver than can perform simultaneous multi-channel processing of single channel per carrier (SCPC) signals originating from various small (mobile or fixed) earth stations. The number of ground users can be as many as 1000. Conventional techniques of simultaneously processing these signals is by employing as many RF-bandpass filters as the number of channels. Consequently, such an approach would result in a bulky receiver, which becomes impractical for satellite applications. A unique approach utilizing a realtime surface acoustic wave (SAW) chirp transform processor is presented. The application of a Convolve-Multiply-Convolve (CMC) chirp transform processor is described. The CMC processor transforms each input channel into a unique timeslot, while preserving its modulation content (in this case QPSK). Subsequently, each channel is individually demodulated without the need of input channel filters. Circuit complexity is significantly reduced, because the output frequency of the CMC processor is common for all input channel frequencies. The results of theoretical analysis and experimental results are in good agreement.

Reconfigurable lattice mesh designs for programmable photonic processors.

PubMed

Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

2016-05-30

We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

Ring-array processor distribution topology for optical interconnects

NASA Technical Reports Server (NTRS)

Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

1992-01-01

The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

Interactive high-resolution isosurface ray casting on multicore processors.

PubMed

Wang, Qin; JaJa, Joseph

2008-01-01

We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

Federal Register 2010, 2011, 2012, 2013, 2014

2012-01-03

... ENVIRONMENTAL PROTECTION AGENCY [FRL-9612-9] Biological Processors of Alabama; Decatur, Morgan... reimbursement of past response costs concerning the Biological Processors of Alabama Superfund Site located in... Ms. Paula V. Painter. Submit your comments by Site name Biological Processors of Alabama Superfund...

A hierarchical, automated target recognition algorithm for a parallel analog processor

NASA Technical Reports Server (NTRS)

Woodward, Gail; Padgett, Curtis

1997-01-01

A hierarchical approach is described for an automated target recognition (ATR) system, VIGILANTE, that uses a massively parallel, analog processor (3DANN). The 3DANN processor is capable of performing 64 concurrent inner products of size 1x4096 every 250 nanoseconds.

Food Consumption According to the Days of the Week – National Food Survey, 2008-2009

PubMed Central

Monteiro, Luana Silva; Hassan, Bruna Kulik; Estima, Camilla Chermont Prochnik; Souza, Amanda de Moura; Verly, Eliseu; Sichieri, Rosely; Pereira, Rosangela Alves

2017-01-01

ABSTRACT OBJECTIVE Evaluate the variations in energy, nutrients, and food groups intake between days of the week and weekend days in the Brazilian population. METHODS We used data from the first National Food Survey (2008-2009) of a one-day food log of a representative sample of the Brazilian population aged 10 years or older (n = 34,003). For the analyses, we considered the sample weights and the effect of the study design. The mean (and standard deviations) and frequencies (%) of energy, nutrients, and food groups consumption were estimated for weekdays (Monday to Friday) and weekend (Saturday and Sunday), we then estimated the differences according to the days of the week for the population strata analyzed. RESULTS The average daily energy intake for the weekend was 8% higher than the one observed for weekdays. The average percentage contribution of carbohydrate to the daily energy intake was higher during the week compared to Saturday and Sunday (56.3% versus 54.1%, p < 0.01). The inverse was observed for averages of the contribution to the daily intake of energy from total fat (26.8% versus 28.4%), saturated fat (9.1% versus 9.9%) and trans fat (1.4% versus 1.6%). The most significant changes between weekdays and weekend days were observed for eggs, sugar-added beverages, puff snacks and chips, beans, and pasta. During weekends, the frequency of beverage with added sugar consumption increased by 34%, the amount consumed increased by 42%, and the contribution to energy intake increased by 62% when compared to weekdays. CONCLUSIONS The Brazilian population increases energy intake and unhealthy food markers on weekends compared to weekdays. PMID:29020121

Hypercluster Parallel Processor

NASA Technical Reports Server (NTRS)

Blech, Richard A.; Cole, Gary L.; Milner, Edward J.; Quealy, Angela

1992-01-01

Hypercluster computer system includes multiple digital processors, operation of which coordinated through specialized software. Configurable according to various parallel-computing architectures of shared-memory or distributed-memory class, including scalar computer, vector computer, reduced-instruction-set computer, and complex-instruction-set computer. Designed as flexible, relatively inexpensive system that provides single programming and operating environment within which one can investigate effects of various parallel-computing architectures and combinations on performance in solution of complicated problems like those of three-dimensional flows in turbomachines. Hypercluster software and architectural concepts are in public domain.

Aligning food-processing policies to promote healthier fat consumption in India.

PubMed

Downs, Shauna M; Marie Thow, Anne; Ghosh-Jerath, Suparna; Leeder, Stephen R

2015-09-01

India is undergoing a shift in consumption from traditional foods to processed foods high in sugar, salt and fat. Partially hydrogenated vegetable oils (PHVOs) high in trans-fat are often used in processed foods in India given their low cost and extended shelf life. The World Health Organization has called for the elimination of PHVOs from the global food supply and recommends their replacement with polyunsaturated fat to maximize health benefits. This study examined barriers to replacing industrially produced trans-fat in the Indian food supply and systematically identified potential policy solutions to assist the government in encouraging its removal and replacement with healthier polyunsaturated fat. A combination of food supply chain analysis and semi-structured interviews with key stakeholders was conducted. The main barriers faced by the food-processing sector in terms of reducing use of trans-fat and replacing it with healthier oils in India were the low availability and high cost of oils high in polyunsaturated fats leading to a reliance on palm oil (high in saturated fat) and the low use of those healthier oils in product reformulation. Improved integration between farmers and processors, investment in technology and pricing strategies to incentivize use of healthier oils for product reformulation were identified as policy options. Food processors have trouble accessing sufficient affordable healthy oils for product reformulation, but existing incentives aimed at supporting food processing could be tweaked to ensure a greater supply of healthy oils with the potential to improve population health. © The Author (2014). Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Phase coherence adaptive processor for automatic signal detection and identification

NASA Astrophysics Data System (ADS)

Wagstaff, Ronald A.

2006-05-01

A continuously adapting acoustic signal processor with an automatic detection/decision aid is presented. Its purpose is to preserve the signals of tactical interest, and filter out other signals and noise. It utilizes single sensor or beamformed spectral data and transforms the signal and noise phase angles into "aligned phase angles" (APA). The APA increase the phase temporal coherence of signals and leave the noise incoherent. Coherence thresholds are set, which are representative of the type of source "threat vehicle" and the geographic area or volume in which it is operating. These thresholds separate signals, based on the "quality" of their APA coherence. An example is presented in which signals from a submerged source in the ocean are preserved, while clutter signals from ships and noise are entirely eliminated. Furthermore, the "signals of interest" were identified by the processor's automatic detection aid. Similar performance is expected for air and ground vehicles. The processor's equations are formulated in such a manner that they can be tuned to eliminate noise and exploit signal, based on the "quality" of their APA temporal coherence. The mathematical formulation for this processor is presented, including the method by which the processor continuously self-adapts. Results show nearly complete elimination of noise, with only the selected category of signals remaining, and accompanying enhancements in spectral and spatial resolution. In most cases, the concept of signal-to-noise ratio looses significance, and "adaptive automated /decision aid" is more relevant.

Prototype Focal-Plane-Array Optoelectronic Image Processor

NASA Technical Reports Server (NTRS)

Fang, Wai-Chi; Shaw, Timothy; Yu, Jeffrey

1995-01-01

Prototype very-large-scale integrated (VLSI) planar array of optoelectronic processing elements combines speed of optical input and output with flexibility of reconfiguration (programmability) of electronic processing medium. Basic concept of processor described in "Optical-Input, Optical-Output Morphological Processor" (NPO-18174). Performs binary operations on binary (black and white) images. Each processing element corresponds to one picture element of image and located at that picture element. Includes input-plane photodetector in form of parasitic phototransistor part of processing circuit. Output of each processing circuit used to modulate one picture element in output-plane liquid-crystal display device. Intended to implement morphological processing algorithms that transform image into set of features suitable for high-level processing; e.g., recognition.

Greater Food Reward Sensitivity Is Associated with More Frequent Intake of Discretionary Foods in a Nationally Representative Sample of Young Adults.

PubMed

Nansel, Tonja R; Lipsky, Leah M; Eisenberg, Miriam H; Haynie, Denise L; Liu, Danping; Simons-Morton, Bruce

2016-01-01

Food reward sensitivity may influence individual susceptibility to an environment replete with highly palatable foods of minimal nutritional value. These foods contain combinations of added sugar, fat, and/or salt that may enhance their motivational salience. This study examined associations of food reward sensitivity with eating behaviors in the NEXT Generation Health Study, a nationally representative sample of U.S. young adults. Participants (n = 2202) completed self-report measures including the Power of Food Scale, assessing food reward sensitivity, and intake frequency of 14 food groups. Multiple linear regressions estimated associations of food reward sensitivity with each of the eating behaviors adjusting for covariates. Higher food reward sensitivity was associated with more frequent intake of fast food (b ± linearized SE = 0.24 ± 0.05, p < 0.001), sweet and salty snacks (0.21 ± 0.05, p < 0.001), foods made with cheese (0.14 ± 0.06, p = 0.03), soda (0.12 ± 0.04, p = 0.009), processed meats (0.12 ± 0.05, p = 0.045), and fish (0.08 ± 0.03, p = 0.03) but was not associated with intake frequency of fruit or juice, green or orange vegetables, beans, whole grains, nuts/seeds, or dairy products. Food reward sensitivity was associated with greater intake of discretionary foods but was not associated with intake of most health-promoting foods, suggesting food reward sensitivity may lead to preferential intake of unhealthful foods.

Greater Food Reward Sensitivity Is Associated with More Frequent Intake of Discretionary Foods in a Nationally Representative Sample of Young Adults

PubMed Central

Nansel, Tonja R.; Lipsky, Leah M.; Eisenberg, Miriam H.; Haynie, Denise L.; Liu, Danping; Simons-Morton, Bruce

2016-01-01

Food reward sensitivity may influence individual susceptibility to an environment replete with highly palatable foods of minimal nutritional value. These foods contain combinations of added sugar, fat, and/or salt that may enhance their motivational salience. This study examined associations of food reward sensitivity with eating behaviors in the NEXT Generation Health Study, a nationally representative sample of U.S. young adults. Participants (n = 2202) completed self-report measures including the Power of Food Scale, assessing food reward sensitivity, and intake frequency of 14 food groups. Multiple linear regressions estimated associations of food reward sensitivity with each of the eating behaviors adjusting for covariates. Higher food reward sensitivity was associated with more frequent intake of fast food (b ± linearized SE = 0.24 ± 0.05, p < 0.001), sweet and salty snacks (0.21 ± 0.05, p < 0.001), foods made with cheese (0.14 ± 0.06, p = 0.03), soda (0.12 ± 0.04, p = 0.009), processed meats (0.12 ± 0.05, p = 0.045), and fish (0.08 ± 0.03, p = 0.03) but was not associated with intake frequency of fruit or juice, green or orange vegetables, beans, whole grains, nuts/seeds, or dairy products. Food reward sensitivity was associated with greater intake of discretionary foods but was not associated with intake of most health-promoting foods, suggesting food reward sensitivity may lead to preferential intake of unhealthful foods. PMID:27588287

17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

Code of Federal Regulations, 2011 CFR

2011-04-01

... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

17 CFR 242.609 - Registration of securities information processors: form of application and amendments.

Code of Federal Regulations, 2010 CFR

2010-04-01

... information processors: form of application and amendments. 242.609 Section 242.609 Commodity and Securities....609 Registration of securities information processors: form of application and amendments. (a) An application for the registration of a securities information processor shall be filed on Form SIP (§ 249.1001...

ARTS III/Parallel Processor Design Study

DOT National Transportation Integrated Search

1975-04-01

It was the purpose of this design study to investigate the feasibility, suitability, and cost-effectiveness of augmenting the ARTS III failsafe/failsoft multiprocessor system with a form of parallel processor to accomodate a large growth in air traff...

Matching the Word Processor to the Job.

ERIC Educational Resources Information Center

Synder, Carin

1982-01-01

The intelligent purchase of school office equipment, specifically word processors, typewriters, calculators, and furniture, requires analysis of present needs and a realistic evaluation of future needs. (MLF)

IMPLEMENTATION OF THE SMOKE EMISSION DATA PROCESSOR AND SMOKE TOOL INPUT DATA PROCESSOR IN MODELS-3

EPA Science Inventory

The U.S. Environmental Protection Agency has implemented Version 1.3 of SMOKE (Sparse Matrix Object Kernel Emission) processor for preparation of area, mobile, point, and biogenic sources emission data within Version 4.1 of the Models-3 air quality modeling framework. The SMOK...

Monitoring the impact of trade agreements on national food environments: trade imports and population nutrition risks in Fiji.

PubMed

Ravuvu, Amerita; Friel, Sharon; Thow, Anne-Marie; Snowdon, Wendy; Wate, Jillian

2017-06-13

Trade agreements are increasingly recognised as playing an influential role in shaping national food environments and the availability and nutritional quality of the food supply. Global monitoring of food environments and trade policies can strengthen the evidence base for the impact of trade policy on nutrition, and support improved policy coherence. Using the INFORMAS trade monitoring protocol, we reviewed available food supply data to understand associations between Fiji's commitments under WTO trade agreements and food import volume trends. First, a desk review was conducted to map and record in one place Fiji's commitments to relevant existing trade agreements that have implications for Fiji's national food environment under the domains of the INFORMAS trade monitoring protocol. An excel database was developed to document the agreements and their provisions. The second aspect of the research focused on data extraction. We began with identifying food import volumes into Fiji by country of origin, with a particular focus on a select number of 'healthy and unhealthy' foods. We also developed a detailed listing of transnational food corporations currently operating in Fiji. The study suggests that Fiji's WTO membership, in conjunction with associated economic and agricultural policy changes have contributed to increased availability of both healthy and less healthy imported foods. In systematically monitoring the import volume trends of these two categories of food, the study highlights an increase in healthy foods such as fresh fruits and vegetables and whole-grain refined cereals. The study also shows that there has been an increase in less healthy foods including fats and oils; meat; processed dairy products; energy-dense beverages; and processed and packaged foods. By monitoring the trends of imported foods at country level from the perspective of trade agreements, we are able to develop appropriate and targeted interventions to improve diets and health. This

Processor Emulator with Benchmark Applications

DOE Office of Scientific and Technical Information (OSTI.GOV)

Lloyd, G. Scott; Pearce, Roger; Gokhale, Maya

2015-11-13

A processor emulator and a suite of benchmark applications have been developed to assist in characterizing the performance of data-centric workloads on current and future computer architectures. Some of the applications have been collected from other open source projects. For more details on the emulator and an example of its usage, see reference [1].

Fast, Massively Parallel Data Processors

NASA Technical Reports Server (NTRS)

Heaton, Robert A.; Blevins, Donald W.; Davis, ED

1994-01-01

Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.

A Descriptive Analysis of Supply Factors and Prices for USDA Foods in the National School Lunch Program

ERIC Educational Resources Information Center

Peterson, Cora

2010-01-01

Purpose/Objectives: Schools that participate in the National School Lunch Program (NSLP) receive a portion of their annual federal funding as commodity entitlement foods--now called USDA Foods--rather than cash payments. Due to rising food prices in recent years, it has been recommended that schools compare the costs and benefits of commodity and…

Scan line graphics generation on the massively parallel processor

NASA Technical Reports Server (NTRS)

Dorband, John E.

1988-01-01

Described here is how researchers implemented a scan line graphics generation algorithm on the Massively Parallel Processor (MPP). Pixels are computed in parallel and their results are applied to the Z buffer in large groups. To perform pixel value calculations, facilitate load balancing across the processors and apply the results to the Z buffer efficiently in parallel requires special virtual routing (sort computation) techniques developed by the author especially for use on single-instruction multiple-data (SIMD) architectures.

Processor farming in two-level analysis of historical bridge

NASA Astrophysics Data System (ADS)

Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

2017-11-01

This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

Contextual classification on a CDC Flexible Processor system. [for photomapped remote sensing data

NASA Technical Reports Server (NTRS)

Smith, B. W.; Siegel, H. J.; Swain, P. H.

1981-01-01

A potential hardware organization for the Flexible Processor Array is presented. An algorithm that implements a contextual classifier for remote sensing data analysis is given, along with uniprocessor classification algorithms. The Flexible Processor algorithm is provided, as are simulated timings for contextual classifiers run on the Flexible Processor Array and another system. The timings are analyzed for context neighborhoods of sizes three and nine.

30/20 GHz communications systems baseband processor development

NASA Astrophysics Data System (ADS)

Brown, L.; Sabourin, D.; Stilwell, J.; McCallister, R.; Borota, M.

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

Embedded Data Processor and Portable Computer Technology testbeds

NASA Technical Reports Server (NTRS)

Alena, Richard; Liu, Yuan-Kwei; Goforth, Andre; Fernquist, Alan R.

1993-01-01

Attention is given to current activities in the Embedded Data Processor and Portable Computer Technology testbed configurations that are part of the Advanced Data Systems Architectures Testbed at the Information Sciences Division at NASA Ames Research Center. The Embedded Data Processor Testbed evaluates advanced microprocessors for potential use in mission and payload applications within the Space Station Freedom Program. The Portable Computer Technology (PCT) Testbed integrates and demonstrates advanced portable computing devices and data system architectures. The PCT Testbed uses both commercial and custom-developed devices to demonstrate the feasibility of functional expansion and networking for portable computers in flight missions.

Method for fast start of a fuel processor

DOEpatents

Ahluwalia, Rajesh K [Burr Ridge, IL; Ahmed, Shabbir [Naperville, IL; Lee, Sheldon H. D. [Willowbrook, IL

2008-01-29

An improved fuel processor for fuel cells is provided whereby the startup time of the processor is less than sixty seconds and can be as low as 30 seconds, if not less. A rapid startup time is achieved by either igniting or allowing a small mixture of air and fuel to react over and warm up the catalyst of an autothermal reformer (ATR). The ATR then produces combustible gases to be subsequently oxidized on and simultaneously warm up water-gas shift zone catalysts. After normal operating temperature has been achieved, the proportion of air included with the fuel is greatly diminished.

30/20 GHz communications systems baseband processor development

NASA Technical Reports Server (NTRS)

Brown, L.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

1982-01-01

The architecture and system design concepts for a commercial satellite communications system planned for the 1990's has been developed. The system provides data communications between the individual users via trunking and customer premise service terminals utilizing a central switching satellite operating in a time-division multiple-access mode. Baseband processing is employed to route and control traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband processor design are being verified in the baseband processor proof-of-concept model described herein.

Design of an integrated fuel processor for residential PEMFCs applications

NASA Astrophysics Data System (ADS)

Seo, Yu Taek; Seo, Dong Joo; Jeong, Jin Hyeok; Yoon, Wang Lai

KIER has been developing a novel fuel processing system to provide hydrogen rich gas to residential PEMFCs system. For the effective design of a compact hydrogen production system, each unit process for steam reforming and water gas shift, has a steam generator and internal heat exchangers which are thermally and physically integrated into a single packaged hardware system. The newly designed fuel processor (prototype II) showed a thermal efficiency of 78% as a HHV basis with methane conversion of 89%. The preferential oxidation unit with two staged cascade reactors, reduces, the CO concentration to below 10 ppm without complicated temperature control hardware, which is the prerequisite CO limit for the PEMFC stack. After we achieve the initial performance of the fuel processor, partial load operation was carried out to test the performance and reliability of the fuel processor at various loads. The stability of the fuel processor was also demonstrated for three successive days with a stable composition of product gas and thermal efficiency. The CO concentration remained below 10 ppm during the test period and confirmed the stable performance of the two-stage PrOx reactors.

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

PubMed Central

Manolakos, Elias S.

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

PubMed

Sharma, Anuj; Manolakos, Elias S

2015-01-01

Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

Development of a Novel, Two-Processor Architecture for a Small UAV Autopilot System,

DTIC Science & Technology

2006-07-26

is, and the control laws the user implements to control it. The flight control system board will contain the processor selected for this system...Unit (IMU). The IMU contains solid-state gyros and accelerometers and uses these to determine the attitude of the UAV within the three dimensions of...multiple-UAV swarming for combat support operations. The mission processor board will contain the processor selected to execute the mission

Application of Advanced Multi-Core Processor Technologies to Oceanographic Research

DTIC Science & Technology

2013-09-30

STM32 NXP LPC series No Proprietary Microchip PIC32/DSPIC No > 500 mW; < 5 W ARM Cortex TI OMAP TI Sitara Broadcom BCM2835 Varies FPGA...1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Application of Advanced Multi-Core Processor Technologies...state-of-the-art information processing architectures. OBJECTIVES Next-generation processor architectures (multi-core, multi-threaded) hold the

National Food, Nutrition, and Physical Activity Survey of the Portuguese General Population (2015-2016): Protocol for Design and Development

PubMed Central

Torres, Duarte; Oliveira, Andreia; Severo, Milton; Guiomar, Sofia; Alarcão, Violeta; Ramos, Elisabete; Rodrigues, Sara; Vilela, Sofia; Oliveira, Luísa; Mota, Jorge; Teixeira, Pedro J; Nicola, Paulo J; Soares, Simão; Andersen, Lene Frost

2018-01-01

Background The assessment of food consumption data using harmonized methodologies at the European level is fundamental to support the development of public policies. Portugal is one of the countries with the most outdated information on individual food consumption. Objective The objective of this study was to describe the design and methodology of the National Food, Nutrition and Physical Activity Survey, 2015-2016, developed to collect national and regional data on dietary habits, physical activity (PA), and nutritional status, in a representative sample of the Portuguese general population (3 months-84 years). Methods Participants were selected by multistage sampling, using the National Heath Registry as the sampling frame. Data collection, during 12 months, was harmonized according to European guidelines (EU-MENU, European Food Safety Authority [EFSA]). Computer-assisted personal interviewing (CAPI) was performed on a specific electronic platform synchronized with nutritional composition data and considering the FoodEx2 classification system. Dietary assessment was performed using 24-hour recalls (two nonconsecutive, 8-15 days apart) or food diaries in the case of children aged <10 years, complemented with a food propensity questionnaire; PA data (International Physical Activity Questionnaire [IPAQ], the Activity Choice Index [ACI], and 4-days PA diaries); sociodemographic data, and other health-related data were also collected. Results A sample of 6553 individuals completed the first interview, and 5811 participants completed two dietary assessments. The participation rate among eligible individuals was 33.38% (6553/19,635), considering the first interview, and 29.60% (5811/19,635) for the participants with two completed interviews (about 40% in children and adolescents and 20% in elderly individuals). Results of the survey will be disseminated in national and international scientific journals during 2018-2019. Conclusions The survey will assist policy planning

Micromechanical Signal Processors

NASA Astrophysics Data System (ADS)

Nguyen, Clark Tu-Cuong

Completely monolithic high-Q micromechanical signal processors constructed of polycrystalline silicon and integrated with CMOS electronics are described. The signal processors implemented include an oscillator, a bandpass filter, and a mixer + filter--all of which are components commonly required for up- and down-conversion in communication transmitters and receivers, and all of which take full advantage of the high Q of micromechanical resonators. Each signal processor is designed, fabricated, then studied with particular attention to the performance consequences associated with miniaturization of the high-Q element. The fabrication technology which realizes these components merges planar integrated circuit CMOS technologies with those of polysilicon surface micromachining. The technologies are merged in a modular fashion, where the CMOS is processed in the first module, the microstructures in a following separate module, and at no point in the process sequence are steps from each module intermixed. Although the advantages of such modularity include flexibility in accommodating new module technologies, the developed process constrained the CMOS metallization to a high temperature refractory metal (tungsten metallization with TiSi _2 contact barriers) and constrained the micromachining process to long-term temperatures below 835^circC. Rapid-thermal annealing (RTA) was used to relieve residual stress in the mechanical structures. To reduce the complexity involved with developing this merged process, capacitively transduced resonators are utilized. High-Q single resonator and spring-coupled micromechanical resonator filters are also investigated, with particular attention to noise performance, bandwidth control, and termination design. The noise in micromechanical filters is found to be fairly high due to poor electromechanical coupling on the micro-scale with present-day technologies. Solutions to this high series resistance problem are suggested, including smaller

Next Generation Security for the 10,240 Processor Columbia System

NASA Technical Reports Server (NTRS)

Hinke, Thomas; Kolano, Paul; Shaw, Derek; Keller, Chris; Tweton, Dave; Welch, Todd; Liu, Wen (Betty)

2005-01-01

This presentation includes a discussion of the Columbia 10,240-processor system located at the NASA Advanced Supercomputing (NAS) division at the NASA Ames Research Center which supports each of NASA's four missions: science, exploration systems, aeronautics, and space operations. It is comprised of 20 Silicon Graphics nodes, each consisting of 512 Itanium II processors. A 64 processor Columbia front-end system supports users as they prepare their jobs and then submits them to the PBS system. Columbia nodes and front-end systems use the Linux OS. Prior to SC04, the Columbia system was used to attain a processing speed of 51.87 TeraFlops, which made it number two on the Top 500 list of the world's supercomputers and the world's fastest "operational" supercomputer since it was fully engaged in supporting NASA users.

Comprehensive mapping of national school food policies across the European Union plus Norway and Switzerland

PubMed Central

Storcksdieck genannt Bonsmann, S

2014-01-01

Childhood obesity is a major public health challenge in Europe. Schools are seen as an important setting to promote healthy diet and lifestyle in a protected environment and school food-related practices are essential in this regard. To understand what policy frameworks European countries have created to govern these practices, a systematic assessment of national school food policies across the European Union plus Norway and Switzerland (n = 30 countries) was carried out. The survey revealed that all 30 countries currently have a school food policy in place; a total of 34 relevant policies were identified, 18 of which were mandatory and the remaining 16 voluntary. Major policy objectives specified were those to improve child nutrition (97% of policies), to help children learn and adopt healthy diet and lifestyle habits (94%) and to reduce or prevent childhood obesity (88%). Most commonly (>90%), the policies offered food-based standards for menu composition, and portion sizes were guided by age-appropriate energy requirements. Lunch and snacks were the most widely addressed mealtimes for almost 90% of all policies examined. Other important areas covered included food marketing to children; the availability of vending services; training requirements for catering staff; and whether nutrition education is a mandatory part of the national curriculum. Evaluation was mentioned in 59% of the school food policies reviewed. Future analyses should focus on evaluating the implementation of these policies and more importantly, their effectiveness in meeting the objectives defined therein. Comparable and up-to-date information along with data on education, attainment and public health indicators will enable a comprehensive impact assessment of school food policies and help facilitate optimal school food provision for all. PMID:25663818

Comprehensive mapping of national school food policies across the European Union plus Norway and Switzerland.

PubMed

Storcksdieck Genannt Bonsmann, S

2014-12-01

Childhood obesity is a major public health challenge in Europe. Schools are seen as an important setting to promote healthy diet and lifestyle in a protected environment and school food-related practices are essential in this regard. To understand what policy frameworks European countries have created to govern these practices, a systematic assessment of national school food policies across the European Union plus Norway and Switzerland ( n  = 30 countries) was carried out. The survey revealed that all 30 countries currently have a school food policy in place; a total of 34 relevant policies were identified, 18 of which were mandatory and the remaining 16 voluntary. Major policy objectives specified were those to improve child nutrition (97% of policies), to help children learn and adopt healthy diet and lifestyle habits (94%) and to reduce or prevent childhood obesity (88%). Most commonly (>90%), the policies offered food-based standards for menu composition, and portion sizes were guided by age-appropriate energy requirements. Lunch and snacks were the most widely addressed mealtimes for almost 90% of all policies examined. Other important areas covered included food marketing to children; the availability of vending services; training requirements for catering staff; and whether nutrition education is a mandatory part of the national curriculum. Evaluation was mentioned in 59% of the school food policies reviewed. Future analyses should focus on evaluating the implementation of these policies and more importantly, their effectiveness in meeting the objectives defined therein. Comparable and up-to-date information along with data on education, attainment and public health indicators will enable a comprehensive impact assessment of school food policies and help facilitate optimal school food provision for all.

Sentinel-2 Level 2A Prototype Processor: Architecture, Algorithms And First Results

NASA Astrophysics Data System (ADS)

Muller-Wilm, Uwe; Louis, Jerome; Richter, Rudolf; Gascon, Ferran; Niezette, Marc

2013-12-01

Sen2Core is a prototype processor for Sentinel-2 Level 2A product processing and formatting. The processor is developed for and with ESA and performs the tasks of Atmospheric Correction and Scene Classification of Level 1C input data. Level 2A outputs are: Bottom-Of- Atmosphere (BOA) corrected reflectance images, Aerosol Optical Thickness-, Water Vapour-, Scene Classification maps and Quality indicators, including cloud and snow probabilities. The Level 2A Product Formatting performed by the processor follows the specification of the Level 1C User Product.

A concept for magazine Bimat processor

NASA Technical Reports Server (NTRS)

Park, C. E.

1969-01-01

Concept utilizes existing film magazines to process photographic film as the film is exposed. A standard magazine can be converted to a Bimat processor by adding three stainless steel rollers. All chemicals required for processing and fixing the negative are contained in the Bimat film.

ESA's Food Security Thematic Exploitation Platform "Supporting Sustainable Food Production from Space"

NASA Astrophysics Data System (ADS)

Gilliams, S. J.

2017-12-01

In line with the paradigm shift in Earth Observation of "Bringing the users to the data", ESA provides collaborative, virtual work environments giving access to EO data and tools, processors, and ICT resources through coherent interfaces. These coherent interfaces are categorized thematically, tailored to the related user communities and named Thematic Exploitation Platforms (TEP). The Food Security Thematic Exploitation Platform (FS-TEP) is the youngest out of seven TEPs and is developed in an agile mode in close coordination with its users. It will provide a "one stop platform" for the extraction of information from EO data for services in the food security sector mainly in Europe & Africa, allowing both access to EO data and processing of these data sets. Thereby it will foster smart, data-intensive agricultural and aquacultural applications in the scientific, private and public domain. The FS-TEP builds on a large and heterogeneous user community, spanning from application developers in agriculture to aquaculture, from small-scale farmers to agricultural industry, from public science to the finance and insurance sectors, from local and national administration to international agencies. To meet the requirements of these groups, the FS-TEP will provide different frontend interfaces. Service pilots will demonstrate the platform's ability to support agriculture and aquaculture with tailored EO based information services.The project team developing the FS-TEP and implementing pilot services during a 30 months period (started in April 2017) is led by Vista GmbH, Germany, supported by CGI Italy, VITO, Belgium, and Hatfield Consultants, Canada. It is funded by ESA under contract number 4000120074/17/I-EF.

Bonneville Power Administration Communication Alarm Processor expert system:

DOE Office of Scientific and Technical Information (OSTI.GOV)

Goeltz, R.; Purucker, S.; Tonn, B.

This report describes the Communications Alarm Processor (CAP), a prototype expert system developed for the Bonneville Power Administration by Oak Ridge National Laboratory. The system is designed to receive and diagnose alarms from Bonneville's Microwave Communications System (MCS). The prototype encompasses one of seven branches of the communications network and a subset of alarm systems and alarm types from each system. The expert system employs a backward chaining approach to diagnosing alarms. Alarms are fed into the expert system directly from the communication system via RS232 ports and sophisticated alarm filtering and mailbox software. Alarm diagnoses are presented to operatorsmore » for their review and concurrence before the diagnoses are archived. Statistical software is incorporated to allow analysis of archived data for report generation and maintenance studies. The delivered system resides on a Digital Equipment Corporation VAX 3200 workstation and utilizes Nexpert Object and SAS for the expert system and statistical analysis, respectively. 11 refs., 23 figs., 7 tabs.« less

A VME-based software trigger system using UNIX processors

NASA Astrophysics Data System (ADS)

Atmur, Robert; Connor, David F.; Molzon, William

1997-02-01

We have constructed a distributed computing platform with eight processors to assemble and filter data from digitization crates. The filtered data were transported to a tape-writing UNIX computer via ethernet. Each processor ran a UNIX operating system and was installed in its own VME crate. Each VME crate contained dual-port memories which interfaced with the digitizers. Using standard hardware and software (VME and UNIX) allows us to select from a wide variety of non-proprietary products and makes upgrades simpler, if they are necessary.

Flight design system level C requirements. Solid rocket booster and external tank impact prediction processors. [space transportation system

NASA Technical Reports Server (NTRS)

Seale, R. H.

1979-01-01

The prediction of the SRB and ET impact areas requires six separate processors. The SRB impact prediction processor computes the impact areas and related trajectory data for each SRB element. Output from this processor is stored on a secure file accessible by the SRB impact plot processor which generates the required plots. Similarly the ET RTLS impact prediction processor and the ET RTLS impact plot processor generates the ET impact footprints for return-to-launch-site (RTLS) profiles. The ET nominal/AOA/ATO impact prediction processor and the ET nominal/AOA/ATO impact plot processor generate the ET impact footprints for non-RTLS profiles. The SRB and ET impact processors compute the size and shape of the impact footprints by tabular lookup in a stored footprint dispersion data base. The location of each footprint is determined by simulating a reference trajectory and computing the reference impact point location. To insure consistency among all flight design system (FDS) users, much input required by these processors will be obtained from the FDS master data base.

Broadband set-top box using MAP-CA processor

NASA Astrophysics Data System (ADS)

Bush, John E.; Lee, Woobin; Basoglu, Chris

2001-12-01

Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

Traditional foods and 25(OH)D concentrations in a subarctic First Nations community.

PubMed

Mansuri, Sudaba; Badawi, Alaa; Kayaniyil, Sheena; Cole, David E; Harris, Stewart B; Mamakeesick, Mary; Wolever, Thomas; Gittelsohn, Joel; Maguire, Jonathon L; Connelly, Philip W; Zinman, Bernard; Hanley, Anthony J

2016-01-01

Sub-optimal vitamin D status is common worldwide and the condition may be associated with increased risk for various chronic diseases. In particular, low vitamin D status is highly prevalent in indigenous communities in Canada, although limited data are available on the determinants of serum 25-hydroxyvitamin D (25(OH)D) concentrations in this population. The relationship between traditional food consumption and vitamin D status has not been well documented. To investigate the determinants of serum 25(OH)D status in a First Nations community in Ontario, Canada, with a focus on the role of traditional food consumption and activities. A cross-sectional analysis was conducted within the Sandy Lake Health and Diabetes Project (2003-2005). A total of 445 participants (>12 years of age) were assessed for serum 25(OH)D status, anthropometric and lifestyle variables, including traditional and non-traditional dietary practices and activities. Diet patterns were identified using factor analysis, and multivariate linear regression analysis was used to analyse the determinants of 25(OH)D concentrations. Mean serum 25(OH)D concentrations were 22.1 nmol/L (16.9, 29.9 nmol/L) in men and 20.5 nmol/L (16.0, 27.3 nmol/L) in women. Multivariate determinants of higher serum 25(OH)D included higher consumption of traditional and healthier market foods, higher wild fish consumption, male gender, spring/summer season of blood collection and more frequent physical activity. Significant negative determinants included hours of TV/day, higher BMI and higher consumption of unhealthy market foods. Traditional food consumption contributed independently to higher 25(OH)D concentrations in a First Nations community with a high prevalence of sub-optimal vitamin D status.

A food store-based environmental intervention is associated with reduced BMI and improved psychosocial factors and food-related behaviors on the Navajo nation.

PubMed

Gittelsohn, Joel; Kim, Elizabeth M; He, Siran; Pardilla, Marla

2013-09-01

The prevalence of obesity is significantly higher among American Indians (AIs) and is associated with increased rates of diabetes, hypertension, and cardiovascular disease. We implemented a 14-mo intervention trial (Navajo Healthy Stores) on the Navajo Nation that sought to increase availability of healthier foods in local food stores and to promote these foods at the point of purchase and through community media. We divided the Navajo Nation into 10 store regions, half of which were randomized to intervention and half to comparison. We evaluated the program by using a pre-post sample of systematically sampled adult Navajo consumers (baseline, n = 276; postintervention, n = 145). Intervention impact was examined by analyzing pre-post differences by intervention group and by intervention exposure level. When intervention and comparison groups were compared, only body mass index (BMI) showed a trend toward impact of the intervention (P = 0.06). However, greater exposure to the intervention was associated with significantly reduced BMI (P ≤ 0.05) and improved healthy food intentions (P ≤ 0.01), healthy cooking methods (P ≤ 0.05), and healthy food getting (P ≤ 0.01). With increasing exposure, the odds of improving overweight or obese status was 5.02 (95% CI: 1.48, 16.99; P ≤ 0.01) times the odds of maintaining or worsening overweight or obese status. In summary, a food store intervention was associated with reduced overweight/obesity and improved obesity-related psychosocial and behavioral factors among those persons most exposed to the intervention on an AI reservation.

Intention to purchase organic food among young consumers: Evidences from a developing nation.

PubMed

Yadav, Rambalak; Pathak, Govind Swaroop

2016-01-01

The present study attempts to investigate the consumer's intention to purchase organic food in the context of a developing nation (India) using the Theory of Planned Behavior (TPB). Further, the study has incorporated additional constructs (moral attitude, health consciousness and environmental concern) in the TPB and measured its appropriateness. Responses were collected from 220 young consumers adopting convenience sampling approach. Data were analyzed using Structural Equation Modeling (SEM) to evaluate the strength of relationship between the constructs. The findings reported that the TPB partially supported the organic food purchase intention. Among the additional constructs incorporated, moral attitude and health consciousness positively influenced the consumer's intention to purchase organic food. The study has supported the inclusion of new constructs in the TPB as it has improved the predictive power of the proposed framework in determining consumer's intention to purchase organic food. Copyright © 2015 Elsevier Ltd. All rights reserved.

Design of a dataway processor for a parallel image signal processing system

NASA Astrophysics Data System (ADS)

Nomura, Mitsuru; Fujii, Tetsuro; Ono, Sadayasu

1995-04-01

Recently, demands for high-speed signal processing have been increasing especially in the field of image data compression, computer graphics, and medical imaging. To achieve sufficient power for real-time image processing, we have been developing parallel signal-processing systems. This paper describes a communication processor called 'dataway processor' designed for a new scalable parallel signal-processing system. The processor has six high-speed communication links (Dataways), a data-packet routing controller, a RISC CORE, and a DMA controller. Each communication link operates at 8-bit parallel in a full duplex mode at 50 MHz. Moreover, data routing, DMA, and CORE operations are processed in parallel. Therefore, sufficient throughput is available for high-speed digital video signals. The processor is designed in a top- down fashion using a CAD system called 'PARTHENON.' The hardware is fabricated using 0.5-micrometers CMOS technology, and its hardware is about 200 K gates.

Digital signal processor and processing method for GPS receivers

NASA Technical Reports Server (NTRS)

Thomas, Jr., Jess B. (Inventor)

1989-01-01

A digital signal processor and processing method therefor for use in receivers of the NAVSTAR/GLOBAL POSITIONING SYSTEM (GPS) employs a digital carrier down-converter, digital code correlator and digital tracking processor. The digital carrier down-converter and code correlator consists of an all-digital, minimum bit implementation that utilizes digital chip and phase advancers, providing exceptional control and accuracy in feedback phase and in feedback delay. Roundoff and commensurability errors can be reduced to extremely small values (e.g., less than 100 nanochips and 100 nanocycles roundoff errors and 0.1 millichip and 1 millicycle commensurability errors). The digital tracking processor bases the fast feedback for phase and for group delay in the C/A, P.sub.1, and P.sub.2 channels on the L.sub.1 C/A carrier phase thereby maintaining lock at lower signal-to-noise ratios, reducing errors in feedback delays, reducing the frequency of cycle slips and in some cases obviating the need for quadrature processing in the P channels. Simple and reliable methods are employed for data bit synchronization, data bit removal and cycle counting. Improved precision in averaged output delay values is provided by carrier-aided data-compression techniques. The signal processor employs purely digital operations in the sense that exactly the same carrier phase and group delay measurements are obtained, to the last decimal place, every time the same sampled data (i.e., exactly the same bits) are processed.

A microcomputer based frequency-domain processor for laser Doppler anemometry

NASA Technical Reports Server (NTRS)

Horne, W. Clifton; Adair, Desmond

1988-01-01

A prototype multi-channel laser Doppler anemometry (LDA) processor was assembled using a wideband transient recorder and a microcomputer with an array processor for fast Fourier transform (FFT) computations. The prototype instrument was used to acquire, process, and record signals from a three-component wind tunnel LDA system subject to various conditions of noise and flow turbulence. The recorded data was used to evaluate the effectiveness of burst acceptance criteria, processing algorithms, and selection of processing parameters such as record length. The recorded signals were also used to obtain comparative estimates of signal-to-noise ratio between time-domain and frequency-domain signal detection schemes. These comparisons show that the FFT processing scheme allows accurate processing of signals for which the signal-to-noise ratio is 10 to 15 dB less than is practical using counter processors.

Parallelising a molecular dynamics algorithm on a multi-processor workstation

NASA Astrophysics Data System (ADS)

Müller-Plathe, Florian

1990-12-01

The Verlet neighbour-list algorithm is parallelised for a multi-processor Hewlett-Packard/Apollo DN10000 workstation. The implementation makes use of memory shared between the processors. It is a genuine master-slave approach by which most of the computational tasks are kept in the master process and the slaves are only called to do part of the nonbonded forces calculation. The implementation features elements of both fine-grain and coarse-grain parallelism. Apart from three calls to library routines, two of which are standard UNIX calls, and two machine-specific language extensions, the whole code is written in standard Fortran 77. Hence, it may be expected that this parallelisation concept can be transfered in parts or as a whole to other multi-processor shared-memory computers. The parallel code is routinely used in production work.

A Bayesian sequential processor approach to spectroscopic portal system decisions

DOE Office of Scientific and Technical Information (OSTI.GOV)

Sale, K; Candy, J; Breitfeller, E

The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waitingmore » for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.« less

Alternative Water Processor Test Development

NASA Technical Reports Server (NTRS)

Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray;

Alternative Water Processor Test Development

NASA Technical Reports Server (NTRS)

Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

2012-01-01

The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

The AIS-5000 parallel processor

DOE Office of Scientific and Technical Information (OSTI.GOV)

Schmitt, L.A.; Wilson, S.S.

1988-05-01

The AIS-5000 is a commercially available massively parallel processor which has been designed to operate in an industrial environment. It has fine-grained parallelism with up to 1024 processing elements arranged in a single-instruction multiple-data (SIMD) architecture. The processing elements are arranged in a one-dimensional chain that, for computer vision applications, can be as wide as the image itself. This architecture has superior cost/performance characteristics than two-dimensional mesh-connected systems. The design of the processing elements and their interconnections as well as the software used to program the system allow a wide variety of algorithms and applications to be implemented. In thismore » paper, the overall architecture of the system is described. Various components of the system are discussed, including details of the processing elements, data I/O pathways and parallel memory organization. A virtual two-dimensional model for programming image-based algorithms for the system is presented. This model is supported by the AIS-5000 hardware and software and allows the system to be treated as a full-image-size, two-dimensional, mesh-connected parallel processor. Performance bench marks are given for certain simple and complex functions.« less

An Overview of Food Patterns and Diet Quality in Qatar: Findings from the National Household Income Expenditure Survey.

PubMed

Al-Thani, Mohammed; Al-Thani, Al-Anoud; Al-Mahdi, Nasser; Al-Kareem, Hefzi; Barakat, Darine; Al-Chetachi, Walaa; Tawfik, Afaf; Akram, Hammad

2017-05-15

Availability of accurate data pertaining to a population's dietary patterns and associated health outcomes is critical for proper development and implementation of related policies. This article is a first attempt to share the food patterns, amounts and diet quality among households (HH) in Qatar. Data from the 2012-2013 Qatar National Household Income and Expenditure Survey (HIES) was used. This cross-sectional survey included 3723 HH (1826 Qatari HH and 1897 non-Qatari HH). Dietary data on monthly amounts food items available at HH according to the nationality was used. The food items were expressed in terms of grams per capita per day and aggregated into groups to examine the food patterns, energy, and adequacy. The overall average amount of purchased food at HH in Qatar was 1885 g/capita/day. Qatari HH purchased more food (2118 g/capita/day) versus non-Qataris (1373 g/capita/day); however, the percentages of the amounts purchased by food types were similar among both nationalities. Average daily energy (kcal) per capita was almost double among Qatari HH (4275 kcal) vs. non-Qatari HH (2424 kcal). The food items under subsidy program for Qatari citizens provided 1753 kcal/capita/day and accounted for 41% of total daily energy. Proteins (29.2), fats (39.2), sodium (3.3), and vitamin C (32.5) had higher than recommended levels of nutrient density (grams per 1000 kcal). Calcium (227), vitamin A (302.3), fiber (2.0), and carbohydrates (132.6) had lower than recommended levels of nutrient energy density (g/1000 kcal). The study predicts unhealthy dietary habits among HH in Qatar and provides useful information for policy makers and healthcare community.

Word Processors and Invention in Technical Writing.

ERIC Educational Resources Information Center

Barker, Thomas T.

1989-01-01

Explores how word processing affects thinking and writing. Examines two myths surrounding word processors and invention in technical writing. Describes how word processing can enhance invention through collaborative writing, templates, and on-screen outlining. (MM)

A Trade Study of Two Membrane-Aerated Biological Water Processors

NASA Technical Reports Server (NTRS)

Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

2011-01-01

Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

Cold plasma inactivation of human pathogens on foods and regulatory status update

USDA-ARS?s Scientific Manuscript database

Contamination of foods with human pathogens such as Salmonella, Listeria monocytogenes, Escherichia coli O157:H7, norovirus, and other pathogens is an ongoing challenge for growers and processors. In recent years, cold plasma has emerged as a promising antimicrobial treatment for fresh and fresh-cut...

The software system development for the TAMU real-time fan beam scatterometer data processors

NASA Technical Reports Server (NTRS)

Clark, B. V.; Jean, B. R.

1980-01-01

A software package was designed and written to process in real-time any one quadrature channel pair of radar scatterometer signals form the NASA L- or C-Band radar scatterometer systems. The software was successfully tested in the C-Band processor breadboard hardware using recorded radar and NERDAS (NASA Earth Resources Data Annotation System) signals as the input data sources. The processor development program and the overall processor theory of operation and design are described. The real-time processor software system is documented and the results of the laboratory software tests, and recommendations for the efficient application of the data processing capabilities are presented.

Realization of a single image haze removal system based on DaVinci DM6467T processor

NASA Astrophysics Data System (ADS)

Liu, Zhuang

2014-10-01

Video monitoring system (VMS) has been extensively applied in domains of target recognition, traffic management, remote sensing, auto navigation and national defence. However the VMS has a strong dependence on the weather, for instance, in foggy weather, the quality of images received by the VMS are distinct degraded and the effective range of VMS is also decreased. All in all, the VMS performs terribly in bad weather. Thus the research of fog degraded images enhancement has very high theoretical and practical application value. A design scheme of a fog degraded images enhancement system based on the TI DaVinci processor is presented in this paper. The main function of the referred system is to extract and digital cameras capture images and execute image enhancement processing to obtain a clear image. The processor used in this system is the dual core TI DaVinci DM6467T - ARM@500MHz+DSP@1GH. A MontaVista Linux operating system is running on the ARM subsystem which handles I/O and application processing. The DSP handles signal processing and the results are available to the ARM subsystem in shared memory.The system benefits from the DaVinci processor so that, with lower power cost and smaller volume, it provides the equivalent image processing capability of a X86 computer. The outcome shows that the system in this paper can process images at 25 frames per second on D1 resolution.

Evaluation of Natural Language Processors.

DTIC Science & Technology

1980-11-01

techniques described. Common practice in describing natural language processors is to describe the programs, then give about 20 examples of correctly...make a decision based on performance as to which approaches are most promising for further research and development. The lack of evaluation leaves...successively more difficult problems. This approach might be compared to children taking achievement tests in school. A 90% score on problems involving

Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

NASA Technical Reports Server (NTRS)

Casasent, D.; Jackson, J.

1986-01-01

A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

[Food and nutritional security: situation analysis of decentralization in the national public policy].

PubMed

Vasconcellos, Ana Beatriz Pinto de Almeida; Moura, Leides Barroso Azevedo de

2018-03-01

The aim of this study was to analyze the situation with the decentralization of the Brazilian National System of Food and Nutritional Security (SISAN), created in 2006 under the Brazilian National Food and Nutritional Security Act (LOSAN). Based on the criteria for joining SISAN, as set out in Decree 7,272 of August 25, 2010, the authors analyzed data from the basic information surveys of the Brazilian Institute of Geography and Statistics, 2014 (Estadic e Munic/2014). The results show that decentralization of SISAN is still incipient at the municipal level, although all the states of Brazil have already joined the system. The social assistance sector has played an outstanding role in coordinating SISAN at the state and municipal levels, while in the latter the health sector has also played a relevant role. The analysis of food and nutritional security activities conducted to date, based on the sources of federal, state, and municipal funds, further shows that the federal sphere has still not played a strong inductive role capable of leading the expansion of SISAN. More effective funding mechanisms and the assignment of responsibilities to the states and municipalities are relevant factors for consolidating the system's state-level base and expanding the municipal base in the search for an identity and capillarity for SISAN.

Comparison of the CENTRM resonance processor to the NITAWL resonance processor in SCALE

DOE Office of Scientific and Technical Information (OSTI.GOV)

Hollenbach, D.F.; Petrie, L.M.

1998-01-01

This report compares the MTAWL and CENTRM resonance processors in the SCALE code system. The cases examined consist of the International OECD/NEA Criticality Working Group Benchmark 20 problem. These cases represent fuel pellets partially dissolved in a borated solution. The assumptions inherent to the Nordheim Integral Treatment, used in MTAWL, are not valid for these problems. CENTRM resolves this limitation by explicitly calculating a problem dependent point flux from point cross sections, which is then used to create group cross sections.

An Efficient Solution Method for Multibody Systems with Loops Using Multiple Processors

NASA Technical Reports Server (NTRS)

Ghosh, Tushar K.; Nguyen, Luong A.; Quiocho, Leslie J.

2015-01-01

This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called "branches" at convenient joints called "connection points", and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

National Food, Nutrition, and Physical Activity Survey of the Portuguese General Population (2015-2016): Protocol for Design and Development.

PubMed

Lopes, Carla; Torres, Duarte; Oliveira, Andreia; Severo, Milton; Guiomar, Sofia; Alarcão, Violeta; Ramos, Elisabete; Rodrigues, Sara; Vilela, Sofia; Oliveira, Luísa; Mota, Jorge; Teixeira, Pedro J; Nicola, Paulo J; Soares, Simão; Andersen, Lene Frost

2018-02-15

The assessment of food consumption data using harmonized methodologies at the European level is fundamental to support the development of public policies. Portugal is one of the countries with the most outdated information on individual food consumption. The objective of this study was to describe the design and methodology of the National Food, Nutrition and Physical Activity Survey, 2015-2016, developed to collect national and regional data on dietary habits, physical activity (PA), and nutritional status, in a representative sample of the Portuguese general population (3 months-84 years). Participants were selected by multistage sampling, using the National Heath Registry as the sampling frame. Data collection, during 12 months, was harmonized according to European guidelines (EU-MENU, European Food Safety Authority [EFSA]). Computer-assisted personal interviewing (CAPI) was performed on a specific electronic platform synchronized with nutritional composition data and considering the FoodEx2 classification system. Dietary assessment was performed using 24-hour recalls (two nonconsecutive, 8-15 days apart) or food diaries in the case of children aged <10 years, complemented with a food propensity questionnaire; PA data (International Physical Activity Questionnaire [IPAQ], the Activity Choice Index [ACI], and 4-days PA diaries); sociodemographic data, and other health-related data were also collected. A sample of 6553 individuals completed the first interview, and 5811 participants completed two dietary assessments. The participation rate among eligible individuals was 33.38% (6553/19,635), considering the first interview, and 29.60% (5811/19,635) for the participants with two completed interviews (about 40% in children and adolescents and 20% in elderly individuals). Results of the survey will be disseminated in national and international scientific journals during 2018-2019. The survey will assist policy planning and management of national and European health

An enhanced Ada run-time system for real-time embedded processors

NASA Technical Reports Server (NTRS)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

A programmable power processor for a 25-kW power module

NASA Technical Reports Server (NTRS)

Lanier, R., Jr.; Kapustka, R. E.; Bush, J. R., Jr.

1979-01-01

A discussion of the power processor for an electrical power system for a 25-kW Power Module that could support the Space Shuttle program during the 1980's and 1990's and which could be a stepping stone to future large space power systems is presented. Trades that led to the selection of a microprocessor-controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Efficiency data from a breadboard programmable power processor are presented, and component selection and design considerations are also discussed.

New Developments in the SCIAMACHY L2 Ground Processor

NASA Astrophysics Data System (ADS)

Gretschany, S.; Lichtenberg, G.; Meringer, M.; Theys, N.; Lerot, C.; Eichmann, K.-U.; Liebing, P.; Noel, S.; Dehn, A.; Fehr, T.

2016-08-01

SCIAMACHY (SCanning Imaging Absorption spectroMeter for Atmospheric ChartographY) aboard ESA's environmental satellite ENVISAT observed the Earth's atmosphere in limb, nadir, and solar/lunar occultation geometries covering the UV-Visible to NIR spectral range. It is a joint project of Germany, the Netherlands and Belgium and was launched in February 2002. SCIAMACHY doubled its originally planned in-orbit lifetime of five years before the communication to ENVISAT was severed in April 2012, and the mission entered its post- operational phase F.The SCIAMACHY Quality Working Group (SQWG) was established in 2007. The group coordinates evolution of algorithms and processors, aiming at improving the quality of the operational data products. University of Bremen (IUP), BIRA, DLR-IMF, SRON (Netherlands Institute for Space Research) and KNMI (The Royal Netherlands Meteorological Institute) are the members providing expertise in this group.In order to preserve the best quality of the outstanding data obtained by SCIAMACHY, data processors are still being updated. This presentation will highlight new developments that are currently being incorporated into the forthcoming Version 7 of ESA's operational Level 2 processor.

Food structure: Its formation and relationships with other properties.

PubMed

Joardder, Mohammad U H; Kumar, Chandan; Karim, M A

2017-04-13

Food materials are complex in nature as it has heterogeneous, amorphous, hygroscopic and porous properties. During processing, microstructure of food materials changes which significantly affects other properties of food. An appropriate understanding of the microstructure of the raw food material and its evolution during processing is critical in order to understand and accurately describe dehydration processes and quality anticipation. This review critically assesses the factors that influence the modification of microstructure in the course of drying of fruits and vegetables. The effect of simultaneous heat and mass transfer on microstructure in various drying methods is investigated. Effects of changes in microstructure on other functional properties of dried foods are discussed. After an extensive review of the literature, it is found that development of food structure significantly depends on fresh food properties and process parameters. Also, modification of microstructure influences the other properties of final product. An enhanced understanding of the relationships between food microstructure, drying process parameters and final product quality will facilitate the energy efficient optimum design of the food processor in order to achieve high-quality food.

SPP: A data base processor data communications protocol

NASA Technical Reports Server (NTRS)

Fishwick, P. A.

1983-01-01

The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

Preliminary study on the potential usefulness of array processor techniques for structural synthesis

NASA Technical Reports Server (NTRS)

Feeser, L. J.

1980-01-01

The effects of the use of array processor techniques within the structural analyzer program, SPAR, are simulated in order to evaluate the potential analysis speedups which may result. In particular the connection of a Floating Point System AP120 processor to the PRIME computer is discussed. Measurements of execution, input/output, and data transfer times are given. Using these data estimates are made as to the relative speedups that can be executed in a more complete implementation on an array processor maxi-mini computer system.

A GaAs vector processor based on parallel RISC microprocessors

NASA Astrophysics Data System (ADS)

Misko, Tim A.; Rasset, Terry L.

A vector processor architecture based on the development of a 32-bit microprocessor using gallium arsenide (GaAs) technology has been developed. The McDonnell Douglas vector processor (MVP) will be fabricated completely from GaAs digital integrated circuits. The MVP architecture includes a vector memory of 1 megabyte, a parallel bus architecture with eight processing elements connected in parallel, and a control processor. The processing elements consist of a reduced instruction set CPU (RISC) with four floating-point coprocessor units and necessary memory interface functions. This architecture has been simulated for several benchmark programs including complex fast Fourier transform (FFT), complex inner product, trigonometric functions, and sort-merge routine. The results of this study indicate that the MVP can process a 1024-point complex FFT at a speed of 112 microsec (389 megaflops) while consuming approximately 618 W of power in a volume of approximately 0.1 ft-cubed.

Novel processor architecture for onboard infrared sensors

NASA Astrophysics Data System (ADS)

Hihara, Hiroki; Iwasaki, Akira; Tamagawa, Nobuo; Kuribayashi, Mitsunobu; Hashimoto, Masanori; Mitsuyama, Yukio; Ochi, Hiroyuki; Onodera, Hidetoshi; Kanbara, Hiroyuki; Wakabayashi, Kazutoshi; Tada, Munehiro

2016-09-01

Infrared sensor system is a major concern for inter-planetary missions that investigate the nature and the formation processes of planets and asteroids. The infrared sensor system requires signal preprocessing functions that compensate for the intensity of infrared image sensors to get high quality data and high compression ratio through the limited capacity of transmission channels towards ground stations. For those implementations, combinations of Field Programmable Gate Arrays (FPGAs) and microprocessors are employed by AKATSUKI, the Venus Climate Orbiter, and HAYABUSA2, the asteroid probe. On the other hand, much smaller size and lower power consumption are demanded for future missions to accommodate more sensors. To fulfill this future demand, we developed a novel processor architecture which consists of reconfigurable cluster cores and programmable-logic cells with complementary atom switches. The complementary atom switches enable hardware programming without configuration memories, and thus soft-error on logic circuit connection is completely eliminated. This is a noteworthy advantage for space applications which cannot be found in conventional re-writable FPGAs. Almost one-tenth of lower power consumption is expected compared to conventional re-writable FPGAs because of the elimination of configuration memories. The proposed processor architecture can be reconfigured by behavioral synthesis with higher level language specification. Consequently, compensation functions are implemented in a single chip without accommodating program memories, which is accompanied with conventional microprocessors, while maintaining the comparable performance. This enables us to embed a processor element on each infrared signal detector output channel.

Single-Scale Retinex Using Digital Signal Processors

NASA Technical Reports Server (NTRS)

Hines, Glenn; Rahman, Zia-Ur; Jobson, Daniel; Woodell, Glenn

2005-01-01

The Retinex is an image enhancement algorithm that improves the brightness, contrast and sharpness of an image. It performs a non-linear spatial/spectral transform that provides simultaneous dynamic range compression and color constancy. It has been used for a wide variety of applications ranging from aviation safety to general purpose photography. Many potential applications require the use of Retinex processing at video frame rates. This is difficult to achieve with general purpose processors because the algorithm contains a large number of complex computations and data transfers. In addition, many of these applications also constrain the potential architectures to embedded processors to save power, weight and cost. Thus we have focused on digital signal processors (DSPs) and field programmable gate arrays (FPGAs) as potential solutions for real-time Retinex processing. In previous efforts we attained a 21 (full) frame per second (fps) processing rate for the single-scale monochromatic Retinex with a TMS320C6711 DSP operating at 150 MHz. This was achieved after several significant code improvements and optimizations. Since then we have migrated our design to the slightly more powerful TMS320C6713 DSP and the fixed point TMS320DM642 DSP. In this paper we briefly discuss the Retinex algorithm, the performance of the algorithm executing on the TMS320C6713 and the TMS320DM642, and compare the results with the TMS320C6711.

Food Insecurity and the Negative Impact on Brazilian Children's Health-Why Does Food Security Matter for Our Future Prosperity? Brazilian National Survey (PNDS 2006/07).

PubMed

Poblacion, Ana Paula; Cook, John T; Marín-León, Leticia; Segall-Corrêa, Ana Maria; Silveira, Jonas A C; Konstantyner, Tulio; Taddei, José Augusto A C

2016-12-01

Food insecurity (FI) refers to limited or uncertain access to food resulting from financial constraints. Numerous studies have shown association between FI and adverse health outcomes among adults and children around the world, but in Brazil, such information is scarce, especially if referring to nationally representative information. To test for an independent association between FI and health outcomes. Most recent Brazilian Demographic and Health Survey using nationally representative complex probability sampling. Participants were 3923 children <5 years of age, each representing a household. Data from the validated Brazilian Food Insecurity Scale were dichotomized as food secure (food security/mild FI) or food insecure (moderate FI/severe FI). Poisson regression was used to test for associations between FI and various health indicators. Models adjusted for socioeconomic and demographic variables showed that children hospitalized for pneumonia or diarrhea were 30% more prevalent in FI households (adjusted prevalence ratio [aPR]: 1.3; 1.1-1.6). Underweight children were 40% more prevalent in FI households (aPR: 1.4; 1.1-1.7). Children who didn't eat meat and fruits and vegetables every day were 20% and 70% more prevalent in FI households (aPR: 1.2; 1.1-1.4 and aPR: 1.7; 1.3-2.3), respectively. Children who grow up in food-insecure households have been shown to have worse health conditions than those in food-secure households. Consequently, their human capital accumulation and work-life productivity are likely to be reduced in the future, leading them into adulthood less capable of generating sufficient income, resulting in a cycle of intergenerational poverty and FI. © The Author(s) 2016.

Autonomous Telemetry Collection for Single-Processor Small Satellites

NASA Technical Reports Server (NTRS)

Speer, Dave

2003-01-01

For the Space Technology 5 mission, which is being developed under NASA's New Millennium Program, a single spacecraft processor will be required to do on-board real-time computations and operations associated with attitude control, up-link and down-link communications, science data processing, solid-state recorder management, power switching and battery charge management, experiment data collection, health and status data collection, etc. Much of the health and status information is in analog form, and each of the analog signals must be routed to the input of an analog-to-digital converter, converted to digital form, and then stored in memory. If the micro-operations of the analog data collection process are implemented in software, the processor may use up a lot of time either waiting for the analog signal to settle, waiting for the analog-to-digital conversion to complete, or servicing a large number of high frequency interrupts. In order to off-load a very busy processor, the collection and digitization of all analog spacecraft health and status data will be done autonomously by a field-programmable gate array that can configure the analog signal chain, control the analog-to-digital converter, and store the converted data in memory.

Advanced development of a programmable power processor

NASA Technical Reports Server (NTRS)

Lukens, F. E.; Lanier, J. R., Jr.; Kapustka, R. E.; Graves, J.

1980-01-01

The need for the development of a multipurpose flexible programmable power processor (PPP) has increased significantly in recent years to reduce ever rising development costs. One of the program requirements the PPP specification will cover is the 25 kW power module power conversion needs. The 25 kW power module could support the Space Shuttle program during the 1980s and 1990s and could be the stepping stone to future large space programs. Trades that led to selection of a microprocessor controlled power processor are briefly discussed. Emphasis is given to the power processing equipment that uses a microprocessor to provide versatility that allows multiple use and to provide for future growth by reprogramming output voltage to a higher level (to 120 V from 30 V). Component selection and design considerations are also discussed.

Software reconfigurable processor technologies: the key to long-life infrastructure for future space missions

NASA Technical Reports Server (NTRS)

Srinivasan, J.; Farrington, A.; Gray, A.

2001-01-01

They present an overview of long-life reconfigurable processor technologies and of a specific architecture for implementing a software reconfigurable (software-defined) network processor for space applications.

Clinical Validation of a Sound Processor Upgrade in Direct Acoustic Cochlear Implant Subjects

PubMed Central

Kludt, Eugen; D’hondt, Christiane; Lenarz, Thomas; Maier, Hannes

2017-01-01

Objective: The objectives of the investigation were to evaluate the effect of a sound processor upgrade on the speech reception threshold in noise and to collect long-term safety and efficacy data after 2½ to 5 years of device use of direct acoustic cochlear implant (DACI) recipients. Study Design: The study was designed as a mono-centric, prospective clinical trial. Setting: Tertiary referral center. Patients: Fifteen patients implanted with a direct acoustic cochlear implant. Intervention: Upgrade with a newer generation of sound processor. Main Outcome Measures: Speech recognition test in quiet and in noise, pure tone thresholds, subject-reported outcome measures. Results: The speech recognition in quiet and in noise is superior after the sound processor upgrade and stable after long-term use of the direct acoustic cochlear implant. The bone conduction thresholds did not decrease significantly after long-term high level stimulation. Conclusions: The new sound processor for the DACI system provides significant benefits for DACI users for speech recognition in both quiet and noise. Especially the noise program with the use of directional microphones (Zoom) allows DACI patients to have much less difficulty when having conversations in noisy environments. Furthermore, the study confirms that the benefits of the sound processor upgrade are available to the DACI recipients even after several years of experience with a legacy sound processor. Finally, our study demonstrates that the DACI system is a safe and effective long-term therapy. PMID:28406848

Modeling Land Application of Food-Processing Wastewater in the Central Valley, California

NASA Astrophysics Data System (ADS)

Rubin, Y.; Benito, P.; Miller, G.; McLaughlin, J.; Hou, Z.; Hermanowicz, S.; Mayer, U.

2007-12-01

California's Central Valley contains over 640 food-processing plants, serving a multi-billion dollar agricultural industry. These processors consume approximately 7.9 x 107 m3 of water per year. Approximately 80% of these processors discharge the resulting wastewater, which is typically high in organic matter, nitrogen, and salts, to land, and many of these use land application as a treatment method. Initial investigations revealed elevated salinity levels to be the most common form of groundwater degradation near land application sites, followed by concentrations of nitrogen compounds, namely ammonia and nitrate. Enforcement actions have been taken against multiple food processors, and the regulatory boards have begun to re-examine the land disposal permitting process. This paper summarizes a study that was commissioned in support of these actions. The study has multiple components which will be reviewed briefly, including: (1) characterization of the food-processing related waste stream; (2) fate and transport of the effluent waste stream in the unsaturated zone at the land application sites; (3) fate and transport of the effluent waste stream at the regional scale; (4) predictive uncertainty due to spatial variability and data scarcity at the land application sites and at the regional scale; (5) problem mitigation through off-site and in-situ actions; (6) long-term solutions. The emphasis of the talk will be placed on presenting and demonstrating a stochastic framework for modeling the transport and attenuation of these wastes in the vadose zone and in the saturated zone, and the related site characterization needs, as affected by site conditions, water table depth, waste water application rate, and waste constituent concentrations.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

PubMed

Cheung, Kit; Schultz, Simon R; Luk, Wayne

2015-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

PubMed Central

Cheung, Kit; Schultz, Simon R.; Luk, Wayne

2016-01-01

NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation. PMID:26834542

Low-Latency Embedded Vision Processor (LLEVS)

DTIC Science & Technology

2016-03-01

26 3.2.3 Task 3 Projected Performance Analysis of FPGA- based Vision Processor ........... 31 3.2.3.1 Algorithms Latency Analysis ...Programmable Gate Array Custom Hardware for Real- Time Multiresolution Analysis . ............................................... 35...conduct data analysis for performance projections. The data acquired through measurements , simulation and estimation provide the requisite platform for

Word Processors and the Teaching of Writing.

ERIC Educational Resources Information Center

Crozier, D. S. R.

1986-01-01

Word processors can assist teachers and students by focusing on writing as a process, rather than a product. Word processing breaks writing up into manageable chunks that permit writing skills to develop in an integraged manner. (10 references) (CJH)

An Overview of Food Patterns and Diet Quality in Qatar: Findings from the National Household Income Expenditure Survey

PubMed Central

Al-Thani, Mohammed; Al-Thani, Al-Anoud; Al-Mahdi, Nasser; Al-Kareem, Hefzi; Barakat, Darine; Al-Chetachi, Walaa; Tawfik, Afaf

2017-01-01

Introduction Availability of accurate data pertaining to a population’s dietary patterns and associated health outcomes is critical for proper development and implementation of related policies. This article is a first attempt to share the food patterns, amounts and diet quality among households (HH) in Qatar. Methods Data from the 2012-2013 Qatar National Household Income and Expenditure Survey (HIES) was used. This cross-sectional survey included 3723 HH (1826 Qatari HH and 1897 non-Qatari HH). Dietary data on monthly amounts food items available at HH according to the nationality was used. The food items were expressed in terms of grams per capita per day and aggregated into groups to examine the food patterns, energy, and adequacy. Results The overall average amount of purchased food at HH in Qatar was 1885 g/capita/day. Qatari HH purchased more food (2118 g/capita/day) versus non-Qataris (1373 g/capita/day); however, the percentages of the amounts purchased by food types were similar among both nationalities. Average daily energy (kcal) per capita was almost double among Qatari HH (4275 kcal) vs. non-Qatari HH (2424 kcal). The food items under subsidy program for Qatari citizens provided 1753 kcal/capita/day and accounted for 41% of total daily energy. Proteins (29.2), fats (39.2), sodium (3.3), and vitamin C (32.5) had higher than recommended levels of nutrient density (grams per 1000 kcal). Calcium (227), vitamin A (302.3), fiber (2.0), and carbohydrates (132.6) had lower than recommended levels of nutrient energy density (g/1000 kcal). Conclusions The study predicts unhealthy dietary habits among HH in Qatar and provides useful information for policy makers and healthcare community. PMID:28630807

Compact gasoline fuel processor for passenger vehicle APU

NASA Astrophysics Data System (ADS)

Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

A Food Store–Based Environmental Intervention Is Associated with Reduced BMI and Improved Psychosocial Factors and Food-Related Behaviors on the Navajo Nation123

PubMed Central

Gittelsohn, Joel; Kim, Elizabeth M.; He, Siran; Pardilla, Marla

2013-01-01

The prevalence of obesity is significantly higher among American Indians (AIs) and is associated with increased rates of diabetes, hypertension, and cardiovascular disease. We implemented a 14-mo intervention trial (Navajo Healthy Stores) on the Navajo Nation that sought to increase availability of healthier foods in local food stores and to promote these foods at the point of purchase and through community media. We divided the Navajo Nation into 10 store regions, half of which were randomized to intervention and half to comparison. We evaluated the program by using a pre-post sample of systematically sampled adult Navajo consumers (baseline, n = 276; postintervention, n = 145). Intervention impact was examined by analyzing pre-post differences by intervention group and by intervention exposure level. When intervention and comparison groups were compared, only body mass index (BMI) showed a trend toward impact of the intervention (P = 0.06). However, greater exposure to the intervention was associated with significantly reduced BMI (P ≤ 0.05) and improved healthy food intentions (P ≤ 0.01), healthy cooking methods (P ≤ 0.05), and healthy food getting (P ≤ 0.01). With increasing exposure, the odds of improving overweight or obese status was 5.02 (95% CI: 1.48, 16.99; P ≤ 0.01) times the odds of maintaining or worsening overweight or obese status. In summary, a food store intervention was associated with reduced overweight/obesity and improved obesity-related psychosocial and behavioral factors among those persons most exposed to the intervention on an AI reservation. PMID:23864511

Design for a Manufacturing Method for Memristor-Based Neuromorphic Computing Processors

DTIC Science & Technology

2013-03-01

DESIGN FOR A MANUFACTURING METHOD FOR MEMRISTOR- BASED NEUROMORPHIC COMPUTING PROCESSORS UNIVERSITY OF PITTSBURGH MARCH 2013...BASED NEUROMORPHIC COMPUTING PROCESSORS 5a. CONTRACT NUMBER FA8750-11-1-0271 5b. GRANT NUMBER N/A 5c. PROGRAM ELEMENT NUMBER 62788F 6. AUTHOR(S...synapses and implemented a neuromorphic computing system based on our proposed synapse designs. The robustness of our system is also evaluated by

National Nutrient Database for Standard Reference - Find Nutrient Value of Common Foods by Nutrient

MedlinePlus

... grams Household * required field ​ USDA Food Composition Databases Software developed by the National Agricultural Library v.3.9.4.1 2018-06-11 NAL Home | USDA.gov | Agricultural Research Service | Plain Language | FOIA | Accessibility Statement | Information Quality | Privacy ...

SPECIAL ISSUE ON OPTICAL PROCESSING OF INFORMATION: Semiconductor-laser Fourier processors of electric signals

NASA Astrophysics Data System (ADS)

Blok, A. S.; Bukhenskii, A. F.; Krupitskii, É. I.; Morozov, S. V.; Pelevin, V. Yu; Sergeenko, T. N.; Yakovlev, V. I.

1995-10-01

An investigation is reported of acousto-optical and fibre-optic Fourier processors of electric signals, based on semiconductor lasers. A description is given of practical acousto-optical processors with an analysis band 120 MHz wide, a resolution of 200 kHz, and 7 cm × 8 cm × 18 cm dimensions. Fibre-optic Fourier processors are considered: they represent a new class of devices which are promising for the processing of gigahertz signals.

Prepared Food Availability in U.S. Food Stores: A National Study.

PubMed

Zenk, Shannon N; Powell, Lisa M; Isgor, Zeynep; Rimkus, Leah; Barker, Dianne C; Chaloupka, Frank J

2015-10-01

Prepared, ready-to-eat foods comprise a significant part of Americans' diets and are increasingly obtained from food stores. Yet, little is known about the availability and healthfulness of prepared, ready-to-eat food offerings at stores. This study examines associations among community characteristics (racial/ethnic composition, poverty level, urbanicity) and availability of both healthier and less-healthy prepared foods in U.S. supermarkets, grocery stores, and convenience stores. Observational data were collected from 4,361 stores in 317 communities spanning 42 states in 2011 and 2012. Prepared food availability was assessed via one healthier food (salads or salad bar), three less-healthy items (pizza, hot dog/hamburger, taco/burrito/taquito), and one cold sandwich item. In 2014, multivariable generalized linear models were used to test associations with community characteristics. Overall, 63.6% of stores sold prepared foods, with 20.0% offering prepared salads and 36.4% offering at least one less-healthy item. Rural stores were 26% less likely to carry prepared salads (prevalence ratio [PR]=0.74, 95% CI=0.62, 0.88) and 14% more likely to carry at least one less-healthy prepared food item (PR=1.14, 95% CI=1.00, 1.30). Convenience stores in high-poverty communities were less likely to carry prepared salads than those in low-poverty communities (PR=0.64, 95% CI=0.47, 0.87). Among supermarkets, prepared salads were more likely to be carried in majority-white, low-poverty communities than in non-white, high-poverty communities. Increasing the healthfulness of prepared foods within stores may offer an important opportunity to improve the food environment. Copyright © 2015 American Journal of Preventive Medicine. Published by Elsevier Inc. All rights reserved.

Do food blogs serve as a source of nutritionally balanced recipes? An analysis of 6 popular food blogs.

PubMed

Schneider, Elizabeth P; McGovern, Emily E; Lynch, Colleen L; Brown, Lisa S

2013-01-01

To determine whether sampled food blogs provide nutritionally balanced recipes. Two entree recipes per season, per year (2010-2011) were selected from 6 highly ranked food blogs (n = 96). Food Processor Nutrition and Fitness software was used to analyze sodium, saturated fat, and energy content. Analysis was separated by protein type (vegetarian, poultry, red meat, and seafood). Recipes met energy recommendations but were excessive in saturated fat and sodium. Vegetarian and seafood recipes were significantly lower in risk nutrients compared with red meat and poultry recipes. Red meat recipes were not significantly different from poultry recipes for risk nutrients studied; poultry recipes were higher in sodium and energy compared with red meat recipes. The public should be aware of the nutritional limitations of popular food blogs; dietitians could assist in modifying blog recipes for individuals and partner with bloggers to improve the nutritional profile of recipes. Copyright © 2013 Society for Nutrition Education and Behavior. Published by Elsevier Inc. All rights reserved.

Attitudes and beliefs on the establishment of a national food safety authority in Cyprus. A population-based survey.

PubMed

Hadjigeorgiou, Andreas; Talias, Michael A; Soteriades, Elpidoforos S; Philalithis, Anastasios; Psaroulaki, Anna; Gikas, Achilleas; Tselentis, Yiannis

2014-04-01

Cyprus does not have a National Food Safety Authority (NFSA), but a multi-level, fragmented system with responsibilities divided among different ministries and governmental agencies, frequently impeding efforts to effectively manage food risks by duplication and overlapping of responsibilities. A population-based survey was carried out to determine the beliefs and attitudes of interested parties concerning the establishment of a NFSA in Cyprus. Information was collected using a random stratified sampling design and a structured questionnaire. A total of 868 questionnaires were collected (704 from regular consumers, 154 from food businesses' representatives, and 10 from public services' directors or acting head officers). About 11% of food businesses' representatives and 45% of consumers reported that they did not know which public authorities are responsible for food control. Moreover, 2 out of 10 (17%) of responders from public agencies, 70% from food businesses and 91% from consumers, although not aware of ongoing efforts to establish a food safety authority in Cyprus (currently under consideration), were supportive of the idea [8 out of 10 (83%) of responders from public services, 93% from food businesses, and 89% of consumers]. Finally, 7 out of 10 (67%) from the public agencies and 84% of representatives from food businesses agreed with the separation of risk assessment from risk management activities. Public opinion in Cyprus as well as public agencies and food businesses' representatives support the establishment of a single independent national food safety authority in Cyprus based on the European paradigm including the division of risk activities. Copyright © 2014 Elsevier Ltd. All rights reserved.

Sustaining food self-sufficiency of a nation: The case of Sri Lankan rice production and related water and fertilizer demands.

PubMed

Davis, Kyle Frankel; Gephart, Jessica A; Gunda, Thushara

2016-04-01

Rising human demand and climatic variability have created greater uncertainty regarding global food trade and its effects on the food security of nations. To reduce reliance on imported food, many countries have focused on increasing their domestic food production in recent years. With clear goals for the complete self-sufficiency of rice production, Sri Lanka provides an ideal case study for examining the projected growth in domestic rice supply, how this compares to future national demand, and what the associated impacts from water and fertilizer demands may be. Using national rice statistics and estimates of intensification, this study finds that improvements in rice production can feed 25.3 million Sri Lankans (compared to a projected population of 23.8 million people) by 2050. However, to achieve this growth, consumptive water use and nitrogen fertilizer application may need to increase by as much as 69 and 23 %, respectively. This assessment demonstrates that targets for maintaining self-sufficiency should better incorporate avenues for improving resource use efficiency.

The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor

DTIC Science & Technology

2015-06-13

The Berkeley Out-of-Order Machine (BOOM): An Industry- Competitive, Synthesizable, Parameterized RISC-V Processor Christopher Celio David A...Synthesizable, Parameterized RISC-V Processor Christopher Celio, David Patterson, and Krste Asanović University of California, Berkeley, California 94720...Order Machine BOOM is a synthesizable, parameterized, superscalar out- of-order RISC-V core designed to serve as the prototypical baseline processor

The Use of a Microcomputer Based Array Processor for Real Time Laser Velocimeter Data Processing

NASA Technical Reports Server (NTRS)

Meyers, James F.

1990-01-01

The application of an array processor to laser velocimeter data processing is presented. The hardware is described along with the method of parallel programming required by the array processor. A portion of the data processing program is described in detail. The increase in computational speed of a microcomputer equipped with an array processor is illustrated by comparative testing with a minicomputer.

The Food Marketing Institute and the National Council of Chain Restaurants: animal welfare and the retail food industry in the United States of America.

PubMed

Brown, K H; Hollingsworth, J

2005-08-01

In order to achieve real change, there must be a motivating force and all the stakeholders need to be involved. This is the premise of the animal welfare programme developed for the food retail, wholesale and chain restaurant industries in the United States of America (USA) by the Food Marketing Institute (FMI) and the National Council of Chain Restaurants (NCCR). This paper outlines a collaborative process that retailers and producers in the USA are using to enhance the care and welfare of animals in commercial food production. Although the efforts of the FMI and the NCCR are still underway, the process provides one example of how different parts of the food production system can work together to achieve positive change.

Increasing homogeneity in global food supplies and the implications for food security

PubMed Central

Khoury, Colin K.; Bjorkman, Anne D.; Dempewolf, Hannes; Ramirez-Villegas, Julian; Guarino, Luigi; Jarvis, Andy; Rieseberg, Loren H.; Struik, Paul C.

2014-01-01

The narrowing of diversity in crop species contributing to the world’s food supplies has been considered a potential threat to food security. However, changes in this diversity have not been quantified globally. We assess trends over the past 50 y in the richness, abundance, and composition of crop species in national food supplies worldwide. Over this period, national per capita food supplies expanded in total quantities of food calories, protein, fat, and weight, with increased proportions of those quantities sourcing from energy-dense foods. At the same time the number of measured crop commodities contributing to national food supplies increased, the relative contribution of these commodities within these supplies became more even, and the dominance of the most significant commodities decreased. As a consequence, national food supplies worldwide became more similar in composition, correlated particularly with an increased supply of a number of globally important cereal and oil crops, and a decline of other cereal, oil, and starchy root species. The increase in homogeneity worldwide portends the establishment of a global standard food supply, which is relatively species-rich in regard to measured crops at the national level, but species-poor globally. These changes in food supplies heighten interdependence among countries in regard to availability and access to these food sources and the genetic resources supporting their production, and give further urgency to nutrition development priorities aimed at bolstering food security. PMID:24591623

Position of the academy of nutrition and dietetics: nutrition security in developing nations: sustainable food, water, and health.

PubMed

Nordin, Stacia M; Boyle, Marie; Kemmer, Teresa M

2013-04-01

It is the position of the Academy of Nutrition and Dietetics that all people should have consistent access to an appropriately nutritious diet of food and water, coupled with a sanitary environment, adequate health services, and care that ensure a healthy and active life for all household members. The Academy supports policies, systems, programs, and practices that work with developing nations to achieve nutrition security and self-sufficiency while being environmentally and economically sustainable. For nations to achieve nutrition security, all people must have access to a variety of nutritious foods and potable drinking water; knowledge, resources, and skills for healthy living; prevention, treatment, and care for diseases affecting nutrition status; and safety-net systems during crisis situations, such as natural disasters or deleterious social and political systems. More than 2 billion people are micronutrient deficient; 1.5 billion people are overweight or obese; 870 million people have inadequate food energy intake; and 783 million people lack potable drinking water. Adequate nutrient intake is a concern, independent of weight status. Although this article focuses on nutritional deficiencies in developing nations, global solutions for excesses and deficiencies need to be addressed. In an effort to achieve nutrition security, lifestyles, policies, and systems (eg, food, water, health, energy, education/knowledge, and economic) contributing to sustainable resource use, environmental management, health promotion, economic stability, and positive social environments are required. Food and nutrition practitioners can get involved in promoting and implementing effective and sustainable policies, systems, programs, and practices that support individual, community, and national efforts. Copyright © 2013 Academy of Nutrition and Dietetics. Published by Elsevier Inc. All rights reserved.

A model for tracking concentration of chemical compounds within a tank of an automatic film processor.

PubMed

Sobol, Wlad T

2002-01-01

A simple kinetic model that describes the time evolution of the chemical concentration of an arbitrary compound within the tank of an automatic film processor is presented. It provides insights into the kinetics of chemistry concentration inside the processor's tank; the results facilitate the tasks of processor tuning and quality control (QC). The model has successfully been used in several troubleshooting sessions of low-volume mammography processors for which maintaining consistent QC tracking was difficult due to fluctuations of bromide levels in the developer tank.

Formal design specification of a Processor Interface Unit

NASA Technical Reports Server (NTRS)

Fura, David A.; Windley, Phillip J.; Cohen, Gerald C.

1992-01-01

This report describes work to formally specify the requirements and design of a processor interface unit (PIU), a single-chip subsystem providing memory-interface bus-interface, and additional support services for a commercial microprocessor within a fault-tolerant computer system. This system, the Fault-Tolerant Embedded Processor (FTEP), is targeted towards applications in avionics and space requiring extremely high levels of mission reliability, extended maintenance-free operation, or both. The need for high-quality design assurance in such applications is an undisputed fact, given the disastrous consequences that even a single design flaw can produce. Thus, the further development and application of formal methods to fault-tolerant systems is of critical importance as these systems see increasing use in modern society.

Biological Water Processor and Forward Osmosis Secondary Treatment

NASA Technical Reports Server (NTRS)

Shull, Sarah; Meyer, Caitlin

2014-01-01

The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

Automatic Recognition of Phonemes Using a Syntactic Processor for Error Correction.

DTIC Science & Technology

1980-12-01

OF PHONEMES USING A SYNTACTIC PROCESSOR FOR ERROR CORRECTION THESIS AFIT/GE/EE/8D-45 Robert B. ’Taylor 2Lt USAF Approved for public release...distribution unlimilted. AbP AFIT/GE/EE/ 80D-45 AUTOMATIC RECOGNITION OF PHONEMES USING A SYNTACTIC PROCESSOR FOR ERROR CORRECTION THESIS Presented to the...Testing ..................... 37 Bayes Decision Rule for Minimum Error ........... 37 Bayes Decision Rule for Minimum Risk ............ 39 Mini Max Test

Detailed description of the HP-9825A HFRMP trajectory processor (TRAJ)

NASA Technical Reports Server (NTRS)

Kindall, S. M.; Wilson, S. W.

1979-01-01

The computer code for the trajectory processor of the HP-9825A High Fidelity Relative Motion Program is described in detail. The processor is a 12-degrees-of-freedom trajectory integrator which can be used to generate digital and graphical data describing the relative motion of the Space Shuttle Orbiter and a free-flying cylindrical payload. Coding standards and flow charts are given and the computational logic is discussed.

A fully integrated mixed-signal neural processor for implantable multichannel cortical recording.

PubMed

Sodagar, Amir M; Wise, Kensall D; Najafi, Khalil

2007-06-01

A 64-channel neural processor has been developed for use in an implantable neural recording microsystem. In the Scan Mode, the processor is capable of detecting neural spikes by programmable positive, negative, or window thresholding. Spikes are tagged with their associated channel addresses and formed into 18-bit data words that are sent serially to the external host. In the Monitor Mode, two channels can be selected and viewed at high resolution for studies where the entire signal is of interest. The processor runs from a 3-V supply and a 2-MHz clock, with a channel scan rate of 64 kS/s and an output bit rate of 2 Mbps.

Food Insecurity and Depression Among Adults With Diabetes: Results From the National Health and Nutrition Examination Survey (NHANES).

PubMed

Montgomery, Joshua; Lu, Juan; Ratliff, Scott; Mezuk, Briana

2017-06-01

Purpose While both food insecurity and depression have been linked to risk of type 2 diabetes, little is known about the relationship between food insecurity and depression among adults with diabetes. Research Design and Methods Cross-sectional analyses of the National Health and Nutrition Examination Survey (2011-2014), a nationally representative, population-based survey. Analytic sample was limited to adults aged ≥20 with diabetes determined by either fasting plasma glucose (≥126 mg/dL) or self-report (n = 1724) and adults age ≥20 with prediabetes determined by fasting plasma glucose (100-125 mg/dL) or self-report (n = 2004). Food insecurity was measured using the US Food Security Survey Module. Depression was assessed using the Patient Health Questionnaire-9 (PHQ-9). Logistic regression was used to assess the relationship between food insecurity and depression while accounting for sociodemographic characteristics and health behaviors. Results Approximately 10% of individuals with diabetes and 8.5% of individuals with prediabetes had severe food insecurity in the past year; an additional 20.3% of individuals with diabetes and 14.3% of those with prediabetes had mild food insecurity. Among individuals with diabetes, both mild and severe food insecurity were associated with elevated odds of depression These relationships were similar in magnitude among individuals with prediabetes. Conclusions Food insecurity is significantly associated with depressive symptoms in people with diabetes and prediabetes. Results point to the need to address economic issues in conjunction with psychosocial issues for comprehensive diabetes care.

Global synchronization of parallel processors using clock pulse width modulation

DOEpatents

Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

2013-04-02

A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

Space Station Water Processor Process Pump

NASA Technical Reports Server (NTRS)

Parker, David

1995-01-01

This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

Phase Fluctuation Enhanced Adaptive Processor

DTIC Science & Technology

2000-02-04

Serial Number Filing Date Inventor 09/498.348 4 February 2000 Ronald A. Wagstaff Jackson A. Mobbs NOTICE The above identified patent...phase angle, as describedin Phase Variations in a Fluctuation Based Processor, Ronald A. Wagstaff and Jacob George, SPIE Vol. 2751, April 1996, pages...16 17 18 19 20 21 22 Docket No.: N.C. 79,518 PATENT APPT TPATT™ Inventor’s Name: Wagstaff , et al APPLICATION 1 have medium phase fluctuations

Prevention and control of food safety risks: the role of governments, food producers, marketers, and academia.

PubMed

Lupien, John R

2007-01-01

Food systems are rapidly changing as world population grows, increasing urbanization occurs, consumer tastes and preferences change and differ in various countries and cultures, large scale food production increases, and food imports and exports grow in volume and value. Consumers in all countries have become more insistent that foods available in the marketplace are of good quality and safe, and do not pose risks to them and their families. Publicity about food risk problems and related risks, including chemical and microbiological contamination of foods, mad-cow disease, avian flu, industrial chemical contamination all have made consumers and policy makers more aware of the need of the control of food safety risk factors in all countries. To discuss changes in food systems, and in consumer expectations, that have placed additional stress on the need for better control of food safety risks. Food producers, processors, and marketers have additional food law and regulations to meet; government agencies must increase monitoring and enforcement of adequate food quality and safety legislation and coordinate efforts between agriculture, health, trade, justice and customs agencies; and academia must take action to strengthen the education of competent food legislation administrators, inspectorate, and laboratory personnel for work in government and industry, including related food and food safety research . Both Government and the food industry must assure that adequate control programs are in place to control the quality and safety of all foods, raw or processed, throughout the food chain from production to final consumption. This includes appropriate laboratory facilities to perform necessary analysis of foods for risk and quality factors, and to carry out a wide range of food science, toxicological and related research.

The effect of governance mechanisms on food safety in the supply chain: Evidence from the Lebanese dairy sector.

PubMed

Abebe, Gumataw K; Chalak, Ali; Abiad, Mohamad G

2017-07-01

Food safety is a key public health issue worldwide. This study aims to characterise existing governance mechanisms - governance structures (GSs) and food safety management systems (FSMSs) - and analyse the alignment thereof in detecting food safety hazards, based on empirical evidence from Lebanon. Firm-to-firm and public baseline are the dominant FSMSs applied in a large-scale, while chain-wide FSMSs are observed only in a small-scale. Most transactions involving farmers are relational and market-based in contrast to (large-scale) processors, which opt for hierarchical GSs. Large-scale processors use a combination of FSMSs and GSs to minimise food safety hazards albeit potential increase in coordination costs; this is an important feature of modern food supply chains. The econometric analysis reveals contract period, on-farm inspection and experience having significant effects in minimising food safety hazards. However, the potential to implement farm-level FSMS is influenced by formality of the contract, herd size, trading partner choice, and experience. Public baseline FSMSs appear effective in controlling food safety hazards; however, this may not be viable due to the scarcity of public resources. We suggest public policies to focus on long-lasting governance mechanisms by introducing incentive schemes and farm-level FSMSs by providing loans and education to farmers. © 2016 Society of Chemical Industry. © 2016 Society of Chemical Industry.

Evaluation of fault-tolerant parallel-processor architectures over long space missions

NASA Technical Reports Server (NTRS)

Johnson, Sally C.

1989-01-01

The impact of a five year space mission environment on fault-tolerant parallel processor architectures is examined. The target application is a Strategic Defense Initiative (SDI) satellite requiring 256 parallel processors to provide the computation throughput. The reliability requirements are that the system still be operational after five years with .99 probability and that the probability of system failure during one-half hour of full operation be less than 10(-7). The fault tolerance features an architecture must possess to meet these reliability requirements are presented, many potential architectures are briefly evaluated, and one candidate architecture, the Charles Stark Draper Laboratory's Fault-Tolerant Parallel Processor (FTPP) is evaluated in detail. A methodology for designing a preliminary system configuration to meet the reliability and performance requirements of the mission is then presented and demonstrated by designing an FTPP configuration.

Frequency-multiplexed and pipelined iterative optical systolic array processors

NASA Technical Reports Server (NTRS)

Casasent, D.; Jackson, J.; Neuman, C.

1983-01-01

Optical matrix processors using acoustooptic transducers are described, with emphasis on new systolic array architectures using frequency multiplexing in addition to space and time multiplexing. A Kalman filtering application is considered in a case study from which the operations required on such a system can be defined. This also serves as a new and powerful application for iterative optical processors. The importance of pipelining the data flow and the ordering of the operations performed in a specific application of such a system are also noted. Several examples of how to effectively achieve this are included. A new technique for handling bipolar data on such architectures is also described.

A floating-point/multiple-precision processor for airborne applications

NASA Technical Reports Server (NTRS)

Yee, R.

1982-01-01

A compact input output (I/O) numerical processor capable of performing floating-point, multiple precision and other arithmetic functions at execution times which are at least 100 times faster than comparable software emulation is described. The I/O device is a microcomputer system containing a 16 bit microprocessor, a numerical coprocessor with eight 80 bit registers running at a 5 MHz clock rate, 18K random access memory (RAM) and 16K electrically programmable read only memory (EPROM). The processor acts as an intelligent slave to the host computer and can be programmed in high order languages such as FORTRAN and PL/M-86.

Direct RF A-O Processor Spectrum Analyzer.

DTIC Science & Technology

1981-08-01

The primary objective was to develop and demonstrate design approach, along with the associated processing technologies, for a wideband acousto optic Bragg...cell spectrum analyzer. The signal processor used to demonstrate feasibility of the technical approach consisted of two bulk wave acousto optic deflectors

Dyslipidemia and Food Security in Low-Income US Adolescents: National Health and Nutrition Examination Survey, 2003-2010.

PubMed

Tester, June M; Laraia, Barbara A; Leung, Cindy W; Mietus-Snyder, Michele L

2016-02-11

Low levels of food security are associated with dyslipidemia and chronic disease in adults, particularly in women. There is a gap in knowledge about the relationship between food security among youth and dyslipidemia and chronic disease. We investigated the relationship between food security status and dyslipidemia among low-income adolescents. We analyzed data from adolescents aged 12 to 18 years (N = 1,072) from households with incomes at or below 200% of the federal poverty level from the National Health and Nutrition Examination Survey (NHANES) 2003-2010. We used logistic regression to examine the relationship between household food security status and the odds of having abnormalities with fasting total cholesterol (TC), low-density lipoprotein cholesterol (LDL-C), serum triglycerides (TGs), high-density lipoprotein cholesterol (HDL-C), TG/HDL-C ratio, and apolipoprotein B (Apo B). Models included age, sex, race/ethnicity, smoking status, partnered status in the household, and maternal education, with additional adjustment for adiposity. Household food security status was not associated with elevated TC or LDL-C. Adolescents with marginal food security were more likely than food-secure peers to have elevated TGs (odds ratio [OR] = 1.86; 95% confidence interval [CI], 1.14-3.05), TG/HDL-C ratio (OR = 1.74; 95% CI, 1.11-2.82), and Apo B (OR = 1.98; 95% CI, 1.17-3.36). Female adolescents with marginal food security had greater odds than male adolescents of having low HDL-C (OR = 2.69; 95% CI, 1.14-6.37). No elevated odds of dyslipidemia were found for adolescents with low or very low food security. Adjustment for adiposity did not attenuate estimates. In this nationally representative sample, low-income adolescents living in households with marginal food security had increased odds of having a pattern consistent with atherogenic dyslipidemia, which represents a cardiometabolic burden above their risk from adiposity alone.

The application of charge-coupled device processors in automatic-control systems

NASA Technical Reports Server (NTRS)

Mcvey, E. S.; Parrish, E. A., Jr.

1977-01-01

The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

7 CFR 201.73 - Processors and processing of all classes of certified seed.

Code of Federal Regulations, 2010 CFR

2010-01-01

... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2010-01-01 2010-01-01 false Processors and processing of all classes of certified...

7 CFR 201.73 - Processors and processing of all classes of certified seed.

Code of Federal Regulations, 2011 CFR

2011-01-01

... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2011-01-01 2011-01-01 false Processors and processing of all classes of certified...

7 CFR 201.73 - Processors and processing of all classes of certified seed.

Code of Federal Regulations, 2013 CFR

2013-01-01

... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2013-01-01 2013-01-01 false Processors and processing of all classes of certified...

7 CFR 201.73 - Processors and processing of all classes of certified seed.

Code of Federal Regulations, 2012 CFR

2012-01-01

... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2012-01-01 2012-01-01 false Processors and processing of all classes of certified...

7 CFR 201.73 - Processors and processing of all classes of certified seed.

Code of Federal Regulations, 2014 CFR

2014-01-01

... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2014-01-01 2014-01-01 false Processors and processing of all classes of certified...